Docs: Update for release FEX-2310

FEXCore: Support CpuState relative vector named constants

.github/workflows/ccpp.yml

@@ -17,11 +17,11 @@ env:
   FEX_ENABLEAVX: 1
 
 jobs:
-  build:
+  build_plus_test:
     runs-on: ${{ matrix.arch }}
     strategy:
       matrix:
-        arch: [[self-hosted, x64], [self-hosted, ARMv8.0], [self-hosted, ARMv8.2], [self-hosted, ARMv8.4]]
+        arch: [[self-hosted, ARMv8.0], [self-hosted, ARMv8.2], [self-hosted, ARMv8.4]]
       fail-fast: false
 
     steps:
@@ -65,7 +65,7 @@ jobs:
       # Note the current convention is to use the -S and -B options here to specify source
       # and build directories, but this is only available with CMake 3.13 and higher.
       # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=True -DBUILD_FEX_LINUX_TESTS=True -DBUILD_THUNKS=True -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_FEX_LINUX_TESTS=True -DBUILD_THUNKS=True -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
 
     - name: Build
       working-directory: ${{runner.workspace}}/build
@@ -78,18 +78,6 @@ jobs:
       shell: bash
       run: cmake --build . --config $BUILD_TYPE --target install
 
-    - name: ASM Tests
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      # Execute the unit tests
-      run: cmake --build . --config $BUILD_TYPE --target asm_tests
-
-    - name: ASM Test Results move
-      if: ${{ always() }}
-      shell: bash
-      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
-
     - name: IR Tests
       working-directory: ${{runner.workspace}}/build
       shell: bash
@@ -102,30 +90,6 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
 
-    - name: Posix Tests
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      # Execute the posixtest
-      run: cmake --build . --config $BUILD_TYPE --target posix_tests
-
-    - name: Posix Test Results move
-      if: ${{ always() }}
-      shell: bash
-      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_Posix.log || true
-
-    - name: gvisor tests
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      # Execute the gvisor tests
-      run: cmake --build . --config $BUILD_TYPE --target gvisor_tests
-
-    - name: GVisor Test Results move
-      if: ${{ always() }}
-      shell: bash
-      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GVisor.log || true
-
     - name: gcc target tests 64
       working-directory: ${{runner.workspace}}/build
       shell: bash
@@ -150,17 +114,6 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC32.log || true
 
-    - name: Struct verifier tests
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      run: cmake --build . --config $BUILD_TYPE --target struct_verifier
-
-    - name: Struct verifier Test Results move
-      if: ${{ always() }}
-      shell: bash
-      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_StructVerifier.log || true
-
     - name: APITest tests
       working-directory: ${{runner.workspace}}/build
       shell: bash
@@ -244,6 +197,53 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ThunkResults.log || true
 
+    - name: ASM Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target asm_tests
+
+    - name: ASM Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
+
+    - name: Posix Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the posixtest
+      run: cmake --build . --config $BUILD_TYPE --target posix_tests
+
+    - name: Posix Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_Posix.log || true
+
+    - name: gvisor tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the gvisor tests
+      run: cmake --build . --config $BUILD_TYPE --target gvisor_tests
+
+    - name: GVisor Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GVisor.log || true
+
+    - name: Struct verifier tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target struct_verifier
+
+    - name: Struct verifier Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_StructVerifier.log || true
+
     - name: Truncate test results
       if: ${{ always() }}
       shell: bash

.github/workflows/glibc_fault.yml

@@ -24,12 +24,11 @@ env:
   FEX_ENABLEAVX: 1
 
 jobs:
-  build:
+  glibc_fault_test:
     runs-on: ${{ matrix.arch }}
     strategy:
       matrix:
-        # Run on an x86 device and any ARM runner.
-        arch: [[self-hosted, x64], [self-hosted, ARM64]]
+        arch: [[self-hosted, ARM64]]
       fail-fast: false
 
     steps:
@@ -73,7 +72,7 @@ jobs:
       # Note the current convention is to use the -S and -B options here to specify source
       # and build directories, but this is only available with CMake 3.13 and higher.
       # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=True -DBUILD_FEX_LINUX_TESTS=True -DENABLE_GLIBC_ALLOCATOR_HOOK_FAULT=True -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_FEX_LINUX_TESTS=True -DENABLE_GLIBC_ALLOCATOR_HOOK_FAULT=True -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
 
     - name: Build
       working-directory: ${{runner.workspace}}/build
@@ -86,18 +85,6 @@ jobs:
       shell: bash
       run: cmake --build . --config $BUILD_TYPE --target install
 
-    - name: ASM Tests
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      # Execute the unit tests
-      run: cmake --build . --config $BUILD_TYPE --target asm_tests
-
-    - name: ASM Test Results move
-      if: ${{ always() }}
-      shell: bash
-      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
-
     - name: IR Tests
       working-directory: ${{runner.workspace}}/build
       shell: bash
@@ -110,18 +97,6 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
 
-    - name: Posix Tests
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      # Execute the posixtest
-      run: cmake --build . --config $BUILD_TYPE --target posix_tests
-
-    - name: Posix Test Results move
-      if: ${{ always() }}
-      shell: bash
-      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_Posix.log || true
-
     - name: gcc target tests 64
       working-directory: ${{runner.workspace}}/build
       shell: bash
@@ -179,6 +154,30 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_FEXLinuxTests.log || true
 
+    - name: ASM Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target asm_tests
+
+    - name: ASM Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
+
+    - name: Posix Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the posixtest
+      run: cmake --build . --config $BUILD_TYPE --target posix_tests
+
+    - name: Posix Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_Posix.log || true
+
     - name: Truncate test results
       if: ${{ always() }}
       shell: bash

.github/workflows/hostrunner.yml

@@ -0,0 +1,107 @@
+name: Hostrunner tests
+
+on:
+  push:
+    branches:
+      - main
+  pull_request:
+    branches:
+      - main
+
+env:
+  # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
+  BUILD_TYPE: Release
+  CC: clang
+  CXX: clang++
+  FEX_ENABLEAVX: 1
+
+jobs:
+  hostrunner_tests:
+    runs-on: ${{ matrix.arch }}
+    strategy:
+      matrix:
+        arch: [[self-hosted, x64]]
+      fail-fast: false
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
+    - name: Set rootfs paths
+      run: |
+        echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+
+    - name: Update RootFS cache
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      run: $GITHUB_WORKSPACE/Scripts/CI_FetchRootFS.py
+
+    - name : submodule checkout
+      # Need to update submodules
+      run: |
+        git submodule sync --recursive
+        git submodule update --init --depth 1
+
+    - name: Clean Build Environment
+      run: rm -Rf ${{runner.workspace}}/build
+
+    - name: Create Build Environment
+      # Some projects don't allow in-source building, so create a separate build directory
+      # We'll use this as our working directory for all subsequent commands
+      run: cmake -E make_directory ${{runner.workspace}}/build
+
+    - name: Configure CMake
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Note the current convention is to use the -S and -B options here to specify source
+      # and build directories, but this is only available with CMake 3.13 and higher.
+      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
+
+    - name: Build
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the build.  You can specify a specific target with "--target <NAME>"
+      run: cmake --build . --config $BUILD_TYPE
+
+    - name: ASM Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target asm_tests
+
+    - name: ASM Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
+
+    - name: Truncate test results
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Cap out the log files at 20M in case something crash spins and dumps fault text
+      # ASM tests get quite close to 10MB
+      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+
+    - name: Set runner name
+      if: ${{ always() }}
+      run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
+
+    - name: Upload results
+      if: ${{ always() }}
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
+      with:
+        name: Results-${{ env.runner_name }}
+        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
+        retention-days: 3
+

.github/workflows/instcountci.yml

@@ -0,0 +1,137 @@
+name: Instruction Count CI run
+
+on:
+  push:
+    branches:
+      - main
+  pull_request:
+    branches:
+      - main
+
+env:
+  # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
+  BUILD_TYPE: Release
+  CC: clang
+  CXX: clang++
+  FEX_ENABLEAVX: 1
+
+jobs:
+  instcountci_tests:
+    runs-on: ${{ matrix.arch }}
+    strategy:
+      matrix:
+        arch: [[self-hosted, x64], [self-hosted, ARM64]]
+      fail-fast: false
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
+    - name: Set rootfs paths
+      run: |
+        echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+
+    - name: Update RootFS cache
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      run: $GITHUB_WORKSPACE/Scripts/CI_FetchRootFS.py
+
+    - name : submodule checkout
+      # Need to update submodules
+      run: |
+        git submodule sync --recursive
+        git submodule update --init --depth 1
+
+    - name: Clean Build Environment
+      run: rm -Rf ${{runner.workspace}}/build
+
+    - name: Create Build Environment
+      # Some projects don't allow in-source building, so create a separate build directory
+      # We'll use this as our working directory for all subsequent commands
+      run: cmake -E make_directory ${{runner.workspace}}/build
+
+    - name: Configure CMake
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Note the current convention is to use the -S and -B options here to specify source
+      # and build directories, but this is only available with CMake 3.13 and higher.
+      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=False -DENABLE_VIXL_DISASSEMBLER=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
+
+    - name: Build
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      env:
+        FEX_DISABLETELEMETRY: 1
+      # Execute the build.  You can specify a specific target with "--target <NAME>"
+      run: cmake --build . --config $BUILD_TYPE --target CodeSizeValidation instcountci_test_files
+
+    - name: Instruction Count Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target instcountci_tests
+
+    - name: Instruction Count Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_InstCountCI.log || true
+
+    - name: Update local repo instcount
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: cmake --build . --config $BUILD_TYPE --target instcountci_update_tests
+
+    - name: Get instcountCI diff
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{github.workspace}}/
+      run: git diff --output=${{runner.workspace}}/build/InstCountCI.diff
+
+    - name: Check if InstCountCI Diff exists
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{github.workspace}}/
+      # Check if the file is empty
+      run: sh -c "! test -s ${{runner.workspace}}/build/InstCountCI.diff"
+
+    - name: Truncate test results
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Cap out the log files at 20M in case something crash spins and dumps fault text
+      # ASM tests get quite close to 10MB
+      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+
+    - name: Set runner name
+      if: ${{ always() }}
+      run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
+
+    - name: Upload results
+      if: ${{ always() }}
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
+      with:
+        name: Results-${{ env.runner_name }}
+        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
+        retention-days: 3
+
+    - name: Upload results InstCountCI
+      if: ${{ always() }}
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
+      with:
+        name: Results-${{ env.runner_name }}-instcountci
+        path: ${{runner.workspace}}/build/InstCountCI.diff
+        retention-days: 3
+

.github/workflows/mingw_build.yml

@@ -13,11 +13,11 @@ env:
   FEX_ENABLEAVX: 1
 
 jobs:
-  build:
+  mingw_build:
     runs-on: ${{ matrix.arch }}
     strategy:
       matrix:
-        arch: [[self-hosted, x64, mingw], [self-hosted, ARM64, mingw]]
+        arch: [[self-hosted, ARM64, mingw]]
       fail-fast: false
 
     steps:
@@ -26,17 +26,18 @@ jobs:
     - name: Set runner label
       run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
 
+    - name: Add MingGW to PATH
+      run: echo "$HOME/llvm-mingw/build/bin/" >> $GITHUB_PATH
+
     - name: Set CC x86
       if: matrix.arch[1] == 'x64'
       run: |
-        echo "CC=$HOME/llvm-mingw/build/bin/x86_64-w64-mingw32-clang" >> $GITHUB_ENV
-        echo "CXX=$HOME/llvm-mingw/build/bin/x86_64-w64-mingw32-clang++" >> $GITHUB_ENV
+        echo "MINGW_TRIPLE=x86_64-w64-mingw32" >> $GITHUB_ENV
 
     - name: Set CC Arm64
       if: matrix.arch[1] == 'ARM64'
       run: |
-        echo "CC=$HOME/llvm-mingw/build/bin/aarch64-w64-mingw32-clang" >> $GITHUB_ENV
-        echo "CXX=$HOME/llvm-mingw/build/bin/aarch64-w64-mingw32-clang++" >> $GITHUB_ENV
+        echo "MINGW_TRIPLE=aarch64-w64-mingw32" >> $GITHUB_ENV
 
     - name: Set rootfs paths
       run: |
@@ -73,7 +74,7 @@ jobs:
       # Note the current convention is to use the -S and -B options here to specify source
       # and build directories, but this is only available with CMake 3.13 and higher.
       # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=False -DBUILD_TESTS=False -DENABLE_JEMALLOC=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/toolchain_mingw.cmake -DMINGW_TRIPLE=$MINGW_TRIPLE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_TESTS=False -DENABLE_JEMALLOC=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
 
     - name: Build
       working-directory: ${{runner.workspace}}/build

.github/workflows/vixl_simulator.yml

@@ -16,7 +16,7 @@ env:
   FEX_ENABLEAVX: 1
 
 jobs:
-  build:
+  vixl_simulator:
     runs-on: ${{ matrix.arch }}
     strategy:
       matrix:
@@ -65,7 +65,7 @@ jobs:
       # Note the current convention is to use the -S and -B options here to specify source
       # and build directories, but this is only available with CMake 3.13 and higher.
       # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=True -DENABLE_VIXL_DISASSEMBLER=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
 
     - name: Build
       working-directory: ${{runner.workspace}}/build
@@ -85,6 +85,21 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
 
+    - name: ASM Tests 128-bit
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      env:
+        FEX_HOSTFEATURES: "disableavx"
+        FEX_FORCESVEWIDTH: "128"
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target asm_tests
+
+    - name: ASM Test 128-bit Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM128bit.log || true
+
     - name: IR Tests
       working-directory: ${{runner.workspace}}/build
       shell: bash

CI/FEXLinuxTestsThunks.json

@@ -0,0 +1,5 @@
+{
+  "ThunksDB": {
+    "fex_thunk_test": 1
+  }
+}

CMakeLists.txt

@@ -25,7 +25,6 @@ option(ENABLE_JEMALLOC_GLIBC_ALLOC "Enables jemalloc glibc allocator" TRUE)
 option(ENABLE_OFFLINE_TELEMETRY "Enables FEX offline telemetry" TRUE)
 option(ENABLE_COMPILE_TIME_TRACE "Enables time trace compile option" FALSE)
 option(ENABLE_LIBCXX "Enables LLVM libc++" FALSE)
-option(ENABLE_INTERPRETER "Enables FEX's Interpreter" FALSE)
 option(ENABLE_CCACHE "Enables ccache for compile caching" TRUE)
 option(ENABLE_TERMUX_BUILD "Forces building for Termux on a non-Termux build machine" FALSE)
 option(ENABLE_VIXL_SIMULATOR "Forces the FEX JIT to use the VIXL simulator" FALSE)
@@ -97,11 +96,6 @@ if (ENABLE_GDB_SYMBOLS)
 endif()
 
 
-if (ENABLE_INTERPRETER)
-  message(STATUS "Interpreter enabled")
-  add_definitions(-DINTERPRETER_ENABLED=1)
-endif()
-
 set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/Bin)
@@ -118,14 +112,6 @@ else()
 endif()
 
 if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
-  option(ENABLE_X86_HOST_DEBUG "Enables compiling on x86_64 host" FALSE)
-  if (NOT ENABLE_X86_HOST_DEBUG)
-    message(FATAL_ERROR
-      " Be warned: FEX isn't optimized for x86_64 hosts!\n"
-      " Support for x86_64 hosts is only for debugging and convenience!\n"
-      " Don't expect amazing performance or optimal code generation!\n"
-      " Pass -DENABLE_X86_HOST_DEBUG=True to bypass this message!")
-  endif()
   set(_M_X86_64 1)
   add_definitions(-D_M_X86_64=1)
   set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
@@ -236,7 +222,7 @@ if (BUILD_TESTS)
 endif()
 
 add_subdirectory(External/vixl/)
-include_directories(External/vixl/src/)
+include_directories(SYSTEM External/vixl/src/)
 
 if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
   # This means we were attempted to get compiled with GCC
@@ -427,7 +413,7 @@ if (BUILD_TESTS)
 endif()
 
 add_subdirectory(FEXHeaderUtils/)
-add_subdirectory(External/FEXCore)
+add_subdirectory(FEXCore/)
 
 # Binfmt_misc files must be installed prior to Source/ installs
 add_subdirectory(Data/binfmts/)
@@ -467,10 +453,10 @@ if (BUILD_THUNKS)
     CMAKE_ARGS
       "-DBITNESS=64"
       "-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}"
+      "-DBUILD_FEX_LINUX_TESTS=${BUILD_FEX_LINUX_TESTS}"
       "-DENABLE_CLANG_THUNKS=${ENABLE_CLANG_THUNKS}"
       "-DCMAKE_TOOLCHAIN_FILE:FILEPATH=${X86_64_TOOLCHAIN_FILE}"
       "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
-      "-DSTRUCT_VERIFIER=${CMAKE_SOURCE_DIR}/Scripts/StructPackVerifier.py"
       "-DFEX_PROJECT_SOURCE_DIR=${FEX_PROJECT_SOURCE_DIR}"
       "-DGENERATOR_EXE=$<TARGET_FILE:thunkgen>"
     INSTALL_COMMAND ""
@@ -485,10 +471,10 @@ if (BUILD_THUNKS)
     CMAKE_ARGS
       "-DBITNESS=32"
       "-DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}"
+      "-DBUILD_FEX_LINUX_TESTS=${BUILD_FEX_LINUX_TESTS}"
       "-DENABLE_CLANG_THUNKS=${ENABLE_CLANG_THUNKS}"
       "-DCMAKE_TOOLCHAIN_FILE:FILEPATH=${X86_32_TOOLCHAIN_FILE}"
       "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
-      "-DSTRUCT_VERIFIER=${CMAKE_SOURCE_DIR}/Scripts/StructPackVerifier.py"
       "-DFEX_PROJECT_SOURCE_DIR=${FEX_PROJECT_SOURCE_DIR}"
       "-DGENERATOR_EXE=$<TARGET_FILE:thunkgen>"
     INSTALL_COMMAND ""

Data/AppConfig/steam.json.in

@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "Env": "STEAM_GAME_LAUNCH_SHELL=@CMAKE_INSTALL_PREFIX@/bin/FEXBash"
-  }
-}

Data/ThunksDB.json

@@ -144,6 +144,12 @@
         "@PREFIX_LIB@/libasound.so.2.0.0"
       ]
     },
+    "fex_thunk_test": {
+      "Library": "libfex_thunk_test-guest.so",
+      "Overlay": [
+        "@PREFIX_LIB@/libfex_thunk_test.so"
+      ]
+    },
     "Xrender": {
       "Library": "libXrender-guest.so",
       "Overlay": [

Data/binfmts/FEX-x86.in

@@ -6,3 +6,4 @@ mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xf
 credentials yes
 fix_binary yes
 preserve yes
+expose_interpreter optional

Data/binfmts/FEX-x86_64.in

@@ -6,3 +6,4 @@ mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xf
 credentials yes
 fix_binary yes
 preserve yes
+expose_interpreter optional

External/FEXCore/Source/Common/JitSymbols.cpp

@@ -1,89 +0,0 @@
-#include <FEXCore/fextl/fmt.h>
-
-#include "Common/JitSymbols.h"
-
-#include <fcntl.h>
-#include <unistd.h>
-
-namespace FEXCore {
-  JITSymbols::JITSymbols() {
-  }
-
-  JITSymbols::~JITSymbols() {
-    if (fd != -1) {
-      close(fd);
-    }
-  }
-
-  void JITSymbols::InitFile() {
-    // We can't use FILE here since we must be robust against forking processes closing our FD from under us.
-#ifdef __ANDROID__
-    // Android simpleperf looks in /data/local/tmp instead of /tmp
-    const auto PerfMap = fextl::fmt::format("/data/local/tmp/perf-{}.map", getpid());
-#else
-    const auto PerfMap = fextl::fmt::format("/tmp/perf-{}.map", getpid());
-#endif
-    fd = open(PerfMap.c_str(), O_CREAT | O_TRUNC | O_WRONLY | O_APPEND, 0644);
-  }
-
-  void JITSymbols::Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
-    if (fd == -1) return;
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fextl::fmt::format("{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
-    auto Result = write(fd, Buffer.c_str(), Buffer.size());
-    if (Result == -1 && errno == EBADF) {
-      fd = -1;
-    }
-  }
-
-  void JITSymbols::Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
-    if (fd == -1) return;
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fextl::fmt::format("{} {:x} {}_{}\n", HostAddr, CodeSize, Name, HostAddr);
-    auto Result = write(fd, Buffer.c_str(), Buffer.size());
-    if (Result == -1 && errno == EBADF) {
-      fd = -1;
-    }
-  }
-
-  void JITSymbols::Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset) {
-    if (fd == -1) return;
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fextl::fmt::format("{} {:x} {}+0x{:x} ({})\n", HostAddr, CodeSize, Name, Offset, HostAddr);
-    auto Result = write(fd, Buffer.c_str(), Buffer.size());
-    if (Result == -1 && errno == EBADF) {
-      fd = -1;
-    }
-  }
-
-  void JITSymbols::RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
-    if (fd == -1) return;
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fextl::fmt::format("{} {:x} {}\n", HostAddr, CodeSize, Name);
-    auto Result = write(fd, Buffer.c_str(), Buffer.size());
-    if (Result == -1 && errno == EBADF) {
-      fd = -1;
-    }
-  }
-
-  void JITSymbols::RegisterJITSpace(const void *HostAddr, uint32_t CodeSize) {
-    if (fd == -1) return;
-
-    // Linux perf format is very straightforward
-    // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fextl::fmt::format("{} {:x} FEXJIT\n", HostAddr, CodeSize);
-    auto Result = write(fd, Buffer.c_str(), Buffer.size());
-    if (Result == -1 && errno == EBADF) {
-      fd = -1;
-    }
-  }
-
-} // namespace FEXCore

External/FEXCore/Source/Common/JitSymbols.h

@@ -1,24 +0,0 @@
-#pragma once
-
-#include <cstdint>
-#include <cstdio>
-#include <memory>
-#include <string_view>
-
-namespace FEXCore {
-class JITSymbols final {
-public:
-  JITSymbols();
-  ~JITSymbols();
-
-  void InitFile();
-  void Register(const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize);
-  void Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name);
-  void Register(const void *HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset);
-  void RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name);
-  void RegisterJITSpace(const void *HostAddr, uint32_t CodeSize);
-
-private:
-  int fd{-1};
-};
-}

External/FEXCore/Source/Interface/Core/CPUBackend.cpp

@@ -1,88 +0,0 @@
-#include "FEXCore/Utils/AllocatorHooks.h"
-#include "Interface/Context/Context.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include <FEXCore/Core/CPUBackend.h>
-
-namespace FEXCore {
-namespace CPU {
-
-CPUBackend::CPUBackend(FEXCore::Core::InternalThreadState *ThreadState, size_t InitialCodeSize, size_t MaxCodeSize)
-    : ThreadState(ThreadState), InitialCodeSize(InitialCodeSize), MaxCodeSize(MaxCodeSize) {}
-
-CPUBackend::~CPUBackend() {
-  for (auto CodeBuffer : CodeBuffers) {
-    FreeCodeBuffer(CodeBuffer);
-  }
-  CodeBuffers.clear();
-}
-
-auto CPUBackend::GetEmptyCodeBuffer() -> CodeBuffer * {
-  if (ThreadState->CurrentFrame->SignalHandlerRefCounter == 0) {
-    if (CodeBuffers.empty()) {
-      auto NewCodeBuffer = AllocateNewCodeBuffer(InitialCodeSize);
-      EmplaceNewCodeBuffer(NewCodeBuffer);
-    } else {
-      if (CodeBuffers.size() > 1) {
-        // If we have more than one code buffer we are tracking then walk them and delete
-        // This is a cleanup step
-        for (size_t i = 1; i < CodeBuffers.size(); i++) {
-          FreeCodeBuffer(CodeBuffers[i]);
-        }
-        CodeBuffers.resize(1);
-      }
-      // Set the current code buffer to the initial
-      CurrentCodeBuffer = &CodeBuffers[0];
-
-      if (CurrentCodeBuffer->Size != MaxCodeSize) {
-        FreeCodeBuffer(*CurrentCodeBuffer);
-
-        // Resize the code buffer and reallocate our code size
-        CurrentCodeBuffer->Size *= 1.5;
-        CurrentCodeBuffer->Size = std::min(CurrentCodeBuffer->Size, MaxCodeSize);
-
-        *CurrentCodeBuffer = AllocateNewCodeBuffer(CurrentCodeBuffer->Size);
-      }
-    }
-  } else {
-    // We have signal handlers that have generated code
-    // This means that we can not safely clear the code at this point in time
-    // Allocate some new code buffers that we can switch over to instead
-    auto NewCodeBuffer = AllocateNewCodeBuffer(InitialCodeSize);
-    EmplaceNewCodeBuffer(NewCodeBuffer);
-  }
-
-  return CurrentCodeBuffer;
-}
-
-auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
-  CodeBuffer Buffer;
-  Buffer.Size = Size;
-  Buffer.Ptr = static_cast<uint8_t *>(
-      FEXCore::Allocator::VirtualAlloc(Buffer.Size, true));
-  LOGMAN_THROW_AA_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer");
-
-  if (static_cast<Context::ContextImpl*>(ThreadState->CTX)->Config.GlobalJITNaming()) {
-    static_cast<Context::ContextImpl*>(ThreadState->CTX)->Symbols.RegisterJITSpace(Buffer.Ptr, Buffer.Size);
-  }
-  return Buffer;
-}
-
-void CPUBackend::FreeCodeBuffer(CodeBuffer Buffer) {
-  FEXCore::Allocator::VirtualFree(Buffer.Ptr, Buffer.Size);
-}
-
-bool CPUBackend::IsAddressInCodeBuffer(uintptr_t Address) const {
-  for (auto &Buffer: CodeBuffers) {
-    auto start = (uintptr_t)Buffer.Ptr;
-    auto end = start + Buffer.Size;
-
-    if (Address >= start && Address < end) {
-      return true;
-    }
-  }
-
-  return false;
-}
-
-}
-}

External/FEXCore/Source/Interface/Core/CPUID.h

@@ -1,306 +0,0 @@
-#pragma once
-
-#include <FEXCore/Core/CPUID.h>
-#include <FEXCore/Config/Config.h>
-#include <FEXCore/fextl/vector.h>
-
-#include <cstdint>
-#include <unordered_map>
-#include <utility>
-
-namespace FEXCore {
-namespace Context {
-  class ContextImpl;
-}
-
-// Debugging define to switch what family of CPU we execute as.
-// Might be useful if an application makes an assumption about a CPU.
-// #define CPUID_AMD
-class CPUIDEmu final {
-private:
-  constexpr static uint32_t CPUID_VENDOR_INTEL1 = 0x756E6547; // "Genu"
-  constexpr static uint32_t CPUID_VENDOR_INTEL2 = 0x49656E69; // "ineI"
-  constexpr static uint32_t CPUID_VENDOR_INTEL3 = 0x6C65746E; // "ntel"
-
-  constexpr static uint32_t CPUID_VENDOR_AMD1 = 0x68747541; // "Auth"
-  constexpr static uint32_t CPUID_VENDOR_AMD2 = 0x69746E65; // "enti"
-  constexpr static uint32_t CPUID_VENDOR_AMD3 = 0x444D4163; // "cAMD"
-
-public:
-  // X86 cacheline size effectively has to be hardcoded to 64
-  // if we report anything differently then applications are likely to break
-  constexpr static uint64_t CACHELINE_SIZE = 64;
-
-  void Init(FEXCore::Context::ContextImpl *ctx);
-
-  FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function, uint32_t Leaf) {
-    if (Function < Primary.size()) {
-      const auto Handler = Primary[Function];
-      return (this->*Handler)(Leaf);
-    }
-
-    constexpr uint32_t HypervisorBase = 0x4000'0000;
-    if (Function >= HypervisorBase && Function < (HypervisorBase + Hypervisor.size())) {
-      const auto Handler = Hypervisor[Function - HypervisorBase];
-      return (this->*Handler)(Leaf);
-    }
-
-    constexpr uint32_t ExtendedBase = 0x8000'0000;
-    if (Function >= ExtendedBase && Function < (ExtendedBase + Extended.size())) {
-      const auto Handler = Extended[Function - ExtendedBase];
-      return (this->*Handler)(Leaf);
-    }
-
-    return Function_Reserved(Leaf);
-  }
-
-  FEXCore::CPUID::FunctionResults RunFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
-    if (Function == 0x8000'0002U)
-      return Function_8000_0002h(Leaf, CPU % PerCPUData.size());
-    else if (Function == 0x8000'0003U)
-      return Function_8000_0003h(Leaf, CPU % PerCPUData.size());
-    else
-      return Function_8000_0004h(Leaf, CPU % PerCPUData.size());
-  }
-
-  FEXCore::CPUID::XCRResults RunXCRFunction(uint32_t Function) {
-    if (Function >= 1) {
-      // XCR function 1 is not yet supported.
-      return {};
-    }
-
-    return XCRFunction_0h();
-  }
-
-private:
-  FEXCore::Context::ContextImpl *CTX;
-  bool Hybrid{};
-  FEX_CONFIG_OPT(Cores, THREADS);
-  FEX_CONFIG_OPT(HideHypervisorBit, HIDEHYPERVISORBIT);
-
-  // XFEATURE_ENABLED_MASK
-  // Mask that configures what features are enabled on the CPU.
-  // Affects XSAVE and XRSTOR when modified.
-  // Bit layout is as follows.
-  // [0]     - x87 enabled
-  // [1]     - SSE enabled
-  // [2]     - YMM enabled (256-bit SSE)
-  // [8:3]   - Reserved. MBZ.
-  // [9]     - MPK
-  // [10]    - Reserved. MBZ.
-  // [11]    - CET_U
-  // [12]    - CET_S
-  // [61:13] - Reserved. MBZ.
-  // [62]    - LWP (Lightweight profiling)
-  // [63]    - Reserved for XCR bit vector expansion. MBZ.
-  // Always enable x87 and SSE by default.
-  constexpr static uint64_t XCR0_X87 = 1ULL << 0;
-  constexpr static uint64_t XCR0_SSE = 1ULL << 1;
-  constexpr static uint64_t XCR0_AVX = 1ULL << 2;
-
-  uint64_t XCR0 {
-    XCR0_X87 |
-    XCR0_SSE
-  };
-
-  uint32_t SupportsAVX() const {
-    return (XCR0 & XCR0_AVX) ? 1 : 0;
-  }
-
-  using FunctionHandler = FEXCore::CPUID::FunctionResults (CPUIDEmu::*)(uint32_t Leaf);
-
-  struct CPUData {
-    const char *ProductName{};
-#ifdef _M_ARM_64
-    uint32_t MIDR{};
-#endif
-    bool IsBig{};
-  };
-  fextl::vector<CPUData> PerCPUData{};
-
-  // Functions
-  FEXCore::CPUID::FunctionResults Function_0h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_01h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_02h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_04h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_06h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_07h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_0Dh(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_15h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_1Ah(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_4000_0000h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_4000_0001h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0000h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0001h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf);
-
-  FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf, uint32_t CPU);
-  FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf, uint32_t CPU);
-  FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf, uint32_t CPU);
-
-  FEXCore::CPUID::FunctionResults Function_8000_0005h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0006h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0007h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0008h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_0019h(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_8000_001Dh(uint32_t Leaf);
-  FEXCore::CPUID::FunctionResults Function_Reserved(uint32_t Leaf);
-
-  FEXCore::CPUID::XCRResults XCRFunction_0h();
-
-  void SetupHostHybridFlag();
-  static constexpr std::array<FunctionHandler, 27> Primary = {
-    // 0: Highest function parameter and ID
-    &CPUIDEmu::Function_0h,
-    // 1: Processor info
-    &CPUIDEmu::Function_01h,
-    // 2: Cache and TLB info
-    &CPUIDEmu::Function_02h,
-    // 3: Serial Number(previously), now reserved
-    &CPUIDEmu::Function_Reserved,
-#ifndef CPUID_AMD
-    // 4: Deterministic cache parameters for each level
-    &CPUIDEmu::Function_04h,
-#else
-    &CPUIDEmu::Function_Reserved,
-#endif
-    // 5: Monitor/mwait
-    &CPUIDEmu::Function_Reserved,
-    // 6: Thermal and power management
-    &CPUIDEmu::Function_06h,
-    // 7: Extended feature flags
-    &CPUIDEmu::Function_07h,
-    // 0x08: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 9: Direct Cache Access information
-    &CPUIDEmu::Function_Reserved,
-    // 0x0A: Architectural performance monitoring
-    &CPUIDEmu::Function_Reserved,
-    // 0x0B: Extended topology enumeration
-    &CPUIDEmu::Function_Reserved,
-    // 0x0C: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x0D: Processor extended state enumeration
-    &CPUIDEmu::Function_0Dh,
-    // 0x0E: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x0F: Intel RDT monitoring
-    &CPUIDEmu::Function_Reserved,
-    // 0x10: Intel RDT allocation enumeration
-    &CPUIDEmu::Function_Reserved,
-    // 0x12: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x12: Intel SGX capability enumeration
-    &CPUIDEmu::Function_Reserved,
-    // 0x13: Reserved
-    &CPUIDEmu::Function_Reserved,
-    // 0x14: Intel Processor trace
-    &CPUIDEmu::Function_Reserved,
-#ifndef CPUID_AMD
-    // Timestamp counter information
-    // Doesn't exist on AMD hardware
-    &CPUIDEmu::Function_15h,
-#else
-    &CPUIDEmu::Function_Reserved,
-#endif
-    // 0x16: Processor frequency information
-    &CPUIDEmu::Function_Reserved,
-    // 0x17: SoC vendor attribute enumeration
-    &CPUIDEmu::Function_Reserved,
-    // 0x18: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x19: Reserved?
-    &CPUIDEmu::Function_Reserved,
-#ifndef CPUID_AMD
-    // 0x1A: Hybrid Information Sub-leaf
-    &CPUIDEmu::Function_1Ah,
-#else
-    &CPUIDEmu::Function_Reserved,
-#endif
-  };
-
-  static constexpr std::array<FunctionHandler, 2> Hypervisor = {
-    // Hypervisor CPUID information leaf
-    &CPUIDEmu::Function_4000_0000h,
-    // FEX-Emu specific leaf
-    &CPUIDEmu::Function_4000_0001h,
-  };
-
-  static constexpr std::array<FunctionHandler, 32> Extended = {
-    // Largest extended function number
-    &CPUIDEmu::Function_8000_0000h,
-    // Processor vendor
-    &CPUIDEmu::Function_8000_0001h,
-    // Processor brand string
-    &CPUIDEmu::Function_8000_0002h,
-    // Processor brand string continued
-    &CPUIDEmu::Function_8000_0003h,
-    // Processor brand string continued
-    &CPUIDEmu::Function_8000_0004h,
-#ifdef CPUID_AMD
-    // 0x8000'0005: L1 Cache and TLB identifiers
-    &CPUIDEmu::Function_8000_0005h,
-#else
-    &CPUIDEmu::Function_Reserved,
-#endif
-    // 0x8000'0006: L2 Cache identifiers
-    &CPUIDEmu::Function_8000_0006h,
-    // 0x8000'0007: Advanced power management information
-    &CPUIDEmu::Function_8000_0007h,
-    // 0x8000'0008: Virtual and physical address sizes
-    &CPUIDEmu::Function_8000_0008h,
-    // 0x8000'0009: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'000A: SVM Revision
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'000B: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'000C: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'000D: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'000E: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'000F: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'0010: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'0011: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'0012: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'0013: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'0014: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'0015: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'0016: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'0017: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'0018: Reserved?
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'0019: TLB 1GB page identifiers
-    &CPUIDEmu::Function_8000_0019h,
-    // 0x8000'001A: Performance optimization identifiers
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'001B: Instruction based sampling identifiers
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'001C: Lightweight profiling capabilities
-    &CPUIDEmu::Function_Reserved,
-#ifdef CPUID_AMD
-    // 0x8000'001D: Cache properties
-    &CPUIDEmu::Function_8000_001Dh,
-#else
-    &CPUIDEmu::Function_Reserved,
-#endif
-    // 0x8000'001E: Extended APIC ID
-    &CPUIDEmu::Function_Reserved,
-    // 0x8000'001F: AMD Secure Encryption
-    &CPUIDEmu::Function_Reserved,
-  };
-};
-}

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.h

@@ -1,66 +0,0 @@
-#pragma once
-
-#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-
-#ifdef VIXL_SIMULATOR
-#include <aarch64/simulator-aarch64.h>
-#endif
-
-namespace FEXCore::Core {
-struct InternalThreadState;
-}
-
-#define STATE_PTR(STATE_TYPE, FIELD) \
-  STATE.R(), offsetof(FEXCore::Core::STATE_TYPE, FIELD)
-
-namespace FEXCore::CPU {
-
-class Arm64Dispatcher final : public Dispatcher, public Arm64Emitter {
-  public:
-    Arm64Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &config);
-    void InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) override;
-    size_t GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) override;
-    size_t GenerateInterpreterTrampoline(uint8_t *CodeBuffer) override;
-
-#ifdef VIXL_SIMULATOR
-  void ExecuteDispatch(FEXCore::Core::CpuStateFrame *Frame) override;
-  void ExecuteJITCallback(FEXCore::Core::CpuStateFrame *Frame, uint64_t RIP) override;
-#endif
-
-  void EmitDispatcher();
-
-  uint16_t GetSRAGPRCount() const override {
-    return StaticRegisters.size();
-  }
-
-  uint16_t GetSRAFPRCount() const override {
-    return StaticFPRegisters.size();
-  }
-
-  void GetSRAGPRMapping(uint8_t Mapping[16]) const override {
-    for (size_t i = 0; i < StaticRegisters.size(); ++i) {
-      Mapping[i] = StaticRegisters[i].Idx();
-    }
-  }
-
-  void GetSRAFPRMapping(uint8_t Mapping[16]) const override {
-    for (size_t i = 0; i < StaticFPRegisters.size(); ++i) {
-      Mapping[i] = StaticFPRegisters[i].Idx();
-    }
-  }
-
-  private:
-    // Long division helpers
-    uint64_t LUDIVHandlerAddress{};
-    uint64_t LDIVHandlerAddress{};
-    uint64_t LUREMHandlerAddress{};
-    uint64_t LREMHandlerAddress{};
-
-#ifdef VIXL_SIMULATOR
-    vixl::aarch64::Decoder Decoder;
-    vixl::aarch64::Simulator Simulator;
-#endif
-};
-
-}

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -1,53 +0,0 @@
-
-#include "Interface/Context/Context.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/Core/X86HelperGen.h"
-
-#include <FEXCore/Config/Config.h>
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/SignalDelegator.h>
-#include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXCore/Utils/Event.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/MathUtils.h>
-
-#include <atomic>
-#include <condition_variable>
-#include <csignal>
-#include <cstring>
-#include <signal.h>
-
-namespace FEXCore::CPU {
-
-void Dispatcher::SleepThread(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::CpuStateFrame *Frame) {
-  auto Thread = Frame->Thread;
-
-  --ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-
-  Thread->RunningEvents.ThreadSleeping = true;
-
-  // Go to sleep
-  Thread->StartRunning.Wait();
-
-  Thread->RunningEvents.Running = true;
-  ++ctx->IdleWaitRefCount;
-  Thread->RunningEvents.ThreadSleeping = false;
-
-  ctx->IdleWaitCV.notify_all();
-}
-
-uint64_t Dispatcher::GetCompileBlockPtr() {
-  using ClassPtrType = void (FEXCore::Context::ContextImpl::*)(FEXCore::Core::CpuStateFrame *, uint64_t);
-  union PtrCast {
-    ClassPtrType ClassPtr;
-    uintptr_t Data;
-  };
-
-  PtrCast CompileBlockPtr;
-  CompileBlockPtr.ClassPtr = &FEXCore::Context::ContextImpl::CompileBlockJit;
-  return CompileBlockPtr.Data;
-}
-
-}

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp

@@ -1,438 +0,0 @@
-#include "FEXCore/Utils/AllocatorHooks.h"
-#include "Interface/Core/LookupCache.h"
-
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/X86HelperGen.h"
-#include "Interface/Context/Context.h"
-
-#include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/CPUBackend.h>
-#include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXCore/Utils/Allocator.h>
-#include <FEXCore/fextl/memory.h>
-#include <FEXCore/fextl/string.h>
-#include <FEXHeaderUtils/Syscalls.h>
-
-#include <cmath>
-#include <memory>
-#include <stddef.h>
-#include <stdint.h>
-
-#define STATE_PTR(STATE_TYPE, FIELD) \
-  [STATE + offsetof(FEXCore::Core::STATE_TYPE, FIELD)]
-
-namespace FEXCore::CPU {
-static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
-#define STATE r14
-
-X86Dispatcher::X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &config)
-  : Dispatcher(ctx, config)
-  , Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE,
-      FEXCore::Allocator::VirtualAlloc(MAX_DISPATCHER_CODE_SIZE, true),
-      nullptr) {
-
-  LOGMAN_THROW_AA_FMT(!config.StaticRegisterAllocation, "X86 dispatcher does not support SRA");
-
-  using namespace Xbyak;
-  using namespace Xbyak::util;
-  DispatchPtr = getCurr<AsmDispatch>();
-
-  // Temp registers
-  // rax, rcx, rdx, rsi, r8, r9,
-  // r10, r11
-  //
-  // Callee Saved
-  // rbx, rbp, r12, r13, r14, r15
-  //
-  // 1St Argument: rdi <ThreadState>
-  // XMM:
-  // All temp
-
-  // while (true) {
-  //    Ptr = FindBlock(RIP)
-  //    if (!Ptr)
-  //      Ptr = CTX->CompileBlock(RIP);
-  //
-  //    if (Ptr)
-  //      Ptr();
-  //    else
-  //    {
-  //      Ptr = FallbackCore->CompileBlock()
-  //      if (Ptr)
-  //        Ptr()
-  //      else {
-  //        ShouldStop = true;
-  //      }
-  //    }
-  // }
-  // Bunch of exit state stuff
-
-  // x86-64 ABI has the stack aligned when /call/ happens
-  // Which means the destination has a misaligned stack at that point
-  push(rbx);
-  push(rbp);
-  push(r12);
-  push(r13);
-  push(r14);
-  push(r15);
-  sub(rsp, 8);
-
-  mov(STATE, rdi);
-
-  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
-  // regardless of where we were in the stack
-  mov(qword STATE_PTR(CpuStateFrame, ReturningStackLocation), rsp);
-
-  Label LoopTop;
-  Label FullLookup;
-  Label NoBlock;
-  Label ExitBlock;
-  Label ThreadPauseHandler;
-
-  L(LoopTop);
-  AbsoluteLoopTopAddressFillSRA = AbsoluteLoopTopAddress = getCurr<uint64_t>();
-
-  {
-    // Load our RIP
-    mov(rdx, qword STATE_PTR(CPUState, rip));
-
-    // L1 Cache
-    mov(r13, qword STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
-    mov(rax, rdx);
-
-    and_(rax, LookupCache::L1_ENTRIES_MASK);
-    shl(rax, 4);
-    cmp(qword[r13 + rax + offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)], rdx);
-    jne(FullLookup);
-
-    jmp(qword[r13 + rax + offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)]);
-
-    L(FullLookup);
-    mov(r13, qword STATE_PTR(CpuStateFrame, Pointers.Common.L2Pointer));
-
-    // Full lookup
-    uint64_t VirtualMemorySize = CTX->Config.VirtualMemSize;
-    mov(rax, rdx);
-    mov(rbx, VirtualMemorySize - 1);
-    and_(rax, rbx);
-    shr(rax, 12);
-
-    // Load page pointer
-    mov(rdi, qword [r13 + rax * 8]);
-
-    cmp(rdi, 0);
-    je(NoBlock);
-
-    mov (rax, rdx);
-    and_(rax, 0x0FFF);
-
-    shl(rax, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
-
-    // check for aliasing
-    mov(rcx, qword [rdi + rax + 8]);
-    cmp(rcx, rdx);
-    jne(NoBlock);
-
-    // Load the block pointer
-    mov(rax, qword [rdi + rax]);
-
-    cmp(rax, 0);
-    je(NoBlock);
-
-    // Update L1
-    mov(r13, qword STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
-    mov(rcx, rdx);
-    and_(rcx, LookupCache::L1_ENTRIES_MASK);
-    shl(rcx, 1);
-    mov(qword[r13 + rcx*8 + 8], rdx);
-    mov(qword[r13 + rcx*8 + 0], rax);
-
-    // Real block if we made it here
-    jmp(rax);
-  }
-
-  {
-    L(ExitBlock);
-    ThreadStopHandlerAddress = getCurr<uint64_t>();
-
-    add(rsp, 8);
-
-    pop(r15);
-    pop(r14);
-    pop(r13);
-    pop(r12);
-    pop(rbp);
-    pop(rbx);
-
-    ret();
-  }
-
-  // Block creation
-  {
-    L(NoBlock);
-
-    inc(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
-
-    // {rdi, rsi, rdx}
-    mov(rdi, reinterpret_cast<uint64_t>(CTX));
-    mov(rsi, STATE);
-    mov(rax, GetCompileBlockPtr());
-
-    call(rax);
-
-    dec(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
-
-    Label AfterStore;
-    // Skip the deferred fault address if the refcount isn't zero
-    jne(AfterStore);
-    mov(rax, qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress)]);
-    mov(rax, qword [rax]);
-
-    L(AfterStore);
-
-    // rdx already contains RIP here
-    jmp(LoopTop);
-  }
-
-  {
-    ExitFunctionLinkerAddress = getCurr<uint64_t>();
-    inc(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
-
-    // {rdi, rsi}
-    mov(rdi, STATE);
-    mov(rsi, rax); // rax is set at the block end
-
-    call(qword STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionLink));
-
-    dec(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
-
-    Label AfterStore;
-    // Skip the deferred fault address if the refcount isn't zero
-    jne(AfterStore);
-    mov(rbx, qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress)]);
-    mov(qword [rbx], rbx);
-
-    L(AfterStore);
-
-    jmp(rax);
-  }
-
-  {
-    // Pause handler
-    ThreadPauseHandlerAddress = getCurr<uint64_t>();
-    L(ThreadPauseHandler);
-
-    mov(rdi, reinterpret_cast<uintptr_t>(CTX));
-    mov(rsi, STATE);
-    mov(rax, reinterpret_cast<uint64_t>(SleepThread));
-
-    call(rax);
-
-    // XXX: Unsupported atm
-    PauseReturnInstruction = getCurr<uint64_t>();
-    ud2();
-  }
-
-  {
-    CallbackPtr = getCurr<JITCallback>();
-
-    push(rbx);
-    push(rbp);
-    push(r12);
-    push(r13);
-    push(r14);
-    push(r15);
-    sub(rsp, 8);
-
-    // First thing we need to move the thread state pointer back in to our register
-    mov(STATE, rdi);
-    // XXX: XMM?
-
-    // Make sure to adjust the refcounter so we don't clear the cache now
-    add(qword STATE_PTR(CpuStateFrame, SignalHandlerRefCounter), 1);
-
-    // Now push the callback return trampoline to the guest stack
-    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
-    mov(rax, CTX->X86CodeGen.CallbackReturn);
-
-    // Store the trampoline to the guest stack
-    // Guest stack is now correctly misaligned after a regular call instruction
-    sub(qword STATE_PTR(CpuStateFrame, State.gregs[X86State::REG_RSP]), 16);
-    mov(rbx, qword STATE_PTR(CpuStateFrame, State.gregs[X86State::REG_RSP]));
-    mov(qword [rbx], rax);
-
-    // Store RIP to the context state
-    mov(qword STATE_PTR(CpuStateFrame, State.rip), rsi);
-
-    // Back to the loop top now
-    jmp(LoopTop);
-  }
-
-  {
-    // Signal return handler
-    SignalHandlerReturnAddress = getCurr<uint64_t>();
-    ud2();
-  }
-
-  {
-    // RT Signal return handler
-    SignalHandlerReturnAddressRT = getCurr<uint64_t>();
-    ud2();
-  }
-
-  {
-    // Guest SIGILL handler
-    // Needs to be distinct from the SignalHandlerReturnAddress
-    GuestSignal_SIGILL = getCurr<uint64_t>();
-    ud2();
-  }
-
-  {
-    // Guest SIGTRAP handler
-    // Needs to be distinct from the SignalHandlerReturnAddress
-    GuestSignal_SIGTRAP = getCurr<uint64_t>();
-
-    // ud2 = SIGILL
-    // int3 = SIGTRAP
-    // hlt = SIGSEGV
-    int3();
-  }
-
-  {
-    // Guest SIGSEGV handler
-    // Needs to be distinct from the SignalHandlerReturnAddress
-    GuestSignal_SIGSEGV = getCurr<uint64_t>();
-
-    // ud2 = SIGILL
-    // int3 = SIGTRAP
-    // hlt = SIGSEGV
-    hlt();
-  }
-
-  {
-    IntCallbackReturnAddress = getCurr<uint64_t>();
-//  using CallbackReturn =  FEX_NAKED void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
-
-    // rdi = thread
-    // rsi = rsp
-
-    mov(rsp, rsi);
-
-    // Now jump back to the thunk
-    // XXX: XMM?
-    add(rsp, 8);
-
-    pop(r15);
-    pop(r14);
-    pop(r13);
-    pop(r12);
-    pop(rbp);
-    pop(rbx);
-
-    ret();
-  }
-  ready();
-
-  Start = reinterpret_cast<uint64_t>(getCode());
-  End = Start + getSize();
-
-  if (CTX->Config.BlockJITNaming()) {
-    fextl::string Name = fextl::fmt::format("Dispatch_{}", FHU::Syscalls::gettid());
-    CTX->Symbols.Register(reinterpret_cast<void*>(Start), End-Start, Name);
-  }
-  if (CTX->Config.GlobalJITNaming()) {
-    CTX->Symbols.RegisterJITSpace(reinterpret_cast<void*>(Start), End-Start);
-  }
-
-}
-
-size_t X86Dispatcher::GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) {
-  using namespace Xbyak;
-  using namespace Xbyak::util;
-
-  Xbyak::CodeGenerator emit(1, &emit); // actual emit target set with setNewBuffer
-  emit.setNewBuffer(CodeBuffer, MaxGDBPauseCheckSize);
-
-  Label RunBlock;
-
-  // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
-  // This happens when single stepping
-  static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
-  emit.mov(rax, reinterpret_cast<uint64_t>(CTX));
-
-  // If the value == 0 then we don't need to stop
-  emit.cmp(dword [rax + (offsetof(FEXCore::Context::ContextImpl, Config.RunningMode))], 0);
-  emit.je(RunBlock);
-  {
-    // Make sure RIP is syncronized to the context
-    emit.mov(rax, GuestRIP);
-    emit.mov(qword STATE_PTR(CpuStateFrame, State.rip), rax);
-
-    // Stop the thread
-    emit.mov(rax, qword STATE_PTR(CpuStateFrame, Pointers.Common.ThreadPauseHandlerSpillSRA));
-    emit.jmp(rax);
-  }
-
-  emit.L(RunBlock);
-
-  emit.ready();
-
-  return emit.getSize();
-}
-
-
-size_t X86Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) {
-  using namespace Xbyak;
-  using namespace Xbyak::util;
-
-  Xbyak::CodeGenerator emit(1, &emit); // actual emit target set with setNewBuffer
-  emit.setNewBuffer(CodeBuffer, MaxInterpreterTrampolineSize);
-
-  Label InlineIRData;
-
-  emit.mov(rdi, STATE);
-  emit.lea(rsi, ptr[rip + InlineIRData]);
-  emit.call(qword STATE_PTR(CpuStateFrame, Pointers.Interpreter.FragmentExecuter));
-
-  emit.jmp(qword STATE_PTR(CpuStateFrame, Pointers.Common.DispatcherLoopTop));
-
-  emit.L(InlineIRData);
-
-  emit.ready();
-
-  return emit.getSize();
-}
-
-X86Dispatcher::~X86Dispatcher() {
-  FEXCore::Allocator::VirtualFree(top_, MAX_DISPATCHER_CODE_SIZE);
-}
-
-void X86Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) {
-  // Setup dispatcher specific pointers that need to be accessed from JIT code
-  {
-    auto &Common = Thread->CurrentFrame->Pointers.Common;
-
-    Common.DispatcherLoopTop = AbsoluteLoopTopAddress;
-    Common.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA;
-    Common.ExitFunctionLinker = ExitFunctionLinkerAddress;
-    Common.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddress;
-    Common.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddress;
-    Common.GuestSignal_SIGILL = GuestSignal_SIGILL;
-    Common.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP;
-    Common.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV;
-    Common.SignalReturnHandler = SignalHandlerReturnAddress;
-    Common.SignalReturnHandlerRT = SignalHandlerReturnAddressRT;
-
-    auto &Interpreter = Thread->CurrentFrame->Pointers.Interpreter;
-    (uintptr_t&)Interpreter.CallbackReturn = IntCallbackReturnAddress;
-  }
-}
-
-fextl::unique_ptr<Dispatcher> Dispatcher::CreateX86(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config) {
-  return fextl::make_unique<X86Dispatcher>(CTX, Config);
-}
-
-}

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.h

@@ -1,39 +0,0 @@
-#pragma once
-
-#include <FEXCore/fextl/list.h>
-#include <FEXCore/fextl/unordered_map.h>
-#include <FEXCore/fextl/unordered_set.h>
-
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-
-#define XBYAK64
-#define XBYAK_CUSTOM_ALLOC
-#define XBYAK_CUSTOM_MALLOC FEXCore::Allocator::malloc
-#define XBYAK_CUSTOM_FREE FEXCore::Allocator::free
-#define XBYAK_CUSTOM_SETS
-#define XBYAK_STD_UNORDERED_SET fextl::unordered_set
-#define XBYAK_STD_UNORDERED_MAP fextl::unordered_map
-#define XBYAK_STD_UNORDERED_MULTIMAP fextl::unordered_multimap
-#define XBYAK_STD_LIST fextl::list
-#define XBYAK_NO_EXCEPTION
-
-#include <xbyak/xbyak.h>
-#include <xbyak/xbyak_util.h>
-
-namespace FEXCore::Core {
-  struct InternalThreadState;
-}
-
-namespace FEXCore::CPU {
-
-class X86Dispatcher final : public Dispatcher, public Xbyak::CodeGenerator {
-  public:
-    X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &config);
-    void InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) override;
-    size_t GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) override;
-    size_t GenerateInterpreterTrampoline(uint8_t *CodeBuffer) override;
-
-    virtual ~X86Dispatcher() override;
-};
-
-}

External/FEXCore/Source/Interface/Core/HostFeatures.cpp

@@ -1,177 +0,0 @@
-#include "Interface/Core/CPUID.h"
-#include <FEXCore/Core/HostFeatures.h>
-
-#if defined(_M_ARM_64) || defined(VIXL_SIMULATOR)
-#include "aarch64/assembler-aarch64.h"
-#include "aarch64/cpu-aarch64.h"
-#include "aarch64/disasm-aarch64.h"
-#include "aarch64/assembler-aarch64.h"
-#endif
-
-#ifdef _M_X86_64
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-#endif
-
-namespace FEXCore {
-
-// Data Zero Prohibited flag
-// 0b0 = ZVA/GVA/GZVA permitted
-// 0b1 = ZVA/GVA/GZVA prohibited
-[[maybe_unused]] constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
-// Log2 of the blocksize in 32-bit words
-[[maybe_unused]] constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
-
-#ifdef _M_ARM_64
-[[maybe_unused]] static uint32_t GetDCZID() {
-  uint64_t Result{};
-  __asm("mrs %[Res], DCZID_EL0"
-      : [Res] "=r" (Result));
-  return Result;
-}
-
-static uint32_t GetFPCR() {
-  uint64_t Result{};
-  __asm ("mrs %[Res], FPCR"
-    : [Res] "=r" (Result));
-  return Result;
-}
-
-static void SetFPCR(uint64_t Value) {
-  __asm ("msr FPCR, %[Value]"
-    :: [Value] "r" (Value));
-}
-
-#else
-static uint32_t GetDCZID() {
-  // Return unsupported
-  return DCZID_DZP_MASK;
-}
-#endif
-
-
-HostFeatures::HostFeatures() {
-#if defined(_M_ARM_64) || defined(VIXL_SIMULATOR)
-#ifdef VIXL_SIMULATOR
-  auto Features = vixl::CPUFeatures::All();
-#else
-#ifndef _WIN32
-  auto Features = vixl::CPUFeatures::InferFromOS();
-#else
-  // Need to use ID registers in WINE.
-  auto Features = vixl::CPUFeatures::InferFromIDRegisters();
-#endif
-#endif
-  SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
-  SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
-  SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
-  SupportsRAND = Features.Has(vixl::CPUFeatures::Feature::kRNG);
-
-  // Only supported when FEAT_AFP is supported
-  SupportsFlushInputsToZero = Features.Has(vixl::CPUFeatures::Feature::kAFP);
-  SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
-  SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
-  SupportsPMULL_128Bit = Features.Has(vixl::CPUFeatures::Feature::kPmull1Q);
-  SupportsCSSC = Features.Has(vixl::CPUFeatures::Feature::kCSSC);
-
-  Supports3DNow = true;
-  SupportsSSE4A = true;
-#ifdef VIXL_SIMULATOR
-  // Hardcode enable SVE with 256-bit wide registers.
-  SupportsAVX = true;
-#else
-  SupportsAVX = Features.Has(vixl::CPUFeatures::Feature::kSVE2) &&
-                vixl::aarch64::CPU::ReadSVEVectorLengthInBits() >= 256;
-#endif
-  SupportsSHA = true;
-  SupportsBMI1 = true;
-  SupportsBMI2 = true;
-  SupportsCLWB = true;
-
-  if (!SupportsAtomics) {
-    WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
-  }
-
-#ifdef _M_ARM_64
-  // We need to get the CPU's cache line size
-  // We expect sane targets that have correct cacheline sizes across clusters
-  uint64_t CTR;
-  __asm volatile ("mrs %[ctr], ctr_el0"
-    : [ctr] "=r"(CTR));
-
-  DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
-  ICacheLineSize = 4 << (CTR & 0xF);
-
-  // Test if this CPU supports float exception trapping by attempting to enable
-  // On unsupported these bits are architecturally defined as RAZ/WI
-  constexpr uint32_t ExceptionEnableTraps =
-    (1U << 8) |  // Invalid Operation float exception trap enable
-    (1U << 9) |  // Divide by zero float exception trap enable
-    (1U << 10) | // Overflow float exception trap enable
-    (1U << 11) | // Underflow float exception trap enable
-    (1U << 12) | // Inexact float exception trap enable
-    (1U << 15);  // Input Denormal float exception trap enable
-
-  uint32_t OriginalFPCR = GetFPCR();
-  uint32_t FPCR = OriginalFPCR | ExceptionEnableTraps;
-  SetFPCR(FPCR);
-  FPCR = GetFPCR();
-  SupportsFloatExceptions = (FPCR & ExceptionEnableTraps) == ExceptionEnableTraps;
-
-  // Set FPCR back to original just in case anything changed
-  SetFPCR(OriginalFPCR);
-#endif
-
-#endif
-#if defined(_M_X86_64) && !defined(VIXL_SIMULATOR)
-  Xbyak::util::Cpu Features{};
-  SupportsAES = Features.has(Xbyak::util::Cpu::tAESNI);
-  SupportsCRC = Features.has(Xbyak::util::Cpu::tSSE42);
-  SupportsRAND = Features.has(Xbyak::util::Cpu::tRDRAND) && Features.has(Xbyak::util::Cpu::tRDSEED);
-  SupportsRCPC = true;
-  SupportsTSOImm9 = true;
-  Supports3DNow = Features.has(Xbyak::util::Cpu::t3DN) && Features.has(Xbyak::util::Cpu::tE3DN);
-  SupportsSSE4A = Features.has(Xbyak::util::Cpu::tSSE4a);
-  SupportsAVX = true;
-  SupportsSHA = Features.has(Xbyak::util::Cpu::tSHA);
-  SupportsBMI1 = Features.has(Xbyak::util::Cpu::tBMI1);
-  SupportsBMI2 = Features.has(Xbyak::util::Cpu::tBMI2);
-  SupportsBMI2 = Features.has(Xbyak::util::Cpu::tCLWB);
-  SupportsPMULL_128Bit = Features.has(Xbyak::util::Cpu::tPCLMULQDQ);
-
-  // xbyak doesn't know how to check for CLZero
-  // First ensure we support a new enough extended CPUID function range
-
-  uint32_t data[4];
-  Xbyak::util::Cpu::getCpuid(0x8000'0000, data);
-  if (data[0] >= 0x8000'0008U) {
-    // CLZero defined in 8000_00008_EBX[bit 0]
-    Xbyak::util::Cpu::getCpuid(0x8000'0008, data);
-    SupportsCLZERO = data[1] & 1;
-  }
-
-  SupportsFlushInputsToZero = true;
-  SupportsFloatExceptions = true;
-#endif
-
-#ifdef VIXL_SIMULATOR
-  // simulator doesn't support dc(ZVA)
-  SupportsCLZERO = false;
-#else
-  // Check if we can support cacheline clears
-  uint32_t DCZID = GetDCZID();
-  if ((DCZID & DCZID_DZP_MASK) == 0) {
-    uint32_t DCZID_Log2 = DCZID & DCZID_BS_MASK;
-    uint32_t DCZID_Bytes = (1 << DCZID_Log2) * sizeof(uint32_t);
-    // If the DC ZVA size matches the emulated cache line size
-    // This means we can use the instruction
-    SupportsCLZERO = DCZID_Bytes == CPUIDEmu::CACHELINE_SIZE;
-  }
-#endif
-
-  // Disable AVX if the configuration explicitly has disabled it.
-  FEX_CONFIG_OPT(EnableAVX, ENABLEAVX);
-  if (!EnableAVX) {
-    SupportsAVX = false;
-  }
-}
-}

External/FEXCore/Source/Interface/Core/Interpreter/AtomicOps.cpp

@@ -1,777 +0,0 @@
-/*
-$info$
-tags: backend|interpreter
-$end_info$
-*/
-
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/InterpreterDefines.h"
-
-#include <FEXCore/Utils/BitUtils.h>
-
-#include <cstdint>
-
-namespace FEXCore::CPU {
-
-#ifdef _M_X86_64
-uint8_t AtomicFetchNeg(uint8_t *Addr) {
-  using Type = uint8_t;
-  std::atomic<Type> *MemData = reinterpret_cast<std::atomic<Type>*>(Addr);
-  Type Expected = MemData->load();
-  Type Desired = -Expected;
-  do {
-    Desired = -Expected;
-  } while (!MemData->compare_exchange_strong(Expected, Desired, std::memory_order_seq_cst));
-
-  return Expected;
-}
-
-uint16_t AtomicFetchNeg(uint16_t *Addr) {
-  using Type = uint16_t;
-  std::atomic<Type> *MemData = reinterpret_cast<std::atomic<Type>*>(Addr);
-  Type Expected = MemData->load();
-  Type Desired = -Expected;
-  do {
-    Desired = -Expected;
-  } while (!MemData->compare_exchange_strong(Expected, Desired, std::memory_order_seq_cst));
-
-  return Expected;
-}
-
-uint32_t AtomicFetchNeg(uint32_t *Addr) {
-  using Type = uint32_t;
-  std::atomic<Type> *MemData = reinterpret_cast<std::atomic<Type>*>(Addr);
-  Type Expected = MemData->load();
-  Type Desired = -Expected;
-  do {
-    Desired = -Expected;
-  } while (!MemData->compare_exchange_strong(Expected, Desired, std::memory_order_seq_cst));
-
-  return Expected;
-}
-
-uint64_t AtomicFetchNeg(uint64_t *Addr) {
-  using Type = uint64_t;
-  std::atomic<Type> *MemData = reinterpret_cast<std::atomic<Type>*>(Addr);
-  Type Expected = MemData->load();
-  Type Desired = -Expected;
-  do {
-    Desired = -Expected;
-  } while (!MemData->compare_exchange_strong(Expected, Desired, std::memory_order_seq_cst));
-
-  return Expected;
-}
-
-template<typename T>
-T AtomicCompareAndSwap(T expected, T desired, T *addr)
-{
-  std::atomic<T> *MemData = reinterpret_cast<std::atomic<T>*>(addr);
-
-  T Src1 = expected;
-  T Src2 = desired;
-
-  T Expected = Src1;
-  bool Result = MemData->compare_exchange_strong(Expected, Src2);
-
-  return Result ? Src1 : Expected;
-}
-
-template uint8_t AtomicCompareAndSwap<uint8_t>(uint8_t expected, uint8_t desired, uint8_t *addr);
-template uint16_t AtomicCompareAndSwap<uint16_t>(uint16_t expected, uint16_t desired, uint16_t *addr);
-template uint32_t AtomicCompareAndSwap<uint32_t>(uint32_t expected, uint32_t desired, uint32_t *addr);
-template uint64_t AtomicCompareAndSwap<uint64_t>(uint64_t expected, uint64_t desired, uint64_t *addr);
-
-#else
-// Needs to match what the AArch64 JIT and unaligned signal handler expects
-uint8_t AtomicFetchNeg(uint8_t *Addr) {
-  using Type = uint8_t;
-  Type Result{};
-  Type Tmp{};
-  Type TmpStatus{};
-
-  __asm__ volatile(
-  R"(
-  1:
-    ldaxrb %w[Result], [%[Memory]];
-    neg %w[Tmp], %w[Result];
-    stlxrb %w[TmpStatus], %w[Tmp], [%[Memory]];
-    cbnz %w[TmpStatus], 1b;
-  )"
-  : [Result] "=r" (Result)
-  , [Tmp] "=r" (Tmp)
-  , [TmpStatus] "=r" (TmpStatus)
-  , [Memory] "+r" (Addr)
-  :: "memory"
-  );
-  return Result;
-}
-
-uint16_t AtomicFetchNeg(uint16_t *Addr) {
-  using Type = uint16_t;
-  Type Result{};
-  Type Tmp{};
-  Type TmpStatus{};
-
-  __asm__ volatile(
-  R"(
-  1:
-    ldaxrh %w[Result], [%[Memory]];
-    neg %w[Tmp], %w[Result];
-    stlxrh %w[TmpStatus], %w[Tmp], [%[Memory]];
-    cbnz %w[TmpStatus], 1b;
-  )"
-  : [Result] "=r" (Result)
-  , [Tmp] "=r" (Tmp)
-  , [TmpStatus] "=r" (TmpStatus)
-  , [Memory] "+r" (Addr)
-  :: "memory"
-  );
-  return Result;
-}
-
-uint32_t AtomicFetchNeg(uint32_t *Addr) {
-  using Type = uint32_t;
-  Type Result{};
-  Type Tmp{};
-  Type TmpStatus{};
-
-  __asm__ volatile(
-  R"(
-  1:
-    ldaxr %w[Result], [%[Memory]];
-    neg %w[Tmp], %w[Result];
-    stlxr %w[TmpStatus], %w[Tmp], [%[Memory]];
-    cbnz %w[TmpStatus], 1b;
-  )"
-  : [Result] "=r" (Result)
-  , [Tmp] "=r" (Tmp)
-  , [TmpStatus] "=r" (TmpStatus)
-  , [Memory] "+r" (Addr)
-  :: "memory"
-  );
-  return Result;
-}
-
-uint64_t AtomicFetchNeg(uint64_t *Addr) {
-  using Type = uint64_t;
-  Type Result{};
-  Type Tmp{};
-  Type TmpStatus{};
-
-  __asm__ volatile(
-  R"(
-  1:
-    ldaxr %[Result], [%[Memory]];
-    neg %[Tmp], %[Result];
-    stlxr %w[TmpStatus], %[Tmp], [%[Memory]];
-    cbnz %w[TmpStatus], 1b;
-  )"
-  : [Result] "=r" (Result)
-  , [Tmp] "=r" (Tmp)
-  , [TmpStatus] "=r" (TmpStatus)
-  , [Memory] "+r" (Addr)
-  :: "memory"
-  );
-  return Result;
-}
-
-template<>
-uint8_t AtomicCompareAndSwap(uint8_t expected, uint8_t desired, uint8_t *addr) {
-  using Type = uint8_t;
-  //force Result to r9 (scratch register) or clang spills to stack
-  register Type Result asm("r9"){};
-  Type Tmp{};
-  Type Tmp2{};
-  __asm__ volatile(
-  R"(
-  1:
-    ldaxrb %w[Tmp], [%[Memory]];
-    cmp %w[Tmp], %w[Expected], uxtb;
-    b.ne 2f;
-    stlxrb %w[Tmp2], %w[Desired], [%[Memory]];
-    cbnz %w[Tmp2], 1b;
-    mov %w[Result], %w[Expected];
-    b 3f;
-  2:
-    mov %w[Result], %w[Tmp];
-    clrex;
-  3:
-  )"
-  : [Tmp] "=r" (Tmp)
-  , [Tmp2] "=r" (Tmp2)
-  , [Desired] "+r" (desired)
-  , [Expected] "+r" (expected)
-  , [Result] "=r" (Result)
-  , [Memory] "+r" (addr)
-  :: "memory"
-  );
-  return Result;
-}
-
-template<>
-uint16_t AtomicCompareAndSwap(uint16_t expected, uint16_t desired, uint16_t *addr) {
-  using Type = uint16_t;
-  //force Result to r9 (scratch register) or clang spills to stack
-  register Type Result asm("r9"){};
-  Type Tmp{};
-  Type Tmp2{};
-  __asm__ volatile(
-  R"(
-  1:
-    ldaxrh %w[Tmp], [%[Memory]];
-    cmp %w[Tmp], %w[Expected], uxth;
-    b.ne 2f;
-    stlxrh %w[Tmp2], %w[Desired], [%[Memory]];
-    cbnz %w[Tmp2], 1b;
-    mov %w[Result], %w[Expected];
-    b 3f;
-  2:
-    mov %w[Result], %w[Tmp];
-    clrex;
-  3:
-  )"
-  : [Tmp] "=r" (Tmp)
-  , [Tmp2] "=r" (Tmp2)
-  , [Desired] "+r" (desired)
-  , [Expected] "+r" (expected)
-  , [Result] "=r" (Result)
-  , [Memory] "+r" (addr)
-  :: "memory"
-  );
-  return Result;
-}
-
-template<>
-uint32_t AtomicCompareAndSwap(uint32_t expected, uint32_t desired, uint32_t *addr) {
-  using Type = uint32_t;
-  //force Result to r9 (scratch register) or clang spills to stack
-  register Type Result asm("r9"){};
-  Type Tmp{};
-  Type Tmp2{};
-  __asm__ volatile(
-  R"(
-  1:
-    ldaxr %w[Tmp], [%[Memory]];
-    cmp %w[Tmp], %w[Expected];
-    b.ne 2f;
-    stlxr %w[Tmp2], %w[Desired], [%[Memory]];
-    cbnz %w[Tmp2], 1b;
-    mov %w[Result], %w[Expected];
-    b 3f;
-  2:
-    mov %w[Result], %w[Tmp];
-    clrex;
-  3:
-  )"
-  : [Tmp] "=r" (Tmp)
-  , [Tmp2] "=r" (Tmp2)
-  , [Desired] "+r" (desired)
-  , [Expected] "+r" (expected)
-  , [Result] "=r" (Result)
-  , [Memory] "+r" (addr)
-  :: "memory"
-  );
-  return Result;
-}
-
-template<>
-uint64_t AtomicCompareAndSwap(uint64_t expected, uint64_t desired, uint64_t *addr) {
-  using Type = uint64_t;
-  //force Result to r9 (scratch register) or clang spills to stack
-  register Type Result asm("r9"){};
-  Type Tmp{};
-  Type Tmp2{};
-  __asm__ volatile(
-  R"(
-  1:
-    ldaxr %[Tmp], [%[Memory]];
-    cmp %[Tmp], %[Expected];
-    b.ne 2f;
-    stlxr %w[Tmp2], %[Desired], [%[Memory]];
-    cbnz %w[Tmp2], 1b;
-    mov %[Result], %[Expected];
-    b 3f;
-  2:
-    mov %[Result], %[Tmp];
-    clrex;
-  3:
-  )"
-  : [Tmp] "=r" (Tmp)
-  , [Tmp2] "=r" (Tmp2)
-  , [Desired] "+r" (desired)
-  , [Expected] "+r" (expected)
-  , [Result] "=r" (Result)
-  , [Memory] "+r" (addr)
-  :: "memory"
-  );
-  return Result;
-}
-
-#endif
-
-#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-DEF_OP(CASPair) {
-  auto Op = IROp->C<IR::IROp_CASPair>();
-
-  // Size is the size of each pair element
-  switch (IROp->ElementSize) {
-    case 4: {
-      GD = AtomicCompareAndSwap(
-        *GetSrc<uint64_t*>(Data->SSAData, Op->Expected),
-        *GetSrc<uint64_t*>(Data->SSAData, Op->Desired),
-        *GetSrc<uint64_t**>(Data->SSAData, Op->Addr)
-      );
-      break;
-    }
-    case 8: {
-      std::atomic<__uint128_t> *MemData = *GetSrc<std::atomic<__uint128_t> **>(Data->SSAData, Op->Addr);
-
-      __uint128_t Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Expected);
-      __uint128_t Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Desired);
-
-      __uint128_t Expected = Src1;
-      bool Result = MemData->compare_exchange_strong(Expected, Src2);
-      memcpy(GDP, Result ? &Src1 : &Expected, 16);
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown CAS size: {}", IROp->ElementSize); break;
-  }
-}
-
-DEF_OP(CAS) {
-  auto Op = IROp->C<IR::IROp_CAS>();
-  uint8_t OpSize = IROp->Size;
-
-  switch (OpSize) {
-    case 1: {
-      GD = AtomicCompareAndSwap(
-        *GetSrc<uint8_t*>(Data->SSAData, Op->Expected),
-        *GetSrc<uint8_t*>(Data->SSAData, Op->Desired),
-        *GetSrc<uint8_t**>(Data->SSAData, Op->Addr)
-      );
-      break;
-    }
-    case 2: {
-      GD = AtomicCompareAndSwap(
-        *GetSrc<uint16_t*>(Data->SSAData, Op->Expected),
-        *GetSrc<uint16_t*>(Data->SSAData, Op->Desired),
-        *GetSrc<uint16_t**>(Data->SSAData, Op->Addr)
-      );
-      break;
-    }
-    case 4: {
-      GD = AtomicCompareAndSwap(
-        *GetSrc<uint32_t*>(Data->SSAData, Op->Expected),
-        *GetSrc<uint32_t*>(Data->SSAData, Op->Desired),
-        *GetSrc<uint32_t**>(Data->SSAData, Op->Addr)
-      );
-      break;
-    }
-    case 8: {
-      GD = AtomicCompareAndSwap(
-        *GetSrc<uint64_t*>(Data->SSAData, Op->Expected),
-        *GetSrc<uint64_t*>(Data->SSAData, Op->Desired),
-        *GetSrc<uint64_t**>(Data->SSAData, Op->Addr)
-      );
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown CAS size: {}", OpSize); break;
-  }
-}
-
-DEF_OP(AtomicAdd) {
-  auto Op = IROp->C<IR::IROp_AtomicAdd>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      *MemData += Src;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      *MemData += Src;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      *MemData += Src;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      *MemData += Src;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicSub) {
-  auto Op = IROp->C<IR::IROp_AtomicSub>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      *MemData -= Src;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      *MemData -= Src;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      *MemData -= Src;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      *MemData -= Src;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicAnd) {
-  auto Op = IROp->C<IR::IROp_AtomicAnd>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      *MemData &= Src;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      *MemData &= Src;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      *MemData &= Src;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      *MemData &= Src;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicOr) {
-  auto Op = IROp->C<IR::IROp_AtomicOr>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      *MemData |= Src;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      *MemData |= Src;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      *MemData |= Src;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      *MemData |= Src;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicXor) {
-  auto Op = IROp->C<IR::IROp_AtomicXor>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      *MemData ^= Src;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      *MemData ^= Src;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      *MemData ^= Src;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      *MemData ^= Src;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicSwap) {
-  auto Op = IROp->C<IR::IROp_AtomicSwap>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      uint8_t Previous = MemData->exchange(Src);
-      GD = Previous;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      uint16_t Previous = MemData->exchange(Src);
-      GD = Previous;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      uint32_t Previous = MemData->exchange(Src);
-      GD = Previous;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      uint64_t Previous = MemData->exchange(Src);
-      GD = Previous;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchAdd) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      uint8_t Previous = MemData->fetch_add(Src);
-      GD = Previous;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      uint16_t Previous = MemData->fetch_add(Src);
-      GD = Previous;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      uint32_t Previous = MemData->fetch_add(Src);
-      GD = Previous;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      uint64_t Previous = MemData->fetch_add(Src);
-      GD = Previous;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchSub) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchSub>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      uint8_t Previous = MemData->fetch_sub(Src);
-      GD = Previous;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      uint16_t Previous = MemData->fetch_sub(Src);
-      GD = Previous;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      uint32_t Previous = MemData->fetch_sub(Src);
-      GD = Previous;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      uint64_t Previous = MemData->fetch_sub(Src);
-      GD = Previous;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchAnd) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchAnd>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      uint8_t Previous = MemData->fetch_and(Src);
-      GD = Previous;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      uint16_t Previous = MemData->fetch_and(Src);
-      GD = Previous;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      uint32_t Previous = MemData->fetch_and(Src);
-      GD = Previous;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      uint64_t Previous = MemData->fetch_and(Src);
-      GD = Previous;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchOr) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchOr>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      uint8_t Previous = MemData->fetch_or(Src);
-      GD = Previous;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      uint16_t Previous = MemData->fetch_or(Src);
-      GD = Previous;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      uint32_t Previous = MemData->fetch_or(Src);
-      GD = Previous;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      uint64_t Previous = MemData->fetch_or(Src);
-      GD = Previous;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchXor) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchXor>();
-  switch (IROp->Size) {
-    case 1: {
-      std::atomic<uint8_t> *MemData = *GetSrc<std::atomic<uint8_t> **>(Data->SSAData, Op->Addr);
-      uint8_t Src = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
-      uint8_t Previous = MemData->fetch_xor(Src);
-      GD = Previous;
-      break;
-    }
-    case 2: {
-      std::atomic<uint16_t> *MemData = *GetSrc<std::atomic<uint16_t> **>(Data->SSAData, Op->Addr);
-      uint16_t Src = *GetSrc<uint16_t*>(Data->SSAData, Op->Value);
-      uint16_t Previous = MemData->fetch_xor(Src);
-      GD = Previous;
-      break;
-    }
-    case 4: {
-      std::atomic<uint32_t> *MemData = *GetSrc<std::atomic<uint32_t> **>(Data->SSAData, Op->Addr);
-      uint32_t Src = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-      uint32_t Previous = MemData->fetch_xor(Src);
-      GD = Previous;
-      break;
-    }
-    case 8: {
-      std::atomic<uint64_t> *MemData = *GetSrc<std::atomic<uint64_t> **>(Data->SSAData, Op->Addr);
-      uint64_t Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-      uint64_t Previous = MemData->fetch_xor(Src);
-      GD = Previous;
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchNeg) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
-  switch (IROp->Size) {
-    case 1: {
-      using Type = uint8_t;
-      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Addr));
-      break;
-    }
-    case 2: {
-      using Type = uint16_t;
-      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Addr));
-      break;
-    }
-    case 4: {
-      using Type = uint32_t;
-      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Addr));
-      break;
-    }
-    case 8: {
-      using Type = uint64_t;
-      GD = AtomicFetchNeg(*GetSrc<Type**>(Data->SSAData, Op->Addr));
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", IROp->Size);
-  }
-}
-
-#undef DEF_OP
-
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/BranchOps.cpp

@@ -1,157 +0,0 @@
-/*
-$info$
-tags: backend|interpreter
-$end_info$
-*/
-
-#include "Interface/Context/Context.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/InterpreterDefines.h"
-#include "Interface/HLE/Thunks/Thunks.h"
-
-#include <FEXCore/Utils/BitUtils.h>
-#include <FEXCore/HLE/SyscallHandler.h>
-
-#include <cstdint>
-#include <unistd.h>
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-
-DEF_OP(CallbackReturn) {
-  Data->State->CurrentFrame->Pointers.Interpreter.CallbackReturn(Data->State, Data->StackEntry);
-}
-
-DEF_OP(ExitFunction) {
-  auto Op = IROp->C<IR::IROp_ExitFunction>();
-  uint8_t OpSize = IROp->Size;
-
-  uintptr_t* ContextPtr = reinterpret_cast<uintptr_t*>(Data->State->CurrentFrame);
-
-  void *ContextData = reinterpret_cast<void*>(ContextPtr);
-  void *Src = GetSrc<void*>(Data->SSAData, Op->NewRIP);
-
-  memcpy(ContextData, Src, OpSize);
-
-  Data->BlockResults.Quit = true;
-}
-
-DEF_OP(Jump) {
-  auto Op = IROp->C<IR::IROp_Jump>();
-  const uintptr_t ListBegin = Data->CurrentIR->GetListData();
-  const uintptr_t DataBegin = Data->CurrentIR->GetData();
-
-  Data->BlockIterator = IR::NodeIterator(ListBegin, DataBegin, Op->TargetBlock);
-  Data->BlockResults.Redo = true;
-}
-
-DEF_OP(CondJump) {
-  auto Op = IROp->C<IR::IROp_CondJump>();
-  const uintptr_t ListBegin = Data->CurrentIR->GetListData();
-  const uintptr_t DataBegin = Data->CurrentIR->GetData();
-
-  bool CompResult;
-
-  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp1);
-  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp2);
-
-  if (Op->CompareSize == 4)
-    CompResult = IsConditionTrue<uint32_t, int32_t, float>(Op->Cond.Val, Src1, Src2);
-  else
-    CompResult = IsConditionTrue<uint64_t, int64_t, double>(Op->Cond.Val, Src1, Src2);
-
-  if (CompResult) {
-    Data->BlockIterator = IR::NodeIterator(ListBegin, DataBegin, Op->TrueBlock);
-  }
-  else  {
-    Data->BlockIterator = IR::NodeIterator(ListBegin, DataBegin, Op->FalseBlock);
-  }
-  Data->BlockResults.Redo = true;
-}
-
-DEF_OP(Syscall) {
-  auto Op = IROp->C<IR::IROp_Syscall>();
-
-  FEXCore::HLE::SyscallArguments Args;
-  for (size_t j = 0; j < FEXCore::HLE::SyscallArguments::MAX_ARGS; ++j) {
-    if (Op->Header.Args[j].IsInvalid()) break;
-    Args.Argument[j] = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[j]);
-  }
-
-  uint64_t Res = FEXCore::Context::HandleSyscall(static_cast<Context::ContextImpl*>(Data->State->CTX)->SyscallHandler, Data->State->CurrentFrame, &Args);
-  GD = Res;
-}
-
-DEF_OP(InlineSyscall) {
-  auto Op = IROp->C<IR::IROp_InlineSyscall>();
-
-  FEXCore::HLE::SyscallArguments Args;
-  for (size_t j = 0; j < FEXCore::HLE::SyscallArguments::MAX_ARGS; ++j) {
-    if (Op->Header.Args[j].IsInvalid()) break;
-    Args.Argument[j] = *GetSrc<uint64_t*>(Data->SSAData, Op->Header.Args[j]);
-  }
-
-  // We don't want the errno handling but I also don't want to write inline ASM atm
-  uint64_t Res = syscall(
-    Op->HostSyscallNumber,
-    Args.Argument[0],
-    Args.Argument[1],
-    Args.Argument[2],
-    Args.Argument[3],
-    Args.Argument[4],
-    Args.Argument[5],
-    Args.Argument[6]
-  );
-
-  if (Res == -1) {
-    Res = -errno;
-  }
-
-  GD = Res;
-}
-
-DEF_OP(Thunk) {
-  auto Op = IROp->C<IR::IROp_Thunk>();
-
-  auto thunkFn = static_cast<Context::ContextImpl*>(Data->State->CTX)->ThunkHandler->LookupThunk(Op->ThunkNameHash);
-  thunkFn(*GetSrc<void**>(Data->SSAData, Op->ArgPtr));
-}
-
-DEF_OP(ValidateCode) {
-  auto Op = IROp->C<IR::IROp_ValidateCode>();
-
-  auto CodePtr = Data->CurrentEntry + Op->Offset;
-  if (memcmp((void*)CodePtr, &Op->CodeOriginalLow, Op->CodeLength) != 0) {
-    GD = 1;
-  } else {
-    GD = 0;
-  }
-}
-
-DEF_OP(ThreadRemoveCodeEntry) {
-  static_cast<Context::ContextImpl*>(Data->State->CTX)->ThreadRemoveCodeEntryFromJit(Data->State->CurrentFrame, Data->CurrentEntry);
-}
-
-DEF_OP(CPUID) {
-  auto Op = IROp->C<IR::IROp_CPUID>();
-  uint64_t *DstPtr = GetDest<uint64_t*>(Data->SSAData, Node);
-  const uint64_t Arg = *GetSrc<uint64_t*>(Data->SSAData, Op->Function);
-  const uint64_t Leaf = *GetSrc<uint64_t*>(Data->SSAData, Op->Leaf);
-
-  auto Results = Data->State->CTX->RunCPUIDFunction(Arg, Leaf);
-  memcpy(DstPtr, &Results, sizeof(uint32_t) * 4);
-}
-
-DEF_OP(XGETBV) {
-  auto Op = IROp->C<IR::IROp_XGetBV>();
-  uint32_t *DstPtr = GetDest<uint32_t*>(Data->SSAData, Node);
-  const uint32_t Function = *GetSrc<uint32_t*>(Data->SSAData, Op->Function);
-
-  auto Results = Data->State->CTX->RunXCRFunction(Function);
-  memcpy(DstPtr, &Results, sizeof(uint32_t) * 2);
-}
-
-#undef DEF_OP
-
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/ConversionOps.cpp

@@ -1,278 +0,0 @@
-/*
-$info$
-tags: backend|interpreter
-$end_info$
-*/
-
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/InterpreterDefines.h"
-
-#include <cstdint>
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-DEF_OP(VInsGPR) {
-  const auto Op = IROp->C<IR::IROp_VInsGPR>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto ElementSizeBits = ElementSize * 8;
-  constexpr auto SSEBitSize = Core::CPUState::XMM_SSE_REG_SIZE * 8;
-
-  const uint64_t Offset = Op->DestIdx * ElementSizeBits;
-  const auto InUpperLane = Offset >= SSEBitSize;
-
-  __uint128_t Mask = (1ULL << ElementSizeBits) - 1;
-  if (ElementSize == 8) {
-    Mask = ~0ULL;
-  }
-
-  const auto Src1 = *GetSrc<InterpVector256*>(Data->SSAData, Op->DestVector);
-  const auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Src);
-
-  const auto Scalar = Src2 & Mask;
-  const auto ScaledOffset = InUpperLane ? Offset - SSEBitSize
-                                        : Offset;
-
-  // Now shift into place and set all bits but
-  // the ones where we're going to insert our value.
-  Mask <<= ScaledOffset;
-  Mask = ~Mask;
-
-  const auto Dst = [&] {
-    if (InUpperLane) {
-      return InterpVector256{
-        .Lower = Src1.Lower,
-        .Upper = (Src1.Upper & Mask) | (Scalar << ScaledOffset),
-      };
-    } else {
-      return InterpVector256{
-        .Lower = (Src1.Lower & Mask) | (Scalar << ScaledOffset),
-        .Upper = Src1.Upper,
-      };
-    }
-  }();
-
-  memcpy(GDP, &Dst, OpSize);
-}
-
-DEF_OP(VCastFromGPR) {
-  auto Op = IROp->C<IR::IROp_VCastFromGPR>();
-  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Src), Op->Header.ElementSize);
-}
-
-DEF_OP(VDupFromGPR) {
-  const auto Op = IROp->C<IR::IROp_VDupFromGPR>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = IROp->ElementSize;
-  const auto NumElements = OpSize / IROp->ElementSize;
-
-  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE]{};
-
-  const auto *Src = GetSrc<void*>(Data->SSAData, Op->Src);
-  for (size_t i = 0; i < NumElements; i++) {
-    memcpy(Tmp + (i * ElementSize), Src, ElementSize);
-  }
-
-  memcpy(GDP, Tmp, sizeof(Tmp));
-}
-
-DEF_OP(Float_FromGPR_S) {
-  auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
-
-  const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
-  switch (Conv) {
-    case 0x0404: { // Float <- int32_t
-      const float Dst = (float)*GetSrc<int32_t*>(Data->SSAData, Op->Src);
-      memcpy(GDP, &Dst, Op->Header.ElementSize);
-      break;
-    }
-    case 0x0408: { // Float <- int64_t
-      const float Dst = (float)*GetSrc<int64_t*>(Data->SSAData, Op->Src);
-      memcpy(GDP, &Dst, Op->Header.ElementSize);
-      break;
-    }
-    case 0x0804: { // Double <- int32_t
-      const double Dst = (double)*GetSrc<int32_t*>(Data->SSAData, Op->Src);
-      memcpy(GDP, &Dst, Op->Header.ElementSize);
-      break;
-    }
-    case 0x0808: { // Double <- int64_t
-      const double Dst = (double)*GetSrc<int64_t*>(Data->SSAData, Op->Src);
-      memcpy(GDP, &Dst, Op->Header.ElementSize);
-      break;
-    }
-  }
-}
-
-DEF_OP(Float_FToF) {
-  auto Op = IROp->C<IR::IROp_Float_FToF>();
-  const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
-  switch (Conv) {
-    case 0x0804: { // Double <- Float
-      const double Dst = (double)*GetSrc<float*>(Data->SSAData, Op->Scalar);
-      memcpy(GDP, &Dst, 8);
-      break;
-    }
-    case 0x0408: { // Float <- Double
-      const float Dst = (float)*GetSrc<double*>(Data->SSAData, Op->Scalar);
-      memcpy(GDP, &Dst, 4);
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown FCVT sizes: 0x{:x}", Conv);
-  }
-}
-
-DEF_OP(Vector_SToF) {
-  auto Op = IROp->C<IR::IROp_Vector_SToF>();
-  const uint8_t OpSize = IROp->Size;
-
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
-  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE]{};
-
-  const uint8_t ElementSize = Op->Header.ElementSize;
-  const uint8_t Elements = OpSize / ElementSize;
-
-  const auto Func = [](auto a, auto min, auto max) { return a; };
-  switch (ElementSize) {
-    DO_VECTOR_1SRC_2TYPE_OP(4, float, int32_t, Func, 0, 0)
-    DO_VECTOR_1SRC_2TYPE_OP(8, double, int64_t, Func, 0, 0)
-    default:
-      LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
-      break;
-  }
-  memcpy(GDP, Tmp, OpSize);
-}
-
-DEF_OP(Vector_FToZS) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToZS>();
-  const uint8_t OpSize = IROp->Size;
-
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
-  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE]{};
-
-  const uint8_t ElementSize = Op->Header.ElementSize;
-  const uint8_t Elements = OpSize / ElementSize;
-
-  const auto Func = [](auto a, auto min, auto max) { return std::trunc(a); };
-  switch (ElementSize) {
-    DO_VECTOR_1SRC_2TYPE_OP(4, int32_t, float, Func, 0, 0)
-    DO_VECTOR_1SRC_2TYPE_OP(8, int64_t, double, Func, 0, 0)
-    default:
-      LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
-      break;
-  }
-  memcpy(GDP, Tmp, OpSize);
-}
-
-DEF_OP(Vector_FToS) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToS>();
-  const uint8_t OpSize = IROp->Size;
-
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
-  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE]{};
-
-  const uint8_t ElementSize = Op->Header.ElementSize;
-  const uint8_t Elements = OpSize / ElementSize;
-
-  const auto Func = [](auto a, auto min, auto max) { return std::nearbyint(a); };
-  switch (ElementSize) {
-    DO_VECTOR_1SRC_2TYPE_OP(4, int32_t, float, Func, 0, 0)
-    DO_VECTOR_1SRC_2TYPE_OP(8, int64_t, double, Func, 0, 0)
-    default:
-      LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
-      break;
-  }
-  memcpy(GDP, Tmp, OpSize);
-}
-
-DEF_OP(Vector_FToF) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToF>();
-  const uint8_t OpSize = IROp->Size;
-
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
-  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE]{};
-
-  const uint16_t ElementSize = Op->Header.ElementSize;
-  const uint16_t Conv = (ElementSize << 8) | Op->SrcElementSize;
-
-  const auto Func = [](auto a, auto min, auto max) { return a; };
-  switch (Conv) {
-    case 0x0804: { // Double <- float
-      // Only the lower elements from the source
-      // This uses half the source elements
-      uint8_t Elements = OpSize / 8;
-      DO_VECTOR_1SRC_2TYPE_OP_NOSIZE(double, float, Func, 0, 0)
-      break;
-    }
-    case 0x0408: { // Float <- Double
-      // Little bit tricky here
-      // Sometimes is used to convert from a 128bit vector register
-      // in to a 64bit vector register with different sized elements
-      // eg: %5 i32v2 = Vector_FToF %4 i128, #0x8
-      uint8_t Elements = OpSize == 8 ? 2 : OpSize / Op->SrcElementSize;
-      DO_VECTOR_1SRC_2TYPE_OP_NOSIZE(float, double, Func, 0, 0)
-      break;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unknown Conversion Type : 0x{:04x}", Conv);
-      break;
-  }
-  memcpy(GDP, Tmp, OpSize);
-}
-
-DEF_OP(Vector_FToI) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToI>();
-  const uint8_t OpSize = IROp->Size;
-
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Vector);
-  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE]{};
-
-  const uint8_t ElementSize = Op->Header.ElementSize;
-  const uint8_t Elements = OpSize / ElementSize;
-  const auto Func_Nearest = [](auto a) { return std::rint(a); };
-  const auto Func_Neg = [](auto a) { return std::floor(a); };
-  const auto Func_Pos = [](auto a) { return std::ceil(a); };
-  const auto Func_Trunc = [](auto a) { return std::trunc(a); };
-  const auto Func_Host = [](auto a) { return std::rint(a); };
-
-  switch (Op->Round) {
-    case FEXCore::IR::Round_Nearest.Val:
-      switch (ElementSize) {
-        DO_VECTOR_1SRC_OP(4, float, Func_Nearest)
-        DO_VECTOR_1SRC_OP(8, double, Func_Nearest)
-      }
-    break;
-    case FEXCore::IR::Round_Negative_Infinity.Val:
-      switch (ElementSize) {
-        DO_VECTOR_1SRC_OP(4, float, Func_Neg)
-        DO_VECTOR_1SRC_OP(8, double, Func_Neg)
-      }
-    break;
-    case FEXCore::IR::Round_Positive_Infinity.Val:
-      switch (ElementSize) {
-        DO_VECTOR_1SRC_OP(4, float, Func_Pos)
-        DO_VECTOR_1SRC_OP(8, double, Func_Pos)
-      }
-    break;
-    case FEXCore::IR::Round_Towards_Zero.Val:
-      switch (ElementSize) {
-        DO_VECTOR_1SRC_OP(4, float, Func_Trunc)
-        DO_VECTOR_1SRC_OP(8, double, Func_Trunc)
-      }
-    break;
-    case FEXCore::IR::Round_Host.Val:
-      switch (ElementSize) {
-        DO_VECTOR_1SRC_OP(4, float, Func_Host)
-        DO_VECTOR_1SRC_OP(8, double, Func_Host)
-      }
-    break;
-  }
-  memcpy(GDP, Tmp, OpSize);
-}
-
-#undef DEF_OP
-
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/EncryptionOps.cpp

@@ -1,556 +0,0 @@
-/*
-$info$
-tags: backend|interpreter
-$end_info$
-*/
-
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/InterpreterDefines.h"
-
-#include <cstdint>
-
-namespace AES {
-  static __uint128_t InvShiftRows(uint8_t *State) {
-    uint8_t Shifted[16] = {
-      State[0], State[13], State[10], State[7],
-      State[4], State[1], State[14], State[11],
-      State[8], State[5], State[2], State[15],
-      State[12], State[9], State[6], State[3],
-    };
-    __uint128_t Res{};
-    memcpy(&Res, Shifted, 16);
-    return Res;
-  }
-
-  static __uint128_t InvSubBytes(uint8_t *State) {
-    // 16x16 matrix table
-    static const uint8_t InvSubstitutionTable[256] = {
-      0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
-      0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
-      0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
-      0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
-      0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
-      0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
-      0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
-      0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
-      0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
-      0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
-      0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
-      0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
-      0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
-      0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
-      0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
-      0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d,
-    };
-
-    // Uses a byte substitution table with a constant set of values
-    // Needs to do a table look up
-    uint8_t Substituted[16];
-    for (size_t i = 0; i < 16; ++i) {
-      Substituted[i] = InvSubstitutionTable[State[i]];
-    }
-
-    __uint128_t Res{};
-    memcpy(&Res, Substituted, 16);
-    return Res;
-  }
-
-  static __uint128_t ShiftRows(uint8_t *State) {
-    uint8_t Shifted[16] = {
-      State[0], State[5], State[10], State[15],
-      State[4], State[9], State[14], State[3],
-      State[8], State[13], State[2], State[7],
-      State[12], State[1], State[6], State[11],
-    };
-    __uint128_t Res{};
-    memcpy(&Res, Shifted, 16);
-    return Res;
-  }
-
-  static __uint128_t SubBytes(uint8_t *State, size_t Bytes) {
-    // 16x16 matrix table
-    static const uint8_t SubstitutionTable[256] = {
-      0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
-      0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
-      0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
-      0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
-      0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
-      0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
-      0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
-      0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
-      0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
-      0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
-      0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
-      0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
-      0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
-      0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
-      0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
-      0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16,
-    };
-    // Uses a byte substitution table with a constant set of values
-    // Needs to do a table look up
-    uint8_t Substituted[16];
-    Bytes = std::min(Bytes, (size_t)16);
-    for (size_t i = 0; i < Bytes; ++i) {
-      Substituted[i] = SubstitutionTable[State[i]];
-    }
-
-    __uint128_t Res{};
-    memcpy(&Res, Substituted, Bytes);
-    return Res;
-  }
-
-  static uint8_t FFMul02(uint8_t in) {
-    static const uint8_t FFMul02[256] = {
-      0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
-      0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e,
-      0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, 0x50, 0x52, 0x54, 0x56, 0x58, 0x5a, 0x5c, 0x5e,
-      0x60, 0x62, 0x64, 0x66, 0x68, 0x6a, 0x6c, 0x6e, 0x70, 0x72, 0x74, 0x76, 0x78, 0x7a, 0x7c, 0x7e,
-      0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9c, 0x9e,
-      0xa0, 0xa2, 0xa4, 0xa6, 0xa8, 0xaa, 0xac, 0xae, 0xb0, 0xb2, 0xb4, 0xb6, 0xb8, 0xba, 0xbc, 0xbe,
-      0xc0, 0xc2, 0xc4, 0xc6, 0xc8, 0xca, 0xcc, 0xce, 0xd0, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde,
-      0xe0, 0xe2, 0xe4, 0xe6, 0xe8, 0xea, 0xec, 0xee, 0xf0, 0xf2, 0xf4, 0xf6, 0xf8, 0xfa, 0xfc, 0xfe,
-      0x1b, 0x19, 0x1f, 0x1d, 0x13, 0x11, 0x17, 0x15, 0x0b, 0x09, 0x0f, 0x0d, 0x03, 0x01, 0x07, 0x05,
-      0x3b, 0x39, 0x3f, 0x3d, 0x33, 0x31, 0x37, 0x35, 0x2b, 0x29, 0x2f, 0x2d, 0x23, 0x21, 0x27, 0x25,
-      0x5b, 0x59, 0x5f, 0x5d, 0x53, 0x51, 0x57, 0x55, 0x4b, 0x49, 0x4f, 0x4d, 0x43, 0x41, 0x47, 0x45,
-      0x7b, 0x79, 0x7f, 0x7d, 0x73, 0x71, 0x77, 0x75, 0x6b, 0x69, 0x6f, 0x6d, 0x63, 0x61, 0x67, 0x65,
-      0x9b, 0x99, 0x9f, 0x9d, 0x93, 0x91, 0x97, 0x95, 0x8b, 0x89, 0x8f, 0x8d, 0x83, 0x81, 0x87, 0x85,
-      0xbb, 0xb9, 0xbf, 0xbd, 0xb3, 0xb1, 0xb7, 0xb5, 0xab, 0xa9, 0xaf, 0xad, 0xa3, 0xa1, 0xa7, 0xa5,
-      0xdb, 0xd9, 0xdf, 0xdd, 0xd3, 0xd1, 0xd7, 0xd5, 0xcb, 0xc9, 0xcf, 0xcd, 0xc3, 0xc1, 0xc7, 0xc5,
-      0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, 0xe3, 0xe1, 0xe7, 0xe5,
-    };
-    return FFMul02[in];
-  }
-
-  static uint8_t FFMul03(uint8_t in) {
-    static const uint8_t FFMul03[256] = {
-      0x00, 0x03, 0x06, 0x05, 0x0c, 0x0f, 0x0a, 0x09, 0x18, 0x1b, 0x1e, 0x1d, 0x14, 0x17, 0x12, 0x11,
-      0x30, 0x33, 0x36, 0x35, 0x3c, 0x3f, 0x3a, 0x39, 0x28, 0x2b, 0x2e, 0x2d, 0x24, 0x27, 0x22, 0x21,
-      0x60, 0x63, 0x66, 0x65, 0x6c, 0x6f, 0x6a, 0x69, 0x78, 0x7b, 0x7e, 0x7d, 0x74, 0x77, 0x72, 0x71,
-      0x50, 0x53, 0x56, 0x55, 0x5c, 0x5f, 0x5a, 0x59, 0x48, 0x4b, 0x4e, 0x4d, 0x44, 0x47, 0x42, 0x41,
-      0xc0, 0xc3, 0xc6, 0xc5, 0xcc, 0xcf, 0xca, 0xc9, 0xd8, 0xdb, 0xde, 0xdd, 0xd4, 0xd7, 0xd2, 0xd1,
-      0xf0, 0xf3, 0xf6, 0xf5, 0xfc, 0xff, 0xfa, 0xf9, 0xe8, 0xeb, 0xee, 0xed, 0xe4, 0xe7, 0xe2, 0xe1,
-      0xa0, 0xa3, 0xa6, 0xa5, 0xac, 0xaf, 0xaa, 0xa9, 0xb8, 0xbb, 0xbe, 0xbd, 0xb4, 0xb7, 0xb2, 0xb1,
-      0x90, 0x93, 0x96, 0x95, 0x9c, 0x9f, 0x9a, 0x99, 0x88, 0x8b, 0x8e, 0x8d, 0x84, 0x87, 0x82, 0x81,
-      0x9b, 0x98, 0x9d, 0x9e, 0x97, 0x94, 0x91, 0x92, 0x83, 0x80, 0x85, 0x86, 0x8f, 0x8c, 0x89, 0x8a,
-      0xab, 0xa8, 0xad, 0xae, 0xa7, 0xa4, 0xa1, 0xa2, 0xb3, 0xb0, 0xb5, 0xb6, 0xbf, 0xbc, 0xb9, 0xba,
-      0xfb, 0xf8, 0xfd, 0xfe, 0xf7, 0xf4, 0xf1, 0xf2, 0xe3, 0xe0, 0xe5, 0xe6, 0xef, 0xec, 0xe9, 0xea,
-      0xcb, 0xc8, 0xcd, 0xce, 0xc7, 0xc4, 0xc1, 0xc2, 0xd3, 0xd0, 0xd5, 0xd6, 0xdf, 0xdc, 0xd9, 0xda,
-      0x5b, 0x58, 0x5d, 0x5e, 0x57, 0x54, 0x51, 0x52, 0x43, 0x40, 0x45, 0x46, 0x4f, 0x4c, 0x49, 0x4a,
-      0x6b, 0x68, 0x6d, 0x6e, 0x67, 0x64, 0x61, 0x62, 0x73, 0x70, 0x75, 0x76, 0x7f, 0x7c, 0x79, 0x7a,
-      0x3b, 0x38, 0x3d, 0x3e, 0x37, 0x34, 0x31, 0x32, 0x23, 0x20, 0x25, 0x26, 0x2f, 0x2c, 0x29, 0x2a,
-      0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, 0x1f, 0x1c, 0x19, 0x1a,
-    };
-    return FFMul03[in];
-  }
-
-  static __uint128_t MixColumns(uint8_t *State) {
-    uint8_t In0[16] = {
-      State[0], State[4], State[8], State[12],
-      State[1], State[5], State[9], State[13],
-      State[2], State[6], State[10], State[14],
-      State[3], State[7], State[11], State[15],
-    };
-
-    uint8_t Out0[4]{};
-    uint8_t Out1[4]{};
-    uint8_t Out2[4]{};
-    uint8_t Out3[4]{};
-
-    for (size_t i = 0; i < 4; ++i) {
-      Out0[i] = FFMul02(In0[0 + i]) ^ FFMul03(In0[4 + i]) ^ In0[8 + i] ^ In0[12 + i];
-      Out1[i] = In0[0 + i] ^ FFMul02(In0[4 + i]) ^ FFMul03(In0[8 + i]) ^ In0[12 + i];
-      Out2[i] = In0[0 + i] ^ In0[4 + i] ^ FFMul02(In0[8 + i]) ^ FFMul03(In0[12 + i]);
-      Out3[i] = FFMul03(In0[0 + i]) ^ In0[4 + i] ^ In0[8 + i] ^ FFMul02(In0[12 + i]);
-    }
-
-    uint8_t OutArray[16] = {
-      Out0[0], Out1[0], Out2[0], Out3[0],
-      Out0[1], Out1[1], Out2[1], Out3[1],
-      Out0[2], Out1[2], Out2[2], Out3[2],
-      Out0[3], Out1[3], Out2[3], Out3[3],
-    };
-    __uint128_t Res{};
-    memcpy(&Res, OutArray, 16);
-    return Res;
-  }
-
-  static uint8_t FFMul09(uint8_t in) {
-    static const uint8_t FFMul09[256] = {
-      0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f, 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
-      0x90, 0x99, 0x82, 0x8b, 0xb4, 0xbd, 0xa6, 0xaf, 0xd8, 0xd1, 0xca, 0xc3, 0xfc, 0xf5, 0xee, 0xe7,
-      0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04, 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
-      0xab, 0xa2, 0xb9, 0xb0, 0x8f, 0x86, 0x9d, 0x94, 0xe3, 0xea, 0xf1, 0xf8, 0xc7, 0xce, 0xd5, 0xdc,
-      0x76, 0x7f, 0x64, 0x6d, 0x52, 0x5b, 0x40, 0x49, 0x3e, 0x37, 0x2c, 0x25, 0x1a, 0x13, 0x08, 0x01,
-      0xe6, 0xef, 0xf4, 0xfd, 0xc2, 0xcb, 0xd0, 0xd9, 0xae, 0xa7, 0xbc, 0xb5, 0x8a, 0x83, 0x98, 0x91,
-      0x4d, 0x44, 0x5f, 0x56, 0x69, 0x60, 0x7b, 0x72, 0x05, 0x0c, 0x17, 0x1e, 0x21, 0x28, 0x33, 0x3a,
-      0xdd, 0xd4, 0xcf, 0xc6, 0xf9, 0xf0, 0xeb, 0xe2, 0x95, 0x9c, 0x87, 0x8e, 0xb1, 0xb8, 0xa3, 0xaa,
-      0xec, 0xe5, 0xfe, 0xf7, 0xc8, 0xc1, 0xda, 0xd3, 0xa4, 0xad, 0xb6, 0xbf, 0x80, 0x89, 0x92, 0x9b,
-      0x7c, 0x75, 0x6e, 0x67, 0x58, 0x51, 0x4a, 0x43, 0x34, 0x3d, 0x26, 0x2f, 0x10, 0x19, 0x02, 0x0b,
-      0xd7, 0xde, 0xc5, 0xcc, 0xf3, 0xfa, 0xe1, 0xe8, 0x9f, 0x96, 0x8d, 0x84, 0xbb, 0xb2, 0xa9, 0xa0,
-      0x47, 0x4e, 0x55, 0x5c, 0x63, 0x6a, 0x71, 0x78, 0x0f, 0x06, 0x1d, 0x14, 0x2b, 0x22, 0x39, 0x30,
-      0x9a, 0x93, 0x88, 0x81, 0xbe, 0xb7, 0xac, 0xa5, 0xd2, 0xdb, 0xc0, 0xc9, 0xf6, 0xff, 0xe4, 0xed,
-      0x0a, 0x03, 0x18, 0x11, 0x2e, 0x27, 0x3c, 0x35, 0x42, 0x4b, 0x50, 0x59, 0x66, 0x6f, 0x74, 0x7d,
-      0xa1, 0xa8, 0xb3, 0xba, 0x85, 0x8c, 0x97, 0x9e, 0xe9, 0xe0, 0xfb, 0xf2, 0xcd, 0xc4, 0xdf, 0xd6,
-      0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, 0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46,
-    };
-    return FFMul09[in];
-  }
-
-  static uint8_t FFMul0B(uint8_t in) {
-    static const uint8_t FFMul0B[256] = {
-      0x00, 0x0b, 0x16, 0x1d, 0x2c, 0x27, 0x3a, 0x31, 0x58, 0x53, 0x4e, 0x45, 0x74, 0x7f, 0x62, 0x69,
-      0xb0, 0xbb, 0xa6, 0xad, 0x9c, 0x97, 0x8a, 0x81, 0xe8, 0xe3, 0xfe, 0xf5, 0xc4, 0xcf, 0xd2, 0xd9,
-      0x7b, 0x70, 0x6d, 0x66, 0x57, 0x5c, 0x41, 0x4a, 0x23, 0x28, 0x35, 0x3e, 0x0f, 0x04, 0x19, 0x12,
-      0xcb, 0xc0, 0xdd, 0xd6, 0xe7, 0xec, 0xf1, 0xfa, 0x93, 0x98, 0x85, 0x8e, 0xbf, 0xb4, 0xa9, 0xa2,
-      0xf6, 0xfd, 0xe0, 0xeb, 0xda, 0xd1, 0xcc, 0xc7, 0xae, 0xa5, 0xb8, 0xb3, 0x82, 0x89, 0x94, 0x9f,
-      0x46, 0x4d, 0x50, 0x5b, 0x6a, 0x61, 0x7c, 0x77, 0x1e, 0x15, 0x08, 0x03, 0x32, 0x39, 0x24, 0x2f,
-      0x8d, 0x86, 0x9b, 0x90, 0xa1, 0xaa, 0xb7, 0xbc, 0xd5, 0xde, 0xc3, 0xc8, 0xf9, 0xf2, 0xef, 0xe4,
-      0x3d, 0x36, 0x2b, 0x20, 0x11, 0x1a, 0x07, 0x0c, 0x65, 0x6e, 0x73, 0x78, 0x49, 0x42, 0x5f, 0x54,
-      0xf7, 0xfc, 0xe1, 0xea, 0xdb, 0xd0, 0xcd, 0xc6, 0xaf, 0xa4, 0xb9, 0xb2, 0x83, 0x88, 0x95, 0x9e,
-      0x47, 0x4c, 0x51, 0x5a, 0x6b, 0x60, 0x7d, 0x76, 0x1f, 0x14, 0x09, 0x02, 0x33, 0x38, 0x25, 0x2e,
-      0x8c, 0x87, 0x9a, 0x91, 0xa0, 0xab, 0xb6, 0xbd, 0xd4, 0xdf, 0xc2, 0xc9, 0xf8, 0xf3, 0xee, 0xe5,
-      0x3c, 0x37, 0x2a, 0x21, 0x10, 0x1b, 0x06, 0x0d, 0x64, 0x6f, 0x72, 0x79, 0x48, 0x43, 0x5e, 0x55,
-      0x01, 0x0a, 0x17, 0x1c, 0x2d, 0x26, 0x3b, 0x30, 0x59, 0x52, 0x4f, 0x44, 0x75, 0x7e, 0x63, 0x68,
-      0xb1, 0xba, 0xa7, 0xac, 0x9d, 0x96, 0x8b, 0x80, 0xe9, 0xe2, 0xff, 0xf4, 0xc5, 0xce, 0xd3, 0xd8,
-      0x7a, 0x71, 0x6c, 0x67, 0x56, 0x5d, 0x40, 0x4b, 0x22, 0x29, 0x34, 0x3f, 0x0e, 0x05, 0x18, 0x13,
-      0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, 0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3,
-    };
-    return FFMul0B[in];
-  }
-
-  static uint8_t FFMul0D(uint8_t in) {
-    static const uint8_t FFMul0D[256] = {
-      0x00, 0x0d, 0x1a, 0x17, 0x34, 0x39, 0x2e, 0x23, 0x68, 0x65, 0x72, 0x7f, 0x5c, 0x51, 0x46, 0x4b,
-      0xd0, 0xdd, 0xca, 0xc7, 0xe4, 0xe9, 0xfe, 0xf3, 0xb8, 0xb5, 0xa2, 0xaf, 0x8c, 0x81, 0x96, 0x9b,
-      0xbb, 0xb6, 0xa1, 0xac, 0x8f, 0x82, 0x95, 0x98, 0xd3, 0xde, 0xc9, 0xc4, 0xe7, 0xea, 0xfd, 0xf0,
-      0x6b, 0x66, 0x71, 0x7c, 0x5f, 0x52, 0x45, 0x48, 0x03, 0x0e, 0x19, 0x14, 0x37, 0x3a, 0x2d, 0x20,
-      0x6d, 0x60, 0x77, 0x7a, 0x59, 0x54, 0x43, 0x4e, 0x05, 0x08, 0x1f, 0x12, 0x31, 0x3c, 0x2b, 0x26,
-      0xbd, 0xb0, 0xa7, 0xaa, 0x89, 0x84, 0x93, 0x9e, 0xd5, 0xd8, 0xcf, 0xc2, 0xe1, 0xec, 0xfb, 0xf6,
-      0xd6, 0xdb, 0xcc, 0xc1, 0xe2, 0xef, 0xf8, 0xf5, 0xbe, 0xb3, 0xa4, 0xa9, 0x8a, 0x87, 0x90, 0x9d,
-      0x06, 0x0b, 0x1c, 0x11, 0x32, 0x3f, 0x28, 0x25, 0x6e, 0x63, 0x74, 0x79, 0x5a, 0x57, 0x40, 0x4d,
-      0xda, 0xd7, 0xc0, 0xcd, 0xee, 0xe3, 0xf4, 0xf9, 0xb2, 0xbf, 0xa8, 0xa5, 0x86, 0x8b, 0x9c, 0x91,
-      0x0a, 0x07, 0x10, 0x1d, 0x3e, 0x33, 0x24, 0x29, 0x62, 0x6f, 0x78, 0x75, 0x56, 0x5b, 0x4c, 0x41,
-      0x61, 0x6c, 0x7b, 0x76, 0x55, 0x58, 0x4f, 0x42, 0x09, 0x04, 0x13, 0x1e, 0x3d, 0x30, 0x27, 0x2a,
-      0xb1, 0xbc, 0xab, 0xa6, 0x85, 0x88, 0x9f, 0x92, 0xd9, 0xd4, 0xc3, 0xce, 0xed, 0xe0, 0xf7, 0xfa,
-      0xb7, 0xba, 0xad, 0xa0, 0x83, 0x8e, 0x99, 0x94, 0xdf, 0xd2, 0xc5, 0xc8, 0xeb, 0xe6, 0xf1, 0xfc,
-      0x67, 0x6a, 0x7d, 0x70, 0x53, 0x5e, 0x49, 0x44, 0x0f, 0x02, 0x15, 0x18, 0x3b, 0x36, 0x21, 0x2c,
-      0x0c, 0x01, 0x16, 0x1b, 0x38, 0x35, 0x22, 0x2f, 0x64, 0x69, 0x7e, 0x73, 0x50, 0x5d, 0x4a, 0x47,
-      0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, 0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97,
-    };
-
-    return FFMul0D[in];
-  }
-
-  static uint8_t FFMul0E(uint8_t in) {
-    static const uint8_t FFMul0E[256] = {
-      0x00, 0x0e, 0x1c, 0x12, 0x38, 0x36, 0x24, 0x2a, 0x70, 0x7e, 0x6c, 0x62, 0x48, 0x46, 0x54, 0x5a,
-      0xe0, 0xee, 0xfc, 0xf2, 0xd8, 0xd6, 0xc4, 0xca, 0x90, 0x9e, 0x8c, 0x82, 0xa8, 0xa6, 0xb4, 0xba,
-      0xdb, 0xd5, 0xc7, 0xc9, 0xe3, 0xed, 0xff, 0xf1, 0xab, 0xa5, 0xb7, 0xb9, 0x93, 0x9d, 0x8f, 0x81,
-      0x3b, 0x35, 0x27, 0x29, 0x03, 0x0d, 0x1f, 0x11, 0x4b, 0x45, 0x57, 0x59, 0x73, 0x7d, 0x6f, 0x61,
-      0xad, 0xa3, 0xb1, 0xbf, 0x95, 0x9b, 0x89, 0x87, 0xdd, 0xd3, 0xc1, 0xcf, 0xe5, 0xeb, 0xf9, 0xf7,
-      0x4d, 0x43, 0x51, 0x5f, 0x75, 0x7b, 0x69, 0x67, 0x3d, 0x33, 0x21, 0x2f, 0x05, 0x0b, 0x19, 0x17,
-      0x76, 0x78, 0x6a, 0x64, 0x4e, 0x40, 0x52, 0x5c, 0x06, 0x08, 0x1a, 0x14, 0x3e, 0x30, 0x22, 0x2c,
-      0x96, 0x98, 0x8a, 0x84, 0xae, 0xa0, 0xb2, 0xbc, 0xe6, 0xe8, 0xfa, 0xf4, 0xde, 0xd0, 0xc2, 0xcc,
-      0x41, 0x4f, 0x5d, 0x53, 0x79, 0x77, 0x65, 0x6b, 0x31, 0x3f, 0x2d, 0x23, 0x09, 0x07, 0x15, 0x1b,
-      0xa1, 0xaf, 0xbd, 0xb3, 0x99, 0x97, 0x85, 0x8b, 0xd1, 0xdf, 0xcd, 0xc3, 0xe9, 0xe7, 0xf5, 0xfb,
-      0x9a, 0x94, 0x86, 0x88, 0xa2, 0xac, 0xbe, 0xb0, 0xea, 0xe4, 0xf6, 0xf8, 0xd2, 0xdc, 0xce, 0xc0,
-      0x7a, 0x74, 0x66, 0x68, 0x42, 0x4c, 0x5e, 0x50, 0x0a, 0x04, 0x16, 0x18, 0x32, 0x3c, 0x2e, 0x20,
-      0xec, 0xe2, 0xf0, 0xfe, 0xd4, 0xda, 0xc8, 0xc6, 0x9c, 0x92, 0x80, 0x8e, 0xa4, 0xaa, 0xb8, 0xb6,
-      0x0c, 0x02, 0x10, 0x1e, 0x34, 0x3a, 0x28, 0x26, 0x7c, 0x72, 0x60, 0x6e, 0x44, 0x4a, 0x58, 0x56,
-      0x37, 0x39, 0x2b, 0x25, 0x0f, 0x01, 0x13, 0x1d, 0x47, 0x49, 0x5b, 0x55, 0x7f, 0x71, 0x63, 0x6d,
-      0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, 0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d,
-    };
-
-    return FFMul0E[in];
-  }
-
-  static __uint128_t InvMixColumns(uint8_t *State) {
-    uint8_t In0[16] = {
-      State[0], State[4], State[8], State[12],
-      State[1], State[5], State[9], State[13],
-      State[2], State[6], State[10], State[14],
-      State[3], State[7], State[11], State[15],
-    };
-
-    uint8_t Out0[4]{};
-    uint8_t Out1[4]{};
-    uint8_t Out2[4]{};
-    uint8_t Out3[4]{};
-
-    for (size_t i = 0; i < 4; ++i) {
-      Out0[i] = FFMul0E(In0[0 + i]) ^ FFMul0B(In0[4 + i]) ^ FFMul0D(In0[8 + i]) ^ FFMul09(In0[12 + i]);
-      Out1[i] = FFMul09(In0[0 + i]) ^ FFMul0E(In0[4 + i]) ^ FFMul0B(In0[8 + i]) ^ FFMul0D(In0[12 + i]);
-      Out2[i] = FFMul0D(In0[0 + i]) ^ FFMul09(In0[4 + i]) ^ FFMul0E(In0[8 + i]) ^ FFMul0B(In0[12 + i]);
-      Out3[i] = FFMul0B(In0[0 + i]) ^ FFMul0D(In0[4 + i]) ^ FFMul09(In0[8 + i]) ^ FFMul0E(In0[12 + i]);
-    }
-
-    uint8_t OutArray[16] = {
-      Out0[0], Out1[0], Out2[0], Out3[0],
-      Out0[1], Out1[1], Out2[1], Out3[1],
-      Out0[2], Out1[2], Out2[2], Out3[2],
-      Out0[3], Out1[3], Out2[3], Out3[3],
-    };
-    __uint128_t Res{};
-    memcpy(&Res, OutArray, 16);
-    return Res;
-  }
-}
-
-namespace CRC32 {
-  // CRC32 per byte lookup table.
-  constexpr std::array<uint32_t, 256> CRC32CTable = []() consteval {
-    std::array<uint32_t, 256> Table{};
-
-    // Clang 11.x doesn't support bitreverse as a consteval
-    // constexpr uint32_t Polynomial = 0x1EDC6F41;
-    constexpr uint32_t PolynomialRev = 0x82F63B78; //__builtin_bitreverse32(Polynomial);
-
-    for (size_t Char = 0; Char < std::size(Table); ++Char) {
-      uint32_t CurrentChar = Char;
-      for (size_t i = 0; i < 8; ++i) {
-        if (CurrentChar & 1) {
-          CurrentChar = (CurrentChar >> 1) ^ PolynomialRev;
-        }
-        else {
-          CurrentChar >>= 1;
-        }
-      }
-      Table[Char] = CurrentChar;
-    }
-
-    return Table;
-  }();
-
-  uint32_t crc32cb(uint32_t Accumulator, uint8_t data) {
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ data] ^ Accumulator >> 8;
-    return Accumulator;
-  }
-
-  uint32_t crc32ch(uint32_t Accumulator, uint16_t data) {
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 0) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 8) & 0xFF)] ^ Accumulator >> 8;
-    return Accumulator;
-  }
-
-  uint32_t crc32cw(uint32_t Accumulator, uint32_t data) {
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  0) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  8) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 16) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 24) & 0xFF)] ^ Accumulator >> 8;
-    return Accumulator;
-  }
-
-  uint32_t crc32cx(uint32_t Accumulator, uint64_t data) {
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  0) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >>  8) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 16) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 24) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 32) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 40) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 48) & 0xFF)] ^ Accumulator >> 8;
-    Accumulator = CRC32CTable[(uint8_t)Accumulator ^ ((data >> 56) & 0xFF)] ^ Accumulator >> 8;
-    return Accumulator;
-  }
-}
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-
-DEF_OP(AESImc) {
-  auto Op = IROp->C<IR::IROp_VAESImc>();
-  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Vector);
-
-  // Pseudo-code
-  // Dst = InvMixColumns(STATE)
-  __uint128_t Tmp{};
-  Tmp = AES::InvMixColumns(reinterpret_cast<uint8_t*>(&Src1));
-  memcpy(GDP, &Tmp, sizeof(Tmp));
-}
-
-DEF_OP(AESEnc) {
-  auto Op = IROp->C<IR::IROp_VAESEnc>();
-  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->State);
-  auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Key);
-
-  // Pseudo-code
-  // STATE = Src1
-  // RoundKey = Src2
-  // STATE = ShiftRows(STATE)
-  // STATE = SubBytes(STATE)
-  // STATE = MixColumns(STATE)
-  // Dst = STATE XOR RoundKey
-  __uint128_t Tmp{};
-  Tmp = AES::ShiftRows(reinterpret_cast<uint8_t*>(&Src1));
-  Tmp = AES::SubBytes(reinterpret_cast<uint8_t*>(&Tmp), 16);
-  Tmp = AES::MixColumns(reinterpret_cast<uint8_t*>(&Tmp));
-  Tmp = Tmp ^ Src2;
-  memcpy(GDP, &Tmp, sizeof(Tmp));
-}
-
-DEF_OP(AESEncLast) {
-  auto Op = IROp->C<IR::IROp_VAESEncLast>();
-  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->State);
-  auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Key);
-
-  // Pseudo-code
-  // STATE = Src1
-  // RoundKey = Src2
-  // STATE = ShiftRows(STATE)
-  // STATE = SubBytes(STATE)
-  // Dst = STATE XOR RoundKey
-  __uint128_t Tmp{};
-  Tmp = AES::ShiftRows(reinterpret_cast<uint8_t*>(&Src1));
-  Tmp = AES::SubBytes(reinterpret_cast<uint8_t*>(&Tmp), 16);
-  Tmp = Tmp ^ Src2;
-  memcpy(GDP, &Tmp, sizeof(Tmp));
-}
-
-DEF_OP(AESDec) {
-  auto Op = IROp->C<IR::IROp_VAESDec>();
-  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->State);
-  auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Key);
-
-  // Pseudo-code
-  // STATE = Src1
-  // RoundKey = Src2
-  // STATE = InvShiftRows(STATE)
-  // STATE = InvSubBytes(STATE)
-  // STATE = InvMixColumns(STATE)
-  // Dst = STATE XOR RoundKey
-  __uint128_t Tmp{};
-  Tmp = AES::InvShiftRows(reinterpret_cast<uint8_t*>(&Src1));
-  Tmp = AES::InvSubBytes(reinterpret_cast<uint8_t*>(&Tmp));
-  Tmp = AES::InvMixColumns(reinterpret_cast<uint8_t*>(&Tmp));
-  Tmp = Tmp ^ Src2;
-  memcpy(GDP, &Tmp, sizeof(Tmp));
-}
-
-DEF_OP(AESDecLast) {
-  auto Op = IROp->C<IR::IROp_VAESDecLast>();
-  auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->State);
-  auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Key);
-
-  // Pseudo-code
-  // STATE = Src1
-  // RoundKey = Src2
-  // STATE = InvShiftRows(STATE)
-  // STATE = InvSubBytes(STATE)
-  // Dst = STATE XOR RoundKey
-  __uint128_t Tmp{};
-  Tmp = AES::InvShiftRows(reinterpret_cast<uint8_t*>(&Src1));
-  Tmp = AES::InvSubBytes(reinterpret_cast<uint8_t*>(&Tmp));
-  Tmp = Tmp ^ Src2;
-  memcpy(GDP, &Tmp, sizeof(Tmp));
-}
-
-DEF_OP(AESKeyGenAssist) {
-  auto Op = IROp->C<IR::IROp_VAESKeyGenAssist>();
-  const uint8_t *Src1 = GetSrc<uint8_t*>(Data->SSAData, Op->Src);
-
-  // Pseudo-code
-  // X3 = Src1[127:96]
-  // X2 = Src1[95:64]
-  // X1 = Src1[63:32]
-  // X0 = Src1[31:30]
-  // RCON = (Zext)rcon
-  // Dest[31:0] = SubWord(X1)
-  // Dest[63:32] = RotWord(SubWord(X1)) XOR RCON
-  // Dest[95:64] = SubWord(X3)
-  // Dest[127:96] = RotWord(SubWord(X3)) XOR RCON
-  __uint128_t Tmp{};
-  uint32_t X1{};
-  uint32_t X3{};
-  memcpy(&X1, &Src1[4], 4);
-  memcpy(&X3, &Src1[12], 4);
-  uint32_t SubWord_X1 = AES::SubBytes(reinterpret_cast<uint8_t*>(&X1), 4);
-  uint32_t SubWord_X3 = AES::SubBytes(reinterpret_cast<uint8_t*>(&X3), 4);
-
-  auto Ror = [] (auto In, auto R) {
-    auto RotateMask = sizeof(In) * 8 - 1;
-    R &= RotateMask;
-    return (In >> R) | (In << (sizeof(In) * 8 - R));
-  };
-
-  uint32_t Rot_X1 = Ror(SubWord_X1, 8);
-  uint32_t Rot_X3 = Ror(SubWord_X3, 8);
-
-  Tmp = Rot_X3 ^ Op->RCON;
-  Tmp <<= 32;
-  Tmp |= SubWord_X3;
-  Tmp <<= 32;
-  Tmp |= Rot_X1 ^ Op->RCON;
-  Tmp <<= 32;
-  Tmp |= SubWord_X1;
-  memcpy(GDP, &Tmp, sizeof(Tmp));
-}
-
-DEF_OP(CRC32) {
-  auto Op = IROp->C<IR::IROp_CRC32>();
-  uint32_t Src1 = *GetSrc<uint32_t*>(Data->SSAData, Op->Src1);
-  uint8_t *Src2 = GetSrc<uint8_t*>(Data->SSAData, Op->Src2);
-  uint32_t Tmp{};
-
-  switch (Op->SrcSize) {
-    case 1:
-      Tmp = CRC32::crc32cb(Src1, *(uint8_t*)Src2);
-      break;
-    case 2:
-      Tmp = CRC32::crc32ch(Src1, *(uint16_t*)Src2);
-      break;
-    case 4:
-      Tmp = CRC32::crc32cw(Src1, *(uint32_t*)Src2);
-      break;
-    case 8:
-      Tmp = CRC32::crc32cx(Src1, *(uint64_t*)Src2);
-      break;
-    default:
-      LOGMAN_MSG_A_FMT("Unknown CRC32C size: {}", Op->SrcSize);
-      break;
-
-  }
-  memcpy(GDP, &Tmp, sizeof(Tmp));
-}
-
-DEF_OP(PCLMUL) {
-  auto Op = IROp->C<IR::IROp_PCLMUL>();
-
-  const auto Selector = Op->Selector;
-  auto* Dst  = GetDest<uint64_t*>(Data->SSAData, Node);
-  auto* Src1 = GetSrc<uint64_t*>(Data->SSAData, Op->Src1);
-  auto* Src2 = GetSrc<uint64_t*>(Data->SSAData, Op->Src2);
-
-  const uint64_t TMP1 = (Selector & 0x01) == 0 ? Src1[0] : Src1[1];
-  const uint64_t TMP2 = (Selector & 0x10) == 0 ? Src2[0] : Src2[1];
-  
-  const auto make_lo = [](uint64_t lhs, uint64_t rhs) {
-    uint64_t result = 0;
-
-    for (size_t i = 0; i < 64; i++) {
-      if ((lhs & (1ULL << i)) != 0) {
-        result ^= rhs << i;
-      }
-    }
-
-    return result;
-  };
-  const auto make_hi = [](uint64_t lhs, uint64_t rhs) {
-    uint64_t result = 0;
-
-    for (size_t i = 1; i < 64; i++) {
-      if ((lhs & (1ULL << i)) != 0) {
-        result ^= rhs >> (64 - i);
-      }
-    }
-
-    return result;
-  };
-
-  Dst[0] = make_lo(TMP1, TMP2);
-  Dst[1] = make_hi(TMP1, TMP2);
-}
-
-#undef DEF_OP
-
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp

@@ -1,422 +0,0 @@
-/*
-$info$
-tags: backend|interpreter
-$end_info$
-*/
-
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/InterpreterDefines.h"
-
-#include "Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h"
-
-#include <cstdint>
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-DEF_OP(F80LOADFCW) {
-  FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle(*GetSrc<uint16_t*>(Data->SSAData, IROp->Args[0]));
-}
-
-DEF_OP(F80ADD) {
-  auto Op = IROp->C<IR::IROp_F80Add>();
-  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
-  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
-  const auto Tmp = X80SoftFloat::FADD(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80SUB) {
-  auto Op = IROp->C<IR::IROp_F80Sub>();
-  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
-  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
-  const auto Tmp = X80SoftFloat::FSUB(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80MUL) {
-  auto Op = IROp->C<IR::IROp_F80Mul>();
-  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
-  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
-  const auto Tmp = X80SoftFloat::FMUL(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80DIV) {
-  auto Op = IROp->C<IR::IROp_F80Div>();
-  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
-  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
-  const auto Tmp = X80SoftFloat::FDIV(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80FYL2X) {
-  auto Op = IROp->C<IR::IROp_F80FYL2X>();
-  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
-  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
-  const auto Tmp = X80SoftFloat::FYL2X(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80ATAN) {
-  auto Op = IROp->C<IR::IROp_F80ATAN>();
-  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
-  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
-  const auto Tmp = X80SoftFloat::FATAN(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80FPREM1) {
-  auto Op = IROp->C<IR::IROp_F80FPREM1>();
-  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
-  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
-  const auto Tmp = X80SoftFloat::FREM1(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80FPREM) {
-  auto Op = IROp->C<IR::IROp_F80FPREM>();
-  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
-  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
-  const auto Tmp = X80SoftFloat::FREM(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80SCALE) {
-  auto Op = IROp->C<IR::IROp_F80SCALE>();
-  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
-  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
-  const auto Tmp = X80SoftFloat::FSCALE(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80CVT) {
-  auto Op = IROp->C<IR::IROp_F80CVT>();
-  const uint8_t OpSize = IROp->Size;
-
-  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
-
-  switch (OpSize) {
-    case 4: {
-      float Tmp = Src;
-      memcpy(GDP, &Tmp, OpSize);
-      break;
-    }
-    case 8: {
-      double Tmp = Src;
-      memcpy(GDP, &Tmp, OpSize);
-      break;
-    }
-    default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
-  }
-}
-
-DEF_OP(F80CVTINT) {
-  auto Op = IROp->C<IR::IROp_F80CVTInt>();
-  const uint8_t OpSize = IROp->Size;
-
-  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
-
-  switch (OpSize) {
-    case 2: {
-      int16_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t : FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2)(Src);
-      memcpy(GDP, &Tmp, sizeof(Tmp));
-      break;
-    }
-    case 4: {
-      int32_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t : FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4)(Src);
-      memcpy(GDP, &Tmp, sizeof(Tmp));
-      break;
-    }
-    case 8: {
-      int64_t Tmp = (Op->Truncate? FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t : FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8)(Src);
-      memcpy(GDP, &Tmp, sizeof(Tmp));
-      break;
-    }
-    default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
-  }
-}
-
-DEF_OP(F80CVTTO) {
-  auto Op = IROp->C<IR::IROp_F80CVTTo>();
-
-  switch (Op->SrcSize) {
-    case 4: {
-      float Src = *GetSrc<float *>(Data->SSAData, Op->X80Src);
-      X80SoftFloat Tmp = Src;
-      memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-      break;
-    }
-    case 8: {
-      double Src = *GetSrc<double *>(Data->SSAData, Op->X80Src);
-      X80SoftFloat Tmp = Src;
-      memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-      break;
-    }
-    default: LogMan::Msg::DFmt("Unhandled size: {}", Op->SrcSize);
-  }
-}
-
-DEF_OP(F80CVTTOINT) {
-  auto Op = IROp->C<IR::IROp_F80CVTToInt>();
-
-  switch (Op->SrcSize) {
-    case 2: {
-      int16_t Src = *GetSrc<int16_t*>(Data->SSAData, Op->Src);
-      X80SoftFloat Tmp = Src;
-      memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-      break;
-    }
-    case 4: {
-      int32_t Src = *GetSrc<int32_t*>(Data->SSAData, Op->Src);
-      X80SoftFloat Tmp = Src;
-      memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-      break;
-    }
-    default: LogMan::Msg::DFmt("Unhandled size: {}", Op->SrcSize);
-  }
-}
-
-DEF_OP(F80ROUND) {
-  auto Op = IROp->C<IR::IROp_F80Round>();
-  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
-  const auto Tmp = X80SoftFloat::FRNDINT(Src);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80F2XM1) {
-  auto Op = IROp->C<IR::IROp_F80F2XM1>();
-  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
-  const auto Tmp = X80SoftFloat::F2XM1(Src);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80TAN) {
-  auto Op = IROp->C<IR::IROp_F80TAN>();
-  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
-  const auto Tmp = X80SoftFloat::FTAN(Src);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80SQRT) {
-  auto Op = IROp->C<IR::IROp_F80SQRT>();
-  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
-  const auto Tmp = X80SoftFloat::FSQRT(Src);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80SIN) {
-  auto Op = IROp->C<IR::IROp_F80SIN>();
-  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
-  const auto Tmp = X80SoftFloat::FSIN(Src);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80COS) {
-  auto Op = IROp->C<IR::IROp_F80COS>();
-  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
-  const auto Tmp = X80SoftFloat::FCOS(Src);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80XTRACT_EXP) {
-  auto Op = IROp->C<IR::IROp_F80XTRACT_EXP>();
-  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
-  const auto Tmp = X80SoftFloat::FXTRACT_EXP(Src);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80XTRACT_SIG) {
-  auto Op = IROp->C<IR::IROp_F80XTRACT_SIG>();
-  const auto Src = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src);
-  const auto Tmp = X80SoftFloat::FXTRACT_SIG(Src);
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80CMP) {
-  auto Op = IROp->C<IR::IROp_F80Cmp>();
-  uint32_t ResultFlags{};
-  const auto Src1 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src1);
-  const auto Src2 = *GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src2);
-  bool eq, lt, nan;
-  X80SoftFloat::FCMP(Src1, Src2, &eq, &lt, &nan);
-  if (Op->Flags & (1 << IR::FCMP_FLAG_LT) &&
-      lt) {
-    ResultFlags |= (1 << IR::FCMP_FLAG_LT);
-  }
-  if (Op->Flags & (1 << IR::FCMP_FLAG_UNORDERED) &&
-      nan) {
-    ResultFlags |= (1 << IR::FCMP_FLAG_UNORDERED);
-  }
-  if (Op->Flags & (1 << IR::FCMP_FLAG_EQ) &&
-      eq) {
-    ResultFlags |= (1 << IR::FCMP_FLAG_EQ);
-  }
-
-  GD = ResultFlags;
-}
-
-DEF_OP(F80BCDLOAD) {
-  auto Op = IROp->C<IR::IROp_F80BCDLoad>();
-  const uint8_t *Src1 = GetSrc<uint8_t*>(Data->SSAData, Op->X80Src);
-  uint64_t BCD{};
-  // We walk through each uint8_t and pull out the BCD encoding
-  // Each 4bit split is a digit
-  // Only 0-9 is supported, A-F results in undefined data
-  // | 4 bit     | 4 bit    |
-  // | 10s place | 1s place |
-  // EG 0x48 = 48
-  // EG 0x4847 = 4847
-  // This gives us an 18digit value encoded in BCD
-  // The last byte lets us know if it negative or not
-  for (size_t i = 0; i < 9; ++i) {
-    uint8_t Digit = Src1[8 - i];
-    // First shift our last value over
-    BCD *= 100;
-
-    // Add the tens place digit
-    BCD += (Digit >> 4) * 10;
-
-    // Add the ones place digit
-    BCD += Digit & 0xF;
-  }
-
-  // Set negative flag once converted to x87
-  bool Negative = Src1[9] & 0x80;
-  X80SoftFloat Tmp;
-
-  Tmp = BCD;
-  Tmp.Sign = Negative;
-
-  memcpy(GDP, &Tmp, sizeof(X80SoftFloat));
-}
-
-DEF_OP(F80BCDSTORE) {
-  auto Op = IROp->C<IR::IROp_F80BCDStore>();
-  X80SoftFloat Src1 = X80SoftFloat::FRNDINT(*GetSrc<X80SoftFloat*>(Data->SSAData, Op->X80Src));
-  bool Negative = Src1.Sign;
-
-  // Clear the Sign bit
-  Src1.Sign = 0;
-
-  uint64_t Tmp = Src1;
-  uint8_t BCD[10]{};
-
-  for (size_t i = 0; i < 9; ++i) {
-    if (Tmp == 0) {
-      // Nothing left? Just leave
-      break;
-    }
-    // Extract the lower 100 values
-    uint8_t Digit = Tmp % 100;
-
-    // Now divide it for the next iteration
-    Tmp /= 100;
-
-    uint8_t UpperNibble = Digit / 10;
-    uint8_t LowerNibble = Digit % 10;
-
-    // Now store the BCD
-    BCD[i] = (UpperNibble << 4) | LowerNibble;
-  }
-
-  // Set negative flag once converted to x87
-  BCD[9] = Negative ? 0x80 : 0;
-
-  memcpy(GDP, BCD, 10);
-}
-
-DEF_OP(F64SIN) {
-  auto Op = IROp->C<IR::IROp_F64SIN>();
-  const double Src = *GetSrc<double*>(Data->SSAData, Op->Src);
-  const double Tmp = sin(Src);
-  memcpy(GDP, &Tmp, sizeof(double));
-}
-
-DEF_OP(F64COS) {
-  auto Op = IROp->C<IR::IROp_F64COS>();
-  const double Src = *GetSrc<double*>(Data->SSAData, Op->Src);
-  const double Tmp = cos(Src);
-  memcpy(GDP, &Tmp, sizeof(double));
-}
-
-DEF_OP(F64TAN) {
-  auto Op = IROp->C<IR::IROp_F64TAN>();
-  const double Src = *GetSrc<double*>(Data->SSAData, Op->Src);
-  const double Tmp = tan(Src);
-  memcpy(GDP, &Tmp, sizeof(double));
-}
-
-DEF_OP(F64F2XM1) {
-  auto Op = IROp->C<IR::IROp_F64F2XM1>();
-  const double Src = *GetSrc<double*>(Data->SSAData, Op->Src);
-  const double Tmp = exp2(Src) - 1.0;
-  memcpy(GDP, &Tmp, sizeof(double));
-}
-
-DEF_OP(F64ATAN) {
-  auto Op = IROp->C<IR::IROp_F64ATAN>();
-  const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Src1);
-  const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Src2);
-  const double Tmp = atan2(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(double));
-}
-
-DEF_OP(F64FPREM) {
-  auto Op = IROp->C<IR::IROp_F64FPREM>();
-  const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Src1);
-  const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Src2);
-  const double Tmp = fmod(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(double));
-}
-
-DEF_OP(F64FPREM1) {
-  auto Op = IROp->C<IR::IROp_F64FPREM1>();
-  const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Src1);
-  const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Src2);
-  const double Tmp = remainder(Src1, Src2);
-
-  memcpy(GDP, &Tmp, sizeof(double));
-}
-
-DEF_OP(F64FYL2X) {
-  auto Op = IROp->C<IR::IROp_F64FYL2X>();
-  const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Src);
-  const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Src2);
-  const double Tmp = Src2 * log2(Src1);
-
-  memcpy(GDP, &Tmp, sizeof(double));
-}
-
-DEF_OP(F64SCALE) {
-  auto Op = IROp->C<IR::IROp_F64SCALE>();
-  const double Src1 = *GetSrc<double*>(Data->SSAData, Op->Src1);
-  const double Src2 = *GetSrc<double*>(Data->SSAData, Op->Src2);
-  const double trunc = (double)(int64_t)(Src2); //truncate
-  const double Tmp = Src1 * exp2(trunc);
-
-  memcpy(GDP, &Tmp, sizeof(double));
-}
-
-#undef DEF_OP
-
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp

@@ -1,336 +0,0 @@
-#include <FEXCore/Core/CoreState.h>
-
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h"
-#include "Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h"
-
-#include <cstddef>
-#include <cstdint>
-
-namespace FEXCore::CPU {
-
-template<typename R, typename... Args>
-static FallbackInfo GetFallbackInfo(R(*fn)(Args...), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_UNKNOWN, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(float), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_F32, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_F64, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(int16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_I16, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(void(*fn)(uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_VOID_U16, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(int32_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_I32, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(float(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F32_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(double(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F64_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(double(*fn)(double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F64_F64, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(double(*fn)(double,double), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F64_F64_F64, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(int16_t(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I16_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(int32_t(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I32_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(int64_t(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I64_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(uint64_t(*fn)(X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I64_F80_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat, X80SoftFloat), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_F80_F80_F80, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(uint32_t(*fn)(uint64_t, uint64_t, __uint128_t, __uint128_t, uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I32_I64_I64_I128_I128_I16, (void*)fn, HandlerIndex};
-}
-
-template<>
-FallbackInfo GetFallbackInfo(uint32_t(*fn)(__uint128_t, __uint128_t, uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
-  return {FABI_I32_I128_I128_I16, (void*)fn, HandlerIndex};
-}
-
-void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) {
-  Info[Core::OPINDEX_F80LOADFCW] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle, Core::OPINDEX_F80LOADFCW).fn);
-  Info[Core::OPINDEX_F80CVTTO_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4).fn);
-  Info[Core::OPINDEX_F80CVTTO_8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8, Core::OPINDEX_F80CVTTO_8).fn);
-  Info[Core::OPINDEX_F80CVT_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4, Core::OPINDEX_F80CVT_4).fn);
-  Info[Core::OPINDEX_F80CVT_8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8, Core::OPINDEX_F80CVT_8).fn);
-  Info[Core::OPINDEX_F80CVTINT_2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2, Core::OPINDEX_F80CVTINT_2).fn);
-  Info[Core::OPINDEX_F80CVTINT_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4, Core::OPINDEX_F80CVTINT_4).fn);
-  Info[Core::OPINDEX_F80CVTINT_8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8, Core::OPINDEX_F80CVTINT_8).fn);
-  Info[Core::OPINDEX_F80CVTINT_TRUNC2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2).fn);
-  Info[Core::OPINDEX_F80CVTINT_TRUNC4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4).fn);
-  Info[Core::OPINDEX_F80CVTINT_TRUNC8] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8).fn);
-  Info[Core::OPINDEX_F80CMP_0] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>, Core::OPINDEX_F80CMP_0).fn);
-  Info[Core::OPINDEX_F80CMP_1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<1>, Core::OPINDEX_F80CMP_1).fn);
-  Info[Core::OPINDEX_F80CMP_2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<2>, Core::OPINDEX_F80CMP_2).fn);
-  Info[Core::OPINDEX_F80CMP_3] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<3>, Core::OPINDEX_F80CMP_3).fn);
-  Info[Core::OPINDEX_F80CMP_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<4>, Core::OPINDEX_F80CMP_4).fn);
-  Info[Core::OPINDEX_F80CMP_5] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<5>, Core::OPINDEX_F80CMP_5).fn);
-  Info[Core::OPINDEX_F80CMP_6] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<6>, Core::OPINDEX_F80CMP_6).fn);
-  Info[Core::OPINDEX_F80CMP_7] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>, Core::OPINDEX_F80CMP_7).fn);
-  Info[Core::OPINDEX_F80CVTTOINT_2] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2, Core::OPINDEX_F80CVTTOINT_2).fn);
-  Info[Core::OPINDEX_F80CVTTOINT_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4, Core::OPINDEX_F80CVTTOINT_4).fn);
-
-  // Unary
-  Info[Core::OPINDEX_F80ROUND] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80ROUND>::handle, Core::OPINDEX_F80ROUND).fn);
-  Info[Core::OPINDEX_F80F2XM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80F2XM1>::handle, Core::OPINDEX_F80F2XM1).fn);
-  Info[Core::OPINDEX_F80TAN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80TAN>::handle, Core::OPINDEX_F80TAN).fn);
-  Info[Core::OPINDEX_F80SQRT] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SQRT>::handle, Core::OPINDEX_F80SQRT).fn);
-  Info[Core::OPINDEX_F80SIN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SIN>::handle, Core::OPINDEX_F80SIN).fn);
-  Info[Core::OPINDEX_F80COS] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80COS>::handle, Core::OPINDEX_F80COS).fn);
-  Info[Core::OPINDEX_F80XTRACT_EXP] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_EXP>::handle, Core::OPINDEX_F80XTRACT_EXP).fn);
-  Info[Core::OPINDEX_F80XTRACT_SIG] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80XTRACT_SIG>::handle, Core::OPINDEX_F80XTRACT_SIG).fn);
-  Info[Core::OPINDEX_F80BCDSTORE] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDSTORE>::handle, Core::OPINDEX_F80BCDSTORE).fn);
-  Info[Core::OPINDEX_F80BCDLOAD] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80BCDLOAD>::handle, Core::OPINDEX_F80BCDLOAD).fn);
-
-  // Binary
-  Info[Core::OPINDEX_F80ADD] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80ADD>::handle, Core::OPINDEX_F80ADD).fn);
-  Info[Core::OPINDEX_F80SUB] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SUB>::handle, Core::OPINDEX_F80SUB).fn);
-  Info[Core::OPINDEX_F80MUL] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80MUL>::handle, Core::OPINDEX_F80MUL).fn);
-  Info[Core::OPINDEX_F80DIV] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80DIV>::handle, Core::OPINDEX_F80DIV).fn);
-  Info[Core::OPINDEX_F80FYL2X] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80FYL2X>::handle, Core::OPINDEX_F80FYL2X).fn);
-  Info[Core::OPINDEX_F80ATAN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80ATAN>::handle, Core::OPINDEX_F80ATAN).fn);
-  Info[Core::OPINDEX_F80FPREM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM1>::handle, Core::OPINDEX_F80FPREM1).fn);
-  Info[Core::OPINDEX_F80FPREM] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80FPREM>::handle, Core::OPINDEX_F80FPREM).fn);
-  Info[Core::OPINDEX_F80SCALE] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80SCALE>::handle, Core::OPINDEX_F80SCALE).fn);
-
-  // Double Precision
-  Info[Core::OPINDEX_F64SIN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64SIN>::handle, Core::OPINDEX_F64SIN).fn);
-  Info[Core::OPINDEX_F64COS] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64COS>::handle, Core::OPINDEX_F64COS).fn);
-  Info[Core::OPINDEX_F64TAN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64TAN>::handle, Core::OPINDEX_F64TAN).fn);
-  Info[Core::OPINDEX_F64ATAN] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64ATAN>::handle, Core::OPINDEX_F64ATAN).fn);
-  Info[Core::OPINDEX_F64F2XM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64F2XM1>::handle, Core::OPINDEX_F64F2XM1).fn);
-  Info[Core::OPINDEX_F64FYL2X] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64FYL2X>::handle, Core::OPINDEX_F64FYL2X).fn);
-  Info[Core::OPINDEX_F64FPREM] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM>::handle, Core::OPINDEX_F64FPREM).fn);
-  Info[Core::OPINDEX_F64FPREM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM1>::handle, Core::OPINDEX_F64FPREM1).fn);
-  Info[Core::OPINDEX_F64SCALE] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64SCALE>::handle, Core::OPINDEX_F64SCALE).fn);
-
-  // SSE4.2 string instructions
-  Info[Core::OPINDEX_VPCMPESTRX] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX).fn);
-  Info[Core::OPINDEX_VPCMPISTRX] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX).fn);
-}
-
-bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInfo *Info) {
-  uint8_t OpSize = IROp->Size;
-  switch(IROp->Op) {
-    case IR::OP_F80LOADFCW: {
-      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle, Core::OPINDEX_F80LOADFCW);
-      return true;
-    }
-
-    case IR::OP_F80CVTTO: {
-      auto Op = IROp->C<IR::IROp_F80CVTTo>();
-
-      switch (Op->SrcSize) {
-        case 4: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4);
-          return true;
-        }
-        case 8: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8, Core::OPINDEX_F80CVTTO_8);
-          return true;
-        }
-      default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
-      }
-      break;
-    }
-    case IR::OP_F80CVT: {
-      switch (OpSize) {
-        case 4: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4, Core::OPINDEX_F80CVT_4);
-          return true;
-        }
-        case 8: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8, Core::OPINDEX_F80CVT_8);
-          return true;
-        }
-        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
-      }
-      break;
-    }
-    case IR::OP_F80CVTINT: {
-      auto Op = IROp->C<IR::IROp_F80CVTInt>();
-
-      switch (OpSize) {
-        case 2: {
-          if (Op->Truncate) {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2);
-          }
-          else {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2, Core::OPINDEX_F80CVTINT_2);
-          }
-          return true;
-        }
-        case 4: {
-          if (Op->Truncate) {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4);
-          }
-          else {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4, Core::OPINDEX_F80CVTINT_4);
-          }
-          return true;
-        }
-        case 8: {
-          if (Op->Truncate) {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8);
-          }
-          else {
-            *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8, Core::OPINDEX_F80CVTINT_8);
-          }
-          return true;
-        }
-        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
-      }
-      break;
-    }
-    case IR::OP_F80CMP: {
-      auto Op = IROp->C<IR::IROp_F80Cmp>();
-
-      static constexpr std::array handlers{
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<1>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<2>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<3>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<4>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<5>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<6>,
-        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>,
-      };
-
-      *Info = GetFallbackInfo(handlers[Op->Flags], (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP_0 + Op->Flags));
-      return true;
-    }
-
-    case IR::OP_F80CVTTOINT: {
-      auto Op = IROp->C<IR::IROp_F80CVTToInt>();
-
-      switch (Op->SrcSize) {
-        case 2: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2, Core::OPINDEX_F80CVTTOINT_2);
-          return true;
-        }
-        case 4: {
-          *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4, Core::OPINDEX_F80CVTTOINT_4);
-          return true;
-        }
-        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
-      }
-      break;
-    }
-
-#define COMMON_X87_OP(OP) \
-    case IR::OP_F80##OP: { \
-      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP); \
-      return true; \
-    }
-
-#define COMMON_F64_OP(OP) \
-    case IR::OP_F64##OP: { \
-      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64##OP>::handle, Core::OPINDEX_F64##OP); \
-      return true; \
-    }
-
-    // Unary
-    COMMON_X87_OP(ROUND)
-    COMMON_X87_OP(F2XM1)
-    COMMON_X87_OP(TAN)
-    COMMON_X87_OP(SQRT)
-    COMMON_X87_OP(SIN)
-    COMMON_X87_OP(COS)
-    COMMON_X87_OP(XTRACT_EXP)
-    COMMON_X87_OP(XTRACT_SIG)
-    COMMON_X87_OP(BCDSTORE)
-    COMMON_X87_OP(BCDLOAD)
-
-    // Binary
-    COMMON_X87_OP(ADD)
-    COMMON_X87_OP(SUB)
-    COMMON_X87_OP(MUL)
-    COMMON_X87_OP(DIV)
-    COMMON_X87_OP(FYL2X)
-    COMMON_X87_OP(ATAN)
-    COMMON_X87_OP(FPREM1)
-    COMMON_X87_OP(FPREM)
-    COMMON_X87_OP(SCALE)
-
-    // Double Precision Unary
-    COMMON_F64_OP(F2XM1)
-    COMMON_F64_OP(TAN)
-    COMMON_F64_OP(SIN)
-    COMMON_F64_OP(COS)
-
-    // Double Precision Binary
-    COMMON_F64_OP(FYL2X)
-    COMMON_F64_OP(ATAN)
-    COMMON_F64_OP(FPREM1)
-    COMMON_F64_OP(FPREM)
-    COMMON_F64_OP(SCALE)
-
-    // SSE4.2 Fallbacks
-    case IR::OP_VPCMPESTRX:
-      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX);
-      return true;
-    case IR::OP_VPCMPISTRX:
-      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX);
-      return true;
-
-    default:
-      break;
-  }
-
-  return false;
-}
-
-
-}

External/FEXCore/Source/Interface/Core/Interpreter/FlagOps.cpp

@@ -1,21 +0,0 @@
-/*
-$info$
-tags: backend|interpreter
-$end_info$
-*/
-
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/InterpreterDefines.h"
-
-#include <cstdint>
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-DEF_OP(GetHostFlag) {
-  auto Op = IROp->C<IR::IROp_GetHostFlag>();
-  GD = (*GetSrc<uint64_t*>(Data->SSAData, Op->Value) >> Op->Flag) & 1;
-}
-#undef DEF_OP
-
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterClass.h

@@ -1,52 +0,0 @@
-#pragma once
-
-#include "Interface/Core/InternalThreadState.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-
-#include <FEXCore/Core/CPUBackend.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/fextl/string.h>
-#include <FEXCore/fextl/vector.h>
-
-namespace FEXCore::CPU {
-class Dispatcher;
-class X86DispatchGenerator;
-class Arm64DispatchGenerator;
-
-using DestMapType = fextl::vector<uint32_t>;
-
-class InterpreterCore final : public CPUBackend {
-public:
-  explicit InterpreterCore(Dispatcher *Dispatch,
-                           FEXCore::Core::InternalThreadState *Thread);
-
-  [[nodiscard]] fextl::string GetName() override { return "Interpreter"; }
-
-  [[nodiscard]] CPUBackend::CompiledCode CompileCode(uint64_t Entry,
-                                  FEXCore::IR::IRListView const *IR,
-                                  FEXCore::Core::DebugData *DebugData,
-                                  FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) override;
-
-  [[nodiscard]] void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
-
-  [[nodiscard]] bool NeedsOpDispatch() override { return true; }
-
-  static void InitializeSignalHandlers(FEXCore::Context::ContextImpl *CTX);
-
-  void ClearCache() override;
-
-private:
-  size_t BufferUsed;
-  Dispatcher *Dispatch;
-};
-
-template<typename T>
-T AtomicCompareAndSwap(T expected, T desired, T *addr);
-
-uint8_t AtomicFetchNeg(uint8_t *Addr);
-uint16_t AtomicFetchNeg(uint16_t *Addr);
-uint32_t AtomicFetchNeg(uint32_t *Addr);
-uint64_t AtomicFetchNeg(uint64_t *Addr);
-
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp

@@ -1,98 +0,0 @@
-#include "Interface/Context/Context.h"
-
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include <FEXCore/Config/Config.h>
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/MathUtils.h>
-#include <FEXCore/fextl/memory.h>
-
-#include <signal.h>
-#include <stdint.h>
-#include <utility>
-
-#include "InterpreterOps.h"
-
-#if defined(_M_X86_64)
-  #include "Interface/Core/Dispatcher/X86Dispatcher.h"
-#elif defined(_M_ARM_64)
-  #include "Interface/Core/Dispatcher/Arm64Dispatcher.h"
-#else
-  #error missing arch
-#endif
-
-static constexpr size_t INITIAL_CODE_SIZE = 1024 * 1024 * 16;
-static constexpr size_t MAX_CODE_SIZE = 1024 * 1024 * 128;
-
-namespace FEXCore::IR {
-  class IRListView;
-  class RegisterAllocationData;
-}
-
-
-namespace FEXCore::CPU {
-
-InterpreterCore::InterpreterCore(Dispatcher *Dispatcher, FEXCore::Core::InternalThreadState *Thread)
-  : CPUBackend(Thread, INITIAL_CODE_SIZE, MAX_CODE_SIZE)
-  , Dispatch(Dispatcher)
-  {
-
-  auto &Interpreter = Thread->CurrentFrame->Pointers.Interpreter;
-
-  Interpreter.FragmentExecuter = reinterpret_cast<uint64_t>(&InterpreterOps::InterpretIR);
-
-  ClearCache();
-}
-
-CPUBackend::CompiledCode InterpreterCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) {
-
-  const auto IRSize = AlignUp(IR->GetInlineSize(), 16);
-  const auto MaxSize = IRSize + Dispatcher::MaxInterpreterTrampolineSize + GDBEnabled * Dispatcher::MaxGDBPauseCheckSize;
-
-  if ((BufferUsed + MaxSize) > CurrentCodeBuffer->Size) {
-    static_cast<Context::ContextImpl*>(ThreadState->CTX)->ClearCodeCache(ThreadState);
-  }
-
-  CPUBackend::CompiledCode CodeData{};
-
-  const auto BufferStartOffset = BufferUsed;
-  CodeData.BlockBegin = CodeData.BlockEntry = CurrentCodeBuffer->Ptr + BufferStartOffset;
-
-  auto DestBuffer = CodeData.BlockBegin;
-
-  if (GDBEnabled) {
-    const auto GDBSize = Dispatch->GenerateGDBPauseCheck(DestBuffer, Entry);
-    DestBuffer += GDBSize;
-    BufferUsed += GDBSize;
-  }
-
-  const auto TrampolineSize = Dispatch->GenerateInterpreterTrampoline(DestBuffer);
-  DestBuffer += TrampolineSize;
-  BufferUsed += TrampolineSize;
-
-
-  IR->Serialize(DestBuffer);
-  DestBuffer += IRSize;
-  BufferUsed += IRSize;
-
-  CodeData.Size = BufferUsed - BufferStartOffset;
-
-  return CodeData;
-}
-
-void InterpreterCore::ClearCache() {
-  // Calling this one is needed to setup the initial CurrentCodeBuffer
-  [[maybe_unused]] auto CodeBuffer = GetEmptyCodeBuffer();
-  BufferUsed = 0;
-}
-
-fextl::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  return fextl::make_unique<InterpreterCore>(ctx->Dispatcher.get(), Thread);
-}
-
-CPUBackendFeatures GetInterpreterBackendFeatures() {
-  return CPUBackendFeatures { };
-}
-}

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.h

@@ -1,23 +0,0 @@
-#pragma once
-
-#include <FEXCore/Core/CPUBackend.h>
-#include <FEXCore/fextl/memory.h>
-
-namespace FEXCore::Context {
-class ContextImpl;
-}
-
-namespace FEXCore::Core {
-  struct InternalThreadState;
-}
-
-namespace FEXCore::CPU {
-class CPUBackend;
-struct DispatcherConfig;
-
-[[nodiscard]] fextl::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::ContextImpl *ctx,
-                                                                FEXCore::Core::InternalThreadState *Thread);
-void InitializeInterpreterSignalHandlers(FEXCore::Context::ContextImpl *CTX);
-CPUBackendFeatures GetInterpreterBackendFeatures();
-
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterDefines.h

@@ -1,184 +0,0 @@
-#pragma once
-
-#include <FEXCore/IR/IR.h>
-
-#define GD *GetDest<uint64_t*>(Data->SSAData, Node)
-#define GDP GetDest<void*>(Data->SSAData, Node)
-
-#define DO_OP(size, type, func)              \
-  case size: {                                      \
-               auto *Dst_d  = reinterpret_cast<type*>(GDP);  \
-               auto *Src1_d = reinterpret_cast<type*>(Src1); \
-               auto *Src2_d = reinterpret_cast<type*>(Src2); \
-               *Dst_d = func(*Src1_d, *Src2_d);          \
-               break;                                            \
-             }
-#define DO_SCALAR_COMPARE_OP(size, type, type2, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type2*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  Dst_d[0] = func(Src1_d[0], Src2_d[0]);          \
-  break;                                            \
-  }
-
-#define DO_VECTOR_COMPARE_OP(size, type, type2, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type2*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src1_d[i], Src2_d[i]);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_OP(size, type, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src1_d[i], Src2_d[i]);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_PAIR_OP(size, type, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src1_d[i*2], Src1_d[i*2 + 1]);          \
-    Dst_d[i+Elements] = func(Src2_d[i*2], Src2_d[i*2 + 1]);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_SCALAR_OP(size, type, func)\
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src1_d[i], *Src2_d);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_0SRC_OP(size, type, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func();          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_1SRC_OP(size, type, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type*>(Src); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src_d[i]);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_REDUCE_1SRC_OP(size, type, func, start_val)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type*>(Src); \
-  type begin = start_val;                           \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    begin = func(begin, Src_d[i]);          \
-  }                                                 \
-  Dst_d[0] = begin;                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_SAT_OP(size, type, func, min, max)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = func(Src1_d[i], Src2_d[i], min, max);          \
-  }                                                 \
-  break;                                            \
-  }
-
-#define DO_VECTOR_1SRC_2TYPE_OP(size, type, type2, func, min, max)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type2*>(Src); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = (type)func(Src_d[i], min, max);          \
-  }                                                 \
-  break;                                            \
-  }
-
-#define DO_VECTOR_1SRC_2TYPE_OP_NOSIZE(type, type2, func, min, max)              \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type2*>(Src); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = (type)func(Src_d[i], min, max);          \
-  }
-#define DO_VECTOR_1SRC_2TYPE_OP_TOP(size, type, type2, func, min, max)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type2*>(Src2); \
-  memcpy(Dst_d, Src1, Elements * sizeof(type2));\
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i+Elements] = (type)func(Src_d[i], min, max);          \
-  }                                                 \
-  break;                                            \
-  }
-
-#define DO_VECTOR_1SRC_2TYPE_OP_TOP_SRC(size, type, type2, func, min, max)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src_d = reinterpret_cast<type2*>(Src); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = (type)func(Src_d[i+Elements], min, max);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_2SRC_2TYPE_OP(size, type, type2, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type2*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type2*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = (type)func((type)Src1_d[i], (type)Src2_d[i]);          \
-  }                                                 \
-  break;                                            \
-  }
-#define DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(size, type, type2, func)              \
-  case size: {                                      \
-  auto *Dst_d  = reinterpret_cast<type*>(Tmp);  \
-  auto *Src1_d = reinterpret_cast<type2*>(Src1); \
-  auto *Src2_d = reinterpret_cast<type2*>(Src2); \
-  for (uint8_t i = 0; i < Elements; ++i) {          \
-    Dst_d[i] = (type)func((type)Src1_d[i+Elements], (type)Src2_d[i+Elements]);          \
-  }                                                 \
-  break;                                            \
-  }
-
-struct InterpVector256 {
-  __uint128_t Lower;
-  __uint128_t Upper;
-};
-
-template<typename Res>
-Res GetDest(void* SSAData, FEXCore::IR::OrderedNodeWrapper Op) {
-  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Op.ID().Value];
-  return reinterpret_cast<Res>(DstPtr);
-}
-
-template<typename Res>
-Res GetDest(void* SSAData, FEXCore::IR::NodeID Op) {
-  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Op.Value];
-  return reinterpret_cast<Res>(DstPtr);
-}
-
-
-template<typename Res>
-Res GetSrc(void* SSAData, FEXCore::IR::OrderedNodeWrapper Src) {
-  auto DstPtr = &reinterpret_cast<InterpVector256*>(SSAData)[Src.ID().Value];
-  return reinterpret_cast<Res>(DstPtr);
-}

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp

@@ -1,401 +0,0 @@
-#include "Interface/Context/Context.h"
-#include "Interface/Core/CPUID.h"
-#include "InterpreterDefines.h"
-#include "InterpreterOps.h"
-
-#include <FEXCore/Core/CPUBackend.h>
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXCore/HLE/SyscallHandler.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/Utils/BitUtils.h>
-#include <FEXCore/Utils/CompilerDefs.h>
-#include <FEXCore/Utils/LogManager.h>
-
-#include "Interface/HLE/Thunks/Thunks.h"
-
-#include <alloca.h>
-#include <algorithm>
-#include <array>
-#include <atomic>
-#include <bit>
-#include <cmath>
-#include <cstddef>
-#include <cstdint>
-#include <cstdlib>
-#include <cstring>
-#include <ctime>
-#include <limits>
-#include <memory>
-
-namespace FEXCore::CPU {
-
-using OpHandler = void (*)(IR::IROp_Header *IROp, InterpreterOps::IROpData *Data, IR::NodeID Node);
-using OpHandlerArray = std::array<OpHandler, IR::IROps::OP_LAST + 1>;
-
-constexpr OpHandlerArray InterpreterOpHandlers = [] {
-  OpHandlerArray Handlers{};
-  for (auto& Entry : Handlers) {
-    Entry = &InterpreterOps::Op_Unhandled;
-  }
-
-  #define REGISTER_OP(op, x) Handlers[IR::IROps::OP_##op] = &InterpreterOps::Op_##x
-
-  // ALU ops
-  REGISTER_OP(TRUNCELEMENTPAIR,       TruncElementPair);
-  REGISTER_OP(CONSTANT,               Constant);
-  REGISTER_OP(ENTRYPOINTOFFSET,       EntrypointOffset);
-  REGISTER_OP(INLINECONSTANT,         InlineConstant);
-  REGISTER_OP(INLINEENTRYPOINTOFFSET, InlineEntrypointOffset);
-  REGISTER_OP(CYCLECOUNTER,           CycleCounter);
-  REGISTER_OP(ADD,                    Add);
-  REGISTER_OP(SUB,                    Sub);
-  REGISTER_OP(NEG,                    Neg);
-  REGISTER_OP(ABS,                    Abs);
-  REGISTER_OP(MUL,                    Mul);
-  REGISTER_OP(UMUL,                   UMul);
-  REGISTER_OP(DIV,                    Div);
-  REGISTER_OP(UDIV,                   UDiv);
-  REGISTER_OP(REM,                    Rem);
-  REGISTER_OP(UREM,                   URem);
-  REGISTER_OP(MULH,                   MulH);
-  REGISTER_OP(UMULH,                  UMulH);
-  REGISTER_OP(OR,                     Or);
-  REGISTER_OP(AND,                    And);
-  REGISTER_OP(ANDN,                   Andn);
-  REGISTER_OP(XOR,                    Xor);
-  REGISTER_OP(LSHL,                   Lshl);
-  REGISTER_OP(LSHR,                   Lshr);
-  REGISTER_OP(ASHR,                   Ashr);
-  REGISTER_OP(ROR,                    Ror);
-  REGISTER_OP(EXTR,                   Extr);
-  REGISTER_OP(PDEP,                   PDep);
-  REGISTER_OP(PEXT,                   PExt);
-  REGISTER_OP(LDIV,                   LDiv);
-  REGISTER_OP(LUDIV,                  LUDiv);
-  REGISTER_OP(LREM,                   LRem);
-  REGISTER_OP(LUREM,                  LURem);
-  REGISTER_OP(NOT,                    Not);
-  REGISTER_OP(POPCOUNT,               Popcount);
-  REGISTER_OP(FINDLSB,                FindLSB);
-  REGISTER_OP(FINDMSB,                FindMSB);
-  REGISTER_OP(FINDTRAILINGZEROS,      FindTrailingZeros);
-  REGISTER_OP(COUNTLEADINGZEROES,     CountLeadingZeroes);
-  REGISTER_OP(REV,                    Rev);
-  REGISTER_OP(BFI,                    Bfi);
-  REGISTER_OP(BFE,                    Bfe);
-  REGISTER_OP(SBFE,                   Sbfe);
-  REGISTER_OP(SELECT,                 Select);
-  REGISTER_OP(VEXTRACTTOGPR,          VExtractToGPR);
-  REGISTER_OP(FLOAT_TOGPR_ZS,         Float_ToGPR_ZS);
-  REGISTER_OP(FLOAT_TOGPR_S,          Float_ToGPR_S);
-  REGISTER_OP(FCMP,                   FCmp);
-
-  // Atomic ops
-  REGISTER_OP(CASPAIR,                CASPair);
-  REGISTER_OP(CAS,                    CAS);
-  REGISTER_OP(ATOMICADD,              AtomicAdd);
-  REGISTER_OP(ATOMICSUB,              AtomicSub);
-  REGISTER_OP(ATOMICAND,              AtomicAnd);
-  REGISTER_OP(ATOMICOR,               AtomicOr);
-  REGISTER_OP(ATOMICXOR,              AtomicXor);
-  REGISTER_OP(ATOMICSWAP,             AtomicSwap);
-  REGISTER_OP(ATOMICFETCHADD,         AtomicFetchAdd);
-  REGISTER_OP(ATOMICFETCHSUB,         AtomicFetchSub);
-  REGISTER_OP(ATOMICFETCHAND,         AtomicFetchAnd);
-  REGISTER_OP(ATOMICFETCHOR,          AtomicFetchOr);
-  REGISTER_OP(ATOMICFETCHXOR,         AtomicFetchXor);
-  REGISTER_OP(ATOMICFETCHNEG,         AtomicFetchNeg);
-
-  // Branch ops
-  REGISTER_OP(CALLBACKRETURN,         CallbackReturn);
-  REGISTER_OP(EXITFUNCTION,           ExitFunction);
-  REGISTER_OP(JUMP,                   Jump);
-  REGISTER_OP(CONDJUMP,               CondJump);
-  REGISTER_OP(SYSCALL,                Syscall);
-  REGISTER_OP(INLINESYSCALL,          InlineSyscall);
-  REGISTER_OP(THUNK,                  Thunk);
-  REGISTER_OP(VALIDATECODE,           ValidateCode);
-  REGISTER_OP(THREADREMOVECODEENTRY,        ThreadRemoveCodeEntry);
-  REGISTER_OP(CPUID,                  CPUID);
-  REGISTER_OP(XGETBV,                 XGETBV);
-
-  // Conversion ops
-  REGISTER_OP(VINSGPR,                VInsGPR);
-  REGISTER_OP(VCASTFROMGPR,           VCastFromGPR);
-  REGISTER_OP(VDUPFROMGPR,            VDupFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_S,        Float_FromGPR_S);
-  REGISTER_OP(FLOAT_FTOF,             Float_FToF);
-  REGISTER_OP(VECTOR_STOF,            Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZS,           Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOS,            Vector_FToS);
-  REGISTER_OP(VECTOR_FTOF,            Vector_FToF);
-  REGISTER_OP(VECTOR_FTOI,            Vector_FToI);
-
-  // Flag ops
-  REGISTER_OP(GETHOSTFLAG,            GetHostFlag);
-
-  // Memory ops
-  REGISTER_OP(LOADCONTEXT,            LoadContext);
-  REGISTER_OP(STORECONTEXT,           StoreContext);
-  REGISTER_OP(LOADREGISTER,           LoadRegister);
-  REGISTER_OP(STOREREGISTER,          StoreRegister);
-  REGISTER_OP(LOADCONTEXTINDEXED,     LoadContextIndexed);
-  REGISTER_OP(STORECONTEXTINDEXED,    StoreContextIndexed);
-  REGISTER_OP(SPILLREGISTER,          SpillRegister);
-  REGISTER_OP(FILLREGISTER,           FillRegister);
-  REGISTER_OP(LOADFLAG,               LoadFlag);
-  REGISTER_OP(STOREFLAG,              StoreFlag);
-  REGISTER_OP(LOADMEM,                LoadMem);
-  REGISTER_OP(STOREMEM,               StoreMem);
-  REGISTER_OP(LOADMEMTSO,             LoadMem);
-  REGISTER_OP(STOREMEMTSO,            StoreMem);
-  REGISTER_OP(VLOADVECTORMASKED,      VLoadVectorMasked);
-  REGISTER_OP(VSTOREVECTORMASKED,     VStoreVectorMasked);
-  REGISTER_OP(MEMSET,                 MemSet);
-  REGISTER_OP(MEMCPY,                 MemCpy);
-  REGISTER_OP(CACHELINECLEAR,         CacheLineClear);
-  REGISTER_OP(CACHELINECLEAN,         CacheLineClean);
-  REGISTER_OP(CACHELINEZERO,          CacheLineZero);
-
-  // Misc ops
-  REGISTER_OP(DUMMY,                  NoOp);
-  REGISTER_OP(IRHEADER,               NoOp);
-  REGISTER_OP(CODEBLOCK,              NoOp);
-  REGISTER_OP(BEGINBLOCK,             NoOp);
-  REGISTER_OP(ENDBLOCK,               NoOp);
-  REGISTER_OP(GUESTOPCODE,            NoOp);
-  REGISTER_OP(FENCE,                  Fence);
-  REGISTER_OP(BREAK,                  Break);
-  REGISTER_OP(PHI,                    NoOp);
-  REGISTER_OP(PHIVALUE,               NoOp);
-  REGISTER_OP(PRINT,                  Print);
-  REGISTER_OP(GETROUNDINGMODE,        GetRoundingMode);
-  REGISTER_OP(SETROUNDINGMODE,        SetRoundingMode);
-  REGISTER_OP(INVALIDATEFLAGS,        NoOp);
-  REGISTER_OP(PROCESSORID,            ProcessorID);
-  REGISTER_OP(RDRAND,                 RDRAND);
-  REGISTER_OP(YIELD,                  Yield);
-
-  // Move ops
-  REGISTER_OP(EXTRACTELEMENTPAIR,     ExtractElementPair);
-  REGISTER_OP(CREATEELEMENTPAIR,      CreateElementPair);
-
-  // Vector ops
-  REGISTER_OP(VECTORZERO,             VectorZero);
-  REGISTER_OP(VECTORIMM,              VectorImm);
-  REGISTER_OP(VMOV,                   VMov);
-  REGISTER_OP(VAND,                   VAnd);
-  REGISTER_OP(VBIC,                   VBic);
-  REGISTER_OP(VOR,                    VOr);
-  REGISTER_OP(VXOR,                   VXor);
-  REGISTER_OP(VADD,                   VAdd);
-  REGISTER_OP(VSUB,                   VSub);
-  REGISTER_OP(VUQADD,                 VUQAdd);
-  REGISTER_OP(VUQSUB,                 VUQSub);
-  REGISTER_OP(VSQADD,                 VSQAdd);
-  REGISTER_OP(VSQSUB,                 VSQSub);
-  REGISTER_OP(VADDP,                  VAddP);
-  REGISTER_OP(VADDV,                  VAddV);
-  REGISTER_OP(VUMINV,                 VUMinV);
-  REGISTER_OP(VURAVG,                 VURAvg);
-  REGISTER_OP(VABS,                   VAbs);
-  REGISTER_OP(VPOPCOUNT,              VPopcount);
-  REGISTER_OP(VFADD,                  VFAdd);
-  REGISTER_OP(VFADDP,                 VFAddP);
-  REGISTER_OP(VFSUB,                  VFSub);
-  REGISTER_OP(VFMUL,                  VFMul);
-  REGISTER_OP(VFDIV,                  VFDiv);
-  REGISTER_OP(VFMIN,                  VFMin);
-  REGISTER_OP(VFMAX,                  VFMax);
-  REGISTER_OP(VFRECP,                 VFRecp);
-  REGISTER_OP(VFSQRT,                 VFSqrt);
-  REGISTER_OP(VFRSQRT,                VFRSqrt);
-  REGISTER_OP(VNEG,                   VNeg);
-  REGISTER_OP(VFNEG,                  VFNeg);
-  REGISTER_OP(VNOT,                   VNot);
-  REGISTER_OP(VUMIN,                  VUMin);
-  REGISTER_OP(VSMIN,                  VSMin);
-  REGISTER_OP(VUMAX,                  VUMax);
-  REGISTER_OP(VSMAX,                  VSMax);
-  REGISTER_OP(VZIP,                   VZip);
-  REGISTER_OP(VZIP2,                  VZip);
-  REGISTER_OP(VUNZIP,                 VUnZip);
-  REGISTER_OP(VUNZIP2,                VUnZip);
-  REGISTER_OP(VTRN,                   VTrn);
-  REGISTER_OP(VTRN2,                  VTrn);
-  REGISTER_OP(VBSL,                   VBSL);
-  REGISTER_OP(VCMPEQ,                 VCMPEQ);
-  REGISTER_OP(VCMPEQZ,                VCMPEQZ);
-  REGISTER_OP(VCMPGT,                 VCMPGT);
-  REGISTER_OP(VCMPGTZ,                VCMPGTZ);
-  REGISTER_OP(VCMPLTZ,                VCMPLTZ);
-  REGISTER_OP(VFCMPEQ,                VFCMPEQ);
-  REGISTER_OP(VFCMPNEQ,               VFCMPNEQ);
-  REGISTER_OP(VFCMPLT,                VFCMPLT);
-  REGISTER_OP(VFCMPGT,                VFCMPGT);
-  REGISTER_OP(VFCMPLE,                VFCMPLE);
-  REGISTER_OP(VFCMPORD,               VFCMPORD);
-  REGISTER_OP(VFCMPUNO,               VFCMPUNO);
-  REGISTER_OP(VUSHL,                  VUShl);
-  REGISTER_OP(VUSHR,                  VUShr);
-  REGISTER_OP(VSSHR,                  VSShr);
-  REGISTER_OP(VUSHLS,                 VUShlS);
-  REGISTER_OP(VUSHRS,                 VUShrS);
-  REGISTER_OP(VSSHRS,                 VSShrS);
-  REGISTER_OP(VINSELEMENT,            VInsElement);
-  REGISTER_OP(VDUPELEMENT,            VDupElement);
-  REGISTER_OP(VEXTR,                  VExtr);
-  REGISTER_OP(VUSHRI,                 VUShrI);
-  REGISTER_OP(VSSHRI,                 VSShrI);
-  REGISTER_OP(VSHLI,                  VShlI);
-  REGISTER_OP(VUSHRNI,                VUShrNI);
-  REGISTER_OP(VUSHRNI2,               VUShrNI2);
-  REGISTER_OP(VSXTL,                  VSXTL);
-  REGISTER_OP(VSXTL2,                 VSXTL2);
-  REGISTER_OP(VUXTL,                  VUXTL);
-  REGISTER_OP(VUXTL2,                 VUXTL2);
-  REGISTER_OP(VSQXTN,                 VSQXTN);
-  REGISTER_OP(VSQXTN2,                VSQXTN2);
-  REGISTER_OP(VSQXTUN,                VSQXTUN);
-  REGISTER_OP(VSQXTUN2,               VSQXTUN2);
-  REGISTER_OP(VUMUL,                  VUMul);
-  REGISTER_OP(VSMUL,                  VSMul);
-  REGISTER_OP(VUMULL,                 VUMull);
-  REGISTER_OP(VSMULL,                 VSMull);
-  REGISTER_OP(VUMULL2,                VUMull2);
-  REGISTER_OP(VSMULL2,                VSMull2);
-  REGISTER_OP(VUABDL,                 VUABDL);
-  REGISTER_OP(VUABDL2,                VUABDL2);
-  REGISTER_OP(VTBL1,                  VTBL1);
-  REGISTER_OP(VREV64,                 VRev64);
-  REGISTER_OP(VPCMPESTRX,             VPCMPESTRX);
-  REGISTER_OP(VPCMPISTRX,             VPCMPISTRX);
-
-  // Encryption ops
-  REGISTER_OP(VAESIMC,                AESImc);
-  REGISTER_OP(VAESENC,                AESEnc);
-  REGISTER_OP(VAESENCLAST,            AESEncLast);
-  REGISTER_OP(VAESDEC,                AESDec);
-  REGISTER_OP(VAESDECLAST,            AESDecLast);
-  REGISTER_OP(VAESKEYGENASSIST,       AESKeyGenAssist);
-  REGISTER_OP(CRC32,                  CRC32);
-  REGISTER_OP(PCLMUL,                 PCLMUL);
-
-  // F80 ops
-  REGISTER_OP(F80LOADFCW,             F80LOADFCW);
-  REGISTER_OP(F80ADD,                 F80ADD);
-  REGISTER_OP(F80SUB,                 F80SUB);
-  REGISTER_OP(F80MUL,                 F80MUL);
-  REGISTER_OP(F80DIV,                 F80DIV);
-  REGISTER_OP(F80FYL2X,               F80FYL2X);
-  REGISTER_OP(F80ATAN,                F80ATAN);
-  REGISTER_OP(F80FPREM1,              F80FPREM1);
-  REGISTER_OP(F80FPREM,               F80FPREM);
-  REGISTER_OP(F80SCALE,               F80SCALE);
-  REGISTER_OP(F80CVT,                 F80CVT);
-  REGISTER_OP(F80CVTINT,              F80CVTINT);
-  REGISTER_OP(F80CVTTO,               F80CVTTO);
-  REGISTER_OP(F80CVTTOINT,            F80CVTTOINT);
-  REGISTER_OP(F80ROUND,               F80ROUND);
-  REGISTER_OP(F80F2XM1,               F80F2XM1);
-  REGISTER_OP(F80TAN,                 F80TAN);
-  REGISTER_OP(F80SQRT,                F80SQRT);
-  REGISTER_OP(F80SIN,                 F80SIN);
-  REGISTER_OP(F80COS,                 F80COS);
-  REGISTER_OP(F80XTRACT_EXP,          F80XTRACT_EXP);
-  REGISTER_OP(F80XTRACT_SIG,          F80XTRACT_SIG);
-  REGISTER_OP(F80CMP,                 F80CMP);
-  REGISTER_OP(F80BCDLOAD,             F80BCDLOAD);
-  REGISTER_OP(F80BCDSTORE,            F80BCDSTORE);
-
-  // F64 ops
-  REGISTER_OP(F64SIN,                 F64SIN);
-  REGISTER_OP(F64COS,                 F64COS);
-  REGISTER_OP(F64TAN,                 F64TAN);
-  REGISTER_OP(F64F2XM1,               F64F2XM1);
-  REGISTER_OP(F64ATAN,                F64ATAN);
-  REGISTER_OP(F64FPREM,               F64FPREM);
-  REGISTER_OP(F64FPREM1,              F64FPREM1);
-  REGISTER_OP(F64FYL2X,               F64FYL2X);
-  REGISTER_OP(F64SCALE,               F64SCALE);
-
-  return Handlers;
-}();
-
-void InterpreterOps::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node) {
-  LOGMAN_MSG_A_FMT("Unhandled IR Op: {}", FEXCore::IR::GetName(IROp->Op));
-}
-
-void InterpreterOps::Op_NoOp(FEXCore::IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node) {
-}
-
-void InterpreterOps::InterpretIR(FEXCore::Core::CpuStateFrame *Frame, FEXCore::IR::IRListView const *CurrentIR) {
-  volatile void *StackEntry = alloca(0);
-
-  const uintptr_t ListSize = CurrentIR->GetSSACount();
-
-  static_assert(sizeof(FEXCore::IR::OrderedNode) == 16);
-
-  auto BlockEnd = CurrentIR->GetBlocks().end();
-
-  constexpr size_t ListEntrySizeInBytes = sizeof(InterpVector256);
-  const size_t SSADataSize = ListSize * ListEntrySizeInBytes;
-
-  InterpreterOps::IROpData OpData{
-    .State = Frame->Thread,
-    .CurrentEntry = Frame->State.rip,
-    .CurrentIR = CurrentIR,
-    .StackEntry = StackEntry,
-    .SSAData = alloca(SSADataSize),
-    .BlockResults = {},
-    .BlockIterator = CurrentIR->GetBlocks().begin(),
-  };
-
-  // Clear all SSAData entries to zero. Required for Zero-extend semantics
-  memset(OpData.SSAData, 0, SSADataSize);
-
-  while (1) {
-    using namespace FEXCore::IR;
-    auto [BlockNode, BlockHeader] = OpData.BlockIterator();
-    auto BlockIROp = BlockHeader->CW<IROp_CodeBlock>();
-    LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
-
-    // Reset the block results per block
-    memset(&OpData.BlockResults, 0, sizeof(OpData.BlockResults));
-
-    auto CodeBegin = CurrentIR->at(BlockIROp->Begin);
-    auto CodeLast = CurrentIR->at(BlockIROp->Last);
-
-    for (auto [CodeNode, IROp] : CurrentIR->GetCode(BlockNode)) {
-      const auto ID = CurrentIR->GetID(CodeNode);
-      const uint32_t Op = IROp->Op;
-
-      // Execute handler
-      OpHandler Handler = InterpreterOpHandlers[Op];
-
-      Handler(IROp, &OpData, ID);
-
-      if (OpData.BlockResults.Quit ||
-          OpData.BlockResults.Redo ||
-          CodeBegin == CodeLast) {
-        break;
-      }
-
-      ++CodeBegin;
-    }
-
-    // Iterator will have been set, go again
-    if (OpData.BlockResults.Redo) {
-      continue;
-    }
-
-    // If we have set to early exit or at the end block then leave
-    if (OpData.BlockResults.Quit || ++OpData.BlockIterator == BlockEnd) {
-      break;
-    }
-  }
-}
-
-}

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h

@@ -1,430 +0,0 @@
-#pragma once
-#include <stdint.h>
-
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-
-namespace FEXCore::Core {
-  struct InternalThreadState;
-}
-
-namespace FEXCore::IR {
-    class IRListView;
-    struct IROp_Header;
-}
-
-namespace FEXCore::Core{
-  struct DebugData;
-}
-
-namespace FEXCore::CPU {
-  enum FallbackABI {
-    FABI_UNKNOWN,
-    FABI_VOID_U16,
-    FABI_F80_F32,
-    FABI_F80_F64,
-    FABI_F80_I16,
-    FABI_F80_I32,
-    FABI_F32_F80,
-    FABI_F64_F80,
-    FABI_F64_F64,
-    FABI_F64_F64_F64,
-    FABI_I16_F80,
-    FABI_I32_F80,
-    FABI_I64_F80,
-    FABI_I64_F80_F80,
-    FABI_F80_F80,
-    FABI_F80_F80_F80,
-    FABI_I32_I64_I64_I128_I128_I16,
-    FABI_I32_I128_I128_I16,
-  };
-
-  struct FallbackInfo {
-    FallbackABI ABI;
-    void *fn;
-    FEXCore::Core::FallbackHandlerIndex HandlerIndex;
-  };
-
-  class InterpreterOps {
-
-    public:
-      static void InterpretIR(FEXCore::Core::CpuStateFrame *Frame, FEXCore::IR::IRListView const *IR);
-      static void FillFallbackIndexPointers(uint64_t *Info);
-      static bool GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInfo *Info);
-
-      struct IROpData {
-        FEXCore::Core::InternalThreadState *State{};
-        uint64_t CurrentEntry{};
-        FEXCore::IR::IRListView const *CurrentIR{};
-        volatile void *StackEntry{};
-        void *SSAData{};
-        struct {
-          bool Quit;
-          bool Redo;
-        } BlockResults{};
-
-        IR::NodeIterator BlockIterator{0, 0};
-      };
-
-#define DEF_OP(x) static void Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-
-  ///< Unhandled handler
-  DEF_OP(Unhandled);
-
-  ///< No-op Handler
-  DEF_OP(NoOp);
-
-  ///< ALU Ops
-  DEF_OP(TruncElementPair);
-  DEF_OP(Constant);
-  DEF_OP(EntrypointOffset);
-  DEF_OP(InlineConstant);
-  DEF_OP(InlineEntrypointOffset);
-  DEF_OP(CycleCounter);
-  DEF_OP(Add);
-  DEF_OP(Sub);
-  DEF_OP(Neg);
-  DEF_OP(Abs);
-  DEF_OP(Mul);
-  DEF_OP(UMul);
-  DEF_OP(Div);
-  DEF_OP(UDiv);
-  DEF_OP(Rem);
-  DEF_OP(URem);
-  DEF_OP(MulH);
-  DEF_OP(UMulH);
-  DEF_OP(Or);
-  DEF_OP(And);
-  DEF_OP(Andn);
-  DEF_OP(Xor);
-  DEF_OP(Lshl);
-  DEF_OP(Lshr);
-  DEF_OP(Ashr);
-  DEF_OP(Rol);
-  DEF_OP(Ror);
-  DEF_OP(Extr);
-  DEF_OP(PDep);
-  DEF_OP(PExt);
-  DEF_OP(LDiv);
-  DEF_OP(LUDiv);
-  DEF_OP(LRem);
-  DEF_OP(LURem);
-  DEF_OP(Zext);
-  DEF_OP(Not);
-  DEF_OP(Popcount);
-  DEF_OP(FindLSB);
-  DEF_OP(FindMSB);
-  DEF_OP(FindTrailingZeros);
-  DEF_OP(CountLeadingZeroes);
-  DEF_OP(Rev);
-  DEF_OP(Bfi);
-  DEF_OP(Bfe);
-  DEF_OP(Sbfe);
-  DEF_OP(Select);
-  DEF_OP(VExtractToGPR);
-  DEF_OP(Float_ToGPR_ZU);
-  DEF_OP(Float_ToGPR_ZS);
-  DEF_OP(Float_ToGPR_S);
-  DEF_OP(FCmp);
-
-  ///< Atomic ops
-  DEF_OP(CASPair);
-  DEF_OP(CAS);
-  DEF_OP(AtomicAdd);
-  DEF_OP(AtomicSub);
-  DEF_OP(AtomicAnd);
-  DEF_OP(AtomicOr);
-  DEF_OP(AtomicXor);
-  DEF_OP(AtomicSwap);
-  DEF_OP(AtomicFetchAdd);
-  DEF_OP(AtomicFetchSub);
-  DEF_OP(AtomicFetchAnd);
-  DEF_OP(AtomicFetchOr);
-  DEF_OP(AtomicFetchXor);
-  DEF_OP(AtomicFetchNeg);
-
-  ///< Branch ops
-  DEF_OP(CallbackReturn);
-  DEF_OP(ExitFunction);
-  DEF_OP(Jump);
-  DEF_OP(CondJump);
-  DEF_OP(Syscall);
-  DEF_OP(InlineSyscall);
-  DEF_OP(Thunk);
-  DEF_OP(ValidateCode);
-  DEF_OP(ThreadRemoveCodeEntry);
-  DEF_OP(CPUID);
-  DEF_OP(XGETBV);
-
-  ///< Conversion ops
-  DEF_OP(VInsGPR);
-  DEF_OP(VCastFromGPR);
-  DEF_OP(VDupFromGPR);
-  DEF_OP(Float_FromGPR_S);
-  DEF_OP(Float_FToF);
-  DEF_OP(Vector_SToF);
-  DEF_OP(Vector_FToZS);
-  DEF_OP(Vector_FToS);
-  DEF_OP(Vector_FToF);
-  DEF_OP(Vector_FToI);
-
-  ///< Flag ops
-  DEF_OP(GetHostFlag);
-
-  ///< Memory ops
-  DEF_OP(LoadContext);
-  DEF_OP(StoreContext);
-  DEF_OP(LoadRegister);
-  DEF_OP(StoreRegister);
-  DEF_OP(LoadContextIndexed);
-  DEF_OP(StoreContextIndexed);
-  DEF_OP(SpillRegister);
-  DEF_OP(FillRegister);
-  DEF_OP(LoadFlag);
-  DEF_OP(StoreFlag);
-  DEF_OP(LoadMem);
-  DEF_OP(StoreMem);
-  DEF_OP(VLoadVectorMasked);
-  DEF_OP(VStoreVectorMasked);
-  DEF_OP(MemSet);
-  DEF_OP(MemCpy);
-  DEF_OP(CacheLineClear);
-  DEF_OP(CacheLineClean);
-  DEF_OP(CacheLineZero);
-
-  ///< Misc ops
-  DEF_OP(EndBlock);
-  DEF_OP(Fence);
-  DEF_OP(Break);
-  DEF_OP(Phi);
-  DEF_OP(PhiValue);
-  DEF_OP(Print);
-  DEF_OP(GetRoundingMode);
-  DEF_OP(SetRoundingMode);
-  DEF_OP(ProcessorID);
-  DEF_OP(RDRAND);
-  DEF_OP(Yield);
-
-  ///< Move ops
-  DEF_OP(ExtractElementPair);
-  DEF_OP(CreateElementPair);
-  DEF_OP(Mov);
-
-  ///< Vector ops
-  DEF_OP(VectorZero);
-  DEF_OP(VectorImm);
-  DEF_OP(VMov);
-  DEF_OP(VAnd);
-  DEF_OP(VBic);
-  DEF_OP(VOr);
-  DEF_OP(VXor);
-  DEF_OP(VAdd);
-  DEF_OP(VSub);
-  DEF_OP(VUQAdd);
-  DEF_OP(VUQSub);
-  DEF_OP(VSQAdd);
-  DEF_OP(VSQSub);
-  DEF_OP(VAddP);
-  DEF_OP(VAddV);
-  DEF_OP(VUMinV);
-  DEF_OP(VURAvg);
-  DEF_OP(VAbs);
-  DEF_OP(VPopcount);
-  DEF_OP(VFAdd);
-  DEF_OP(VFAddP);
-  DEF_OP(VFSub);
-  DEF_OP(VFMul);
-  DEF_OP(VFDiv);
-  DEF_OP(VFMin);
-  DEF_OP(VFMax);
-  DEF_OP(VFRecp);
-  DEF_OP(VFSqrt);
-  DEF_OP(VFRSqrt);
-  DEF_OP(VNeg);
-  DEF_OP(VFNeg);
-  DEF_OP(VNot);
-  DEF_OP(VUMin);
-  DEF_OP(VSMin);
-  DEF_OP(VUMax);
-  DEF_OP(VSMax);
-  DEF_OP(VZip);
-  DEF_OP(VUnZip);
-  DEF_OP(VTrn);
-  DEF_OP(VBSL);
-  DEF_OP(VCMPEQ);
-  DEF_OP(VCMPEQZ);
-  DEF_OP(VCMPGT);
-  DEF_OP(VCMPGTZ);
-  DEF_OP(VCMPLTZ);
-  DEF_OP(VFCMPEQ);
-  DEF_OP(VFCMPNEQ);
-  DEF_OP(VFCMPLT);
-  DEF_OP(VFCMPGT);
-  DEF_OP(VFCMPLE);
-  DEF_OP(VFCMPORD);
-  DEF_OP(VFCMPUNO);
-  DEF_OP(VUShl);
-  DEF_OP(VUShr);
-  DEF_OP(VSShr);
-  DEF_OP(VUShlS);
-  DEF_OP(VUShrS);
-  DEF_OP(VSShrS);
-  DEF_OP(VInsElement);
-  DEF_OP(VDupElement);
-  DEF_OP(VExtr);
-  DEF_OP(VUShrI);
-  DEF_OP(VSShrI);
-  DEF_OP(VShlI);
-  DEF_OP(VUShrNI);
-  DEF_OP(VUShrNI2);
-  DEF_OP(VSXTL);
-  DEF_OP(VSXTL2);
-  DEF_OP(VUXTL);
-  DEF_OP(VUXTL2);
-  DEF_OP(VSQXTN);
-  DEF_OP(VSQXTN2);
-  DEF_OP(VSQXTUN);
-  DEF_OP(VSQXTUN2);
-  DEF_OP(VUMul);
-  DEF_OP(VUMull);
-  DEF_OP(VSMul);
-  DEF_OP(VSMull);
-  DEF_OP(VUMull2);
-  DEF_OP(VSMull2);
-  DEF_OP(VUABDL);
-  DEF_OP(VUABDL2);
-  DEF_OP(VTBL1);
-  DEF_OP(VRev64);
-  DEF_OP(VPCMPESTRX);
-  DEF_OP(VPCMPISTRX);
-
-  ///< Encryption ops
-  DEF_OP(AESImc);
-  DEF_OP(AESEnc);
-  DEF_OP(AESEncLast);
-  DEF_OP(AESDec);
-  DEF_OP(AESDecLast);
-  DEF_OP(AESKeyGenAssist);
-  DEF_OP(CRC32);
-  DEF_OP(PCLMUL);
-
-  ///< F80 ops
-  DEF_OP(F80LOADFCW);
-  DEF_OP(F80ADD);
-  DEF_OP(F80SUB);
-  DEF_OP(F80MUL);
-  DEF_OP(F80DIV);
-  DEF_OP(F80FYL2X);
-  DEF_OP(F80ATAN);
-  DEF_OP(F80FPREM1);
-  DEF_OP(F80FPREM);
-  DEF_OP(F80SCALE);
-  DEF_OP(F80CVT);
-  DEF_OP(F80CVTINT);
-  DEF_OP(F80CVTTO);
-  DEF_OP(F80CVTTOINT);
-  DEF_OP(F80ROUND);
-  DEF_OP(F80F2XM1);
-  DEF_OP(F80TAN);
-  DEF_OP(F80SQRT);
-  DEF_OP(F80SIN);
-  DEF_OP(F80COS);
-  DEF_OP(F80XTRACT_EXP);
-  DEF_OP(F80XTRACT_SIG);
-  DEF_OP(F80CMP);
-  DEF_OP(F80BCDLOAD);
-  DEF_OP(F80BCDSTORE);
-
-  //< F64 ops
-  DEF_OP(F64SIN);
-  DEF_OP(F64COS);
-  DEF_OP(F64TAN);
-  DEF_OP(F64F2XM1);
-  DEF_OP(F64ATAN);
-  DEF_OP(F64FPREM);
-  DEF_OP(F64FPREM1);
-  DEF_OP(F64FYL2X);
-  DEF_OP(F64SCALE);
-#undef DEF_OP
-  template<typename unsigned_type, typename signed_type, typename float_type>
-  [[nodiscard]] static bool IsConditionTrue(uint8_t Cond, uint64_t Src1, uint64_t Src2) {
-    bool CompResult = false;
-    if constexpr (sizeof(unsigned_type) == 16) {
-      LOGMAN_THROW_A_FMT(Cond != FEXCore::IR::COND_FLU &&
-        Cond != FEXCore::IR::COND_FGE &&
-        Cond != FEXCore::IR::COND_FLEU &&
-        Cond != FEXCore::IR::COND_FGT &&
-        Cond != FEXCore::IR::COND_FU &&
-        Cond != FEXCore::IR::COND_FNU, "Unsupported comparison for 128-bit floats");
-    }
-
-    switch (Cond) {
-      case FEXCore::IR::COND_EQ:
-        CompResult = static_cast<unsigned_type>(Src1) == static_cast<unsigned_type>(Src2);
-        break;
-      case FEXCore::IR::COND_NEQ:
-        CompResult = static_cast<unsigned_type>(Src1) != static_cast<unsigned_type>(Src2);
-        break;
-      case FEXCore::IR::COND_SGE:
-        CompResult = static_cast<signed_type>(Src1) >= static_cast<signed_type>(Src2);
-        break;
-      case FEXCore::IR::COND_SLT:
-        CompResult = static_cast<signed_type>(Src1) < static_cast<signed_type>(Src2);
-        break;
-      case FEXCore::IR::COND_SGT:
-        CompResult = static_cast<signed_type>(Src1) > static_cast<signed_type>(Src2);
-        break;
-      case FEXCore::IR::COND_SLE:
-        CompResult = static_cast<signed_type>(Src1) <= static_cast<signed_type>(Src2);
-        break;
-      case FEXCore::IR::COND_UGE:
-        CompResult = static_cast<unsigned_type>(Src1) >= static_cast<unsigned_type>(Src2);
-        break;
-      case FEXCore::IR::COND_ULT:
-        CompResult = static_cast<unsigned_type>(Src1) < static_cast<unsigned_type>(Src2);
-        break;
-      case FEXCore::IR::COND_UGT:
-        CompResult = static_cast<unsigned_type>(Src1) > static_cast<unsigned_type>(Src2);
-        break;
-      case FEXCore::IR::COND_ULE:
-        CompResult = static_cast<unsigned_type>(Src1) <= static_cast<unsigned_type>(Src2);
-        break;
-
-      case FEXCore::IR::COND_FLU:
-        CompResult = reinterpret_cast<float_type&>(Src1) < reinterpret_cast<float_type&>(Src2) || (std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
-        break;
-      case FEXCore::IR::COND_FGE:
-        CompResult = reinterpret_cast<float_type&>(Src1) >= reinterpret_cast<float_type&>(Src2) && !(std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
-        break;
-      case FEXCore::IR::COND_FLEU:
-        CompResult = reinterpret_cast<float_type&>(Src1) <= reinterpret_cast<float_type&>(Src2) || (std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
-        break;
-      case FEXCore::IR::COND_FGT:
-        CompResult = reinterpret_cast<float_type&>(Src1) > reinterpret_cast<float_type&>(Src2) && !(std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
-        break;
-      case FEXCore::IR::COND_FU:
-        CompResult = (std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
-        break;
-      case FEXCore::IR::COND_FNU:
-        CompResult = !(std::isnan(reinterpret_cast<float_type&>(Src1)) || std::isnan(reinterpret_cast<float_type&>(Src2)));
-        break;
-      case FEXCore::IR::COND_MI:
-      case FEXCore::IR::COND_PL:
-      case FEXCore::IR::COND_VS:
-      case FEXCore::IR::COND_VC:
-      default:
-        LOGMAN_MSG_A_FMT("Unsupported compare type");
-        break;
-    }
-
-    return CompResult;
-  }
-
-  static uint8_t GetOpSize(FEXCore::IR::IRListView const *CurrentIR, IR::OrderedNodeWrapper Node) {
-    auto IROp = CurrentIR->GetOp<FEXCore::IR::IROp_Header>(Node);
-    return IROp->Size;
-  }
-
-  };
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/MemoryOps.cpp

@@ -1,699 +0,0 @@
-/*
-$info$
-tags: backend|interpreter
-$end_info$
-*/
-
-#include "Interface/Core/CPUID.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/InterpreterDefines.h"
-
-#include <cstdint>
-
-namespace FEXCore::CPU {
-static inline void CacheLineFlush(char *Addr) {
-#ifdef _M_X86_64
-  __asm volatile (
-    "clflush (%[Addr]);"
-    :: [Addr] "r" (Addr)
-    : "memory");
-#else
-  __builtin___clear_cache(Addr, Addr+64);
-#endif
-}
-
-static inline void CacheLineClean(char *Addr) {
-#ifdef _M_X86_64
-  __asm volatile (
-    "clwb (%[Addr]);"
-    :: [Addr] "r" (Addr)
-    : "memory");
-#elif _M_ARM_64
-  __asm volatile (
-    "dc cvac, %[Addr]"
-    :: [Addr] "r" (Addr)
-    : "memory");
-#else
-    LOGMAN_THROW_A_FMT("Unsupported architecture with cacheline clean");
-#endif
-}
-
-#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-DEF_OP(LoadContext) {
-  const auto Op = IROp->C<IR::IROp_LoadContext>();
-  const auto OpSize = IROp->Size;
-
-  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  const auto Src = ContextPtr + Op->Offset;
-
-  #define LOAD_CTX(x, y) \
-    case x: { \
-      y const *MemData = reinterpret_cast<y const*>(Src); \
-      GD = *MemData; \
-      break; \
-    }
-
-  switch (OpSize) {
-    LOAD_CTX(1, uint8_t)
-    LOAD_CTX(2, uint16_t)
-    LOAD_CTX(4, uint32_t)
-    LOAD_CTX(8, uint64_t)
-    case 16:
-    case 32: {
-      void const *MemData = reinterpret_cast<void const*>(Src);
-      memcpy(GDP, MemData, OpSize);
-      break;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
-      break;
-  }
-  #undef LOAD_CTX
-}
-
-DEF_OP(StoreContext) {
-  const auto Op = IROp->C<IR::IROp_StoreContext>();
-  const auto OpSize = IROp->Size;
-
-  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  const auto Dst = ContextPtr + Op->Offset;
-
-  void *MemData = reinterpret_cast<void*>(Dst);
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Value);
-  memcpy(MemData, Src, OpSize);
-}
-
-DEF_OP(LoadRegister) {
-  const auto Op = IROp->C<IR::IROp_LoadRegister>();
-  const auto OpSize = IROp->Size;
-
-  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  const auto Src = ContextPtr + Op->Offset;
-
-  #define LOAD_CTX(x, y) \
-    case x: { \
-      y const *MemData = reinterpret_cast<y const*>(Src); \
-      GD = *MemData; \
-      break; \
-    }
-
-  switch (OpSize) {
-    LOAD_CTX(1, uint8_t)
-    LOAD_CTX(2, uint16_t)
-    LOAD_CTX(4, uint32_t)
-    LOAD_CTX(8, uint64_t)
-    case 16:
-    case 32: {
-      void const *MemData = reinterpret_cast<void const*>(Src);
-      memcpy(GDP, MemData, OpSize);
-      break;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
-      break;
-  }
-  #undef LOAD_CTX
-}
-
-DEF_OP(StoreRegister) {
-  const auto Op = IROp->C<IR::IROp_StoreRegister>();
-  const auto OpSize = IROp->Size;
-
-  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  const auto Dst = ContextPtr + Op->Offset;
-
-  void *MemData = reinterpret_cast<void*>(Dst);
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Value);
-  memcpy(MemData, Src, OpSize);
-}
-
-DEF_OP(LoadContextIndexed) {
-  const auto Op = IROp->C<IR::IROp_LoadContextIndexed>();
-  const auto OpSize = IROp->Size;
-
-  const auto Index = *GetSrc<uint64_t*>(Data->SSAData, Op->Index);
-
-  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  const auto Src = ContextPtr + Op->BaseOffset + (Index * Op->Stride);
-
-  #define LOAD_CTX(x, y) \
-    case x: { \
-      y const *MemData = reinterpret_cast<y const*>(Src); \
-      GD = *MemData; \
-      break; \
-    }
-
-  switch (OpSize) {
-    LOAD_CTX(1, uint8_t)
-    LOAD_CTX(2, uint16_t)
-    LOAD_CTX(4, uint32_t)
-    LOAD_CTX(8, uint64_t)
-    case 16:
-    case 32: {
-      void const *MemData = reinterpret_cast<void const*>(Src);
-      memcpy(GDP, MemData, OpSize);
-      break;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", OpSize);
-      break;
-  }
-  #undef LOAD_CTX
-}
-
-DEF_OP(StoreContextIndexed) {
-  const auto Op = IROp->C<IR::IROp_StoreContextIndexed>();
-  const auto OpSize = IROp->Size;
-
-  const auto Index = *GetSrc<uint64_t*>(Data->SSAData, Op->Index);
-
-  const auto ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  const auto Dst = ContextPtr + Op->BaseOffset + (Index * Op->Stride);
-
-  void *MemData = reinterpret_cast<void*>(Dst);
-  void *Src = GetSrc<void*>(Data->SSAData, Op->Value);
-  memcpy(MemData, Src, OpSize);
-}
-
-DEF_OP(SpillRegister) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
-DEF_OP(FillRegister) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
-DEF_OP(LoadFlag) {
-  auto Op = IROp->C<IR::IROp_LoadFlag>();
-
-  uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  ContextPtr += offsetof(FEXCore::Core::CPUState, flags[0]);
-  ContextPtr += Op->Flag;
-
-  if (Op->Flag == 24 /* NZCV */) {
-    uint32_t const *MemData = reinterpret_cast<uint32_t const*>(ContextPtr);
-    GD = *MemData;
-  } else {
-    uint8_t const *MemData = reinterpret_cast<uint8_t const*>(ContextPtr);
-    GD = *MemData;
-  }
-}
-
-DEF_OP(StoreFlag) {
-  auto Op = IROp->C<IR::IROp_StoreFlag>();
-  uint32_t Arg = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
-
-  uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
-  ContextPtr += offsetof(FEXCore::Core::CPUState, flags[0]);
-  ContextPtr += Op->Flag;
-
-  if (Op->Flag == 24 /* NZCV */) {
-    uint32_t *MemData = reinterpret_cast<uint32_t*>(ContextPtr);
-    *MemData = Arg;
-  } else {
-    uint8_t *MemData = reinterpret_cast<uint8_t*>(ContextPtr);
-    *MemData = Arg;
-  }
-}
-
-DEF_OP(LoadMem) {
-  const auto Op = IROp->C<IR::IROp_LoadMem>();
-  const auto OpSize = IROp->Size;
-
-  uint8_t const *MemData = *GetSrc<uint8_t const**>(Data->SSAData, Op->Addr);
-
-  if (!Op->Offset.IsInvalid()) {
-    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
-
-    switch(Op->OffsetType.Val) {
-      case IR::MEM_OFFSET_SXTX.Val: MemData +=  Offset; break;
-      case IR::MEM_OFFSET_UXTW.Val: MemData += (uint32_t)Offset; break;
-      case IR::MEM_OFFSET_SXTW.Val: MemData += (int32_t)Offset; break;
-    }
-  }
-
-  memset(GDP, 0, Core::CPUState::XMM_AVX_REG_SIZE);
-  switch (OpSize) {
-    case 1: {
-      auto D = reinterpret_cast<const std::atomic<uint8_t>*>(MemData);
-      GD = D->load();
-      break;
-    }
-    case 2: {
-      auto D = reinterpret_cast<const std::atomic<uint16_t>*>(MemData);
-      GD = D->load();
-      break;
-    }
-    case 4: {
-      auto D = reinterpret_cast<const std::atomic<uint32_t>*>(MemData);
-      GD = D->load();
-      break;
-    }
-    case 8: {
-      auto D = reinterpret_cast<const std::atomic<uint64_t>*>(MemData);
-      GD = D->load();
-      break;
-    }
-    default:
-      memcpy(GDP, MemData, OpSize);
-      break;
-  }
-}
-
-DEF_OP(StoreMem) {
-  const auto Op = IROp->C<IR::IROp_StoreMem>();
-  const auto OpSize = IROp->Size;
-
-  uint8_t *MemData = *GetSrc<uint8_t **>(Data->SSAData, Op->Addr);
-
-  if (!Op->Offset.IsInvalid()) {
-    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
-
-    switch(Op->OffsetType.Val) {
-      case IR::MEM_OFFSET_SXTX.Val: MemData +=  Offset; break;
-      case IR::MEM_OFFSET_UXTW.Val: MemData += (uint32_t)Offset; break;
-      case IR::MEM_OFFSET_SXTW.Val: MemData += (int32_t)Offset; break;
-    }
-  }
-  switch (OpSize) {
-    case 1: {
-      reinterpret_cast<std::atomic<uint8_t>*>(MemData)->store(*GetSrc<uint8_t*>(Data->SSAData, Op->Value));
-      break;
-    }
-    case 2: {
-      reinterpret_cast<std::atomic<uint16_t>*>(MemData)->store(*GetSrc<uint16_t*>(Data->SSAData, Op->Value));
-      break;
-    }
-    case 4: {
-      reinterpret_cast<std::atomic<uint32_t>*>(MemData)->store(*GetSrc<uint32_t*>(Data->SSAData, Op->Value));
-      break;
-    }
-    case 8: {
-      reinterpret_cast<std::atomic<uint64_t>*>(MemData)->store(*GetSrc<uint64_t*>(Data->SSAData, Op->Value));
-      break;
-    }
-
-    default:
-      memcpy(MemData, GetSrc<void*>(Data->SSAData, Op->Value), OpSize);
-      break;
-  }
-}
-
-DEF_OP(VLoadVectorMasked) {
-  const auto Op = IROp->C<IR::IROp_VLoadVectorMasked>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = IROp->ElementSize;
-  const auto NumElements = OpSize / ElementSize;
-
-  const auto *MemData = *GetSrc<uint8_t const**>(Data->SSAData, Op->Addr);
-  const auto *Mask = GetSrc<uint8_t const*>(Data->SSAData, Op->Mask);
-
-  const auto SetElements = [NumElements]<typename T>(void* Dst, const T* MaskValues, const T* MemoryData) {
-    const auto SignBit = 1ULL << ((sizeof(T) * 8) - 1);
-    for (size_t i = 0; i < NumElements; i++) {
-      if ((MaskValues[i] & SignBit) != 0) {
-        std::memcpy(static_cast<uint8_t*>(Dst) + (i * sizeof(T)), MemoryData + i, sizeof(T));
-      }
-    }
-  };
-
-  if (!Op->Offset.IsInvalid()) {
-    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
-
-    switch(Op->OffsetType.Val) {
-      case IR::MEM_OFFSET_SXTX.Val: MemData +=  Offset; break;
-      case IR::MEM_OFFSET_UXTW.Val: MemData += (uint32_t)Offset; break;
-      case IR::MEM_OFFSET_SXTW.Val: MemData += (int32_t)Offset; break;
-    }
-  }
-
-  memset(GDP, 0, Core::CPUState::XMM_AVX_REG_SIZE);
-  switch (ElementSize) {
-    case 1: {
-      SetElements(GDP, Mask, MemData);
-      return;
-    }
-    case 2: {
-      SetElements(GDP,
-                  reinterpret_cast<const uint16_t*>(Mask),
-                  reinterpret_cast<const uint16_t*>(MemData));
-      return;
-    }
-    case 4: {
-      SetElements(GDP,
-                  reinterpret_cast<const uint32_t*>(Mask),
-                  reinterpret_cast<const uint32_t*>(MemData));
-      return;
-    }
-    case 8: {
-      SetElements(GDP,
-                  reinterpret_cast<const uint64_t*>(Mask),
-                  reinterpret_cast<const uint64_t*>(MemData));
-      return;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled VLoadVectorMasked element size: {}", ElementSize);
-      return;
-  }
-}
-
-DEF_OP(VStoreVectorMasked) {
-  const auto Op = IROp->C<IR::IROp_VStoreVectorMasked>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = IROp->ElementSize;
-  const auto NumElements = OpSize / ElementSize;
-
-  auto *Dst = *GetSrc<uint8_t**>(Data->SSAData, Op->Addr);
-  const auto *RegData = GetSrc<uint8_t const*>(Data->SSAData, Op->Data);
-  const auto *Mask = GetSrc<uint8_t const*>(Data->SSAData, Op->Mask);
-
-  const auto SetElements = [NumElements]<typename T>(void* Dst, const T* MaskValues, const T* DataVals) {
-    const auto SignBit = 1ULL << ((sizeof(T) * 8) - 1);
-    for (size_t i = 0; i < NumElements; i++) {
-      if ((MaskValues[i] & SignBit) != 0) {
-        std::memcpy(static_cast<uint8_t*>(Dst) + (i * sizeof(T)), DataVals + i, sizeof(T));
-      }
-    }
-  };
-
-  if (!Op->Offset.IsInvalid()) {
-    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
-
-    switch(Op->OffsetType.Val) {
-      case IR::MEM_OFFSET_SXTX.Val: Dst +=  Offset; break;
-      case IR::MEM_OFFSET_UXTW.Val: Dst += (uint32_t)Offset; break;
-      case IR::MEM_OFFSET_SXTW.Val: Dst += (int32_t)Offset; break;
-    }
-  }
-
-  switch (ElementSize) {
-    case 1: {
-      SetElements(Dst, Mask, RegData);
-      return;
-    }
-    case 2: {
-      SetElements(Dst,
-                  reinterpret_cast<const uint16_t*>(Mask),
-                  reinterpret_cast<const uint16_t*>(RegData));
-      return;
-    }
-    case 4: {
-      SetElements(Dst,
-                  reinterpret_cast<const uint32_t*>(Mask),
-                  reinterpret_cast<const uint32_t*>(RegData));
-      return;
-    }
-    case 8: {
-      SetElements(Dst,
-                  reinterpret_cast<const uint64_t*>(Mask),
-                  reinterpret_cast<const uint64_t*>(RegData));
-      return;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled VStoreVectorMasked element size: {}", ElementSize);
-      return;
-  }
-}
-
-DEF_OP(MemSet) {
-  const auto Op = IROp->C<IR::IROp_MemSet>();
-  const int32_t Size = Op->Size;
-
-  char *MemData = *GetSrc<char **>(Data->SSAData, Op->Addr);
-  uint64_t MemPrefix{};
-  if (!Op->Prefix.IsInvalid()) {
-    MemPrefix = *GetSrc<uint64_t*>(Data->SSAData, Op->Prefix);
-  }
-
-  const auto Value = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-  const auto Length = *GetSrc<uint64_t*>(Data->SSAData, Op->Length);
-  const auto Direction = *GetSrc<uint8_t*>(Data->SSAData, Op->Direction);
-
-  auto MemSetElements = [](auto* Memory, uint64_t Value, size_t Length) {
-    for (size_t i = 0; i < Length; ++i) {
-      Memory[i] = Value;
-    }
-  };
-
-  auto MemSetElementsInverse = [](auto* Memory, uint64_t Value, size_t Length) {
-    for (size_t i = 0; i < Length; ++i) {
-      Memory[-i] = Value;
-    }
-  };
-
-  if (Direction == 0) { // Forward
-    if (Op->IsAtomic) {
-      switch (Size) {
-        case 1:
-          MemSetElements(reinterpret_cast<std::atomic<uint8_t>*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 2:
-          MemSetElements(reinterpret_cast<std::atomic<uint16_t>*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 4:
-          MemSetElements(reinterpret_cast<std::atomic<uint32_t>*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 8:
-          MemSetElements(reinterpret_cast<std::atomic<uint64_t>*>(MemData + MemPrefix), Value, Length);
-          break;
-        default:
-          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
-          break;
-      }
-    }
-    else {
-      switch (Size) {
-        case 1:
-          MemSetElements(reinterpret_cast<uint8_t*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 2:
-          MemSetElements(reinterpret_cast<uint16_t*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 4:
-          MemSetElements(reinterpret_cast<uint32_t*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 8:
-          MemSetElements(reinterpret_cast<uint64_t*>(MemData + MemPrefix), Value, Length);
-          break;
-        default:
-          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
-          break;
-      }
-    }
-    GD = reinterpret_cast<uint64_t>(MemData + (Length * Size));
-  }
-  else { // Backward
-    if (Op->IsAtomic) {
-      switch (Size) {
-        case 1:
-          MemSetElementsInverse(reinterpret_cast<std::atomic<uint8_t>*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 2:
-          MemSetElementsInverse(reinterpret_cast<std::atomic<uint16_t>*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 4:
-          MemSetElementsInverse(reinterpret_cast<std::atomic<uint32_t>*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 8:
-          MemSetElementsInverse(reinterpret_cast<std::atomic<uint64_t>*>(MemData + MemPrefix), Value, Length);
-          break;
-        default:
-          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
-          break;
-      }
-    }
-    else {
-      switch (Size) {
-        case 1:
-          MemSetElementsInverse(reinterpret_cast<uint8_t*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 2:
-          MemSetElementsInverse(reinterpret_cast<uint16_t*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 4:
-          MemSetElementsInverse(reinterpret_cast<uint32_t*>(MemData + MemPrefix), Value, Length);
-          break;
-        case 8:
-          MemSetElementsInverse(reinterpret_cast<uint64_t*>(MemData + MemPrefix), Value, Length);
-          break;
-        default:
-          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
-          break;
-      }
-    }
-    GD = reinterpret_cast<uint64_t>(MemData - (Length * Size));
-  }
-}
-
-DEF_OP(MemCpy) {
-  const auto Op = IROp->C<IR::IROp_MemCpy>();
-  const int32_t Size = Op->Size;
-
-  uint64_t *DstPtr = GetDest<uint64_t*>(Data->SSAData, Node);
-
-  char *MemDataDest = *GetSrc<char **>(Data->SSAData, Op->AddrDest);
-  char *MemDataSrc = *GetSrc<char **>(Data->SSAData, Op->AddrSrc);
-
-  uint64_t DestPrefix{};
-  uint64_t SrcPrefix{};
-  if (!Op->PrefixDest.IsInvalid()) {
-    DestPrefix = *GetSrc<uint64_t*>(Data->SSAData, Op->PrefixDest);
-
-  }
-  if (!Op->PrefixSrc.IsInvalid()) {
-    SrcPrefix = *GetSrc<uint64_t*>(Data->SSAData, Op->PrefixSrc);
-  }
-
-  const auto Length = *GetSrc<uint64_t*>(Data->SSAData, Op->Length);
-  const auto Direction = *GetSrc<uint8_t*>(Data->SSAData, Op->Direction);
-
-  auto MemSetElementsAtomic = [](auto* MemDst, auto* MemSrc, size_t Length) {
-    for (size_t i = 0; i < Length; ++i) {
-      MemDst[i].store(MemSrc[i].load());
-    }
-  };
-
-  auto MemSetElementsAtomicInverse = [](auto* MemDst, auto* MemSrc, size_t Length) {
-    for (size_t i = 0; i < Length; ++i) {
-      MemDst[-i].store(MemSrc[-i].load());
-    }
-  };
-
-  auto MemSetElements = [](auto* MemDst, auto* MemSrc, size_t Length) {
-    for (size_t i = 0; i < Length; ++i) {
-      MemDst[i] = MemSrc[i];
-    }
-  };
-
-  auto MemSetElementsInverse = [](auto* MemDst, auto* MemSrc, size_t Length) {
-    for (size_t i = 0; i < Length; ++i) {
-      MemDst[-i] = MemSrc[-i];
-    }
-  };
-
-  if (Direction == 0) { // Forward
-    if (Op->IsAtomic) {
-      switch (Size) {
-        case 1:
-          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint8_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint8_t>*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 2:
-          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint16_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint16_t>*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 4:
-          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint32_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint32_t>*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 8:
-          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint64_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint64_t>*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        default:
-          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
-          break;
-      }
-    }
-    else {
-      switch (Size) {
-        case 1:
-          MemSetElements(reinterpret_cast<uint8_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint8_t*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 2:
-          MemSetElements(reinterpret_cast<uint16_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint16_t*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 4:
-          MemSetElements(reinterpret_cast<uint32_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint32_t*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 8:
-          MemSetElements(reinterpret_cast<uint64_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint64_t*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        default:
-          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
-          break;
-      }
-    }
-    DstPtr[0] = reinterpret_cast<uint64_t>(MemDataDest + (Length * Size));
-    DstPtr[1] = reinterpret_cast<uint64_t>(MemDataSrc + (Length * Size));
-  }
-  else { // Backward
-    if (Op->IsAtomic) {
-      switch (Size) {
-        case 1:
-          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint8_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint8_t>*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 2:
-          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint16_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint16_t>*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 4:
-          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint32_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint32_t>*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 8:
-          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint64_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint64_t>*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        default:
-          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
-          break;
-      }
-    }
-    else {
-      switch (Size) {
-        case 1:
-          MemSetElementsInverse(reinterpret_cast<uint8_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint8_t*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 2:
-          MemSetElementsInverse(reinterpret_cast<uint16_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint16_t*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 4:
-          MemSetElementsInverse(reinterpret_cast<uint32_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint32_t*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        case 8:
-          MemSetElementsInverse(reinterpret_cast<uint64_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint64_t*>(MemDataSrc + SrcPrefix), Length);
-          break;
-        default:
-          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
-          break;
-      }
-    }
-    DstPtr[0] = reinterpret_cast<uint64_t>(MemDataDest - (Length * Size));
-    DstPtr[1] = reinterpret_cast<uint64_t>(MemDataSrc - (Length * Size));
-  }
-}
-
-DEF_OP(CacheLineClear) {
-  auto Op = IROp->C<IR::IROp_CacheLineClear>();
-
-  char *MemData = *GetSrc<char **>(Data->SSAData, Op->Addr);
-
-  // 64-byte cache line clear
-  CacheLineFlush(MemData);
-}
-
-DEF_OP(CacheLineClean) {
-  auto Op = IROp->C<IR::IROp_CacheLineClean>();
-
-  char *MemData = *GetSrc<char **>(Data->SSAData, Op->Addr);
-
-  // 64-byte cache line clear
-  CacheLineClean(MemData);
-}
-
-DEF_OP(CacheLineZero) {
-  auto Op = IROp->C<IR::IROp_CacheLineZero>();
-
-  uintptr_t MemData = *GetSrc<uintptr_t*>(Data->SSAData, Op->Addr);
-
-  // Force cacheline alignment
-  MemData = MemData & ~(CPUIDEmu::CACHELINE_SIZE - 1);
-
-  using DataType = uint64_t;
-  DataType *MemData64 = reinterpret_cast<DataType*>(MemData);
-
-  // 64-byte cache line zero
-  for (size_t i = 0; i < (CPUIDEmu::CACHELINE_SIZE / sizeof(DataType)); ++i) {
-    MemData64[i] = 0;
-  }
-}
-
-#undef DEF_OP
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/MiscOps.cpp

@@ -1,174 +0,0 @@
-/*
-$info$
-tags: backend|interpreter
-$end_info$
-*/
-
-#include "Interface/Context/Context.h"
-
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/InterpreterDefines.h"
-
-#include <FEXHeaderUtils/Syscalls.h>
-
-#include <cstdint>
-#ifdef _M_X86_64
-#include <xmmintrin.h>
-#endif
-#include <sys/random.h>
-
-namespace FEXCore::CPU {
-
-#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-DEF_OP(Fence) {
-  auto Op = IROp->C<IR::IROp_Fence>();
-  switch (Op->Fence) {
-    case IR::Fence_Load.Val:
-      std::atomic_thread_fence(std::memory_order_acquire);
-      break;
-    case IR::Fence_LoadStore.Val:
-      std::atomic_thread_fence(std::memory_order_seq_cst);
-      break;
-    case IR::Fence_Store.Val:
-      std::atomic_thread_fence(std::memory_order_release);
-      break;
-    default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
-  }
-}
-
-DEF_OP(Break) {
-  auto Op = IROp->C<IR::IROp_Break>();
-
-  Data->State->CurrentFrame->SynchronousFaultData.FaultToTopAndGeneratedException = 1;
-  Data->State->CurrentFrame->SynchronousFaultData.Signal = Op->Reason.Signal;
-  Data->State->CurrentFrame->SynchronousFaultData.TrapNo = Op->Reason.TrapNumber;
-  Data->State->CurrentFrame->SynchronousFaultData.err_code = Op->Reason.ErrorRegister;
-  Data->State->CurrentFrame->SynchronousFaultData.si_code = Op->Reason.si_code;
-
-  switch (Op->Reason.Signal) {
-  case SIGILL:
-    FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGILL);
-    break;
-  case SIGTRAP:
-    FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGTRAP);
-    break;
-  case SIGSEGV:
-    FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGSEGV);
-    break;
-  default:
-    FHU::Syscalls::tgkill(Data->State->ThreadManager.PID, Data->State->ThreadManager.TID, SIGTRAP);
-    break;
-  }
-}
-
-DEF_OP(GetRoundingMode) {
-  uint32_t GuestRounding{};
-#ifdef _M_ARM_64
-  uint64_t Tmp{};
-  __asm(R"(
-    mrs %[Tmp], FPCR;
-  )"
-  : [Tmp] "=r" (Tmp));
-  // Extract the rounding
-  // On ARM the ordering is different than on x86
-  GuestRounding |= ((Tmp >> 24) & 1) ? IR::ROUND_MODE_FLUSH_TO_ZERO : 0;
-  uint8_t RoundingMode = (Tmp >> 22) & 0b11;
-  if (RoundingMode == 0)
-    GuestRounding |= IR::ROUND_MODE_NEAREST;
-  else if (RoundingMode == 1)
-    GuestRounding |= IR::ROUND_MODE_POSITIVE_INFINITY;
-  else if (RoundingMode == 2)
-    GuestRounding |= IR::ROUND_MODE_NEGATIVE_INFINITY;
-  else if (RoundingMode == 3)
-    GuestRounding |= IR::ROUND_MODE_TOWARDS_ZERO;
-#else
-  GuestRounding = _mm_getcsr();
-
-  // Extract the rounding
-  GuestRounding = (GuestRounding >> 13) & 0b111;
-#endif
-  memcpy(GDP, &GuestRounding, sizeof(GuestRounding));
-}
-
-DEF_OP(SetRoundingMode) {
-  auto Op = IROp->C<IR::IROp_SetRoundingMode>();
-  const auto GuestRounding = *GetSrc<uint8_t*>(Data->SSAData, Op->RoundMode);
-#ifdef _M_ARM_64
-  uint64_t HostRounding{};
-  __asm volatile(R"(
-    mrs %[Tmp], FPCR;
-  )"
-  : [Tmp] "=r" (HostRounding));
-  // Mask out the rounding
-  HostRounding &= ~(0b111 << 22);
-
-  HostRounding |= (GuestRounding & IR::ROUND_MODE_FLUSH_TO_ZERO) ? (1U << 24) : 0;
-
-  uint8_t RoundingMode = GuestRounding & 0b11;
-  if (RoundingMode == IR::ROUND_MODE_NEAREST)
-    HostRounding |= (0b00U << 22);
-  else if (RoundingMode == IR::ROUND_MODE_POSITIVE_INFINITY)
-    HostRounding |= (0b01U << 22);
-  else if (RoundingMode == IR::ROUND_MODE_NEGATIVE_INFINITY)
-    HostRounding |= (0b10U << 22);
-  else if (RoundingMode == IR::ROUND_MODE_TOWARDS_ZERO)
-    HostRounding |= (0b11U << 22);
-
-  __asm volatile(R"(
-    msr FPCR, %[Tmp];
-  )"
-  :: [Tmp] "r" (HostRounding));
-#else
-  uint32_t HostRounding = _mm_getcsr();
-
-  // Cut out the host rounding mode
-  HostRounding &= ~(0b111 << 13);
-
-  // Insert our new rounding mode
-  HostRounding |= GuestRounding << 13;
-  _mm_setcsr(HostRounding);
-#endif
-}
-
-DEF_OP(Print) {
-  auto Op = IROp->C<IR::IROp_Print>();
-  const uint8_t OpSize = IROp->Size;
-
-  if (OpSize <= 8) {
-    const auto Src = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
-    LogMan::Msg::IFmt(">>>> Value in Arg: 0x{:x}, {}", Src, Src);
-  }
-  else if (OpSize == 16) {
-    const auto Src = *GetSrc<__uint128_t*>(Data->SSAData, Op->Value);
-    const uint64_t Src0 = Src;
-    const uint64_t Src1 = Src >> 64;
-    LogMan::Msg::IFmt(">>>> Value[0] in Arg: 0x{:x}, {}", Src0, Src0);
-    LogMan::Msg::IFmt("     Value[1] in Arg: 0x{:x}, {}", Src1, Src1);
-  }
-  else
-    LOGMAN_MSG_A_FMT("Unknown value size: {}", OpSize);
-}
-
-DEF_OP(ProcessorID) {
-  uint32_t CPU, CPUNode;
-  FHU::Syscalls::getcpu(&CPU, &CPUNode);
-  GD = (CPUNode << 12) | CPU;
-}
-
-DEF_OP(RDRAND) {
-  // We are ignoring Op->GetReseeded in the interpreter
-  uint64_t *DstPtr = GetDest<uint64_t*>(Data->SSAData, Node);
-  ssize_t Result = ::getrandom(&DstPtr[0], 8, 0);
-
-  // Second result is if we managed to read a valid random number or not
-  DstPtr[1] = Result == 8 ? 1 : 0;
-}
-
-DEF_OP(Yield) {
-  // Nop implementation
-}
-
-#undef DEF_OP
-
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/MoveOps.cpp

@@ -1,35 +0,0 @@
-/*
-$info$
-tags: backend|interpreter
-$end_info$
-*/
-
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/InterpreterDefines.h"
-
-#include <cstdint>
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void InterpreterOps::Op_##x(IR::IROp_Header *IROp, IROpData *Data, IR::NodeID Node)
-DEF_OP(ExtractElementPair) {
-  auto Op = IROp->C<IR::IROp_ExtractElementPair>();
-  const auto Src = GetSrc<uintptr_t>(Data->SSAData, Op->Pair);
-  memcpy(GDP,
-    reinterpret_cast<void*>(Src + Op->Header.Size * Op->Element), Op->Header.Size);
-}
-
-DEF_OP(CreateElementPair) {
-  auto Op = IROp->C<IR::IROp_CreateElementPair>();
-  const void *Src_Lower = GetSrc<void*>(Data->SSAData, Op->Lower);
-  const void *Src_Upper = GetSrc<void*>(Data->SSAData, Op->Upper);
-
-  uint8_t *Dst = GetDest<uint8_t*>(Data->SSAData, Node);
-
-  memcpy(Dst, Src_Lower, IROp->ElementSize);
-  memcpy(Dst + IROp->ElementSize, Src_Upper, IROp->ElementSize);
-}
-
-#undef DEF_OP
-
-} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/JIT/x86_64/AtomicOps.cpp

@@ -1,651 +0,0 @@
-/*
-$info$
-tags: backend|x86-64
-$end_info$
-*/
-
-#include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/Utils/LogManager.h>
-
-#include <array>
-#include <stdint.h>
-#include <utility>
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-DEF_OP(CASPair) {
-  auto Op = IROp->C<IR::IROp_CAS>();
-
-  // DataSrc = *Src1
-  // if (DataSrc == Src3) { *Src1 == Src2; } Src2 = DataSrc
-  // This will write to memory! Careful!
-  // Third operand must be a calculated guest memory address
-  //OrderedNode *CASResult = _CAS(Src3, Src2, Src1);
-  auto Dst = GetSrcPair<RA_64>(Node);
-  auto Expected = GetSrcPair<RA_64>(Op->Expected.ID());
-  auto Desired = GetSrcPair<RA_64>(Op->Desired.ID());
-  auto MemSrc = GetSrc<RA_64>(Op->Addr.ID());
-
-  Xbyak::Reg MemReg = MemSrc;
-
-  mov(rax, Expected.first);
-  mov(rdx, Expected.second);
-
-  mov(rbx, Desired.first);
-  mov(rcx, Desired.second);
-
-  // RDI(Or Source) now contains pointer
-  // RDX:RAX contains our expected value
-  // RCX:RBX contains our desired
-
-  lock();
-
-  switch (IROp->ElementSize) {
-    case 4: {
-      cmpxchg8b(dword [MemReg]);
-      // EDX:EAX now contains the result
-      mov(Dst.first.cvt32(), eax);
-      mov(Dst.second.cvt32(), edx);
-    break;
-    }
-    case 8: {
-      cmpxchg16b(qword [MemReg]);
-      // RDX:RAX now contains the result
-      mov(Dst.first, rax);
-      mov(Dst.second, rdx);
-    break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unsupported: {}", IROp->ElementSize);
-  }
-}
-
-DEF_OP(CAS) {
-  auto Op = IROp->C<IR::IROp_CAS>();
-  uint8_t OpSize = IROp->Size;
-
-  // DataSrc = *Src1
-  // if (DataSrc == Src3) { *Src1 == Src2; } Src2 = DataSrc
-  // This will write to memory! Careful!
-  // Third operand must be a calculated guest memory address
-  //OrderedNode *CASResult = _CAS(Src3, Src2, Src1);
-
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-
-  mov(rax, GetSrc<RA_64>(Op->Expected.ID()));
-
-  // RCX now contains pointer
-  // RAX contains our expected value
-  // RDX contains our desired
-
-  lock();
-  switch (OpSize) {
-  case 1: {
-    cmpxchg(byte [MemReg], GetSrc<RA_8>(Op->Desired.ID()));
-    movzx(GetDst<RA_64>(Node), al);
-  break;
-  }
-  case 2: {
-    cmpxchg(word [MemReg], GetSrc<RA_16>(Op->Desired.ID()));
-    movzx(GetDst<RA_64>(Node), ax);
-  break;
-  }
-  case 4: {
-    cmpxchg(dword [MemReg], GetSrc<RA_32>(Op->Desired.ID()));
-    // RAX now contains the result
-    mov (GetDst<RA_64>(Node), eax);
-  break;
-  }
-  case 8: {
-    cmpxchg(qword [MemReg], GetSrc<RA_64>(Op->Desired.ID()));
-    // RAX now contains the result
-    mov (GetDst<RA_64>(Node), rax);
-  break;
-  }
-  default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
-  }
-}
-
-DEF_OP(AtomicAdd) {
-  auto Op = IROp->C<IR::IROp_AtomicAdd>();
-
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-
-  lock();
-  switch (IROp->Size) {
-    case 1:
-      add(byte [MemReg], GetSrc<RA_8>(Op->Value.ID()));
-      break;
-    case 2:
-      add(word [MemReg], GetSrc<RA_16>(Op->Value.ID()));
-      break;
-    case 4:
-      add(dword [MemReg], GetSrc<RA_32>(Op->Value.ID()));
-      break;
-    case 8:
-      add(qword [MemReg], GetSrc<RA_64>(Op->Value.ID()));
-      break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicSub) {
-  auto Op = IROp->C<IR::IROp_AtomicSub>();
-
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-  lock();
-  switch (IROp->Size) {
-    case 1:
-      sub(byte [MemReg], GetSrc<RA_8>(Op->Value.ID()));
-      break;
-    case 2:
-      sub(word [MemReg], GetSrc<RA_16>(Op->Value.ID()));
-      break;
-    case 4:
-      sub(dword [MemReg], GetSrc<RA_32>(Op->Value.ID()));
-      break;
-    case 8:
-      sub(qword [MemReg], GetSrc<RA_64>(Op->Value.ID()));
-      break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicAnd) {
-  auto Op = IROp->C<IR::IROp_AtomicAnd>();
-
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-  lock();
-  switch (IROp->Size) {
-    case 1:
-      and_(byte [MemReg], GetSrc<RA_8>(Op->Value.ID()));
-      break;
-    case 2:
-      and_(word [MemReg], GetSrc<RA_16>(Op->Value.ID()));
-      break;
-    case 4:
-      and_(dword [MemReg], GetSrc<RA_32>(Op->Value.ID()));
-      break;
-    case 8:
-      and_(qword [MemReg], GetSrc<RA_64>(Op->Value.ID()));
-      break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicOr) {
-  auto Op = IROp->C<IR::IROp_AtomicOr>();
-
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-  lock();
-  switch (IROp->Size) {
-    case 1:
-      or_(byte [MemReg], GetSrc<RA_8>(Op->Value.ID()));
-      break;
-    case 2:
-      or_(word [MemReg], GetSrc<RA_16>(Op->Value.ID()));
-      break;
-    case 4:
-      or_(dword [MemReg], GetSrc<RA_32>(Op->Value.ID()));
-      break;
-    case 8:
-      or_(qword [MemReg], GetSrc<RA_64>(Op->Value.ID()));
-      break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicXor) {
-  auto Op = IROp->C<IR::IROp_AtomicXor>();
-
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-  lock();
-  switch (IROp->Size) {
-    case 1:
-      xor_(byte [MemReg], GetSrc<RA_8>(Op->Value.ID()));
-      break;
-    case 2:
-      xor_(word [MemReg], GetSrc<RA_16>(Op->Value.ID()));
-      break;
-    case 4:
-      xor_(dword [MemReg], GetSrc<RA_32>(Op->Value.ID()));
-      break;
-    case 8:
-      xor_(qword [MemReg], GetSrc<RA_64>(Op->Value.ID()));
-      break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicSwap) {
-  auto Op = IROp->C<IR::IROp_AtomicSwap>();
-
-  Xbyak::Reg MemReg = rax;
-  mov(MemReg, GetSrc<RA_64>(Op->Addr.ID()));
-
-  switch (IROp->Size) {
-    case 1:
-      movzx(GetDst<RA_64>(Node), GetSrc<RA_8>(Op->Value.ID()));
-      lock();
-      xchg(byte [MemReg], GetDst<RA_8>(Node));
-      break;
-    case 2:
-      movzx(GetDst<RA_64>(Node), GetSrc<RA_16>(Op->Value.ID()));
-      lock();
-      xchg(word [MemReg], GetDst<RA_16>(Node));
-      break;
-    case 4:
-      mov(GetDst<RA_64>(Node), GetSrc<RA_32>(Op->Value.ID()));
-      lock();
-      xchg(dword [MemReg], GetDst<RA_32>(Node));
-      break;
-    case 8:
-      mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Value.ID()));
-      lock();
-      xchg(qword [MemReg], GetDst<RA_64>(Node));
-      break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicSwap size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchAdd) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();
-
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-  switch (IROp->Size) {
-    case 1:
-      movzx(rcx, GetSrc<RA_8>(Op->Value.ID()));
-      lock();
-      xadd(byte [MemReg], cl);
-      movzx(GetDst<RA_32>(Node), cl);
-      break;
-    case 2:
-      movzx(rcx, GetSrc<RA_16>(Op->Value.ID()));
-      lock();
-      xadd(word [MemReg], cx);
-      movzx(GetDst<RA_32>(Node), cx);
-      break;
-    case 4:
-      mov(ecx, GetSrc<RA_32>(Op->Value.ID()));
-      lock();
-      xadd(dword [MemReg], ecx);
-      mov(GetDst<RA_64>(Node), ecx);
-      break;
-    case 8:
-      mov(rcx, GetSrc<RA_64>(Op->Value.ID()));
-      lock();
-      xadd(qword [MemReg], rcx);
-      mov(GetDst<RA_64>(Node), rcx);
-      break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchAdd size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchSub) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchSub>();
-
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-  switch (IROp->Size) {
-    case 1:
-      mov(cl, GetSrc<RA_8>(Op->Value.ID()));
-      neg(cl);
-      lock();
-      xadd(byte [MemReg], cl);
-      movzx(GetDst<RA_32>(Node), cl);
-      break;
-    case 2:
-      mov(cx, GetSrc<RA_16>(Op->Value.ID()));
-      neg(cx);
-      lock();
-      xadd(word [MemReg], cx);
-      movzx(GetDst<RA_32>(Node), cx);
-      break;
-    case 4:
-      mov(ecx, GetSrc<RA_32>(Op->Value.ID()));
-      neg(ecx);
-      lock();
-      xadd(dword [MemReg], ecx);
-      mov(GetDst<RA_32>(Node), ecx);
-      break;
-    case 8:
-      mov(rcx, GetSrc<RA_64>(Op->Value.ID()));
-      neg(rcx);
-      lock();
-      xadd(qword [MemReg], rcx);
-      mov(GetDst<RA_64>(Node), rcx);
-      break;
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchSub size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchAnd) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchAnd>();
-
-  // TMP1 = rax
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-
-  switch (IROp->Size) {
-    case 1: {
-      mov(TMP1.cvt8(), byte [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt8(), TMP1.cvt8());
-      mov(TMP3.cvt8(), TMP1.cvt8());
-      and_(TMP2.cvt8(), GetSrc<RA_8>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
-      jne(Loop);
-      // Result is the previous value from memory, which is currently in TMP3
-      movzx(GetDst<RA_64>(Node), TMP3.cvt8());
-      break;
-    }
-    case 2: {
-      mov(TMP1.cvt16(), word [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt16(), TMP1.cvt16());
-      mov(TMP3.cvt16(), TMP1.cvt16());
-      and_(TMP2.cvt16(), GetSrc<RA_16>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(word [MemReg], TMP2.cvt16());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      movzx(GetDst<RA_64>(Node), TMP3.cvt16());
-      break;
-    }
-    case 4: {
-      mov(TMP1.cvt32(), dword [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt32(), TMP1.cvt32());
-      mov(TMP3.cvt32(), TMP1.cvt32());
-      and_(TMP2.cvt32(), GetSrc<RA_32>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      mov(GetDst<RA_32>(Node), TMP3.cvt32());
-      break;
-    }
-    case 8: {
-      mov(TMP1.cvt64(), qword [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt64(), TMP1.cvt64());
-      mov(TMP3.cvt64(), TMP1.cvt64());
-      and_(TMP2.cvt64(), GetSrc<RA_64>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      mov(GetDst<RA_64>(Node), TMP3.cvt64());
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchAnd size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchOr) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchOr>();
-
-  // TMP1 = rax
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-  switch (IROp->Size) {
-    case 1: {
-      mov(TMP1.cvt8(), byte [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt8(), TMP1.cvt8());
-      mov(TMP3.cvt8(), TMP1.cvt8());
-      or_(TMP2.cvt8(), GetSrc<RA_8>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
-      jne(Loop);
-      // Result is the previous value from memory, which is currently in TMP3
-      movzx(GetDst<RA_64>(Node), TMP3.cvt8());
-      break;
-    }
-    case 2: {
-      mov(TMP1.cvt16(), word [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt16(), TMP1.cvt16());
-      mov(TMP3.cvt16(), TMP1.cvt16());
-      or_(TMP2.cvt16(), GetSrc<RA_16>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(word [MemReg], TMP2.cvt16());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      movzx(GetDst<RA_64>(Node), TMP3.cvt16());
-      break;
-    }
-    case 4: {
-      mov(TMP1.cvt32(), dword [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt32(), TMP1.cvt32());
-      mov(TMP3.cvt32(), TMP1.cvt32());
-      or_(TMP2.cvt32(), GetSrc<RA_32>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      mov(GetDst<RA_32>(Node), TMP3.cvt32());
-      break;
-    }
-    case 8: {
-      mov(TMP1.cvt64(), qword [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt64(), TMP1.cvt64());
-      mov(TMP3.cvt64(), TMP1.cvt64());
-      or_(TMP2.cvt64(), GetSrc<RA_64>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      mov(GetDst<RA_64>(Node), TMP3.cvt64());
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchOr size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchXor) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchXor>();
-
-  // TMP1 = rax
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-  switch (IROp->Size) {
-    case 1: {
-      mov(TMP1.cvt8(), byte [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt8(), TMP1.cvt8());
-      mov(TMP3.cvt8(), TMP1.cvt8());
-      xor_(TMP2.cvt8(), GetSrc<RA_8>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
-      jne(Loop);
-      // Result is the previous value from memory, which is currently in TMP3
-      movzx(GetDst<RA_64>(Node), TMP3.cvt8());
-      break;
-    }
-    case 2: {
-      mov(TMP1.cvt16(), word [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt16(), TMP1.cvt16());
-      mov(TMP3.cvt16(), TMP1.cvt16());
-      xor_(TMP2.cvt16(), GetSrc<RA_16>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(word [MemReg], TMP2.cvt16());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      movzx(GetDst<RA_64>(Node), TMP3.cvt16());
-      break;
-    }
-    case 4: {
-      mov(TMP1.cvt32(), dword [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt32(), TMP1.cvt32());
-      mov(TMP3.cvt32(), TMP1.cvt32());
-      xor_(TMP2.cvt32(), GetSrc<RA_32>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      mov(GetDst<RA_32>(Node), TMP3.cvt32());
-      break;
-    }
-    case 8: {
-      mov(TMP1.cvt64(), qword [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt64(), TMP1.cvt64());
-      mov(TMP3.cvt64(), TMP1.cvt64());
-      xor_(TMP2.cvt64(), GetSrc<RA_64>(Op->Value.ID()));
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      mov(GetDst<RA_64>(Node), TMP3.cvt64());
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchXor size: {}", IROp->Size);
-  }
-}
-
-DEF_OP(AtomicFetchNeg) {
-  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
-
-  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
-  switch (IROp->Size) {
-    case 1: {
-      mov(TMP1.cvt8(), byte [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt8(), TMP1.cvt8());
-      mov(TMP3.cvt8(), TMP1.cvt8());
-      neg(TMP2.cvt8());
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
-      jne(Loop);
-      // Result is the previous value from memory, which is currently in TMP3
-      movzx(GetDst<RA_64>(Node), TMP3.cvt8());
-      break;
-    }
-    case 2: {
-      mov(TMP1.cvt16(), word [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt16(), TMP1.cvt16());
-      mov(TMP3.cvt16(), TMP1.cvt16());
-      neg(TMP2.cvt16());
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(word [MemReg], TMP2.cvt16());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      movzx(GetDst<RA_64>(Node), TMP3.cvt16());
-      break;
-    }
-    case 4: {
-      mov(TMP1.cvt32(), dword [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt32(), TMP1.cvt32());
-      mov(TMP3.cvt32(), TMP1.cvt32());
-      neg(TMP2.cvt32());
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      mov(GetDst<RA_32>(Node), TMP3.cvt32());
-      break;
-    }
-    case 8: {
-      mov(TMP1.cvt64(), qword [MemReg]);
-
-      Label Loop;
-      L(Loop);
-      mov(TMP2.cvt64(), TMP1.cvt64());
-      mov(TMP3.cvt64(), TMP1.cvt64());
-      neg(TMP2.cvt64());
-
-      // Updates RAX with the value from memory
-      lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
-      jne(Loop);
-
-      // Result is the previous value from memory, which is currently in TMP3
-      mov(GetDst<RA_64>(Node), TMP3.cvt64());
-      break;
-    }
-    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchNeg size: {}", IROp->Size);
-  }
-}
-
-#undef DEF_OP
-void X86JITCore::RegisterAtomicHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
-  REGISTER_OP(CASPAIR,        CASPair);
-  REGISTER_OP(CAS,            CAS);
-  REGISTER_OP(ATOMICADD,      AtomicAdd);
-  REGISTER_OP(ATOMICSUB,      AtomicSub);
-  REGISTER_OP(ATOMICAND,      AtomicAnd);
-  REGISTER_OP(ATOMICOR,       AtomicOr);
-  REGISTER_OP(ATOMICXOR,      AtomicXor);
-  REGISTER_OP(ATOMICSWAP,     AtomicSwap);
-  REGISTER_OP(ATOMICFETCHADD, AtomicFetchAdd);
-  REGISTER_OP(ATOMICFETCHSUB, AtomicFetchSub);
-  REGISTER_OP(ATOMICFETCHAND, AtomicFetchAnd);
-  REGISTER_OP(ATOMICFETCHOR,  AtomicFetchOr);
-  REGISTER_OP(ATOMICFETCHXOR, AtomicFetchXor);
-  REGISTER_OP(ATOMICFETCHNEG, AtomicFetchNeg);
-#undef REGISTER_OP
-}
-}
-

External/FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp

@@ -1,361 +0,0 @@
-/*
-$info$
-tags: backend|x86-64
-$end_info$
-*/
-
-#include "Interface/Context/Context.h"
-#include "Interface/Core/CPUID.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-#include "Interface/Core/LookupCache.h"
-#include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/HLE/Thunks/Thunks.h"
-
-#include <FEXCore/Core/CPUID.h>
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXCore/HLE/SyscallHandler.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/Utils/LogManager.h>
-
-#include <array>
-#include <memory>
-#include <stddef.h>
-#include <stdint.h>
-#include <unordered_map>
-#include <utility>
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-
-DEF_OP(CallbackReturn) {
-  // Adjust the stack first for a regular return
-  if (SpillSlots) {
-    add(rsp, SpillSlots * MaxSpillSlotSize); // + 8 to consume return address
-  }
-
-  // Make sure to adjust the refcounter so we don't clear the cache now
-  sub(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, SignalHandlerRefCounter)], 1);
-
-  // We need to adjust an additional 8 bytes to get back to the original "misaligned" RSP state
-  add(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])], 8);
-
-  // Now jump back to the thunk
-  // XXX: XMM?
-  add(rsp, 8);
-
-  pop(r15);
-  pop(r14);
-  pop(r13);
-  pop(r12);
-  pop(rbp);
-  pop(rbx);
-
-  ret();
-}
-
-DEF_OP(ExitFunction) {
-  Label FullLookup;
-  auto Op = IROp->C<IR::IROp_ExitFunction>();
-
-
-  if (SpillSlots) {
-    add(rsp, SpillSlots * MaxSpillSlotSize);
-  }
-
-  uint64_t NewRIP;
-
-  if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
-    Label l_BranchHost;
-    Label l_BranchGuest;
-
-    lea(rax, ptr[rip + l_BranchHost]);
-    jmp(qword[rax]);
-
-    L(l_BranchHost);
-    //FEX_TODO(this is not per thread)
-    dq(ThreadState->CurrentFrame->Pointers.Common.ExitFunctionLinker);
-    L(l_BranchGuest);
-    dq(NewRIP);
-  } else {
-    Xbyak::Reg RipReg = GetSrc<RA_64>(Op->NewRIP.ID());
-
-    // L1 Cache
-    mov(rcx, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.L1Pointer)]);
-
-    mov(rax, RipReg);
-
-    and_(rax, LookupCache::L1_ENTRIES_MASK);
-    shl(rax, 4);
-
-    Xbyak::RegExp LookupBase = rcx + rax;
-
-    cmp(qword[LookupBase + 8], RipReg);
-    jne(FullLookup);
-    jmp(qword[LookupBase + 0]);
-
-    L(FullLookup);
-    mov(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.rip)], RipReg);
-    jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop)]);
-  }
-
-#ifdef BLOCKSTATS
-  ExitBlock();
-#endif
-}
-
-DEF_OP(Jump) {
-  const auto Op = IROp->C<IR::IROp_Jump>();
-  const auto Target = Op->TargetBlock.ID();
-
-  PendingTargetLabel = &JumpTargets.try_emplace(Target).first->second;
-}
-
-#define GRCMP(Node) (Op->CompareSize == 4 ? GetSrc<RA_32>(Node) : GetSrc<RA_64>(Node))
-
-DEF_OP(CondJump) {
-  auto Op = IROp->C<IR::IROp_CondJump>();
-
-  Label *TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;
-
-  if (IsGPR(Op->Cmp1.ID())) {
-    uint64_t Const;
-    if (IsInlineConstant(Op->Cmp2, &Const)) {
-      cmp(GRCMP(Op->Cmp1.ID()), Const);
-    } else {
-      cmp(GRCMP(Op->Cmp1.ID()), GRCMP(Op->Cmp2.ID()));
-    }
-  } else if (IsFPR(Op->Cmp1.ID())) {
-    if (Op->CompareSize == 4) {
-      ucomiss(GetSrc(Op->Cmp1.ID()), GetSrc(Op->Cmp2.ID()));
-    } else {
-      ucomisd(GetSrc(Op->Cmp1.ID()), GetSrc(Op->Cmp2.ID()));
-    }
-  }
-
-  auto [_, __, JCC] = GetCC(Op->Cond);
-
-  (this->*JCC)(*TrueTargetLabel, T_NEAR);
-
-  PendingTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
-}
-
-DEF_OP(Syscall) {
-  auto Op = IROp->C<IR::IROp_Syscall>();
-  // XXX: This is very terrible, but I don't care for right now
-
-  FEXCore::IR::SyscallFlags Flags = Op->Flags;
-  auto NumPush = RA64.size();
-
-  for (auto &Reg : RA64)
-    push(Reg);
-
-  // Syscall ABI for x86-64
-  // this: rdi
-  // Thread: rsi
-  // ArgPointer: rdx (Stack)
-  //
-  // Result: RAX
-
-  // These are pushed in reverse order because stacks
-  for (uint32_t i = FEXCore::HLE::SyscallArguments::MAX_ARGS; i > 0; --i) {
-    if (Op->Header.Args[i - 1].IsInvalid()) continue;
-    push(GetSrc<RA_64>(Op->Header.Args[i - 1].ID()));
-    ++NumPush;
-  }
-
-  mov(rsi, STATE); // Move thread in to rsi
-  mov(rdi, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerObj)]);
-  mov(rdx, rsp);
-
-  if (NumPush & 1)
-    sub(rsp, 8); // Align
-  // {rdi, rsi, rdx}
-  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerFunc)]);
-
-  if (NumPush & 1)
-    add(rsp, 8); // Align
-
-  // Reload arguments just in case they are sill live after the fact
-  for (uint32_t i = 0; i < FEXCore::HLE::SyscallArguments::MAX_ARGS; ++i) {
-    if (Op->Header.Args[i].IsInvalid()) continue;
-    pop(GetSrc<RA_64>(Op->Header.Args[i].ID()));
-  }
-
-  for (uint32_t i = RA64.size(); i > 0; --i)
-    pop(RA64[i - 1]);
-
-  if ((Flags & FEXCore::IR::SyscallFlags::NORETURNEDRESULT) != FEXCore::IR::SyscallFlags::NORETURNEDRESULT) {
-    // Move result to its destination register.
-    // Only if `NORETURNEDRESULT` wasn't set, otherwise we might overwrite the CPUState refilled with `FillStaticRegs`
-    mov (GetDst<RA_64>(Node), rax);
-  }
-}
-
-DEF_OP(Thunk) {
-  auto Op = IROp->C<IR::IROp_Thunk>();
-
-  auto NumPush = RA64.size();
-
-  for (auto &Reg : RA64)
-    push(Reg);
-
-  if (NumPush & 1)
-    sub(rsp, 8); // Align
-
-  mov(rdi, GetSrc<RA_64>(Op->ArgPtr.ID()));
-
-  auto thunkFn = static_cast<Context::ContextImpl*>(ThreadState->CTX)->ThunkHandler->LookupThunk(Op->ThunkNameHash);
-
-  mov(rax, reinterpret_cast<uintptr_t>(thunkFn));
-  call(rax);
-
-  if (NumPush & 1)
-    add(rsp, 8); // Align
-
-  for (uint32_t i = RA64.size(); i > 0; --i)
-    pop(RA64[i - 1]);
-}
-
-DEF_OP(ValidateCode) {
-  auto Op = IROp->C<IR::IROp_ValidateCode>();
-  const auto* OldCode = (const uint8_t*)&Op->CodeOriginalLow;
-  int len = Op->CodeLength;
-  int idx = 0;
-
-  xor_(GetDst<RA_64>(Node), GetDst<RA_64>(Node));
-  mov(rax, Entry + Op->Offset);
-  mov(rbx, 1);
-  while (len >= 4) {
-    cmp(dword[rax + idx], *(const uint32_t*)(OldCode + idx));
-    cmovne(GetDst<RA_64>(Node), rbx);
-    len-=4;
-    idx+=4;
-  }
-  while (len >= 2) {
-    mov(rcx, *(const uint16_t*)(OldCode + idx));
-    cmp(word[rax + idx], cx);
-    cmovne(GetDst<RA_64>(Node), rbx);
-    len-=2;
-    idx+=2;
-  }
-  while (len >= 1) {
-    cmp(byte[rax + idx], *(const uint8_t*)(OldCode + idx));
-    cmovne(GetDst<RA_64>(Node), rbx);
-    len-=1;
-    idx+=1;
-  }
-}
-
-DEF_OP(ThreadRemoveCodeEntry) {
-  auto NumPush = RA64.size();
-
-  for (auto &Reg : RA64)
-    push(Reg);
-
-  if (NumPush & 1)
-    sub(rsp, 8); // Align
-
-  mov(rdi, STATE);
-  mov(rax, Entry); // imm64 move
-  mov(rsi, rax);
-
-  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadRemoveCodeEntryFromJIT)]);
-
-  if (NumPush & 1)
-    add(rsp, 8); // Align
-
-  for (uint32_t i = RA64.size(); i > 0; --i)
-    pop(RA64[i - 1]);
-}
-
-DEF_OP(CPUID) {
-  auto Op = IROp->C<IR::IROp_CPUID>();
-
-  for (auto &Reg : RA64)
-    push(Reg);
-
-  // CPUID ABI
-  // this: rdi
-  // Function: rsi
-  //
-  // Result: RAX, RDX. 4xi32
-
-  // rsi can be in the source registers, so copy argument to edx first
-  mov (edx, GetSrc<RA_32>(Op->Leaf.ID()));
-  mov (esi, GetSrc<RA_32>(Op->Function.ID()));
-  mov (rdi, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj)]);
-
-  auto NumPush = RA64.size();
-
-  if (NumPush & 1)
-    sub(rsp, 8); // Align
-
-  // {rdi, rsi, rdx}
-  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDFunction)]);
-
-  if (NumPush & 1)
-    add(rsp, 8); // Align
-
-  for (uint32_t i = RA64.size(); i > 0; --i)
-    pop(RA64[i - 1]);
-
-  auto Dst = GetSrcPair<RA_64>(Node);
-  mov(Dst.first, rax);
-  mov(Dst.second, rdx);
-}
-
-DEF_OP(XGETBV) {
-  auto Op = IROp->C<IR::IROp_XGetBV>();
-
-  for (auto &Reg : RA64)
-    push(Reg);
-
-  // CPUID ABI
-  // this: rdi
-  // Function: rsi
-  //
-  // Result: RAX, RDX. 4xi32
-
-  // rsi can be in the source registers, so copy argument to edx first
-  mov (esi, GetSrc<RA_32>(Op->Function.ID()));
-  mov (rdi, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj)]);
-
-  auto NumPush = RA64.size();
-
-  if (NumPush & 1)
-    sub(rsp, 8); // Align
-
-  // {rdi, rsi, rdx}
-  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.XCRFunction)]);
-
-  if (NumPush & 1)
-    add(rsp, 8); // Align
-
-  for (uint32_t i = RA64.size(); i > 0; --i)
-    pop(RA64[i - 1]);
-
-  auto Dst = GetSrcPair<RA_64>(Node);
-  mov(Dst.first.cvt32(), eax);
-  mov(Dst.second, rax);
-  shr(Dst.second, 32);
-}
-
-#undef DEF_OP
-void X86JITCore::RegisterBranchHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
-  REGISTER_OP(CALLBACKRETURN,    CallbackReturn);
-  REGISTER_OP(EXITFUNCTION,      ExitFunction);
-  REGISTER_OP(JUMP,              Jump);
-  REGISTER_OP(CONDJUMP,          CondJump);
-  REGISTER_OP(SYSCALL,           Syscall);
-  REGISTER_OP(THUNK,             Thunk);
-  REGISTER_OP(VALIDATECODE,      ValidateCode);
-  REGISTER_OP(THREADREMOVECODEENTRY,   ThreadRemoveCodeEntry);
-  REGISTER_OP(CPUID,             CPUID);
-  REGISTER_OP(XGETBV,            XGETBV);
-#undef REGISTER_OP
-}
-}

External/FEXCore/Source/Interface/Core/JIT/x86_64/ConversionOps.cpp

@@ -1,417 +0,0 @@
-/*
-$info$
-tags: backend|x86-64
-$end_info$
-*/
-
-#include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/Utils/LogManager.h>
-
-#include <array>
-#include <stdint.h>
-
-namespace FEXCore::CPU {
-
-#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-DEF_OP(VInsGPR) {
-  const auto Op = IROp->C<IR::IROp_VInsGPR>();
-  const auto OpSize = IROp->Size;
-
-  const auto Dst = GetDst(Node);
-  const auto DestVector = GetSrc(Op->DestVector.ID());
-
-  const auto DestIdx = Op->DestIdx;
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto ElementSizeBits = ElementSize * 8;
-  const auto Offset = ElementSizeBits * DestIdx;
-
-  constexpr auto SSEBitSize = Core::CPUState::XMM_SSE_REG_SIZE * 8;
-
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-  const auto InUpperLane = Offset >= SSEBitSize;
-
-  if (InUpperLane && !Is256Bit) {
-    LOGMAN_MSG_A_FMT("Attempt to access upper 128-bit lane in 128-bit operation! Offset={}",
-                     Offset);
-    return;
-  }
-
-  if (Is256Bit) {
-    vmovapd(ToYMM(Dst), ToYMM(DestVector));
-  } else {
-    vmovapd(Dst, DestVector);
-  }
-
-  const auto Insert = [&](const Xbyak::Xmm& reg, int index) {
-    switch (ElementSize) {
-      case 1: {
-        if (InUpperLane) {
-          index -= 16;
-        }
-        pinsrb(reg, GetSrc<RA_32>(Op->Src.ID()), index);
-        break;
-      }
-      case 2: {
-        if (InUpperLane) {
-          index -= 8;
-        }
-        pinsrw(reg, GetSrc<RA_32>(Op->Src.ID()), index);
-        break;
-      }
-      case 4: {
-        if (InUpperLane) {
-          index -= 4;
-        }
-        pinsrd(reg, GetSrc<RA_32>(Op->Src.ID()), index);
-        break;
-      }
-      case 8: {
-        if (InUpperLane) {
-          index -= 2;
-        }
-        pinsrq(reg, GetSrc<RA_64>(Op->Src.ID()), index);
-        break;
-      }
-      default:
-        LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
-        break;
-    }
-  };
-
-  if (InUpperLane) {
-    vextracti128(xmm15, ToYMM(Dst), 1);
-    Insert(xmm15, DestIdx);
-    vinserti128(ToYMM(Dst), ToYMM(Dst), xmm15, 1);
-  } else {
-    Insert(Dst, DestIdx);
-  }
-}
-
-DEF_OP(VCastFromGPR) {
-  auto Op = IROp->C<IR::IROp_VCastFromGPR>();
-  switch (Op->Header.ElementSize) {
-    case 1:
-      movzx(rax, GetSrc<RA_8>(Op->Src.ID()));
-      vmovq(GetDst(Node), rax);
-      break;
-    case 2:
-      movzx(rax, GetSrc<RA_16>(Op->Src.ID()));
-      vmovq(GetDst(Node), rax);
-      break;
-    case 4:
-      vmovd(GetDst(Node), GetSrc<RA_32>(Op->Src.ID()).cvt32());
-      break;
-    case 8:
-      vmovq(GetDst(Node), GetSrc<RA_64>(Op->Src.ID()).cvt64());
-      break;
-    default: LOGMAN_MSG_A_FMT("Unknown VCastFromGPR element size: {}", Op->Header.ElementSize);
-  }
-}
-
-DEF_OP(VDupFromGPR) {
-  const auto Op = IROp->C<IR::IROp_VDupFromGPR>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = IROp->ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Src = GetSrc<RA_64>(Op->Src.ID()).cvt64();
-
-  vmovq(Dst, Src);
-
-  switch (ElementSize) {
-    case 1:
-      if (Is256Bit) {
-        vpbroadcastb(ToYMM(Dst), Dst);
-      } else {
-        vpbroadcastb(Dst, Dst);
-      }
-      break;
-    case 2:
-      if (Is256Bit) {
-        vpbroadcastw(ToYMM(Dst), Dst);
-      } else {
-        vpbroadcastw(Dst, Dst);
-      }
-      break;
-    case 4:
-      if (Is256Bit) {
-        vpbroadcastd(ToYMM(Dst), Dst);
-      } else {
-        vpbroadcastd(Dst, Dst);
-      }
-      break;
-    case 8:
-      if (Is256Bit) {
-        vpbroadcastq(ToYMM(Dst), Dst);
-      } else {
-        vpbroadcastq(Dst, Dst);
-      }
-      break;
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled element size: {}", ElementSize);
-      return;
-  }
-}
-
-DEF_OP(Float_FromGPR_S) {
-  const auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
-
-  const uint16_t ElementSize = Op->Header.ElementSize;
-  const uint16_t Conv = (ElementSize << 8) | Op->SrcElementSize;
-
-  switch (Conv) {
-    case 0x0404: { // Float <- int32_t
-      cvtsi2ss(GetDst(Node), GetSrc<RA_32>(Op->Src.ID()));
-      break;
-    }
-    case 0x0408: { // Float <- int64_t
-      cvtsi2ss(GetDst(Node), GetSrc<RA_64>(Op->Src.ID()));
-      break;
-    }
-    case 0x0804: { // Double <- int32_t
-      cvtsi2sd(GetDst(Node), GetSrc<RA_32>(Op->Src.ID()));
-      break;
-    }
-    case 0x0808: { // Double <- int64_t
-      cvtsi2sd(GetDst(Node), GetSrc<RA_64>(Op->Src.ID()));
-      break;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled conversion mask: Mask=0x{:04x}, ElementSize={}, SrcElementSize={}",
-                       Conv, ElementSize, Op->SrcElementSize);
-      break;
-  }
-}
-
-DEF_OP(Float_FToF) {
-  auto Op = IROp->C<IR::IROp_Float_FToF>();
-  const uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
-
-  switch (Conv) {
-    case 0x0804: { // Double <- Float
-      cvtss2sd(GetDst(Node), GetSrc(Op->Scalar.ID()));
-      break;
-    }
-    case 0x0408: { // Float <- Double
-      cvtsd2ss(GetDst(Node), GetSrc(Op->Scalar.ID()));
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown Float_FToF sizes: 0x{:x}", Conv);
-  }
-}
-
-DEF_OP(Vector_SToF) {
-  const auto Op = IROp->C<IR::IROp_Vector_SToF>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
-
-  switch (ElementSize) {
-    case 4:
-      if (Is256Bit) {
-        vcvtdq2ps(ToYMM(Dst), ToYMM(Vector));
-      } else {
-        vcvtdq2ps(Dst, Vector);
-      }
-      break;
-    case 8:
-      // This operation is a bit disgusting in x86
-      // There is no vector form of this instruction until AVX512VL + AVX512DQ (vcvtqq2pd)
-      // 1) First extract the top 64bits
-      // 2) Do a scalar conversion on each
-      // 3) Make sure to merge them together at the end
-      pextrq(rax, Vector, 1);
-      pextrq(rcx, Vector, 0);
-      cvtsi2sd(Dst, rcx);
-      cvtsi2sd(xmm15, rax);
-      if (Is256Bit) {
-        movlhps(Dst, xmm15);
-        vextracti128(xmm15, ToYMM(Vector), 1);
-
-        pextrq(rax, xmm15, 1);
-        pextrq(rcx, xmm15, 0);
-        cvtsi2sd(xmm15, rcx);
-        cvtsi2sd(xmm14, rax);
-        movlhps(xmm15, xmm14);
-
-        vinserti128(ToYMM(Dst), ToYMM(Dst), xmm15, 1);
-      } else {
-        vmovlhps(Dst, Dst, xmm15);
-      }
-      break;
-    default:
-      LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", ElementSize);
-      break;
-  }
-}
-
-DEF_OP(Vector_FToZS) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToZS>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
-
-  switch (ElementSize) {
-    case 4:
-      if (Is256Bit) {
-        vcvttps2dq(ToYMM(Dst), ToYMM(Vector));
-      } else {
-        vcvttps2dq(Dst, Vector);
-      }
-      break;
-    case 8:
-      if (Is256Bit) {
-        vcvttpd2dq(ToYMM(Dst), ToYMM(Vector));
-      } else {
-        vcvttpd2dq(Dst, Vector);
-      }
-      break;
-    default:
-      LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", ElementSize);
-      break;
-  }
-}
-
-DEF_OP(Vector_FToS) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToS>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
-
-  switch (ElementSize) {
-    case 4:
-      if (Is256Bit) {
-        vcvtps2dq(ToYMM(Dst), ToYMM(Vector));
-      } else {
-        vcvtps2dq(Dst, Vector);
-      }
-      break;
-    case 8:
-      if (Is256Bit) {
-        vcvtpd2dq(ToYMM(Dst), ToYMM(Vector));
-      } else {
-        vcvtpd2dq(Dst, Vector);
-      }
-      break;
-    default:
-      LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", ElementSize);
-      break;
-  }
-}
-
-DEF_OP(Vector_FToF) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToF>();
-  const auto OpSize = IROp->Size;
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-  const auto Conv = (ElementSize << 8) | Op->SrcElementSize;
-
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
-
-  switch (Conv) {
-    case 0x0804: { // Double <- Float
-      if (Is256Bit) {
-        vcvtps2pd(ToYMM(Dst), Vector);
-      } else {
-        vcvtps2pd(Dst, Vector);
-      }
-      break;
-    }
-    case 0x0408: { // Float <- Double
-      if (Is256Bit) {
-        vcvtpd2ps(Dst, ToYMM(Vector));
-      } else {
-        vcvtpd2ps(Dst, Vector);
-      }
-      break;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unknown Vector_FToF conversion type : 0x{:04x}", Conv);
-      break;
-  }
-}
-
-DEF_OP(Vector_FToI) {
-  const auto Op = IROp->C<IR::IROp_Vector_FToI>();
-  const auto OpSize = IROp->Size;
-
-  const uint8_t RoundMode = [Op] {
-    switch (Op->Round) {
-      case FEXCore::IR::Round_Nearest.Val:
-        return 0b0000'0'0'00;
-      case FEXCore::IR::Round_Negative_Infinity.Val:
-        return 0b0000'0'0'01;
-      case FEXCore::IR::Round_Positive_Infinity.Val:
-        return 0b0000'0'0'10;
-      case FEXCore::IR::Round_Towards_Zero.Val:
-        return 0b0000'0'0'11;
-      case FEXCore::IR::Round_Host.Val:
-        return 0b0000'0'1'00;
-      default:
-        LOGMAN_MSG_A_FMT("Unhandled rounding mode");
-        return 0;
-    }
-  }();
-
-  const auto ElementSize = Op->Header.ElementSize;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Vector = GetSrc(Op->Vector.ID());
-
-  switch (ElementSize) {
-    case 4:
-      if (Is256Bit) {
-        vroundps(ToYMM(Dst), ToYMM(Vector), RoundMode);
-      } else {
-        vroundps(Dst, Vector, RoundMode);
-      }
-      break;
-    case 8:
-      if (Is256Bit) {
-        vroundpd(ToYMM(Dst), ToYMM(Vector), RoundMode);
-      } else {
-        vroundpd(Dst, Vector, RoundMode);
-      }
-      break;
-    default:
-      LOGMAN_MSG_A_FMT("Unhandled element size: {}", ElementSize);
-      break;
-  }
-}
-
-#undef DEF_OP
-void X86JITCore::RegisterConversionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
-  REGISTER_OP(VINSGPR,         VInsGPR);
-  REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
-  REGISTER_OP(VDUPFROMGPR,     VDupFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
-  REGISTER_OP(FLOAT_FTOF,      Float_FToF);
-  REGISTER_OP(VECTOR_STOF,     Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZS,    Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOS,     Vector_FToS);
-  REGISTER_OP(VECTOR_FTOF,     Vector_FToF);
-  REGISTER_OP(VECTOR_FTOI,     Vector_FToI);
-#undef REGISTER_OP
-}
-}
-

External/FEXCore/Source/Interface/Core/JIT/x86_64/EncryptionOps.cpp

@@ -1,160 +0,0 @@
-/*
-$info$
-tags: backend|x86-64
-$end_info$
-*/
-
-#include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-#include <FEXCore/IR/IR.h>
-
-#include <array>
-#include <stdint.h>
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-
-DEF_OP(AESImc) {
-  auto Op = IROp->C<IR::IROp_VAESImc>();
-  vaesimc(GetDst(Node), GetSrc(Op->Vector.ID()));
-}
-
-DEF_OP(AESEnc) {
-  const auto Op = IROp->C<IR::IROp_VAESEnc>();
-  const auto OpSize = IROp->Size;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Key = GetSrc(Op->Key.ID());
-  const auto State = GetSrc(Op->State.ID());
-
-  if (Is256Bit) {
-    vaesenc(ToYMM(Dst), ToYMM(State), ToYMM(Key));
-  } else {
-    vaesenc(Dst, State, Key);
-  }
-}
-
-DEF_OP(AESEncLast) {
-  const auto Op = IROp->C<IR::IROp_VAESEncLast>();
-  const auto OpSize = IROp->Size;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Key = GetSrc(Op->Key.ID());
-  const auto State = GetSrc(Op->State.ID());
-
-  if (Is256Bit) {
-    vaesenclast(ToYMM(Dst), ToYMM(State), ToYMM(Key));
-  } else {
-    vaesenclast(Dst, State, Key);
-  }
-}
-
-DEF_OP(AESDec) {
-  const auto Op = IROp->C<IR::IROp_VAESDec>();
-  const auto OpSize = IROp->Size;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Key = GetSrc(Op->Key.ID());
-  const auto State = GetSrc(Op->State.ID());
-
-  if (Is256Bit) {
-    vaesdec(ToYMM(Dst), ToYMM(State), ToYMM(Key));
-  } else {
-    vaesdec(Dst, State, Key);
-  }
-}
-
-DEF_OP(AESDecLast) {
-  const auto Op = IROp->C<IR::IROp_VAESDecLast>();
-  const auto OpSize = IROp->Size;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Key = GetSrc(Op->Key.ID());
-  const auto State = GetSrc(Op->State.ID());
-
-  if (Is256Bit) {
-    vaesdeclast(ToYMM(Dst), ToYMM(State), ToYMM(Key));
-  } else {
-    vaesdeclast(Dst, State, Key);
-  }
-}
-
-DEF_OP(AESKeyGenAssist) {
-  auto Op = IROp->C<IR::IROp_VAESKeyGenAssist>();
-  vaeskeygenassist(GetDst(Node), GetSrc(Op->Src.ID()), Op->RCON);
-}
-
-DEF_OP(CRC32) {
-  auto Op = IROp->C<IR::IROp_CRC32>();
-  switch (IROp->Size) {
-  case 4:
-    mov(TMP1, GetSrc<RA_32>(Op->Src2.ID()));
-    mov(GetDst<RA_32>(Node), GetSrc<RA_32>(Op->Src1.ID()));
-  break;
-  case 8:
-    mov(TMP1, GetSrc<RA_64>(Op->Src2.ID()));
-    mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Src1.ID()));
-  break;
-  default: LOGMAN_MSG_A_FMT("Unknown CRC32 size: {}", IROp->Size);
-  }
-
-  switch (Op->SrcSize) {
-    case 1:
-      crc32(GetDst<RA_32>(Node).cvt32(), TMP1.cvt8());
-      break;
-    case 2:
-      crc32(GetDst<RA_32>(Node).cvt32(), TMP1.cvt16());
-      break;
-    case 4:
-      crc32(GetDst<RA_32>(Node).cvt32(), TMP1.cvt32());
-      break;
-    case 8:
-      crc32(GetDst<RA_64>(Node).cvt64(), TMP1.cvt64());
-      break;
-  }
-}
-
-DEF_OP(PCLMUL) {
-  const auto Op = IROp->C<IR::IROp_PCLMUL>();
-  const auto OpSize = IROp->Size;
-  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  const auto Dst = GetDst(Node);
-  const auto Src1 = GetSrc(Op->Src1.ID());
-  const auto Src2 = GetSrc(Op->Src2.ID());
-
-  switch (Op->Selector) {
-  case 0b00000000:
-  case 0b00000001:
-  case 0b00010000:
-  case 0b00010001:
-    if (Is256Bit) {
-      vpclmulqdq(ToYMM(Dst), ToYMM(Src1), ToYMM(Src2), Op->Selector);
-    } else {
-      vpclmulqdq(Dst, Src1, Src2, Op->Selector);
-    }
-    break;
-  default:
-    LOGMAN_MSG_A_FMT("Unknown PCLMUL selector: {}", Op->Selector);
-    break;
-  }
-}
-
-#undef DEF_OP
-void X86JITCore::RegisterEncryptionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
-  REGISTER_OP(VAESIMC,           AESImc);
-  REGISTER_OP(VAESENC,           AESEnc);
-  REGISTER_OP(VAESENCLAST,       AESEncLast);
-  REGISTER_OP(VAESDEC,           AESDec);
-  REGISTER_OP(VAESDECLAST,       AESDecLast);
-  REGISTER_OP(VAESKEYGENASSIST,  AESKeyGenAssist);
-  REGISTER_OP(CRC32,             CRC32);
-  REGISTER_OP(PCLMUL,            PCLMUL);
-#undef REGISTER_OP
-}
-}

External/FEXCore/Source/Interface/Core/JIT/x86_64/FlagOps.cpp

@@ -1,34 +0,0 @@
-/*
-$info$
-tags: backend|x86-64
-$end_info$
-*/
-
-#include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-
-#include <FEXCore/IR/IR.h>
-
-#include <array>
-#include <stdint.h>
-
-namespace FEXCore::CPU {
-
-#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-DEF_OP(GetHostFlag) {
-  auto Op = IROp->C<IR::IROp_GetHostFlag>();
-
-  mov(rax, GetSrc<RA_64>(Op->Value.ID()));
-  shr(rax, Op->Flag);
-  and_(rax, 1);
-  mov(GetDst<RA_64>(Node), rax);
-}
-
-#undef DEF_OP
-void X86JITCore::RegisterFlagHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
-  REGISTER_OP(GETHOSTFLAG, GetHostFlag);
-#undef REGISTER_OP
-}
-}
-

External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp

@@ -1,877 +0,0 @@
-/*
-$info$
-tags: backend|x86-64
-desc: Main glue logic of the x86-64 splatter backend
-$end_info$
-*/
-
-#include "Interface/Context/Context.h"
-#include "Interface/Core/LookupCache.h"
-
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-#include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/IR/PassManager.h"
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
-
-#include "Utils/MemberFunctionToPointer.h"
-
-#include <FEXCore/Core/CPUBackend.h>
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/IR/RegisterAllocationData.h>
-#include <FEXCore/Utils/Allocator.h>
-#include <FEXCore/Utils/EnumUtils.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/Profiler.h>
-#include <FEXCore/fextl/sstream.h>
-
-#include <algorithm>
-#include <array>
-#include <memory>
-#include <stddef.h>
-#include <stdint.h>
-#include <signal.h>
-#include <tuple>
-#include <unordered_map>
-#include <utility>
-
-// #define DEBUG_RA 1
-// #define DEBUG_CYCLES
-
-static constexpr size_t INITIAL_CODE_SIZE = 1024 * 1024 * 16;
-static constexpr size_t MAX_CODE_SIZE = 1024 * 1024 * 256;
-
-namespace {
-static void PrintValue(uint64_t Value) {
-  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
-}
-
-static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
-  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
-}
-}
-
-namespace FEXCore::CPU {
-
-void X86JITCore::PushRegs() {
-  const auto AVXRegSize = Core::CPUState::XMM_AVX_REG_SIZE;
-
-  sub(rsp, AVXRegSize * RAXMM_x.size());
-  for (size_t i = 0; i < RAXMM_x.size(); ++i) {
-    vmovups(ptr[rsp + i * AVXRegSize], ToYMM(RAXMM_x[i]));
-  }
-
-  for (const auto &Reg : RA64) {
-    push(Reg);
-  }
-
-  const auto NumPush = RA64.size();
-  if ((NumPush & 1) != 0) {
-    // Align
-    sub(rsp, 8);
-  }
-}
-
-void X86JITCore::PopRegs() {
-  const auto AVXRegSize = Core::CPUState::XMM_AVX_REG_SIZE;
-  const auto NumPush = RA64.size();
-
-  if ((NumPush & 1) != 0) {
-    // Align
-    add(rsp, 8);
-  }
-
-  for (uint32_t i = RA64.size(); i > 0; --i) {
-    pop(RA64[i - 1]);
-  }
-
-  for (size_t i = 0; i < RAXMM_x.size(); ++i) {
-    vmovups(ToYMM(RAXMM_x[i]), ptr[rsp + i * AVXRegSize]);
-  }
-
-  add(rsp, AVXRegSize * RAXMM_x.size());
-}
-
-void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) {
-  FallbackInfo Info;
-  if (!InterpreterOps::GetFallbackHandler(IROp, &Info)) {
-#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-    LOGMAN_MSG_A_FMT("Unhandled IR Op: {}", FEXCore::IR::GetName(IROp->Op));
-#endif
-  } else {
-    switch(Info.ABI) {
-      case FABI_VOID_U16: {
-        PushRegs();
-        mov(edi, GetSrc<RA_32>(IROp->Args[0].ID()));
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-        break;
-      }
-      case FABI_F80_F32:{
-        PushRegs();
-
-        movss(xmm0, GetSrc(IROp->Args[0].ID()));
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        pxor(GetDst(Node), GetDst(Node));
-        movq(GetDst(Node), rax);
-        pinsrw(GetDst(Node), edx, 4);
-      }
-      break;
-
-      case FABI_F80_F64:{
-        PushRegs();
-
-        movsd(xmm0, GetSrc(IROp->Args[0].ID()));
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        pxor(GetDst(Node), GetDst(Node));
-        movq(GetDst(Node), rax);
-        pinsrw(GetDst(Node), edx, 4);
-      }
-      break;
-
-      case FABI_F80_I16:
-      case FABI_F80_I32: {
-        PushRegs();
-
-        if (Info.ABI == FABI_F80_I16) {
-          movsx(rdi, GetSrc<RA_32>(IROp->Args[0].ID()).cvt16());
-        }
-        else {
-          mov(edi, GetSrc<RA_32>(IROp->Args[0].ID()));
-        }
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        pxor(GetDst(Node), GetDst(Node));
-        movq(GetDst(Node), rax);
-        pinsrw(GetDst(Node), edx, 4);
-      }
-      break;
-
-      case FABI_F32_F80:{
-        PushRegs();
-
-        movq(rdi, GetSrc(IROp->Args[0].ID()));
-        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        movss(GetDst(Node), xmm0);
-      }
-      break;
-
-      case FABI_F64_F80:{
-        PushRegs();
-
-        movq(rdi, GetSrc(IROp->Args[0].ID()));
-        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        movsd(GetDst(Node), xmm0);
-      }
-      break;
-
-      case FABI_F64_F64: {
-        PushRegs();
-
-        movsd(xmm0, GetSrc(IROp->Args[0].ID()));
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        movsd(GetDst(Node), xmm0);
-      }
-      break;
-
-      case FABI_F64_F64_F64: {
-        PushRegs();
-
-        movsd(xmm0, GetSrc(IROp->Args[0].ID()));
-        movsd(xmm1, GetSrc(IROp->Args[1].ID()));
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        movsd(GetDst(Node), xmm0);
-      }
-      break;
-
-      case FABI_I16_F80:{
-        PushRegs();
-
-        movq(rdi, GetSrc(IROp->Args[0].ID()));
-        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        movsx(GetDst<RA_64>(Node), ax);
-      }
-      break;
-      case FABI_I32_F80:{
-        PushRegs();
-
-        movq(rdi, GetSrc(IROp->Args[0].ID()));
-        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        mov(GetDst<RA_32>(Node), eax);
-      }
-      break;
-      case FABI_I64_F80:{
-        PushRegs();
-
-        movq(rdi, GetSrc(IROp->Args[0].ID()));
-        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        mov(GetDst<RA_64>(Node), rax);
-      }
-      break;
-      case FABI_I64_F80_F80:{
-        PushRegs();
-
-        movq(rdi, GetSrc(IROp->Args[0].ID()));
-        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);
-
-        movq(rdx, GetSrc(IROp->Args[1].ID()));
-        pextrq(rcx, GetSrc(IROp->Args[1].ID()), 1);
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        mov(GetDst<RA_64>(Node), rax);
-      }
-      break;
-      case FABI_F80_F80:{
-        PushRegs();
-
-        movq(rdi, GetSrc(IROp->Args[0].ID()));
-        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        pxor(GetDst(Node), GetDst(Node));
-        movq(GetDst(Node), rax);
-        pinsrw(GetDst(Node), edx, 4);
-      }
-      break;
-      case FABI_F80_F80_F80:{
-        PushRegs();
-
-        movq(rdi, GetSrc(IROp->Args[0].ID()));
-        pextrq(rsi, GetSrc(IROp->Args[0].ID()), 1);
-
-        movq(rdx, GetSrc(IROp->Args[1].ID()));
-        pextrq(rcx, GetSrc(IROp->Args[1].ID()), 1);
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        pxor(GetDst(Node), GetDst(Node));
-        movq(GetDst(Node), rax);
-        pinsrw(GetDst(Node), edx, 4);
-      }
-      break;
-
-      case FABI_I32_I64_I64_I128_I128_I16: {
-        PushRegs();
-
-        const auto Op = IROp->C<IR::IROp_VPCMPESTRX>();
-        const auto Control = Op->Control;
-
-        const auto LHS = GetSrc(Op->LHS.ID());
-        const auto RHS = GetSrc(Op->RHS.ID());
-        const auto SrcRAX = GetSrc<RA_64>(Op->RAX.ID());
-        const auto SrcRDX = GetSrc<RA_64>(Op->RDX.ID());
-
-        mov(rdi, SrcRAX);
-        mov(rsi, SrcRDX);
-
-        movq(rdx, LHS);
-        pextrq(rcx, LHS, 1);
-
-        movq(r8, RHS);
-        pextrq(r9, RHS, 1);
-
-        sub(rsp, 16);
-        mov(dword [rsp], Control);
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        add(rsp, 16);
-        PopRegs();
-
-        mov(GetDst<RA_32>(Node), rax);
-        break;
-      }
-
-      case FABI_I32_I128_I128_I16: {
-        PushRegs();
-
-        const auto Op = IROp->C<IR::IROp_VPCMPISTRX>();
-
-        const auto LHS = GetSrc(Op->LHS.ID());
-        const auto RHS = GetSrc(Op->RHS.ID());
-        const auto Control = Op->Control;
-
-        movq(rdi, LHS);
-        pextrq(rsi, LHS, 1);
-
-        movq(rdx, RHS);
-        pextrq(rcx, RHS, 1);
-
-        mov(r8, Control);
-
-        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
-
-        PopRegs();
-
-        mov(GetDst<RA_32>(Node), rax);
-        break;
-      }
-
-      case FABI_UNKNOWN:
-      default:
-#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-        LOGMAN_MSG_A_FMT("Unhandled IR Fallback ABI: {} {}",
-                         IR::GetName(IROp->Op), ToUnderlying(Info.ABI));
-#endif
-        break;
-    }
-  }
-}
-
-static uint64_t X86JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, uint64_t *record) {
-  auto Thread = Frame->Thread;
-  auto GuestRip = record[1];
-
-  auto HostCode = Thread->LookupCache->FindBlock(GuestRip);
-
-  if (!HostCode) {
-    Thread->CurrentFrame->State.rip = GuestRip;
-    return Frame->Pointers.Common.DispatcherLoopTop;
-  }
-
-  auto LinkerAddress = Frame->Pointers.Common.ExitFunctionLinker;
-  Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [record, LinkerAddress]{
-    // undo the link
-    record[0] = LinkerAddress;
-  });
-
-  record[0] = HostCode;
-  return HostCode;
-}
-
-void X86JITCore::Op_NoOp(IR::IROp_Header *IROp, IR::NodeID Node) {
-}
-
-X86JITCore::X86JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread)
-  : CPUBackend(Thread, INITIAL_CODE_SIZE, MAX_CODE_SIZE)
-  , CodeGenerator(0, this, nullptr) // this is not used here
-  , CTX {ctx} {
-
-  RAPass = Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA");
-
-  RAPass->AllocateRegisterSet(RegisterClasses);
-  RAPass->AddRegisters(FEXCore::IR::GPRClass, NumGPRs);
-  RAPass->AddRegisters(FEXCore::IR::FPRClass, NumXMMs);
-  RAPass->AddRegisters(FEXCore::IR::GPRPairClass, NumGPRPairs);
-
-  for (uint32_t i = 0; i < NumGPRPairs; ++i) {
-    RAPass->AddRegisterConflict(FEXCore::IR::GPRClass, i * 2,     FEXCore::IR::GPRPairClass, i);
-    RAPass->AddRegisterConflict(FEXCore::IR::GPRClass, i * 2 + 1, FEXCore::IR::GPRPairClass, i);
-  }
-
-  for (uint32_t i = 0; i < FEXCore::IR::IROps::OP_LAST + 1; ++i) {
-    OpHandlers[i] = &X86JITCore::Op_Unhandled;
-  }
-
-  RegisterALUHandlers();
-  RegisterAtomicHandlers();
-  RegisterBranchHandlers();
-  RegisterConversionHandlers();
-  RegisterFlagHandlers();
-  RegisterMemoryHandlers();
-  RegisterMiscHandlers();
-  RegisterMoveHandlers();
-  RegisterVectorHandlers();
-  RegisterEncryptionHandlers();
-
-  {
-    auto &Common = ThreadState->CurrentFrame->Pointers.Common;
-
-    Common.PrintValue = reinterpret_cast<uint64_t>(PrintValue);
-    Common.PrintVectorValue = reinterpret_cast<uint64_t>(PrintVectorValue);
-    Common.ThreadRemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadRemoveCodeEntryFromJit);
-    Common.CPUIDObj = reinterpret_cast<uint64_t>(&CTX->CPUID);
-
-    {
-      FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunFunction);
-      Common.CPUIDFunction = PMF.GetConvertedPointer();
-    }
-
-    {
-      FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunXCRFunction);
-      Common.XCRFunction = PMF.GetConvertedPointer();
-    }
-
-    Common.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
-    Common.SyscallHandlerFunc = reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall);
-    Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadExitFunctionLink<X86JITCore_ExitFunctionLink>);
-
-    // Fill in the fallback handlers
-    InterpreterOps::FillFallbackIndexPointers(Common.FallbackHandlerPointers);
-  }
-
-  // Must be done after Dispatcher init
-  ClearCache();
-}
-
-X86JITCore::~X86JITCore() {
-
-}
-
-void X86JITCore::EmitDetectionString() {
-  const char JITString[] = "FEXJIT::X86JITCore::";
-  for (char c : JITString) {
-    db(c);
-  }
-}
-
-void X86JITCore::ClearCache() {
-  auto CodeBuffer = GetEmptyCodeBuffer();
-  setNewBuffer(CodeBuffer->Ptr, CodeBuffer->Size);
-  EmitDetectionString();
-}
-
-IR::PhysicalRegister X86JITCore::GetPhys(IR::NodeID Node) const {
-  auto PhyReg = RAData->GetNodeRegister(Node);
-
-  LOGMAN_THROW_AA_FMT(PhyReg.Raw != 255, "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class);
-
-  return PhyReg;
-}
-
-bool X86JITCore::IsFPR(IR::NodeID Node) const {
-  return RAData->GetNodeRegister(Node).Class == IR::FPRClass;
-}
-
-bool X86JITCore::IsGPR(IR::NodeID Node) const {
-  return RAData->GetNodeRegister(Node).Class == IR::GPRClass;
-}
-
-bool X86JITCore::IsGPRPair(IR::NodeID Node) const {
-  return RAData->GetNodeRegister(Node).Class == IR::GPRPairClass;
-}
-
-template<uint8_t RAType>
-Xbyak::Reg X86JITCore::GetSrc(IR::NodeID Node) const {
-  // rax, rcx, rdx, rsi, r8, r9,
-  // r10
-  // Callee Saved
-  // rbx, rbp, r12, r13, r14, r15
-  auto PhyReg = GetPhys(Node);
-  if constexpr (RAType == RA_64)
-    return RA64[PhyReg.Reg].cvt64();
-  else if constexpr (RAType == RA_XMM)
-    return RAXMM[PhyReg.Reg];
-  else if constexpr (RAType == RA_32)
-    return RA64[PhyReg.Reg].cvt32();
-  else if constexpr (RAType == RA_16)
-    return RA64[PhyReg.Reg].cvt16();
-  else if constexpr (RAType == RA_8)
-    return RA64[PhyReg.Reg].cvt8();
-}
-
-template
-Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_64>(IR::NodeID Node) const;
-
-template
-Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_32>(IR::NodeID Node) const;
-
-template
-Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_16>(IR::NodeID Node) const;
-
-template
-Xbyak::Reg X86JITCore::GetSrc<X86JITCore::RA_8>(IR::NodeID Node) const;
-
-Xbyak::Xmm X86JITCore::GetSrc(IR::NodeID Node) const {
-  auto PhyReg = GetPhys(Node);
-  return RAXMM_x[PhyReg.Reg];
-}
-
-template<uint8_t RAType>
-Xbyak::Reg X86JITCore::GetDst(IR::NodeID Node) const {
-  auto PhyReg = GetPhys(Node);
-  if constexpr (RAType == RA_64)
-    return RA64[PhyReg.Reg].cvt64();
-  else if constexpr (RAType == RA_XMM)
-    return RAXMM[PhyReg.Reg];
-  else if constexpr (RAType == RA_32)
-    return RA64[PhyReg.Reg].cvt32();
-  else if constexpr (RAType == RA_16)
-    return RA64[PhyReg.Reg].cvt16();
-  else if constexpr (RAType == RA_8)
-    return RA64[PhyReg.Reg].cvt8();
-}
-
-template
-Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_64>(IR::NodeID Node) const;
-
-template
-Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_32>(IR::NodeID Node) const;
-
-template
-Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_16>(IR::NodeID Node) const;
-
-template
-Xbyak::Reg X86JITCore::GetDst<X86JITCore::RA_8>(IR::NodeID Node) const;
-
-template<uint8_t RAType>
-std::pair<Xbyak::Reg, Xbyak::Reg> X86JITCore::GetSrcPair(IR::NodeID Node) const {
-  auto PhyReg = GetPhys(Node);
-  if constexpr (RAType == RA_64)
-    return RA64Pair[PhyReg.Reg];
-  else if constexpr (RAType == RA_32)
-    return {RA64Pair[PhyReg.Reg].first.cvt32(), RA64Pair[PhyReg.Reg].second.cvt32()};
-}
-
-template
-std::pair<Xbyak::Reg, Xbyak::Reg> X86JITCore::GetSrcPair<X86JITCore::RA_64>(IR::NodeID Node) const;
-
-template
-std::pair<Xbyak::Reg, Xbyak::Reg> X86JITCore::GetSrcPair<X86JITCore::RA_32>(IR::NodeID Node) const;
-
-Xbyak::Xmm X86JITCore::GetDst(IR::NodeID Node) const {
-  auto PhyReg = GetPhys(Node);
-  return RAXMM_x[PhyReg.Reg];
-}
-
-bool X86JITCore::IsInlineConstant(const IR::OrderedNodeWrapper& WNode, uint64_t* Value) const {
-  auto OpHeader = IR->GetOp<IR::IROp_Header>(WNode);
-
-  if (OpHeader->Op == IR::IROps::OP_INLINECONSTANT) {
-    auto Op = OpHeader->C<IR::IROp_InlineConstant>();
-    if (Value) {
-      *Value = Op->Constant;
-    }
-    return true;
-  } else {
-    return false;
-  }
-}
-
-bool X86JITCore::IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value) const {
-  auto OpHeader = IR->GetOp<IR::IROp_Header>(WNode);
-
-  if (OpHeader->Op == IR::IROps::OP_INLINEENTRYPOINTOFFSET) {
-    auto Op = OpHeader->C<IR::IROp_InlineEntrypointOffset>();
-    if (Value) {
-      uint64_t Mask = ~0ULL;
-      uint8_t OpSize = OpHeader->Size;
-      if (OpSize == 4) {
-        Mask = 0xFFFF'FFFFULL;
-      }
-      *Value = (Entry + Op->Offset) & Mask;
-    }
-    return true;
-  } else {
-    return false;
-  }
-}
-
-std::tuple<X86JITCore::SetCC, X86JITCore::CMovCC, X86JITCore::JCC> X86JITCore::GetCC(IR::CondClassType cond) {
-    switch (cond.Val) {
-    case FEXCore::IR::COND_EQ:  return { &CodeGenerator::sete , &CodeGenerator::cmove , &CodeGenerator::je  };
-    case FEXCore::IR::COND_NEQ: return { &CodeGenerator::setne, &CodeGenerator::cmovne, &CodeGenerator::jne };
-    case FEXCore::IR::COND_SGE: return { &CodeGenerator::setge, &CodeGenerator::cmovge, &CodeGenerator::jge };
-    case FEXCore::IR::COND_SLT: return { &CodeGenerator::setl , &CodeGenerator::cmovl , &CodeGenerator::jl  };
-    case FEXCore::IR::COND_SGT: return { &CodeGenerator::setg , &CodeGenerator::cmovg , &CodeGenerator::jg  };
-    case FEXCore::IR::COND_SLE: return { &CodeGenerator::setle, &CodeGenerator::cmovle, &CodeGenerator::jle };
-    case FEXCore::IR::COND_UGE: return { &CodeGenerator::setae, &CodeGenerator::cmovae, &CodeGenerator::jae };
-    case FEXCore::IR::COND_ULT: return { &CodeGenerator::setb , &CodeGenerator::cmovb , &CodeGenerator::jb  };
-    case FEXCore::IR::COND_UGT: return { &CodeGenerator::seta , &CodeGenerator::cmova , &CodeGenerator::ja  };
-    case FEXCore::IR::COND_ULE: return { &CodeGenerator::setna, &CodeGenerator::cmovna, &CodeGenerator::jna };
-
-	  case FEXCore::IR::COND_FLU:  return { &CodeGenerator::setb , &CodeGenerator::cmovb , &CodeGenerator::jb  };
-	  case FEXCore::IR::COND_FGE:  return { &CodeGenerator::setae, &CodeGenerator::cmovae, &CodeGenerator::jae };
-	  case FEXCore::IR::COND_FLEU: return { &CodeGenerator::setna, &CodeGenerator::cmovna, &CodeGenerator::jna };
-	  case FEXCore::IR::COND_FGT:  return { &CodeGenerator::seta , &CodeGenerator::cmova , &CodeGenerator::ja  };
-	  case FEXCore::IR::COND_FU:   return { &CodeGenerator::setp , &CodeGenerator::cmovp , &CodeGenerator::jp  };
-	  case FEXCore::IR::COND_FNU:  return { &CodeGenerator::setnp, &CodeGenerator::cmovnp, &CodeGenerator::jnp };
-
-    case FEXCore::IR::COND_MI:
-    case FEXCore::IR::COND_PL:
-    case FEXCore::IR::COND_VS:
-    case FEXCore::IR::COND_VC:
-    default:
-      LOGMAN_MSG_A_FMT("Unsupported compare type");
-      break;
-  }
-
-  // Hope for the best
-  return { &CodeGenerator::sete , &CodeGenerator::cmove , &CodeGenerator::je  };
-}
-
-CPUBackend::CompiledCode X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) {
-
-  FEXCORE_PROFILE_SCOPED("x86::CompileCode");
-  JumpTargets.clear();
-  uint32_t SSACount = IR->GetSSACount();
-
-  this->Entry = Entry;
-  this->RAData = RAData;
-  this->DebugData = DebugData;
-
-  // Fairly excessive buffer range to make sure we don't overflow
-  uint32_t BufferRange = SSACount * 16 + GDBEnabled * Dispatcher::MaxGDBPauseCheckSize;
-  if ((getSize() + BufferRange) > CurrentCodeBuffer->Size) {
-    CTX->ClearCodeCache(ThreadState);
-  }
-
-  CodeData.BlockBegin = getCurr<uint8_t*>();
-
-  // Put the code header at the start of the data block.
-  Label JITCodeHeaderLabel{};
-  L(JITCodeHeaderLabel);
-
-  JITCodeHeader *CodeHeader = getCurr<JITCodeHeader *>();
-  setSize(getSize() + sizeof(JITCodeHeader));
-
-  CodeData.BlockEntry = getCurr<uint8_t*>();
-
-  // Get the address of the JITCodeHeader and store in to the core state.
-  // Only two instructions, so very low overhead.
-  lea(TMP1, ptr [rip + JITCodeHeaderLabel]);
-  mov(qword [STATE + offsetof(FEXCore::Core::CPUState, InlineJITBlockHeader)], TMP1);
-
-  CursorEntry = getSize();
-  this->IR = IR;
-
-  if (GDBEnabled) {
-    auto GDBSize = CTX->Dispatcher->GenerateGDBPauseCheck(CodeData.BlockBegin, Entry);
-    setSize(getSize() + GDBSize);
-  }
-
-  LOGMAN_THROW_AA_FMT(RAData != nullptr, "Needs RA");
-
-  SpillSlots = RAData->SpillSlots();
-
-  if (SpillSlots) {
-    sub(rsp, SpillSlots * MaxSpillSlotSize);
-  }
-
-#ifdef BLOCKSTATS
-  BlockSamplingData::BlockData *SamplingData = CTX->BlockData->GetBlockData(Entry);
-  if (GetSamplingData) {
-    mov(rcx, reinterpret_cast<uintptr_t>(SamplingData));
-    rdtsc();
-    shl(rdx, 32);
-    or_(rax, rdx);
-    mov(qword [rcx + offsetof(BlockSamplingData::BlockData, Start)], rax);
-  }
-
-  auto ExitBlock = [&]() {
-    if (GetSamplingData) {
-      mov(rcx, reinterpret_cast<uintptr_t>(SamplingData));
-      // Get time
-      rdtsc();
-      shl(rdx, 32);
-      or_(rax, rdx);
-
-      // Calculate time spent in block
-      mov(rdx, qword [rcx + offsetof(BlockSamplingData::BlockData, Start)]);
-      sub(rax, rdx);
-
-      // Add time to total time
-      add(qword [rcx + offsetof(BlockSamplingData::BlockData, TotalTime)], rax);
-
-      // Increment call count
-      inc(qword [rcx + offsetof(BlockSamplingData::BlockData, TotalCalls)]);
-
-      // Calculate min
-      mov(rdx, qword [rcx + offsetof(BlockSamplingData::BlockData, Min)]);
-      cmp(rdx, rax);
-      cmova(rdx, rax);
-      mov(qword [rcx + offsetof(BlockSamplingData::BlockData, Min)], rdx);
-
-      // Calculate max
-      mov(rdx, qword [rcx + offsetof(BlockSamplingData::BlockData, Max)]);
-      cmp(rdx, rax);
-      cmovb(rdx, rax);
-      mov(qword [rcx + offsetof(BlockSamplingData::BlockData, Max)], rdx);
-    }
-  };
-#endif
-
-  PendingTargetLabel = nullptr;
-
-  for (auto [BlockNode, BlockHeader] : IR->GetBlocks()) {
-    using namespace FEXCore::IR;
-#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-    auto BlockIROp = BlockHeader->CW<IROp_CodeBlock>();
-    LOGMAN_THROW_AA_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
-#endif
-
-    auto BlockStartHostCode = getCurr<uint8_t *>();
-    {
-      const auto Node = IR->GetID(BlockNode);
-      const auto IsTarget = JumpTargets.try_emplace(Node).first;
-
-      // if there is a pending branch, and it is not fall-through
-      if (PendingTargetLabel && PendingTargetLabel != &IsTarget->second) {
-        jmp(*PendingTargetLabel, T_NEAR);
-      }
-      PendingTargetLabel = nullptr;
-
-      L(IsTarget->second);
-    }
-
-    for (auto [CodeNode, IROp] : IR->GetCode(BlockNode)) {
-      #ifdef DEBUG_RA
-      if (IROp->Op != IR::OP_BEGINBLOCK &&
-          IROp->Op != IR::OP_CONDJUMP &&
-          IROp->Op != IR::OP_JUMP) {
-        fextl::stringstream Inst;
-        auto Name = FEXCore::IR::GetName(IROp->Op);
-
-        if (IROp->HasDest) {
-          uint64_t PhysReg = RAPass->GetNodeRegister(Node);
-          if (PhysReg >= GPRPairBase)
-            Inst << "\tPair" << GetPhys(Node) << " = " << Name << " ";
-          else if (PhysReg >= XMMBase)
-            Inst << "\tXMM" << GetPhys(Node) << " = " << Name << " ";
-          else
-            Inst << "\tReg" << GetPhys(Node) << " = " << Name << " ";
-        }
-        else {
-          Inst << "\t" << Name << " ";
-        }
-
-        const uint8_t NumArgs = IR::GetArgs(IROp->Op);
-        for (uint8_t i = 0; i < NumArgs; ++i) {
-          const auto ArgNode = IROp->Args[i].ID();
-          const uint64_t PhysReg = RAPass->GetNodeRegister(ArgNode);
-          if (PhysReg >= GPRPairBase)
-            Inst << "Pair" << GetPhys(ArgNode) << (i + 1 == NumArgs ? "" : ", ");
-          else if (PhysReg >= XMMBase)
-            Inst << "XMM" << GetPhys(ArgNode) << (i + 1 == NumArgs ? "" : ", ");
-          else
-            Inst << "Reg" << GetPhys(ArgNode) << (i + 1 == NumArgs ? "" : ", ");
-        }
-
-        LogMan::Msg::DFmt("{}", Inst.str());
-      }
-      #endif
-      const auto ID = IR->GetID(CodeNode);
-
-      // Execute handler
-      OpHandler Handler = OpHandlers[IROp->Op];
-      (this->*Handler)(IROp, ID);
-    }
-
-    if (DebugData) {
-      DebugData->Subblocks.push_back({
-        static_cast<uint32_t>(BlockStartHostCode - CodeData.BlockBegin),
-        static_cast<uint32_t>(getCurr<uint8_t *>() - BlockStartHostCode)
-      });
-    }
-  }
-
-  // Make sure last branch is generated. It certainly can't be eliminated here.
-  if (PendingTargetLabel)
-  {
-    jmp(*PendingTargetLabel, T_NEAR);
-  }
-  PendingTargetLabel = nullptr;
-
-  // Add the JitCodeTail
-  auto JITBlockTailLocation = getCurr<uint8_t *>();
-  auto JITBlockTail = getCurr<JITCodeTail*>();
-  setSize(getSize() + sizeof(JITCodeTail));
-
-  auto JITRIPEntriesLocation = getCurr<uint8_t *>();
-  auto JITRIPEntries = getCurr<JITRIPReconstructEntries*>();
-
-  setSize(getSize() + sizeof(JITRIPReconstructEntries) * DebugData->GuestOpcodes.size());
-
-  // Put the block's RIP entry in the tail.
-  // This will be used for RIP reconstruction in the future.
-  // TODO: This needs to be a data RIP relocation once code caching works.
-  //   Current relocation code doesn't support this feature yet.
-  JITBlockTail->RIP = Entry;
-
-  {
-    // Store the RIP entries.
-    JITBlockTail->NumberOfRIPEntries = DebugData->GuestOpcodes.size();
-    JITBlockTail->OffsetToRIPEntries = JITRIPEntriesLocation - JITBlockTailLocation;
-    uintptr_t CurrentRIPOffset = 0;
-    uint64_t CurrentPCOffset = 0;
-    for (size_t i = 0; i < DebugData->GuestOpcodes.size(); i++) {
-      const auto &GuestOpcode = DebugData->GuestOpcodes[i];
-      auto &RIPEntry = JITRIPEntries[i];
-      RIPEntry.HostPCOffset = GuestOpcode.HostEntryOffset - CurrentPCOffset;
-      RIPEntry.GuestRIPOffset = GuestOpcode.GuestEntryOffset - CurrentRIPOffset;
-      CurrentPCOffset = GuestOpcode.HostEntryOffset;
-      CurrentRIPOffset = GuestOpcode.GuestEntryOffset;
-    }
-  }
-
-  CodeHeader->OffsetToBlockTail = JITBlockTailLocation - CodeData.BlockBegin;
-
-  CodeData.Size = getCurr<uint8_t*>() - CodeData.BlockBegin;
-
-  JITBlockTail->Size = CodeData.Size;
-
-  this->IR = nullptr;
-
-  ready();
-
-  if (DebugData) {
-    DebugData->HostCodeSize = CodeData.Size;
-    DebugData->Relocations = &Relocations;
-  }
-
-  return CodeData;
-}
-
-fextl::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  return fextl::make_unique<X86JITCore>(ctx, Thread);
-}
-
-CPUBackendFeatures GetX86JITBackendFeatures() {
-  return CPUBackendFeatures { };
-}
-
-}

External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h

@@ -1,474 +0,0 @@
-/*
-$info$
-tags: backend|x86-64
-$end_info$
-*/
-
-#pragma once
-
-#include <FEXCore/IR/RegisterAllocationData.h>
-#include "Interface/Core/BlockSamplingData.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-#include "Interface/Core/ObjectCache/Relocations.h"
-
-using namespace Xbyak;
-
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/CPUBackend.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/Utils/MathUtils.h>
-#include <FEXCore/fextl/string.h>
-#include <FEXCore/fextl/unordered_map.h>
-#include <FEXCore/fextl/vector.h>
-
-#include "Interface/IR/Passes/RegisterAllocationPass.h"
-
-#include <tuple>
-
-namespace FEXCore::CPU {
-
-// Temp registers
-// rax, rcx, rdx, rsi, r8, r9,
-// r10, r11
-//
-// Callee Saved
-// rbx, rbp, r12, r13, r14, r15
-//
-// 1St Argument: rdi <ThreadState>
-// XMM:
-// All temp
-#define STATE r14
-#define TMP1 rax
-#define TMP2 rcx
-#define TMP3 rdx
-#define TMP4 rdi
-#define TMP5 rbx
-using namespace Xbyak::util;
-const std::array<Xbyak::Reg, 9> RA64 = { rsi, r8, r9, r10, r11, rbp, r12, r13, r15 };
-const std::array<std::pair<Xbyak::Reg, Xbyak::Reg>, 4> RA64Pair = {{ {rsi, r8}, {r9, r10}, {r11, rbp}, {r12, r13} }};
-const std::array<Xbyak::Reg, 11> RAXMM = { xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10, xmm11};
-const std::array<Xbyak::Xmm, 11> RAXMM_x = {  xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10, xmm11};
-
-class X86JITCore final : public CPUBackend, public Xbyak::CodeGenerator {
-public:
-  explicit X86JITCore(FEXCore::Context::ContextImpl *ctx,
-                      FEXCore::Core::InternalThreadState *Thread);
-  ~X86JITCore() override;
-
-  [[nodiscard]] fextl::string GetName() override { return "JIT"; }
-
-  [[nodiscard]] CPUBackend::CompiledCode CompileCode(uint64_t Entry,
-                                  FEXCore::IR::IRListView const *IR,
-                                  FEXCore::Core::DebugData *DebugData,
-                                  FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) override;
-
-  [[nodiscard]] void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
-
-  [[nodiscard]] bool NeedsOpDispatch() override { return true; }
-
-  void ClearCache() override;
-
-  void ClearRelocations() override { Relocations.clear(); }
-
-private:
-
-  /**
-   * @name Relocations
-   * @{ */
-    uint64_t GetNamedSymbolLiteral(FEXCore::CPU::RelocNamedSymbolLiteral::NamedSymbol Op);
-    void LoadConstantWithPadding(Xbyak::Reg Reg, uint64_t Constant);
-
-    /**
-     * @brief A literal pair relocation object for named symbol literals
-     */
-    struct NamedSymbolLiteralPair {
-      Label Offset;
-      Relocation MoveABI{};
-    };
-
-    /**
-     * @brief Inserts a thunk relocation
-     *
-     * @param Reg - The GPR to move the thunk handler in to
-     * @param Sum - The hash of the thunk
-     */
-    void InsertNamedThunkRelocation(Xbyak::Reg Reg, const IR::SHA256Sum &Sum);
-
-    /**
-     * @brief Inserts a guest GPR move relocation
-     *
-     * @param Reg - The GPR to move the guest RIP in to
-     * @param Constant - The guest RIP that will be relocated
-     */
-    void InsertGuestRIPMove(Xbyak::Reg Reg, uint64_t Constant);
-
-    /**
-     * @brief Inserts a named symbol as a literal in memory
-     *
-     * Need to use `PlaceNamedSymbolLiteral` with the return value to place the literal in the desired location
-     *
-     * @param Op The named symbol to place
-     *
-     * @return A temporary `NamedSymbolLiteralPair`
-     */
-    NamedSymbolLiteralPair InsertNamedSymbolLiteral(FEXCore::CPU::RelocNamedSymbolLiteral::NamedSymbol Op);
-
-    /**
-     * @brief Place the named symbol literal relocation in memory
-     *
-     * @param Lit - Which literal to place
-     */
-
-    void PlaceNamedSymbolLiteral(NamedSymbolLiteralPair &Lit);
-
-    fextl::vector<FEXCore::CPU::Relocation> Relocations;
-
-    ///< Relocation code loading
-    bool ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uint64_t CursorEntry, size_t NumRelocations, const char* EntryRelocations);
-
-    /**
-    * @brief Current guest RIP entrypoint
-    */
-    uint64_t CursorEntry{};
-  /**  @} */
-
-  Label* PendingTargetLabel{};
-  FEXCore::Context::ContextImpl *CTX;
-  FEXCore::IR::IRListView const *IR;
-  uint64_t Entry;
-  CPUBackend::CompiledCode CodeData{};
-
-  fextl::unordered_map<IR::NodeID, Label> JumpTargets;
-  Xbyak::util::Cpu Features{};
-
-  bool MemoryDebug = false;
-
-  /**
-   * @name Register Allocation
-   * @{ */
-  constexpr static uint32_t NumGPRs = RA64.size(); // 4 is the minimum required for GPR ops
-  constexpr static uint32_t NumXMMs = RAXMM.size();
-  constexpr static uint32_t NumGPRPairs = RA64Pair.size();
-  constexpr static uint32_t RegisterClasses = 6;
-
-  constexpr static uint64_t GPRBase = (0ULL << 32);
-  constexpr static uint64_t XMMBase = (1ULL << 32);
-  constexpr static uint64_t GPRPairBase = (2ULL << 32);
-
-  /**  @} */
-
-  constexpr static uint8_t RA_8 = 0;
-  constexpr static uint8_t RA_16 = 1;
-  constexpr static uint8_t RA_32 = 2;
-  constexpr static uint8_t RA_64 = 3;
-  constexpr static uint8_t RA_XMM = 4;
-
-  [[nodiscard]] IR::PhysicalRegister GetPhys(IR::NodeID Node) const;
-
-  [[nodiscard]] bool IsFPR(IR::NodeID Node) const;
-  [[nodiscard]] bool IsGPR(IR::NodeID Node) const;
-  [[nodiscard]] bool IsGPRPair(IR::NodeID Node) const;
-
-  template<uint8_t RAType>
-  [[nodiscard]] Xbyak::Reg GetSrc(IR::NodeID Node) const;
-  template<uint8_t RAType>
-  [[nodiscard]] std::pair<Xbyak::Reg, Xbyak::Reg> GetSrcPair(IR::NodeID Node) const;
-
-  template<uint8_t RAType>
-  [[nodiscard]] Xbyak::Reg GetDst(IR::NodeID Node) const;
-
-  [[nodiscard]] Xbyak::Xmm GetSrc(IR::NodeID Node) const;
-  [[nodiscard]] Xbyak::Xmm GetDst(IR::NodeID Node) const;
-
-  [[nodiscard]] static Xbyak::Ymm ToYMM(const Xbyak::Xmm& xmm) {
-    return Xbyak::Ymm{xmm.getIdx()};
-  }
-
-  [[nodiscard]] Xbyak::RegExp GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset,
-                                            IR::MemOffsetType OffsetType, uint8_t OffsetScale) const;
-
-  [[nodiscard]] bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr) const;
-  [[nodiscard]] bool IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value) const;
-
-  IR::RegisterAllocationPass *RAPass;
-  FEXCore::IR::RegisterAllocationData *RAData;
-  FEXCore::Core::DebugData *DebugData;
-
-#ifdef BLOCKSTATS
-  bool GetSamplingData {true};
-#endif
-
-  static uint64_t ExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, uint64_t *record);
-
-  // This is purely a debugging aid for developers to see if they are in JIT code space when inspecting raw memory
-  void EmitDetectionString();
-
-  uint32_t SpillSlots{};
-
-  using SetCC = void (X86JITCore::*)(const Operand& op);
-  using CMovCC = void (X86JITCore::*)(const Reg& reg, const Operand& op);
-  using JCC = void (X86JITCore::*)(const Label& label, LabelType type);
-
-  std::tuple<SetCC, CMovCC, JCC> GetCC(IR::CondClassType cond);
-
-  using OpHandler = void (X86JITCore::*)(IR::IROp_Header *IROp, IR::NodeID Node);
-  std::array<OpHandler, IR::IROps::OP_LAST + 1> OpHandlers {};
-  void RegisterALUHandlers();
-  void RegisterAtomicHandlers();
-  void RegisterBranchHandlers();
-  void RegisterConversionHandlers();
-  void RegisterFlagHandlers();
-  void RegisterMemoryHandlers();
-  void RegisterMiscHandlers();
-  void RegisterMoveHandlers();
-  void RegisterVectorHandlers();
-  void RegisterEncryptionHandlers();
-
-  void PushRegs();
-  void PopRegs();
-#define DEF_OP(x) void Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-
-  ///< Unhandled handler
-  DEF_OP(Unhandled);
-
-  ///< No-op Handler
-  DEF_OP(NoOp);
-
-  ///< ALU Ops
-  DEF_OP(TruncElementPair);
-  DEF_OP(Constant);
-  DEF_OP(EntrypointOffset);
-  DEF_OP(InlineConstant);
-  DEF_OP(InlineEntrypointOffset);
-  DEF_OP(CycleCounter);
-  DEF_OP(Add);
-  DEF_OP(Sub);
-  DEF_OP(Neg);
-  DEF_OP(Abs);
-  DEF_OP(Mul);
-  DEF_OP(UMul);
-  DEF_OP(Div);
-  DEF_OP(UDiv);
-  DEF_OP(Rem);
-  DEF_OP(URem);
-  DEF_OP(MulH);
-  DEF_OP(UMulH);
-  DEF_OP(Or);
-  DEF_OP(And);
-  DEF_OP(Andn);
-  DEF_OP(Xor);
-  DEF_OP(Lshl);
-  DEF_OP(Lshr);
-  DEF_OP(Ashr);
-  DEF_OP(Rol);
-  DEF_OP(Ror);
-  DEF_OP(Extr);
-  DEF_OP(PDep);
-  DEF_OP(PExt);
-  DEF_OP(LDiv);
-  DEF_OP(LUDiv);
-  DEF_OP(LRem);
-  DEF_OP(LURem);
-  DEF_OP(Zext);
-  DEF_OP(Not);
-  DEF_OP(Popcount);
-  DEF_OP(FindLSB);
-  DEF_OP(FindMSB);
-  DEF_OP(FindTrailingZeros);
-  DEF_OP(CountLeadingZeroes);
-  DEF_OP(Rev);
-  DEF_OP(Bfi);
-  DEF_OP(Bfe);
-  DEF_OP(Sbfe);
-  DEF_OP(Select);
-  DEF_OP(VExtractToGPR);
-  DEF_OP(Float_ToGPR_ZS);
-  DEF_OP(Float_ToGPR_S);
-  DEF_OP(FCmp);
-  DEF_OP(F80Cmp);
-
-  ///< Atomic ops
-  DEF_OP(CASPair);
-  DEF_OP(CAS);
-  DEF_OP(AtomicAdd);
-  DEF_OP(AtomicSub);
-  DEF_OP(AtomicAnd);
-  DEF_OP(AtomicOr);
-  DEF_OP(AtomicXor);
-  DEF_OP(AtomicSwap);
-  DEF_OP(AtomicFetchAdd);
-  DEF_OP(AtomicFetchSub);
-  DEF_OP(AtomicFetchAnd);
-  DEF_OP(AtomicFetchOr);
-  DEF_OP(AtomicFetchXor);
-  DEF_OP(AtomicFetchNeg);
-
-  ///< Branch ops
-  DEF_OP(CallbackReturn);
-  DEF_OP(ExitFunction);
-  DEF_OP(Jump);
-  DEF_OP(CondJump);
-  DEF_OP(Syscall);
-  DEF_OP(Thunk);
-  DEF_OP(ValidateCode);
-  DEF_OP(ThreadRemoveCodeEntry);
-  DEF_OP(CPUID);
-  DEF_OP(XGETBV);
-
-  ///< Conversion ops
-  DEF_OP(VInsGPR);
-  DEF_OP(VCastFromGPR);
-  DEF_OP(VDupFromGPR);
-  DEF_OP(Float_FromGPR_S);
-  DEF_OP(Float_FToF);
-  DEF_OP(Vector_UToF);
-  DEF_OP(Vector_SToF);
-  DEF_OP(Vector_FToZS);
-  DEF_OP(Vector_FToS);
-  DEF_OP(Vector_FToF);
-  DEF_OP(Vector_FToI);
-
-  ///< Flag ops
-  DEF_OP(GetHostFlag);
-
-  ///< Memory ops
-  DEF_OP(LoadContext);
-  DEF_OP(StoreContext);
-  DEF_OP(LoadRegister);
-  DEF_OP(StoreRegister);
-  DEF_OP(LoadContextIndexed);
-  DEF_OP(StoreContextIndexed);
-  DEF_OP(SpillRegister);
-  DEF_OP(FillRegister);
-  DEF_OP(LoadFlag);
-  DEF_OP(StoreFlag);
-  DEF_OP(LoadMem);
-  DEF_OP(StoreMem);
-  DEF_OP(VLoadVectorMasked);
-  DEF_OP(VStoreVectorMasked);
-  DEF_OP(MemSet);
-  DEF_OP(MemCpy);
-  DEF_OP(CacheLineClear);
-  DEF_OP(CacheLineClean);
-  DEF_OP(CacheLineZero);
-
-  ///< Misc ops
-  DEF_OP(GuestOpcode);
-  DEF_OP(Fence);
-  DEF_OP(Break);
-  DEF_OP(Phi);
-  DEF_OP(PhiValue);
-  DEF_OP(Print);
-  DEF_OP(GetRoundingMode);
-  DEF_OP(SetRoundingMode);
-  DEF_OP(ProcessorID);
-  DEF_OP(RDRAND);
-  DEF_OP(Yield);
-
-  ///< Move ops
-  DEF_OP(ExtractElementPair);
-  DEF_OP(CreateElementPair);
-
-  ///< Vector ops
-  DEF_OP(VectorZero);
-  DEF_OP(VectorImm);
-  DEF_OP(VMov);
-  DEF_OP(VAnd);
-  DEF_OP(VBic);
-  DEF_OP(VOr);
-  DEF_OP(VXor);
-  DEF_OP(VAdd);
-  DEF_OP(VSub);
-  DEF_OP(VUQAdd);
-  DEF_OP(VUQSub);
-  DEF_OP(VSQAdd);
-  DEF_OP(VSQSub);
-  DEF_OP(VAddP);
-  DEF_OP(VAddV);
-  DEF_OP(VUMinV);
-  DEF_OP(VURAvg);
-  DEF_OP(VAbs);
-  DEF_OP(VPopcount);
-  DEF_OP(VFAdd);
-  DEF_OP(VFAddP);
-  DEF_OP(VFSub);
-  DEF_OP(VFMul);
-  DEF_OP(VFDiv);
-  DEF_OP(VFMin);
-  DEF_OP(VFMax);
-  DEF_OP(VFRecp);
-  DEF_OP(VFSqrt);
-  DEF_OP(VFRSqrt);
-  DEF_OP(VNeg);
-  DEF_OP(VFNeg);
-  DEF_OP(VNot);
-  DEF_OP(VUMin);
-  DEF_OP(VSMin);
-  DEF_OP(VUMax);
-  DEF_OP(VSMax);
-  DEF_OP(VZip);
-  DEF_OP(VZip2);
-  DEF_OP(VUnZip);
-  DEF_OP(VUnZip2);
-  DEF_OP(VTrn);
-  DEF_OP(VTrn2);
-  DEF_OP(VBSL);
-  DEF_OP(VCMPEQ);
-  DEF_OP(VCMPEQZ);
-  DEF_OP(VCMPGT);
-  DEF_OP(VCMPGTZ);
-  DEF_OP(VCMPLTZ);
-  DEF_OP(VFCMPEQ);
-  DEF_OP(VFCMPNEQ);
-  DEF_OP(VFCMPLT);
-  DEF_OP(VFCMPGT);
-  DEF_OP(VFCMPLE);
-  DEF_OP(VFCMPORD);
-  DEF_OP(VFCMPUNO);
-  DEF_OP(VUShl);
-  DEF_OP(VUShr);
-  DEF_OP(VSShr);
-  DEF_OP(VUShlS);
-  DEF_OP(VUShrS);
-  DEF_OP(VSShrS);
-  DEF_OP(VInsElement);
-  DEF_OP(VDupElement);
-  DEF_OP(VExtr);
-  DEF_OP(VUShrI);
-  DEF_OP(VSShrI);
-  DEF_OP(VShlI);
-  DEF_OP(VUShrNI);
-  DEF_OP(VUShrNI2);
-  DEF_OP(VSXTL);
-  DEF_OP(VSXTL2);
-  DEF_OP(VUXTL);
-  DEF_OP(VUXTL2);
-  DEF_OP(VSQXTN);
-  DEF_OP(VSQXTN2);
-  DEF_OP(VSQXTUN);
-  DEF_OP(VSQXTUN2);
-  DEF_OP(VMul);
-  DEF_OP(VUMull);
-  DEF_OP(VSMull);
-  DEF_OP(VUMull2);
-  DEF_OP(VSMull2);
-  DEF_OP(VUABDL);
-  DEF_OP(VUABDL2);
-  DEF_OP(VTBL1);
-  DEF_OP(VRev64);
-
-  ///< Encryption ops
-  DEF_OP(AESImc);
-  DEF_OP(AESEnc);
-  DEF_OP(AESEncLast);
-  DEF_OP(AESDec);
-  DEF_OP(AESDecLast);
-  DEF_OP(AESKeyGenAssist);
-  DEF_OP(CRC32);
-  DEF_OP(PCLMUL);
-#undef DEF_OP
-};
-
-}

External/FEXCore/Source/Interface/Core/JIT/x86_64/MiscOps.cpp

@@ -1,191 +0,0 @@
-/*
-$info$
-tags: backend|x86-64
-$end_info$
-*/
-
-#include "Interface/Context/Context.h"
-#include "Interface/Core/Dispatcher/Dispatcher.h"
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-#include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "FEXCore/Debug/InternalThreadState.h"
-
-#include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/IR/IR.h>
-
-#include <array>
-#include <stddef.h>
-#include <stdint.h>
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-
-DEF_OP(GuestOpcode) {
-  auto Op = IROp->C<IR::IROp_GuestOpcode>();
-  // metadata
-  DebugData->GuestOpcodes.push_back({Op->GuestEntryOffset, getCurr<uint8_t*>() - CodeData.BlockBegin});
-}
-
-DEF_OP(Fence) {
-  auto Op = IROp->C<IR::IROp_Fence>();
-  switch (Op->Fence) {
-    case IR::Fence_Load.Val:
-      lfence();
-      break;
-    case IR::Fence_LoadStore.Val:
-      mfence();
-      break;
-    case IR::Fence_Store.Val:
-      sfence();
-      break;
-    default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
-  }
-}
-
-#ifndef _WIN32
-DEF_OP(Break) {
-  auto Op = IROp->C<IR::IROp_Break>();
-
-  if (SpillSlots) {
-    add(rsp, SpillSlots * MaxSpillSlotSize);
-  }
-
-  Core::CpuStateFrame::SynchronousFaultDataStruct State = {
-    .FaultToTopAndGeneratedException = 1,
-    .Signal = Op->Reason.Signal,
-    .TrapNo = Op->Reason.TrapNumber,
-    .si_code = Op->Reason.si_code,
-    .err_code = Op->Reason.ErrorRegister,
-  };
-
-  uint64_t Constant{};
-  memcpy(&Constant, &State, sizeof(State));
-
-  mov(TMP1, Constant);
-  mov(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData)], TMP1);
-
-  switch (Op->Reason.Signal) {
-  case SIGILL:
-    jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGILL)]);
-    break;
-  case SIGTRAP:
-    jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)]);
-    break;
-  case SIGSEGV:
-    jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGSEGV)]);
-    break;
-  default:
-    jmp(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP)]);
-    break;
-  }
-}
-#else
-DEF_OP(Break) {
-  ERROR_AND_DIE_FMT("Unsupported");
-}
-#endif
-
-DEF_OP(GetRoundingMode) {
-  auto Dst = GetDst<RA_32>(Node);
-  sub(rsp, 4);
-  // Only stores to memory
-  stmxcsr(dword [rsp]);
-  mov(Dst, dword [rsp]);
-  add(rsp, 4);
-  shr(Dst, 13);
-}
-
-DEF_OP(SetRoundingMode) {
-  auto Op = IROp->C<IR::IROp_SetRoundingMode>();
-  auto Src = GetSrc<RA_32>(Op->RoundMode.ID());
-
-  // Load old mxcsr
-  // Only stores to memory
-  sub(rsp, 4);
-  stmxcsr(dword [rsp]);
-  mov(TMP1.cvt32(), dword [rsp]);
-
-  // Insert the new rounding mode
-  and_(TMP1.cvt32(), ~(0b111 << 13));
-  mov(TMP2.cvt32(), Src);
-  shl(TMP2.cvt32(), 13);
-  or_(TMP1.cvt32(), TMP2.cvt32());
-
-  // Store it to mxcsr
-  // Only loads from memory
-  mov(dword [rsp], TMP1.cvt32());
-  ldmxcsr(dword [rsp]);
-  add(rsp, 4);
-}
-
-DEF_OP(Print) {
-  auto Op = IROp->C<IR::IROp_Print>();
-
-  PushRegs();
-  if (IsGPR(Op->Value.ID())) {
-    mov (rdi, GetSrc<RA_64>(Op->Value.ID()));
-    call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintValue)]);
-  }
-  else {
-    pextrq(rdi, GetSrc(Op->Value.ID()), 0);
-    pextrq(rsi, GetSrc(Op->Value.ID()), 1);
-
-    call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintVectorValue)]);
-  }
-
-  PopRegs();
-}
-
-DEF_OP(ProcessorID) {
-  // Cyclecounter in EDX:EAX
-  // IA32_TSC_AUX in ECX
-  rdtscp();
-  mov (GetDst<RA_32>(Node), ecx);
-}
-
-DEF_OP(RDRAND) {
-  auto Op = IROp->C<IR::IROp_RDRAND>();
-
-  auto Dst = GetSrcPair<RA_64>(Node);
-
-  if (Op->GetReseeded) {
-    rdrand(Dst.first);
-  }
-  else {
-    rdseed(Dst.first);
-  }
-
-  // In the case of RDRAND or RDSEED returning a valid number then CF = 1, else 0
-  mov (Dst.second, 0);
-  setc(Dst.second.cvt8());
-}
-
-DEF_OP(Yield) {
-  pause();
-}
-
-#undef DEF_OP
-void X86JITCore::RegisterMiscHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
-  REGISTER_OP(DUMMY,      NoOp);
-  REGISTER_OP(IRHEADER,   NoOp);
-  REGISTER_OP(CODEBLOCK,  NoOp);
-  REGISTER_OP(BEGINBLOCK, NoOp);
-  REGISTER_OP(ENDBLOCK,   NoOp);
-  REGISTER_OP(GUESTOPCODE, GuestOpcode);
-  REGISTER_OP(FENCE,      Fence);
-  REGISTER_OP(BREAK,      Break);
-  REGISTER_OP(PHI,        NoOp);
-  REGISTER_OP(PHIVALUE,   NoOp);
-  REGISTER_OP(PRINT,      Print);
-  REGISTER_OP(GETROUNDINGMODE, GetRoundingMode);
-  REGISTER_OP(SETROUNDINGMODE, SetRoundingMode);
-  REGISTER_OP(INVALIDATEFLAGS,   NoOp);
-  REGISTER_OP(PROCESSORID,   ProcessorID);
-  REGISTER_OP(RDRAND, RDRAND);
-  REGISTER_OP(YIELD, Yield);
-#undef REGISTER_OP
-}
-}
-

External/FEXCore/Source/Interface/Core/JIT/x86_64/MoveOps.cpp

@@ -1,84 +0,0 @@
-/*
-$info$
-tags: backend|x86-64
-$end_info$
-*/
-
-#include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/Core/Dispatcher/X86Dispatcher.h"
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/IR/IR.h>
-
-#include <array>
-#include <stdint.h>
-#include <utility>
-
-namespace FEXCore::CPU {
-
-#define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
-DEF_OP(ExtractElementPair) {
-  auto Op = IROp->C<IR::IROp_ExtractElementPair>();
-  switch (Op->Header.Size) {
-    case 4: {
-      auto Src = GetSrcPair<RA_32>(Op->Pair.ID());
-      std::array<Xbyak::Reg, 2> Regs = {Src.first, Src.second};
-      mov (GetDst<RA_32>(Node), Regs[Op->Element]);
-      break;
-    }
-    case 8: {
-      auto Src = GetSrcPair<RA_64>(Op->Pair.ID());
-      std::array<Xbyak::Reg, 2> Regs = {Src.first, Src.second};
-      mov (GetDst<RA_64>(Node), Regs[Op->Element]);
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
-  }
-}
-
-DEF_OP(CreateElementPair) {
-  auto Op = IROp->C<IR::IROp_CreateElementPair>();
-  std::pair<Xbyak::Reg, Xbyak::Reg> Dst;
-  Xbyak::Reg RegFirst;
-  Xbyak::Reg RegSecond;
-  Xbyak::Reg RegTmp;
-
-  switch (IROp->ElementSize) {
-    case 4: {
-      Dst = GetSrcPair<RA_32>(Node);
-      RegFirst = GetSrc<RA_32>(Op->Lower.ID());
-      RegSecond = GetSrc<RA_32>(Op->Upper.ID());
-      RegTmp = eax;
-      break;
-    }
-    case 8: {
-      Dst = GetSrcPair<RA_64>(Node);
-      RegFirst = GetSrc<RA_64>(Op->Lower.ID());
-      RegSecond = GetSrc<RA_64>(Op->Upper.ID());
-      RegTmp = rax;
-      break;
-    }
-    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
-  }
-
-  if (Dst.first != RegSecond) {
-    mov(Dst.first, RegFirst);
-    mov(Dst.second, RegSecond);
-  } else if (Dst.second != RegFirst) {
-    mov(Dst.second, RegSecond);
-    mov(Dst.first, RegFirst);
-  } else {
-    mov(RegTmp, RegFirst);
-    mov(Dst.second, RegSecond);
-    mov(Dst.first, RegTmp);
-  }
-}
-
-#undef DEF_OP
-void X86JITCore::RegisterMoveHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
-  REGISTER_OP(EXTRACTELEMENTPAIR, ExtractElementPair);
-  REGISTER_OP(CREATEELEMENTPAIR,  CreateElementPair);
-#undef REGISTER_OP
-}
-}
-

External/FEXCore/Source/Interface/Core/JIT/x86_64/x64Relocations.cpp

@@ -1,139 +0,0 @@
-/*
-$info$
-tags: backend|x86-64
-desc: relocation logic of the x86-64 splatter backend
-$end_info$
-*/
-#include "Interface/Context/Context.h"
-#include "Interface/Core/JIT/x86_64/JITClass.h"
-#include "Interface/HLE/Thunks/Thunks.h"
-
-namespace FEXCore::CPU {
-uint64_t X86JITCore::GetNamedSymbolLiteral(FEXCore::CPU::RelocNamedSymbolLiteral::NamedSymbol Op) {
-  switch (Op) {
-    case FEXCore::CPU::RelocNamedSymbolLiteral::NamedSymbol::SYMBOL_LITERAL_EXITFUNCTION_LINKER:
-      return ThreadState->CurrentFrame->Pointers.Common.ExitFunctionLinker;
-    break;
-    default:
-      ERROR_AND_DIE_FMT("Unknown named symbol literal: {}", static_cast<uint32_t>(Op));
-    break;
-  }
-  return ~0ULL;
-
-}
-
-void X86JITCore::LoadConstantWithPadding(Xbyak::Reg Reg, uint64_t Constant) {
-  // The maximum size a move constant can be in bytes
-  // Need to NOP pad to this size to ensure backpatching is always the same size
-  // Calculated as:
-  // [Rex]
-  // [Mov op]
-  // [8 byte constant]
-  //
-  // All other move types are smaller than this. xbyak will use a NOP slide which is quite quick
-  constexpr static size_t MAX_MOVE_SIZE = 10;
-  auto StartingOffset = getSize();
-  mov(Reg, Constant);
-  auto MoveSize = getSize() - StartingOffset;
-  auto NOPPadSize = MAX_MOVE_SIZE - MoveSize;
-  nop(NOPPadSize);
-}
-
-X86JITCore::NamedSymbolLiteralPair X86JITCore::InsertNamedSymbolLiteral(FEXCore::CPU::RelocNamedSymbolLiteral::NamedSymbol Op) {
-  NamedSymbolLiteralPair Lit {
-    .MoveABI = {
-      .NamedSymbolLiteral = {
-        .Header = {
-          .Type = FEXCore::CPU::RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL,
-        },
-        .Symbol = Op,
-        .Offset = 0,
-      },
-    },
-  };
-  return Lit;
-}
-
-void X86JITCore::PlaceNamedSymbolLiteral(NamedSymbolLiteralPair &Lit) {
-  // Offset is the offset from the entrypoint of the block
-  auto CurrentCursor = getSize();
-  Lit.MoveABI.NamedSymbolLiteral.Offset = CurrentCursor - CursorEntry;
-
-  uint64_t Pointer = GetNamedSymbolLiteral(Lit.MoveABI.NamedSymbolLiteral.Symbol);
-
-  L(Lit.Offset);
-  dq(Pointer);
-  Relocations.emplace_back(Lit.MoveABI);
-}
-
-
-void X86JITCore::InsertGuestRIPMove(Xbyak::Reg Reg, uint64_t Constant) {
-  Relocation MoveABI{};
-  MoveABI.GuestRIPMove.Header.Type = FEXCore::CPU::RelocationTypes::RELOC_GUEST_RIP_MOVE;
-
-  // Offset is the offset from the entrypoint of the block
-  auto CurrentCursor = getSize();
-  MoveABI.GuestRIPMove.Offset = CurrentCursor - CursorEntry;
-  MoveABI.GuestRIPMove.GuestRIP = Constant;
-  MoveABI.GuestRIPMove.RegisterIndex = Reg.getIdx();
-
-  if (CTX->Config.CacheObjectCodeCompilation()) {
-    LoadConstantWithPadding(Reg, Constant);
-  }
-  else {
-    mov(Reg, Constant);
-  }
-
-  Relocations.emplace_back(MoveABI);
-}
-
-bool X86JITCore::ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uint64_t CursorEntry, size_t NumRelocations, const char* EntryRelocations) {
-  size_t DataIndex{};
-  for (size_t j = 0; j < NumRelocations; ++j) {
-    const FEXCore::CPU::Relocation *Reloc = reinterpret_cast<const FEXCore::CPU::Relocation *>(&EntryRelocations[DataIndex]);
-    LOGMAN_THROW_AA_FMT((DataIndex % alignof(Relocation)) == 0, "Alignment of relocation wasn't adhered to");
-
-    switch (Reloc->Header.Type) {
-      case FEXCore::CPU::RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL: {
-        uint64_t Pointer = GetNamedSymbolLiteral(Reloc->NamedSymbolLiteral.Symbol);
-        // Relocation occurs at the cursorEntry + offset relative to that cursor.
-        setSize(CursorEntry + Reloc->NamedSymbolLiteral.Offset);
-
-        // Place the pointer
-        dq(Pointer);
-
-        DataIndex += sizeof(Reloc->NamedSymbolLiteral);
-        break;
-      }
-      case FEXCore::CPU::RelocationTypes::RELOC_NAMED_THUNK_MOVE: {
-        uint64_t Pointer = reinterpret_cast<uint64_t>(CTX->ThunkHandler->LookupThunk(Reloc->NamedThunkMove.Symbol));
-        if (Pointer == ~0ULL) {
-          return false;
-        }
-
-        // Relocation occurs at the cursorEntry + offset relative to that cursor.
-        setSize(CursorEntry + Reloc->NamedThunkMove.Offset);
-        LoadConstantWithPadding(Xbyak::Reg64(Reloc->NamedThunkMove.RegisterIndex), Pointer);
-        DataIndex += sizeof(Reloc->NamedThunkMove);
-        break;
-      }
-      case FEXCore::CPU::RelocationTypes::RELOC_GUEST_RIP_MOVE:
-        // XXX: Reenable once the JIT Object Cache is upstream
-        // XXX: Should spin the relocation list, create a list of guest RIP moves, and ask for them all once, reduces lock contention.
-        uint64_t Pointer = ~0ULL; // EmitterCTX->JITObjectCache->FindRelocatedRIP(Reloc->GuestRIPMove.GuestRIP);
-        if (Pointer == ~0ULL) {
-          return false;
-        }
-
-        // Relocation occurs at the cursorEntry + offset relative to that cursor.
-        setSize(CursorEntry + Reloc->GuestRIPMove.Offset);
-        LoadConstantWithPadding(Xbyak::Reg64(Reloc->GuestRIPMove.RegisterIndex), Pointer);
-        DataIndex += sizeof(Reloc->GuestRIPMove);
-        break;
-    }
-  }
-
-  return true;
-}
-}
-

External/FEXCore/Source/Interface/IR/Passes/PhiValidation.cpp

@@ -1,77 +0,0 @@
-/*
-$info$
-tags: ir|opts
-desc: Sanity checking pass
-$end_info$
-*/
-
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/Utils/Profiler.h>
-#include <FEXCore/fextl/sstream.h>
-
-#include "Interface/IR/PassManager.h"
-
-#include <memory>
-
-namespace FEXCore::IR::Validation {
-
-class PhiValidation final : public FEXCore::IR::Pass {
-public:
-  bool Run(IREmitter *IREmit) override;
-};
-
-bool PhiValidation::Run(IREmitter *IREmit) {
-  FEXCORE_PROFILE_SCOPED("PassManager::PHIValidation");
-
-  bool HadError = false;
-  auto CurrentIR = IREmit->ViewIR();
-
-  fextl::ostringstream Errors;
-
-  // Walk the list and calculate the control flow
-  for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
-
-    bool FoundNonPhi{};
-
-    for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) {
-
-      switch (IROp->Op) {
-        // BEGINBLOCK doesn't matter for us
-        case IR::OP_BEGINBLOCK: break;
-        case IR::OP_PHIVALUE:
-        case IR::OP_PHI: {
-          if (FoundNonPhi) {
-            // If we have found a non-phi IR op and then had a Phi or PhiValue value then this is a programming mistake
-            // PHI values MUST be defined at the top of the block only
-            HadError |= true;
-            Errors << "Phi %" << CurrentIR.GetID(CodeNode) << ": Was defined after non-phi operations. Which is invalid!" << std::endl;
-          }
-
-          // Check all the phi values to ensure they have the same type
-          break;
-        }
-        default:
-          FoundNonPhi = true;
-          break;
-      }
-    }
-  }
-
-  if (HadError) {
-    fextl::stringstream Out;
-    FEXCore::IR::Dump(&Out, &CurrentIR, nullptr);
-    Out << "Errors:" << std::endl << Errors.str() << std::endl;
-    LogMan::Msg::EFmt("{}", Out.str());
-  }
-
-  return false;
-}
-
-fextl::unique_ptr<FEXCore::IR::Pass> CreatePhiValidation() {
-  return fextl::make_unique<PhiValidation>();
-}
-
-}

External/FEXCore/Source/Interface/IR/Passes/SyscallOptimization.cpp

@@ -1,89 +0,0 @@
-/*
-$info$
-tags: ir|opts
-desc: Removes unused arguments if known syscall number
-$end_info$
-*/
-
-#include "Interface/IR/PassManager.h"
-
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/HLE/SyscallHandler.h>
-#include <FEXCore/Utils/Profiler.h>
-
-#include <memory>
-#include <stdint.h>
-
-namespace FEXCore::IR {
-
-class SyscallOptimization final : public FEXCore::IR::Pass {
-public:
-  bool Run(IREmitter *IREmit) override;
-};
-
-bool SyscallOptimization::Run(IREmitter *IREmit) {
-  FEXCORE_PROFILE_SCOPED("PassManager::SyscallOpt");
-
-  bool Changed = false;
-  auto CurrentIR = IREmit->ViewIR();
-
-  for (auto [CodeNode, IROp] : CurrentIR.GetAllCode()) {
-
-    if (IROp->Op == FEXCore::IR::OP_SYSCALL) {
-      auto Op = IROp->CW<IR::IROp_Syscall>();
-
-      // Is the first argument a constant?
-      uint64_t Constant;
-      if (IREmit->IsValueConstant(Op->SyscallID, &Constant)) {
-        auto SyscallDef = Manager->SyscallHandler->GetSyscallABI(Constant);
-        auto SyscallFlags = Manager->SyscallHandler->GetSyscallFlags(Constant);
-
-        // Update the syscall flags
-        Op->Flags = SyscallFlags;
-
-        // XXX: Once we have the ability to do real function calls then we can call directly in to the syscall handler
-        if (SyscallDef.NumArgs < FEXCore::HLE::SyscallArguments::MAX_ARGS) {
-          // If the number of args are less than what the IR op supports then we can remove arg usage
-          // We need +1 since we are still passing in syscall number here
-          for (uint8_t Arg = (SyscallDef.NumArgs + 1); Arg < FEXCore::HLE::SyscallArguments::MAX_ARGS; ++Arg) {
-            IREmit->ReplaceNodeArgument(CodeNode, Arg, IREmit->Invalid());
-          }
-#ifdef _M_ARM_64
-          // Replace syscall with inline passthrough syscall if we can
-          if (SyscallDef.HostSyscallNumber != -1) {
-            IREmit->SetWriteCursor(CodeNode);
-            // Skip Args[0] since that is the syscallid
-            auto InlineSyscall = IREmit->_InlineSyscall(
-              CurrentIR.GetNode(IROp->Args[1]),
-              CurrentIR.GetNode(IROp->Args[2]),
-              CurrentIR.GetNode(IROp->Args[3]),
-              CurrentIR.GetNode(IROp->Args[4]),
-              CurrentIR.GetNode(IROp->Args[5]),
-              CurrentIR.GetNode(IROp->Args[6]),
-              SyscallDef.HostSyscallNumber,
-              Op->Flags);
-
-            // Replace all syscall uses with this inline one
-            IREmit->ReplaceAllUsesWith(CodeNode, InlineSyscall);
-
-            // We must remove here since DCE can't remove a IROp with sideeffects
-            IREmit->Remove(CodeNode);
-          }
-#endif
-        }
-
-        Changed = true;
-      }
-    }
-  }
-
-  return Changed;
-}
-
-fextl::unique_ptr<FEXCore::IR::Pass> CreateSyscallOptimization() {
-  return fextl::make_unique<SyscallOptimization>();
-}
-
-}

External/FEXCore/unittests/APITests/ILog2.cpp

@@ -1,7 +0,0 @@
-#include <FEXCore/Utils/MathUtils.h>
-#include <catch2/catch.hpp>
-
-TEST_CASE("ILog2") {
-  auto i = GENERATE(range(0, 64));
-  REQUIRE(FEXCore::ilog2(1ull << i) == i);
-}

FEXCore/CMakeLists.txt

@@ -13,15 +13,6 @@ if (CMAKE_SYSTEM_PROCESSOR MATCHES "^aarch64|^arm64|^armv8\.*")
   set(_M_ARM_64 1)
 endif()
 
-if (ENABLE_VIXL_SIMULATOR)
-  # If the vixl simulator is enabled then we are using the ARM64 JIT
-  option(ENABLE_JIT_X86_64 "Enable the x86_64 JIT" FALSE)
-  option(ENABLE_JIT_ARM64 "Enable the ARM64 JIT" TRUE)
-else()
-  option(ENABLE_JIT_X86_64 "Enable the x86_64 JIT" ${_M_X86_64})
-  option(ENABLE_JIT_ARM64 "Enable the ARM64 JIT" ${_M_ARM_64})
-endif()
-
 option(ENABLE_CLANG_FORMAT "Run clang format over the source" FALSE)
 
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)
@@ -33,6 +24,22 @@ set(CMAKE_INCLUDE_CURRENT_DIR ON)
 
 include(CheckCXXCompilerFlag)
 include(CheckIncludeFileCXX)
+include(CheckCXXSourceCompiles)
+
+set(CMAKE_REQUIRED_FLAGS "-std=c++11 -Wattributes -Werror=attributes")
+check_cxx_source_compiles(
+  "
+  __attribute__((preserve_all))
+  void Testy() {
+  }
+  int main() {
+  return 0;
+  }"
+  HAS_CLANG_PRESERVE_ALL)
+unset(CMAKE_REQUIRED_FLAGS)
+if (HAS_CLANG_PRESERVE_ALL)
+  message(STATUS "Has clang::preserve_all")
+endif ()
 
 if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
     # Useful to have for freestanding libFEXCore

FEXCore/Scripts/config_generator.py

@@ -402,7 +402,7 @@ def print_parse_argloader_options(options):
 
             if (value_type == "strenum"):
                 output_argloader.write("\tfextl::string UserValue = Options[\"{0}\"];\n".format(op_key))
-                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{}, FEXCore::Config::EnumParser(FEXCore::Config::{}_EnumPairs, UserValue));\n".format(op_key.upper(), op_key, op_key))
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{}, FEXCore::Config::EnumParser<FEXCore::Config::{}ConfigPair>(FEXCore::Config::{}_EnumPairs, UserValue));\n".format(op_key.upper(), op_key, op_key, op_key))
             elif (value_type == "strarray"):
                 # these need a bit more help
                 output_argloader.write("\tauto Array = Options.all(\"{0}\");\n".format(op_key))
@@ -431,13 +431,13 @@ def print_parse_envloader_options(options):
             value_type = op_vals["Type"]
             if (value_type == "strenum"):
                 output_argloader.write("else if (Key == \"FEX_{0}\") {{\n".format(op_key.upper()))
-                output_argloader.write("Value = FEXCore::Config::EnumParser(FEXCore::Config::{}_EnumPairs, Value);\n".format(op_key, op_key))
+                output_argloader.write("Value = FEXCore::Config::EnumParser<FEXCore::Config::{}ConfigPair>(FEXCore::Config::{}_EnumPairs, Value_View);\n".format(op_key, op_key, op_key))
                 output_argloader.write("}\n")
 
             if ("ArgumentHandler" in op_vals):
                 conversion_func = "FEXCore::Config::Handler::{0}".format(op_vals["ArgumentHandler"])
                 output_argloader.write("else if (Key == \"FEX_{0}\") {{\n".format(op_key.upper()))
-                output_argloader.write("Value = {0}(Value);\n".format(conversion_func))
+                output_argloader.write("Value = {0}(Value_View);\n".format(conversion_func))
                 output_argloader.write("}\n")
     output_argloader.write("#endif\n")
 
@@ -447,7 +447,7 @@ def print_parse_enum_options(options):
     for op_group, group_vals in options.items():
         for op_key, op_vals in group_vals.items():
             if (op_vals["Type"] == "strenum"):
-                output_argloader.write("enum {} : uint64_t {{\n".format(op_key))
+                output_argloader.write("enum class {} : uint64_t {{\n".format(op_key))
                 Enums = op_vals["Enums"]
                 i = 0
                 # Always have an OFF.
@@ -457,6 +457,8 @@ def print_parse_enum_options(options):
                     i += 1
 
                 output_argloader.write("};\n")
+                output_argloader.write("FEX_DEF_NUM_OPS({})\n".format(op_key))
+
 
     for op_group, group_vals in options.items():
         for op_key, op_vals in group_vals.items():

FEXCore/Scripts/json_ir_generator.py

@@ -144,7 +144,7 @@ def parse_ops(ops):
                     Argument = Argument.strip()
                     OpArg = OpArgument()
 
-                    Split = Argument.split(":")
+                    Split = Argument.split(":", 1)
                     if len(Split) != 2:
                         ExitError("Error parsing argument. Missing Type and name colon split")
 

FEXCore/Source/CMakeLists.txt

@@ -107,9 +107,19 @@ set (SRCS
   Interface/Core/X86HelperGen.cpp
   Interface/Core/ArchHelpers/Arm64Emitter.cpp
   Interface/Core/Dispatcher/Dispatcher.cpp
-  Interface/Core/Dispatcher/X86Dispatcher.cpp
-  Interface/Core/Dispatcher/Arm64Dispatcher.cpp
   Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp
+  Interface/Core/JIT/Arm64/JIT.cpp
+  Interface/Core/JIT/Arm64/ALUOps.cpp
+  Interface/Core/JIT/Arm64/AtomicOps.cpp
+  Interface/Core/JIT/Arm64/BranchOps.cpp
+  Interface/Core/JIT/Arm64/ConversionOps.cpp
+  Interface/Core/JIT/Arm64/EncryptionOps.cpp
+  Interface/Core/JIT/Arm64/FlagOps.cpp
+  Interface/Core/JIT/Arm64/MemoryOps.cpp
+  Interface/Core/JIT/Arm64/MiscOps.cpp
+  Interface/Core/JIT/Arm64/MoveOps.cpp
+  Interface/Core/JIT/Arm64/VectorOps.cpp
+  Interface/Core/JIT/Arm64/Arm64Relocations.cpp
   Interface/Core/X86Tables/BaseTables.cpp
   Interface/Core/X86Tables/DDDTables.cpp
   Interface/Core/X86Tables/EVEXTables.cpp
@@ -133,15 +143,15 @@ set (SRCS
   Interface/IR/Passes/DeadCodeElimination.cpp
   Interface/IR/Passes/DeadContextStoreElimination.cpp
   Interface/IR/Passes/IRCompaction.cpp
+  Interface/IR/Passes/IRDumperPass.cpp
   Interface/IR/Passes/IRValidation.cpp
   Interface/IR/Passes/RAValidation.cpp
   Interface/IR/Passes/LongDivideRemovalPass.cpp
   Interface/IR/Passes/ValueDominanceValidation.cpp
-  Interface/IR/Passes/PhiValidation.cpp
   Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
   Interface/IR/Passes/DeadStoreElimination.cpp
   Interface/IR/Passes/RegisterAllocationPass.cpp
-  Interface/IR/Passes/SyscallOptimization.cpp
+  Interface/IR/Passes/InlineCallOptimization.cpp
   Utils/NetStream.cpp
   Utils/Telemetry.cpp
   Utils/Threads.cpp
@@ -159,24 +169,7 @@ if (ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
     Utils/AllocatorOverride.cpp)
 endif()
 
-if (ENABLE_INTERPRETER)
-  list(APPEND SRCS
-    Interface/Core/Interpreter/InterpreterCore.cpp
-    Interface/Core/Interpreter/InterpreterOps.cpp
-    Interface/Core/Interpreter/ALUOps.cpp
-    Interface/Core/Interpreter/AtomicOps.cpp
-    Interface/Core/Interpreter/BranchOps.cpp
-    Interface/Core/Interpreter/ConversionOps.cpp
-    Interface/Core/Interpreter/EncryptionOps.cpp
-    Interface/Core/Interpreter/F80Ops.cpp
-    Interface/Core/Interpreter/FlagOps.cpp
-    Interface/Core/Interpreter/MemoryOps.cpp
-    Interface/Core/Interpreter/MiscOps.cpp
-    Interface/Core/Interpreter/MoveOps.cpp
-    Interface/Core/Interpreter/VectorOps.cpp)
-endif()
-
-set(DEFINES -DTHREAD_LOCAL=_Thread_local)
+set(DEFINES -DTHREAD_LOCAL=_Thread_local -DJIT_ARM64)
 
 if (_M_X86_64)
   list(APPEND DEFINES -D_M_X86_64=1)
@@ -195,41 +188,14 @@ if (ENABLE_VIXL_DISASSEMBLER)
   list(APPEND DEFINES -DVIXL_DISASSEMBLER=1)
 endif()
 
-if (ENABLE_JIT_X86_64)
-  list(APPEND SRCS
-    Interface/Core/JIT/x86_64/JIT.cpp
-    Interface/Core/JIT/x86_64/ALUOps.cpp
-    Interface/Core/JIT/x86_64/AtomicOps.cpp
-    Interface/Core/JIT/x86_64/BranchOps.cpp
-    Interface/Core/JIT/x86_64/ConversionOps.cpp
-    Interface/Core/JIT/x86_64/EncryptionOps.cpp
-    Interface/Core/JIT/x86_64/FlagOps.cpp
-    Interface/Core/JIT/x86_64/MemoryOps.cpp
-    Interface/Core/JIT/x86_64/MiscOps.cpp
-    Interface/Core/JIT/x86_64/MoveOps.cpp
-    Interface/Core/JIT/x86_64/VectorOps.cpp
-    Interface/Core/JIT/x86_64/x64Relocations.cpp
-    )
-  list(APPEND DEFINES -DJIT_X86_64)
+if (_M_ARM_64 AND HAS_CLANG_PRESERVE_ALL)
+  list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=__attribute__((preserve_all));-DFEXCORE_HAS_PRESERVE_ALL_ATTR=1")
+else()
+  list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=;-DFEXCORE_HAS_PRESERVE_ALL_ATTR=0")
 endif()
 
-if (ENABLE_JIT_ARM64)
-  list(APPEND DEFINES -DJIT_ARM64)
-  list(APPEND SRCS
-    Interface/Core/JIT/Arm64/JIT.cpp
-    Interface/Core/JIT/Arm64/ALUOps.cpp
-    Interface/Core/JIT/Arm64/AtomicOps.cpp
-    Interface/Core/JIT/Arm64/BranchOps.cpp
-    Interface/Core/JIT/Arm64/ConversionOps.cpp
-    Interface/Core/JIT/Arm64/EncryptionOps.cpp
-    Interface/Core/JIT/Arm64/FlagOps.cpp
-    Interface/Core/JIT/Arm64/MemoryOps.cpp
-    Interface/Core/JIT/Arm64/MiscOps.cpp
-    Interface/Core/JIT/Arm64/MoveOps.cpp
-    Interface/Core/JIT/Arm64/VectorOps.cpp
-    Interface/Core/JIT/Arm64/Arm64Relocations.cpp
-    )
-endif()
+# Some defines for the softfloat library
+list(APPEND DEFINES "-DSOFTFLOAT_BUILTIN_CLZ")
 
 set (LIBS fmt::fmt vixl xxhash FEXHeaderUtils)
 

FEXCore/Source/Common/BitSet.h

@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: MIT
 #pragma once
 
 #include <FEXCore/Utils/Allocator.h>

FEXCore/Source/Common/JitSymbols.cpp

@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: MIT
+#include <FEXCore/fextl/fmt.h>
+
+#include "Common/JitSymbols.h"
+
+#include <fcntl.h>
+#include <unistd.h>
+
+namespace FEXCore {
+  JITSymbols::JITSymbols() {
+  }
+
+  JITSymbols::~JITSymbols() {
+    if (fd != -1) {
+      close(fd);
+    }
+  }
+
+  void JITSymbols::InitFile() {
+    // We can't use FILE here since we must be robust against forking processes closing our FD from under us.
+#ifdef __ANDROID__
+    // Android simpleperf looks in /data/local/tmp instead of /tmp
+    const auto PerfMap = fextl::fmt::format("/data/local/tmp/perf-{}.map", getpid());
+#else
+    const auto PerfMap = fextl::fmt::format("/tmp/perf-{}.map", getpid());
+#endif
+    fd = open(PerfMap.c_str(), O_CREAT | O_TRUNC | O_WRONLY | O_APPEND, 0644);
+  }
+
+  void JITSymbols::RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
+    if (fd == -1) return;
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    const auto Buffer = fextl::fmt::format("{} {:x} {}\n", HostAddr, CodeSize, Name);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
+  }
+
+  void JITSymbols::RegisterJITSpace(const void *HostAddr, uint32_t CodeSize) {
+    if (fd == -1) return;
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    const auto Buffer = fextl::fmt::format("{} {:x} FEXJIT\n", HostAddr, CodeSize);
+    auto Result = write(fd, Buffer.c_str(), Buffer.size());
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
+  }
+
+  // Buffered JIT symbols.
+  void JITSymbols::Register(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize) {
+    if (fd == -1) return;
+
+    // Calculate remaining sizes.
+    const auto RemainingSize = Buffer->BUFFER_SIZE - Buffer->Offset;
+    const auto CurrentBufferOffset = &Buffer->Buffer[Buffer->Offset];
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    const auto FMTResult = fmt::format_to_n(CurrentBufferOffset, RemainingSize, "{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
+    if (FMTResult.out >= &Buffer->Buffer[Buffer->BUFFER_SIZE]) {
+      // Couldn't fit, need to force a write.
+      WriteBuffer(Buffer, true);
+      // Rerun
+      Register(Buffer, HostAddr, GuestAddr, CodeSize);
+      return;
+    }
+
+    Buffer->Offset += FMTResult.size;
+    WriteBuffer(Buffer);
+  }
+
+  void JITSymbols::Register(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset) {
+    if (fd == -1) return;
+
+    // Calculate remaining sizes.
+    const auto RemainingSize = Buffer->BUFFER_SIZE - Buffer->Offset;
+    const auto CurrentBufferOffset = &Buffer->Buffer[Buffer->Offset];
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    const auto FMTResult = fmt::format_to_n(CurrentBufferOffset, RemainingSize, "{} {:x} {}+0x{:x} ({})\n", HostAddr, CodeSize, Name, Offset, HostAddr);
+    if (FMTResult.out >= &Buffer->Buffer[Buffer->BUFFER_SIZE]) {
+      // Couldn't fit, need to force a write.
+      WriteBuffer(Buffer, true);
+      // Rerun
+      Register(Buffer, HostAddr, CodeSize, Name, Offset);
+      return;
+    }
+
+    Buffer->Offset += FMTResult.size;
+    WriteBuffer(Buffer);
+  }
+
+  void JITSymbols::RegisterNamedRegion(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint32_t CodeSize, std::string_view Name) {
+    if (fd == -1) return;
+
+    // Calculate remaining sizes.
+    const auto RemainingSize = Buffer->BUFFER_SIZE - Buffer->Offset;
+    const auto CurrentBufferOffset = &Buffer->Buffer[Buffer->Offset];
+
+    // Linux perf format is very straightforward
+    // `<HostPtr> <Size> <Name>\n`
+    const auto FMTResult = fmt::format_to_n(CurrentBufferOffset, RemainingSize, "{} {:x} {}\n", HostAddr, CodeSize, Name);
+    if (FMTResult.out >= &Buffer->Buffer[Buffer->BUFFER_SIZE]) {
+      // Couldn't fit, need to force a write.
+      WriteBuffer(Buffer, true);
+      // Rerun
+      RegisterNamedRegion(Buffer, HostAddr, CodeSize, Name);
+      return;
+    }
+
+    Buffer->Offset += FMTResult.size;
+    WriteBuffer(Buffer);
+  }
+
+  void JITSymbols::WriteBuffer(Core::JITSymbolBuffer *Buffer, bool ForceWrite) {
+    auto Now = std::chrono::steady_clock::now();
+    if (!ForceWrite) {
+      if (((Buffer->LastWrite - Now) < Buffer->MAXIMUM_THRESHOLD) &&
+          Buffer->Offset < Buffer->NEEDS_WRITE_DISTANCE) {
+        // Still buffering, no need to write.
+        return;
+      }
+    }
+
+    Buffer->LastWrite = Now;
+    auto Result = write(fd, Buffer->Buffer, Buffer->Offset);
+    if (Result == -1 && errno == EBADF) {
+      fd = -1;
+    }
+
+    Buffer->Offset = 0;
+  }
+} // namespace FEXCore

FEXCore/Source/Common/JitSymbols.h

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: MIT
+#pragma once
+
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/Debug/InternalThreadState.h>
+
+#include <chrono>
+#include <cstdint>
+#include <cstdio>
+#include <memory>
+#include <string_view>
+
+namespace FEXCore {
+class JITSymbols final {
+public:
+  JITSymbols();
+  ~JITSymbols();
+
+  void InitFile();
+  void RegisterNamedRegion(const void *HostAddr, uint32_t CodeSize, std::string_view Name);
+  void RegisterJITSpace(const void *HostAddr, uint32_t CodeSize);
+
+  // Allocate JIT buffer.
+  static fextl::unique_ptr<Core::JITSymbolBuffer> AllocateBuffer() {
+    return fextl::make_unique<Core::JITSymbolBuffer>();
+  }
+
+  void Register(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint64_t GuestAddr, uint32_t CodeSize);
+  void Register(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint32_t CodeSize, std::string_view Name, uintptr_t Offset);
+  void RegisterNamedRegion(Core::JITSymbolBuffer *Buffer, const void *HostAddr, uint32_t CodeSize, std::string_view Name);
+
+private:
+  int fd{-1};
+  void WriteBuffer(Core::JITSymbolBuffer *Buffer, bool ForceWrite = false);
+};
+}

FEXCore/Source/Common/SoftFloat-3e/extF80_add.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "internals.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_div.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_eq.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 bool extF80_eq( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_lt.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 bool extF80_lt( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_mul.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_rem.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_rem( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_roundToInt.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
  extF80_roundToInt( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {

FEXCore/Source/Common/SoftFloat-3e/extF80_sqrt.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_sqrt( extFloat80_t a )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_sub.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "internals.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_to_f128.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 float128_t extF80_to_f128( extFloat80_t a )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_to_f32.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 float32_t extF80_to_f32( extFloat80_t a )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_to_f64.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 float64_t extF80_to_f64( extFloat80_t a )
 {
     union { struct extFloat80M s; extFloat80_t f; } uA;

FEXCore/Source/Common/SoftFloat-3e/extF80_to_i32.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast32_t
  extF80_to_i32( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {

FEXCore/Source/Common/SoftFloat-3e/extF80_to_i64.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
  extF80_to_i64( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {

FEXCore/Source/Common/SoftFloat-3e/extF80_to_ui64.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast64_t
  extF80_to_ui64( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {

FEXCore/Source/Common/SoftFloat-3e/f128_to_extF80.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t f128_to_extF80( float128_t a )
 {
     union ui128_f128 uA;

FEXCore/Source/Common/SoftFloat-3e/f32_to_extF80.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t f32_to_extF80( float32_t a )
 {
     union ui32_f32 uA;

FEXCore/Source/Common/SoftFloat-3e/f64_to_extF80.c

@@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "specialize.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t f64_to_extF80( float64_t a )
 {
     union ui64_f64 uA;

FEXCore/Source/Common/SoftFloat-3e/i32_to_extF80.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "internals.h"
 #include "softfloat.h"
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t i32_to_extF80( int32_t a )
 {
     uint_fast16_t uiZ64;

FEXCore/Source/Common/SoftFloat-3e/internals.h

@@ -68,9 +68,11 @@ uint_fast64_t
 uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool );
 #endif
 
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool );
 
 #ifdef SOFTFLOAT_FAST_INT64
+FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
  softfloat_roundToI64(
      bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
@@ -109,8 +111,10 @@ float16_t
 #define isNaNF32UI( a ) (((~(a) & 0x7F800000) == 0) && ((a) & 0x007FFFFF))
 
 struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; };
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t );
 
+FEXCORE_PRESERVE_ALL_ATTR
 float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t );
 float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t );
 
@@ -130,8 +134,10 @@ float32_t
 #define isNaNF64UI( a ) (((~(a) & UINT64_C( 0x7FF0000000000000 )) == 0) && ((a) & UINT64_C( 0x000FFFFFFFFFFFFF )))
 
 struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; };
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t );
 
+FEXCORE_PRESERVE_ALL_ATTR
 float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t );
 float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t );
 
@@ -155,11 +161,14 @@ float64_t
 *----------------------------------------------------------------------------*/
 
 struct exp32_sig64 { int_fast32_t exp; uint64_t sig; };
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t );
 
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
  softfloat_roundPackToExtF80(
      bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
  softfloat_normRoundPackToExtF80(
      bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
@@ -181,6 +190,7 @@ extFloat80_t
 #define isNaNF128UI( a64, a0 ) (((~(a64) & UINT64_C( 0x7FFF000000000000 )) == 0) && (a0 || ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF ))))
 
 struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; };
+FEXCORE_PRESERVE_ALL_ATTR
 struct exp32_sig128
  softfloat_normSubnormalF128Sig( uint_fast64_t, uint_fast64_t );
 

FEXCore/Source/Common/SoftFloat-3e/primitives.h

@@ -53,6 +53,7 @@ INLINE
 uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist )
     { return a>>dist | ((a & (((uint_fast64_t) 1<<dist) - 1)) != 0); }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist );
 #endif
 #endif
@@ -74,6 +75,7 @@ INLINE uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist )
         (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0);
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist );
 #endif
 #endif
@@ -95,6 +97,7 @@ INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist )
         (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0);
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist );
 #endif
 #endif
@@ -148,6 +151,7 @@ INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
     return count;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast8_t softfloat_countLeadingZeros32( uint32_t a );
 #endif
 #endif
@@ -157,6 +161,7 @@ uint_fast8_t softfloat_countLeadingZeros32( uint32_t a );
 | Returns the number of leading 0 bits before the most-significant 1 bit of
 | 'a'.  If 'a' is zero, 64 is returned.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 uint_fast8_t softfloat_countLeadingZeros64( uint64_t a );
 #endif
 
@@ -178,6 +183,7 @@ extern const uint16_t softfloat_approxRecip_1k1s[16];
 #ifdef SOFTFLOAT_FAST_DIV64TO32
 #define softfloat_approxRecip32_1( a ) ((uint32_t) (UINT64_C( 0x7FFFFFFFFFFFFFFF ) / (uint32_t) (a)))
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_approxRecip32_1( uint32_t a );
 #endif
 #endif
@@ -204,6 +210,7 @@ extern const uint16_t softfloat_approxRecipSqrt_1k1s[16];
 | returned is also always within the range 0.5 to 1; thus, the most-
 | significant bit of the result is always set.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a );
 #endif
 
@@ -240,6 +247,7 @@ INLINE
 bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
     { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
 #endif
@@ -255,6 +263,7 @@ INLINE
 bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
     { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
 #endif
@@ -275,6 +284,7 @@ struct uint128
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
@@ -296,6 +306,7 @@ struct uint128
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
 #endif
@@ -413,6 +424,7 @@ struct uint64_extra
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint64_extra
  softfloat_shiftRightJam64Extra(
      uint64_t a, uint64_t extra, uint_fast32_t dist );
@@ -492,6 +504,7 @@ struct uint128
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
@@ -528,6 +541,7 @@ struct uint128
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
 #endif
@@ -562,6 +576,7 @@ INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
     return z;
 }
 #else
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b );
 #endif
 #endif
@@ -570,6 +585,7 @@ struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b );
 /*----------------------------------------------------------------------------
 | Returns the 128-bit product of 'a' and 'b'.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b );
 #endif
 

FEXCore/Source/Common/SoftFloat-3e/s_add128.c

@@ -40,6 +40,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #ifndef softfloat_add128
 
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
  softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
 {

FEXCore/Source/Common/SoftFloat-3e/s_approxRecip32_1.c

@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 extern const uint16_t softfloat_approxRecip_1k0s[16];
 extern const uint16_t softfloat_approxRecip_1k1s[16];
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_approxRecip32_1( uint32_t a )
 {
     int index;

FEXCore/Source/Common/SoftFloat-3e/s_approxRecipSqrt32_1.c

@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 extern const uint16_t softfloat_approxRecipSqrt_1k0s[];
 extern const uint16_t softfloat_approxRecipSqrt_1k1s[];
 
+FEXCORE_PRESERVE_ALL_ATTR
 uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a )
 {
     int index;

FEXCore/Source/Common/SoftFloat-3e/s_commonNaNToExtF80UI.c

@@ -44,6 +44,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | floating-point NaN, and returns the bit pattern of this value as an unsigned
 | integer.
 *----------------------------------------------------------------------------*/
+FEXCORE_PRESERVE_ALL_ATTR
 struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
 {
     struct uint128 uiZ;