Merge pull request #3027 from Sonicadvance1/remove_implicit_andn

IR: Removes implicit sized andn

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -1538,7 +1538,7 @@ void OpDispatchBuilder::SAHFOp(OpcodeArgs) {
   OrderedNode *Src = LoadGPRRegister(X86State::REG_RAX, 1, 8);
 
   // Clear bits that aren't supposed to be set
-  Src = _Andn(Src, _Constant(0b101000));
+  Src = _Andn(OpSize::i64Bit, Src, _Constant(0b101000));
 
   // Set the bit that is always set here
   Src = _Or(OpSize::i64Bit, Src, _Constant(0b10));
@@ -2297,7 +2297,7 @@ void OpDispatchBuilder::ANDNBMIOp(OpcodeArgs) {
   auto* Src1 = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
   auto* Src2 = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags, -1);
 
-  auto Dest = _Andn(Src2, Src1);
+  auto Dest = _Andn(OpSizeFromSrc(Op), Src2, Src1);
 
   StoreResult(GPRClass, Op, Dest, -1);
   GenerateFlags_Logical(Op, Dest, Src1, Src2);
@@ -2417,7 +2417,7 @@ void OpDispatchBuilder::BZHI(OpcodeArgs) {
   // Now clear the high bits specified by the index.
   auto NegOne = _Constant(OperandSize, -1);
   auto Mask = _Lshl(IR::SizeToOpSize(Size), NegOne, MaskedIndex);
-  auto MaskResult = _Andn(Src, Mask);
+  auto MaskResult = _Andn(IR::SizeToOpSize(Size), Src, Mask);
 
   // If the index is above OperandSize, we don't clear anything.
   auto Bounds = _Constant(OperandSize - 1);
@@ -2995,7 +2995,7 @@ void OpDispatchBuilder::BTROp(OpcodeArgs) {
     Result = _Lshr(IR::SizeToOpSize(std::max<uint8_t>(4u, GetOpSize(Dest))), Dest, BitSelect);
 
     OrderedNode *BitMask = _Lshl(OpSize::i64Bit, _Constant(1), BitSelect);
-    Dest = _Andn(Dest, BitMask);
+    Dest = _Andn(OpSize::i64Bit, Dest, BitMask);
     StoreResult(GPRClass, Op, Dest, -1);
   } else {
     // Load the address to the memory location
@@ -3029,7 +3029,7 @@ void OpDispatchBuilder::BTROp(OpcodeArgs) {
 
       // Now shift in to the correct bit location
       Result = _Lshr(IR::SizeToOpSize(std::max<uint8_t>(4u, GetOpSize(Value))), Value, BitSelect);
-      Value = _Andn(Value, BitMask);
+      Value = _Andn(OpSize::i64Bit, Value, BitMask);
       _StoreMemAutoTSO(GPRClass, 1, MemoryLocation, Value, 1);
     }
   }

FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp

@@ -74,7 +74,7 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
   using FnType = OrderedNode* (*)(OpDispatchBuilder&, OrderedNode*, OrderedNode*, OrderedNode*);
 
   const auto f0 = [](OpDispatchBuilder &Self, OrderedNode *B, OrderedNode *C, OrderedNode *D) -> OrderedNode* {
-    return Self._Xor(Self._And(B, C), Self._Andn(D, B));
+    return Self._Xor(Self._And(B, C), Self._Andn(OpSize::i32Bit, D, B));
   };
   const auto f1 = [](OpDispatchBuilder &Self, OrderedNode *B, OrderedNode *C, OrderedNode *D) -> OrderedNode* {
     return Self._Xor(Self._Xor(B, C), D);
@@ -201,7 +201,7 @@ void OpDispatchBuilder::SHA256MSG2Op(OpcodeArgs) {
 
 void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) {
   const auto Ch = [this](OrderedNode *E, OrderedNode *F, OrderedNode *G) -> OrderedNode* {
-    return _Xor(_And(E, F), _Andn(G, E));
+    return _Xor(_And(E, F), _Andn(OpSize::i32Bit, G, E));
   };
   const auto Major = [this](OrderedNode *A, OrderedNode *B, OrderedNode *C) -> OrderedNode* {
     return _Xor(_Xor(_And(A, B), _And(A, C)), _And(B, C));

FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp

@@ -67,7 +67,7 @@ void OpDispatchBuilder::ZeroMultipleFlags(uint32_t FlagsMask) {
       }
       else {
         auto IndexMaskConstant = _Constant(IndexMask);
-        auto NewNZCV = _Andn(GetNZCV(), IndexMaskConstant);
+        auto NewNZCV = _Andn(OpSize::i64Bit, GetNZCV(), IndexMaskConstant);
         SetNZCV(NewNZCV);
       }
       // Unset the possibly set bits.
@@ -171,7 +171,7 @@ OrderedNode *OpDispatchBuilder::GetPackedRFLAG(uint32_t FlagsMask) {
 void OpDispatchBuilder::CalculateOF_Add(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
   auto XorOp1 = _Xor(Src1, Src2);
   auto XorOp2 = _Xor(Res, Src1);
-  OrderedNode *AndOp1 = _Andn(XorOp2, XorOp1);
+  OrderedNode *AndOp1 = _Andn(SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit, XorOp2, XorOp1);
   AndOp1 = _Bfe(1, SrcSize * 8 - 1, AndOp1);
   SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(AndOp1);
 }

FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp

@@ -35,7 +35,7 @@ void OpDispatchBuilder::SetX87TopTag(OrderedNode *Value, X87Tag Tag) {
   // TODO: This can all be done with OpSize::i32Bit.
   auto TopOffset = _Lshl(IR::SizeToOpSize(std::max<uint8_t>(4, GetOpSize(Value))), Value, _Constant(1));
   Mask = _Lshl(OpSize::i64Bit, Mask, TopOffset);
-  OrderedNode *NewFTW = _Andn(FTW, Mask);
+  OrderedNode *NewFTW = _Andn(OpSize::i64Bit, FTW, Mask);
   if (Tag != X87Tag::Valid) {
     auto TagVal = _Lshl(OpSize::i64Bit, _Constant(ToUnderlying(Tag)), TopOffset);
     NewFTW = _Or(OpSize::i64Bit, NewFTW, TagVal);

FEXCore/Source/Interface/IR/Passes/ConstProp.cpp

@@ -910,8 +910,7 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
         }
         else {
           // We are wanting to clear the bitfield.
-          auto andn = IREmit->_Andn(CurrentIR.GetNode(Op->Header.Args[0]), IREmit->_Constant(NewConstant));
-          andn.first->Header.Size = IROp->Size;
+          auto andn = IREmit->_Andn(IR::SizeToOpSize(IROp->Size), CurrentIR.GetNode(Op->Header.Args[0]), IREmit->_Constant(NewConstant));
           IREmit->ReplaceAllUsesWith(CodeNode, andn);
           Changed = true;
         }

FEXCore/include/FEXCore/IR/IREmitter.h

@@ -105,9 +105,6 @@ friend class FEXCore::IR::PassManager;
   IRPair<IROp_And> _And(OrderedNode *_Src1, OrderedNode *_Src2) {
     return _And(static_cast<OpSize>(std::max<uint8_t>(4, std::max(GetOpSize(_Src1), GetOpSize(_Src2)))), _Src1, _Src2);
   }
-  IRPair<IROp_Andn> _Andn(OrderedNode *_Src1, OrderedNode *_Src2) {
-    return _Andn(static_cast<OpSize>(std::max<uint8_t>(4, std::max(GetOpSize(_Src1), GetOpSize(_Src2)))), _Src1, _Src2);
-  }
   IRPair<IROp_Bfi> _Bfi(uint8_t DestSize, uint8_t _Width, uint8_t _lsb, OrderedNode *_Dest, OrderedNode *_Src) {
     return _Bfi(static_cast<OpSize>(DestSize), _Width, _lsb, _Dest, _Src);
   }