steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-06 12:00:17 +02:00
Code Issues Packages Projects Releases 66 Wiki Activity

InstCountCI: Update for BT minor opt

Browse Source
This commit is contained in:
Ryan Houdek committed 2023-09-10 20:23:08 -07:00
1 parent 4feb059f51
commit e3a00fb2fb
9 files changed
+335 -640
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

unittests/InstructionCountCI/H0F38.json
+3 -6
View File
@@ -416,7 +416,7 @@
]
},
"ptest xmm0, xmm1": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 21,
"Optimal": "No",
"Comment": [
"0x66 0x0f 0x38 0x17"
@@ -436,11 +436,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
unittests/InstructionCountCI/Primary.json
+5 -8
View File
@@ -3202,7 +3202,7 @@
]
},
"popf": {
"ExpectedInstructionCount": 42,
"ExpectedInstructionCount": 39,
"Optimal": "No",
"Comment": "0x9d",
"ExpectedArm64ASM": [
@@ -3211,18 +3211,15 @@
"mov w21, #0x202",
"orr x20, x20, x21",
"ubfx w21, w20, #0, #1",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"lsl x21, x21, #29",
"ubfx w22, w20, #2, #1",
"eor w22, w22, #0x1",
"strb w22, [x28, #706]",
"strb w20, [x28, #708]",
"ubfx w22, w20, #6, #1",
"bfi w21, w22, #30, #1",
"orr w21, w21, w22, lsl #30",
"ubfx w22, w20, #7, #1",
"bfi w21, w22, #31, #1",
"orr w21, w21, w22, lsl #31",
"ubfx w22, w20, #8, #1",
"strb w22, [x28, #712]",
"ubfx w22, w20, #9, #1",
@@ -3230,7 +3227,7 @@
"ubfx w22, w20, #10, #1",
"strb w22, [x28, #714]",
"ubfx w22, w20, #11, #1",
"bfi w21, w22, #28, #1",
"orr w21, w21, w22, lsl #28",
"ubfx w22, w20, #12, #1",
"strb w22, [x28, #716]",
"ubfx w22, w20, #14, #1",
unittests/InstructionCountCI/Primary_32Bit.json
+18 -32
View File
@@ -226,7 +226,7 @@
]
},
"aaa": {
"ExpectedInstructionCount": 31,
"ExpectedInstructionCount": 30,
"Optimal": "No",
"Comment": "0x37",
"ExpectedArm64ASM": [
@@ -240,14 +240,13 @@
"cmp x21, #0x9 (9)",
"cset x21, hi",
"orr x20, x20, x21",
"cbnz x20, #+0x2c",
"cbnz x20, #+0x28",
"mov w20, #0xff0f",
"and x20, x22, x20",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"mov w20, #0x0",
"ldr w21, [x28, #728]",
"and w21, w21, #0xdfffffff",
"mov w21, #0x0",
"strb w20, [x28, #708]",
"str w21, [x28, #728]",
"b #+0x2c",
@@ -264,7 +263,7 @@
]
},
"aas": {
"ExpectedInstructionCount": 32,
"ExpectedInstructionCount": 31,
"Optimal": "No",
"Comment": "0x3f",
"ExpectedArm64ASM": [
@@ -278,14 +277,13 @@
"cmp x21, #0x9 (9)",
"cset x21, hi",
"orr x20, x20, x21",
"cbnz x20, #+0x2c",
"cbnz x20, #+0x28",
"mov w20, #0xff0f",
"and x20, x22, x20",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"mov w20, #0x0",
"ldr w21, [x28, #728]",
"and w21, w21, #0xdfffffff",
"mov w21, #0x0",
"strb w20, [x28, #708]",
"str w21, [x28, #728]",
"b #+0x30",
@@ -494,7 +492,7 @@
]
},
"aam": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": "0xd4",
"ExpectedArm64ASM": [
@@ -511,20 +509,17 @@
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"lsl x21, x21, #31",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"orr w21, w21, w22, lsl #30",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"aad": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": "0xd5",
"ExpectedArm64ASM": [
@@ -541,20 +536,17 @@
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"lsl x21, x21, #31",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"orr w21, w21, w22, lsl #30",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"db 0xd4, 0x40": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": [
"aam with a different immediate byte base",
@@ -574,20 +566,17 @@
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"lsl x21, x21, #31",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"orr w21, w21, w22, lsl #30",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"db 0xd5, 0x40": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 19,
"Optimal": "No",
"Comment": [
"aad with a different immediate byte base",
@@ -606,14 +595,11 @@
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"lsl x21, x21, #31",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"orr w21, w21, w22, lsl #30",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
unittests/InstructionCountCI/Secondary.json
+85 -168
View File
@@ -200,7 +200,7 @@
]
},
"ucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 19,
"Optimal": "No",
"Comment": "0x0f 0x2e",
"ExpectedArm64ASM": [
@@ -214,11 +214,8 @@
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
@@ -1825,24 +1822,20 @@
]
},
"bt ax, bx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"and x20, x20, #0xf",
"lsr w20, w21, w20",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, x20",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt [rax], bx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
@@ -1852,32 +1845,25 @@
"ldrb w20, [x4, x20, sxtx]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt eax, ebx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"and x20, x20, #0x1f",
"lsr w20, w21, w20",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, x20",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt [rax], ebx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
@@ -1887,30 +1873,24 @@
"ldrb w20, [x4, x20, sxtx]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt rax, rbx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"and x20, x7, #0x3f",
"lsr x20, x4, x20",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt [rax], rbx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
@@ -1919,10 +1899,7 @@
"ldrb w21, [x4, x21, sxtx]",
"lsr w20, w21, w20",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
@@ -2308,28 +2285,24 @@
]
},
"bts ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"and x20, x20, #0xf",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"orr x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"orr x20, x4, x20",
"bfxil x4, x20, #0, #16",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts [rax], bx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
@@ -2343,36 +2316,29 @@
"orr x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts eax, ebx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"and x20, x20, #0x1f",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"orr x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"orr x20, x4, x20",
"lsr w4, w20, #0",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts [rax], ebx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
@@ -2386,15 +2352,12 @@
"orr x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts rax, rbx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
@@ -2404,15 +2367,12 @@
"lsl x20, x22, x20",
"orr x4, x4, x20",
"ubfx x20, x21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts [rax], rbx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
@@ -2425,10 +2385,7 @@
"orr x22, x23, x22",
"strb w22, [x4, x21, sxtx]",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
@@ -2715,28 +2672,24 @@
]
},
"btr ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"and x20, x20, #0xf",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"bic x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"bic x20, x4, x20",
"bfxil x4, x20, #0, #16",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr [rax], bx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
@@ -2750,36 +2703,29 @@
"bic x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr eax, ebx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"and x20, x20, #0x1f",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"bic x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"bic x20, x4, x20",
"lsr w4, w20, #0",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr [rax], ebx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
@@ -2793,15 +2739,12 @@
"bic x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr rax, rbx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
@@ -2811,15 +2754,12 @@
"lsl x20, x22, x20",
"bic x4, x4, x20",
"ubfx x20, x21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr [rax], rbx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
@@ -2832,10 +2772,7 @@
"bic x22, x23, x22",
"strb w22, [x4, x21, sxtx]",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
@@ -2922,28 +2859,24 @@
]
},
"btc ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"and x20, x20, #0xf",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"eor x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"eor x20, x4, x20",
"bfxil x4, x20, #0, #16",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc [rax], bx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
@@ -2957,36 +2890,29 @@
"eor x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc eax, ebx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"and x20, x20, #0x1f",
"lsr w22, w21, w20",
"mov w23, #0x1",
"lsl x20, x23, x20",
"eor x20, x21, x20",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"eor x20, x4, x20",
"lsr w4, w20, #0",
"ubfx w20, w22, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc [rax], ebx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
@@ -3000,15 +2926,12 @@
"eor x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc rax, rbx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
@@ -3018,15 +2941,12 @@
"lsl x20, x22, x20",
"eor x4, x4, x20",
"ubfx x20, x21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc [rax], rbx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
@@ -3039,10 +2959,7 @@
"eor x22, x23, x22",
"strb w22, [x4, x21, sxtx]",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
unittests/InstructionCountCI/SecondaryGroup.json
+104 -186
View File
@@ -22,375 +22,293 @@
]
},
"bt ax, 0": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"str w20, [x28, #728]"
]
},
"bt eax, 0": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"str w20, [x28, #728]"
]
},
"bt rax, 0": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt eax, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt rax, 0": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt ax, 15": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w20, w20, #15",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #15",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt eax, 31": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"lsr w20, w20, #31",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #31",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bt rax, 63": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts ax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov x20, x4",
"orr x21, x20, #0x1",
"bfxil x4, x21, #0, #16",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts eax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov x20, x4",
"orr x21, x20, #0x1",
"lsr w4, w21, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts rax, 0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"mov x20, x4",
"orr x4, x20, #0x1",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts ax, 15": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w21, w20, #15",
"orr x20, x20, #0x8000",
"bfxil x4, x20, #0, #16",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #15",
"orr x21, x4, #0x8000",
"bfxil x4, x21, #0, #16",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts eax, 31": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"lsr w21, w20, #31",
"orr x20, x20, #0x80000000",
"lsr w4, w20, #0",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #31",
"orr x21, x4, #0x80000000",
"lsr w4, w21, #0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"bts rax, 63": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"orr x4, x4, #0x8000000000000000",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr ax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov x20, x4",
"and x21, x20, #0xfffffffffffffffe",
"bfxil x4, x21, #0, #16",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr eax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov x20, x4",
"and x21, x20, #0xfffffffffffffffe",
"lsr w4, w21, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr rax, 0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"mov x20, x4",
"and x4, x20, #0xfffffffffffffffe",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr ax, 15": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w21, w20, #15",
"and x20, x20, #0xffffffffffff7fff",
"bfxil x4, x20, #0, #16",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #15",
"and x21, x4, #0xffffffffffff7fff",
"bfxil x4, x21, #0, #16",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr eax, 31": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"lsr w21, w20, #31",
"and x20, x20, #0xffffffff7fffffff",
"lsr w4, w20, #0",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #31",
"and x21, x4, #0xffffffff7fffffff",
"lsr w4, w21, #0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btr rax, 63": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"and x4, x4, #0x7fffffffffffffff",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc ax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov x20, x4",
"eor x21, x20, #0x1",
"bfxil x4, x21, #0, #16",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc eax, 0": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov x20, x4",
"eor x21, x20, #0x1",
"lsr w4, w21, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc rax, 0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"mov x20, x4",
"eor x4, x20, #0x1",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc ax, 15": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsr w21, w20, #15",
"eor x20, x20, #0x8000",
"bfxil x4, x20, #0, #16",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #15",
"eor x21, x4, #0x8000",
"bfxil x4, x21, #0, #16",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc eax, 31": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"lsr w21, w20, #31",
"eor x20, x20, #0x80000000",
"lsr w4, w20, #0",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsr x20, x4, #31",
"eor x21, x4, #0x80000000",
"lsr w4, w21, #0",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"btc rax, 63": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"lsr x20, x4, #63",
"eor x4, x4, #0x8000000000000000",
"ubfx x20, x20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
unittests/InstructionCountCI/Secondary_OpSize.json
+3 -6
View File
@@ -145,7 +145,7 @@
]
},
"ucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 19,
"Optimal": "No",
"Comment": "0x66 0x0f 0x2e",
"ExpectedArm64ASM": [
@@ -159,11 +159,8 @@
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
unittests/InstructionCountCI/VEX_map1.json
+3 -6
View File
@@ -3779,7 +3779,7 @@
]
},
"vucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 21,
"Optimal": "No",
"Comment": [
"Map 1 0b00 0x2e 128-bit"
@@ -3797,11 +3797,8 @@
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
unittests/InstructionCountCI/VEX_map2.json
+18 -36
View File
@@ -593,7 +593,7 @@
]
},
"vtestps xmm0, xmm1": {
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 27,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0e 128-bit"
@@ -619,11 +619,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
@@ -632,7 +629,7 @@
]
},
"vtestps ymm0, ymm1": {
"ExpectedInstructionCount": 38,
"ExpectedInstructionCount": 35,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0e 256-bit"
@@ -666,11 +663,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
@@ -679,7 +673,7 @@
]
},
"vtestpd xmm0, xmm1": {
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 27,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0f 128-bit"
@@ -705,11 +699,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
@@ -718,7 +709,7 @@
]
},
"vtestpd ymm0, ymm1": {
"ExpectedInstructionCount": 38,
"ExpectedInstructionCount": 35,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0f 256-bit"
@@ -752,11 +743,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
@@ -803,7 +791,7 @@
]
},
"vptest xmm0, xmm1": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x16 128-bit"
@@ -825,11 +813,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
@@ -838,7 +823,7 @@
]
},
"vptest ymm0, ymm1": {
"ExpectedInstructionCount": 34,
"ExpectedInstructionCount": 31,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x16 256-bit"
@@ -868,11 +853,8 @@
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
unittests/InstructionCountCI/x87.json
+96 -192
View File
@@ -10334,7 +10334,7 @@
]
},
"fucomi st0, st0": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xe8 /5"
@@ -10395,18 +10395,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st1": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xe9 /5"
@@ -10467,18 +10464,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st2": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xea /5"
@@ -10539,18 +10533,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st3": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xeb /5"
@@ -10611,18 +10602,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st4": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xec /5"
@@ -10683,18 +10671,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st5": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xed /5"
@@ -10755,18 +10740,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st6": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xee /5"
@@ -10827,18 +10809,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st7": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xef /5"
@@ -10899,18 +10878,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st0": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf0 /6"
@@ -10971,18 +10947,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st1": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf1 /6"
@@ -11043,18 +11016,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st2": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf2 /6"
@@ -11115,18 +11085,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st3": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf3 /6"
@@ -11187,18 +11154,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st4": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf4 /6"
@@ -11259,18 +11223,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st5": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf5 /6"
@@ -11331,18 +11292,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st6": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf6 /6"
@@ -11403,18 +11361,15 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st7": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf7 /6"
@@ -11475,11 +11430,8 @@
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"ldr w23, [x28, #728]",
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"lsl x21, x21, #29",
"orr w21, w21, w22, lsl #30",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
@@ -22409,7 +22361,7 @@
]
},
"fucomip st0": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xe8 /5"
@@ -22470,11 +22422,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22489,7 +22438,7 @@
]
},
"fucomip st1": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xe9 /5"
@@ -22551,11 +22500,8 @@
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"ldr w25, [x28, #728]",
"mov w0, w25",
"bfi w0, w23, #29, #1",
"mov w23, w0",
"bfi w23, w24, #30, #1",
"lsl x23, x23, #29",
"orr w23, w23, w24, lsl #30",
"eor w22, w22, #0x1",
"strb w22, [x28, #706]",
"ldrb w22, [x28, #1010]",
@@ -22569,7 +22515,7 @@
]
},
"fucomip st2": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xea /5"
@@ -22630,11 +22576,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22649,7 +22592,7 @@
]
},
"fucomip st3": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xeb /5"
@@ -22710,11 +22653,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22729,7 +22669,7 @@
]
},
"fucomip st4": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xec /5"
@@ -22790,11 +22730,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22809,7 +22746,7 @@
]
},
"fucomip st5": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xed /5"
@@ -22870,11 +22807,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22889,7 +22823,7 @@
]
},
"fucomip st6": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xee /5"
@@ -22950,11 +22884,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -22969,7 +22900,7 @@
]
},
"fucomip st7": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xef /5"
@@ -23030,11 +22961,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23049,7 +22977,7 @@
]
},
"fcomip st0": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf0 /6"
@@ -23110,11 +23038,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23129,7 +23054,7 @@
]
},
"fcomip st1": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf1 /6"
@@ -23191,11 +23116,8 @@
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"ldr w25, [x28, #728]",
"mov w0, w25",
"bfi w0, w23, #29, #1",
"mov w23, w0",
"bfi w23, w24, #30, #1",
"lsl x23, x23, #29",
"orr w23, w23, w24, lsl #30",
"eor w22, w22, #0x1",
"strb w22, [x28, #706]",
"ldrb w22, [x28, #1010]",
@@ -23209,7 +23131,7 @@
]
},
"fcomip st2": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf2 /6"
@@ -23270,11 +23192,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23289,7 +23208,7 @@
]
},
"fcomip st3": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf3 /6"
@@ -23350,11 +23269,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23369,7 +23285,7 @@
]
},
"fcomip st4": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf4 /6"
@@ -23430,11 +23346,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23449,7 +23362,7 @@
]
},
"fcomip st5": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf5 /6"
@@ -23510,11 +23423,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23529,7 +23439,7 @@
]
},
"fcomip st6": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf6 /6"
@@ -23590,11 +23500,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
@@ -23609,7 +23516,7 @@
]
},
"fcomip st7": {
"ExpectedInstructionCount": 71,
"ExpectedInstructionCount": 68,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf7 /6"
@@ -23670,11 +23577,8 @@
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"lsl x22, x22, #29",
"orr w22, w22, w23, lsl #30",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",