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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2023-09-05 14:21:18 -04:00
1 parent 02c864d837
commit 305bb98cf8
4 files changed
+235 -358
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unittests/InstructionCountCI/Primary.json
+154 -232
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/PrimaryGroup.json
+43 -82
View File
@@ -13,7 +13,7 @@
],
"Instructions": {
"add al, 1": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
@@ -22,7 +22,6 @@
"bfxil x4, x21, #0, #8",
"uxtb w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -61,7 +60,7 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 31,
"ExpectedInstructionCount": 30,
"Optimal": "No",
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
@@ -74,7 +73,6 @@
"bfxil x4, x20, #0, #8",
"uxtb w20, w20",
"eor w23, w22, #0x1",
"eor w23, w23, w20",
"strb w23, [x28, #708]",
"eor x23, x20, #0x1",
"strb w23, [x28, #706]",
@@ -99,7 +97,7 @@
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 31,
"ExpectedInstructionCount": 30,
"Optimal": "No",
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
@@ -112,7 +110,6 @@
"bfxil x4, x20, #0, #8",
"uxtb w20, w20",
"eor w23, w22, #0x1",
"eor w23, w23, w20",
"strb w23, [x28, #708]",
"eor x23, x20, #0x1",
"strb w23, [x28, #706]",
@@ -155,7 +152,7 @@
]
},
"sub al, 1": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
@@ -164,7 +161,6 @@
"bfxil x4, x21, #0, #8",
"uxtb w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -203,7 +199,7 @@
]
},
"cmp al, 1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 21,
"Optimal": "No",
"Comment": "GROUP1 0x80 /7",
"ExpectedArm64ASM": [
@@ -211,7 +207,6 @@
"sub w21, w20, #0x1 (1)",
"uxtb w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -232,7 +227,7 @@
]
},
"add ax, 256": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
@@ -241,7 +236,6 @@
"bfxil x4, x21, #0, #16",
"uxth w21, w21",
"eor w22, w20, #0x100",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -262,14 +256,13 @@
]
},
"add eax, 256": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"add w4, w20, #0x100 (256)",
"eor w21, w20, #0x100",
"eor w21, w21, w4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -279,14 +272,13 @@
]
},
"add rax, 256": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "Yes",
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x20, x4",
"add x4, x20, #0x100 (256)",
"eor x21, x20, #0x100",
"eor x21, x21, x4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -323,7 +315,7 @@
]
},
"adc eax, 256": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
@@ -334,7 +326,6 @@
"lsr w22, w4, #0",
"add w4, w22, w20",
"eor w20, w22, #0x100",
"eor w20, w20, w4",
"strb w20, [x28, #708]",
"eor x20, x4, #0x1",
"strb w20, [x28, #706]",
@@ -356,7 +347,7 @@
]
},
"adc rax, 256": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
@@ -367,7 +358,6 @@
"mov x22, x4",
"add x4, x22, x20",
"eor x20, x22, #0x100",
"eor x20, x20, x4",
"strb w20, [x28, #708]",
"eor x20, x4, #0x1",
"strb w20, [x28, #706]",
@@ -389,7 +379,7 @@
]
},
"sbb eax, 256": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
@@ -400,7 +390,6 @@
"lsr w22, w4, #0",
"sub w4, w22, w20",
"eor w20, w22, #0x100",
"eor w20, w20, w4",
"strb w20, [x28, #708]",
"eor x20, x4, #0x1",
"strb w20, [x28, #706]",
@@ -422,7 +411,7 @@
]
},
"sbb rax, 256": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
@@ -433,7 +422,6 @@
"mov x22, x4",
"sub x4, x22, x20",
"eor x20, x22, #0x100",
"eor x20, x20, x4",
"strb w20, [x28, #708]",
"eor x20, x4, #0x1",
"strb w20, [x28, #706]",
@@ -482,14 +470,13 @@
]
},
"sub eax, 256": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"sub w4, w20, #0x100 (256)",
"eor w21, w20, #0x100",
"eor w21, w21, w4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -500,14 +487,13 @@
]
},
"sub rax, 256": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "Yes",
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x20, x4",
"sub x4, x20, #0x100 (256)",
"eor x21, x20, #0x100",
"eor x21, x21, x4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -545,14 +531,13 @@
]
},
"cmp eax, 256": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"sub w21, w20, #0x100 (256)",
"eor w22, w20, #0x100",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x21, x21, #0x1",
"strb w21, [x28, #706]",
@@ -563,13 +548,12 @@
]
},
"cmp rax, 256": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "Yes",
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"sub x20, x4, #0x100 (256)",
"eor x21, x4, #0x100",
"eor x21, x21, x20",
"strb w21, [x28, #708]",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
@@ -580,7 +564,7 @@
]
},
"add ax, 1": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
@@ -589,7 +573,6 @@
"bfxil x4, x21, #0, #16",
"uxth w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -610,14 +593,13 @@
]
},
"add eax, 1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"add w4, w20, #0x1 (1)",
"eor w21, w20, #0x1",
"eor w21, w21, w4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -627,14 +609,13 @@
]
},
"add rax, 1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "Yes",
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov x20, x4",
"add x4, x20, #0x1 (1)",
"eor x21, x20, #0x1",
"eor x21, x21, x4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -671,7 +652,7 @@
]
},
"adc eax, 1": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
@@ -682,7 +663,6 @@
"lsr w22, w4, #0",
"add w4, w22, w20",
"eor w20, w22, #0x1",
"eor w20, w20, w4",
"strb w20, [x28, #708]",
"eor x20, x4, #0x1",
"strb w20, [x28, #706]",
@@ -704,7 +684,7 @@
]
},
"adc rax, 1": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
@@ -715,7 +695,6 @@
"mov x22, x4",
"add x4, x22, x20",
"eor x20, x22, #0x1",
"eor x20, x20, x4",
"strb w20, [x28, #708]",
"eor x20, x4, #0x1",
"strb w20, [x28, #706]",
@@ -737,7 +716,7 @@
]
},
"sbb eax, 1": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
@@ -748,7 +727,6 @@
"lsr w22, w4, #0",
"sub w4, w22, w20",
"eor w20, w22, #0x1",
"eor w20, w20, w4",
"strb w20, [x28, #708]",
"eor x20, x4, #0x1",
"strb w20, [x28, #706]",
@@ -770,7 +748,7 @@
]
},
"sbb rax, 1": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
@@ -781,7 +759,6 @@
"mov x22, x4",
"sub x4, x22, x20",
"eor x20, x22, #0x1",
"eor x20, x20, x4",
"strb w20, [x28, #708]",
"eor x20, x4, #0x1",
"strb w20, [x28, #706]",
@@ -830,14 +807,13 @@
]
},
"sub eax, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"sub w4, w20, #0x1 (1)",
"eor w21, w20, #0x1",
"eor w21, w21, w4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -848,14 +824,13 @@
]
},
"sub rax, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x20, x4",
"sub x4, x20, #0x1 (1)",
"eor x21, x20, #0x1",
"eor x21, x21, x4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -893,14 +868,13 @@
]
},
"cmp eax, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"sub w21, w20, #0x1 (1)",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x21, x21, #0x1",
"strb w21, [x28, #706]",
@@ -911,13 +885,12 @@
]
},
"cmp rax, 1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"sub x20, x4, #0x1 (1)",
"eor x21, x4, #0x1",
"eor x21, x21, x20",
"strb w21, [x28, #708]",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
@@ -2962,7 +2935,7 @@
]
},
"neg bl": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
@@ -2971,8 +2944,7 @@
"neg w22, w21",
"bfxil x7, x22, #0, #8",
"uxtb w22, w22",
"eor w23, w21, w22",
"strb w23, [x28, #708]",
"strb w21, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
"lsl w23, w22, #24",
@@ -3137,7 +3109,7 @@
]
},
"neg bx": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
@@ -3146,8 +3118,7 @@
"neg w22, w21",
"bfxil x7, x22, #0, #16",
"uxth w22, w22",
"eor w23, w21, w22",
"strb w23, [x28, #708]",
"strb w21, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
"lsl w23, w22, #16",
@@ -3165,14 +3136,13 @@
]
},
"neg ebx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"neg w7, w20",
"eor w21, w20, w7",
"strb w21, [x28, #708]",
"strb w20, [x28, #708]",
"eor x21, x7, #0x1",
"strb w21, [x28, #706]",
"cmp wzr, w20",
@@ -3182,14 +3152,13 @@
]
},
"neg rbx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x20, x7",
"neg x7, x20",
"eor x21, x20, x7",
"strb w21, [x28, #708]",
"strb w20, [x28, #708]",
"eor x21, x7, #0x1",
"strb w21, [x28, #706]",
"cmp xzr, x20",
@@ -3452,7 +3421,7 @@
]
},
"inc al": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "GROUP3 0xfe /0",
"ExpectedArm64ASM": [
@@ -3461,7 +3430,6 @@
"bfxil x4, x21, #0, #8",
"uxtb w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -3482,7 +3450,7 @@
]
},
"dec al": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "GROUP3 0xfe /1",
"ExpectedArm64ASM": [
@@ -3491,7 +3459,6 @@
"bfxil x4, x21, #0, #8",
"uxtb w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -3512,7 +3479,7 @@
]
},
"inc ax": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
@@ -3521,7 +3488,6 @@
"bfxil x4, x21, #0, #16",
"uxth w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -3542,14 +3508,13 @@
]
},
"inc eax": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"add w4, w20, #0x1 (1)",
"eor w21, w20, #0x1",
"eor w21, w21, w4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -3562,14 +3527,13 @@
]
},
"inc rax": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Optimal": "Yes",
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov x20, x4",
"add x4, x20, #0x1 (1)",
"eor x21, x20, #0x1",
"eor x21, x21, x4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -3582,7 +3546,7 @@
]
},
"dec ax": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
@@ -3591,7 +3555,6 @@
"bfxil x4, x21, #0, #16",
"uxth w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -3612,14 +3575,13 @@
]
},
"dec eax": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Optimal": "No",
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"sub w4, w20, #0x1 (1)",
"eor w21, w20, #0x1",
"eor w21, w21, w4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -3633,14 +3595,13 @@
]
},
"dec rax": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Optimal": "Yes",
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov x20, x4",
"sub x4, x20, #0x1 (1)",
"eor x21, x20, #0x1",
"eor x21, x21, x4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
unittests/InstructionCountCI/Primary_32Bit.json
+22 -12
View File
@@ -94,13 +94,15 @@
]
},
"daa": {
"ExpectedInstructionCount": 55,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": "0x27",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx w21, w20, #29, #1",
"ldrb w22, [x28, #708]",
"ldrb w23, [x28, #706]",
"eor w22, w22, w23",
"ubfx w22, w22, #4, #1",
"uxtb w23, w4",
"and w20, w20, #0xdfffffff",
@@ -152,17 +154,22 @@
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"ldrb w22, [x28, #708]",
"eor w20, w22, w20",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
},
"das": {
"ExpectedInstructionCount": 55,
"ExpectedInstructionCount": 60,
"Optimal": "No",
"Comment": "0x2f",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx w21, w20, #29, #1",
"ldrb w22, [x28, #708]",
"ldrb w23, [x28, #706]",
"eor w22, w22, w23",
"ubfx w22, w22, #4, #1",
"uxtb w23, w4",
"and w20, w20, #0xdfffffff",
@@ -214,15 +221,20 @@
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"ldrb w22, [x28, #708]",
"eor w20, w22, w20",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
},
"aaa": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 31,
"Optimal": "No",
"Comment": "0x37",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"ldrb w21, [x28, #706]",
"eor w20, w20, w21",
"ubfx w20, w20, #4, #1",
"uxtb w21, w4",
"uxth w22, w4",
@@ -254,11 +266,13 @@
]
},
"aas": {
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 32,
"Optimal": "No",
"Comment": "0x3f",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"ldrb w21, [x28, #706]",
"eor w20, w20, w21",
"ubfx w20, w20, #4, #1",
"uxtb w21, w4",
"uxth w22, w4",
@@ -291,7 +305,7 @@
]
},
"inc ax": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": "0x40",
"ExpectedArm64ASM": [
@@ -301,7 +315,6 @@
"bfxil x4, x4, #0, #32",
"uxth w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -322,7 +335,7 @@
]
},
"inc eax": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Optimal": "No",
"Comment": "0x40",
"ExpectedArm64ASM": [
@@ -330,7 +343,6 @@
"add w4, w20, #0x1 (1)",
"bfxil x4, x4, #0, #32",
"eor w21, w20, #0x1",
"eor w21, w21, w4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
@@ -343,7 +355,7 @@
]
},
"dec ax": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": "0x48",
"ExpectedArm64ASM": [
@@ -353,7 +365,6 @@
"bfxil x4, x4, #0, #32",
"uxth w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -374,7 +385,7 @@
]
},
"dec eax": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 14,
"Optimal": "No",
"Comment": "0x48",
"ExpectedArm64ASM": [
@@ -382,7 +393,6 @@
"sub w4, w20, #0x1 (1)",
"bfxil x4, x4, #0, #32",
"eor w21, w20, #0x1",
"eor w21, w21, w4",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
unittests/InstructionCountCI/Secondary.json
+16 -32
View File
@@ -2494,7 +2494,7 @@
]
},
"cmpxchg al, bl": {
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 29,
"Optimal": "No",
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
@@ -2510,7 +2510,6 @@
"sub x20, x22, x23",
"uxtb x20, w20",
"eor w21, w22, w23",
"eor w21, w21, w20",
"strb w21, [x28, #708]",
"eor x21, x20, #0x1",
"strb w21, [x28, #706]",
@@ -2531,7 +2530,7 @@
]
},
"cmpxchg [rax], bl": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 26,
"Optimal": "No",
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
@@ -2544,7 +2543,6 @@
"sub w22, w21, w20",
"uxtb w22, w22",
"eor w23, w21, w20",
"eor w23, w23, w22",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
@@ -2565,7 +2563,7 @@
]
},
"cmpxchg ax, bx": {
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 29,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2581,7 +2579,6 @@
"sub x20, x22, x23",
"uxth x20, w20",
"eor w21, w22, w23",
"eor w21, w21, w20",
"strb w21, [x28, #708]",
"eor x21, x20, #0x1",
"strb w21, [x28, #706]",
@@ -2602,7 +2599,7 @@
]
},
"cmpxchg [rax], bx": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 26,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2615,7 +2612,6 @@
"sub w22, w21, w20",
"uxth w22, w22",
"eor w23, w21, w20",
"eor w23, w23, w22",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
@@ -2636,7 +2632,7 @@
]
},
"cmpxchg eax, ebx": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 21,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2654,7 +2650,6 @@
"mov x4, x20",
"sub x20, x24, x25",
"eor w21, w24, w25",
"eor w21, w21, w20",
"strb w21, [x28, #708]",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
@@ -2665,7 +2660,7 @@
]
},
"cmpxchg [rax], ebx": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2679,7 +2674,6 @@
"csel x4, x21, x20, eq",
"sub w21, w22, w20",
"eor w23, w22, w20",
"eor w23, w23, w21",
"strb w23, [x28, #708]",
"eor x21, x21, #0x1",
"strb w21, [x28, #706]",
@@ -2690,7 +2684,7 @@
]
},
"cmpxchg rax, rbx": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 17,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2704,7 +2698,6 @@
"mov x4, x20",
"sub x20, x21, x22",
"eor x23, x21, x22",
"eor x23, x23, x20",
"strb w23, [x28, #708]",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
@@ -2715,7 +2708,7 @@
]
},
"cmpxchg [rax], rbx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2725,7 +2718,6 @@
"mov x4, x1",
"sub x21, x20, x4",
"eor x22, x20, x4",
"eor x22, x22, x21",
"strb w22, [x28, #708]",
"eor x21, x21, #0x1",
"strb w21, [x28, #706]",
@@ -3275,7 +3267,7 @@
]
},
"xadd al, bl": {
"ExpectedInstructionCount": 25,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
@@ -3286,7 +3278,6 @@
"bfxil x4, x22, #0, #8",
"uxtb w22, w22",
"eor w23, w20, w21",
"eor w23, w23, w22",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
@@ -3307,7 +3298,7 @@
]
},
"xadd [rax], bl": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
@@ -3317,7 +3308,6 @@
"add w22, w21, w20",
"uxtb w22, w22",
"eor w23, w21, w20",
"eor w23, w23, w22",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
@@ -3338,7 +3328,7 @@
]
},
"xadd ax, bx": {
"ExpectedInstructionCount": 25,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3349,7 +3339,6 @@
"bfxil x4, x22, #0, #16",
"uxth w22, w22",
"eor w23, w20, w21",
"eor w23, w23, w22",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
@@ -3370,7 +3359,7 @@
]
},
"xadd [rax], bx": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3380,7 +3369,6 @@
"add w22, w21, w20",
"uxth w22, w22",
"eor w23, w21, w20",
"eor w23, w23, w22",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
@@ -3401,7 +3389,7 @@
]
},
"xadd eax, ebx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3410,7 +3398,6 @@
"add w4, w20, w21",
"mov x7, x20",
"eor w22, w20, w21",
"eor w22, w22, w4",
"strb w22, [x28, #708]",
"eor x22, x4, #0x1",
"strb w22, [x28, #706]",
@@ -3420,7 +3407,7 @@
]
},
"xadd [rax], ebx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "Yes",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3428,7 +3415,6 @@
"ldaddal w20, w7, [x4]",
"add w21, w7, w20",
"eor w22, w7, w20",
"eor w22, w22, w21",
"strb w22, [x28, #708]",
"eor x21, x21, #0x1",
"strb w21, [x28, #706]",
@@ -3438,7 +3424,7 @@
]
},
"xadd rax, rbx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3447,7 +3433,6 @@
"add x4, x20, x21",
"mov x7, x20",
"eor x22, x20, x21",
"eor x22, x22, x4",
"strb w22, [x28, #708]",
"eor x22, x4, #0x1",
"strb w22, [x28, #706]",
@@ -3457,7 +3442,7 @@
]
},
"xadd [rax], rbx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "Yes",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3465,7 +3450,6 @@
"ldaddal x20, x7, [x4]",
"add x21, x7, x20",
"eor x22, x7, x20",
"eor x22, x22, x21",
"strb w22, [x28, #708]",
"eor x21, x21, #0x1",
"strb w21, [x28, #706]",