IR/Passes/RA: Enable SRA for 32-bit GPRs

Noticed that we hadn't ever enabled this, which was a concern when our
GPR operations weren't as strict about leaving garbage in the upper bits
when operating as a 32-bit operation.

Now that our ALU operations are more strict about enforcing upper bit
zeroing we can enable this.

This causes Half-Life: Source FPS to get to > 200FPS finally. Causes
significant performance improvements for 32-bit games because we're no
longer redundantly moving registers before and after every operation.
Causing a bunch of 3-4 instruction sequences to convert to 1.

FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp

@@ -548,7 +548,7 @@ namespace {
     auto IsPreWritable = [](uint8_t Size, RegisterClassType StaticClass) {
       LOGMAN_THROW_A_FMT(StaticClass == GPRFixedClass || StaticClass == FPRFixedClass, "Unexpected static class {}", StaticClass);
       if (StaticClass == GPRFixedClass) {
-        return Size == 8;
+        return Size == 8 || Size == 4;
       } else if (StaticClass == FPRFixedClass) {
         return Size == 16;
       }
@@ -560,7 +560,7 @@ namespace {
       LOGMAN_THROW_A_FMT(StaticClass == GPRFixedClass || StaticClass == FPRFixedClass, "Unexpected static class {}", StaticClass);
       if (StaticClass == GPRFixedClass) {
         // We need more meta info to support not-size-of-reg
-        return (Size == 8 /*|| Size == 4*/) && ((Offset & 7) == 0);
+        return (Size == 8 || Size == 4) && ((Offset & 7) == 0);
       } else if (StaticClass == FPRFixedClass) {
         // We need more meta info to support not-size-of-reg
         return (Size == 16 /*|| Size == 8 || Size == 4*/) && ((Offset & 15) == 0);