InstCountCI: Update for FCW optimization

This commit is contained in:
Ryan Houdek committed 2023-09-12 05:21:06 -07:00
1 parent 76bd81af15
commit 97a6184e53
2 files changed
+2264 -2285

No files matched your search

@@ -1039,52 +1039,11 @@
]
},
"fxrstor [rax]": {
"ExpectedInstructionCount": 105,
"ExpectedInstructionCount": 64,
"Optimal": "No",
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"stp x8, x9, [x28, #40]",
"stp x10, x11, [x28, #56]",
"stp x12, x13, [x28, #72]",
"stp x14, x15, [x28, #88]",
"stp x16, x17, [x28, #104]",
"stp x19, x29, [x28, #120]",
"add x0, x28, #0xc0 (192)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"sub sp, sp, #0xf0 (240)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
"str x30, [x0]",
"uxth w0, w20",
"ldr x1, [x28, #1144]",
"blr x1",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
"ldr x30, [sp], #16",
"add x5, x28, #0xc0 (192)",
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldp x8, x9, [x28, #40]",
"ldp x10, x11, [x28, #56]",
"ldp x12, x13, [x28, #72]",
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"strh w20, [x28, #1008]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
@@ -1350,7 +1309,7 @@
]
},
"xrstor [rax]": {
"ExpectedInstructionCount": 194,
"ExpectedInstructionCount": 112,
"Optimal": "No",
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
@@ -1358,49 +1317,8 @@
"ldr x21, [x20, #512]",
"ubfx x22, x21, #0, #1",
"cbnz x22, #+0x8",
"b #+0x128",
"b #+0x84",
"ldrh w22, [x20]",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"stp x8, x9, [x28, #40]",
"stp x10, x11, [x28, #56]",
"stp x12, x13, [x28, #72]",
"stp x14, x15, [x28, #88]",
"stp x16, x17, [x28, #104]",
"stp x19, x29, [x28, #120]",
"add x0, x28, #0xc0 (192)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"sub sp, sp, #0xf0 (240)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
"str x30, [x0]",
"uxth w0, w22",
"ldr x1, [x28, #1144]",
"blr x1",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
"ldr x30, [sp], #16",
"add x5, x28, #0xc0 (192)",
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldp x8, x9, [x28, #40]",
"ldp x10, x11, [x28, #56]",
"ldp x12, x13, [x28, #72]",
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"strh w22, [x28, #1008]",
"ldrh w22, [x20, #2]",
"ubfx w23, w22, #11, #3",
@@ -1431,50 +1349,9 @@
"str q2, [x28, #848]",
"ldr q2, [x20, #144]",
"str q2, [x28, #864]",
"b #+0xf0",
"b #+0x4c",
"mov w22, #0x0",
"mov w23, #0x37f",
"stp x4, x5, [x28, #8]",
"stp x6, x7, [x28, #24]",
"stp x8, x9, [x28, #40]",
"stp x10, x11, [x28, #56]",
"stp x12, x13, [x28, #72]",
"stp x14, x15, [x28, #88]",
"stp x16, x17, [x28, #104]",
"stp x19, x29, [x28, #120]",
"add x0, x28, #0xc0 (192)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"sub sp, sp, #0xf0 (240)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64",
"st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64",
"str x30, [x0]",
"uxth w0, w23",
"ldr x1, [x28, #1144]",
"blr x1",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
"ldr x30, [sp], #16",
"add x5, x28, #0xc0 (192)",
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
"ldp x4, x5, [x28, #8]",
"ldp x6, x7, [x28, #24]",
"ldp x8, x9, [x28, #40]",
"ldp x10, x11, [x28, #56]",
"ldp x12, x13, [x28, #72]",
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"strh w23, [x28, #1008]",
"strb w22, [x28, #747]",
"strb w22, [x28, #744]",
File diff suppressed because it is too large. Load diff