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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2023-09-15 12:33:53 -04:00
1 parent d29b8bab36
commit 2385c275ac
3 files changed
+126 -153
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unittests/InstructionCountCI/Primary.json
+6 -9
View File
@@ -3100,19 +3100,18 @@
"ExpectedArm64ASM": []
},
"pushf": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 43,
"Optimal": "No",
"Comment": "0x9c",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx w21, w20, #29, #1",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s2, w22",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x22, x23, x22",
"and x22, x22, #0x1",
"orr x21, x21, x22, lsl #2",
"ldrb w22, [x28, #708]",
"ldrb w23, [x28, #706]",
@@ -3151,19 +3150,18 @@
]
},
"pushfq": {
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 43,
"Optimal": "No",
"Comment": "0x9c",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx w21, w20, #29, #1",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s2, w22",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x22, x23, x22",
"and x22, x22, #0x1",
"orr x21, x21, x22, lsl #2",
"ldrb w22, [x28, #708]",
"ldrb w23, [x28, #706]",
@@ -3275,19 +3273,18 @@
]
},
"lahf": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 19,
"Optimal": "Yes",
"Comment": "0x9f",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx w21, w20, #29, #1",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s2, w22",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x22, x23, x22",
"and x22, x22, #0x1",
"orr x21, x21, x22, lsl #2",
"ldrb w22, [x28, #708]",
"ldrb w23, [x28, #706]",
unittests/InstructionCountCI/Secondary.json
+24 -32
View File
@@ -687,107 +687,101 @@
]
},
"cmovpe ax, bx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s2, w22",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x22, x23, x22",
"and x22, x22, #0x1",
"cmp x22, #0x0 (0)",
"csel w20, w20, w21, ne",
"bfxil x4, x20, #0, #16"
]
},
"cmovpe eax, ebx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s2, w22",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x22, x23, x22",
"and x22, x22, #0x1",
"cmp x22, #0x0 (0)",
"csel w4, w20, w21, ne"
]
},
"cmovpe rax, rbx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"mov w21, #0x1",
"eor w20, w20, #0x1",
"fmov s2, w20",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"and x20, x21, x20",
"and x20, x20, #0x1",
"cmp x20, #0x0 (0)",
"csel x4, x7, x4, ne"
]
},
"cmovnp ax, bx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s2, w22",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x22, x23, x22",
"and x22, x22, #0x1",
"cmp x22, #0x0 (0)",
"csel w20, w20, w21, eq",
"bfxil x4, x20, #0, #16"
]
},
"cmovnp eax, ebx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s2, w22",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x22, x23, x22",
"and x22, x22, #0x1",
"cmp x22, #0x0 (0)",
"csel w4, w20, w21, eq"
]
},
"cmovnp rax, rbx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"mov w21, #0x1",
"eor w20, w20, #0x1",
"fmov s2, w20",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"and x20, x21, x20",
"and x20, x20, #0x1",
"cmp x20, #0x0 (0)",
"csel x4, x7, x4, eq"
]
@@ -1708,34 +1702,32 @@
]
},
"setpe al": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "Yes",
"Comment": "0x0f 0x9a",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"ldrb w20, [x28, #706]",
"eor w20, w20, #0x1",
"fmov s2, w20",
"cnt v2.16b, v2.16b",
"umov w21, v2.b[0]",
"and x20, x20, x21",
"umov w20, v2.b[0]",
"and x20, x20, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, ne",
"bfxil x4, x20, #0, #8"
]
},
"setnp al": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "Yes",
"Comment": "0x0f 0x9b",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"ldrb w20, [x28, #706]",
"eor w20, w20, #0x1",
"fmov s2, w20",
"cnt v2.16b, v2.16b",
"umov w21, v2.b[0]",
"and x20, x20, x21",
"umov w20, v2.b[0]",
"and x20, x20, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"bfxil x4, x20, #0, #8"
unittests/InstructionCountCI/x87.json
+96 -112
View File
@@ -8988,20 +8988,19 @@
]
},
"fcmovu st0, st0": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xda 11b 0xd8 /1"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov w21, #0x0",
"mov x22, #0xffffffffffffffff",
@@ -9021,20 +9020,19 @@
]
},
"fcmovu st0, st1": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xda 11b 0xd9 /1"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov w21, #0x0",
"mov x22, #0xffffffffffffffff",
@@ -9054,20 +9052,19 @@
]
},
"fcmovu st0, st2": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xda 11b 0xda /1"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov w21, #0x0",
"mov x22, #0xffffffffffffffff",
@@ -9087,20 +9084,19 @@
]
},
"fcmovu st0, st3": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xda 11b 0xdb /1"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov w21, #0x0",
"mov x22, #0xffffffffffffffff",
@@ -9120,20 +9116,19 @@
]
},
"fcmovu st0, st4": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xda 11b 0xdc /1"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov w21, #0x0",
"mov x22, #0xffffffffffffffff",
@@ -9153,20 +9148,19 @@
]
},
"fcmovu st0, st5": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xda 11b 0xdd /1"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov w21, #0x0",
"mov x22, #0xffffffffffffffff",
@@ -9186,20 +9180,19 @@
]
},
"fcmovu st0, st6": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xda 11b 0xde /1"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov w21, #0x0",
"mov x22, #0xffffffffffffffff",
@@ -9219,20 +9212,19 @@
]
},
"fcmovu st0, st7": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xda 11b 0xdf /1"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov w21, #0x0",
"mov x22, #0xffffffffffffffff",
@@ -10291,20 +10283,19 @@
]
},
"fcmovnu st0, st0": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xd8 /3"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov x21, #0xffffffffffffffff",
"mov w22, #0x0",
@@ -10324,20 +10315,19 @@
]
},
"fcmovnu st0, st1": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xd9 /3"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov x21, #0xffffffffffffffff",
"mov w22, #0x0",
@@ -10357,20 +10347,19 @@
]
},
"fcmovnu st0, st2": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xda /3"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov x21, #0xffffffffffffffff",
"mov w22, #0x0",
@@ -10390,20 +10379,19 @@
]
},
"fcmovnu st0, st3": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xdb /3"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov x21, #0xffffffffffffffff",
"mov w22, #0x0",
@@ -10423,20 +10411,19 @@
]
},
"fcmovnu st0, st4": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xdc /3"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov x21, #0xffffffffffffffff",
"mov w22, #0x0",
@@ -10456,20 +10443,19 @@
]
},
"fcmovnu st0, st5": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xdd /3"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov x21, #0xffffffffffffffff",
"mov w22, #0x0",
@@ -10489,20 +10475,19 @@
]
},
"fcmovnu st0, st6": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xde /3"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov x21, #0xffffffffffffffff",
"mov w22, #0x0",
@@ -10522,20 +10507,19 @@
]
},
"fcmovnu st0, st7": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xdf /3"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s2, w22",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s2, w21",
"cnt v2.16b, v2.16b",
"umov w22, v2.b[0]",
"and x21, x21, x22",
"umov w21, v2.b[0]",
"and x21, x21, #0x1",
"orr x20, x20, x21, lsl #2",
"mov x21, #0xffffffffffffffff",
"mov w22, #0x0",