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Merge pull request #3055 from Sonicadvance1/defer_disasm_init
Arm64: Only allocate vixl::Decoder if enabled
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@@ -161,7 +161,12 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl *ctx, size_t size)
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Simulator.SetVectorLengthInBits(ForceSVEWidth() ? ForceSVEWidth() : 256);
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#endif
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#ifdef VIXL_DISASSEMBLER
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DisasmDecoder.AppendVisitor(&Disasm);
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// Only setup the disassembler if enabled.
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// vixl's decoder is expensive to setup.
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if (Disassemble()) {
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DisasmDecoder = fextl::make_unique<vixl::aarch64::Decoder>();
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DisasmDecoder->AppendVisitor(&Disasm);
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}
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#endif
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CPU.SetUp();
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@@ -181,7 +181,7 @@ protected:
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#ifdef VIXL_DISASSEMBLER
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vixl::aarch64::Disassembler Disasm;
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vixl::aarch64::Decoder DisasmDecoder;
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fextl::unique_ptr<vixl::aarch64::Decoder> DisasmDecoder;
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FEX_CONFIG_OPT(Disassemble, DISASSEMBLE);
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#endif
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@@ -497,7 +497,7 @@ void Arm64Dispatcher::EmitDispatcher() {
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if (Disassemble() & FEXCore::Config::Disassemble::DISPATCHER) {
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const auto DisasmEnd = GetCursorAddress<const vixl::aarch64::Instruction*>();
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for (auto PCToDecode = DisasmBegin; PCToDecode < DisasmEnd; PCToDecode += 4) {
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DisasmDecoder.Decode(PCToDecode);
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DisasmDecoder->Decode(PCToDecode);
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auto Output = Disasm.GetOutput();
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LogMan::Msg::IFmt("{}", Output);
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}
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@@ -1189,7 +1189,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
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const auto DisasmEnd = reinterpret_cast<const vixl::aarch64::Instruction*>(JITBlockTailLocation);
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LogMan::Msg::IFmt("Disassemble Begin");
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for (auto PCToDecode = DisasmBegin; PCToDecode < DisasmEnd; PCToDecode += 4) {
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DisasmDecoder.Decode(PCToDecode);
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DisasmDecoder->Decode(PCToDecode);
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auto Output = Disasm.GetOutput();
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LogMan::Msg::IFmt("{}", Output);
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}
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