Merge pull request #3055 from Sonicadvance1/defer_disasm_init

Arm64: Only allocate vixl::Decoder if enabled
This commit is contained in:
Mai authored and GitHub committed 2023-09-03 18:58:42 -04:00
commit 2d78b1fbca
4 files changed
+9 -4

No files matched your search

@@ -161,7 +161,12 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl *ctx, size_t size)
Simulator.SetVectorLengthInBits(ForceSVEWidth() ? ForceSVEWidth() : 256);
#endif
#ifdef VIXL_DISASSEMBLER
DisasmDecoder.AppendVisitor(&Disasm);
// Only setup the disassembler if enabled.
// vixl's decoder is expensive to setup.
if (Disassemble()) {
DisasmDecoder = fextl::make_unique<vixl::aarch64::Decoder>();
DisasmDecoder->AppendVisitor(&Disasm);
}
#endif
CPU.SetUp();
@@ -181,7 +181,7 @@ protected:
#ifdef VIXL_DISASSEMBLER
vixl::aarch64::Disassembler Disasm;
vixl::aarch64::Decoder DisasmDecoder;
fextl::unique_ptr<vixl::aarch64::Decoder> DisasmDecoder;
FEX_CONFIG_OPT(Disassemble, DISASSEMBLE);
#endif
@@ -497,7 +497,7 @@ void Arm64Dispatcher::EmitDispatcher() {
if (Disassemble() & FEXCore::Config::Disassemble::DISPATCHER) {
const auto DisasmEnd = GetCursorAddress<const vixl::aarch64::Instruction*>();
for (auto PCToDecode = DisasmBegin; PCToDecode < DisasmEnd; PCToDecode += 4) {
DisasmDecoder.Decode(PCToDecode);
DisasmDecoder->Decode(PCToDecode);
auto Output = Disasm.GetOutput();
LogMan::Msg::IFmt("{}", Output);
}
@@ -1189,7 +1189,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
const auto DisasmEnd = reinterpret_cast<const vixl::aarch64::Instruction*>(JITBlockTailLocation);
LogMan::Msg::IFmt("Disassemble Begin");
for (auto PCToDecode = DisasmBegin; PCToDecode < DisasmEnd; PCToDecode += 4) {
DisasmDecoder.Decode(PCToDecode);
DisasmDecoder->Decode(PCToDecode);
auto Output = Disasm.GetOutput();
LogMan::Msg::IFmt("{}", Output);
}