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Merge pull request #3063 from alyssarosenzweig/flag/defer-pf-completely

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Defer PF calculation completely
This commit is contained in:
Ryan Houdek authored and GitHub committed 2023-09-05 13:18:22 -07:00
2 parents 8184c55424 5a3dc8c2ab
commit 04228952fa
16 files changed
+852 -1003
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FEXCore/Source/Interface/Core/Core.cpp
+4 -3
View File
@@ -253,7 +253,7 @@ namespace FEXCore::Context {
// PF calculation is deferred, calculate it now.
// Popcount the 8-bit flag and then extract the lower bit.
uint32_t PFByte = Frame->State.flags[X86State::RFLAG_PF_LOC];
uint32_t PF = std::popcount(PFByte) & 1;
uint32_t PF = std::popcount(PFByte ^ 1) & 1;
EFLAGS |= PF << X86State::RFLAG_PF_LOC;
// AF calculation is deferred, calculate it now.
@@ -281,8 +281,9 @@ namespace FEXCore::Context {
Frame->State.flags[i] = (EFLAGS & (1U << i)) ? (1 << 4) : 0;
break;
case X86State::RFLAG_PF_LOC:
// PF is intentional fallthrough here.
// PF calculation for storing back in to internal representation works.
// PF is inverted in our internal representation.
Frame->State.flags[i] = (EFLAGS & (1U << i)) ? 0 : 1;
break;
default:
Frame->State.flags[i] = (EFLAGS & (1U << i)) ? 1 : 0;
break;
FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp
+25 -14
View File
@@ -78,6 +78,12 @@ void OpDispatchBuilder::ZeroMultipleFlags(uint32_t FlagsMask) {
FlagsMask &= ~FullNZCVMask;
}
// PF is stored inverted, so invert it when we zero.
if (FlagsMask & (1u << X86State::RFLAG_PF_LOC)) {
SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(_Constant(1));
FlagsMask &= ~(1u << X86State::RFLAG_PF_LOC);
}
// Handle remaining masks.
for (size_t i = 0; FlagsMask && i < FlagOffsets.size(); ++i) {
const auto FlagOffset = FlagOffsets[i];
@@ -117,6 +123,11 @@ void OpDispatchBuilder::SetPackedRFLAG(bool Lower8, OrderedNode *Src) {
// So we write out the whole flags byte to AF without an extract.
static_assert(FEXCore::X86State::RFLAG_AF_LOC == 4);
SetRFLAG(Src, FEXCore::X86State::RFLAG_AF_LOC);
} else if (FlagOffset == FEXCore::X86State::RFLAG_PF_LOC) {
// PF is stored parity flipped
OrderedNode *Tmp = _Bfe(OpSize::i32Bit, 1, FlagOffset, Src);
Tmp = _Xor(OpSize::i32Bit, Tmp, _Constant(1));
SetRFLAG(Tmp, FlagOffset);
} else {
auto Tmp = _Bfe(OpSize::i32Bit, 1, FlagOffset, Src);
SetRFLAG(Tmp, FlagOffset);
@@ -199,6 +210,11 @@ OrderedNode *OpDispatchBuilder::LoadPF() {
// Read the stored byte. This is the original 8-bit result, it needs parity calculated.
auto PFByte = GetRFLAG(FEXCore::X86State::RFLAG_PF_LOC);
// We will use the bottom bit of the popcount, set if an odd number of bits are set.
// But the x86 parity flag is supposed to be set for an even number of bits.
// Simply invert any bit of the input GPR and that will invert the bottom bit of the
PFByte = _Xor(OpSize::i32Bit, PFByte, _Constant(1));
// Cast the input to a 32-bit FPR. Logically we only need 8-bit, but that would
// generate unwanted an ubfx instruction. VPopcount will ignore the upper bits anyway.
auto InputFPR = _VCastFromGPR(4, 4, PFByte);
@@ -215,8 +231,7 @@ OrderedNode *OpDispatchBuilder::LoadAF() {
// Read the stored byte. This is the XOR of the arguments.
auto AFByte = GetRFLAG(FEXCore::X86State::RFLAG_AF_LOC);
// Read the result ^ 1, stored as the PF byte for deferred PF calculation.
// This is the same as result as far as the extracted bit 4 is concerned.
// Read the result, stored as the PF byte for deferred PF calculation.
auto PFByte = GetRFLAG(FEXCore::X86State::RFLAG_PF_LOC);
// What's left is to XOR and extract. This is the deferred part.
@@ -238,25 +253,17 @@ void OpDispatchBuilder::FixupAF() {
}
void OpDispatchBuilder::CalculatePF(OrderedNode *Res, OrderedNode *condition) {
// We will use the bottom bit of the popcount, set if an odd number of bits are set.
// But the x86 parity flag is supposed to be set for an even number of bits.
// Simply invert any bit of the input GPR and that will invert the bottom bit of the
// output FPR.
OrderedNode *Flipped = _Xor(OpSize::i64Bit, Res, _Constant(1));
// For shifts, we can only update for nonzero shift. If zero, we nop out the flag write by
// writing the existing value. Note we call GetRFLAG directly, rather than LoadPF, because
// we need the existing /encoded/ value rather than the decoded PF value. In particular,
// this does not calculate a popcount.
if (condition) {
auto OldFlag = GetRFLAG(FEXCore::X86State::RFLAG_PF_LOC);
Flipped = _Select(FEXCore::IR::COND_EQ, condition, _Constant(0), OldFlag, Flipped);
Res = _Select(FEXCore::IR::COND_EQ, condition, _Constant(0), OldFlag, Res);
}
// To go from the 8-bit value to the 1-bit flag, we need a popcount. That
// will happen on load, on the assumption that PF is written much more often
// than it's read. Store the value now without the popcount.
SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(Flipped);
// Calculation is entirely deferred until load, just store the 8-bit result.
SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(Res);
}
void OpDispatchBuilder::CalculateAF(OpSize OpSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
@@ -996,7 +1003,11 @@ void OpDispatchBuilder::CalculateFlags_FCMP(uint8_t SrcSize, OrderedNode *Res, O
SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(HostFlag_CF);
SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(HostFlag_ZF);
SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(HostFlag_Unordered);
// PF is stored inverted, so invert from the host flag.
// TODO: This could perhaps be optimized?
auto PF = _Xor(OpSize::i32Bit, HostFlag_Unordered, _Constant(1));
SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(PF);
// Zero AF. Note that we set the PF byte to 0/1 above, so PF[4] is 0 so the
// XOR with PF will have no effect, so setting the AF byte to zero will indeed
FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+19 -10
View File
@@ -3992,10 +3992,13 @@ void OpDispatchBuilder::PTestOp(OpcodeArgs) {
SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(Test1);
SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(Test2);
SetAF(0);
SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(ZeroConst);
SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(ZeroConst);
SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(ZeroConst);
uint32_t FlagsMaskToZero =
(1U << X86State::RFLAG_PF_LOC) |
(1U << X86State::RFLAG_AF_LOC) |
(1U << X86State::RFLAG_SF_LOC) |
(1U << X86State::RFLAG_OF_LOC);
ZeroMultipleFlags(FlagsMaskToZero);
}
void OpDispatchBuilder::VTESTOpImpl(OpcodeArgs, size_t ElementSize) {
@@ -4036,10 +4039,13 @@ void OpDispatchBuilder::VTESTOpImpl(OpcodeArgs, size_t ElementSize) {
SetRFLAG<X86State::RFLAG_ZF_LOC>(ZFResult);
SetRFLAG<X86State::RFLAG_CF_LOC>(CFResult);
SetAF(0);
SetRFLAG<X86State::RFLAG_SF_LOC>(ZeroConst);
SetRFLAG<X86State::RFLAG_OF_LOC>(ZeroConst);
SetRFLAG<X86State::RFLAG_PF_LOC>(ZeroConst);
uint32_t FlagsMaskToZero =
(1U << X86State::RFLAG_PF_LOC) |
(1U << X86State::RFLAG_AF_LOC) |
(1U << X86State::RFLAG_SF_LOC) |
(1U << X86State::RFLAG_OF_LOC);
ZeroMultipleFlags(FlagsMaskToZero);
}
template <size_t ElementSize>
@@ -4759,8 +4765,11 @@ void OpDispatchBuilder::PCMPXSTRXOpImpl(OpcodeArgs, bool IsExplicit, bool IsMask
SetRFLAG<X86State::RFLAG_CF_LOC>(GetFlagBit(18));
SetRFLAG<X86State::RFLAG_OF_LOC>(GetFlagBit(19));
SetAF(0);
SetRFLAG<X86State::RFLAG_PF_LOC>(ZeroConst);
uint32_t FlagsMaskToZero =
(1U << X86State::RFLAG_PF_LOC) |
(1U << X86State::RFLAG_AF_LOC);
ZeroMultipleFlags(FlagsMaskToZero);
}
void OpDispatchBuilder::VPCMPESTRIOp(OpcodeArgs) {
FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
+5 -1
View File
@@ -762,7 +762,11 @@ void OpDispatchBuilder::FCOMI(OpcodeArgs) {
SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(HostFlag_CF);
SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(HostFlag_ZF);
SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(HostFlag_Unordered);
// PF is stored inverted, so invert from the host flag.
// TODO: This could perhaps be optimized?
auto PF = _Xor(OpSize::i32Bit, HostFlag_Unordered, _Constant(1));
SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(PF);
}
if constexpr (poptwice) {
FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp
+5 -1
View File
@@ -721,7 +721,11 @@ void OpDispatchBuilder::FCOMIF64(OpcodeArgs) {
SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(HostFlag_CF);
SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(HostFlag_ZF);
SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(HostFlag_Unordered);
// PF is stored inverted, so invert from the host flag.
// TODO: This could perhaps be optimized?
auto PF = _Xor(OpSize::i32Bit, HostFlag_Unordered, _Constant(1));
SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(PF);
}
if constexpr (poptwice) {
unittests/InstructionCountCI/H0F38.json
+7 -6
View File
@@ -416,7 +416,7 @@
]
},
"ptest xmm0, xmm1": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0x66 0x0f 0x38 0x17"
@@ -431,19 +431,20 @@
"umov w20, v4.h[0]",
"umov w21, v5.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w23, [x28, #728]",
"mov w0, w23",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"and w20, w20, #0x7fffffff",
"and w20, w20, #0xefffffff",
"strb w22, [x28, #706]",
"str w20, [x28, #728]"
]
},
unittests/InstructionCountCI/Primary.json
+305 -428
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/PrimaryGroup.json
+184 -278
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/Primary_32Bit.json
+14 -24
View File
@@ -94,7 +94,7 @@
]
},
"daa": {
"ExpectedInstructionCount": 60,
"ExpectedInstructionCount": 59,
"Optimal": "No",
"Comment": "0x27",
"ExpectedArm64ASM": [
@@ -152,7 +152,6 @@
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"ldrb w22, [x28, #708]",
"eor w20, w22, w20",
@@ -161,7 +160,7 @@
]
},
"das": {
"ExpectedInstructionCount": 60,
"ExpectedInstructionCount": 59,
"Optimal": "No",
"Comment": "0x2f",
"ExpectedArm64ASM": [
@@ -219,7 +218,6 @@
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"ldrb w22, [x28, #708]",
"eor w20, w22, w20",
@@ -305,7 +303,7 @@
]
},
"inc ax": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "0x40",
"ExpectedArm64ASM": [
@@ -316,8 +314,7 @@
"uxth w21, w21",
"eor w22, w20, #0x1",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #706]",
"ldr w22, [x28, #728]",
"ubfx w22, w22, #29, #1",
"lsl w23, w21, #16",
@@ -335,7 +332,7 @@
]
},
"inc eax": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x40",
"ExpectedArm64ASM": [
@@ -344,8 +341,7 @@
"bfxil x4, x4, #0, #32",
"eor w21, w20, #0x1",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
"strb w4, [x28, #706]",
"ldr w21, [x28, #728]",
"ubfx w21, w21, #29, #1",
"cmn w20, #0x1 (1)",
@@ -355,7 +351,7 @@
]
},
"dec ax": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "0x48",
"ExpectedArm64ASM": [
@@ -366,8 +362,7 @@
"uxth w21, w21",
"eor w22, w20, #0x1",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #706]",
"ldr w22, [x28, #728]",
"ubfx w22, w22, #29, #1",
"lsl w23, w21, #16",
@@ -385,7 +380,7 @@
]
},
"dec eax": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 13,
"Optimal": "No",
"Comment": "0x48",
"ExpectedArm64ASM": [
@@ -394,8 +389,7 @@
"bfxil x4, x4, #0, #32",
"eor w21, w20, #0x1",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
"strb w4, [x28, #706]",
"ldr w21, [x28, #728]",
"ubfx w21, w21, #29, #1",
"cmp w20, #0x1 (1)",
@@ -500,7 +494,7 @@
]
},
"aam": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": "0xd4",
"ExpectedArm64ASM": [
@@ -525,13 +519,12 @@
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"aad": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": "0xd5",
"ExpectedArm64ASM": [
@@ -556,13 +549,12 @@
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"db 0xd4, 0x40": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"aam with a different immediate byte base",
@@ -590,13 +582,12 @@
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"db 0xd5, 0x40": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": [
"aad with a different immediate byte base",
@@ -623,7 +614,6 @@
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
unittests/InstructionCountCI/Secondary.json
+85 -106
View File
@@ -200,7 +200,7 @@
]
},
"ucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "0x0f 0x2e",
"ExpectedArm64ASM": [
@@ -219,6 +219,7 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
@@ -228,7 +229,7 @@
]
},
"comiss xmm0, xmm1": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "0x0f 0x2f",
"ExpectedArm64ASM": [
@@ -247,6 +248,7 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
@@ -688,17 +690,18 @@
]
},
"cmovpe ax, bx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
"mov w23, #0x1",
"and x22, x23, x22",
"cmp x22, #0x0 (0)",
"csel w20, w20, w21, ne",
@@ -706,49 +709,52 @@
]
},
"cmovpe eax, ebx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
"mov w23, #0x1",
"and x22, x23, x22",
"cmp x22, #0x0 (0)",
"csel w4, w20, w21, ne"
]
},
"cmovpe rax, rbx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"mov w21, #0x1",
"eor w20, w20, #0x1",
"fmov s4, w20",
"cnt v4.16b, v4.16b",
"umov w20, v4.b[0]",
"mov w21, #0x1",
"and x20, x21, x20",
"cmp x20, #0x0 (0)",
"csel x4, x7, x4, ne"
]
},
"cmovnp ax, bx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
"mov w23, #0x1",
"and x22, x23, x22",
"cmp x22, #0x0 (0)",
"csel w20, w20, w21, eq",
@@ -756,32 +762,34 @@
]
},
"cmovnp eax, ebx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"lsr w20, w7, #0",
"lsr w21, w4, #0",
"ldrb w22, [x28, #706]",
"mov w23, #0x1",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
"mov w23, #0x1",
"and x22, x23, x22",
"cmp x22, #0x0 (0)",
"csel w4, w20, w21, eq"
]
},
"cmovnp rax, rbx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"mov w21, #0x1",
"eor w20, w20, #0x1",
"fmov s4, w20",
"cnt v4.16b, v4.16b",
"umov w20, v4.b[0]",
"mov w21, #0x1",
"and x20, x21, x20",
"cmp x20, #0x0 (0)",
"csel x4, x7, x4, eq"
@@ -1692,12 +1700,13 @@
]
},
"setpe al": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Optimal": "Yes",
"Comment": "0x0f 0x9a",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s4, w21",
"cnt v4.16b, v4.16b",
"umov w21, v4.b[0]",
@@ -1708,12 +1717,13 @@
]
},
"setnp al": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Optimal": "Yes",
"Comment": "0x0f 0x9b",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldrb w21, [x28, #706]",
"eor w21, w21, #0x1",
"fmov s4, w21",
"cnt v4.16b, v4.16b",
"umov w21, v4.b[0]",
@@ -1923,7 +1933,7 @@
"ExpectedArm64ASM": []
},
"shld ax, bx, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 18,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -1940,8 +1950,7 @@
"orr w22, w22, w23, lsl #30",
"ubfx w23, w21, #15, #1",
"orr w22, w22, w23, lsl #29",
"eor x23, x20, #0x1",
"strb w23, [x28, #706]",
"strb w20, [x28, #706]",
"eor w20, w20, w21",
"ubfx w20, w20, #15, #1",
"orr w20, w22, w20, lsl #28",
@@ -1949,7 +1958,7 @@
]
},
"shld ax, bx, 15": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 15,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -1966,13 +1975,12 @@
"orr w22, w22, w23, lsl #30",
"ubfx w21, w21, #1, #1",
"orr w21, w22, w21, lsl #29",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"shld ax, bx, 16": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 14,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -1988,13 +1996,12 @@
"orr w22, w22, w23, lsl #30",
"ubfx w21, w21, #0, #1",
"orr w21, w22, w21, lsl #29",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"shld ax, bx, 31": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 15,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -2011,7 +2018,6 @@
"orr w22, w22, w23, lsl #30",
"ubfx w21, w21, #1, #1",
"orr w21, w22, w21, lsl #29",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
@@ -2025,7 +2031,7 @@
]
},
"shld eax, ebx, 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -2036,8 +2042,7 @@
"mrs x20, nzcv",
"lsr w22, w21, #31",
"orr w20, w20, w22, lsl #29",
"eor x22, x4, #0x1",
"strb w22, [x28, #706]",
"strb w4, [x28, #706]",
"eor w21, w4, w21",
"lsr w21, w21, #31",
"orr w20, w20, w21, lsl #28",
@@ -2045,7 +2050,7 @@
]
},
"shld eax, ebx, 15": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -2056,13 +2061,12 @@
"mrs x20, nzcv",
"ubfx w21, w21, #17, #1",
"orr w20, w20, w21, lsl #29",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
"strb w4, [x28, #706]",
"str w20, [x28, #728]"
]
},
"shld eax, ebx, 16": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -2073,13 +2077,12 @@
"mrs x20, nzcv",
"ubfx w21, w21, #16, #1",
"orr w20, w20, w21, lsl #29",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
"strb w4, [x28, #706]",
"str w20, [x28, #728]"
]
},
"shld eax, ebx, 31": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -2090,8 +2093,7 @@
"mrs x20, nzcv",
"ubfx w21, w21, #1, #1",
"orr w20, w20, w21, lsl #29",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
"strb w4, [x28, #706]",
"str w20, [x28, #728]"
]
},
@@ -2102,7 +2104,7 @@
"ExpectedArm64ASM": []
},
"shld rax, rbx, 1": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -2112,8 +2114,7 @@
"mrs x21, nzcv",
"lsr x22, x20, #63",
"orr w21, w21, w22, lsl #29",
"eor x22, x4, #0x1",
"strb w22, [x28, #706]",
"strb w4, [x28, #706]",
"eor x20, x4, x20",
"lsr x20, x20, #63",
"orr w20, w21, w20, lsl #28",
@@ -2121,7 +2122,7 @@
]
},
"shld rax, rbx, 15": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -2131,13 +2132,12 @@
"mrs x21, nzcv",
"ubfx x20, x20, #49, #1",
"orr w20, w21, w20, lsl #29",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
"strb w4, [x28, #706]",
"str w20, [x28, #728]"
]
},
"shld rax, rbx, 32": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -2147,13 +2147,12 @@
"mrs x21, nzcv",
"ubfx x20, x20, #32, #1",
"orr w20, w21, w20, lsl #29",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
"strb w4, [x28, #706]",
"str w20, [x28, #728]"
]
},
"shld rax, rbx, 63": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
@@ -2163,13 +2162,12 @@
"mrs x21, nzcv",
"ubfx x20, x20, #1, #1",
"orr w20, w21, w20, lsl #29",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
"strb w4, [x28, #706]",
"str w20, [x28, #728]"
]
},
"shld ax, bx, cl": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 35,
"Optimal": "No",
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
@@ -2185,7 +2183,7 @@
"cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq",
"bfxil x4, x20, #0, #16",
"cbz x22, #+0x60",
"cbz x22, #+0x5c",
"uxth x20, w20",
"ldr w23, [x28, #728]",
"mov w24, #0x10",
@@ -2198,10 +2196,9 @@
"lsr w24, w21, w24",
"ubfx w24, w24, #0, #1",
"orr w24, w25, w24, lsl #29",
"eor x25, x20, #0x1",
"ldrb w26, [x28, #706]",
"ldrb w25, [x28, #706]",
"cmp x22, #0x0 (0)",
"csel x25, x26, x25, eq",
"csel x25, x25, x20, eq",
"strb w25, [x28, #706]",
"eor w20, w21, w20",
"ubfx w20, w20, #15, #1",
@@ -2212,7 +2209,7 @@
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 33,
"ExpectedInstructionCount": 32,
"Optimal": "No",
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
@@ -2228,7 +2225,7 @@
"cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq",
"lsr w4, w20, #0",
"cbz x22, #+0x54",
"cbz x22, #+0x50",
"ubfx x20, x20, #0, #32",
"ldr w23, [x28, #728]",
"tst w20, w20",
@@ -2238,10 +2235,9 @@
"lsr w25, w21, w25",
"ubfx w25, w25, #0, #1",
"orr w24, w24, w25, lsl #29",
"eor x25, x20, #0x1",
"ldrb w26, [x28, #706]",
"ldrb w25, [x28, #706]",
"cmp x22, #0x0 (0)",
"csel x25, x26, x25, eq",
"csel x25, x25, x20, eq",
"strb w25, [x28, #706]",
"eor w20, w21, w20",
"lsr w20, w20, #31",
@@ -2252,7 +2248,7 @@
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 31,
"ExpectedInstructionCount": 30,
"Optimal": "No",
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
@@ -2267,7 +2263,7 @@
"cmp x21, #0x0 (0)",
"csel x22, x20, x22, eq",
"mov x4, x22",
"cbz x21, #+0x50",
"cbz x21, #+0x4c",
"ldr w23, [x28, #728]",
"tst x22, x22",
"mrs x24, nzcv",
@@ -2276,10 +2272,9 @@
"lsr x25, x20, x25",
"ubfx x25, x25, #0, #1",
"orr w24, w24, w25, lsl #29",
"eor x25, x22, #0x1",
"ldrb w26, [x28, #706]",
"ldrb w25, [x28, #706]",
"cmp x21, #0x0 (0)",
"csel x25, x26, x25, eq",
"csel x25, x25, x22, eq",
"strb w25, [x28, #706]",
"eor x20, x20, x22",
"lsr x20, x20, #63",
@@ -2494,7 +2489,7 @@
]
},
"cmpxchg al, bl": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 28,
"Optimal": "No",
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
@@ -2511,8 +2506,7 @@
"uxtb x20, w20",
"eor w21, w22, w23",
"strb w21, [x28, #708]",
"eor x21, x20, #0x1",
"strb w21, [x28, #706]",
"strb w20, [x28, #706]",
"lsl w21, w20, #24",
"and w21, w21, #0x80000000",
"cmp x20, #0x0 (0)",
@@ -2530,7 +2524,7 @@
]
},
"cmpxchg [rax], bl": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
@@ -2544,8 +2538,7 @@
"uxtb w22, w22",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
"strb w22, [x28, #706]",
"lsl w23, w22, #24",
"and w23, w23, #0x80000000",
"cmp x22, #0x0 (0)",
@@ -2563,7 +2556,7 @@
]
},
"cmpxchg ax, bx": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 28,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2580,8 +2573,7 @@
"uxth x20, w20",
"eor w21, w22, w23",
"strb w21, [x28, #708]",
"eor x21, x20, #0x1",
"strb w21, [x28, #706]",
"strb w20, [x28, #706]",
"lsl w21, w20, #16",
"and w21, w21, #0x80000000",
"cmp x20, #0x0 (0)",
@@ -2599,7 +2591,7 @@
]
},
"cmpxchg [rax], bx": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2613,8 +2605,7 @@
"uxth w22, w22",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
"strb w22, [x28, #706]",
"lsl w23, w22, #16",
"and w23, w23, #0x80000000",
"cmp x22, #0x0 (0)",
@@ -2632,7 +2623,7 @@
]
},
"cmpxchg eax, ebx": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 20,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2651,7 +2642,6 @@
"sub x20, x24, x25",
"eor w21, w24, w25",
"strb w21, [x28, #708]",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"cmp w24, w25",
"mrs x20, nzcv",
@@ -2660,7 +2650,7 @@
]
},
"cmpxchg [rax], ebx": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2675,7 +2665,6 @@
"sub w21, w22, w20",
"eor w23, w22, w20",
"strb w23, [x28, #708]",
"eor x21, x21, #0x1",
"strb w21, [x28, #706]",
"cmp w22, w20",
"mrs x20, nzcv",
@@ -2684,7 +2673,7 @@
]
},
"cmpxchg rax, rbx": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 16,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2699,7 +2688,6 @@
"sub x20, x21, x22",
"eor x23, x21, x22",
"strb w23, [x28, #708]",
"eor x20, x20, #0x1",
"strb w20, [x28, #706]",
"cmp x21, x22",
"mrs x20, nzcv",
@@ -2708,7 +2696,7 @@
]
},
"cmpxchg [rax], rbx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
@@ -2719,7 +2707,6 @@
"sub x21, x20, x4",
"eor x22, x20, x4",
"strb w22, [x28, #708]",
"eor x21, x21, #0x1",
"strb w21, [x28, #706]",
"cmp x20, x4",
"mrs x20, nzcv",
@@ -3267,7 +3254,7 @@
]
},
"xadd al, bl": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
@@ -3279,8 +3266,7 @@
"uxtb w22, w22",
"eor w23, w20, w21",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
"strb w22, [x28, #706]",
"lsl w23, w22, #24",
"and w23, w23, #0x80000000",
"cmp x22, #0x0 (0)",
@@ -3298,7 +3284,7 @@
]
},
"xadd [rax], bl": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
@@ -3309,8 +3295,7 @@
"uxtb w22, w22",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
"strb w22, [x28, #706]",
"lsl w23, w22, #24",
"and w23, w23, #0x80000000",
"cmp x22, #0x0 (0)",
@@ -3328,7 +3313,7 @@
]
},
"xadd ax, bx": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3340,8 +3325,7 @@
"uxth w22, w22",
"eor w23, w20, w21",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
"strb w22, [x28, #706]",
"lsl w23, w22, #16",
"and w23, w23, #0x80000000",
"cmp x22, #0x0 (0)",
@@ -3359,7 +3343,7 @@
]
},
"xadd [rax], bx": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3370,8 +3354,7 @@
"uxth w22, w22",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"eor x23, x22, #0x1",
"strb w23, [x28, #706]",
"strb w22, [x28, #706]",
"lsl w23, w22, #16",
"and w23, w23, #0x80000000",
"cmp x22, #0x0 (0)",
@@ -3389,7 +3372,7 @@
]
},
"xadd eax, ebx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3399,15 +3382,14 @@
"mov x7, x20",
"eor w22, w20, w21",
"strb w22, [x28, #708]",
"eor x22, x4, #0x1",
"strb w22, [x28, #706]",
"strb w4, [x28, #706]",
"cmn w20, w21",
"mrs x20, nzcv",
"str w20, [x28, #728]"
]
},
"xadd [rax], ebx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "Yes",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3416,7 +3398,6 @@
"add w21, w7, w20",
"eor w22, w7, w20",
"strb w22, [x28, #708]",
"eor x21, x21, #0x1",
"strb w21, [x28, #706]",
"cmn w7, w20",
"mrs x20, nzcv",
@@ -3424,7 +3405,7 @@
]
},
"xadd rax, rbx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3434,15 +3415,14 @@
"mov x7, x20",
"eor x22, x20, x21",
"strb w22, [x28, #708]",
"eor x22, x4, #0x1",
"strb w22, [x28, #706]",
"strb w4, [x28, #706]",
"cmn x20, x21",
"mrs x20, nzcv",
"str w20, [x28, #728]"
]
},
"xadd [rax], rbx": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "Yes",
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
@@ -3451,7 +3431,6 @@
"add x21, x7, x20",
"eor x22, x7, x20",
"strb w22, [x28, #708]",
"eor x21, x21, #0x1",
"strb w21, [x28, #706]",
"cmn x7, x20",
"mrs x20, nzcv",
unittests/InstructionCountCI/SecondaryGroup.json
+18 -12
View File
@@ -455,7 +455,7 @@
]
},
"rdrand ax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
@@ -465,14 +465,15 @@
"mov x20, x21",
"bfxil x4, x22, #0, #16",
"mov w21, #0x0",
"strb w21, [x28, #706]",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"rdrand eax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
@@ -482,14 +483,15 @@
"mov x20, x21",
"lsr w4, w22, #0",
"mov w21, #0x0",
"strb w21, [x28, #706]",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"rdrand rax": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
@@ -498,14 +500,15 @@
"mov x4, x20",
"mov x20, x21",
"mov w21, #0x0",
"strb w21, [x28, #706]",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"rdseed ax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
@@ -515,14 +518,15 @@
"mov x20, x21",
"bfxil x4, x22, #0, #16",
"mov w21, #0x0",
"strb w21, [x28, #706]",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"rdseed eax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
@@ -532,14 +536,15 @@
"mov x20, x21",
"lsr w4, w22, #0",
"mov w21, #0x0",
"strb w21, [x28, #706]",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
]
},
"rdseed rax": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
@@ -548,7 +553,8 @@
"mov x4, x20",
"mov x20, x21",
"mov w21, #0x0",
"strb w21, [x28, #706]",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #29",
"str w20, [x28, #728]"
unittests/InstructionCountCI/Secondary_OpSize.json
+4 -2
View File
@@ -145,7 +145,7 @@
]
},
"ucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "0x66 0x0f 0x2e",
"ExpectedArm64ASM": [
@@ -164,6 +164,7 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
@@ -173,7 +174,7 @@
]
},
"comisd xmm0, xmm1": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "0x66 0x0f 0x2f",
"ExpectedArm64ASM": [
@@ -192,6 +193,7 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
unittests/InstructionCountCI/Secondary_REP.json
+13 -10
View File
@@ -432,7 +432,7 @@
]
},
"popcnt ax, bx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 14,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
@@ -443,16 +443,17 @@
"umov w20, v0.b[0]",
"bfxil x4, x20, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"strb w21, [x28, #706]",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #30",
"str w20, [x28, #728]"
]
},
"popcnt eax, ebx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 13,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
@@ -462,16 +463,17 @@
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"mov w21, #0x1",
"cmp x4, #0x0 (0)",
"cset x21, eq",
"strb w20, [x28, #706]",
"cset x22, eq",
"strb w21, [x28, #706]",
"strb w20, [x28, #708]",
"lsl x20, x21, #30",
"lsl x20, x22, #30",
"str w20, [x28, #728]"
]
},
"popcnt rax, rbx": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 12,
"Optimal": "No",
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
@@ -480,11 +482,12 @@
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"mov w21, #0x1",
"cmp x4, #0x0 (0)",
"cset x21, eq",
"strb w20, [x28, #706]",
"cset x22, eq",
"strb w21, [x28, #706]",
"strb w20, [x28, #708]",
"lsl x20, x21, #30",
"lsl x20, x22, #30",
"str w20, [x28, #728]"
]
},
unittests/InstructionCountCI/VEX_map1.json
+8 -4
View File
@@ -3779,7 +3779,7 @@
]
},
"vucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"Map 1 0b00 0x2e 128-bit"
@@ -3802,6 +3802,7 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
@@ -3811,7 +3812,7 @@
]
},
"vucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"Map 1 0b01 0x2e 128-bit"
@@ -3834,6 +3835,7 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
@@ -3843,7 +3845,7 @@
]
},
"vcomiss xmm0, xmm1": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"Map 1 0b00 0x2f 128-bit"
@@ -3866,6 +3868,7 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
@@ -3875,7 +3878,7 @@
]
},
"vcomisd xmm0, xmm1": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"Map 1 0b01 0x2f 128-bit"
@@ -3898,6 +3901,7 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
unittests/InstructionCountCI/VEX_map2.json
+46 -42
View File
@@ -593,7 +593,7 @@
]
},
"vtestps xmm0, xmm1": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 30,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0e 128-bit"
@@ -614,24 +614,25 @@
"umov w20, v5.h[0]",
"umov w21, v4.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w23, [x28, #728]",
"mov w0, w23",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"and w20, w20, #0x7fffffff",
"and w20, w20, #0xefffffff",
"strb w22, [x28, #706]",
"str w20, [x28, #728]"
]
},
"vtestps ymm0, ymm1": {
"ExpectedInstructionCount": 37,
"ExpectedInstructionCount": 38,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0e 256-bit"
@@ -660,24 +661,25 @@
"umov w20, v5.h[0]",
"umov w21, v4.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w23, [x28, #728]",
"mov w0, w23",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"and w20, w20, #0x7fffffff",
"and w20, w20, #0xefffffff",
"strb w22, [x28, #706]",
"str w20, [x28, #728]"
]
},
"vtestpd xmm0, xmm1": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 30,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0f 128-bit"
@@ -698,24 +700,25 @@
"umov w20, v5.h[0]",
"umov w21, v4.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w23, [x28, #728]",
"mov w0, w23",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"and w20, w20, #0x7fffffff",
"and w20, w20, #0xefffffff",
"strb w22, [x28, #706]",
"str w20, [x28, #728]"
]
},
"vtestpd ymm0, ymm1": {
"ExpectedInstructionCount": 37,
"ExpectedInstructionCount": 38,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x0f 256-bit"
@@ -744,19 +747,20 @@
"umov w20, v5.h[0]",
"umov w21, v4.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w23, [x28, #728]",
"mov w0, w23",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"and w20, w20, #0x7fffffff",
"and w20, w20, #0xefffffff",
"strb w22, [x28, #706]",
"str w20, [x28, #728]"
]
},
@@ -799,7 +803,7 @@
]
},
"vptest xmm0, xmm1": {
"ExpectedInstructionCount": 25,
"ExpectedInstructionCount": 26,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x16 128-bit"
@@ -816,24 +820,25 @@
"umov w20, v5.h[0]",
"umov w21, v4.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w23, [x28, #728]",
"mov w0, w23",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"and w20, w20, #0x7fffffff",
"and w20, w20, #0xefffffff",
"strb w22, [x28, #706]",
"str w20, [x28, #728]"
]
},
"vptest ymm0, ymm1": {
"ExpectedInstructionCount": 33,
"ExpectedInstructionCount": 34,
"Optimal": "No",
"Comment": [
"Map 2 0b01 0x16 256-bit"
@@ -858,19 +863,20 @@
"umov w20, v5.h[0]",
"umov w21, v4.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"ldr w23, [x28, #728]",
"mov w0, w23",
"ldr w24, [x28, #728]",
"mov w0, w24",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"and w20, w20, #0x7fffffff",
"and w20, w20, #0xefffffff",
"strb w22, [x28, #706]",
"str w20, [x28, #728]"
]
},
@@ -3723,7 +3729,7 @@
]
},
"andn eax, ebx, ecx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": [
"Map 2 0b00 0xf2 32-bit"
@@ -3732,23 +3738,21 @@
"lsr w20, w7, #0",
"lsr w21, w5, #0",
"bic w4, w21, w20",
"eor x20, x4, #0x1",
"strb w20, [x28, #706]",
"strb w4, [x28, #706]",
"tst w4, w4",
"mrs x20, nzcv",
"str w20, [x28, #728]"
]
},
"andn rax, rbx, rcx": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": [
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x4, x5, x7",
"eor x20, x4, #0x1",
"strb w20, [x28, #706]",
"strb w4, [x28, #706]",
"tst x4, x4",
"mrs x20, nzcv",
"str w20, [x28, #728]"
unittests/InstructionCountCI/x87.json
+110 -62
View File
@@ -8715,7 +8715,7 @@
]
},
"fcmovu st0, st0": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xda 11b 0xd8 /1"
@@ -8724,6 +8724,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -8747,7 +8748,7 @@
]
},
"fcmovu st0, st1": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xda 11b 0xd9 /1"
@@ -8756,6 +8757,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -8779,7 +8781,7 @@
]
},
"fcmovu st0, st2": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xda 11b 0xda /1"
@@ -8788,6 +8790,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -8811,7 +8814,7 @@
]
},
"fcmovu st0, st3": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xda 11b 0xdb /1"
@@ -8820,6 +8823,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -8843,7 +8847,7 @@
]
},
"fcmovu st0, st4": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xda 11b 0xdc /1"
@@ -8852,6 +8856,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -8875,7 +8880,7 @@
]
},
"fcmovu st0, st5": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xda 11b 0xdd /1"
@@ -8884,6 +8889,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -8907,7 +8913,7 @@
]
},
"fcmovu st0, st6": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xda 11b 0xde /1"
@@ -8916,6 +8922,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -8939,7 +8946,7 @@
]
},
"fcmovu st0, st7": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xda 11b 0xdf /1"
@@ -8948,6 +8955,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -9997,7 +10005,7 @@
]
},
"fcmovnu st0, st0": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xd8 /3"
@@ -10006,6 +10014,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -10029,7 +10038,7 @@
]
},
"fcmovnu st0, st1": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xd9 /3"
@@ -10038,6 +10047,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -10061,7 +10071,7 @@
]
},
"fcmovnu st0, st2": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xda /3"
@@ -10070,6 +10080,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -10093,7 +10104,7 @@
]
},
"fcmovnu st0, st3": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xdb /3"
@@ -10102,6 +10113,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -10125,7 +10137,7 @@
]
},
"fcmovnu st0, st4": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xdc /3"
@@ -10134,6 +10146,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -10157,7 +10170,7 @@
]
},
"fcmovnu st0, st5": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xdd /3"
@@ -10166,6 +10179,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -10189,7 +10203,7 @@
]
},
"fcmovnu st0, st6": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xde /3"
@@ -10198,6 +10212,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -10221,7 +10236,7 @@
]
},
"fcmovnu st0, st7": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xdf /3"
@@ -10230,6 +10245,7 @@
"mov w20, #0x0",
"mov w21, #0x1",
"ldrb w22, [x28, #706]",
"eor w22, w22, #0x1",
"fmov s4, w22",
"cnt v4.16b, v4.16b",
"umov w22, v4.b[0]",
@@ -10318,7 +10334,7 @@
]
},
"fucomi st0, st0": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xe8 /5"
@@ -10384,12 +10400,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st1": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xe9 /5"
@@ -10455,12 +10472,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st2": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xea /5"
@@ -10526,12 +10544,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st3": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xeb /5"
@@ -10597,12 +10616,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st4": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xec /5"
@@ -10668,12 +10688,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st5": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xed /5"
@@ -10739,12 +10760,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st6": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xee /5"
@@ -10810,12 +10832,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fucomi st0, st7": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xef /5"
@@ -10881,12 +10904,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st0": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf0 /6"
@@ -10952,12 +10976,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st1": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf1 /6"
@@ -11023,12 +11048,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st2": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf2 /6"
@@ -11094,12 +11120,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st3": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf3 /6"
@@ -11165,12 +11192,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st4": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf4 /6"
@@ -11236,12 +11264,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st5": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf5 /6"
@@ -11307,12 +11336,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st6": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf6 /6"
@@ -11378,12 +11408,13 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"fcomi st0, st7": {
"ExpectedInstructionCount": 62,
"ExpectedInstructionCount": 63,
"Optimal": "No",
"Comment": [
"0xdb 11b 0xf7 /6"
@@ -11449,6 +11480,7 @@
"bfi w0, w21, #29, #1",
"mov w21, w0",
"bfi w21, w22, #30, #1",
"eor w20, w20, #0x1",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
@@ -22377,7 +22409,7 @@
]
},
"fucomip st0": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xe8 /5"
@@ -22443,9 +22475,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -22456,7 +22489,7 @@
]
},
"fucomip st1": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xe9 /5"
@@ -22523,6 +22556,7 @@
"bfi w0, w23, #29, #1",
"mov w23, w0",
"bfi w23, w24, #30, #1",
"eor w22, w22, #0x1",
"strb w22, [x28, #706]",
"ldrb w22, [x28, #1010]",
"lsl w21, w21, w20",
@@ -22535,7 +22569,7 @@
]
},
"fucomip st2": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xea /5"
@@ -22601,9 +22635,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -22614,7 +22649,7 @@
]
},
"fucomip st3": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xeb /5"
@@ -22680,9 +22715,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -22693,7 +22729,7 @@
]
},
"fucomip st4": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xec /5"
@@ -22759,9 +22795,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -22772,7 +22809,7 @@
]
},
"fucomip st5": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xed /5"
@@ -22838,9 +22875,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -22851,7 +22889,7 @@
]
},
"fucomip st6": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xee /5"
@@ -22917,9 +22955,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -22930,7 +22969,7 @@
]
},
"fucomip st7": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xef /5"
@@ -22996,9 +23035,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -23009,7 +23049,7 @@
]
},
"fcomip st0": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf0 /6"
@@ -23075,9 +23115,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -23088,7 +23129,7 @@
]
},
"fcomip st1": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf1 /6"
@@ -23155,6 +23196,7 @@
"bfi w0, w23, #29, #1",
"mov w23, w0",
"bfi w23, w24, #30, #1",
"eor w22, w22, #0x1",
"strb w22, [x28, #706]",
"ldrb w22, [x28, #1010]",
"lsl w21, w21, w20",
@@ -23167,7 +23209,7 @@
]
},
"fcomip st2": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf2 /6"
@@ -23233,9 +23275,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -23246,7 +23289,7 @@
]
},
"fcomip st3": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf3 /6"
@@ -23312,9 +23355,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -23325,7 +23369,7 @@
]
},
"fcomip st4": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf4 /6"
@@ -23391,9 +23435,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -23404,7 +23449,7 @@
]
},
"fcomip st5": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf5 /6"
@@ -23470,9 +23515,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -23483,7 +23529,7 @@
]
},
"fcomip st6": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf6 /6"
@@ -23549,9 +23595,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",
@@ -23562,7 +23609,7 @@
]
},
"fcomip st7": {
"ExpectedInstructionCount": 70,
"ExpectedInstructionCount": 71,
"Optimal": "No",
"Comment": [
"0xdf 11b 0xf7 /6"
@@ -23628,9 +23675,10 @@
"bfi w0, w22, #29, #1",
"mov w22, w0",
"bfi w22, w23, #30, #1",
"mov w23, #0x1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"ldrb w21, [x28, #1010]",
"mov w23, #0x1",
"lsl w23, w23, w20",
"bic w21, w21, w23",
"strb w21, [x28, #1010]",