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FEXCore: Minor optimization to StoreRegisterSRA

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{Load,Store}RegisterSRA always loads or stores GPRSize. 8-bit and 16-bit
are vestigial and all OpcodeDispatcher usage will load the full GPR size
(32-bit or 64-bit) and then extract or insert as necessary.

This cleans up a few bits of codegen in InstCountCI.
This commit is contained in:
Ryan Houdek committed 2023-09-12 14:36:08 -07:00
1 parent 90f7937146
commit e6c0bebee9
1 file changed
+3 -21
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FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp
+3 -21
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@@ -302,16 +302,6 @@ DEF_OP(LoadRegisterSRA) {
const auto reg = StaticRegisters[regId];
switch (OpSize) {
case 1:
LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
ubfx(ARMEmitter::Size::i64Bit, GetReg(Node), reg, regOffs * 8, 8);
break;
case 2:
LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
ubfx(ARMEmitter::Size::i64Bit, GetReg(Node), reg, 0, 16);
break;
case 4:
LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
if (GetReg(Node).Idx() != reg.Idx())
@@ -491,19 +481,11 @@ DEF_OP(StoreRegisterSRA) {
const auto Src = GetReg(Op->Value.ID());
switch (OpSize) {
case 1:
LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
bfi(ARMEmitter::Size::i64Bit, reg, Src, regOffs * 8, 8);
break;
case 2:
LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
bfi(ARMEmitter::Size::i64Bit, reg, Src, 0, 16);
break;
case 4:
LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
bfi(ARMEmitter::Size::i64Bit, reg, Src, 0, 32);
if (Src.Idx() != reg.Idx()) {
mov(ARMEmitter::Size::i32Bit, reg, Src);
}
break;
case 8:
LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");