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Arm64/VectorOps: Remove redundant moves from SVE VFMin is possible

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If Dst and Vector1 alias one another, then we can do the merging move
in place instead of shuffling data around.
This commit is contained in:
Lioncache committed 2023-08-23 17:16:25 -04:00
1 parent a40526a541
commit ecf02846e6
2 files changed
+14 -11
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FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
+10 -3
View File
@@ -843,9 +843,16 @@ DEF_OP(VFMin) {
fcmgt(SubRegSize, ComparePred, Mask.Zeroing(),
Vector2.Z(), Vector1.Z());
not_(ComparePred, Mask.Zeroing(), ComparePred);
mov(VTMP1.Z(), Vector1.Z());
mov(SubRegSize, VTMP1.Z(), ComparePred.Merging(), Vector2.Z());
mov(Dst.Z(), VTMP1.Z());
if (Dst == Vector1) {
// Trivial case where Vector1 is also the destination.
// We don't need to move any data around in this case (aside from the merge).
mov(SubRegSize, Dst.Z(), ComparePred.Merging(), Vector2.Z());
} else {
mov(VTMP1.Z(), Vector1.Z());
mov(SubRegSize, VTMP1.Z(), ComparePred.Merging(), Vector2.Z());
mov(Dst.Z(), VTMP1.Z());
}
} else {
if (IsScalar) {
switch (ElementSize) {
unittests/InstructionCountCI/VEX_map1.json
+4 -8
View File
@@ -4336,7 +4336,7 @@
]
},
"vminps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": [
"Map 1 0b00 0x5d 256-bit"
@@ -4346,9 +4346,7 @@
"mov z5.d, p7/m, z18.d",
"fcmgt p0.s, p7/z, z5.s, z4.s",
"not p0.b, p7/z, p0.b",
"mov z0.d, z4.d",
"mov z0.s, p0/m, z5.s",
"mov z4.d, z0.d",
"mov z4.s, p0/m, z5.s",
"mov z16.d, p7/m, z4.d"
]
},
@@ -4368,7 +4366,7 @@
]
},
"vminpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": [
"Map 1 0b01 0x5d 256-bit"
@@ -4378,9 +4376,7 @@
"mov z5.d, p7/m, z18.d",
"fcmgt p0.d, p7/z, z5.d, z4.d",
"not p0.b, p7/z, p0.b",
"mov z0.d, z4.d",
"mov z0.d, p0/m, z5.d",
"mov z4.d, z0.d",
"mov z4.d, p0/m, z5.d",
"mov z16.d, p7/m, z4.d"
]
},