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InstCountCI: Update for previous changes

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Missed thsi in the SRA PR
This commit is contained in:
Ryan Houdek committed 2023-08-27 23:41:41 -07:00
1 parent 6f2b3e76ac
commit f02d291da1
15 files changed
+1540 -1630
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unittests/InstructionCountCI/H0F38.json
+13 -13
View File
@@ -1032,8 +1032,8 @@
"0xf2 0x0f 0x38 0xf0"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"uxtb x21, w7",
"lsr w20, w4, #0",
"uxtb w21, w7",
"crc32cb w4, w20, w21"
]
},
@@ -1044,8 +1044,8 @@
"0xf2 0x0f 0x38 0xf1"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"uxth x21, w7",
"lsr w20, w4, #0",
"uxth w21, w7",
"crc32ch w4, w20, w21"
]
},
@@ -1056,8 +1056,8 @@
"0xf2 0x0f 0x38 0xf1"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"ubfx x21, x7, #0, #32",
"lsr w20, w4, #0",
"lsr w21, w7, #0",
"crc32cw w4, w20, w21"
]
},
@@ -1068,7 +1068,7 @@
"0xf2 0x0f 0x38 0xf0"
],
"ExpectedArm64ASM": [
"uxtb x20, w7",
"uxtb w20, w7",
"crc32cb w4, w4, w20"
]
},
@@ -1090,9 +1090,9 @@
],
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx x21, x20, #29, #1",
"ubfx x22, x7, #0, #32",
"ubfx x23, x4, #0, #32",
"ubfx w21, w20, #29, #1",
"lsr w22, w7, #0",
"lsr w23, w4, #0",
"add w24, w22, w21",
"add w4, w23, w24",
"cmp w4, w22",
@@ -1134,9 +1134,9 @@
],
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx x21, x20, #28, #1",
"ubfx x22, x7, #0, #32",
"ubfx x23, x4, #0, #32",
"ubfx w21, w20, #28, #1",
"lsr w22, w7, #0",
"lsr w23, w4, #0",
"add w24, w22, w21",
"add w4, w23, w24",
"cmp w4, w22",
unittests/InstructionCountCI/H0F3A.json
+6 -6
View File
@@ -730,7 +730,7 @@
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"mov v16.b[0], w20"
]
},
@@ -741,7 +741,7 @@
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"mov v16.b[1], w20"
]
},
@@ -752,7 +752,7 @@
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"mov v16.b[15], w20"
]
},
@@ -793,7 +793,7 @@
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"mov v16.s[0], w20"
]
},
@@ -804,7 +804,7 @@
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"mov v16.s[1], w20"
]
},
@@ -815,7 +815,7 @@
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"mov v16.s[3], w20"
]
},
unittests/InstructionCountCI/Primary.json
+396 -396
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/PrimaryGroup.json
+331 -330
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/Primary_32Bit.json
+212 -302
View File
@@ -9,107 +9,99 @@
},
"Instructions": {
"push es": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x06",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldrh w21, [x28, #136]",
"str w21, [x20, #-4]!",
"bfxil x8, x20, #0, #32"
"ldrh w20, [x28, #136]",
"str w20, [x8, #-4]!",
"bfxil x8, x8, #0, #32"
]
},
"pop es": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x07",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"strh w21, [x28, #136]",
"ubfx x20, x21, #3, #13",
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"bfxil x8, x8, #0, #32",
"strh w20, [x28, #136]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #152]"
]
},
"push cs": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x0e",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldrh w21, [x28, #138]",
"str w21, [x20, #-4]!",
"bfxil x8, x20, #0, #32"
"ldrh w20, [x28, #138]",
"str w20, [x8, #-4]!",
"bfxil x8, x8, #0, #32"
]
},
"push ss": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x16",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldrh w21, [x28, #140]",
"str w21, [x20, #-4]!",
"bfxil x8, x20, #0, #32"
"ldrh w20, [x28, #140]",
"str w20, [x8, #-4]!",
"bfxil x8, x8, #0, #32"
]
},
"pop ss": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x17",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"strh w21, [x28, #140]",
"ubfx x20, x21, #3, #13",
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"bfxil x8, x8, #0, #32",
"strh w20, [x28, #140]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #160]"
]
},
"push ds": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x1e",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldrh w21, [x28, #142]",
"str w21, [x20, #-4]!",
"bfxil x8, x20, #0, #32"
"ldrh w20, [x28, #142]",
"str w20, [x8, #-4]!",
"bfxil x8, x8, #0, #32"
]
},
"pop ds": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x1f",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"strh w21, [x28, #142]",
"ubfx x20, x21, #3, #13",
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"bfxil x8, x8, #0, #32",
"strh w20, [x28, #142]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #164]"
]
},
"daa": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 54,
"Optimal": "No",
"Comment": "0x27",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx x21, x20, #29, #1",
"ldrb w22, [x28, #708]",
"mov w23, w4",
"uxtb x23, w23",
"uxtb w23, w4",
"and w20, w20, #0xdfffffff",
"str w20, [x28, #728]",
"and x20, x23, #0xf",
@@ -119,16 +111,13 @@
"cbnz x20, #+0x10",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"b #+0x38",
"b #+0x2c",
"add x20, x23, #0x6 (6)",
"mov w22, w4",
"mov w0, w22",
"bfxil w0, w20, #0, #8",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"bfxil w4, w20, #0, #8",
"bfxil x4, x4, #0, #32",
"ldr w20, [x28, #728]",
"ubfx x22, x20, #29, #1",
"orr w22, w21, w22",
"orr x22, x21, x22",
"bfi w20, w22, #29, #1",
"mov w22, #0x1",
"strb w22, [x28, #708]",
@@ -140,20 +129,15 @@
"ldr w20, [x28, #728]",
"and w20, w20, #0xdfffffff",
"str w20, [x28, #728]",
"b #+0x30",
"mov w20, w4",
"uxtb x20, w20",
"b #+0x20",
"uxtb w20, w4",
"add x20, x20, #0x60 (96)",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #8",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"bfxil w4, w20, #0, #8",
"bfxil x4, x4, #0, #32",
"ldr w20, [x28, #728]",
"orr w20, w20, #0x20000000",
"str w20, [x28, #728]",
"mov w20, w4",
"uxtb x20, w20",
"uxtb w20, w4",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
@@ -171,15 +155,14 @@
]
},
"das": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 54,
"Optimal": "No",
"Comment": "0x2f",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx x21, x20, #29, #1",
"ldrb w22, [x28, #708]",
"mov w23, w4",
"uxtb x23, w23",
"uxtb w23, w4",
"and w20, w20, #0xdfffffff",
"str w20, [x28, #728]",
"and x20, x23, #0xf",
@@ -189,16 +172,13 @@
"cbnz x20, #+0x10",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"b #+0x38",
"b #+0x2c",
"sub x20, x23, #0x6 (6)",
"mov w22, w4",
"mov w0, w22",
"bfxil w0, w20, #0, #8",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"bfxil w4, w20, #0, #8",
"bfxil x4, x4, #0, #32",
"ldr w20, [x28, #728]",
"ubfx x22, x20, #29, #1",
"orr w22, w21, w22",
"orr x22, x21, x22",
"bfi w20, w22, #29, #1",
"mov w22, #0x1",
"strb w22, [x28, #708]",
@@ -210,20 +190,15 @@
"ldr w20, [x28, #728]",
"and w20, w20, #0xdfffffff",
"str w20, [x28, #728]",
"b #+0x30",
"mov w20, w4",
"uxtb x20, w20",
"b #+0x20",
"uxtb w20, w4",
"sub x20, x20, #0x60 (96)",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #8",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"bfxil w4, w20, #0, #8",
"bfxil x4, x4, #0, #32",
"ldr w20, [x28, #728]",
"orr w20, w20, #0x20000000",
"str w20, [x28, #728]",
"mov w20, w4",
"uxtb x20, w20",
"uxtb w20, w4",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
@@ -241,41 +216,33 @@
]
},
"aaa": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 28,
"Optimal": "No",
"Comment": "0x37",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"mov w21, w4",
"uxtb x21, w21",
"mov w22, w4",
"uxth x22, w22",
"uxtb w21, w4",
"uxth w22, w4",
"and x21, x21, #0xf",
"cmp x21, #0x9 (9)",
"cset x21, hi",
"orr x20, x20, x21",
"cbnz x20, #+0x38",
"cbnz x20, #+0x2c",
"mov w20, #0xff0f",
"and x20, x22, x20",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"mov w20, #0x0",
"ldr w21, [x28, #728]",
"and w21, w21, #0xdfffffff",
"strb w20, [x28, #708]",
"str w21, [x28, #728]",
"b #+0x38",
"b #+0x2c",
"add x20, x22, #0x106 (262)",
"mov w21, #0xff0f",
"and x20, x20, x21",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"mov w20, #0x1",
"ldr w21, [x28, #728]",
"orr w21, w21, #0x20000000",
@@ -284,42 +251,34 @@
]
},
"aas": {
"ExpectedInstructionCount": 37,
"ExpectedInstructionCount": 29,
"Optimal": "No",
"Comment": "0x3f",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"mov w21, w4",
"uxtb x21, w21",
"mov w22, w4",
"uxth x22, w22",
"uxtb w21, w4",
"uxth w22, w4",
"and x21, x21, #0xf",
"cmp x21, #0x9 (9)",
"cset x21, hi",
"orr x20, x20, x21",
"cbnz x20, #+0x38",
"cbnz x20, #+0x2c",
"mov w20, #0xff0f",
"and x20, x22, x20",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"mov w20, #0x0",
"ldr w21, [x28, #728]",
"and w21, w21, #0xdfffffff",
"strb w20, [x28, #708]",
"str w21, [x28, #728]",
"b #+0x3c",
"b #+0x30",
"sub x20, x22, #0x6 (6)",
"sub x20, x20, #0x100 (256)",
"mov w21, #0xff0f",
"and x20, x20, x21",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"mov w20, #0x1",
"ldr w21, [x28, #728]",
"orr w21, w21, #0x20000000",
@@ -328,20 +287,18 @@
]
},
"inc ax": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "0x40",
"ExpectedArm64ASM": [
"mov w20, w4",
"uxth x20, w20",
"uxth w20, w4",
"add w21, w20, #0x1 (1)",
"mov w22, w4",
"bfxil w22, w21, #0, #16",
"bfxil x4, x22, #0, #32",
"uxth x21, w21",
"bfxil w4, w21, #0, #16",
"bfxil x4, x4, #0, #32",
"uxth w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"ubfx x22, x22, #4, #1",
"ubfx w22, w22, #4, #1",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -356,7 +313,7 @@
"eor w23, w20, #0x1",
"eor w20, w21, w20",
"bic w20, w20, w23",
"ubfx x20, x20, #15, #1",
"ubfx w20, w20, #15, #1",
"orr x20, x22, x20, lsl #28",
"str w20, [x28, #728]"
]
@@ -367,42 +324,40 @@
"Comment": "0x40",
"ExpectedArm64ASM": [
"mov w20, w4",
"add w21, w20, #0x1 (1)",
"bfxil x4, x21, #0, #32",
"add w4, w20, #0x1 (1)",
"bfxil x4, x4, #0, #32",
"eor w21, w20, #0x1",
"eor w21, w21, w4",
"ubfx w21, w21, #4, #1",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
"ldr w21, [x28, #728]",
"ubfx x21, x21, #29, #1",
"tst w4, w4",
"mrs x22, nzcv",
"orr x21, x22, x21, lsl #29",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"ubfx x22, x22, #4, #1",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
"ldr w22, [x28, #728]",
"ubfx x22, x22, #29, #1",
"tst w21, w21",
"mrs x23, nzcv",
"orr w22, w23, w22, lsl #29",
"eor w23, w20, #0x1",
"eor w20, w21, w20",
"bic w20, w20, w23",
"ubfx x20, x20, #31, #1",
"orr w20, w22, w20, lsl #28",
"eor w20, w4, w20",
"bic w20, w20, w22",
"lsr w20, w20, #31",
"orr x20, x21, x20, lsl #28",
"str w20, [x28, #728]"
]
},
"dec ax": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 25,
"Optimal": "No",
"Comment": "0x48",
"ExpectedArm64ASM": [
"mov w20, w4",
"uxth x20, w20",
"uxth w20, w4",
"sub w21, w20, #0x1 (1)",
"mov w22, w4",
"bfxil w22, w21, #0, #16",
"bfxil x4, x22, #0, #32",
"uxth x21, w21",
"bfxil w4, w21, #0, #16",
"bfxil x4, x4, #0, #32",
"uxth w21, w21",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"ubfx x22, x22, #4, #1",
"ubfx w22, w22, #4, #1",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
@@ -417,7 +372,7 @@
"eor w23, w20, #0x1",
"eor w20, w21, w20",
"and w20, w23, w20",
"ubfx x20, x20, #15, #1",
"ubfx w20, w20, #15, #1",
"orr x20, x22, x20, lsl #28",
"str w20, [x28, #728]"
]
@@ -428,159 +383,136 @@
"Comment": "0x48",
"ExpectedArm64ASM": [
"mov w20, w4",
"sub w21, w20, #0x1 (1)",
"bfxil x4, x21, #0, #32",
"sub w4, w20, #0x1 (1)",
"bfxil x4, x4, #0, #32",
"eor w21, w20, #0x1",
"eor w21, w21, w4",
"ubfx w21, w21, #4, #1",
"strb w21, [x28, #708]",
"eor x21, x4, #0x1",
"strb w21, [x28, #706]",
"ldr w21, [x28, #728]",
"ubfx x21, x21, #29, #1",
"tst w4, w4",
"mrs x22, nzcv",
"orr x21, x22, x21, lsl #29",
"eor w22, w20, #0x1",
"eor w22, w22, w21",
"ubfx x22, x22, #4, #1",
"strb w22, [x28, #708]",
"eor x22, x21, #0x1",
"strb w22, [x28, #706]",
"ldr w22, [x28, #728]",
"ubfx x22, x22, #29, #1",
"tst w21, w21",
"mrs x23, nzcv",
"orr w22, w23, w22, lsl #29",
"eor w23, w20, #0x1",
"eor w20, w21, w20",
"and w20, w23, w20",
"ubfx x20, x20, #31, #1",
"orr w20, w22, w20, lsl #28",
"eor w20, w4, w20",
"and w20, w22, w20",
"lsr w20, w20, #31",
"orr x20, x21, x20, lsl #28",
"str w20, [x28, #728]"
]
},
"pusha": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x60",
"ExpectedArm64ASM": [
"mov w20, w8",
"mov w21, w4",
"stur w21, [x20, #-4]",
"sub w21, w20, #0x4 (4)",
"mov w22, w5",
"str w22, [x21, #-4]!",
"mov w22, w6",
"str w22, [x21, #-4]!",
"mov w22, w7",
"str w22, [x21, #-4]!",
"stur w20, [x21, #-4]",
"sub w20, w21, #0x4 (4)",
"mov w21, w9",
"str w21, [x20, #-4]!",
"mov w21, w10",
"str w21, [x20, #-4]!",
"mov w21, w11",
"str w21, [x20, #-4]!",
"bfxil x8, x20, #0, #32"
"str w4, [x20, #-4]!",
"str w5, [x20, #-4]!",
"str w6, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w8, [x20, #-4]!",
"str w9, [x20, #-4]!",
"str w10, [x20, #-4]!",
"mov w8, w20",
"str w11, [x8, #-4]!",
"bfxil x8, x8, #0, #32"
]
},
"pushad": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 11,
"Optimal": "No",
"Comment": "0x60",
"ExpectedArm64ASM": [
"mov w20, w8",
"mov w21, w4",
"stur w21, [x20, #-4]",
"sub w21, w20, #0x4 (4)",
"mov w22, w5",
"str w22, [x21, #-4]!",
"mov w22, w6",
"str w22, [x21, #-4]!",
"mov w22, w7",
"str w22, [x21, #-4]!",
"stur w20, [x21, #-4]",
"sub w20, w21, #0x4 (4)",
"mov w21, w9",
"str w21, [x20, #-4]!",
"mov w21, w10",
"str w21, [x20, #-4]!",
"mov w21, w11",
"str w21, [x20, #-4]!",
"bfxil x8, x20, #0, #32"
"str w4, [x20, #-4]!",
"str w5, [x20, #-4]!",
"str w6, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w8, [x20, #-4]!",
"str w9, [x20, #-4]!",
"str w10, [x20, #-4]!",
"mov w8, w20",
"str w11, [x8, #-4]!",
"bfxil x8, x8, #0, #32"
]
},
"popa": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "0x61",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"bfxil x11, x21, #0, #32",
"ldr w11, [x8]",
"bfxil x11, x11, #0, #32",
"add x20, x8, #0x4 (4)",
"ldr w10, [x8, #4]",
"bfxil x10, x10, #0, #32",
"add x21, x20, #0x4 (4)",
"ldr w20, [x20, #4]",
"bfxil x10, x20, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x9, x21, #0, #32",
"add x21, x20, #0x8 (8)",
"ldr w20, [x20, #8]",
"bfxil x7, x20, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x6, x21, #0, #32",
"ldr w9, [x20, #4]",
"bfxil x9, x9, #0, #32",
"add x20, x21, #0x8 (8)",
"ldr w7, [x21, #8]",
"bfxil x7, x7, #0, #32",
"add x21, x20, #0x4 (4)",
"ldr w20, [x20, #4]",
"bfxil x5, x20, #0, #32",
"ldr w6, [x20, #4]",
"bfxil x6, x6, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x4, x21, #0, #32",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32"
"ldr w5, [x21, #4]",
"bfxil x5, x5, #0, #32",
"add x21, x20, #0x4 (4)",
"ldr w4, [x20, #4]",
"bfxil x4, x4, #0, #32",
"add x8, x21, #0x4 (4)",
"bfxil x8, x8, #0, #32"
]
},
"popad": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 22,
"Optimal": "No",
"Comment": "0x61",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"bfxil x11, x21, #0, #32",
"ldr w11, [x8]",
"bfxil x11, x11, #0, #32",
"add x20, x8, #0x4 (4)",
"ldr w10, [x8, #4]",
"bfxil x10, x10, #0, #32",
"add x21, x20, #0x4 (4)",
"ldr w20, [x20, #4]",
"bfxil x10, x20, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x9, x21, #0, #32",
"add x21, x20, #0x8 (8)",
"ldr w20, [x20, #8]",
"bfxil x7, x20, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x6, x21, #0, #32",
"ldr w9, [x20, #4]",
"bfxil x9, x9, #0, #32",
"add x20, x21, #0x8 (8)",
"ldr w7, [x21, #8]",
"bfxil x7, x7, #0, #32",
"add x21, x20, #0x4 (4)",
"ldr w20, [x20, #4]",
"bfxil x5, x20, #0, #32",
"ldr w6, [x20, #4]",
"bfxil x6, x6, #0, #32",
"add x20, x21, #0x4 (4)",
"ldr w21, [x21, #4]",
"bfxil x4, x21, #0, #32",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32"
"ldr w5, [x21, #4]",
"bfxil x5, x5, #0, #32",
"add x21, x20, #0x4 (4)",
"ldr w4, [x20, #4]",
"bfxil x4, x4, #0, #32",
"add x8, x21, #0x4 (4)",
"bfxil x8, x8, #0, #32"
]
},
"aam": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": "0xd4",
"ExpectedArm64ASM": [
"mov w20, w4",
"uxtb x20, w20",
"uxtb w20, w4",
"mov w21, #0xa",
"udiv x22, x20, x21",
"udiv x2, x20, x21",
"msub x20, x2, x21, x20",
"lsl x21, x22, #8",
"add x20, x21, x20",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"mov w20, w4",
"uxtb x20, w20",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"uxtb w20, w4",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
@@ -598,26 +530,20 @@
]
},
"aad": {
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": "0xd5",
"ExpectedArm64ASM": [
"mov w20, w4",
"uxtb x20, w20",
"mov w21, w4",
"uxth x21, w21",
"uxtb w20, w4",
"uxth w21, w4",
"lsr w21, w21, #8",
"mov w22, #0xa",
"mul x21, x21, x22",
"add x20, x20, x21",
"and x20, x20, #0xff",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"mov w20, w4",
"uxtb x20, w20",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"uxtb w20, w4",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
@@ -635,28 +561,23 @@
]
},
"db 0xd4, 0x40": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 24,
"Optimal": "No",
"Comment": [
"aam with a different immediate byte base",
"0xd4"
],
"ExpectedArm64ASM": [
"mov w20, w4",
"uxtb x20, w20",
"uxtb w20, w4",
"mov w21, #0x40",
"udiv x22, x20, x21",
"udiv x2, x20, x21",
"msub x20, x2, x21, x20",
"lsl x21, x22, #8",
"add x20, x21, x20",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"mov w20, w4",
"uxtb x20, w20",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"uxtb w20, w4",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
@@ -674,28 +595,22 @@
]
},
"db 0xd5, 0x40": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 23,
"Optimal": "No",
"Comment": [
"aad with a different immediate byte base",
"0xd5"
],
"ExpectedArm64ASM": [
"mov w20, w4",
"uxtb x20, w20",
"mov w21, w4",
"uxth x21, w21",
"uxtb w20, w4",
"uxth w21, w4",
"lsr w21, w21, #8",
"lsl x21, x21, #6",
"add x20, x20, x21",
"and x20, x20, #0xff",
"mov w21, w4",
"mov w0, w21",
"bfxil w0, w20, #0, #16",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"mov w20, w4",
"uxtb x20, w20",
"bfxil w4, w20, #0, #16",
"bfxil x4, x4, #0, #32",
"uxtb w20, w4",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
@@ -713,23 +628,18 @@
]
},
"salc": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "0xd6",
"ExpectedArm64ASM": [
"mov w20, w4",
"uxtb x20, w20",
"uxtb w20, w4",
"ldr w21, [x28, #728]",
"ubfx x22, x21, #29, #1",
"ubfx w22, w21, #29, #1",
"add w20, w20, w22",
"mov w22, w4",
"uxtb x22, w22",
"uxtb w22, w4",
"sub w20, w22, w20",
"mov w22, w4",
"mov w0, w22",
"bfxil w0, w20, #0, #8",
"mov w20, w0",
"bfxil x4, x20, #0, #32",
"bfxil w4, w20, #0, #8",
"bfxil x4, x4, #0, #32",
"str w21, [x28, #728]"
]
}
unittests/InstructionCountCI/Secondary.json
+265 -264
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/SecondaryGroup.json
+65 -63
View File
@@ -26,8 +26,8 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"uxth x20, w4",
"ubfx x20, x20, #0, #1",
"uxth w20, w4",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -40,8 +40,8 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"ubfx x20, x20, #0, #1",
"lsr w20, w4, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -67,9 +67,9 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"lsr w20, w20, #15",
"ubfx x20, x20, #0, #1",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -82,9 +82,9 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /4",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"lsr w20, w20, #31",
"ubfx x20, x20, #0, #1",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -111,10 +111,10 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"orr x21, x20, #0x1",
"bfxil x4, x21, #0, #16",
"ubfx x20, x20, #0, #1",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -127,10 +127,10 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"orr x21, x20, #0x1",
"ubfx x4, x21, #0, #32",
"ubfx x20, x20, #0, #1",
"lsr w4, w21, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -158,11 +158,11 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"lsr w21, w20, #15",
"orr x20, x20, #0x8000",
"bfxil x4, x20, #0, #16",
"ubfx x20, x21, #0, #1",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -175,11 +175,11 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /5",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"lsr w21, w20, #31",
"orr x20, x20, #0x80000000",
"ubfx x4, x20, #0, #32",
"ubfx x20, x21, #0, #1",
"lsr w4, w20, #0",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -207,10 +207,10 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"uxth x20, w4",
"and w21, w20, #0xfffffffe",
"uxth w20, w4",
"and x21, x20, #0xfffffffffffffffe",
"bfxil x4, x21, #0, #16",
"ubfx x20, x20, #0, #1",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -219,13 +219,14 @@
]
},
"btr eax, 0": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"and w4, w20, #0xfffffffe",
"ubfx x20, x20, #0, #1",
"lsr w20, w4, #0",
"and x21, x20, #0xfffffffffffffffe",
"lsr w4, w21, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -253,11 +254,11 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"lsr w21, w20, #15",
"and w20, w20, #0xffff7fff",
"and x20, x20, #0xffffffffffff7fff",
"bfxil x4, x20, #0, #16",
"ubfx x20, x21, #0, #1",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -266,14 +267,15 @@
]
},
"btr eax, 31": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /6",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"lsr w21, w20, #31",
"and w4, w20, #0x7fffffff",
"ubfx x20, x21, #0, #1",
"and x20, x20, #0xffffffff7fffffff",
"lsr w4, w20, #0",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -301,10 +303,10 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"eor x21, x20, #0x1",
"bfxil x4, x21, #0, #16",
"ubfx x20, x20, #0, #1",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -317,10 +319,10 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"eor x21, x20, #0x1",
"ubfx x4, x21, #0, #32",
"ubfx x20, x20, #0, #1",
"lsr w4, w21, #0",
"ubfx w20, w20, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -348,11 +350,11 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"lsr w21, w20, #15",
"eor x20, x20, #0x8000",
"bfxil x4, x20, #0, #16",
"ubfx x20, x21, #0, #1",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -365,11 +367,11 @@
"Optimal": "No",
"Comment": "GROUP8 0x0F 0xBA /7",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"lsr w21, w20, #31",
"eor x20, x20, #0x80000000",
"ubfx x4, x20, #0, #32",
"ubfx x20, x21, #0, #1",
"lsr w4, w20, #0",
"ubfx w20, w21, #0, #1",
"ldr w21, [x28, #728]",
"mov w0, w21",
"bfi w0, w20, #29, #1",
@@ -398,12 +400,12 @@
"Comment": "GROUP9 0x0F 0xC7 /1",
"ExpectedArm64ASM": [
"add x20, x9, #0x0 (0)",
"ubfx x21, x4, #0, #32",
"ubfx x22, x6, #0, #32",
"lsr w21, w4, #0",
"lsr w22, w6, #0",
"mov w23, w22",
"mov w22, w21",
"ubfx x21, x7, #0, #32",
"ubfx x24, x5, #0, #32",
"lsr w21, w7, #0",
"lsr w24, w5, #0",
"mov w25, w24",
"mov w24, w21",
"mov w2, w22",
@@ -478,7 +480,7 @@
"cset x21, ne",
"mov x22, x20",
"mov x20, x21",
"ubfx x4, x22, #0, #32",
"lsr w4, w22, #0",
"mov w21, #0x0",
"strb w21, [x28, #706]",
"strb w21, [x28, #708]",
@@ -528,7 +530,7 @@
"cset x21, ne",
"mov x22, x20",
"mov x20, x21",
"ubfx x4, x22, #0, #32",
"lsr w4, w22, #0",
"mov w21, #0x0",
"strb w21, [x28, #706]",
"strb w21, [x28, #708]",
@@ -1153,12 +1155,12 @@
"ldp x19, x29, [x28, #120]",
"strh w20, [x28, #1008]",
"ldrh w20, [x4, #2]",
"ubfx x21, x20, #11, #3",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #747]",
"ubfx x21, x20, #8, #1",
"ubfx x22, x20, #9, #1",
"ubfx x23, x20, #10, #1",
"ubfx x20, x20, #14, #1",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w20, w20, #14, #1",
"strb w21, [x28, #744]",
"strb w22, [x28, #745]",
"strb w23, [x28, #746]",
@@ -1198,7 +1200,7 @@
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"ldr w20, [x4, #24]",
"ubfx x20, x20, #13, #3",
"ubfx w20, w20, #13, #3",
"and x0, x20, #0x3",
"cmp x0, #0x2 (2)",
"mov w2, #0x1",
@@ -1238,7 +1240,7 @@
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"ubfx x20, x20, #13, #3",
"ubfx w20, w20, #13, #3",
"and x0, x20, #0x3",
"cmp x0, #0x2 (2)",
"mov w2, #0x1",
@@ -1261,7 +1263,7 @@
"Optimal": "Yes",
"Comment": "GROUP15 0x0F 0xAE /2",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"str x20, [x28, #176]"
]
},
@@ -1302,7 +1304,7 @@
"Optimal": "Yes",
"Comment": "GROUP15 0x0F 0xAE /3",
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"str x20, [x28, #168]"
]
},
@@ -1467,12 +1469,12 @@
"ldp x19, x29, [x28, #120]",
"strh w22, [x28, #1008]",
"ldrh w22, [x20, #2]",
"ubfx x23, x22, #11, #3",
"ubfx w23, w22, #11, #3",
"strb w23, [x28, #747]",
"ubfx x23, x22, #8, #1",
"ubfx x24, x22, #9, #1",
"ubfx x25, x22, #10, #1",
"ubfx x22, x22, #14, #1",
"ubfx w23, w22, #8, #1",
"ubfx w24, w22, #9, #1",
"ubfx w25, w22, #10, #1",
"ubfx w22, w22, #14, #1",
"strb w23, [x28, #744]",
"strb w24, [x28, #745]",
"strb w25, [x28, #746]",
@@ -1594,7 +1596,7 @@
"cbnz x21, #+0x8",
"b #+0x4c",
"ldr w20, [x20, #24]",
"ubfx x20, x20, #13, #3",
"ubfx w20, w20, #13, #3",
"and x0, x20, #0x3",
"cmp x0, #0x2 (2)",
"mov w2, #0x1",
unittests/InstructionCountCI/Secondary_32Bit.json
+20 -24
View File
@@ -9,54 +9,50 @@
},
"Instructions": {
"push fs": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldrh w21, [x28, #146]",
"str w21, [x20, #-4]!",
"bfxil x8, x20, #0, #32"
"ldrh w20, [x28, #146]",
"str w20, [x8, #-4]!",
"bfxil x8, x8, #0, #32"
]
},
"pop fs": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xa1",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"strh w21, [x28, #146]",
"ubfx x20, x21, #3, #13",
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"bfxil x8, x8, #0, #32",
"strh w20, [x28, #146]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #176]"
]
},
"push gs": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldrh w21, [x28, #144]",
"str w21, [x20, #-4]!",
"bfxil x8, x20, #0, #32"
"ldrh w20, [x28, #144]",
"str w20, [x8, #-4]!",
"bfxil x8, x8, #0, #32"
]
},
"pop gs": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": "0x0f 0xa9",
"ExpectedArm64ASM": [
"mov w20, w8",
"ldr w21, [x20]",
"add x20, x20, #0x4 (4)",
"bfxil x8, x20, #0, #32",
"strh w21, [x28, #144]",
"ubfx x20, x21, #3, #13",
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"bfxil x8, x8, #0, #32",
"strh w20, [x28, #144]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #168]"
unittests/InstructionCountCI/Secondary_OpSize.json
+2 -2
View File
@@ -167,7 +167,7 @@
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
"bic w21, w21, w22",
"bic x21, x21, x22",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
@@ -195,7 +195,7 @@
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
"bic w21, w21, w22",
"bic x21, x21, x22",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
unittests/InstructionCountCI/Secondary_REP.json
+10 -10
View File
@@ -436,7 +436,7 @@
"Optimal": "No",
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"uxth x20, w7",
"uxth w20, w7",
"fmov s0, w20",
"cnt v0.8b, v0.8b",
"addp v0.8b, v0.8b, v0.8b",
@@ -456,7 +456,7 @@
"Optimal": "No",
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"lsr w20, w7, #0",
"fmov s0, w20",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
@@ -493,7 +493,7 @@
"Optimal": "No",
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"uxth x20, w7",
"uxth w20, w7",
"rbit w20, w20",
"orr w20, w20, #0x8000",
"clz w20, w20",
@@ -501,7 +501,7 @@
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"ubfx x20, x20, #0, #1",
"ubfx w20, w20, #0, #1",
"orr x20, x21, x20, lsl #30",
"str w20, [x28, #728]"
]
@@ -511,13 +511,13 @@
"Optimal": "No",
"Comment": "0xf3 0x0f 0xbc",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"lsr w20, w7, #0",
"rbit w4, w20",
"clz w4, w4",
"cmp x4, #0x0 (0)",
"cset x20, eq",
"lsl x20, x20, #29",
"ubfx x21, x4, #0, #1",
"ubfx w21, w4, #0, #1",
"orr x20, x20, x21, lsl #30",
"str w20, [x28, #728]"
]
@@ -542,7 +542,7 @@
"Optimal": "No",
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"uxth x20, w7",
"uxth w20, w7",
"lsl w21, w20, #16",
"orr w21, w21, #0x8000",
"clz w21, w21",
@@ -550,7 +550,7 @@
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"ubfx x20, x20, #15, #1",
"ubfx w20, w20, #15, #1",
"orr x20, x21, x20, lsl #30",
"str w20, [x28, #728]"
]
@@ -560,12 +560,12 @@
"Optimal": "No",
"Comment": "0xf3 0x0f 0xbd",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"lsr w20, w7, #0",
"clz w4, w20",
"cmp x20, #0x0 (0)",
"cset x21, eq",
"lsl x21, x21, #29",
"ubfx x20, x20, #31, #1",
"lsr w20, w20, #31",
"orr x20, x21, x20, lsl #30",
"str w20, [x28, #728]"
]
unittests/InstructionCountCI/VEX_map1.json
+17 -17
View File
@@ -546,45 +546,45 @@
"mov z4.d, p7/m, z16.d",
"mov w20, #0x0",
"mov w21, v4.s[0]",
"ubfx x21, x21, #31, #1",
"lsr w21, w21, #31",
"orr x20, x20, x21",
"mov w21, v4.s[1]",
"ubfx x21, x21, #31, #1",
"lsr w21, w21, #31",
"lsl w21, w21, #1",
"orr x20, x20, x21",
"mov w21, v4.s[2]",
"ubfx x21, x21, #31, #1",
"lsr w21, w21, #31",
"lsl w21, w21, #2",
"orr x20, x20, x21",
"mov w21, v4.s[3]",
"ubfx x21, x21, #31, #1",
"lsr w21, w21, #31",
"lsl w21, w21, #3",
"orr x20, x20, x21",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z4.d",
"mov w21, v4.s[0]",
"ubfx x21, x21, #31, #1",
"lsr w21, w21, #31",
"lsl w21, w21, #4",
"orr x20, x20, x21",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z4.d",
"mov w21, v4.s[1]",
"ubfx x21, x21, #31, #1",
"lsr w21, w21, #31",
"lsl w21, w21, #5",
"orr x20, x20, x21",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z4.d",
"mov w21, v4.s[2]",
"ubfx x21, x21, #31, #1",
"lsr w21, w21, #31",
"lsl w21, w21, #6",
"orr x20, x20, x21",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z4.d",
"mov w21, v4.s[3]",
"ubfx x21, x21, #31, #1",
"lsr w21, w21, #31",
"lsl w21, w21, #7",
"orr x20, x20, x21",
"ubfx x4, x20, #0, #32"
"lsr w4, w20, #0"
]
},
"vmovmskpd rax, xmm0": {
@@ -629,7 +629,7 @@
"lsr x21, x21, #63",
"lsl x21, x21, #3",
"orr x20, x20, x21",
"ubfx x4, x20, #0, #32"
"lsr w4, w20, #0"
]
},
"vsqrtps xmm0, xmm1": {
@@ -3023,7 +3023,7 @@
"Map 1 0b01 0xC4 128-bit"
],
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"mov z4.d, p7/m, z17.d",
"mov v4.h[0], w20",
"mov v4.16b, v4.16b",
@@ -3037,7 +3037,7 @@
"Map 1 0b01 0xC4 128-bit"
],
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"mov z4.d, p7/m, z17.d",
"mov v4.h[1], w20",
"mov v4.16b, v4.16b",
@@ -3051,7 +3051,7 @@
"Map 1 0b01 0xC4 128-bit"
],
"ExpectedArm64ASM": [
"uxth x20, w4",
"uxth w20, w4",
"mov z4.d, p7/m, z17.d",
"mov v4.h[7], w20",
"mov v4.16b, v4.16b",
@@ -3805,7 +3805,7 @@
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
"bic w21, w21, w22",
"bic x21, x21, x22",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
@@ -3837,7 +3837,7 @@
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
"bic w21, w21, w22",
"bic x21, x21, x22",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
@@ -3869,7 +3869,7 @@
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
"bic w21, w21, w22",
"bic x21, x21, x22",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
@@ -3901,7 +3901,7 @@
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w22, #0x90000000",
"bic w21, w21, w22",
"bic x21, x21, x22",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
unittests/InstructionCountCI/VEX_map2.json
+20 -20
View File
@@ -3733,8 +3733,8 @@
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"ubfx x21, x5, #0, #32",
"lsr w20, w7, #0",
"lsr w21, w5, #0",
"bic w4, w21, w20",
"mov w20, #0x0",
"strb w20, [x28, #708]",
@@ -3769,8 +3769,8 @@
"Map 2 0b00 0xf5 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"ubfx x21, x5, #0, #32",
"lsr w20, w7, #0",
"lsr w21, w5, #0",
"and x21, x21, #0xff",
"mov w22, #0xffff",
"movk w22, #0xffff, lsl #16",
@@ -3832,8 +3832,8 @@
"Map 2 0b10 0xf5 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"ubfx x21, x5, #0, #32",
"lsr w20, w7, #0",
"lsr w21, w5, #0",
"cbz w21, #+0x40",
"mov w0, w21",
"mov w3, wzr",
@@ -3888,8 +3888,8 @@
"Map 2 0b11 0xf5 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"ubfx x21, x5, #0, #32",
"lsr w20, w7, #0",
"lsr w21, w5, #0",
"cbz w21, #+0x58",
"mov w3, wzr",
"stp x4, x5, [x28, #8]",
@@ -3954,8 +3954,8 @@
"Map 2 0b11 0xf6 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x5, #0, #32",
"ubfx x21, x6, #0, #32",
"lsr w20, w5, #0",
"lsr w21, w6, #0",
"mul w7, w20, w21",
"ubfx x0, x20, #0, #32",
"ubfx x1, x21, #0, #32",
@@ -3981,15 +3981,15 @@
"Map 2 0b00 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"ubfx x21, x5, #0, #32",
"lsr w20, w7, #0",
"lsr w21, w5, #0",
"mov w22, #0x1f",
"uxtb x23, w21",
"uxtb w23, w21",
"lsr w20, w20, w23",
"mov w24, #0x0",
"cmp w23, #0x1f (31)",
"csel w20, w20, w24, ls",
"ubfx x21, x21, #8, #8",
"ubfx w21, w21, #8, #8",
"cmp w21, #0x1f (31)",
"csel w21, w21, w22, ls",
"mov w22, #0x1",
@@ -4037,8 +4037,8 @@
"Map 2 0b01 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"ubfx x21, x5, #0, #32",
"lsr w20, w7, #0",
"lsr w21, w5, #0",
"lsl w4, w20, w21"
]
},
@@ -4059,8 +4059,8 @@
"Map 2 0b10 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"ubfx x21, x5, #0, #32",
"lsr w20, w7, #0",
"lsr w21, w5, #0",
"asr w4, w20, w21"
]
},
@@ -4081,8 +4081,8 @@
"Map 2 0b11 0xf7 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"ubfx x21, x5, #0, #32",
"lsr w20, w7, #0",
"lsr w21, w5, #0",
"lsr w4, w20, w21"
]
},
unittests/InstructionCountCI/VEX_map3.json
+7 -7
View File
@@ -3241,7 +3241,7 @@
"Map 3 0b01 0x20 128-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"mov z4.d, p7/m, z17.d",
"mov v4.b[0], w20",
"mov v4.16b, v4.16b",
@@ -3256,7 +3256,7 @@
"Map 3 0b01 0x20 128-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"mov z4.d, p7/m, z17.d",
"mov v4.b[15], w20",
"mov v4.16b, v4.16b",
@@ -3314,7 +3314,7 @@
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"mov z4.d, p7/m, z17.d",
"mov v4.s[0], w20",
"mov v4.16b, v4.16b",
@@ -3329,7 +3329,7 @@
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x4, #0, #32",
"lsr w20, w4, #0",
"mov z4.d, p7/m, z17.d",
"mov v4.s[3], w20",
"mov v4.16b, v4.16b",
@@ -5103,7 +5103,7 @@
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"lsr w20, w7, #0",
"ror w4, w20, #0"
]
},
@@ -5114,7 +5114,7 @@
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"lsr w20, w7, #0",
"ror w4, w20, #31"
]
},
@@ -5125,7 +5125,7 @@
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"lsr w20, w7, #0",
"ror w4, w20, #0"
]
},
unittests/InstructionCountCI/VEX_map_group.json
+8 -8
View File
@@ -757,7 +757,7 @@
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"ubfx x20, x20, #13, #3",
"ubfx w20, w20, #13, #3",
"and x0, x20, #0x3",
"cmp x0, #0x2 (2)",
"mov w2, #0x1",
@@ -809,10 +809,10 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ubfx x21, x7, #0, #32",
"lsr w21, w7, #0",
"sub x22, x21, #0x1 (1)",
"and x22, x22, x21",
"ubfx x4, x22, #0, #32",
"lsr w4, w22, #0",
"mov w23, #0x0",
"tst w22, w22",
"mrs x22, nzcv",
@@ -853,14 +853,14 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ubfx x21, x7, #0, #32",
"lsr w21, w7, #0",
"sub x22, x21, #0x1 (1)",
"eor x22, x22, x21",
"ubfx x4, x22, #0, #32",
"lsr w4, w22, #0",
"mov w22, #0x0",
"mov w23, #0x50000000",
"ldr w24, [x28, #728]",
"bic w23, w24, w23",
"bic x23, x24, x23",
"strb w22, [x28, #706]",
"strb w22, [x28, #708]",
"cmp x21, #0x0 (0)",
@@ -884,7 +884,7 @@
"mov w21, #0x0",
"mov w22, #0x50000000",
"ldr w23, [x28, #728]",
"bic w22, w23, w22",
"bic x22, x23, x22",
"strb w21, [x28, #706]",
"strb w21, [x28, #708]",
"cmp x7, #0x0 (0)",
@@ -902,7 +902,7 @@
"Map group 17 0b011 32-bit"
],
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #32",
"lsr w20, w7, #0",
"neg w21, w20",
"and w4, w20, w21",
"mov w20, #0x0",
unittests/InstructionCountCI/x87.json
+168 -168
View File
File diff suppressed because it is too large. Load diff