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Merge pull request #2938 from lioncash/fcmp

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OpcodeDispatcher: Eliminate unnecessary moves in {AVX}VFCMPOp
This commit is contained in:
Ryan Houdek authored and GitHub committed 2023-08-19 19:27:24 -07:00
2 parents ac53913c37 343b00818d
commit 4c409ea47d
4 files changed
+113 -171
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FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+8 -2
View File
@@ -2398,9 +2398,12 @@ OrderedNode* OpDispatchBuilder::VFCMPOpImpl(OpcodeArgs, size_t ElementSize, bool
template<size_t ElementSize, bool Scalar>
void OpDispatchBuilder::VFCMPOp(OpcodeArgs) {
// No need for zero-extending in the scalar case, since
// all we need is an insert at the end of the operation.
const auto SrcSize = Scalar && Op->Src[0].IsGPR() ? 16U : GetSrcSize(Op);
const auto DstSize = GetDstSize(Op);
OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
OrderedNode *Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags, -1);
OrderedNode *Dest = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, DstSize, Op->Flags, -1);
const uint8_t CompType = Op->Src[1].Data.Literal.Value;
@@ -2420,6 +2423,9 @@ void OpDispatchBuilder::VFCMPOp<8, true>(OpcodeArgs);
template <size_t ElementSize, bool Scalar>
void OpDispatchBuilder::AVXVFCMPOp(OpcodeArgs) {
// No need for zero-extending in the scalar case, since
// all we need is an insert at the end of the operation.
const auto SrcSize = Scalar && Op->Src[1].IsGPR() ? 16U : GetSrcSize(Op);
const auto DstSize = GetDstSize(Op);
const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
@@ -2427,7 +2433,7 @@ void OpDispatchBuilder::AVXVFCMPOp(OpcodeArgs) {
const uint8_t CompType = Op->Src[2].Data.Literal.Value;
OrderedNode *Src1 = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], DstSize, Op->Flags, -1);
OrderedNode *Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags, -1);
OrderedNode *Src2 = LoadSource_WithOpSize(FPRClass, Op, Op->Src[1], SrcSize, Op->Flags, -1);
OrderedNode *Result = VFCMPOpImpl(Op, ElementSize, Scalar, Src1, Src2, CompType);
if (Is128Bit) {
unittests/InstructionCountCI/Secondary_REP.json
+27 -51
View File
@@ -574,36 +574,42 @@
]
},
"cmpss xmm0, xmm1, 0": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmeq s4, s16, s4",
"fcmeq s4, s16, s17",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 1": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmgt s4, s4, s16",
"fcmgt s4, s17, s16",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 2": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmge s4, s17, s16",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 3": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": [
@@ -611,92 +617,62 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmge s4, s4, s16",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 3": {
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmge s0, s16, s4",
"fcmgt s1, s4, s16",
"fcmge s0, s16, s17",
"fcmgt s1, s17, s16",
"orr v4.8b, v0.8b, v1.8b",
"mvn v4.8b, v4.8b",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 4": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmeq s4, s16, s4",
"fcmeq s4, s16, s17",
"mvn v4.8b, v4.8b",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 5": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmgt s4, s4, s16",
"fcmgt s4, s17, s16",
"mvn v4.16b, v4.16b",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 6": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmge s4, s4, s16",
"fcmge s4, s17, s16",
"mvn v4.16b, v4.16b",
"mov v16.s[0], v4.s[0]"
]
},
"cmpss xmm0, xmm1, 7": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v17.s[0]",
"mov v4.16b, v0.16b",
"fcmge s0, s16, s4",
"fcmgt s1, s4, s16",
"fcmge s0, s16, s17",
"fcmgt s1, s17, s16",
"orr v4.8b, v0.8b, v1.8b",
"mov v16.s[0], v4.s[0]"
]
unittests/InstructionCountCI/Secondary_REPNE.json
+62 -70
View File
@@ -405,103 +405,42 @@
]
},
"cmpsd xmm0, xmm1, 0": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmeq d4, d16, d4",
"fcmeq d4, d16, d17",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmgt d4, d4, d16",
"fcmgt d4, d17, d16",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 2": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 2,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmge d4, d4, d16",
"fcmge d4, d17, d16",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 3": {
"ExpectedInstructionCount": 6,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmge d0, d16, d4",
"fcmgt d1, d4, d16",
"orr v4.8b, v0.8b, v1.8b",
"mvn v4.8b, v4.8b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 4": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmeq d4, d16, d4",
"mvn v4.8b, v4.8b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 5": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmgt d4, d4, d16",
"mvn v4.16b, v4.16b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 6": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmge d4, d4, d16",
"mvn v4.16b, v4.16b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 7": {
"ExpectedInstructionCount": 5,
"Optimal": "No",
"Comment": [
@@ -509,9 +448,62 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"mov v4.8b, v17.8b",
"fcmge d0, d16, d4",
"fcmgt d1, d4, d16",
"fcmge d0, d16, d17",
"fcmgt d1, d17, d16",
"orr v4.8b, v0.8b, v1.8b",
"mvn v4.8b, v4.8b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 4": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq d4, d16, d17",
"mvn v4.8b, v4.8b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 5": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmgt d4, d17, d16",
"mvn v4.16b, v4.16b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 6": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmge d4, d17, d16",
"mvn v4.16b, v4.16b",
"mov v16.d[0], v4.d[0]"
]
},
"cmpsd xmm0, xmm1, 7": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"With AFP mode FEX can remove an insert after the operation.",
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmge d0, d16, d17",
"fcmgt d1, d17, d16",
"orr v4.8b, v0.8b, v1.8b",
"mov v16.d[0], v4.d[0]"
]
unittests/InstructionCountCI/VEX_map1.json
+16 -48
View File
@@ -3114,7 +3114,7 @@
]
},
"vcmpss xmm0, xmm1, xmm2, 0x00": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": [
"Map 1 0b10 0xC2 128-bit"
@@ -3122,9 +3122,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"movi v0.2d, #0x0",
"mov v0.s[0], v5.s[0]",
"mov v5.16b, v0.16b",
"fcmeq s5, s4, s5",
"mov v4.s[0], v5.s[0]",
"mov v4.16b, v4.16b",
@@ -3133,7 +3130,7 @@
]
},
"vcmpss xmm0, xmm1, xmm2, 0x01": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": [
"Map 1 0b10 0xC2 128-bit"
@@ -3141,9 +3138,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"movi v0.2d, #0x0",
"mov v0.s[0], v5.s[0]",
"mov v5.16b, v0.16b",
"fcmgt s5, s5, s4",
"mov v4.s[0], v5.s[0]",
"mov v4.16b, v4.16b",
@@ -3152,7 +3146,7 @@
]
},
"vcmpss xmm0, xmm1, xmm2, 0x02": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": [
"Map 1 0b10 0xC2 128-bit"
@@ -3160,9 +3154,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"movi v0.2d, #0x0",
"mov v0.s[0], v5.s[0]",
"mov v5.16b, v0.16b",
"fcmge s5, s5, s4",
"mov v4.s[0], v5.s[0]",
"mov v4.16b, v4.16b",
@@ -3171,7 +3162,7 @@
]
},
"vcmpss xmm0, xmm1, xmm2, 0x03": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": [
"Map 1 0b10 0xC2 128-bit"
@@ -3179,9 +3170,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"movi v0.2d, #0x0",
"mov v0.s[0], v5.s[0]",
"mov v5.16b, v0.16b",
"fcmge s0, s4, s5",
"fcmgt s1, s5, s4",
"orr v5.8b, v0.8b, v1.8b",
@@ -3193,7 +3181,7 @@
]
},
"vcmpss xmm0, xmm1, xmm2, 0x04": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": [
"Map 1 0b10 0xC2 128-bit"
@@ -3201,9 +3189,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"movi v0.2d, #0x0",
"mov v0.s[0], v5.s[0]",
"mov v5.16b, v0.16b",
"fcmeq s5, s4, s5",
"mvn v5.8b, v5.8b",
"mov v4.s[0], v5.s[0]",
@@ -3213,7 +3198,7 @@
]
},
"vcmpss xmm0, xmm1, xmm2, 0x05": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": [
"Map 1 0b10 0xC2 128-bit"
@@ -3221,9 +3206,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"movi v0.2d, #0x0",
"mov v0.s[0], v5.s[0]",
"mov v5.16b, v0.16b",
"fcmgt s5, s5, s4",
"mvn v5.16b, v5.16b",
"mov v4.s[0], v5.s[0]",
@@ -3233,7 +3215,7 @@
]
},
"vcmpss xmm0, xmm1, xmm2, 0x06": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": [
"Map 1 0b10 0xC2 128-bit"
@@ -3241,9 +3223,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"movi v0.2d, #0x0",
"mov v0.s[0], v5.s[0]",
"mov v5.16b, v0.16b",
"fcmge s5, s5, s4",
"mvn v5.16b, v5.16b",
"mov v4.s[0], v5.s[0]",
@@ -3253,7 +3232,7 @@
]
},
"vcmpss xmm0, xmm1, xmm2, 0x07": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": [
"Map 1 0b10 0xC2 128-bit"
@@ -3261,9 +3240,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"movi v0.2d, #0x0",
"mov v0.s[0], v5.s[0]",
"mov v5.16b, v0.16b",
"fcmge s0, s4, s5",
"fcmgt s1, s5, s4",
"orr v5.8b, v0.8b, v1.8b",
@@ -3274,7 +3250,7 @@
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x00": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": [
"Map 1 0b11 0xC2 128-bit"
@@ -3282,7 +3258,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"mov v5.8b, v5.8b",
"fcmeq d5, d4, d5",
"mov v4.d[0], v5.d[0]",
"mov v4.16b, v4.16b",
@@ -3291,7 +3266,7 @@
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x01": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": [
"Map 1 0b11 0xC2 128-bit"
@@ -3299,7 +3274,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"mov v5.8b, v5.8b",
"fcmgt d5, d5, d4",
"mov v4.d[0], v5.d[0]",
"mov v4.16b, v4.16b",
@@ -3308,7 +3282,7 @@
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x02": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": [
"Map 1 0b11 0xC2 128-bit"
@@ -3316,7 +3290,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"mov v5.8b, v5.8b",
"fcmge d5, d5, d4",
"mov v4.d[0], v5.d[0]",
"mov v4.16b, v4.16b",
@@ -3325,7 +3298,7 @@
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x03": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": [
"Map 1 0b11 0xC2 128-bit"
@@ -3333,7 +3306,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"mov v5.8b, v5.8b",
"fcmge d0, d4, d5",
"fcmgt d1, d5, d4",
"orr v5.8b, v0.8b, v1.8b",
@@ -3345,7 +3317,7 @@
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x04": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": [
"Map 1 0b11 0xC2 128-bit"
@@ -3353,7 +3325,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"mov v5.8b, v5.8b",
"fcmeq d5, d4, d5",
"mvn v5.8b, v5.8b",
"mov v4.d[0], v5.d[0]",
@@ -3363,7 +3334,7 @@
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x05": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": [
"Map 1 0b11 0xC2 128-bit"
@@ -3371,7 +3342,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"mov v5.8b, v5.8b",
"fcmgt d5, d5, d4",
"mvn v5.16b, v5.16b",
"mov v4.d[0], v5.d[0]",
@@ -3381,7 +3351,7 @@
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x06": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Optimal": "No",
"Comment": [
"Map 1 0b11 0xC2 128-bit"
@@ -3389,7 +3359,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"mov v5.8b, v5.8b",
"fcmge d5, d5, d4",
"mvn v5.16b, v5.16b",
"mov v4.d[0], v5.d[0]",
@@ -3399,7 +3368,7 @@
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x07": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Optimal": "No",
"Comment": [
"Map 1 0b11 0xC2 128-bit"
@@ -3407,7 +3376,6 @@
"ExpectedArm64ASM": [
"mov z4.d, p7/m, z17.d",
"mov z5.d, p7/m, z18.d",
"mov v5.8b, v5.8b",
"fcmge d0, d4, d5",
"fcmgt d1, d5, d4",
"orr v5.8b, v0.8b, v1.8b",