Docs: Update for release FEX-2408

Merge pull request #3945 from Sonicadvance1/config_nonnullable
Config: Little assume non-null check
2026-10-07 06:00:16 +02:00 · 2024-08-12 15:05:37 -07:00 · 2024-08-11 15:23:37 -04:00 · 2024-08-11 10:25:53 -07:00 · 2024-08-10 20:07:43 -04:00 · 2024-08-10 09:07:58 -07:00
618 changed files with 271379 additions and 53809 deletions
@@ -7,7 +7,7 @@ AlignConsecutiveAssignments: None
 AlignConsecutiveBitFields: Consecutive
 AlignConsecutiveDeclarations: None
 AlignConsecutiveMacros: None
-AlignEscapedNewlines: DontAlign
+AlignEscapedNewlines: Left
 AlignOperands: Align
 AlignTrailingComments: true
 AllowAllParametersOfDeclarationOnNextLine: false
@@ -8,7 +8,5 @@ FEXCore/Source/Common/SoftFloat-3e/*
 Source/Common/cpp-optparse/*

 # Files with human-indented tables for readability - don't mess with these
-FEXCore/Source/Interface/Core/X86Tables/X87Tables.cpp
-FEXCore/Source/Interface/Core/X86Tables/XOPTables.cpp
 FEXCore/Source/Interface/Core/X86Tables/*

@@ -13,7 +13,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_ENABLEAVX: 1

 jobs:
  build_plus_test:
@@ -64,7 +63,7 @@ jobs:
      # Note the current convention is to use the -S and -B options here to specify source
      # and build directories, but this is only available with CMake 3.13 and higher.
      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DBUILD_FEX_LINUX_TESTS=True -DBUILD_THUNKS=True -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_FEX_LINUX_TESTS=True -DBUILD_THUNKS=True -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install

    - name: Build
      working-directory: ${{runner.workspace}}/build
@@ -20,7 +20,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_ENABLEAVX: 1

 jobs:
  glibc_fault_test:
@@ -71,7 +70,7 @@ jobs:
      # Note the current convention is to use the -S and -B options here to specify source
      # and build directories, but this is only available with CMake 3.13 and higher.
      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DBUILD_FEX_LINUX_TESTS=True -DENABLE_GLIBC_ALLOCATOR_HOOK_FAULT=True -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_FEX_LINUX_TESTS=True -DENABLE_GLIBC_ALLOCATOR_HOOK_FAULT=True -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install

    - name: Build
      working-directory: ${{runner.workspace}}/build
@@ -13,7 +13,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_ENABLEAVX: 1

 jobs:
  hostrunner_tests:
@@ -64,7 +63,7 @@ jobs:
      # Note the current convention is to use the -S and -B options here to specify source
      # and build directories, but this is only available with CMake 3.13 and higher.
      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True

    - name: Build
      working-directory: ${{runner.workspace}}/build
@@ -13,7 +13,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_ENABLEAVX: 1

 jobs:
  instcountci_tests:
@@ -74,7 +73,7 @@ jobs:
      # Note the current convention is to use the -S and -B options here to specify source
      # and build directories, but this is only available with CMake 3.13 and higher.
      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=$VIXL_SIM_ENABLED -DENABLE_VIXL_DISASSEMBLER=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=$VIXL_SIM_ENABLED -DENABLE_VIXL_DISASSEMBLER=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True

    - name: Build
      working-directory: ${{runner.workspace}}/build
@@ -10,14 +10,13 @@ on:

 env:
  BUILD_TYPE: Debug
-  FEX_ENABLEAVX: 1

 jobs:
  mingw_build:
    runs-on: ${{ matrix.arch }}
    strategy:
      matrix:
-        arch: [[self-hosted, ARM64, mingw]]
+        arch: [[self-hosted, ARM64, mingw], [self-hosted, ARM64EC, mingw, ARM64]]
      fail-fast: false

    steps:
@@ -39,6 +38,11 @@ jobs:
      run: |
        echo "MINGW_TRIPLE=aarch64-w64-mingw32" >> $GITHUB_ENV

+    - name: Set CC Arm64EC
+      if: matrix.arch[1] == 'ARM64EC'
+      run: |
+        echo "MINGW_TRIPLE=arm64ec-w64-mingw32" >> $GITHUB_ENV
+
    - name: Set rootfs paths
      run: |
        echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
@@ -74,7 +78,7 @@ jobs:
      # Note the current convention is to use the -S and -B options here to specify source
      # and build directories, but this is only available with CMake 3.13 and higher.
      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/toolchain_mingw.cmake -DMINGW_TRIPLE=$MINGW_TRIPLE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DBUILD_TESTS=False -DENABLE_JEMALLOC=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_TOOLCHAIN_FILE=$GITHUB_WORKSPACE/toolchain_mingw.cmake -DMINGW_TRIPLE=$MINGW_TRIPLE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DBUILD_TESTS=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install

    - name: Build
      working-directory: ${{runner.workspace}}/build
@@ -20,6 +20,7 @@ jobs:

      - name: Checkout through merge base
        uses: rmacklin/fetch-through-merge-base@v0
+        timeout-minutes: 3
        with:
          base_ref: ${{ github.event.pull_request.base.ref }}
          head_ref: ${{ github.event.pull_request.head.sha }}
@@ -13,7 +13,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_ENABLEAVX: 1

 jobs:
  vixl_simulator:
@@ -65,7 +64,7 @@ jobs:
      # Note the current convention is to use the -S and -B options here to specify source
      # and build directories, but this is only available with CMake 3.13 and higher.
      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=True -DENABLE_VIXL_DISASSEMBLER=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_VIXL_SIMULATOR=True -DENABLE_VIXL_DISASSEMBLER=True -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True

    - name: Build
      working-directory: ${{runner.workspace}}/build
@@ -73,23 +72,22 @@ jobs:
      # Execute the build.  You can specify a specific target with "--target <NAME>"
      run: cmake --build . --config $BUILD_TYPE

-    - name: ASM Tests
+    - name: ASM Tests - SVE256
      working-directory: ${{runner.workspace}}/build
      shell: bash
      # Execute the unit tests
      run: cmake --build . --config $BUILD_TYPE --target asm_tests

-    - name: ASM Test Results move
+    - name: ASM Test SVE256 Results move
      if: ${{ always() }}
      shell: bash
      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM_SVE256Bit.log || true

-    - name: ASM Tests 128-bit
+    - name: ASM Tests - SVE128
      working-directory: ${{runner.workspace}}/build
      shell: bash
      env:
-        FEX_HOSTFEATURES: "disableavx"
        FEX_FORCESVEWIDTH: "128"
      # Execute the unit tests
      run: cmake --build . --config $BUILD_TYPE --target asm_tests
@@ -98,7 +96,21 @@ jobs:
      if: ${{ always() }}
      shell: bash
      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM128bit.log || true
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM_SVE128Bit.log || true
+
+    - name: ASM Tests - ASIMD
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      env:
+        FEX_HOSTFEATURES: "disablesve"
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target asm_tests
+
+    - name: ASM Test ASIMD Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM_ASIMD.log || true

    - name: Truncate test results
      if: ${{ always() }}
@@ -1,5 +1,5 @@
 cmake_minimum_required(VERSION 3.14)
-project(FEX)
+project(FEX C CXX ASM)

 INCLUDE (CheckIncludeFiles)
 CHECK_INCLUDE_FILES ("gdb/jit-reader.h" HAVE_GDB_JIT_READER_H)
@@ -15,6 +15,7 @@ option(ENABLE_XRAY "Enable building with LLVM X-Ray" FALSE)
 set(USE_LINKER "" CACHE STRING "Allow overriding the linker path directly")
 option(ENABLE_ASAN "Enables Clang ASAN" FALSE)
 option(ENABLE_TSAN "Enables Clang TSAN" FALSE)
+option(ENABLE_COVERAGE "Enables Coverage" FALSE)
 option(ENABLE_ASSERTIONS "Enables assertions in build" FALSE)
 option(ENABLE_GDB_SYMBOLS "Enables GDBSymbols integration support" ${HAVE_GDB_JIT_READER_H})
 option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
@@ -31,6 +32,7 @@ option(COMPILE_VIXL_DISASSEMBLER "Compiles the vixl disassembler in to vixl" FAL
 option(ENABLE_FEXCORE_PROFILER "Enables use of the FEXCore timeline profiling capabilities" FALSE)
 set (FEXCORE_PROFILER_BACKEND "gpuvis" CACHE STRING "Set which backend you want to use for the FEXCore profiler")
 option(ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT "Enables glibc memory allocation hooking with fault for CI testing")
+option(USE_PDB_DEBUGINFO "Builds debug info in PDB format" FALSE)

 set (X86_32_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/toolchain_x86_32.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting i686")
 set (X86_64_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/toolchain_x86_64.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting x86_64")
@@ -40,7 +42,16 @@ string(FIND ${CMAKE_BASE_NAME} mingw CONTAINS_MINGW)
 if (NOT CONTAINS_MINGW EQUAL -1)
  message (STATUS "Mingw build")
  set (MINGW_BUILD TRUE)
-  set (ENABLE_JEMALLOC FALSE)
+  set (ENABLE_JEMALLOC TRUE)
+  set (ENABLE_JEMALLOC_GLIBC_ALLOC FALSE)
+endif()
+
+if (NOT MINGW_BUILD)
+  message (STATUS "Clang version ${CMAKE_CXX_COMPILER_VERSION}")
+  set (CLANG_MINIMUM_VERSION 12.0)
+  if (CMAKE_CXX_COMPILER_VERSION VERSION_LESS ${CLANG_MINIMUM_VERSION})
+    message (FATAL_ERROR "Clang version too old for FEX. Need at least ${CLANG_MINIMUM_VERSION} but has ${CMAKE_CXX_COMPILER_VERSION}")
+  endif()
 endif()

 if (ENABLE_FEXCORE_PROFILER)
@@ -110,6 +121,12 @@ else()
 endif()

 if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
+  option(ENABLE_X86_HOST_DEBUG "Enables compiling on x86_64 host" FALSE)
+  if (NOT ENABLE_X86_HOST_DEBUG)
+    message(FATAL_ERROR
+    " FEX-Emu doesn't support compiling for x86-64 hosts!"
+    " This is /only/ a supported configuration for FEX CI and nothing else!")
+  endif()
  set(_M_X86_64 1)
  add_definitions(-D_M_X86_64=1)
  set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
@@ -123,9 +140,39 @@ endif()
 if (CMAKE_SYSTEM_PROCESSOR MATCHES "^arm64ec")
  set(_M_ARM_64EC 1)
  add_definitions(-D_M_ARM_64EC=1)
+endif()

-  # Required as FEX is not allowed to lock the CRT heap lock during compilation or callbacks
-  set(ENABLE_JEMALLOC TRUE)
+include(CheckCXXSourceCompiles)
+set(CMAKE_REQUIRED_FLAGS "-std=c++11 -Wattributes -Werror=attributes")
+check_cxx_source_compiles(
+  "
+  __attribute__((preserve_all))
+  int Testy(int a, int b, int c, int d, int e, int f) {
+  return a + b + c + d + e + f;
+  }
+  int main() {
+  return Testy(0, 1, 2, 3, 4, 5);
+  }"
+  HAS_CLANG_PRESERVE_ALL)
+unset(CMAKE_REQUIRED_FLAGS)
+if (HAS_CLANG_PRESERVE_ALL)
+  if (MINGW_BUILD)
+    message(STATUS "Ignoring broken clang::preserve_all support")
+    set(HAS_CLANG_PRESERVE_ALL FALSE)
+  else()
+    message(STATUS "Has clang::preserve_all")
+  endif()
+endif ()
+
+if (_M_ARM_64 AND HAS_CLANG_PRESERVE_ALL)
+  add_definitions("-DFEX_PRESERVE_ALL_ATTR=__attribute__((preserve_all))" "-DFEX_HAS_PRESERVE_ALL_ATTR=1")
+else()
+  add_definitions("-DFEX_PRESERVE_ALL_ATTR=" "-DFEX_HAS_PRESERVE_ALL_ATTR=0")
+endif()
+
+if (ENABLE_VIXL_SIMULATOR)
+  # We can run the simulator on both x86-64 or AArch64 hosts
+  add_definitions(-DVIXL_SIMULATOR=1 -DVIXL_INCLUDE_SIMULATOR_AARCH64=1)
 endif()

 if (ENABLE_CCACHE)
@@ -175,13 +222,18 @@ if (ENABLE_TSAN)
  link_libraries(-fno-omit-frame-pointer -fsanitize=thread)
 endif()

+if (ENABLE_COVERAGE)
+  add_compile_options(-fprofile-instr-generate -fcoverage-mapping)
+  link_libraries(-fprofile-instr-generate -fcoverage-mapping)
+endif()
+
 if (ENABLE_JEMALLOC_GLIBC_ALLOC)
  # The glibc jemalloc subproject which hooks the glibc allocator.
  # Required for thunks to work.
  # All host native libraries will use this allocator, while *most* other FEX internal allocations will use the other jemalloc allocator.
  add_definitions(-DENABLE_JEMALLOC_GLIBC=1)
  add_subdirectory(External/jemalloc_glibc/)
-else()
+elseif (NOT MINGW_BUILD)
  message (STATUS
    " jemalloc glibc allocator disabled!\n"
    " This is not a recommended configuration!\n"
@@ -194,7 +246,7 @@ if (ENABLE_JEMALLOC)
  add_definitions(-DENABLE_JEMALLOC=1)
  add_subdirectory(External/jemalloc/)
  include_directories(External/jemalloc/pregen/include/)
-else()
+elseif (NOT MINGW_BUILD)
  message (STATUS
    " jemalloc disabled!\n"
    " This is not a recommended configuration!\n"
@@ -202,6 +254,11 @@ else()
    " Use at your own risk!")
 endif()

+if (USE_PDB_DEBUGINFO)
+  add_compile_options(-g -gcodeview)
+  add_link_options(-g -Wl,--pdb=)
+endif()
+
 set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
 set (CMAKE_LINKER_FLAGS_RELWITHDEBINFO "${CMAKE_LINKER_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")

@@ -235,8 +292,6 @@ add_definitions(-Wno-trigraphs)
 add_definitions(-DGLOBAL_DATA_DIRECTORY="${DATA_DIRECTORY}/")

 if (BUILD_TESTS)
-  option(CATCH_BUILD_STATIC_LIBRARY "" ON)
-  set(CATCH_BUILD_STATIC_LIBRARY ON)
  add_subdirectory(External/Catch2/)

  # Pull in catch_discover_tests definition
@@ -257,8 +312,6 @@ include_directories(External/json-maker/)
 add_subdirectory(External/tiny-json/)
 include_directories(External/tiny-json/)

-include_directories(External/xbyak/)
-
 include_directories(Source/)
 include_directories("${CMAKE_BINARY_DIR}/Source/")

@@ -356,9 +409,18 @@ if (BUILD_TESTS)
  include(CTest)
  enable_testing()
  message(STATUS "Unit tests are enabled")
+
+  set (TEST_JOB_COUNT "" CACHE STRING "Override number of parallel jobs to use while running tests")
+  if (TEST_JOB_COUNT)
+    message(STATUS "Running tests with ${TEST_JOB_COUNT} jobs")
+  elseif(CMAKE_VERSION VERSION_LESS "3.29")
+    execute_process(COMMAND "nproc" OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE TEST_JOB_COUNT)
+  endif()
+  set(TEST_JOB_FLAG "-j${TEST_JOB_COUNT}")
 endif()

 add_subdirectory(FEXHeaderUtils/)
+add_subdirectory(CodeEmitter/)
 add_subdirectory(FEXCore/)

 # Binfmt_misc files must be installed prior to Source/ installs
@@ -0,0 +1,2 @@
+add_library(CodeEmitter INTERFACE)
+target_include_directories(CodeEmitter INTERFACE .)
@@ -8,11 +8,11 @@ public:
  public:
    // Conditional branch immediate
    ///< Branch conditional
-    void b(FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) {
+    void b(ARMEmitter::Condition Cond, uint32_t Imm) {
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 0, Cond, Imm);
    }
-    void b(FEXCore::ARMEmitter::Condition Cond, BackwardLabel const* Label) {
+    void b(ARMEmitter::Condition Cond, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
      constexpr uint32_t Op = 0b0101'010 << 25;
@@ -20,13 +20,13 @@ public:
    }
    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void b(FEXCore::ARMEmitter::Condition Cond, LabelType *Label) {
+    void b(ARMEmitter::Condition Cond, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 0, Cond, 0);
    }

-    void b(FEXCore::ARMEmitter::Condition Cond, BiDirectionalLabel *Label) {
+    void b(ARMEmitter::Condition Cond, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        b(Cond, &Label->Backward);
      }
@@ -36,11 +36,11 @@ public:
    }

    ///< Branch consistent conditional
-    void bc(FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) {
+    void bc(ARMEmitter::Condition Cond, uint32_t Imm) {
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 1, Cond, Imm);
    }
-    void bc(FEXCore::ARMEmitter::Condition Cond, BackwardLabel const* Label) {
+    void bc(ARMEmitter::Condition Cond, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
      constexpr uint32_t Op = 0b0101'010 << 25;
@@ -49,13 +49,13 @@ public:

    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void bc(FEXCore::ARMEmitter::Condition Cond, LabelType *Label) {
+    void bc(ARMEmitter::Condition Cond, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 1, Cond, 0);
    }

-    void bc(FEXCore::ARMEmitter::Condition Cond, BiDirectionalLabel *Label) {
+    void bc(ARMEmitter::Condition Cond, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        bc(Cond, &Label->Backward);
      }
@@ -65,7 +65,7 @@ public:
    }

    // Unconditional branch register
-    void br(FEXCore::ARMEmitter::Register rn) {
+    void br(ARMEmitter::Register rn) {
      constexpr uint32_t Op = 0b1101011 << 25 |
                              0b0'000 << 21 |   // opc
                              0b1'1111 << 16 |  // op2
@@ -74,7 +74,7 @@ public:

      UnconditionalBranch(Op, rn);
    }
-    void blr(FEXCore::ARMEmitter::Register rn) {
+    void blr(ARMEmitter::Register rn) {
      constexpr uint32_t Op = 0b1101011 << 25 |
                              0b0'001 << 21 |   // opc
                              0b1'1111 << 16 |  // op2
@@ -83,7 +83,7 @@ public:

      UnconditionalBranch(Op, rn);
    }
-    void ret(FEXCore::ARMEmitter::Register rn = FEXCore::ARMEmitter::Reg::r30) {
+    void ret(ARMEmitter::Register rn = ARMEmitter::Reg::r30) {
      constexpr uint32_t Op = 0b1101011 << 25 |
                              0b0'010 << 21 |   // opc
                              0b1'1111 << 16 |  // op2
@@ -156,13 +156,13 @@ public:
    }

    // Compare and branch
-    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) {
+    void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, uint32_t Imm) {
      constexpr uint32_t Op = 0b0011'0100 << 24;

      CompareAndBranch(Op, s, rt, Imm);
    }

-    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BackwardLabel const* Label) {
+    void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");

@@ -173,7 +173,7 @@ public:

    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, LabelType *Label) {
+    void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });

      constexpr uint32_t Op = 0b0011'0100 << 24;
@@ -181,7 +181,7 @@ public:
      CompareAndBranch(Op, s, rt, 0);
    }

-    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BiDirectionalLabel *Label) {
+    void cbz(ARMEmitter::Size s, ARMEmitter::Register rt, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        cbz(s, rt, &Label->Backward);
      }
@@ -190,13 +190,13 @@ public:
      }
    }

-    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) {
+    void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, uint32_t Imm) {
      constexpr uint32_t Op = 0b0011'0101 << 24;

      CompareAndBranch(Op, s, rt, Imm);
    }

-    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BackwardLabel const* Label) {
+    void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");

@@ -207,7 +207,7 @@ public:

    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, LabelType *Label) {
+    void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });

      constexpr uint32_t Op = 0b0011'0101 << 24;
@@ -215,7 +215,7 @@ public:
      CompareAndBranch(Op, s, rt, 0);
    }

-    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, BiDirectionalLabel *Label) {
+    void cbnz(ARMEmitter::Size s, ARMEmitter::Register rt, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        cbnz(s, rt, &Label->Backward);
      }
@@ -225,12 +225,12 @@ public:
    }

    // Test and branch immediate
-    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
+    void tbz(ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
      constexpr uint32_t Op = 0b0011'0110 << 24;

      TestAndBranch(Op, rt, Bit, Imm);
    }
-    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) {
+    void tbz(ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");

@@ -241,7 +241,7 @@ public:

    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) {
+    void tbz(ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::TEST_BRANCH });

      constexpr uint32_t Op = 0b0011'0110 << 24;
@@ -249,7 +249,7 @@ public:
      TestAndBranch(Op, rt, Bit, 0);
    }

-    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) {
+    void tbz(ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        tbz(rt, Bit, &Label->Backward);
      }
@@ -258,12 +258,12 @@ public:
      }
    }

-    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
+    void tbnz(ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
      constexpr uint32_t Op = 0b0011'0111 << 24;

      TestAndBranch(Op, rt, Bit, Imm);
    }
-    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) {
+    void tbnz(ARMEmitter::Register rt, uint32_t Bit, BackwardLabel const* Label) {
      int32_t Imm = static_cast<int32_t>(Label->Location - GetCursorAddress<uint8_t*>());
      LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");

@@ -274,14 +274,14 @@ public:

    template<typename LabelType>
    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
-    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) {
+    void tbnz(ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) {
      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::TEST_BRANCH });
      constexpr uint32_t Op = 0b0011'0111 << 24;

      TestAndBranch(Op, rt, Bit, 0);
    }

-    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) {
+    void tbnz(ARMEmitter::Register rt, uint32_t Bit, BiDirectionalLabel *Label) {
      if (Label->Backward.Location) {
        tbnz(rt, Bit, &Label->Backward);
      }
@@ -292,7 +292,7 @@ public:

 private:
    // Conditional branch immediate
-    void Branch_Conditional(uint32_t Op, uint32_t Op1, uint32_t Op0, FEXCore::ARMEmitter::Condition Cond, uint32_t Imm) {
+    void Branch_Conditional(uint32_t Op, uint32_t Op1, uint32_t Op0, ARMEmitter::Condition Cond, uint32_t Imm) {
      uint32_t Instr = Op;

      Instr |= Op1 << 24;
@@ -304,7 +304,7 @@ private:
    }

    // Unconditional branch register
-    void UnconditionalBranch(uint32_t Op, FEXCore::ARMEmitter::Register rn) {
+    void UnconditionalBranch(uint32_t Op, ARMEmitter::Register rn) {
      uint32_t Instr = Op;
      Instr |= Encode_rn(rn);
      dc32(Instr);
@@ -318,8 +318,8 @@ private:
    }

    // Compare and branch
-    void CompareAndBranch(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, uint32_t Imm) {
-      const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+    void CompareAndBranch(uint32_t Op, ARMEmitter::Size s, ARMEmitter::Register rt, uint32_t Imm) {
+      const uint32_t SF = s == ARMEmitter::Size::i64Bit ? (1U << 31) : 0;

      uint32_t Instr = Op;

@@ -330,7 +330,7 @@ private:
    }

    // Test and branch - immediate
-    void TestAndBranch(uint32_t Op, FEXCore::ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
+    void TestAndBranch(uint32_t Op, ARMEmitter::Register rt, uint32_t Bit, uint32_t Imm) {
      uint32_t Instr = Op;

      Instr |= (Bit >> 5) << 31;
@@ -4,7 +4,7 @@
 #include <cstdint>
 #include <cstring>

-namespace FEXCore::ARMEmitter {
+namespace ARMEmitter {
 class Buffer {
 public:
  Buffer() {
@@ -103,4 +103,4 @@ protected:
  uint8_t* CurrentOffset;
  uint64_t Size;
 };
-} // namespace FEXCore::ARMEmitter
+} // namespace ARMEmitter
@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: MIT
 #pragma once

-#include "Interface/Core/ArchHelpers/CodeEmitter/Buffer.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
-
 #include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
@@ -11,8 +8,8 @@
 #include <FEXCore/fextl/vector.h>

 #include <FEXHeaderUtils/BitUtils.h>
-
-#include <aarch64/assembler-aarch64.h>
+#include <CodeEmitter/Buffer.h>
+#include <CodeEmitter/Registers.h>

 #include <array>
 #include <cstdint>
@@ -56,7 +53,7 @@
 *     it easier to select the correct load-store instruction. Mostly because these are a nightmare selecting
 *     the right instruction.
 */
-namespace FEXCore::ARMEmitter {
+namespace ARMEmitter {
 /*
 * This `Size` enum is used for most ALU operations.
 * These follow the AArch64 encoding style in most cases.
@@ -605,13 +602,25 @@ constexpr bool AreVectorsSequential(T first, const Args&... args) {
  return (fn(first, args) && ...);
 }

+// Returns if the immediate can fit in to add/sub immediate instruction encodings.
+constexpr bool IsImmAddSub(uint64_t imm) {
+  constexpr uint64_t U12Mask = 0xFFF;
+  auto FitsWithin12Bits = [](uint64_t imm) {
+    return (imm & ~U12Mask) == 0;
+  };
+  // Can fit in to the instruction encoding:
+  // - if only bits [11:0] are set.
+  // - if only bits [23:12] are set.
+  return FitsWithin12Bits(imm) || (FitsWithin12Bits(imm >> 12) && (imm & U12Mask) == 0);
+}
+
 // This is an emitter that is designed around the smallest code bloat as possible.
 // Eschewing most developer convenience in order to keep code as small as possible.

 // Choices:
 // - Size of ops passed as an argument rather than template to let the compiler use csel instead of branching.
 // - Registers are unsized so they can be passed in a GPR and not need conversion operations
-class Emitter : public FEXCore::ARMEmitter::Buffer {
+class Emitter : public ARMEmitter::Buffer {
 public:
  Emitter() = default;

@@ -759,15 +768,17 @@ public:
    Bind<false>(&Label->Forward);
  }

+#include <CodeEmitter/VixlUtils.inl>
+
 public:
  // TODO: Implement SME when it matters.
-#include "Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/BranchOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/LoadstoreOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/SystemOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/ScalarOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/ASIMDOps.inl"
-#include "Interface/Core/ArchHelpers/CodeEmitter/SVEOps.inl"
+#include <CodeEmitter/ALUOps.inl>
+#include <CodeEmitter/BranchOps.inl>
+#include <CodeEmitter/LoadstoreOps.inl>
+#include <CodeEmitter/SystemOps.inl>
+#include <CodeEmitter/ScalarOps.inl>
+#include <CodeEmitter/ASIMDOps.inl>
+#include <CodeEmitter/SVEOps.inl>

 private:
  template<typename T>
@@ -829,4 +840,4 @@ private:
    return FEXCore::ToUnderlying(Reg);
  }
 };
-} // namespace FEXCore::ARMEmitter
+} // namespace ARMEmitter
@@ -6,7 +6,7 @@
 #include <compare>
 #include <cstdint>

-namespace FEXCore::ARMEmitter {
+namespace ARMEmitter {
 class WRegister;
 class XRegister;

@@ -1024,4 +1024,4 @@ enum class OpType : uint32_t {
  Destructive = 0,
  Constructive,
 };
-} // namespace FEXCore::ARMEmitter
+} // namespace ARMEmitter
@@ -1506,13 +1506,14 @@ public:
  }

  // SVE broadcast floating-point immediate (unpredicated)
-  void fdup(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, float Value) {
-    LOGMAN_THROW_AA_FMT(size == FEXCore::ARMEmitter::SubRegSize::i16Bit ||
-                        size == FEXCore::ARMEmitter::SubRegSize::i32Bit ||
-                        size == FEXCore::ARMEmitter::SubRegSize::i64Bit, "Unsupported fmov size");
+  void fdup(ARMEmitter::SubRegSize size, ARMEmitter::ZRegister zd, float Value) {
+    LOGMAN_THROW_AA_FMT(size == ARMEmitter::SubRegSize::i16Bit ||
+                        size == ARMEmitter::SubRegSize::i32Bit ||
+                        size == ARMEmitter::SubRegSize::i64Bit, "Unsupported fmov size");
    uint32_t Imm{};
    if (size == SubRegSize::i16Bit) {
-      Imm = FP16ToImm8(vixl::Float16(Value));
+      LOGMAN_MSG_A_FMT("Unsupported");
+      FEX_UNREACHABLE;
    } else if (size == SubRegSize::i32Bit) {
      Imm = FP32ToImm8(Value);
    } else if (size == SubRegSize::i64Bit) {
@@ -1521,7 +1522,7 @@ public:

    SVEBroadcastFloatImmUnpredicated(0b00, 0, Imm, size, zd);
  }
-  void fmov(FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, float Value) {
+  void fmov(ARMEmitter::SubRegSize size, ARMEmitter::ZRegister zd, float Value) {
    fdup(size, zd, Value);
  }

@@ -2568,7 +2569,19 @@ public:
  }

  // SVE contiguous non-temporal load (scalar plus immediate)
-  // XXX:
+  void ldnt1b(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalLoad(0b00, zt, pg, rn, Imm);
+  }
+  void ldnt1h(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalLoad(0b01, zt, pg, rn, Imm);
+  }
+  void ldnt1w(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalLoad(0b10, zt, pg, rn, Imm);
+  }
+  void ldnt1d(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalLoad(0b11, zt, pg, rn, Imm);
+  }
+
  // SVE contiguous non-temporal load (scalar plus scalar)
  // XXX:
  // SVE load multiple structures (scalar plus immediate)
@@ -3320,7 +3333,18 @@ public:

  // SVE Memory - Contiguous Store with Immediate Offset
  // SVE contiguous non-temporal store (scalar plus immediate)
-  // XXX:
+  void stnt1b(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalStore(0b00, zt, pg, rn, Imm);
+  }
+  void stnt1h(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalStore(0b01, zt, pg, rn, Imm);
+  }
+  void stnt1w(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalStore(0b10, zt, pg, rn, Imm);
+  }
+  void stnt1d(ZRegister zt, PRegister pg, Register rn, int32_t Imm = 0) {
+    SVEContiguousNontemporalStore(0b11, zt, pg, rn, Imm);
+  }

  // SVE store multiple structures (scalar plus immediate)
  void st2b(ZRegister zt1, ZRegister zt2, PRegister pg, Register rn, int32_t Imm = 0) {
@@ -3513,7 +3537,8 @@ private:
                        size == SubRegSize::i64Bit, "Unsupported fcpy/fmov size");
    uint32_t imm{};
    if (size == SubRegSize::i16Bit) {
-      imm = FP16ToImm8(vixl::Float16(value));
+      LOGMAN_MSG_A_FMT("Unsupported");
+      FEX_UNREACHABLE;
    } else if (size == SubRegSize::i32Bit) {
      imm = FP32ToImm8(value);
    } else if (size == SubRegSize::i64Bit) {
@@ -3717,7 +3742,7 @@ private:

  // SVE bitwise logical operations (predicated)
  void SVEBitwiseLogicalPredicated(uint32_t opc, SubRegSize size, PRegister pg, ZRegister zdn, ZRegister zm, ZRegister zd) {
-    LOGMAN_THROW_AA_FMT(size != FEXCore::ARMEmitter::SubRegSize::i128Bit, "Can't use 128-bit size");
+    LOGMAN_THROW_AA_FMT(size != ARMEmitter::SubRegSize::i128Bit, "Can't use 128-bit size");
    LOGMAN_THROW_A_FMT(zd == zdn, "zd needs to equal zdn");
    LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate");

@@ -4479,6 +4504,38 @@ private:
    dc32(Instr);
  }

+  // SVE contiguous non-temporal load (scalar plus immediate)
+  void SVEContiguousNontemporalLoad(uint32_t msz, ZRegister zt, PRegister pg, Register rn, int32_t imm) {
+    LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate");
+    LOGMAN_THROW_AA_FMT(imm >= -8 && imm <= 7,
+                        "Invalid loadstore offset ({}). Must be between [-8, 7]", imm);
+
+    const auto imm4 = static_cast<uint32_t>(imm) & 0xF;
+    uint32_t Instr = 0b1010'0100'0000'0000'1110'0000'0000'0000;
+    Instr |= msz << 23;
+    Instr |= imm4 << 16;
+    Instr |= pg.Idx() << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= zt.Idx();
+    dc32(Instr);
+  }
+
+  // SVE contiguous non-temporal store (scalar plus immediate)
+  void SVEContiguousNontemporalStore(uint32_t msz, ZRegister zt, PRegister pg, Register rn, int32_t imm) {
+    LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate");
+    LOGMAN_THROW_AA_FMT(imm >= -8 && imm <= 7,
+                        "Invalid loadstore offset ({}). Must be between [-8, 7]", imm);
+
+    const auto imm4 = static_cast<uint32_t>(imm) & 0xF;
+    uint32_t Instr = 0b1110'0100'0001'0000'1110'0000'0000'0000;
+    Instr |= msz << 23;
+    Instr |= imm4 << 16;
+    Instr |= pg.Idx() << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= zt.Idx();
+    dc32(Instr);
+  }
+
  void SVEContiguousLoadImm(bool is_store, uint32_t dtype, int32_t imm, PRegister pg, Register rn, ZRegister zt) {
    LOGMAN_THROW_A_FMT(pg <= PReg::p7, "Can only use p0-p7 as a governing predicate");
    LOGMAN_THROW_AA_FMT(imm >= -8 && imm <= 7,
@@ -4743,7 +4800,7 @@ private:
    dc32(Instr);
  }

-  void SVEPermuteVector(uint32_t op0, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::ZRegister zm, uint32_t Imm) {
+  void SVEPermuteVector(uint32_t op0, ARMEmitter::ZRegister zd, ARMEmitter::ZRegister zm, uint32_t Imm) {
    constexpr uint32_t Op = 0b0000'0101'0010'0000'000 << 13;
    uint32_t Instr = Op;

@@ -5228,15 +5285,14 @@ private:

  // Alias that returns the equivalently sized unsigned type for a floating-point type T.
  template <typename T>
-  requires(std::is_same_v<T, float> || std::is_same_v<T, double> || std::is_same_v<T, vixl::Float16>)
-  using FloatToEquivalentUInt = std::conditional_t<std::is_same_v<T, vixl::Float16>, uint16_t,
-                                                   std::conditional_t<std::is_same_v<T, float>, uint32_t, uint64_t>>;
+  requires(std::is_same_v<T, float> || std::is_same_v<T, double>)
+  using FloatToEquivalentUInt = std::conditional_t<std::is_same_v<T, float>, uint32_t, uint64_t>;

  // Determines if a floating-point value is capable of being converted
  // into an 8-bit immediate. See pseudocode definition of VFPExpandImm
  // in ARM A-profile reference manual for a general overview of how this was derived.
  template <typename T>
-  requires(std::is_same_v<T, float> || std::is_same_v<T, double> || std::is_same_v<T, vixl::Float16>)
+  requires(std::is_same_v<T, float> || std::is_same_v<T, double>)
  [[nodiscard, maybe_unused]] static bool IsValidFPValueForImm8(T value) {
    const uint64_t bits = FEXCore::BitCast<FloatToEquivalentUInt<T>>(value);
    const uint64_t datasize_idx = FEXCore::ilog2(sizeof(T)) - 1;
@@ -5277,18 +5333,6 @@ private:
    return true;
  }

-  static uint32_t FP16ToImm8(vixl::Float16 value) {
-    LOGMAN_THROW_A_FMT(IsValidFPValueForImm8(value),
-                       "Value cannot be encoded into an 8-bit immediate");
-
-    const uint32_t bits = vixl::Float16ToRawbits(value);
-    const uint32_t sign = (bits & 0x8000) >> 8;
-    const uint32_t expb2 = (bits & 0x2000) >> 7;
-    const uint32_t b5_to_0 = (bits >> 6) & 0x3F;
-
-    return sign | expb2 | b5_to_0;
-  }
-
  static uint32_t FP32ToImm8(float value) {
    LOGMAN_THROW_A_FMT(IsValidFPValueForImm8(value),
                       "Value ({}) cannot be encoded into an 8-bit immediate", value);
@@ -33,7 +33,7 @@ public:
    ASIMDScalarCopy(Op, 1, imm5, 0b0000, rd, rn);
  }

-  void mov(FEXCore::ARMEmitter::ScalarRegSize size, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn, uint32_t Index) {
+  void mov(ARMEmitter::ScalarRegSize size, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn, uint32_t Index) {
    dup(size, rd, rn, Index);
  }

@@ -1052,21 +1052,21 @@ public:
  }

 // Floating-point immediate
-  void fmov(FEXCore::ARMEmitter::ScalarRegSize size, FEXCore::ARMEmitter::VRegister rd, float Value) {
+  void fmov(ARMEmitter::ScalarRegSize size, ARMEmitter::VRegister rd, float Value) {
    uint32_t M = 0;
    uint32_t S = 0;
    uint32_t ptype;
    uint32_t imm8;
    uint32_t imm5 = 0b0'0000;
-    if (size == FEXCore::ARMEmitter::ScalarRegSize::i16Bit) {
-      ptype = 0b11;
-      imm8 = FP16ToImm8(vixl::Float16(Value));
+    if (size == ARMEmitter::ScalarRegSize::i16Bit) {
+      LOGMAN_MSG_A_FMT("Unsupported");
+      FEX_UNREACHABLE;
    }
-    else if (size == FEXCore::ARMEmitter::ScalarRegSize::i32Bit) {
+    else if (size == ARMEmitter::ScalarRegSize::i32Bit) {
      ptype = 0b00;
      imm8 = FP32ToImm8(Value);
    }
-    else if (size == FEXCore::ARMEmitter::ScalarRegSize::i64Bit) {
+    else if (size == ARMEmitter::ScalarRegSize::i64Bit) {
      ptype = 0b01;
      imm8 = FP64ToImm8(Value);
    }
@@ -1077,7 +1077,7 @@ public:
    FloatScalarImmediate(M, S, ptype, imm8, imm5, rd);
  }

-  void FloatScalarImmediate(uint32_t M, uint32_t S, uint32_t ptype, uint32_t imm8, uint32_t imm5, FEXCore::ARMEmitter::VRegister rd) {
+  void FloatScalarImmediate(uint32_t M, uint32_t S, uint32_t ptype, uint32_t imm8, uint32_t imm5, ARMEmitter::VRegister rd) {
    constexpr uint32_t Op = 0b0001'1110'0010'0000'0001'00 << 10;
    uint32_t Instr = Op;

@@ -1286,7 +1286,7 @@ public:

 private:
 // Advanced SIMD scalar copy
-  void ASIMDScalarCopy(uint32_t Op, uint32_t Q, uint32_t imm5, uint32_t imm4, FEXCore::ARMEmitter::VRegister rd, FEXCore::ARMEmitter::VRegister rn) {
+  void ASIMDScalarCopy(uint32_t Op, uint32_t Q, uint32_t imm5, uint32_t imm4, ARMEmitter::VRegister rd, ARMEmitter::VRegister rn) {
    uint32_t Instr = Op;

    Instr |= Q << 30;
@@ -11,7 +11,7 @@ public:
    // TODO: AT
    // TODO: CFP
    // TODO: CPP
-    void dc(FEXCore::ARMEmitter::DataCacheOperation DCOp, FEXCore::ARMEmitter::Register rt) {
+    void dc(ARMEmitter::DataCacheOperation DCOp, ARMEmitter::Register rt) {
      constexpr uint32_t Op = 0b1101'0101'0000'1000'0111 << 12;
      SystemInstruction(Op, 0, FEXCore::ToUnderlying(DCOp), rt);
    }
@@ -48,67 +48,67 @@ public:
      ExceptionGeneration(0b101, 0b000, 0b11, Imm);
    }
    // System instructions with register argument
-    void wfet(FEXCore::ARMEmitter::Register rt) {
+    void wfet(ARMEmitter::Register rt) {
      SystemInstructionWithReg(0b0000, 0b000, rt);
    }
-    void wfit(FEXCore::ARMEmitter::Register rt) {
+    void wfit(ARMEmitter::Register rt) {
      SystemInstructionWithReg(0b0000, 0b001, rt);
    }

    // Hints
    void nop() {
-      Hint(FEXCore::ARMEmitter::HintRegister::NOP);
+      Hint(ARMEmitter::HintRegister::NOP);
    }
    void yield() {
-      Hint(FEXCore::ARMEmitter::HintRegister::YIELD);
+      Hint(ARMEmitter::HintRegister::YIELD);
    }
    void wfe() {
-      Hint(FEXCore::ARMEmitter::HintRegister::WFE);
+      Hint(ARMEmitter::HintRegister::WFE);
    }
    void wfi() {
-      Hint(FEXCore::ARMEmitter::HintRegister::WFI);
+      Hint(ARMEmitter::HintRegister::WFI);
    }
    void sev() {
-      Hint(FEXCore::ARMEmitter::HintRegister::SEV);
+      Hint(ARMEmitter::HintRegister::SEV);
    }
    void sevl() {
-      Hint(FEXCore::ARMEmitter::HintRegister::SEVL);
+      Hint(ARMEmitter::HintRegister::SEVL);
    }
    void dgh() {
-      Hint(FEXCore::ARMEmitter::HintRegister::DGH);
+      Hint(ARMEmitter::HintRegister::DGH);
    }
    void csdb() {
-      Hint(FEXCore::ARMEmitter::HintRegister::CSDB);
+      Hint(ARMEmitter::HintRegister::CSDB);
    }

    // Barriers
    void clrex(uint32_t imm = 15) {
      LOGMAN_THROW_AA_FMT(imm < 16, "Immediate out of range");
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::CLREX, imm);
+      Barrier(ARMEmitter::BarrierRegister::CLREX, imm);
    }
-    void dsb(FEXCore::ARMEmitter::BarrierScope Scope) {
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::DSB, FEXCore::ToUnderlying(Scope));
+    void dsb(ARMEmitter::BarrierScope Scope) {
+      Barrier(ARMEmitter::BarrierRegister::DSB, FEXCore::ToUnderlying(Scope));
    }
-    void dmb(FEXCore::ARMEmitter::BarrierScope Scope) {
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::DMB, FEXCore::ToUnderlying(Scope));
+    void dmb(ARMEmitter::BarrierScope Scope) {
+      Barrier(ARMEmitter::BarrierRegister::DMB, FEXCore::ToUnderlying(Scope));
    }
    void isb() {
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::ISB, FEXCore::ToUnderlying(FEXCore::ARMEmitter::BarrierScope::SY));
+      Barrier(ARMEmitter::BarrierRegister::ISB, FEXCore::ToUnderlying(ARMEmitter::BarrierScope::SY));
    }
    void sb() {
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::SB, 0);
+      Barrier(ARMEmitter::BarrierRegister::SB, 0);
    }
    void tcommit() {
-      Barrier(FEXCore::ARMEmitter::BarrierRegister::TCOMMIT, 0);
+      Barrier(ARMEmitter::BarrierRegister::TCOMMIT, 0);
    }

    // System register move
-    void msr(FEXCore::ARMEmitter::SystemRegister reg, FEXCore::ARMEmitter::Register rt) {
+    void msr(ARMEmitter::SystemRegister reg, ARMEmitter::Register rt) {
      constexpr uint32_t Op = 0b1101'0101'0001 << 20;
      SystemRegisterMove(Op, rt, reg);
    }

-    void mrs(FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::SystemRegister reg) {
+    void mrs(ARMEmitter::Register rd, ARMEmitter::SystemRegister reg) {
      constexpr uint32_t Op = 0b1101'0101'0011 << 20;
      SystemRegisterMove(Op, rd, reg);
    }
@@ -130,7 +130,7 @@ private:
    }

    // System instructions with register argument
-    void SystemInstructionWithReg(uint32_t CRm, uint32_t op2, FEXCore::ARMEmitter::Register rt) {
+    void SystemInstructionWithReg(uint32_t CRm, uint32_t op2, ARMEmitter::Register rt) {
      uint32_t Instr = 0b1101'0101'0000'0011'0001 << 12;

      Instr |= CRm << 8;
@@ -140,13 +140,13 @@ private:
    }

    // Hints
-    void Hint(FEXCore::ARMEmitter::HintRegister Reg) {
+    void Hint(ARMEmitter::HintRegister Reg) {
      uint32_t Instr = 0b1101'0101'0000'0011'0010'0000'0001'1111U;
      Instr |= FEXCore::ToUnderlying(Reg);
      dc32(Instr);
    }
    // Barriers
-    void Barrier(FEXCore::ARMEmitter::BarrierRegister Reg, uint32_t CRm) {
+    void Barrier(ARMEmitter::BarrierRegister Reg, uint32_t CRm) {
      uint32_t Instr = 0b1101'0101'0000'0011'0011'0000'0001'1111U;
      Instr |= CRm << 8;
      Instr |= FEXCore::ToUnderlying(Reg);
@@ -154,7 +154,7 @@ private:
    }

    // System Instruction
-    void SystemInstruction(uint32_t Op, uint32_t L, uint32_t SubOp, FEXCore::ARMEmitter::Register rt) {
+    void SystemInstruction(uint32_t Op, uint32_t L, uint32_t SubOp, ARMEmitter::Register rt) {
      uint32_t Instr = Op;

      Instr |= L << 21;
@@ -165,7 +165,7 @@ private:
    }

    // System register move
-    void SystemRegisterMove(uint32_t Op, FEXCore::ARMEmitter::Register rt, FEXCore::ARMEmitter::SystemRegister reg) {
+    void SystemRegisterMove(uint32_t Op, ARMEmitter::Register rt, ARMEmitter::SystemRegister reg) {
      uint32_t Instr = Op;

      Instr |= FEXCore::ToUnderlying(reg);
@@ -0,0 +1,351 @@
+// Collection of utilities from vixl.
+// Following is the vixl license.
+// Copyright 2015, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+// Test if a given value can be encoded in the immediate field of a logical
+// instruction.
+// If it can be encoded, the function returns true, and values pointed to by n,
+// imm_s and imm_r are updated with immediates encoded in the format required
+// by the corresponding fields in the logical instruction.
+// If it can not be encoded, the function returns false, and the values pointed
+// to by n, imm_s and imm_r are undefined.
+static bool IsImmLogical(uint64_t value,
+                             unsigned width,
+                             unsigned* n = nullptr,
+                             unsigned* imm_s = nullptr,
+                             unsigned* imm_r = nullptr) {
+  [[maybe_unused]] constexpr auto kBRegSize = 8;
+  [[maybe_unused]] constexpr auto kHRegSize = 16;
+  [[maybe_unused]] constexpr auto kSRegSize = 32;
+  [[maybe_unused]] constexpr auto kDRegSize = 64;
+
+  constexpr auto kWRegSize = 32;
+  constexpr auto kXRegSize = 64;
+
+  LOGMAN_THROW_A_FMT((width == kBRegSize) || (width == kHRegSize) ||
+              (width == kSRegSize) || (width == kDRegSize), "Unexpected imm size");
+
+  bool negate = false;
+
+  // Logical immediates are encoded using parameters n, imm_s and imm_r using
+  // the following table:
+  //
+  //    N   imms    immr    size        S             R
+  //    1  ssssss  rrrrrr    64    UInt(ssssss)  UInt(rrrrrr)
+  //    0  0sssss  xrrrrr    32    UInt(sssss)   UInt(rrrrr)
+  //    0  10ssss  xxrrrr    16    UInt(ssss)    UInt(rrrr)
+  //    0  110sss  xxxrrr     8    UInt(sss)     UInt(rrr)
+  //    0  1110ss  xxxxrr     4    UInt(ss)      UInt(rr)
+  //    0  11110s  xxxxxr     2    UInt(s)       UInt(r)
+  // (s bits must not be all set)
+  //
+  // A pattern is constructed of size bits, where the least significant S+1 bits
+  // are set. The pattern is rotated right by R, and repeated across a 32 or
+  // 64-bit value, depending on destination register width.
+  //
+  // Put another way: the basic format of a logical immediate is a single
+  // contiguous stretch of 1 bits, repeated across the whole word at intervals
+  // given by a power of 2. To identify them quickly, we first locate the
+  // lowest stretch of 1 bits, then the next 1 bit above that; that combination
+  // is different for every logical immediate, so it gives us all the
+  // information we need to identify the only logical immediate that our input
+  // could be, and then we simply check if that's the value we actually have.
+  //
+  // (The rotation parameter does give the possibility of the stretch of 1 bits
+  // going 'round the end' of the word. To deal with that, we observe that in
+  // any situation where that happens the bitwise NOT of the value is also a
+  // valid logical immediate. So we simply invert the input whenever its low bit
+  // is set, and then we know that the rotated case can't arise.)
+
+  if (value & 1) {
+    // If the low bit is 1, negate the value, and set a flag to remember that we
+    // did (so that we can adjust the return values appropriately).
+    negate = true;
+    value = ~value;
+  }
+
+  if (width <= kWRegSize) {
+    // To handle 8/16/32-bit logical immediates, the very easiest thing is to repeat
+    // the input value to fill a 64-bit word. The correct encoding of that as a
+    // logical immediate will also be the correct encoding of the value.
+
+    // Avoid making the assumption that the most-significant 56/48/32 bits are zero by
+    // shifting the value left and duplicating it.
+    for (unsigned bits = width; bits <= kWRegSize; bits *= 2) {
+      value <<= bits;
+      uint64_t mask = (UINT64_C(1) << bits) - 1;
+      value |= ((value >> bits) & mask);
+    }
+  }
+
+  // The basic analysis idea: imagine our input word looks like this.
+  //
+  //    0011111000111110001111100011111000111110001111100011111000111110
+  //                                                          c  b    a
+  //                                                          |<--d-->|
+  //
+  // We find the lowest set bit (as an actual power-of-2 value, not its index)
+  // and call it a. Then we add a to our original number, which wipes out the
+  // bottommost stretch of set bits and replaces it with a 1 carried into the
+  // next zero bit. Then we look for the new lowest set bit, which is in
+  // position b, and subtract it, so now our number is just like the original
+  // but with the lowest stretch of set bits completely gone. Now we find the
+  // lowest set bit again, which is position c in the diagram above. Then we'll
+  // measure the distance d between bit positions a and c (using CLZ), and that
+  // tells us that the only valid logical immediate that could possibly be equal
+  // to this number is the one in which a stretch of bits running from a to just
+  // below b is replicated every d bits.
+  uint64_t a = LowestSetBit(value);
+  uint64_t value_plus_a = value + a;
+  uint64_t b = LowestSetBit(value_plus_a);
+  uint64_t value_plus_a_minus_b = value_plus_a - b;
+  uint64_t c = LowestSetBit(value_plus_a_minus_b);
+
+  int d, clz_a, out_n;
+  uint64_t mask;
+
+  if (c != 0) {
+    // The general case, in which there is more than one stretch of set bits.
+    // Compute the repeat distance d, and set up a bitmask covering the basic
+    // unit of repetition (i.e. a word with the bottom d bits set). Also, in all
+    // of these cases the N bit of the output will be zero.
+    clz_a = CountLeadingZeros(a, kXRegSize);
+    int clz_c = CountLeadingZeros(c, kXRegSize);
+    d = clz_a - clz_c;
+    mask = ((UINT64_C(1) << d) - 1);
+    out_n = 0;
+  } else {
+    // Handle degenerate cases.
+    //
+    // If any of those 'find lowest set bit' operations didn't find a set bit at
+    // all, then the word will have been zero thereafter, so in particular the
+    // last lowest_set_bit operation will have returned zero. So we can test for
+    // all the special case conditions in one go by seeing if c is zero.
+    if (a == 0) {
+      // The input was zero (or all 1 bits, which will come to here too after we
+      // inverted it at the start of the function), for which we just return
+      // false.
+      return false;
+    } else {
+      // Otherwise, if c was zero but a was not, then there's just one stretch
+      // of set bits in our word, meaning that we have the trivial case of
+      // d == 64 and only one 'repetition'. Set up all the same variables as in
+      // the general case above, and set the N bit in the output.
+      clz_a = CountLeadingZeros(a, kXRegSize);
+      d = 64;
+      mask = ~UINT64_C(0);
+      out_n = 1;
+    }
+  }
+
+  // If the repeat period d is not a power of two, it can't be encoded.
+  if (!IsPowerOf2(d)) {
+    return false;
+  }
+
+  if (((b - a) & ~mask) != 0) {
+    // If the bit stretch (b - a) does not fit within the mask derived from the
+    // repeat period, then fail.
+    return false;
+  }
+
+  // The only possible option is b - a repeated every d bits. Now we're going to
+  // actually construct the valid logical immediate derived from that
+  // specification, and see if it equals our original input.
+  //
+  // To repeat a value every d bits, we multiply it by a number of the form
+  // (1 + 2^d + 2^(2d) + ...), i.e. 0x0001000100010001 or similar. These can
+  // be derived using a table lookup on CLZ(d).
+  static const uint64_t multipliers[] = {
+      0x0000000000000001UL,
+      0x0000000100000001UL,
+      0x0001000100010001UL,
+      0x0101010101010101UL,
+      0x1111111111111111UL,
+      0x5555555555555555UL,
+  };
+  uint64_t multiplier = multipliers[CountLeadingZeros(d, kXRegSize) - 57];
+  uint64_t candidate = (b - a) * multiplier;
+
+  if (value != candidate) {
+    // The candidate pattern doesn't match our input value, so fail.
+    return false;
+  }
+
+  // We have a match! This is a valid logical immediate, so now we have to
+  // construct the bits and pieces of the instruction encoding that generates
+  // it.
+
+  // Count the set bits in our basic stretch. The special case of clz(0) == -1
+  // makes the answer come out right for stretches that reach the very top of
+  // the word (e.g. numbers like 0xffffc00000000000).
+  int clz_b = (b == 0) ? -1 : CountLeadingZeros(b, kXRegSize);
+  int s = clz_a - clz_b;
+
+  // Decide how many bits to rotate right by, to put the low bit of that basic
+  // stretch in position a.
+  int r;
+  if (negate) {
+    // If we inverted the input right at the start of this function, here's
+    // where we compensate: the number of set bits becomes the number of clear
+    // bits, and the rotation count is based on position b rather than position
+    // a (since b is the location of the 'lowest' 1 bit after inversion).
+    s = d - s;
+    r = (clz_b + 1) & (d - 1);
+  } else {
+    r = (clz_a + 1) & (d - 1);
+  }
+
+  // Now we're done, except for having to encode the S output in such a way that
+  // it gives both the number of set bits and the length of the repeated
+  // segment. The s field is encoded like this:
+  //
+  //     imms    size        S
+  //    ssssss    64    UInt(ssssss)
+  //    0sssss    32    UInt(sssss)
+  //    10ssss    16    UInt(ssss)
+  //    110sss     8    UInt(sss)
+  //    1110ss     4    UInt(ss)
+  //    11110s     2    UInt(s)
+  //
+  // So we 'or' (2 * -d) with our computed s to form imms.
+  if ((n != NULL) || (imm_s != NULL) || (imm_r != NULL)) {
+    *n = out_n;
+    *imm_s = ((2 * -d) | (s - 1)) & 0x3f;
+    *imm_r = r;
+  }
+
+  return true;
+}
+
+static inline bool IsIntN(unsigned n, int64_t x) {
+  if (n == 64) return true;
+  int64_t limit = INT64_C(1) << (n - 1);
+  return (-limit <= x) && (x < limit);
+}
+
+static inline bool IsUintN(unsigned n, int64_t x) {
+  // Convert to an unsigned integer to avoid implementation-defined behavior.
+  return !(static_cast<uint64_t>(x) >> n);
+}
+
+// clang-format off
+#define INT_1_TO_32_LIST(V)                                                    \
+V(1)  V(2)  V(3)  V(4)  V(5)  V(6)  V(7)  V(8)                                 \
+V(9)  V(10) V(11) V(12) V(13) V(14) V(15) V(16)                                \
+V(17) V(18) V(19) V(20) V(21) V(22) V(23) V(24)                                \
+V(25) V(26) V(27) V(28) V(29) V(30) V(31) V(32)
+
+#define INT_33_TO_63_LIST(V)                                                   \
+V(33) V(34) V(35) V(36) V(37) V(38) V(39) V(40)                                \
+V(41) V(42) V(43) V(44) V(45) V(46) V(47) V(48)                                \
+V(49) V(50) V(51) V(52) V(53) V(54) V(55) V(56)                                \
+V(57) V(58) V(59) V(60) V(61) V(62) V(63)
+
+#define INT_1_TO_63_LIST(V) INT_1_TO_32_LIST(V) INT_33_TO_63_LIST(V)
+
+// clang-format on
+
+#define DECLARE_IS_INT_N(N)                                       \
+  static inline bool IsInt##N(int64_t x) { return IsIntN(N, x); }
+
+#define DECLARE_IS_UINT_N(N)                                        \
+  static inline bool IsUint##N(int64_t x) { return IsUintN(N, x); }
+
+INT_1_TO_63_LIST(DECLARE_IS_INT_N)
+INT_1_TO_63_LIST(DECLARE_IS_UINT_N)
+
+#undef DECLARE_IS_INT_N
+#undef DECLARE_IS_UINT_N
+
+private:
+
+template <typename V>
+static inline bool IsPowerOf2(V value) {
+  return (value != 0) && ((value & (value - 1)) == 0);
+}
+
+// Some compilers dislike negating unsigned integers,
+// so we provide an equivalent.
+template <typename T>
+static inline T UnsignedNegate(T value) {
+  static_assert(std::is_unsigned<T>::value);
+  return ~value + 1;
+}
+
+static inline uint64_t LowestSetBit(uint64_t value) {
+  return value & UnsignedNegate(value);
+}
+
+template <typename V>
+static inline int CountLeadingZeros(V value, int width = (sizeof(V) * 8)) {
+#if COMPILER_HAS_BUILTIN_CLZ
+  if (width == 32) {
+    return (value == 0) ? 32 : __builtin_clz(static_cast<unsigned>(value));
+  } else if (width == 64) {
+    return (value == 0) ? 64 : __builtin_clzll(value);
+  }
+#endif
+  return CountLeadingZerosFallBack(value, width);
+}
+
+static inline int CountLeadingZerosFallBack(uint64_t value, int width) {
+  LOGMAN_THROW_A_FMT(IsPowerOf2(width) && (width <= 64), "Invalid width");
+  if (value == 0) {
+    return width;
+  }
+  int count = 0;
+  value = value << (64 - width);
+  if ((value & UINT64_C(0xffffffff00000000)) == 0) {
+    count += 32;
+    value = value << 32;
+  }
+  if ((value & UINT64_C(0xffff000000000000)) == 0) {
+    count += 16;
+    value = value << 16;
+  }
+  if ((value & UINT64_C(0xff00000000000000)) == 0) {
+    count += 8;
+    value = value << 8;
+  }
+  if ((value & UINT64_C(0xf000000000000000)) == 0) {
+    count += 4;
+    value = value << 4;
+  }
+  if ((value & UINT64_C(0xc000000000000000)) == 0) {
+    count += 2;
+    value = value << 2;
+  }
+  if ((value & UINT64_C(0x8000000000000000)) == 0) {
+    count += 1;
+  }
+  count += (value == 0);
+  return count;
+}
+
+public:
@@ -20,8 +20,7 @@ the coding style of LLVM. It can also be installed as a pre-commit git hook to
 check the coding style before submitting it. The canonical source of this script
 is in the LLVM source tree under llvm/utils/git.

-For C/C++ code it uses clang-format and for Python code it uses darker (which
-in turn invokes black).
+For C/C++ code it uses clang-format.

 You can learn more about the LLVM coding style on llvm.org:
 https://llvm.org/docs/CodingStandards.html
@@ -31,8 +30,8 @@ directory:

 ln -s $(pwd)/llvm/utils/git/code-format-helper.py .git/hooks/pre-commit

-You can control the exact path to clang-format or darker with the following
-environment variables: $CLANG_FORMAT_PATH and $DARKER_FORMAT_PATH.
+You can control the exact path to clang-format with the following
+environment variable: $CLANG_FORMAT_PATH.
 """


@@ -173,6 +172,12 @@ class ClangFormatHelper(FormatHelper):
    name = "clang-format"
    friendly_name = "C/C++ code formatter"

+    @property
+    def cformat_wrapper_path(self) -> str:
+        relpath = "../../Scripts/clang-format.py"
+        curpath = os.path.dirname(os.path.abspath(__file__))
+        return os.path.abspath(os.path.normpath(os.path.join(curpath, relpath)))
+
    @property
    def instructions(self) -> str:
        return " ".join(self.cf_cmd)
@@ -210,7 +215,11 @@ class ClangFormatHelper(FormatHelper):
        if not cpp_files:
            return None

-        cf_cmd = [self.clang_fmt_path, "--diff"]
+        cf_cmd = [
+            self.clang_fmt_path,
+            f"--binary={self.cformat_wrapper_path}",
+            "--diff",
+        ]

        if args.start_rev and args.end_rev:
            cf_cmd.append(args.start_rev)
@@ -235,74 +244,7 @@ class ClangFormatHelper(FormatHelper):
        else:
            return None

-
-class DarkerFormatHelper(FormatHelper):
-    name = "darker"
-    friendly_name = "Python code formatter"
-
-    @property
-    def instructions(self) -> str:
-        return " ".join(self.darker_cmd)
-
-    def filter_changed_files(self, changed_files: List[str]) -> List[str]:
-        filtered_files = []
-        for path in changed_files:
-            name, ext = os.path.splitext(path)
-            if ext == ".py":
-                filtered_files.append(path)
-
-        return filtered_files
-
-    @property
-    def darker_fmt_path(self) -> str:
-        if "DARKER_FORMAT_PATH" in os.environ:
-            return os.environ["DARKER_FORMAT_PATH"]
-        return "darker"
-
-    def has_tool(self) -> bool:
-        cmd = [self.darker_fmt_path, "--version"]
-        proc = None
-        try:
-            proc = subprocess.run(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
-        except:
-            return False
-        return proc.returncode == 0
-
-    def format_run(self, changed_files: List[str], args: FormatArgs) -> Optional[str]:
-        py_files = self.filter_changed_files(changed_files)
-        if not py_files:
-            return None
-        darker_cmd = [
-            self.darker_fmt_path,
-            "--check",
-            "--diff",
-        ]
-        if args.start_rev and args.end_rev:
-            darker_cmd += ["-r", f"{args.start_rev}...{args.end_rev}"]
-        darker_cmd += py_files
-        if args.verbose:
-            print(f"Running: {' '.join(darker_cmd)}")
-        self.darker_cmd = darker_cmd
-        proc = subprocess.run(
-            darker_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE
-        )
-        if args.verbose:
-            sys.stdout.write(proc.stderr.decode("utf-8"))
-
-        if proc.returncode != 0:
-            # formatting needed, or the command otherwise failed
-            if args.verbose:
-                print(f"error: {self.name} exited with code {proc.returncode}")
-                # Print the diff in the log so that it is viewable there
-                print(proc.stdout.decode("utf-8"))
-            return proc.stdout.decode("utf-8")
-        else:
-            sys.stdout.write(proc.stdout.decode("utf-8"))
-            return None
-
-
-ALL_FORMATTERS = (DarkerFormatHelper(), ClangFormatHelper())
-
+ALL_FORMATTERS = [ClangFormatHelper()]

 def hook_main():
    # fill out args
@@ -24,27 +24,6 @@ include(CheckCXXCompilerFlag)
 include(CheckIncludeFileCXX)
 include(CheckCXXSourceCompiles)

-set(CMAKE_REQUIRED_FLAGS "-std=c++11 -Wattributes -Werror=attributes")
-check_cxx_source_compiles(
-  "
-  __attribute__((preserve_all))
-  int Testy(int a, int b, int c, int d, int e, int f) {
-  return a + b + c + d + e + f;
-  }
-  int main() {
-  return Testy(0, 1, 2, 3, 4, 5);
-  }"
-  HAS_CLANG_PRESERVE_ALL)
-unset(CMAKE_REQUIRED_FLAGS)
-if (HAS_CLANG_PRESERVE_ALL)
-  if (MINGW_BUILD)
-    message(STATUS "Ignoring broken clang::preserve_all support")
-    set(HAS_CLANG_PRESERVE_ALL FALSE)
-  else()
-    message(STATUS "Has clang::preserve_all")
-  endif()
-endif ()
-
 if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
    # Useful to have for freestanding libFEXCore
    add_subdirectory(External/vixl/)
@@ -148,9 +148,8 @@ def print_man_options(options):
            if (value_type == "strenum"):
                Enums = op_vals["Enums"]
                output_man.write("\\fBAvailable Options:\\fR\n")
-                for enum_op_key, enum_op_vals in Enums.items():
-                    output_man.write("{}, ".format(enum_op_vals))
-                output_man.write("\n")
+                output_man.write(", ".join(f"{enum_op_val}" for [_, enum_op_val] in Enums.items()))
+                output_man.write("\n.sp\n")

    output_man.write(".El\n")

@@ -179,9 +178,8 @@ def print_man_environment(options):
            if (value_type == "strenum"):
                Enums = op_vals["Enums"]
                output_man.write("\\fBAvailable Options:\\fR\n")
-                for enum_op_key, enum_op_vals in Enums.items():
-                    output_man.write("{}, ".format(enum_op_vals))
-                output_man.write("\n")
+                output_man.write(", ".join(f"{enum_op_val}" for [_, enum_op_val] in Enums.items()))
+                output_man.write("\n.sp\n")

    print_man_environment_tail()
    output_man.write(".El\n")
@@ -2,6 +2,7 @@
 import json
 import sys
 from dataclasses import dataclass, field
+import textwrap

 def ExitError(msg):
    print(msg)
@@ -53,8 +54,10 @@ class OpDefinition:
    SSAArgNum: int
    NonSSAArgNum: int
    DynamicDispatch: bool
+    LoweredX87: bool
    JITDispatch: bool
    JITDispatchOverride: str
+    TiedSource: int
    Arguments: list
    EmitValidation: list
    Desc: list
@@ -75,8 +78,10 @@ class OpDefinition:
        self.SSAArgNum = 0
        self.NonSSAArgNum = 0
        self.DynamicDispatch = False
+        self.LoweredX87 = False
        self.JITDispatch = True
        self.JITDispatchOverride = None
+        self.TiedSource = -1
        self.Arguments = []
        self.EmitValidation = []
        self.Desc = []
@@ -202,7 +207,7 @@ def parse_ops(ops):
                        (OpArg.Type == "GPR" or
                        OpArg.Type == "GPRPair" or
                        OpArg.Type == "FPR")):
-                        OpDef.EmitValidation.append("GetOpRegClass({}) == InvalidClass || WalkFindRegClass({}) == {}Class".format(NameWithPrefix, NameWithPrefix, OpArg.Type))
+                        OpDef.EmitValidation.append(f"GetOpRegClass({ArgName}) == InvalidClass || WalkFindRegClass({ArgName}) == {OpArg.Type}Class")

                    OpArg.Name = ArgName
                    OpArg.NameWithPrefix = NameWithPrefix
@@ -248,17 +253,23 @@ def parse_ops(ops):
            if "JITDispatchOverride" in op_val:
                OpDef.JITDispatchOverride = op_val["JITDispatchOverride"]

+            if "X87" in op_val:
+                OpDef.LoweredX87 = op_val["X87"]
+
+                # X87 implies !JITDispatch
+                assert("JITDispatch" not in op_val)
+                OpDef.JITDispatch = False
+
+            if "TiedSource" in op_val:
+                OpDef.TiedSource = op_val["TiedSource"]
+
            # Do some fixups of the data here
            if len(OpDef.EmitValidation) != 0:
                for i in range(len(OpDef.EmitValidation)):
                    # Patch up all the argument names
                    for Arg in OpDef.Arguments:
-                        if Arg.Temporary:
-                            # Temporary ops just replace all instances no prefix variant
-                            OpDef.EmitValidation[i] = OpDef.EmitValidation[i].replace(Arg.NameWithPrefix, Arg.Name)
-                        else:
-                            # All other ops replace $ with _ variant for argument passed in
-                            OpDef.EmitValidation[i] = OpDef.EmitValidation[i].replace(Arg.NameWithPrefix, "_{}".format(Arg.Name))
+                        # Temporary ops just replace all instances no prefix variant
+                        OpDef.EmitValidation[i] = OpDef.EmitValidation[i].replace(Arg.NameWithPrefix, Arg.Name)

            #OpDef.print()

@@ -363,25 +374,28 @@ def print_ir_sizes():
        if op.Name == "Last":
            output_file.write("\t-1ULL,\n")
        else:
-            output_file.write("\tsizeof(IROp_{}),\n".format(op.Name))
+            output_file.write(f"\tsizeof(IROp_{op.Name}),\n")

-    output_file.write("};\n\n")
+    output_file.write(textwrap.dedent("""
+    };

-    output_file.write("// Make sure our array maps directly to the IROps enum\n")
-    output_file.write("static_assert(IRSizes[IROps::OP_LAST] == -1ULL);\n\n")
+    // Make sure our array maps directly to the IROps enum
+    static_assert(IRSizes[IROps::OP_LAST] == -1ULL);

-    output_file.write("[[maybe_unused, nodiscard]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }\n\n")
+    [[maybe_unused, nodiscard]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }
+    [[nodiscard, gnu::const, gnu::visibility("default")]] std::string_view const& GetName(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] uint8_t GetArgs(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] uint8_t GetRAArgs(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool HasSideEffects(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool ImplicitFlagClobber(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool GetHasDest(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] bool LoweredX87(IROps Op);
+    [[nodiscard, gnu::const, gnu::visibility("default")]] int8_t TiedSource(IROps Op);

-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] std::string_view const& GetName(IROps Op);\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetArgs(IROps Op);\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] uint8_t GetRAArgs(IROps Op);\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool HasSideEffects(IROps Op);\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool ImplicitFlagClobber(IROps Op);\n")
-    output_file.write("[[nodiscard, gnu::const, gnu::visibility(\"default\")]] bool GetHasDest(IROps Op);\n")
-
-    output_file.write("#undef IROP_SIZES\n")
-    output_file.write("#endif\n\n")
+    #undef IROP_SIZES
+    #endif
+    """))

 def print_ir_reg_classes():
    output_file.write("#ifdef IROP_REG_CLASSES_IMPL\n")
@@ -471,16 +485,27 @@ def print_ir_getraargs():
 def print_ir_hassideeffects():
    output_file.write("#ifdef IROP_HASSIDEEFFECTS_IMPL\n")

-    for array, prop in [("SideEffects", "HasSideEffects"),
-                        ("ImplicitFlagClobbers", "ImplicitFlagClobber")]:
-        output_file.write(f"constexpr std::array<uint8_t, OP_LAST + 1> {array} = {{\n")
+    for prop, T in [
+        ("HasSideEffects", "bool"),
+        ("ImplicitFlagClobber", "bool"),
+        ("LoweredX87", "bool"),
+        ("TiedSource", "int8_t"),
+    ]:
+        output_file.write(
+            f"constexpr std::array<{'uint8_t' if T == 'bool' else T}, OP_LAST + 1> {prop}_ = {{\n"
+        )
        for op in IROps:
-            output_file.write("\t{},\n".format(("true" if getattr(op, prop) else "false")))
+            if T == "bool":
+                output_file.write(
+                    "\t{},\n".format(("true" if getattr(op, prop) else "false"))
+                )
+            else:
+                output_file.write(f"\t{getattr(op, prop)},\n")

        output_file.write("};\n\n")

-        output_file.write(f"bool {prop}(IROps Op) {{\n")
-        output_file.write(f"  return {array}[Op];\n")
+        output_file.write(f"{T} {prop}(IROps Op) {{\n")
+        output_file.write(f"  return {prop}_[Op];\n")
        output_file.write("}\n")

    output_file.write("#undef IROP_HASSIDEEFFECTS_IMPL\n")
@@ -520,14 +545,20 @@ def print_ir_arg_printer():
            output_file.write("\t*out << \" \";\n")

            SSAArgNum = 0
+            FirstArg = True
            for i in range(0, len(op.Arguments)):
                arg = op.Arguments[i]
-                LastArg = len(op.Arguments) - i - 1 == 0

+                # No point printing temporaries that we can't recover
                if arg.Temporary:
-                    # Temporary that we can't recover
-                    output_file.write("\t*out << \"{}:Tmp:{}\";\n".format(arg.Type, arg.Name))
-                elif arg.IsSSA:
+                    continue
+
+                if FirstArg:
+                    FirstArg = False
+                else:
+                    output_file.write('\t*out << ", ";\n')
+
+                if arg.IsSSA:
                    # SSA value
                    output_file.write("\tPrintArg(out, IR, Op->Header.Args[{}], RAData);\n".format(SSAArgNum))
                    SSAArgNum = SSAArgNum + 1
@@ -535,9 +566,6 @@ def print_ir_arg_printer():
                    # User defined op that is stored
                    output_file.write("\tPrintArg(out, IR, Op->{});\n".format(arg.Name))

-                if not LastArg:
-                    output_file.write("\t*out << \", \";\n")
-
        output_file.write("break;\n")
        output_file.write("}\n")

@@ -636,11 +664,11 @@ def print_ir_allocator_helpers():
                    output_file.write("{} {}".format(CType, arg.Name));
                elif arg.IsSSA:
                    # SSA value
-                    output_file.write("OrderedNode *_{}".format(arg.Name))
+                    output_file.write("OrderedNode *{}".format(arg.Name))
                else:
                    # User defined op that is stored
                    CType = IRTypesToCXX[arg.Type].CXXName
-                    output_file.write("{} _{}".format(CType, arg.Name));
+                    output_file.write("{} {}".format(CType, arg.Name));

                if arg.DefaultInitializer != None:
                    output_file.write(" = {}".format(arg.DefaultInitializer))
@@ -654,23 +682,28 @@ def print_ir_allocator_helpers():
            if op.ImplicitFlagClobber:
                output_file.write("\t\tSaveNZCV(IROps::OP_{});".format(op.Name.upper()))

-            output_file.write("\t\tauto Op = AllocateOp<IROp_{}, IROps::OP_{}>();\n".format(op.Name, op.Name.upper()))
+            # We gather the "has x87?" flag as we go. This saves the user from
+            # having to keep track of whether they emitted any x87.
+            if op.LoweredX87:
+                output_file.write("\t\tRecordX87Use();\n")
+
+            output_file.write("\t\tauto _Op = AllocateOp<IROp_{}, IROps::OP_{}>();\n".format(op.Name, op.Name.upper()))

            if op.SSAArgNum != 0:
                output_file.write("\t\tauto ListDataBegin = DualListData.ListBegin();\n")
                for arg in op.Arguments:
                    if arg.IsSSA:
-                        output_file.write("\t\tOp.first->{} = _{}->Wrapped(ListDataBegin);\n".format(arg.Name, arg.Name))
+                        output_file.write("\t\t_Op.first->{} = {}->Wrapped(ListDataBegin);\n".format(arg.Name, arg.Name))

            if op.SSAArgNum != 0:
                for arg in op.Arguments:
                    if arg.IsSSA:
-                        output_file.write("\t\t_{}->AddUse();\n".format(arg.Name))
+                        output_file.write("\t\t{}->AddUse();\n".format(arg.Name))

            if len(op.Arguments) != 0:
                for arg in op.Arguments:
                    if not arg.Temporary and not arg.IsSSA:
-                        output_file.write("\t\tOp.first->{} = _{};\n".format(arg.Name, arg.Name))
+                        output_file.write("\t\t_Op.first->{} = {};\n".format(arg.Name, arg.Name))

            if (op.HasDest):
                # We can only infer a size if we have arguments
@@ -680,22 +713,22 @@ def print_ir_allocator_helpers():
                    if len(op.Arguments) != 0:
                        for arg in op.Arguments:
                            if arg.IsSSA:
-                                output_file.write("\t\tuint8_t Size{} = GetOpSize(_{});\n".format(arg.Name, arg.Name))
+                                output_file.write("\t\tuint8_t Size{} = GetOpSize({});\n".format(arg.Name, arg.Name))
                        for arg in op.Arguments:
                            if arg.IsSSA:
                                output_file.write("\t\tInferSize = std::max(InferSize, Size{});\n".format(arg.Name))

-                    output_file.write("\t\tOp.first->Header.Size = InferSize;\n")
+                    output_file.write("\t\t_Op.first->Header.Size = InferSize;\n")

            # Some ops without a destination still need an operating size
            # Effectively reusing the destination size value for operation size
            if op.DestSize != None:
-                output_file.write("\t\tOp.first->Header.Size = {};\n".format(op.DestSize))
+                output_file.write("\t\t_Op.first->Header.Size = {};\n".format(op.DestSize))

            if op.NumElements == None:
-                output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / ({});\n".format(1))
+                output_file.write("\t\t_Op.first->Header.ElementSize = _Op.first->Header.Size / ({});\n".format(1))
            else:
-                output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / ({});\n".format(op.NumElements))
+                output_file.write("\t\t_Op.first->Header.ElementSize = _Op.first->Header.Size / ({});\n".format(op.NumElements))

            # Insert validation here
            if op.EmitValidation != None:
@@ -706,58 +739,12 @@ def print_ir_allocator_helpers():
                    output_file.write("\tLOGMAN_THROW_A_FMT({}, \"{}\");\n".format(Validation, Sanitized))
                output_file.write("\t\t#endif\n")

-            output_file.write("\t\treturn Op;\n")
+            output_file.write("\t\treturn _Op;\n")
            output_file.write("\t}\n\n")

    output_file.write("#undef IROP_ALLOCATE_HELPERS\n")
    output_file.write("#endif\n")

-def print_ir_parser_switch_helper():
-    output_file.write("#ifdef IROP_PARSER_SWITCH_HELPERS\n")
-    for op in IROps:
-        if op.Name != "Last" and op.SwitchGen:
-            output_file.write("\tcase FEXCore::IR::IROps::OP_%s: {\n" % (op.Name.upper()))
-
-            for i in range(0, len(op.Arguments)):
-                arg = op.Arguments[i]
-                LastArg = len(op.Arguments) - i - 1 == 0
-
-                if arg.Temporary:
-                    CType = IRTypesToCXX[arg.Type].CXXName
-                    output_file.write("\t\tauto arg{} = DecodeValue<{}>(Def.Args[{}]);\n".format(i, CType, i))
-                    output_file.write("\t\tif (!CheckPrintErrorArg(Def, arg{}.first, {})) return false;\n".format(i, i))
-                elif arg.IsSSA:
-                    # SSA value
-                    output_file.write("\t\tauto arg{} = DecodeValue<OrderedNode*>(Def.Args[{}]);\n".format(i, i))
-                    output_file.write("\t\tif (!CheckPrintErrorArg(Def, arg{}.first, {})) return false;\n".format(i, i))
-                else:
-                    # User defined op that is stored
-                    CType = IRTypesToCXX[arg.Type].CXXName
-                    output_file.write("\t\tauto arg{} = DecodeValue<{}>(Def.Args[{}]);\n".format(i, CType, i))
-                    output_file.write("\t\tif (!CheckPrintErrorArg(Def, arg{}.first, {})) return false;\n".format(i, i))
-
-            output_file.write("\t\tDef.Node = _{}(\n".format(op.Name))
-
-            for i in range(0, len(op.Arguments)):
-                arg = op.Arguments[i]
-                LastArg = len(op.Arguments) - i - 1 == 0
-                output_file.write("\t\t\targ{}.second".format(i))
-                if not LastArg:
-                    output_file.write(",\n")
-                else:
-                    output_file.write("\n")
-
-            output_file.write("\t\t);\n")
-
-            output_file.write("\t\tSSANameMapper[Def.Definition] = Def.Node;\n")
-
-            output_file.write("\t\tbreak;\n")
-            output_file.write("\t}\n")
-
-
-    output_file.write("#undef IROP_PARSER_SWITCH_HELPERS\n")
-    output_file.write("#endif\n")
-
 def print_ir_dispatcher_defs():
    output_dispatch_file.write("#ifdef IROP_DISPATCH_DEFS\n")
    for op in IROps:
@@ -816,7 +803,6 @@ print_ir_hassideeffects()
 print_ir_gethasdest()
 print_ir_arg_printer()
 print_ir_allocator_helpers()
-print_ir_parser_switch_helper()

 output_file.close()

@@ -67,7 +67,6 @@ set (SRCS
  Common/SoftFloat-3e/s_approxRecipSqrt32_1.c
  Common/SoftFloat-3e/s_approxRecipSqrt_1Ks.c
  Common/SoftFloat-3e/softfloat_raiseFlags.c
-  Common/SoftFloat-3e/softfloat_state.c
  Common/SoftFloat-3e/f64_to_extF80.c
  Common/SoftFloat-3e/s_commonNaNToExtF80UI.c
  Common/SoftFloat-3e/s_normSubnormalF64Sig.c
@@ -91,10 +90,10 @@ set (SRCS
  Interface/Core/CPUBackend.cpp
  Interface/Core/CPUID.cpp
  Interface/Core/Frontend.cpp
-  Interface/Core/HostFeatures.cpp
  Interface/Core/ObjectCache/JobHandling.cpp
  Interface/Core/ObjectCache/NamedRegionObjectHandler.cpp
  Interface/Core/ObjectCache/ObjectCacheService.cpp
+  Interface/Core/OpcodeDispatcher/AVX_128.cpp
  Interface/Core/OpcodeDispatcher/Crypto.cpp
  Interface/Core/OpcodeDispatcher/Flags.cpp
  Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -112,7 +111,6 @@ set (SRCS
  Interface/Core/JIT/Arm64/BranchOps.cpp
  Interface/Core/JIT/Arm64/ConversionOps.cpp
  Interface/Core/JIT/Arm64/EncryptionOps.cpp
-  Interface/Core/JIT/Arm64/FlagOps.cpp
  Interface/Core/JIT/Arm64/MemoryOps.cpp
  Interface/Core/JIT/Arm64/MiscOps.cpp
  Interface/Core/JIT/Arm64/MoveOps.cpp
@@ -134,22 +132,16 @@ set (SRCS
  Interface/GDBJIT/GDBJIT.cpp
  Interface/IR/AOTIR.cpp
  Interface/IR/IRDumper.cpp
-  Interface/IR/IRParser.cpp
  Interface/IR/IREmitter.cpp
  Interface/IR/PassManager.cpp
  Interface/IR/Passes/ConstProp.cpp
-  Interface/IR/Passes/DeadCodeElimination.cpp
-  Interface/IR/Passes/DeadContextStoreElimination.cpp
-  Interface/IR/Passes/IRCompaction.cpp
  Interface/IR/Passes/IRDumperPass.cpp
  Interface/IR/Passes/IRValidation.cpp
  Interface/IR/Passes/RAValidation.cpp
-  Interface/IR/Passes/LongDivideRemovalPass.cpp
-  Interface/IR/Passes/ValueDominanceValidation.cpp
  Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
  Interface/IR/Passes/DeadStoreElimination.cpp
  Interface/IR/Passes/RegisterAllocationPass.cpp
-  Interface/IR/Passes/InlineCallOptimization.cpp
+  Interface/IR/Passes/x87StackOptimizationPass.cpp
  Utils/Telemetry.cpp
  Utils/Threads.cpp
  Utils/Profiler.cpp
@@ -166,7 +158,7 @@ if (ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
    Utils/AllocatorOverride.cpp)
 endif()

-set(DEFINES -DTHREAD_LOCAL=_Thread_local -DJIT_ARM64)
+set(DEFINES -DJIT_ARM64)

 if (_M_X86_64)
  list(APPEND DEFINES -D_M_X86_64=1)
@@ -176,11 +168,6 @@ if (_M_ARM_64)
  list(APPEND DEFINES -D_M_ARM_64=1)
 endif()

-if (ENABLE_VIXL_SIMULATOR)
-  # We can run the simulator on both x86-64 or AArch64 hosts
-  list(APPEND DEFINES -DVIXL_SIMULATOR=1 -DVIXL_INCLUDE_SIMULATOR_AARCH64=1)
-endif()
-
 if (ENABLE_VIXL_DISASSEMBLER)
  list(APPEND DEFINES -DVIXL_DISASSEMBLER=1)
 endif()
@@ -194,7 +181,7 @@ endif()
 # Some defines for the softfloat library
 list(APPEND DEFINES "-DSOFTFLOAT_BUILTIN_CLZ")

-set (LIBS fmt::fmt vixl xxHash::xxhash FEXHeaderUtils)
+set (LIBS fmt::fmt vixl xxHash::xxhash FEXHeaderUtils CodeEmitter)

 if (NOT MINGW_BUILD)
  list (APPEND LIBS dl)
@@ -373,16 +360,6 @@ function(AddLibrary Name Type)
  target_link_libraries(${Name} FEXCore_Base)
  target_compile_options(${Name} PRIVATE ${FEX_TUNE_COMPILE_FLAGS})
  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
-  if (MINGW_BUILD)
-    # Mingw build isn't building a linux shared library, so it can't have a SONAME.
-    set_target_properties(${Name} PROPERTIES NO_SONAME ON)
-    # Change the suffixes otherwise cmake continues using .a and .so
-    if (${Type} STREQUAL SHARED)
-      set_target_properties(${Name} PROPERTIES SUFFIX ".dll")
-    elseif(${Type} STREQUAL STATIC)
-      set_target_properties(${Name} PROPERTIES SUFFIX ".lib")
-    endif()
-  endif()

  AddDefaultOptionsToTarget(${Name})
 endfunction()
@@ -20,12 +20,12 @@ struct BitSet final {

  ElementType* Memory;
  void Allocate(size_t Elements) {
-    size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
+    size_t AllocateSize = ToBytes(Elements);
    LOGMAN_THROW_AA_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
    Memory = static_cast<ElementType*>(FEXCore::Allocator::malloc(AllocateSize));
  }
  void Realloc(size_t Elements) {
-    size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
+    size_t AllocateSize = ToBytes(Elements);
    LOGMAN_THROW_AA_FMT((AllocateSize * MinimumSize) >= Elements, "Fail");
    Memory = static_cast<ElementType*>(FEXCore::Allocator::realloc(Memory, AllocateSize));
  }
@@ -43,10 +43,13 @@ struct BitSet final {
    Memory[Element / MinimumSizeBits] &= (1ULL << (Element % MinimumSizeBits));
  }
  void MemClear(size_t Elements) {
-    memset(Memory, 0, AlignUp(Elements / MinimumSizeBits, MinimumSizeBits));
+    memset(Memory, 0, ToBytes(Elements));
  }
  void MemSet(size_t Elements) {
-    memset(Memory, 0xFF, AlignUp(Elements / MinimumSizeBits, MinimumSizeBits));
+    memset(Memory, 0xFF, ToBytes(Elements));
+  }
+  uint32_t ToBytes(size_t Elements) {
+    return AlignUp(Elements, MinimumSizeBits) / MinimumSize;
  }

  // This very explicitly doesn't let you take an address
@@ -41,7 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b )
+extFloat80_t extF80_add( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -53,7 +53,7 @@ extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b )
    bool signB;
    extFloat80_t
        (*magsFuncPtr)(
-            uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+            struct softfloat_state *, uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );

    uA.f = a;
    uiA64 = uA.s.signExp;
@@ -65,6 +65,6 @@ extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b )
    signB = signExtF80UI64( uiB64 );
    magsFuncPtr =
        (signA == signB) ? softfloat_addMagsExtF80 : softfloat_subMagsExtF80;
-    return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+    return (*magsFuncPtr)( state, uiA64, uiA0, uiB64, uiB0, signA );
 }

@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b )
+extFloat80_t extF80_div( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -107,7 +107,7 @@ extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b )
    if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) {
        if ( ! sigB ) {
            if ( ! sigA ) goto invalid;
-            softfloat_raiseFlags( softfloat_flag_infinite );
+            softfloat_raiseFlags( state, softfloat_flag_infinite );
            goto infinity;
        }
        normExpSig = softfloat_normSubnormalExtF80Sig( sigB );
@@ -169,18 +169,18 @@ extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b )
    sigZExtra = (uint64_t) ((uint_fast64_t) q<<41);
    return
        softfloat_roundPackToExtF80(
-            signZ, expZ, sigZ, sigZExtra, extF80_roundingPrecision );
+            state, signZ, expZ, sigZ, sigZExtra, state->roundingPrecision );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 propagateNaN:
-    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, uiB64, uiB0 );
    uiZ64 = uiZ.v64;
    uiZ0  = uiZ.v0;
    goto uiZ;
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    uiZ64 = defaultNaNExtF80UI64;
    uiZ0  = defaultNaNExtF80UI0;
    goto uiZ;
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-bool extF80_eq( extFloat80_t a, extFloat80_t b )
+bool extF80_eq( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -62,7 +62,7 @@ bool extF80_eq( extFloat80_t a, extFloat80_t b )
               softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
            || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
        ) {
-            softfloat_raiseFlags( softfloat_flag_invalid );
+            softfloat_raiseFlags( state, softfloat_flag_invalid );
        }
        return false;
    }
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-bool extF80_lt( extFloat80_t a, extFloat80_t b )
+bool extF80_lt( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -59,7 +59,7 @@ bool extF80_lt( extFloat80_t a, extFloat80_t b )
    uiB64 = uB.s.signExp;
    uiB0  = uB.s.signif;
    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        return false;
    }
    signA = signExtF80UI64( uiA64 );
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b )
+extFloat80_t extF80_mul( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -125,11 +125,11 @@ extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b )
    }
    return
        softfloat_roundPackToExtF80(
-            signZ, expZ, sig128Z.v64, sig128Z.v0, extF80_roundingPrecision );
+            state, signZ, expZ, sig128Z.v64, sig128Z.v0, state->roundingPrecision );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 propagateNaN:
-    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, uiB64, uiB0 );
    uiZ64 = uiZ.v64;
    uiZ0  = uiZ.v0;
    goto uiZ;
@@ -137,7 +137,7 @@ extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b )
    *------------------------------------------------------------------------*/
 infArg:
    if ( ! magBits ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        uiZ64 = defaultNaNExtF80UI64;
        uiZ0  = defaultNaNExtF80UI0;
    } else {
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_rem( extFloat80_t a, extFloat80_t b )
+extFloat80_t extF80_rem( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -193,18 +193,18 @@ extFloat80_t extF80_rem( extFloat80_t a, extFloat80_t b )
    }
    return
        softfloat_normRoundPackToExtF80(
-            signRem, rem.v64 | rem.v0 ? expB + 32 : 0, rem.v64, rem.v0, 80 );
+            state, signRem, rem.v64 | rem.v0 ? expB + 32 : 0, rem.v64, rem.v0, 80 );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 propagateNaN:
-    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, uiB64, uiB0 );
    uiZ64 = uiZ.v64;
    uiZ0  = uiZ.v0;
    goto uiZ;
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    uiZ64 = defaultNaNExtF80UI64;
    uiZ0  = defaultNaNExtF80UI0;
    goto uiZ;
@@ -43,7 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
- extF80_roundToInt( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+ extF80_roundToInt( struct softfloat_state *state, extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64, signUI64;
@@ -80,7 +80,7 @@ extFloat80_t
    if ( 0x403E <= exp ) {
        if ( exp == 0x7FFF ) {
            if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
-                uiZ = softfloat_propagateNaNExtF80UI( uiA64, sigA, 0, 0 );
+                uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, sigA, 0, 0 );
                uiZ64 = uiZ.v64;
                sigZ  = uiZ.v0;
                goto uiZ;
@@ -93,7 +93,7 @@ extFloat80_t
        goto uiZ;
    }
    if ( exp <= 0x3FFE ) {
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( exact ) state->exceptionFlags |= softfloat_flag_inexact;
        switch ( roundingMode ) {
         case softfloat_round_near_even:
            if ( !(sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) break;
@@ -145,7 +145,7 @@ extFloat80_t
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) sigZ |= lastBitMask;
 #endif
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( exact ) state->exceptionFlags |= softfloat_flag_inexact;
    }
 uiZ:
    uZ.s.signExp = uiZ64;
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_sqrt( extFloat80_t a )
+extFloat80_t extF80_sqrt( struct softfloat_state *state, extFloat80_t a )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -74,7 +74,7 @@ extFloat80_t extF80_sqrt( extFloat80_t a )
    *------------------------------------------------------------------------*/
    if ( expA == 0x7FFF ) {
        if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
-            uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, 0, 0 );
+            uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, 0, 0 );
            uiZ64 = uiZ.v64;
            uiZ0  = uiZ.v0;
            goto uiZ;
@@ -155,11 +155,11 @@ extFloat80_t extF80_sqrt( extFloat80_t a )
    }
    return
        softfloat_roundPackToExtF80(
-            0, expZ, sigZ, sigZExtra, extF80_roundingPrecision );
+            state, 0, expZ, sigZ, sigZExtra, state->roundingPrecision );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    uiZ64 = defaultNaNExtF80UI64;
    uiZ0  = defaultNaNExtF80UI0;
    goto uiZ;
@@ -41,7 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b )
+extFloat80_t extF80_sub( struct softfloat_state *state, extFloat80_t a, extFloat80_t b )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -54,7 +54,7 @@ extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b )
 #if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
    extFloat80_t
        (*magsFuncPtr)(
-            uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+            struct softfloat_state *, uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
 #endif

    uA.f = a;
@@ -67,14 +67,14 @@ extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b )
    signB = signExtF80UI64( uiB64 );
 #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
    if ( signA == signB ) {
-        return softfloat_subMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+        return softfloat_subMagsExtF80( state, uiA64, uiA0, uiB64, uiB0, signA );
    } else {
-        return softfloat_addMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+        return softfloat_addMagsExtF80( state, uiA64, uiA0, uiB64, uiB0, signA );
    }
 #else
    magsFuncPtr =
        (signA == signB) ? softfloat_subMagsExtF80 : softfloat_addMagsExtF80;
-    return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+    return (*magsFuncPtr)( state, uiA64, uiA0, uiB64, uiB0, signA );
 #endif

 }
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-float128_t extF80_to_f128( extFloat80_t a )
+float128_t extF80_to_f128( struct softfloat_state *state, extFloat80_t a )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -61,7 +61,7 @@ float128_t extF80_to_f128( extFloat80_t a )
    exp = expExtF80UI64( uiA64 );
    frac = uiA0 & UINT64_C( 0x7FFFFFFFFFFFFFFF );
    if ( (exp == 0x7FFF) && frac ) {
-        softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN );
+        softfloat_extF80UIToCommonNaN( state, uiA64, uiA0, &commonNaN );
        uiZ = softfloat_commonNaNToF128UI( &commonNaN );
    } else {
        sign = signExtF80UI64( uiA64 );
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-float32_t extF80_to_f32( extFloat80_t a )
+float32_t extF80_to_f32( struct softfloat_state *state, extFloat80_t a )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -66,7 +66,7 @@ float32_t extF80_to_f32( extFloat80_t a )
    *------------------------------------------------------------------------*/
    if ( exp == 0x7FFF ) {
        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
-            softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            softfloat_extF80UIToCommonNaN( state, uiA64, uiA0, &commonNaN );
            uiZ = softfloat_commonNaNToF32UI( &commonNaN );
        } else {
            uiZ = packToF32UI( sign, 0xFF, 0 );
@@ -86,7 +86,7 @@ float32_t extF80_to_f32( extFloat80_t a )
    if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) {
        if ( exp < -0x1000 ) exp = -0x1000;
    }
-    return softfloat_roundPackToF32( sign, exp, sig32 );
+    return softfloat_roundPackToF32( state, sign, exp, sig32 );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 uiZ:
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-float64_t extF80_to_f64( extFloat80_t a )
+float64_t extF80_to_f64( struct softfloat_state *state, extFloat80_t a )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -72,7 +72,7 @@ float64_t extF80_to_f64( extFloat80_t a )
    *------------------------------------------------------------------------*/
    if ( exp == 0x7FFF ) {
        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
-            softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            softfloat_extF80UIToCommonNaN( state, uiA64, uiA0, &commonNaN );
            uiZ = softfloat_commonNaNToF64UI( &commonNaN );
        } else {
            uiZ = packToF64UI( sign, 0x7FF, 0 );
@@ -86,7 +86,7 @@ float64_t extF80_to_f64( extFloat80_t a )
    if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) {
        if ( exp < -0x1000 ) exp = -0x1000;
    }
-    return softfloat_roundPackToF64( sign, exp, sig );
+    return softfloat_roundPackToF64( state, sign, exp, sig );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 uiZ:
@@ -43,7 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 int_fast32_t
- extF80_to_i32( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+ extF80_to_i32( struct softfloat_state *state, extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -68,7 +68,7 @@ int_fast32_t
 #elif (i32_fromNaN == i32_fromNegOverflow)
        sign = 1;
 #else
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        return i32_fromNaN;
 #endif
    }
@@ -78,7 +78,7 @@ int_fast32_t
    shiftDist = 0x4032 - exp;
    if ( shiftDist <= 0 ) shiftDist = 1;
    sig = softfloat_shiftRightJam64( sig, shiftDist );
-    return softfloat_roundToI32( sign, sig, roundingMode, exact );
+    return softfloat_roundToI32( state, sign, sig, roundingMode, exact );

 }

@@ -43,7 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
- extF80_to_i64( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+ extF80_to_i64( struct softfloat_state *state, extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -68,7 +68,7 @@ int_fast64_t
        /*--------------------------------------------------------------------
        *--------------------------------------------------------------------*/
        if ( shiftDist ) {
-            softfloat_raiseFlags( softfloat_flag_invalid );
+            softfloat_raiseFlags( state, softfloat_flag_invalid );
            return
                (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
                    ? i64_fromNaN
@@ -84,7 +84,7 @@ int_fast64_t
        sig = sig64Extra.v;
        sigExtra = sig64Extra.extra;
    }
-    return softfloat_roundToI64( sign, sig, sigExtra, roundingMode, exact );
+    return softfloat_roundToI64( state, sign, sig, sigExtra, roundingMode, exact );

 }

@@ -43,7 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 uint_fast64_t
- extF80_to_ui64( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+ extF80_to_ui64( struct softfloat_state *state, extFloat80_t a, uint_fast8_t roundingMode, bool exact )
 {
    union { struct extFloat80M s; extFloat80_t f; } uA;
    uint_fast16_t uiA64;
@@ -65,7 +65,7 @@ uint_fast64_t
    *------------------------------------------------------------------------*/
    shiftDist = 0x403E - exp;
    if ( shiftDist < 0 ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        return
            (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
                ? ui64_fromNaN
@@ -79,7 +79,7 @@ uint_fast64_t
        sig = sig64Extra.v;
        sigExtra = sig64Extra.extra;
    }
-    return softfloat_roundToUI64( sign, sig, sigExtra, roundingMode, exact );
+    return softfloat_roundToUI64( state, sign, sig, sigExtra, roundingMode, exact );

 }

@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f128_to_extF80( float128_t a )
+extFloat80_t f128_to_extF80( struct softfloat_state *state, float128_t a )
 {
    union ui128_f128 uA;
    uint_fast64_t uiA64, uiA0;
@@ -70,7 +70,7 @@ extFloat80_t f128_to_extF80( float128_t a )
    *------------------------------------------------------------------------*/
    if ( exp == 0x7FFF ) {
        if ( frac64 | frac0 ) {
-            softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            softfloat_f128UIToCommonNaN( state, uiA64, uiA0, &commonNaN );
            uiZ = softfloat_commonNaNToExtF80UI( &commonNaN );
            uiZ64 = uiZ.v64;
            uiZ0  = uiZ.v0;
@@ -98,7 +98,7 @@ extFloat80_t f128_to_extF80( float128_t a )
    sig128 =
        softfloat_shortShiftLeft128(
            frac64 | UINT64_C( 0x0001000000000000 ), frac0, 15 );
-    return softfloat_roundPackToExtF80( sign, exp, sig128.v64, sig128.v0, 80 );
+    return softfloat_roundPackToExtF80( state, sign, exp, sig128.v64, sig128.v0, 80 );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 uiZ:
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f32_to_extF80( float32_t a )
+extFloat80_t f32_to_extF80( struct softfloat_state *state, float32_t a )
 {
    union ui32_f32 uA;
    uint_fast32_t uiA;
@@ -67,7 +67,7 @@ extFloat80_t f32_to_extF80( float32_t a )
    *------------------------------------------------------------------------*/
    if ( exp == 0xFF ) {
        if ( frac ) {
-            softfloat_f32UIToCommonNaN( uiA, &commonNaN );
+            softfloat_f32UIToCommonNaN( state, uiA, &commonNaN );
            uiZ = softfloat_commonNaNToExtF80UI( &commonNaN );
            uiZ64 = uiZ.v64;
            uiZ0  = uiZ.v0;
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include "softfloat.h"

 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f64_to_extF80( float64_t a )
+extFloat80_t f64_to_extF80( struct softfloat_state *state, float64_t a )
 {
    union ui64_f64 uA;
    uint_fast64_t uiA;
@@ -67,7 +67,7 @@ extFloat80_t f64_to_extF80( float64_t a )
    *------------------------------------------------------------------------*/
    if ( exp == 0x7FF ) {
        if ( frac ) {
-            softfloat_f64UIToCommonNaN( uiA, &commonNaN );
+            softfloat_f64UIToCommonNaN( state, uiA, &commonNaN );
            uiZ = softfloat_commonNaNToExtF80UI( &commonNaN );
            uiZ64 = uiZ.v64;
            uiZ0  = uiZ.v0;
@@ -63,19 +63,19 @@ uint_fast32_t softfloat_roundToUI32( bool, uint_fast64_t, uint_fast8_t, bool );
 #ifdef SOFTFLOAT_FAST_INT64
 uint_fast64_t
 softfloat_roundToUI64(
-     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
+     struct softfloat_state *, bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
 #else
 uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool );
 #endif

 FEXCORE_PRESERVE_ALL_ATTR
-int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool );
+int_fast32_t softfloat_roundToI32( struct softfloat_state *, bool, uint_fast64_t, uint_fast8_t, bool );

 #ifdef SOFTFLOAT_FAST_INT64
 FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
 softfloat_roundToI64(
-     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
+     struct softfloat_state *, bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
 #else
 int_fast64_t softfloat_roundMToI64( bool, uint32_t *, uint_fast8_t, bool );
 #endif
@@ -115,7 +115,7 @@ FEXCORE_PRESERVE_ALL_ATTR
 struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t );

 FEXCORE_PRESERVE_ALL_ATTR
-float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t );
+float32_t softfloat_roundPackToF32( struct softfloat_state *, bool, int_fast16_t, uint_fast32_t );
 float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t );

 float32_t softfloat_addMagsF32( uint_fast32_t, uint_fast32_t );
@@ -138,7 +138,7 @@ FEXCORE_PRESERVE_ALL_ATTR
 struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t );

 FEXCORE_PRESERVE_ALL_ATTR
-float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t );
+float64_t softfloat_roundPackToF64( struct softfloat_state *, bool, int_fast16_t, uint_fast64_t );
 float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t );

 float64_t softfloat_addMagsF64( uint_fast64_t, uint_fast64_t, bool );
@@ -167,18 +167,18 @@ struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t );
 FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
 softfloat_roundPackToExtF80(
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+     struct softfloat_state *, bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
 FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
 softfloat_normRoundPackToExtF80(
-     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+     struct softfloat_state *, bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );

 extFloat80_t
 softfloat_addMagsExtF80(
-     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+     struct softfloat_state *, uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
 extFloat80_t
 softfloat_subMagsExtF80(
-     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+     struct softfloat_state *, uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );

 /*----------------------------------------------------------------------------
 *----------------------------------------------------------------------------*/
@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 extFloat80_t
 softfloat_addMagsExtF80(
+     struct softfloat_state *state,
     uint_fast16_t uiA64,
     uint_fast64_t uiA0,
     uint_fast16_t uiB64,
@@ -140,11 +141,11 @@ extFloat80_t
 roundAndPack:
    return
        softfloat_roundPackToExtF80(
-            signZ, expZ, sigZ, sigZExtra, extF80_roundingPrecision );
+            state, signZ, expZ, sigZ, sigZExtra, state->roundingPrecision );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 propagateNaN:
-    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, uiB64, uiB0 );
    uiZ64 = uiZ.v64;
    uiZ0  = uiZ.v0;
 uiZ:
@@ -49,11 +49,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 void
 softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+     struct softfloat_state *state, uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
 {

    if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
    }
    zPtr->sign = uiA64>>15;
    zPtr->v64  = uiA0<<1;
@@ -50,12 +50,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 void
 softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+     struct softfloat_state *state, uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
 {
    struct uint128 NaNSig;

    if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
    }
    NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 );
    zPtr->sign = uiA64>>63;
@@ -46,11 +46,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | exception is raised.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr )
+void softfloat_f32UIToCommonNaN( struct softfloat_state *state, uint_fast32_t uiA, struct commonNaN *zPtr )
 {

    if ( softfloat_isSigNaNF32UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
    }
    zPtr->sign = uiA>>31;
    zPtr->v64  = (uint_fast64_t) uiA<<41;
@@ -46,11 +46,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | exception is raised.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr )
+void softfloat_f64UIToCommonNaN( struct softfloat_state *state, uint_fast64_t uiA, struct commonNaN *zPtr )
 {

    if ( softfloat_isSigNaNF64UI( uiA ) ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
    }
    zPtr->sign = uiA>>63;
    zPtr->v64  = uiA<<12;
@@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
 softfloat_normRoundPackToExtF80(
+     struct softfloat_state *state,
     bool sign,
     int_fast32_t exp,
     uint_fast64_t sig,
@@ -66,7 +67,7 @@ extFloat80_t
    }
    return
        softfloat_roundPackToExtF80(
-            sign, exp, sig, sigExtra, roundingPrecision );
+            state, sign, exp, sig, sigExtra, roundingPrecision );

 }

@@ -53,6 +53,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
 softfloat_propagateNaNExtF80UI(
+     struct softfloat_state *state,
     uint_fast16_t uiA64,
     uint_fast64_t uiA0,
     uint_fast16_t uiB64,
@@ -76,7 +77,7 @@ struct uint128
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    if ( isSigNaNA | isSigNaNB ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        if ( isSigNaNA ) {
            if ( isSigNaNB ) goto returnLargerMag;
            if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto returnB;
@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 extFloat80_t
 softfloat_roundPackToExtF80(
+     struct softfloat_state *state,
     bool sign,
     int_fast32_t exp,
     uint_fast64_t sig,
@@ -59,7 +60,7 @@ extFloat80_t

    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
-    roundingMode = softfloat_roundingMode;
+    roundingMode = state->roundingMode;
    roundNearEven = (roundingMode == softfloat_round_near_even);
    if ( roundingPrecision == 80 ) goto precision80;
    if ( roundingPrecision == 64 ) {
@@ -87,15 +88,15 @@ extFloat80_t
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            isTiny =
-                   (softfloat_detectTininess
+                   (state->detectTininess
                        == softfloat_tininess_beforeRounding)
                || (exp < 0)
                || (sig <= (uint64_t) (sig + roundIncrement));
            sig = softfloat_shiftRightJam64( sig, 1 - exp );
            roundBits = sig & roundMask;
            if ( roundBits ) {
-                if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow );
-                softfloat_exceptionFlags |= softfloat_flag_inexact;
+                if ( isTiny ) softfloat_raiseFlags( state, softfloat_flag_underflow );
+                state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
                if ( roundingMode == softfloat_round_odd ) {
                    sig |= roundMask + 1;
@@ -121,7 +122,7 @@ extFloat80_t
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    if ( roundBits ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
+        state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) {
            sig = (sig & ~roundMask) | (roundMask + 1);
@@ -157,7 +158,7 @@ extFloat80_t
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            isTiny =
-                   (softfloat_detectTininess
+                   (state->detectTininess
                        == softfloat_tininess_beforeRounding)
                || (exp < 0)
                || ! doIncrement
@@ -168,8 +169,8 @@ extFloat80_t
            sig = sig64Extra.v;
            sigExtra = sig64Extra.extra;
            if ( sigExtra ) {
-                if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow );
-                softfloat_exceptionFlags |= softfloat_flag_inexact;
+                if ( isTiny ) softfloat_raiseFlags( state, softfloat_flag_underflow );
+                state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
                if ( roundingMode == softfloat_round_odd ) {
                    sig |= 1;
@@ -207,7 +208,7 @@ extFloat80_t
            roundMask = 0;
 overflow:
            softfloat_raiseFlags(
-                softfloat_flag_overflow | softfloat_flag_inexact );
+                state, softfloat_flag_overflow | softfloat_flag_inexact );
            if (
                   roundNearEven
                || (roundingMode == softfloat_round_near_maxMag)
@@ -226,7 +227,7 @@ extFloat80_t
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
    if ( sigExtra ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
+        state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) {
            sig |= 1;
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 float32_t
- softfloat_roundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig )
+ softfloat_roundPackToF32( struct softfloat_state *state, bool sign, int_fast16_t exp, uint_fast32_t sig )
 {
    uint_fast8_t roundingMode;
    bool roundNearEven;
@@ -53,7 +53,7 @@ float32_t

    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
-    roundingMode = softfloat_roundingMode;
+    roundingMode = state->roundingMode;
    roundNearEven = (roundingMode == softfloat_round_near_even);
    roundIncrement = 0x40;
    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
@@ -71,19 +71,19 @@ float32_t
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            isTiny =
-                (softfloat_detectTininess == softfloat_tininess_beforeRounding)
+                (state->detectTininess == softfloat_tininess_beforeRounding)
                    || (exp < -1) || (sig + roundIncrement < 0x80000000);
            sig = softfloat_shiftRightJam32( sig, -exp );
            exp = 0;
            roundBits = sig & 0x7F;
            if ( isTiny && roundBits ) {
-                softfloat_raiseFlags( softfloat_flag_underflow );
+                softfloat_raiseFlags( state, softfloat_flag_underflow );
            }
        } else if ( (0xFD < exp) || (0x80000000 <= sig + roundIncrement) ) {
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            softfloat_raiseFlags(
-                softfloat_flag_overflow | softfloat_flag_inexact );
+                state, softfloat_flag_overflow | softfloat_flag_inexact );
            uiZ = packToF32UI( sign, 0xFF, 0 ) - ! roundIncrement;
            goto uiZ;
        }
@@ -92,7 +92,7 @@ float32_t
    *------------------------------------------------------------------------*/
    sig = (sig + roundIncrement)>>7;
    if ( roundBits ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
+        state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) {
            sig |= 1;
@@ -42,7 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 FEXCORE_PRESERVE_ALL_ATTR
 float64_t
- softfloat_roundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig )
+ softfloat_roundPackToF64( struct softfloat_state *state, bool sign, int_fast16_t exp, uint_fast64_t sig )
 {
    uint_fast8_t roundingMode;
    bool roundNearEven;
@@ -53,7 +53,7 @@ float64_t

    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
-    roundingMode = softfloat_roundingMode;
+    roundingMode = state->roundingMode;
    roundNearEven = (roundingMode == softfloat_round_near_even);
    roundIncrement = 0x200;
    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
@@ -71,14 +71,14 @@ float64_t
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            isTiny =
-                (softfloat_detectTininess == softfloat_tininess_beforeRounding)
+                (state->detectTininess == softfloat_tininess_beforeRounding)
                    || (exp < -1)
                    || (sig + roundIncrement < UINT64_C( 0x8000000000000000 ));
            sig = softfloat_shiftRightJam64( sig, -exp );
            exp = 0;
            roundBits = sig & 0x3FF;
            if ( isTiny && roundBits ) {
-                softfloat_raiseFlags( softfloat_flag_underflow );
+                softfloat_raiseFlags( state, softfloat_flag_underflow );
            }
        } else if (
            (0x7FD < exp)
@@ -87,7 +87,7 @@ float64_t
            /*----------------------------------------------------------------
            *----------------------------------------------------------------*/
            softfloat_raiseFlags(
-                softfloat_flag_overflow | softfloat_flag_inexact );
+                state, softfloat_flag_overflow | softfloat_flag_inexact );
            uiZ = packToF64UI( sign, 0x7FF, 0 ) - ! roundIncrement;
            goto uiZ;
        }
@@ -96,7 +96,7 @@ float64_t
    *------------------------------------------------------------------------*/
    sig = (sig + roundIncrement)>>10;
    if ( roundBits ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
+        state->exceptionFlags |= softfloat_flag_inexact;
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) {
            sig |= 1;
@@ -44,7 +44,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 int_fast32_t
 softfloat_roundToI32(
-     bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact )
+     struct softfloat_state *state, bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact )
 {
    uint_fast16_t roundIncrement, roundBits;
    uint_fast32_t sig32;
@@ -86,13 +86,13 @@ int_fast32_t
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) z |= 1;
 #endif
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( exact ) state->exceptionFlags |= softfloat_flag_inexact;
    }
    return z;
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    return sign ? i32_fromNegOverflow : i32_fromPosOverflow;

 }
@@ -44,6 +44,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FEXCORE_PRESERVE_ALL_ATTR
 int_fast64_t
 softfloat_roundToI64(
+     struct softfloat_state *state,
     bool sign,
     uint_fast64_t sig,
     uint_fast64_t sigExtra,
@@ -89,13 +90,13 @@ int_fast64_t
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) z |= 1;
 #endif
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( exact ) state->exceptionFlags |= softfloat_flag_inexact;
    }
    return z;
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    return sign ? i64_fromNegOverflow : i64_fromPosOverflow;

 }
@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 uint_fast64_t
 softfloat_roundToUI64(
+     struct softfloat_state *state,
     bool sign,
     uint_fast64_t sig,
     uint_fast64_t sigExtra,
@@ -84,13 +85,13 @@ uint_fast64_t
 #ifdef SOFTFLOAT_ROUND_ODD
        if ( roundingMode == softfloat_round_odd ) sig |= 1;
 #endif
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( exact ) state->exceptionFlags |= softfloat_flag_inexact;
    }
    return sig;
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
+    softfloat_raiseFlags( state, softfloat_flag_invalid );
    return sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;

 }
@@ -43,6 +43,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 extFloat80_t
 softfloat_subMagsExtF80(
+     struct softfloat_state *state,
     uint_fast16_t uiA64,
     uint_fast64_t uiA0,
     uint_fast16_t uiB64,
@@ -77,7 +78,7 @@ extFloat80_t
        if ( (sigA | sigB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
            goto propagateNaN;
        }
-        softfloat_raiseFlags( softfloat_flag_invalid );
+        softfloat_raiseFlags( state, softfloat_flag_invalid );
        uiZ64 = defaultNaNExtF80UI64;
        uiZ0  = defaultNaNExtF80UI0;
        goto uiZ;
@@ -90,7 +91,7 @@ extFloat80_t
    if ( sigB < sigA ) goto aBigger;
    if ( sigA < sigB ) goto bBigger;
    uiZ64 =
-        packToExtF80UI64( (softfloat_roundingMode == softfloat_round_min), 0 );
+        packToExtF80UI64( (state->roundingMode == softfloat_round_min), 0 );
    uiZ0 = 0;
    goto uiZ;
    /*------------------------------------------------------------------------
@@ -142,11 +143,11 @@ extFloat80_t
 normRoundPack:
    return
        softfloat_normRoundPackToExtF80(
-            signZ, expZ, sig128.v64, sig128.v0, extF80_roundingPrecision );
+            state, signZ, expZ, sig128.v64, sig128.v0, state->roundingPrecision );
    /*------------------------------------------------------------------------
    *------------------------------------------------------------------------*/
 propagateNaN:
-    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ = softfloat_propagateNaNExtF80UI( state, uiA64, uiA0, uiB64, uiB0 );
    uiZ64 = uiZ.v64;
    uiZ0  = uiZ.v0;
 uiZ:
@@ -50,50 +50,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #include <stdint.h>
 #include "softfloat_types.h"

-#ifndef THREAD_LOCAL
-#define THREAD_LOCAL
-#endif
-
-/*----------------------------------------------------------------------------
-| Software floating-point underflow tininess-detection mode.
-*----------------------------------------------------------------------------*/
-extern THREAD_LOCAL uint_fast8_t softfloat_detectTininess;
-enum {
-    softfloat_tininess_beforeRounding = 0,
-    softfloat_tininess_afterRounding  = 1
-};
-
-/*----------------------------------------------------------------------------
-| Software floating-point rounding mode.  (Mode "odd" is supported only if
-| SoftFloat is compiled with macro 'SOFTFLOAT_ROUND_ODD' defined.)
-*----------------------------------------------------------------------------*/
-extern THREAD_LOCAL uint_fast8_t softfloat_roundingMode;
-enum {
-    softfloat_round_near_even   = 0,
-    softfloat_round_minMag      = 1,
-    softfloat_round_min         = 2,
-    softfloat_round_max         = 3,
-    softfloat_round_near_maxMag = 4,
-    softfloat_round_odd         = 6
-};
-
-/*----------------------------------------------------------------------------
-| Software floating-point exception flags.
-*----------------------------------------------------------------------------*/
-extern THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags;
-enum {
-    softfloat_flag_inexact   =  1,
-    softfloat_flag_underflow =  2,
-    softfloat_flag_overflow  =  4,
-    softfloat_flag_infinite  =  8,
-    softfloat_flag_invalid   = 16
-};
-
 /*----------------------------------------------------------------------------
 | Routine to raise any or all of the software floating-point exception flags.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_raiseFlags( uint_fast8_t );
+void softfloat_raiseFlags( struct softfloat_state *, uint_fast8_t );

 /*----------------------------------------------------------------------------
 | Integer-to-floating-point conversion routines.
@@ -187,7 +148,7 @@ float16_t f32_to_f16( float32_t );
 float64_t f32_to_f64( float32_t );
 #ifdef SOFTFLOAT_FAST_INT64
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f32_to_extF80( float32_t );
+extFloat80_t f32_to_extF80( struct softfloat_state *, float32_t );
 float128_t f32_to_f128( float32_t );
 #endif
 void f32_to_extF80M( float32_t, extFloat80_t * );
@@ -223,7 +184,7 @@ float16_t f64_to_f16( float64_t );
 float32_t f64_to_f32( float64_t );
 #ifdef SOFTFLOAT_FAST_INT64
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f64_to_extF80( float64_t );
+extFloat80_t f64_to_extF80( struct softfloat_state *, float64_t );
 float128_t f64_to_f128( float64_t );
 #endif
 void f64_to_extF80M( float64_t, extFloat80_t * );
@@ -244,53 +205,47 @@ bool f64_le_quiet( float64_t, float64_t );
 bool f64_lt_quiet( float64_t, float64_t );
 bool f64_isSignalingNaN( float64_t );

-/*----------------------------------------------------------------------------
-| Rounding precision for 80-bit extended double-precision floating-point.
-| Valid values are 32, 64, and 80.
-*----------------------------------------------------------------------------*/
-extern THREAD_LOCAL uint_fast8_t extF80_roundingPrecision;
-
 /*----------------------------------------------------------------------------
 | 80-bit extended double-precision floating-point operations.
 *----------------------------------------------------------------------------*/
 #ifdef SOFTFLOAT_FAST_INT64
 uint_fast32_t extF80_to_ui32( extFloat80_t, uint_fast8_t, bool );
 FEXCORE_PRESERVE_ALL_ATTR
-uint_fast64_t extF80_to_ui64( extFloat80_t, uint_fast8_t, bool );
+uint_fast64_t extF80_to_ui64( struct softfloat_state *, extFloat80_t, uint_fast8_t, bool );
 FEXCORE_PRESERVE_ALL_ATTR
-int_fast32_t extF80_to_i32( extFloat80_t, uint_fast8_t, bool );
+int_fast32_t extF80_to_i32( struct softfloat_state *, extFloat80_t, uint_fast8_t, bool );
 FEXCORE_PRESERVE_ALL_ATTR
-int_fast64_t extF80_to_i64( extFloat80_t, uint_fast8_t, bool );
+int_fast64_t extF80_to_i64( struct softfloat_state *, extFloat80_t, uint_fast8_t, bool );
 uint_fast32_t extF80_to_ui32_r_minMag( extFloat80_t, bool );
 uint_fast64_t extF80_to_ui64_r_minMag( extFloat80_t, bool );
 int_fast32_t extF80_to_i32_r_minMag( extFloat80_t, bool );
 int_fast64_t extF80_to_i64_r_minMag( extFloat80_t, bool );
 float16_t extF80_to_f16( extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-float32_t extF80_to_f32( extFloat80_t );
+float32_t extF80_to_f32( struct softfloat_state *, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-float64_t extF80_to_f64( extFloat80_t );
+float64_t extF80_to_f64( struct softfloat_state *, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-float128_t extF80_to_f128( extFloat80_t );
+float128_t extF80_to_f128( struct softfloat_state *, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_roundToInt( extFloat80_t, uint_fast8_t, bool );
+extFloat80_t extF80_roundToInt( struct softfloat_state *, extFloat80_t, uint_fast8_t, bool );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_add( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_add( struct softfloat_state *, extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_sub( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_sub( struct softfloat_state *, extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_mul( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_mul( struct softfloat_state *, extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_div( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_div( struct softfloat_state *, extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_rem( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_rem( struct softfloat_state *, extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t extF80_sqrt( extFloat80_t );
+extFloat80_t extF80_sqrt( struct softfloat_state *, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-bool extF80_eq( extFloat80_t, extFloat80_t );
+bool extF80_eq( struct softfloat_state *, extFloat80_t, extFloat80_t );
 bool extF80_le( extFloat80_t, extFloat80_t );
 FEXCORE_PRESERVE_ALL_ATTR
-bool extF80_lt( extFloat80_t, extFloat80_t );
+bool extF80_lt( struct softfloat_state *, extFloat80_t, extFloat80_t );
 bool extF80_eq_signaling( extFloat80_t, extFloat80_t );
 bool extF80_le_quiet( extFloat80_t, extFloat80_t );
 bool extF80_lt_quiet( extFloat80_t, extFloat80_t );
@@ -341,7 +296,7 @@ float16_t f128_to_f16( float128_t );
 float32_t f128_to_f32( float128_t );
 float64_t f128_to_f64( float128_t );
 FEXCORE_PRESERVE_ALL_ATTR
-extFloat80_t f128_to_extF80( float128_t );
+extFloat80_t f128_to_extF80( struct softfloat_state *, float128_t );
 float128_t f128_roundToInt( float128_t, uint_fast8_t, bool );
 float128_t f128_add( float128_t, float128_t );
 float128_t f128_sub( float128_t, float128_t );
@@ -44,10 +44,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 | should be simply `softfloat_exceptionFlags |= flags;'.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_raiseFlags( uint_fast8_t flags )
+void softfloat_raiseFlags( struct softfloat_state *state, uint_fast8_t flags )
 {

-    softfloat_exceptionFlags |= flags;
+    state->exceptionFlags |= flags;

 }

@@ -1,52 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
-Package, Release 3e, by John R. Hauser.
-
-Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
-California.  All Rights Reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
-    this list of conditions, and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
-    this list of conditions, and the following disclaimer in the documentation
-    and/or other materials provided with the distribution.
-
- 3. Neither the name of the University nor the names of its contributors may
-    be used to endorse or promote products derived from this software without
-    specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
-DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-=============================================================================*/
-
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-#ifndef THREAD_LOCAL
-#define THREAD_LOCAL
-#endif
-
-THREAD_LOCAL uint_fast8_t softfloat_roundingMode = softfloat_round_near_even;
-THREAD_LOCAL uint_fast8_t softfloat_detectTininess = init_detectTininess;
-THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags = 0;
-
-THREAD_LOCAL uint_fast8_t extF80_roundingPrecision = 80;
-
@@ -77,5 +77,50 @@ struct extFloat80M { uint16_t signExp; uint64_t signif; };
 *----------------------------------------------------------------------------*/
 typedef struct extFloat80M extFloat80_t;

+enum {
+    softfloat_tininess_beforeRounding = 0,
+    softfloat_tininess_afterRounding  = 1
+};
+
+enum {
+    softfloat_round_near_even   = 0,
+    softfloat_round_minMag      = 1,
+    softfloat_round_min         = 2,
+    softfloat_round_max         = 3,
+    softfloat_round_near_maxMag = 4,
+    softfloat_round_odd         = 6
+};
+
+enum {
+    softfloat_flag_inexact   =  1,
+    softfloat_flag_underflow =  2,
+    softfloat_flag_overflow  =  4,
+    softfloat_flag_infinite  =  8,
+    softfloat_flag_invalid   = 16
+};
+
+struct softfloat_state {
+/*----------------------------------------------------------------------------
+| Software floating-point underflow tininess-detection mode.
+*----------------------------------------------------------------------------*/
+uint8_t detectTininess; /* = init_detectTininess */
+/*----------------------------------------------------------------------------
+| Software floating-point rounding mode.  (Mode "odd" is supported only if
+| SoftFloat is compiled with macro 'SOFTFLOAT_ROUND_ODD' defined.)
+*----------------------------------------------------------------------------*/
+uint8_t roundingMode; /* = softfloat_round_near_even */
+
+/*----------------------------------------------------------------------------
+| Software floating-point exception flags.
+*----------------------------------------------------------------------------*/
+uint8_t exceptionFlags; /* = 0 */
+
+/*----------------------------------------------------------------------------
+| Rounding precision for 80-bit extended double-precision floating-point.
+| Valid values are 32, 64, and 80.
+*----------------------------------------------------------------------------*/
+uint8_t roundingPrecision; /* = 80 */
+};
+
 #endif

@@ -136,7 +136,7 @@ uint_fast16_t
 | exception is raised.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
+void softfloat_f32UIToCommonNaN( struct softfloat_state *, uint_fast32_t uiA, struct commonNaN *zPtr );

 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
@@ -173,7 +173,7 @@ uint_fast32_t
 | exception is raised.
 *----------------------------------------------------------------------------*/
 FEXCORE_PRESERVE_ALL_ATTR
-void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
+void softfloat_f64UIToCommonNaN( struct softfloat_state *, uint_fast64_t uiA, struct commonNaN *zPtr );

 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
@@ -222,7 +222,7 @@ uint_fast64_t
 FEXCORE_PRESERVE_ALL_ATTR
 void
 softfloat_extF80UIToCommonNaN(
-     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+     struct softfloat_state *, uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );

 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
@@ -244,6 +244,7 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
 FEXCORE_PRESERVE_ALL_ATTR
 struct uint128
 softfloat_propagateNaNExtF80UI(
+     struct softfloat_state *,
     uint_fast16_t uiA64,
     uint_fast64_t uiA0,
     uint_fast16_t uiB64,
@@ -274,7 +275,7 @@ struct uint128
 FEXCORE_PRESERVE_ALL_ATTR
 void
 softfloat_f128UIToCommonNaN(
-     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+     struct softfloat_state *, uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );

 /*----------------------------------------------------------------------------
 | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
@@ -63,7 +63,7 @@ struct FEX_PACKED X80SoftFloat {
  }

  // Ops
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FADD(const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FADD(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
    asm(R"(
@@ -79,11 +79,11 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    return extF80_add(lhs, rhs);
+    return extF80_add(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSUB(const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSUB(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
    asm(R"(
@@ -99,11 +99,11 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    return extF80_sub(lhs, rhs);
+    return extF80_sub(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FMUL(const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FMUL(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
    asm(R"(
@@ -119,11 +119,11 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    return extF80_mul(lhs, rhs);
+    return extF80_mul(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FDIV(const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FDIV(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
    asm(R"(
@@ -139,11 +139,11 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    return extF80_div(lhs, rhs);
+    return extF80_div(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM(const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #if defined(DEBUG_X86_FLOAT)
    BIGFLOAT Result;
    asm(R"(
@@ -160,11 +160,11 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    return extF80_rem(lhs, rhs);
+    return extF80_rem(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM1(const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FREM1(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
 #if defined(DEBUG_X86_FLOAT)
    BIGFLOAT Result;
    asm(R"(
@@ -181,16 +181,16 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    return extF80_rem(lhs, rhs);
+    return extF80_rem(state, lhs, rhs);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(const X80SoftFloat& lhs) {
-    return extF80_roundToInt(lhs, softfloat_roundingMode, false);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(softfloat_state* state, const X80SoftFloat& lhs) {
+    return extF80_roundToInt(state, lhs, state->roundingMode, false);
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(const X80SoftFloat& lhs, uint_fast8_t RoundMode) {
-    return extF80_roundToInt(lhs, RoundMode, false);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FRNDINT(softfloat_state* state, const X80SoftFloat& lhs, uint_fast8_t RoundMode) {
+    return extF80_roundToInt(state, lhs, RoundMode, false);
  }

  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FXTRACT_SIG(const X80SoftFloat& lhs) {
@@ -237,13 +237,14 @@ struct FEX_PACKED X80SoftFloat {
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static void FCMP(const X80SoftFloat& lhs, const X80SoftFloat& rhs, bool* eq, bool* lt, bool* nan) {
-    *eq = extF80_eq(lhs, rhs);
-    *lt = extF80_lt(lhs, rhs);
+  FEXCORE_PRESERVE_ALL_ATTR static void
+  FCMP(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs, bool* eq, bool* lt, bool* nan) {
+    *eq = extF80_eq(state, lhs, rhs);
+    *lt = extF80_lt(state, lhs, rhs);
    *nan = IsNan(lhs) || IsNan(rhs);
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSCALE(const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSCALE(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
    WARN_ONCE_FMT("x87: Application used FSCALE which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
@@ -261,16 +262,16 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    X80SoftFloat Int = FRNDINT(rhs, softfloat_round_minMag);
-    LIBRARY_PRECISION Src2_d = Int;
+    X80SoftFloat Int = FRNDINT(state, rhs, softfloat_round_minMag);
+    LIBRARY_PRECISION Src2_d = Int.ToFMax(state);
    Src2_d = exp2l(Src2_d);
-    X80SoftFloat Src2_X80 = Src2_d;
-    X80SoftFloat Result = extF80_mul(lhs, Src2_X80);
+    X80SoftFloat Src2_X80(state, Src2_d);
+    X80SoftFloat Result = extF80_mul(state, lhs, Src2_X80);
    return Result;
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat F2XM1(const X80SoftFloat& lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat F2XM1(softfloat_state* state, const X80SoftFloat& lhs) {
    WARN_ONCE_FMT("x87: Application used F2XM1 which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
@@ -286,14 +287,14 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    LIBRARY_PRECISION Src1_d = lhs;
+    LIBRARY_PRECISION Src1_d = lhs.ToFMax(state);
    LIBRARY_PRECISION Result = exp2l(Src1_d);
    Result -= 1.0;
-    return Result;
+    return X80SoftFloat(state, Result);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FYL2X(const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FYL2X(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
    WARN_ONCE_FMT("x87: Application used FYL2X which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
@@ -310,14 +311,14 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    LIBRARY_PRECISION Src1_d = lhs;
-    LIBRARY_PRECISION Src2_d = rhs;
+    LIBRARY_PRECISION Src1_d = lhs.ToFMax(state);
+    LIBRARY_PRECISION Src2_d = rhs.ToFMax(state);
    LIBRARY_PRECISION Tmp = Src2_d * log2l(Src1_d);
-    return Tmp;
+    return X80SoftFloat(state, Tmp);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FATAN(const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FATAN(softfloat_state* state, const X80SoftFloat& lhs, const X80SoftFloat& rhs) {
    WARN_ONCE_FMT("x87: Application used FATAN which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
@@ -334,14 +335,14 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    LIBRARY_PRECISION Src1_d = lhs;
-    LIBRARY_PRECISION Src2_d = rhs;
+    LIBRARY_PRECISION Src1_d = lhs.ToFMax(state);
+    LIBRARY_PRECISION Src2_d = rhs.ToFMax(state);
    LIBRARY_PRECISION Tmp = atan2l(Src1_d, Src2_d);
-    return Tmp;
+    return X80SoftFloat(state, Tmp);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FTAN(const X80SoftFloat& lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FTAN(softfloat_state* state, const X80SoftFloat& lhs) {
    WARN_ONCE_FMT("x87: Application used FTAN which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
@@ -358,13 +359,13 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    LIBRARY_PRECISION Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs.ToFMax(state);
    Src_d = tanl(Src_d);
-    return Src_d;
+    return X80SoftFloat(state, Src_d);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSIN(const X80SoftFloat& lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSIN(softfloat_state* state, const X80SoftFloat& lhs) {
    WARN_ONCE_FMT("x87: Application used FSIN which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
@@ -380,13 +381,13 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    LIBRARY_PRECISION Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs.ToFMax(state);
    Src_d = sinl(Src_d);
-    return Src_d;
+    return X80SoftFloat(state, Src_d);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FCOS(const X80SoftFloat& lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FCOS(softfloat_state* state, const X80SoftFloat& lhs) {
    WARN_ONCE_FMT("x87: Application used FCOS which may have accuracy problems");
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
@@ -402,13 +403,13 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    LIBRARY_PRECISION Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs.ToFMax(state);
    Src_d = cosl(Src_d);
-    return Src_d;
+    return X80SoftFloat(state, Src_d);
 #endif
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSQRT(const X80SoftFloat& lhs) {
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat FSQRT(softfloat_state* state, const X80SoftFloat& lhs) {
 #ifdef DEBUG_X86_FLOAT
    BIGFLOAT Result;
    asm(R"(
@@ -423,62 +424,55 @@ struct FEX_PACKED X80SoftFloat {

    return Result;
 #else
-    return extF80_sqrt(lhs);
+    return extF80_sqrt(state, lhs);
 #endif
  }

-  operator float() const {
-    const float32_t Result = extF80_to_f32(*this);
+  float ToF32(softfloat_state* state) const {
+    const float32_t Result = extF80_to_f32(state, *this);
    return FEXCore::BitCast<float>(Result);
  }

-  operator double() const {
-    const float64_t Result = extF80_to_f64(*this);
+  double ToF64(softfloat_state* state) const {
+    const float64_t Result = extF80_to_f64(state, *this);
    return FEXCore::BitCast<double>(Result);
  }

-#ifndef _WIN32
-  operator BIGFLOAT() const {
+  LIBRARY_PRECISION ToFMax(softfloat_state* state) const {
+#ifdef _WIN32
+    return ToF64(state);
+#else
 #if BIGFLOATSIZE == 16
-    const float128_t Result = extF80_to_f128(*this);
+    const float128_t Result = extF80_to_f128(state, *this);
    return FEXCore::BitCast<BIGFLOAT>(Result);
 #else
    BIGFLOAT result {};
    memcpy(&result, this, sizeof(result));
    return result;
 #endif
-  }
 #endif
+  }

-  operator int16_t() const {
-    auto rv = extF80_to_i32(*this, softfloat_roundingMode, false);
-    if (rv > INT16_MAX) {
-      return INT16_MAX;
-    } else if (rv < INT16_MIN) {
+  int16_t ToI16(softfloat_state* state) const {
+    auto rv = extF80_to_i32(state, *this, state->roundingMode, false);
+    if (rv > INT16_MAX || rv < INT16_MIN) {
+      ///< Indefinite value for 16-bit conversions.
      return INT16_MIN;
    } else {
      return rv;
    }
  }

-  operator int32_t() const {
-    return extF80_to_i32(*this, softfloat_roundingMode, false);
+  int32_t ToI32(softfloat_state* state) const {
+    return extF80_to_i32(state, *this, state->roundingMode, false);
  }

-  operator int64_t() const {
-    return extF80_to_i64(*this, softfloat_roundingMode, false);
+  int64_t ToI64(softfloat_state* state) const {
+    return extF80_to_i64(state, *this, state->roundingMode, false);
  }

-  operator uint64_t() const {
-    return extF80_to_ui64(*this, softfloat_roundingMode, false);
-  }
-
-  void operator=(const float rhs) {
-    *this = f32_to_extF80(FEXCore::BitCast<float32_t>(rhs));
-  }
-
-  void operator=(const double rhs) {
-    *this = f64_to_extF80(FEXCore::BitCast<float64_t>(rhs));
+  uint64_t ToUI64(softfloat_state* state) const {
+    return extF80_to_ui64(state, *this, state->roundingMode, false);
  }

  void operator=(const int16_t rhs) {
@@ -509,18 +503,18 @@ struct FEX_PACKED X80SoftFloat {
    Sign = rhs.signExp >> 15;
  }

-  X80SoftFloat(const float rhs) {
-    *this = f32_to_extF80(FEXCore::BitCast<float32_t>(rhs));
+  X80SoftFloat(softfloat_state* state, const float rhs) {
+    *this = f32_to_extF80(state, FEXCore::BitCast<float32_t>(rhs));
  }

-  X80SoftFloat(const double rhs) {
-    *this = f64_to_extF80(FEXCore::BitCast<float64_t>(rhs));
+  X80SoftFloat(softfloat_state* state, const double rhs) {
+    *this = f64_to_extF80(state, FEXCore::BitCast<float64_t>(rhs));
  }

 #ifndef _WIN32
-  X80SoftFloat(BIGFLOAT rhs) {
+  X80SoftFloat(softfloat_state* state, BIGFLOAT rhs) {
 #if BIGFLOATSIZE == 16
-    *this = f128_to_extF80(FEXCore::BitCast<float128_t>(rhs));
+    *this = f128_to_extF80(state, FEXCore::BitCast<float128_t>(rhs));
 #else
    *this = FEXCore::BitCast<long double>(rhs);
 #endif
@@ -50,8 +50,6 @@
          "DISABLESVE": "disablesve",
          "ENABLEAVX": "enableavx",
          "DISABLEAVX": "disableavx",
-          "ENABLEAVX2": "enableavx2",
-          "DISABLEAVX2": "disableavx2",
          "ENABLEAFP": "enableafp",
          "DISABLEAFP": "disableafp",
          "ENABLELRCPC": "enablelrcpc",
@@ -78,6 +76,8 @@
          "DISABLECRYPTO": "disablecrypto",
          "ENABLERPRES": "enablerpres",
          "DISABLERPRES": "disablerpres",
+          "ENABLESVEBITPERM": "enablesvebitperm",
+          "DISABLESVEBITPERM": "disablesvebitperm",
          "ENABLEPRESERVEALLABI": "enablepreserveallabi",
          "DISABLEPRESERVEALLABI": "disablepreserveallabi"
        },
@@ -86,7 +86,6 @@
          "\toff: Default CPU features queried from CPU features",
          "\t{enable,disable}sve: Will force enable or disable sve even if the host doesn't support it",
          "\t{enable,disable}avx: Will force enable or disable avx even if the host doesn't support it",
-          "\t{enable,disable}avx2: Will force enable or disable avx2 even if the host doesn't support it",
          "\t{enable,disable}afp: Will force enable or disable afp even if the host doesn't support it",
          "\t{enable,disable}lrcpc: Will force enable or disable lrcpc even if the host doesn't support it",
          "\t{enable,disable}lrcpc2: Will force enable or disable lrcpc2 even if the host doesn't support it",
@@ -100,6 +99,7 @@
          "\t{enable,disable}flagm2: Will force enable or disable flagm2 even if the host doesn't support it",
          "\t{enable,disable}crypto: Will force enable or disable crypto extensions even if the host doesn't support it",
          "\t{enable,disable}rpres: Will force enable or disable rpres even if the host doesn't support it",
+          "\t{enable,disable}svebitperm: Will force enable or disable svebitperm even if the host doesn't support it",
          "\t{enable,disable}preserveallabi: Will force enable or disable preserve_all abi even if the host doesn't support it"
        ]
      },
@@ -401,14 +401,14 @@
      },
      "VectorTSOEnabled": {
        "Type": "bool",
-        "Default": "true",
+        "Default": "false",
        "Desc": [
          "When TSO emulation is enabled, controls if vector loadstores should also be atomic."
        ]
      },
      "MemcpySetTSOEnabled": {
        "Type": "bool",
-        "Default": "true",
+        "Default": "false",
        "Desc": [
          "When TSO emulation is enabled, controls if memcpy and memset should also be atomic.",
          "Only affects REP MOVS and REP STOS instructions"
@@ -6,6 +6,7 @@
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/CPUID.h>
+#include <FEXCore/Core/HostFeatures.h>
 #include <FEXCore/Core/SignalDelegator.h>
 #include "FEXCore/Debug/InternalThreadState.h"

@@ -18,8 +19,8 @@ void InitializeStaticTables(OperatingMode Mode) {
  IR::InstallOpcodeHandlers(Mode);
 }

-fextl::unique_ptr<FEXCore::Context::Context> FEXCore::Context::Context::CreateNewContext() {
-  return fextl::make_unique<FEXCore::Context::ContextImpl>();
+fextl::unique_ptr<FEXCore::Context::Context> FEXCore::Context::Context::CreateNewContext(const FEXCore::HostFeatures& Features) {
+  return fextl::make_unique<FEXCore::Context::ContextImpl>(Features);
 }

 void FEXCore::Context::ContextImpl::SetExitHandler(ExitHandler handler) {
@@ -42,10 +43,6 @@ void FEXCore::Context::ContextImpl::SetCustomCPUBackendFactory(CustomCPUFactoryT
  CustomCPUFactory = std::move(Factory);
 }

-HostFeatures FEXCore::Context::ContextImpl::GetHostFeatures() const {
-  return HostFeatures;
-}
-
 void FEXCore::Context::ContextImpl::SetSignalDelegator(FEXCore::SignalDelegator* _SignalDelegation) {
  SignalDelegation = _SignalDelegation;
 }
@@ -57,6 +57,7 @@ namespace HLE {

 namespace FEXCore::IR {
 class RegisterAllocationData;
+struct IRListCopy;
 class IRListView;
 namespace Validation {
  class IRValidation;
@@ -95,14 +96,15 @@ public:

  void SetCustomCPUBackendFactory(CustomCPUFactoryType Factory) override;

-  HostFeatures GetHostFeatures() const override;
-
  void HandleCallback(FEXCore::Core::InternalThreadState* Thread, uint64_t RIP) override;

  uint64_t RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState* Thread, uint64_t HostPC) override;
  uint32_t ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadState* Thread, bool WasInJIT, uint64_t* HostGPRs, uint64_t PSTATE) override;
  void SetFlagsFromCompactedEFLAGS(FEXCore::Core::InternalThreadState* Thread, uint32_t EFLAGS) override;

+  void ReconstructXMMRegisters(const FEXCore::Core::InternalThreadState* Thread, __uint128_t* XMM_Low, __uint128_t* YMM_High) override;
+  void SetXMMRegistersFromState(FEXCore::Core::InternalThreadState* Thread, const __uint128_t* XMM_Low, const __uint128_t* YMM_High) override;
+
  /**
   * @brief Used to create FEX thread objects in preparation for creating a true OS thread. Does set a TID or PID.
   *
@@ -191,7 +193,7 @@ public:
  // returns false if a handler was already registered
  CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void* Creator = nullptr, void* Data = nullptr);

-  void AppendThunkDefinitions(const fextl::vector<FEXCore::IR::ThunkDefinition>& Definitions) override;
+  void AppendThunkDefinitions(std::span<const FEXCore::IR::ThunkDefinition> Definitions) override;

 public:
  friend class FEXCore::HLE::SyscallHandler;
@@ -205,9 +207,6 @@ public:
    CoreRunningMode RunningMode {CoreRunningMode::MODE_RUN};
    uint64_t VirtualMemSize {1ULL << 36};

-    // this is for internal use
-    bool ValidateIRarser {false};
-
    // Used if the JIT needs to have its interrupt fault code emitted.
    bool NeedsPendingInterruptFaultCheck {false};

@@ -263,7 +262,7 @@ public:
  SignalDelegator* SignalDelegation {};
  X86GeneratedCode X86CodeGen;

-  ContextImpl();
+  ContextImpl(const FEXCore::HostFeatures& Features);
  ~ContextImpl();

  static void ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP);
@@ -282,9 +281,6 @@ public:
  // Must be called from owning thread
  static void ThreadRemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame* Frame, uint64_t GuestRIP) {
    auto Thread = Frame->Thread;
-
-    LOGMAN_THROW_A_FMT(Thread->ThreadManager.GetTID() == FHU::Syscalls::gettid(), "Must be called from owning thread {}, not {}",
-                       Thread->ThreadManager.GetTID(), FHU::Syscalls::gettid());
    auto lk = GuardSignalDeferringSection(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);

    ThreadRemoveCodeEntry(Thread, GuestRIP);
@@ -293,8 +289,7 @@ public:
  void RemoveCustomIREntrypoint(uintptr_t Entrypoint);

  struct GenerateIRResult {
-    FEXCore::IR::IRListView* IRList;
-    FEXCore::IR::RegisterAllocationData::UniquePtr RAData;
+    fextl::unique_ptr<FEXCore::IR::IRStorageBase> IR;
    uint64_t TotalInstructions;
    uint64_t TotalInstructionsLength;
    uint64_t StartAddr;
@@ -305,9 +300,8 @@ public:

  struct CompileCodeResult {
    void* CompiledCode;
-    FEXCore::IR::IRListView* IRData;
+    fextl::unique_ptr<FEXCore::IR::IRStorageBase> IR;
    FEXCore::Core::DebugData* DebugData;
-    FEXCore::IR::RegisterAllocationData::UniquePtr RAData;
    bool GeneratedIR;
    uint64_t StartAddr;
    uint64_t Length;
@@ -379,8 +373,6 @@ public:
    return ExitOnHLT;
  }

-  FEXCore::CPU::CPUBackendFeatures BackendFeatures;
-
 protected:
  void UpdateAtomicTSOEmulationConfig() {
    if (SupportsHardwareTSO) {
@@ -2,8 +2,6 @@
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
 #include "FEXCore/Core/X86Enums.h"
 #include "FEXCore/Utils/AllocatorHooks.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Context/Context.h"
 #include "Interface/HLE/Thunks/Thunks.h"
@@ -13,128 +11,118 @@
 #include <FEXCore/Utils/MathUtils.h>

 #include <FEXHeaderUtils/BitUtils.h>
+#include <CodeEmitter/Emitter.h>
+#include <CodeEmitter/Registers.h>

+#ifdef VIXL_DISASSEMBLER
 #include <aarch64/cpu-aarch64.h>
 #include <aarch64/instructions-aarch64.h>
 #include <cpu-features.h>
 #include <utils-vixl.h>
+#endif

 #include <array>
 #include <tuple>
 #include <utility>

 namespace FEXCore::CPU {
-// Register x18 is unused in the current configuration.
-// This is due to it being a platform register on wine platforms.
-// TODO: Allow x18 register allocation on Linux in the future to gain one more register.
-
 namespace x64 {
 #ifndef _M_ARM_64EC
  // All but x19 and x29 are caller saved
-  constexpr std::array<FEXCore::ARMEmitter::Register, 18> SRA = {
-    FEXCore::ARMEmitter::Reg::r4,
-    FEXCore::ARMEmitter::Reg::r5,
-    FEXCore::ARMEmitter::Reg::r6,
-    FEXCore::ARMEmitter::Reg::r7,
-    FEXCore::ARMEmitter::Reg::r8,
-    FEXCore::ARMEmitter::Reg::r9,
-    FEXCore::ARMEmitter::Reg::r10,
-    FEXCore::ARMEmitter::Reg::r11,
-    FEXCore::ARMEmitter::Reg::r12,
-    FEXCore::ARMEmitter::Reg::r13,
-    FEXCore::ARMEmitter::Reg::r14,
-    FEXCore::ARMEmitter::Reg::r15,
-    FEXCore::ARMEmitter::Reg::r16,
-    FEXCore::ARMEmitter::Reg::r17,
-    FEXCore::ARMEmitter::Reg::r19,
-    FEXCore::ARMEmitter::Reg::r29,
+  constexpr std::array<ARMEmitter::Register, 18> SRA = {
+    ARMEmitter::Reg::r4,
+    ARMEmitter::Reg::r5,
+    ARMEmitter::Reg::r6,
+    ARMEmitter::Reg::r7,
+    ARMEmitter::Reg::r8,
+    ARMEmitter::Reg::r9,
+    ARMEmitter::Reg::r10,
+    ARMEmitter::Reg::r11,
+    ARMEmitter::Reg::r12,
+    ARMEmitter::Reg::r13,
+    ARMEmitter::Reg::r14,
+    ARMEmitter::Reg::r15,
+    ARMEmitter::Reg::r16,
+    ARMEmitter::Reg::r17,
+    ARMEmitter::Reg::r19,
+    ARMEmitter::Reg::r29,
    // PF/AF must be last.
    REG_PF,
    REG_AF,
  };

-  constexpr std::array<FEXCore::ARMEmitter::Register, 7> RA = {
+  constexpr std::array<ARMEmitter::Register, 8> RA = {
    // All these callee saved
-    FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21, FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23,
-    FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25, FEXCore::ARMEmitter::Reg::r30,
+    ARMEmitter::Reg::r20, ARMEmitter::Reg::r21, ARMEmitter::Reg::r22, ARMEmitter::Reg::r23,
+    ARMEmitter::Reg::r24, ARMEmitter::Reg::r25, ARMEmitter::Reg::r30, ARMEmitter::Reg::r18,
  };

-  constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 3> RAPair = {{
-    {FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21},
-    {FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23},
-    {FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25},
-  }};
+  constexpr unsigned RAPairs = 6;

  // All are caller saved
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 16> SRAFPR = {
-    FEXCore::ARMEmitter::VReg::v16, FEXCore::ARMEmitter::VReg::v17, FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19,
-    FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21, FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23,
-    FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25, FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27,
-    FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29, FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31};
+  constexpr std::array<ARMEmitter::VRegister, 16> SRAFPR = {
+    ARMEmitter::VReg::v16, ARMEmitter::VReg::v17, ARMEmitter::VReg::v18, ARMEmitter::VReg::v19,
+    ARMEmitter::VReg::v20, ARMEmitter::VReg::v21, ARMEmitter::VReg::v22, ARMEmitter::VReg::v23,
+    ARMEmitter::VReg::v24, ARMEmitter::VReg::v25, ARMEmitter::VReg::v26, ARMEmitter::VReg::v27,
+    ARMEmitter::VReg::v28, ARMEmitter::VReg::v29, ARMEmitter::VReg::v30, ARMEmitter::VReg::v31};

  //  v8..v15 = (lower 64bits) Callee saved
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 14> RAFPR = {
+  constexpr std::array<ARMEmitter::VRegister, 14> RAFPR = {
    // v0 ~ v1 are used as temps.
-    // FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1,
+    // ARMEmitter::VReg::v0, ARMEmitter::VReg::v1,

-    FEXCore::ARMEmitter::VReg::v2,  FEXCore::ARMEmitter::VReg::v3,  FEXCore::ARMEmitter::VReg::v4,  FEXCore::ARMEmitter::VReg::v5,
-    FEXCore::ARMEmitter::VReg::v6,  FEXCore::ARMEmitter::VReg::v7,  FEXCore::ARMEmitter::VReg::v8,  FEXCore::ARMEmitter::VReg::v9,
-    FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
-    FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+    ARMEmitter::VReg::v2,  ARMEmitter::VReg::v3,  ARMEmitter::VReg::v4,  ARMEmitter::VReg::v5,  ARMEmitter::VReg::v6,
+    ARMEmitter::VReg::v7,  ARMEmitter::VReg::v8,  ARMEmitter::VReg::v9,  ARMEmitter::VReg::v10, ARMEmitter::VReg::v11,
+    ARMEmitter::VReg::v12, ARMEmitter::VReg::v13, ARMEmitter::VReg::v14, ARMEmitter::VReg::v15,
  };
 #else
-  constexpr std::array<FEXCore::ARMEmitter::Register, 18> SRA = {
-    FEXCore::ARMEmitter::Reg::r8,
-    FEXCore::ARMEmitter::Reg::r0,
-    FEXCore::ARMEmitter::Reg::r1,
-    FEXCore::ARMEmitter::Reg::r27,
+  constexpr std::array<ARMEmitter::Register, 18> SRA = {
+    ARMEmitter::Reg::r8,
+    ARMEmitter::Reg::r0,
+    ARMEmitter::Reg::r1,
+    ARMEmitter::Reg::r27,
    // SP's register location isn't specified by the ARM64EC ABI, we choose to use r23
-    FEXCore::ARMEmitter::Reg::r23,
-    FEXCore::ARMEmitter::Reg::r29,
-    FEXCore::ARMEmitter::Reg::r25,
-    FEXCore::ARMEmitter::Reg::r26,
-    FEXCore::ARMEmitter::Reg::r2,
-    FEXCore::ARMEmitter::Reg::r3,
-    FEXCore::ARMEmitter::Reg::r4,
-    FEXCore::ARMEmitter::Reg::r5,
-    FEXCore::ARMEmitter::Reg::r19,
-    FEXCore::ARMEmitter::Reg::r20,
-    FEXCore::ARMEmitter::Reg::r21,
-    FEXCore::ARMEmitter::Reg::r22,
+    ARMEmitter::Reg::r23,
+    ARMEmitter::Reg::r29,
+    ARMEmitter::Reg::r25,
+    ARMEmitter::Reg::r26,
+    ARMEmitter::Reg::r2,
+    ARMEmitter::Reg::r3,
+    ARMEmitter::Reg::r4,
+    ARMEmitter::Reg::r5,
+    ARMEmitter::Reg::r19,
+    ARMEmitter::Reg::r20,
+    ARMEmitter::Reg::r21,
+    ARMEmitter::Reg::r22,
    REG_PF,
    REG_AF,
  };

-  constexpr std::array<FEXCore::ARMEmitter::Register, 7> RA = {
-    FEXCore::ARMEmitter::Reg::r6,  FEXCore::ARMEmitter::Reg::r7,  FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15,
-    FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17, FEXCore::ARMEmitter::Reg::r30,
+  constexpr std::array<ARMEmitter::Register, 7> RA = {
+    ARMEmitter::Reg::r6,  ARMEmitter::Reg::r7,  ARMEmitter::Reg::r14, ARMEmitter::Reg::r15,
+    ARMEmitter::Reg::r16, ARMEmitter::Reg::r17, ARMEmitter::Reg::r30,
  };

-  constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 3> RAPair = {{
-    {FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7},
-    {FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15},
-    {FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17},
-  }};
+  constexpr unsigned RAPairs = 6;

-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 16> SRAFPR = {
-    FEXCore::ARMEmitter::VReg::v0,  FEXCore::ARMEmitter::VReg::v1,  FEXCore::ARMEmitter::VReg::v2,  FEXCore::ARMEmitter::VReg::v3,
-    FEXCore::ARMEmitter::VReg::v4,  FEXCore::ARMEmitter::VReg::v5,  FEXCore::ARMEmitter::VReg::v6,  FEXCore::ARMEmitter::VReg::v7,
-    FEXCore::ARMEmitter::VReg::v8,  FEXCore::ARMEmitter::VReg::v9,  FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11,
-    FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13, FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+  constexpr std::array<ARMEmitter::VRegister, 16> SRAFPR = {
+    ARMEmitter::VReg::v0,  ARMEmitter::VReg::v1,  ARMEmitter::VReg::v2,  ARMEmitter::VReg::v3,
+    ARMEmitter::VReg::v4,  ARMEmitter::VReg::v5,  ARMEmitter::VReg::v6,  ARMEmitter::VReg::v7,
+    ARMEmitter::VReg::v8,  ARMEmitter::VReg::v9,  ARMEmitter::VReg::v10, ARMEmitter::VReg::v11,
+    ARMEmitter::VReg::v12, ARMEmitter::VReg::v13, ARMEmitter::VReg::v14, ARMEmitter::VReg::v15,
  };

-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 14> RAFPR = {
-    FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19, FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21,
-    FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23, FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25,
-    FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27, FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29,
-    FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31};
+  constexpr std::array<ARMEmitter::VRegister, 14> RAFPR = {
+    ARMEmitter::VReg::v18, ARMEmitter::VReg::v19, ARMEmitter::VReg::v20, ARMEmitter::VReg::v21, ARMEmitter::VReg::v22,
+    ARMEmitter::VReg::v23, ARMEmitter::VReg::v24, ARMEmitter::VReg::v25, ARMEmitter::VReg::v26, ARMEmitter::VReg::v27,
+    ARMEmitter::VReg::v28, ARMEmitter::VReg::v29, ARMEmitter::VReg::v30, ARMEmitter::VReg::v31};
 #endif

  // I wish this could get constexpr generated from SRA's definition but impossible until libstdc++12, libc++15.
  // SRA GPRs that need to be spilled when calling a function with `preserve_all` ABI.
-  constexpr std::array<FEXCore::ARMEmitter::Register, 7> PreserveAll_SRA = {
-    FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5,  FEXCore::ARMEmitter::Reg::r6,  FEXCore::ARMEmitter::Reg::r7,
-    FEXCore::ARMEmitter::Reg::r8, FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17,
+  constexpr std::array<ARMEmitter::Register, 7> PreserveAll_SRA = {
+    ARMEmitter::Reg::r4, ARMEmitter::Reg::r5,  ARMEmitter::Reg::r6,  ARMEmitter::Reg::r7,
+    ARMEmitter::Reg::r8, ARMEmitter::Reg::r16, ARMEmitter::Reg::r17,
  };

  constexpr uint32_t PreserveAll_SRAMask = {[]() -> uint32_t {
@@ -160,12 +148,12 @@ namespace x64 {
  }()};

  // Dynamic GPRs
-  constexpr std::array<FEXCore::ARMEmitter::Register, 1> PreserveAll_Dynamic = {
+  constexpr std::array<ARMEmitter::Register, 1> PreserveAll_Dynamic = {
    // Only LR needs to get saved.
-    FEXCore::ARMEmitter::Reg::r30};
+    ARMEmitter::Reg::r30};

  // SRA FPRs that need to be spilled when calling a function with `preserve_all` ABI.
-  constexpr std::array<FEXCore::ARMEmitter::Register, 0> PreserveAll_SRAFPR = {
+  constexpr std::array<ARMEmitter::Register, 0> PreserveAll_SRAFPR = {
    // None.
  };

@@ -179,15 +167,14 @@ namespace x64 {

  // Dynamic FPRs
  // - v0-v7
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 6> PreserveAll_DynamicFPR = {
+  constexpr std::array<ARMEmitter::VRegister, 6> PreserveAll_DynamicFPR = {
    // v0 ~ v1 are temps
-    FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, FEXCore::ARMEmitter::VReg::v4,
-    FEXCore::ARMEmitter::VReg::v5, FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
+    ARMEmitter::VReg::v2, ARMEmitter::VReg::v3, ARMEmitter::VReg::v4, ARMEmitter::VReg::v5, ARMEmitter::VReg::v6, ARMEmitter::VReg::v7,
  };

  // SRA FPRs that need to be spilled when the host supports SVE-256bit with `preserve_all` ABI.
  // This is /all/ of the SRA registers
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 16> PreserveAll_SRAFPRSVE = SRAFPR;
+  constexpr std::array<ARMEmitter::VRegister, 16> PreserveAll_SRAFPRSVE = SRAFPR;

  constexpr uint32_t PreserveAll_SRAFPRSVEMask = {[]() -> uint32_t {
    uint32_t Mask {};
@@ -198,89 +185,77 @@ namespace x64 {
  }()};

  // Dynamic FPRs when the host supports SVE-256bit.
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 14> PreserveAll_DynamicFPRSVE = {
+  constexpr std::array<ARMEmitter::VRegister, 14> PreserveAll_DynamicFPRSVE = {
    // v0 ~ v1 are used as temps.
-    FEXCore::ARMEmitter::VReg::v2,  FEXCore::ARMEmitter::VReg::v3,  FEXCore::ARMEmitter::VReg::v4,  FEXCore::ARMEmitter::VReg::v5,
-    FEXCore::ARMEmitter::VReg::v6,  FEXCore::ARMEmitter::VReg::v7,  FEXCore::ARMEmitter::VReg::v8,  FEXCore::ARMEmitter::VReg::v9,
-    FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
-    FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+    ARMEmitter::VReg::v2,  ARMEmitter::VReg::v3,  ARMEmitter::VReg::v4,  ARMEmitter::VReg::v5,  ARMEmitter::VReg::v6,
+    ARMEmitter::VReg::v7,  ARMEmitter::VReg::v8,  ARMEmitter::VReg::v9,  ARMEmitter::VReg::v10, ARMEmitter::VReg::v11,
+    ARMEmitter::VReg::v12, ARMEmitter::VReg::v13, ARMEmitter::VReg::v14, ARMEmitter::VReg::v15,
  };
 } // namespace x64

 namespace x32 {
  // All but x19 and x29 are caller saved
-  constexpr std::array<FEXCore::ARMEmitter::Register, 10> SRA = {
-    FEXCore::ARMEmitter::Reg::r4,
-    FEXCore::ARMEmitter::Reg::r5,
-    FEXCore::ARMEmitter::Reg::r6,
-    FEXCore::ARMEmitter::Reg::r7,
-    FEXCore::ARMEmitter::Reg::r8,
-    FEXCore::ARMEmitter::Reg::r9,
-    FEXCore::ARMEmitter::Reg::r10,
-    FEXCore::ARMEmitter::Reg::r11,
+  constexpr std::array<ARMEmitter::Register, 10> SRA = {
+    ARMEmitter::Reg::r4,
+    ARMEmitter::Reg::r5,
+    ARMEmitter::Reg::r6,
+    ARMEmitter::Reg::r7,
+    ARMEmitter::Reg::r8,
+    ARMEmitter::Reg::r9,
+    ARMEmitter::Reg::r10,
+    ARMEmitter::Reg::r11,
    // PF/AF must be last.
    REG_PF,
    REG_AF,
  };

-  constexpr std::array<FEXCore::ARMEmitter::Register, 15> RA = {
+  constexpr std::array<ARMEmitter::Register, 15> RA = {
    // All these callee saved
-    FEXCore::ARMEmitter::Reg::r20,
-    FEXCore::ARMEmitter::Reg::r21,
-    FEXCore::ARMEmitter::Reg::r22,
-    FEXCore::ARMEmitter::Reg::r23,
-    FEXCore::ARMEmitter::Reg::r24,
-    FEXCore::ARMEmitter::Reg::r25,
+    ARMEmitter::Reg::r20,
+    ARMEmitter::Reg::r21,
+    ARMEmitter::Reg::r22,
+    ARMEmitter::Reg::r23,
+    ARMEmitter::Reg::r24,
+    ARMEmitter::Reg::r25,

    // Registers only available on 32-bit
    // All these are caller saved (except for r19).
-    FEXCore::ARMEmitter::Reg::r12,
-    FEXCore::ARMEmitter::Reg::r13,
-    FEXCore::ARMEmitter::Reg::r14,
-    FEXCore::ARMEmitter::Reg::r15,
-    FEXCore::ARMEmitter::Reg::r16,
-    FEXCore::ARMEmitter::Reg::r17,
-    FEXCore::ARMEmitter::Reg::r29,
-    FEXCore::ARMEmitter::Reg::r30,
+    ARMEmitter::Reg::r12,
+    ARMEmitter::Reg::r13,
+    ARMEmitter::Reg::r14,
+    ARMEmitter::Reg::r15,
+    ARMEmitter::Reg::r16,
+    ARMEmitter::Reg::r17,
+    ARMEmitter::Reg::r29,
+    ARMEmitter::Reg::r30,

-    FEXCore::ARMEmitter::Reg::r19,
+    ARMEmitter::Reg::r19,
  };

-  constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 7> RAPair = {{
-    {FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21},
-    {FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23},
-    {FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25},
-
-    {FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r13},
-    {FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15},
-    {FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17},
-    {FEXCore::ARMEmitter::Reg::r29, FEXCore::ARMEmitter::Reg::r30},
-  }};
+  constexpr unsigned RAPairs = 12;

  // All are caller saved
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 8> SRAFPR = {
-    FEXCore::ARMEmitter::VReg::v16, FEXCore::ARMEmitter::VReg::v17, FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19,
-    FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21, FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23,
+  constexpr std::array<ARMEmitter::VRegister, 8> SRAFPR = {
+    ARMEmitter::VReg::v16, ARMEmitter::VReg::v17, ARMEmitter::VReg::v18, ARMEmitter::VReg::v19,
+    ARMEmitter::VReg::v20, ARMEmitter::VReg::v21, ARMEmitter::VReg::v22, ARMEmitter::VReg::v23,
  };

  //  v8..v15 = (lower 64bits) Callee saved
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 22> RAFPR = {
+  constexpr std::array<ARMEmitter::VRegister, 22> RAFPR = {
    // v0 ~ v1 are used as temps.
-    // FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1,
+    // ARMEmitter::VReg::v0, ARMEmitter::VReg::v1,

-    FEXCore::ARMEmitter::VReg::v2,  FEXCore::ARMEmitter::VReg::v3,  FEXCore::ARMEmitter::VReg::v4,  FEXCore::ARMEmitter::VReg::v5,
-    FEXCore::ARMEmitter::VReg::v6,  FEXCore::ARMEmitter::VReg::v7,  FEXCore::ARMEmitter::VReg::v8,  FEXCore::ARMEmitter::VReg::v9,
-    FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
-    FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+    ARMEmitter::VReg::v2,  ARMEmitter::VReg::v3,  ARMEmitter::VReg::v4,  ARMEmitter::VReg::v5,  ARMEmitter::VReg::v6,
+    ARMEmitter::VReg::v7,  ARMEmitter::VReg::v8,  ARMEmitter::VReg::v9,  ARMEmitter::VReg::v10, ARMEmitter::VReg::v11,
+    ARMEmitter::VReg::v12, ARMEmitter::VReg::v13, ARMEmitter::VReg::v14, ARMEmitter::VReg::v15,

-    FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25, FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27,
-    FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29, FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31};
+    ARMEmitter::VReg::v24, ARMEmitter::VReg::v25, ARMEmitter::VReg::v26, ARMEmitter::VReg::v27, ARMEmitter::VReg::v28,
+    ARMEmitter::VReg::v29, ARMEmitter::VReg::v30, ARMEmitter::VReg::v31};

  // I wish this could get constexpr generated from SRA's definition but impossible until libstdc++12, libc++15.
  // SRA GPRs that need to be spilled when calling a function with `preserve_all` ABI.
-  constexpr std::array<FEXCore::ARMEmitter::Register, 5> PreserveAll_SRA = {
-    FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5, FEXCore::ARMEmitter::Reg::r6,
-    FEXCore::ARMEmitter::Reg::r7, FEXCore::ARMEmitter::Reg::r8,
+  constexpr std::array<ARMEmitter::Register, 5> PreserveAll_SRA = {
+    ARMEmitter::Reg::r4, ARMEmitter::Reg::r5, ARMEmitter::Reg::r6, ARMEmitter::Reg::r7, ARMEmitter::Reg::r8,
  };

  constexpr uint32_t PreserveAll_SRAMask = {[]() -> uint32_t {
@@ -306,11 +281,10 @@ namespace x32 {
  }()};

  // Dynamic GPRs
-  constexpr std::array<FEXCore::ARMEmitter::Register, 3> PreserveAll_Dynamic = {
-    FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17, FEXCore::ARMEmitter::Reg::r30};
+  constexpr std::array<ARMEmitter::Register, 3> PreserveAll_Dynamic = {ARMEmitter::Reg::r16, ARMEmitter::Reg::r17, ARMEmitter::Reg::r30};

  // SRA FPRs that need to be spilled when calling a function with `preserve_all` ABI.
-  constexpr std::array<FEXCore::ARMEmitter::Register, 0> PreserveAll_SRAFPR = {
+  constexpr std::array<ARMEmitter::Register, 0> PreserveAll_SRAFPR = {
    // None.
  };

@@ -324,15 +298,14 @@ namespace x32 {

  // Dynamic FPRs
  // - v0-v7
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 6> PreserveAll_DynamicFPR = {
+  constexpr std::array<ARMEmitter::VRegister, 6> PreserveAll_DynamicFPR = {
    // v0 ~ v1 are temps
-    FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3, FEXCore::ARMEmitter::VReg::v4,
-    FEXCore::ARMEmitter::VReg::v5, FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
+    ARMEmitter::VReg::v2, ARMEmitter::VReg::v3, ARMEmitter::VReg::v4, ARMEmitter::VReg::v5, ARMEmitter::VReg::v6, ARMEmitter::VReg::v7,
  };

  // SRA FPRs that need to be spilled when the host supports SVE-256bit with `preserve_all` ABI.
  // This is /all/ of the SRA registers
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 8> PreserveAll_SRAFPRSVE = SRAFPR;
+  constexpr std::array<ARMEmitter::VRegister, 8> PreserveAll_SRAFPRSVE = SRAFPR;

  constexpr uint32_t PreserveAll_SRAFPRSVEMask = {[]() -> uint32_t {
    uint32_t Mask {};
@@ -343,15 +316,14 @@ namespace x32 {
  }()};

  // Dynamic FPRs when the host supports SVE-256bit.
-  constexpr std::array<FEXCore::ARMEmitter::VRegister, 22> PreserveAll_DynamicFPRSVE = {
+  constexpr std::array<ARMEmitter::VRegister, 22> PreserveAll_DynamicFPRSVE = {
    // v0 ~ v1 are used as temps.
-    FEXCore::ARMEmitter::VReg::v2,  FEXCore::ARMEmitter::VReg::v3,  FEXCore::ARMEmitter::VReg::v4,  FEXCore::ARMEmitter::VReg::v5,
-    FEXCore::ARMEmitter::VReg::v6,  FEXCore::ARMEmitter::VReg::v7,  FEXCore::ARMEmitter::VReg::v8,  FEXCore::ARMEmitter::VReg::v9,
-    FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
-    FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+    ARMEmitter::VReg::v2,  ARMEmitter::VReg::v3,  ARMEmitter::VReg::v4,  ARMEmitter::VReg::v5,  ARMEmitter::VReg::v6,
+    ARMEmitter::VReg::v7,  ARMEmitter::VReg::v8,  ARMEmitter::VReg::v9,  ARMEmitter::VReg::v10, ARMEmitter::VReg::v11,
+    ARMEmitter::VReg::v12, ARMEmitter::VReg::v13, ARMEmitter::VReg::v14, ARMEmitter::VReg::v15,

-    FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25, FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27,
-    FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29, FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31};
+    ARMEmitter::VReg::v24, ARMEmitter::VReg::v25, ARMEmitter::VReg::v26, ARMEmitter::VReg::v27, ARMEmitter::VReg::v28,
+    ARMEmitter::VReg::v29, ARMEmitter::VReg::v30, ARMEmitter::VReg::v31};
 } // namespace x32

 // We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one.
@@ -379,24 +351,22 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl* ctx, void* EmissionPtr
  }
 #endif

-  CPU.SetUp();
-
  // Number of register available is dependent on what operating mode the proccess is in.
  if (EmitterCTX->Config.Is64BitMode()) {
    StaticRegisters = x64::SRA;
    GeneralRegisters = x64::RA;
-    GeneralPairRegisters = x64::RAPair;
    StaticFPRegisters = x64::SRAFPR;
    GeneralFPRegisters = x64::RAFPR;
+    PairRegisters = x64::RAPairs;
 #ifdef _M_ARM_64EC
    ConfiguredDynamicRegisterBase = std::span(x64::RA.begin(), 7);
 #endif
  } else {
    ConfiguredDynamicRegisterBase = std::span(x32::RA.begin() + 6, 8);
+    PairRegisters = x32::RAPairs;

    StaticRegisters = x32::SRA;
    GeneralRegisters = x32::RA;
-    GeneralPairRegisters = x32::RAPair;

    StaticFPRegisters = x32::SRAFPR;
    GeneralFPRegisters = x32::RAFPR;
@@ -451,7 +421,7 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
  if (RequiredMoveSegments > 1) {
    // Only try to use this path if the number of segments is > 1.
    // `movz` is better than `orr` since hardware will rename or merge if possible when `movz` is used.
-    const auto IsImm = vixl::aarch64::Assembler::IsImmLogical(Constant, RegSizeInBits(s));
+    const auto IsImm = ARMEmitter::Emitter::IsImmLogical(Constant, RegSizeInBits(s));
    if (IsImm) {
      orr(s, Reg, ARMEmitter::Reg::zr, Constant);
      if (NOPPad) {
@@ -463,6 +433,17 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
    }
  }

+  // If we can't handle negatives with the orr, try with movn+movk
+  if (Is64Bit && ((~Constant) >> 32) == 0) {
+    movn(s, Reg, (~Constant) & 0xFFFF);
+    movk(s, Reg, (Constant >> 16) & 0xFFFF, 16);
+    if (NOPPad) {
+      nop();
+      nop();
+    }
+    return;
+  }
+
  // ADRP+ADD is specifically optimized in hardware
  // Check if we can use this
  auto PC = GetCursorAddress<uint64_t>();
@@ -477,7 +458,7 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui

  // If the aligned offset is within the 4GB window then we can use ADRP+ADD
  // and the number of move segments more than 1
-  if (RequiredMoveSegments > 1 && vixl::IsInt32(AlignedOffset)) {
+  if (RequiredMoveSegments > 1 && ARMEmitter::Emitter::IsInt32(AlignedOffset)) {
    // If this is 4k page aligned then we only need ADRP
    if ((AlignedOffset & 0xFFF) == 0) {
      adrp(Reg, AlignedOffset >> 12);
@@ -485,7 +466,7 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
      // If the constant is within 1MB of PC then we can still use ADR to load in a single instruction
      // 21-bit signed integer here
      int64_t SmallOffset = static_cast<int64_t>(Constant) - static_cast<int64_t>(PC);
-      if (vixl::IsInt21(SmallOffset)) {
+      if (ARMEmitter::Emitter::IsInt21(SmallOffset)) {
        adr(Reg, SmallOffset);
      } else {
        // Need to use ADRP + ADD
@@ -589,12 +570,53 @@ void Arm64Emitter::PopCalleeSavedRegisters() {
  }
 }

-void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FPRs, uint32_t GPRSpillMask, uint32_t FPRSpillMask) {
+void Arm64Emitter::FillSpecialRegs(ARMEmitter::Register TmpReg, ARMEmitter::Register TmpReg2, bool SetFIZ, bool SetPredRegs) {
+#ifndef VIXL_SIMULATOR
+  if (EmitterCTX->HostFeatures.SupportsAFP) {
+    // Enable AFP features when filling JIT state.
+    mrs(TmpReg, ARMEmitter::SystemRegister::FPCR);
+
+    // Enable FPCR.NEP and FPCR.AH
+    // NEP(2): Changes ASIMD scalar instructions to insert in to the lower bits of the destination.
+    // AH(1):  Changes NaN behaviour in some instructions. Specifically fmin, fmax.
+    //
+    // Additional interesting AFP bits:
+    // FIZ(0): Flush Inputs to Zero
+    orr(ARMEmitter::Size::i64Bit, TmpReg, TmpReg,
+        (1U << 2) |   // NEP
+          (1U << 1)); // AH
+
+    if (SetFIZ) {
+      // Insert MXCSR.DAZ in to FIZ
+      ldr(TmpReg2.W(), STATE.R(), offsetof(FEXCore::Core::CPUState, mxcsr));
+      bfxil(ARMEmitter::Size::i64Bit, TmpReg, TmpReg2, 6, 1);
+    }
+
+    msr(ARMEmitter::SystemRegister::FPCR, TmpReg);
+  }
+#endif
+
+  if (SetPredRegs) {
+    // Set up predicate registers.
+    // We don't bother spilling these in SpillStaticRegs,
+    // since all that matters is we restore them on a fill.
+    // It's not a concern if they get trounced by something else.
+    if (EmitterCTX->HostFeatures.SupportsSVE256) {
+      ptrue(ARMEmitter::SubRegSize::i8Bit, PRED_TMP_32B, ARMEmitter::PredicatePattern::SVE_VL32);
+    }
+
+    if (EmitterCTX->HostFeatures.SupportsSVE128) {
+      ptrue(ARMEmitter::SubRegSize::i8Bit, PRED_TMP_16B, ARMEmitter::PredicatePattern::SVE_VL16);
+    }
+  }
+}
+
+void Arm64Emitter::SpillStaticRegs(ARMEmitter::Register TmpReg, bool FPRs, uint32_t GPRSpillMask, uint32_t FPRSpillMask) {
 #ifndef VIXL_SIMULATOR
  if (EmitterCTX->HostFeatures.SupportsAFP) {
    // Disable AFP features when spilling registers.
    //
-    // Disable FPCR.NEP and FPCR.AH
+    // Disable FPCR.NEP and FPCR.AH and FPCR.FIZ
    // NEP(2): Changes ASIMD scalar instructions to insert in to the lower bits of the destination.
    // AH(1):  Changes NaN behaviour in some instructions. Specifically fmin, fmax.
    //         Also interacts with RPRES to change reciprocal/rsqrt precision from 8-bit mantissa to 12-bit.
@@ -604,7 +626,8 @@ void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FP
    mrs(TmpReg, ARMEmitter::SystemRegister::FPCR);
    bic(ARMEmitter::Size::i64Bit, TmpReg, TmpReg,
        (1U << 2) |   // NEP
-          (1U << 1)); // AH
+          (1U << 1) | // AH
+          (1U << 0)); // FIZ
    msr(ARMEmitter::SystemRegister::FPCR, TmpReg);
  }
 #endif
@@ -643,7 +666,7 @@ void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FP
  }

  if (FPRs) {
-    if (EmitterCTX->HostFeatures.SupportsAVX) {
+    if (EmitterCTX->HostFeatures.SupportsAVX && EmitterCTX->HostFeatures.SupportsSVE256) {
      for (size_t i = 0; i < StaticFPRegisters.size(); i++) {
        const auto Reg = StaticFPRegisters[i];

@@ -682,37 +705,37 @@ void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FP
  }
 }

-void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRFillMask) {
-  FEXCore::ARMEmitter::Register TmpReg = FEXCore::ARMEmitter::Reg::r0;
-  LOGMAN_THROW_A_FMT(GPRFillMask != 0, "Must fill at least 1 GPR for a temp");
-  [[maybe_unused]] bool FoundRegister {};
-  for (auto Reg : StaticRegisters) {
-    if (((1U << Reg.Idx()) & GPRFillMask)) {
-      TmpReg = Reg;
-      FoundRegister = true;
-      break;
+void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRFillMask, std::optional<ARMEmitter::Register> OptionalReg,
+                                  std::optional<ARMEmitter::Register> OptionalReg2) {
+  auto FindTempReg = [this](uint32_t* GPRFillMask) -> std::optional<ARMEmitter::Register> {
+    for (auto Reg : StaticRegisters) {
+      if (((1U << Reg.Idx()) & *GPRFillMask)) {
+        *GPRFillMask &= ~(1U << Reg.Idx());
+        return std::make_optional(Reg);
+      }
    }
+    return std::nullopt;
+  };
+
+  LOGMAN_THROW_A_FMT(GPRFillMask != 0, "Must fill at least 2 GPRs for a temp");
+  uint32_t TempGPRFillMask = GPRFillMask;
+  if (!OptionalReg.has_value()) {
+    OptionalReg = FindTempReg(&TempGPRFillMask);
  }

-  LOGMAN_THROW_A_FMT(FoundRegister, "Didn't have an SRA register to use as a temporary while spilling!");
-
-#ifndef VIXL_SIMULATOR
-  if (EmitterCTX->HostFeatures.SupportsAFP) {
-    // Enable AFP features when filling JIT state.
-    LOGMAN_THROW_A_FMT(GPRFillMask != 0, "Must fill at least 1 GPR for a temp");
-    mrs(TmpReg, ARMEmitter::SystemRegister::FPCR);
-
-    // Enable FPCR.NEP and FPCR.AH
-    // NEP(2): Changes ASIMD scalar instructions to insert in to the lower bits of the destination.
-    // AH(1):  Changes NaN behaviour in some instructions. Specifically fmin, fmax.
-    //
-    // Additional interesting AFP bits:
-    // FIZ(0): Flush Inputs to Zero
-    orr(ARMEmitter::Size::i64Bit, TmpReg, TmpReg,
-        (1U << 2) |   // NEP
-          (1U << 1)); // AH
-    msr(ARMEmitter::SystemRegister::FPCR, TmpReg);
+  if (!OptionalReg2.has_value()) {
+    OptionalReg2 = FindTempReg(&TempGPRFillMask);
  }
+  LOGMAN_THROW_A_FMT(OptionalReg.has_value() && OptionalReg2.has_value(), "Didn't have an SRA register to use as a temporary while "
+                                                                          "spilling!");
+
+  auto TmpReg = *OptionalReg;
+  auto TmpReg2 = *OptionalReg2;
+
+#ifdef _M_ARM_64EC
+  // Load STATE in from the CPU area as x28 is not callee saved in the ARM64EC ABI.
+  ldr(TmpReg.X(), ARMEmitter::Reg::r18, TEB_CPU_AREA_OFFSET);
+  ldr(STATE, TmpReg, CPU_AREA_EMULATOR_DATA_OFFSET);
 #endif

  // Regardless of what GPRs/FPRs we're filling, we need to fill NZCV since it
@@ -723,18 +746,10 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
  ldr(TmpReg.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
  msr(ARMEmitter::SystemRegister::NZCV, TmpReg);

+  FillSpecialRegs(TmpReg, TmpReg2, true, FPRs);
+
  if (FPRs) {
-    // Set up predicate registers.
-    // We don't bother spilling these in SpillStaticRegs,
-    // since all that matters is we restore them on a fill.
-    // It's not a concern if they get trounced by something else.
-    if (EmitterCTX->HostFeatures.SupportsSVE) {
-      ptrue(ARMEmitter::SubRegSize::i8Bit, PRED_TMP_16B, ARMEmitter::PredicatePattern::SVE_VL16);
-    }
-
-    if (EmitterCTX->HostFeatures.SupportsAVX) {
-      ptrue(ARMEmitter::SubRegSize::i8Bit, PRED_TMP_32B, ARMEmitter::PredicatePattern::SVE_VL32);
-
+    if (EmitterCTX->HostFeatures.SupportsAVX && EmitterCTX->HostFeatures.SupportsSVE256) {
      for (size_t i = 0; i < StaticFPRegisters.size(); i++) {
        const auto Reg = StaticFPRegisters[i];
        if (((1U << Reg.Idx()) & FPRFillMask) != 0) {
@@ -798,8 +813,8 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
  }
 }

-void Arm64Emitter::PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs) {
-  if (SVERegs) {
+void Arm64Emitter::PushVectorRegisters(ARMEmitter::Register TmpReg, bool SVE256Regs, std::span<const ARMEmitter::VRegister> VRegs) {
+  if (SVE256Regs) {
    size_t i = 0;

    for (; i < (VRegs.size() % 4); i += 2) {
@@ -835,7 +850,7 @@ void Arm64Emitter::PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, boo
  }
 }

-void Arm64Emitter::PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, std::span<const FEXCore::ARMEmitter::Register> Regs) {
+void Arm64Emitter::PushGeneralRegisters(ARMEmitter::Register TmpReg, std::span<const ARMEmitter::Register> Regs) {
  size_t i = 0;
  for (; i < (Regs.size() % 2); ++i) {
    const auto Reg1 = Regs[i];
@@ -849,8 +864,8 @@ void Arm64Emitter::PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, st
  }
 }

-void Arm64Emitter::PopVectorRegisters(bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs) {
-  if (SVERegs) {
+void Arm64Emitter::PopVectorRegisters(bool SVE256Regs, std::span<const ARMEmitter::VRegister> VRegs) {
+  if (SVE256Regs) {
    size_t i = 0;
    for (; i < (VRegs.size() % 4); i += 2) {
      const auto Reg1 = VRegs[i];
@@ -885,7 +900,7 @@ void Arm64Emitter::PopVectorRegisters(bool SVERegs, std::span<const FEXCore::ARM
  }
 }

-void Arm64Emitter::PopGeneralRegisters(std::span<const FEXCore::ARMEmitter::Register> Regs) {
+void Arm64Emitter::PopGeneralRegisters(std::span<const ARMEmitter::Register> Regs) {
  size_t i = 0;
  for (; i < (Regs.size() % 2); ++i) {
    const auto Reg1 = Regs[i];
@@ -898,10 +913,10 @@ void Arm64Emitter::PopGeneralRegisters(std::span<const FEXCore::ARMEmitter::Regi
  }
 }

-void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
-  const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
+void Arm64Emitter::PushDynamicRegsAndLR(ARMEmitter::Register TmpReg) {
+  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256;
  const auto GPRSize = (ConfiguredDynamicRegisterBase.size() + 1) * Core::CPUState::GPR_REG_SIZE;
-  const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE : Core::CPUState::XMM_SSE_REG_SIZE;
+  const auto FPRRegSize = CanUseSVE256 ? 32 : 16;
  const auto FPRSize = GeneralFPRegisters.size() * FPRRegSize;
  const uint64_t SPOffset = AlignUp(GPRSize + FPRSize, 16);

@@ -913,7 +928,7 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
  LOGMAN_THROW_A_FMT(GeneralFPRegisters.size() % 2 == 0, "Needs to have multiple of 2 FPRs for RA");

  // Push the vector registers
-  PushVectorRegisters(TmpReg, CanUseSVE, GeneralFPRegisters);
+  PushVectorRegisters(TmpReg, CanUseSVE256, GeneralFPRegisters);

  // Push the general registers.
  PushGeneralRegisters(TmpReg, ConfiguredDynamicRegisterBase);
@@ -924,10 +939,10 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
 }

 void Arm64Emitter::PopDynamicRegsAndLR() {
-  const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
+  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256;

  // Pop vectors first
-  PopVectorRegisters(CanUseSVE, GeneralFPRegisters);
+  PopVectorRegisters(CanUseSVE256, GeneralFPRegisters);

  // Pop GPRs second
  PopGeneralRegisters(ConfiguredDynamicRegisterBase);
@@ -937,12 +952,12 @@ void Arm64Emitter::PopDynamicRegsAndLR() {
 #endif
 }

-void Arm64Emitter::SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpReg, bool FPRs) {
-  const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
-  const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE : Core::CPUState::XMM_SSE_REG_SIZE;
+void Arm64Emitter::SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool FPRs) {
+  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256;
+  const auto FPRRegSize = CanUseSVE256 ? 32 : 16;

-  std::span<const FEXCore::ARMEmitter::Register> DynamicGPRs {};
-  std::span<const FEXCore::ARMEmitter::VRegister> DynamicFPRs {};
+  std::span<const ARMEmitter::Register> DynamicGPRs {};
+  std::span<const ARMEmitter::VRegister> DynamicFPRs {};
  uint32_t PreserveSRAMask {};
  uint32_t PreserveSRAFPRMask {};
  if (EmitterCTX->Config.Is64BitMode()) {
@@ -951,7 +966,7 @@ void Arm64Emitter::SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpR
    PreserveSRAMask = x64::PreserveAll_SRAMask;
    PreserveSRAFPRMask = x64::PreserveAll_SRAFPRMask;

-    if (CanUseSVE) {
+    if (CanUseSVE256) {
      DynamicFPRs = x64::PreserveAll_DynamicFPRSVE;
      PreserveSRAFPRMask = x64::PreserveAll_SRAFPRSVEMask;
    }
@@ -961,7 +976,7 @@ void Arm64Emitter::SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpR
    PreserveSRAMask = x32::PreserveAll_SRAMask;
    PreserveSRAFPRMask = x32::PreserveAll_SRAFPRMask;

-    if (CanUseSVE) {
+    if (CanUseSVE256) {
      DynamicFPRs = x32::PreserveAll_DynamicFPRSVE;
      PreserveSRAFPRMask = x32::PreserveAll_SRAFPRSVEMask;
    }
@@ -980,17 +995,17 @@ void Arm64Emitter::SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpR
  add(ARMEmitter::Size::i64Bit, TmpReg, ARMEmitter::Reg::rsp, 0);

  // Push the vector registers.
-  PushVectorRegisters(TmpReg, CanUseSVE, DynamicFPRs);
+  PushVectorRegisters(TmpReg, CanUseSVE256, DynamicFPRs);

  // Push the general registers.
  PushGeneralRegisters(TmpReg, DynamicGPRs);
 }

 void Arm64Emitter::FillForPreserveAllABICall(bool FPRs) {
-  const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
+  const auto CanUseSVE256 = EmitterCTX->HostFeatures.SupportsSVE256;

-  std::span<const FEXCore::ARMEmitter::Register> DynamicGPRs {};
-  std::span<const FEXCore::ARMEmitter::VRegister> DynamicFPRs {};
+  std::span<const ARMEmitter::Register> DynamicGPRs {};
+  std::span<const ARMEmitter::VRegister> DynamicFPRs {};
  uint32_t PreserveSRAMask {};
  uint32_t PreserveSRAFPRMask {};

@@ -1000,7 +1015,7 @@ void Arm64Emitter::FillForPreserveAllABICall(bool FPRs) {
    PreserveSRAMask = x64::PreserveAll_SRAMask;
    PreserveSRAFPRMask = x64::PreserveAll_SRAFPRMask;

-    if (CanUseSVE) {
+    if (CanUseSVE256) {
      DynamicFPRs = x64::PreserveAll_DynamicFPRSVE;
      PreserveSRAFPRMask = x64::PreserveAll_SRAFPRSVEMask;
    }
@@ -1010,7 +1025,7 @@ void Arm64Emitter::FillForPreserveAllABICall(bool FPRs) {
    PreserveSRAMask = x32::PreserveAll_SRAMask;
    PreserveSRAFPRMask = x32::PreserveAll_SRAFPRMask;

-    if (CanUseSVE) {
+    if (CanUseSVE256) {
      DynamicFPRs = x32::PreserveAll_DynamicFPRSVE;
      PreserveSRAFPRMask = x32::PreserveAll_SRAFPRSVEMask;
    }
@@ -1020,7 +1035,7 @@ void Arm64Emitter::FillForPreserveAllABICall(bool FPRs) {
  FillStaticRegs(true, PreserveSRAMask, PreserveSRAFPRMask);

  // Pop the vector registers.
-  PopVectorRegisters(CanUseSVE, DynamicFPRs);
+  PopVectorRegisters(CanUseSVE256, DynamicFPRs);

  // Pop the general registers.
  PopGeneralRegisters(DynamicGPRs);
@@ -2,9 +2,6 @@
 #pragma once

 #include "FEXCore/Utils/EnumUtils.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
-
 #include "Interface/Core/ObjectCache/Relocations.h"

 #include <aarch64/assembler-aarch64.h>
@@ -22,6 +19,8 @@

 #include <FEXCore/Config/Config.h>
 #include <FEXCore/fextl/vector.h>
+#include <CodeEmitter/Emitter.h>
+#include <CodeEmitter/Registers.h>

 #include <array>
 #include <cstddef>
@@ -35,86 +34,85 @@ class ContextImpl;

 namespace FEXCore::CPU {
 // Contains the address to the currently available CPU state
-constexpr auto STATE = FEXCore::ARMEmitter::XReg::x28;
+constexpr auto STATE = ARMEmitter::XReg::x28;

 #ifndef _M_ARM_64EC
 // GPR temporaries. Only x3 can be used across spill boundaries
 // so if these ever need to change, be very careful about that.
-constexpr auto TMP1 = FEXCore::ARMEmitter::XReg::x0;
-constexpr auto TMP2 = FEXCore::ARMEmitter::XReg::x1;
-constexpr auto TMP3 = FEXCore::ARMEmitter::XReg::x2;
-constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x3;
+constexpr auto TMP1 = ARMEmitter::XReg::x0;
+constexpr auto TMP2 = ARMEmitter::XReg::x1;
+constexpr auto TMP3 = ARMEmitter::XReg::x2;
+constexpr auto TMP4 = ARMEmitter::XReg::x3;
 constexpr bool TMP_ABIARGS = true;

 // We pin r26/r27 as PF/AF respectively, this is internal FEX ABI.
-constexpr auto REG_PF = FEXCore::ARMEmitter::Reg::r26;
-constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r27;
+constexpr auto REG_PF = ARMEmitter::Reg::r26;
+constexpr auto REG_AF = ARMEmitter::Reg::r27;

 // Vector temporaries
-constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v0;
-constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v1;
+constexpr auto VTMP1 = ARMEmitter::VReg::v0;
+constexpr auto VTMP2 = ARMEmitter::VReg::v1;
 #else
-constexpr auto TMP1 = FEXCore::ARMEmitter::XReg::x10;
-constexpr auto TMP2 = FEXCore::ARMEmitter::XReg::x11;
-constexpr auto TMP3 = FEXCore::ARMEmitter::XReg::x12;
-constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x13;
+constexpr auto TMP1 = ARMEmitter::XReg::x10;
+constexpr auto TMP2 = ARMEmitter::XReg::x11;
+constexpr auto TMP3 = ARMEmitter::XReg::x12;
+constexpr auto TMP4 = ARMEmitter::XReg::x13;
 constexpr bool TMP_ABIARGS = false;

 // We pin r11/r12 as PF/AF respectively for arm64ec, as r26/r27 are used for SRA.
-constexpr auto REG_PF = FEXCore::ARMEmitter::Reg::r9;
-constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r24;
+constexpr auto REG_PF = ARMEmitter::Reg::r9;
+constexpr auto REG_AF = ARMEmitter::Reg::r24;

 // Vector temporaries
-constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v16;
-constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v17;
+constexpr auto VTMP1 = ARMEmitter::VReg::v16;
+constexpr auto VTMP2 = ARMEmitter::VReg::v17;
+
+// Entry/Exit ABI
+constexpr auto EC_CALL_CHECKER_PC_REG = ARMEmitter::XReg::x9;
+constexpr auto EC_ENTRY_CPUAREA_REG = ARMEmitter::XReg::x17;
+
+// These structures are not included in the standard Windows headers, define the offsets of members we care about for EC here.
+constexpr size_t TEB_CPU_AREA_OFFSET = 0x1788;
+constexpr size_t TEB_PEB_OFFSET = 0x60;
+constexpr size_t PEB_EC_CODE_BITMAP_OFFSET = 0x368;
+constexpr size_t CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET = 0x1;
+constexpr size_t CPU_AREA_EMULATOR_STACK_BASE_OFFSET = 0x8;
+constexpr size_t CPU_AREA_EMULATOR_DATA_OFFSET = 0x30;
 #endif

 // Predicate register temporaries (used when AVX support is enabled)
 // PRED_TMP_16B indicates a predicate register that indicates the first 16 bytes set to 1.
 // PRED_TMP_32B indicates a predicate register that indicates the first 32 bytes set to 1.
-constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_16B = FEXCore::ARMEmitter::PReg::p6;
-constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_32B = FEXCore::ARMEmitter::PReg::p7;
+constexpr ARMEmitter::PRegister PRED_TMP_16B = ARMEmitter::PReg::p6;
+constexpr ARMEmitter::PRegister PRED_TMP_32B = ARMEmitter::PReg::p7;


 // This class contains common emitter utility functions that can
 // be used by both Arm64 JIT and ARM64 Dispatcher
-class Arm64Emitter : public FEXCore::ARMEmitter::Emitter {
+class Arm64Emitter : public ARMEmitter::Emitter {
 protected:
  Arm64Emitter(FEXCore::Context::ContextImpl* ctx, void* EmissionPtr = nullptr, size_t size = 0);

  FEXCore::Context::ContextImpl* EmitterCTX;
-  vixl::aarch64::CPU CPU;

-  std::span<const FEXCore::ARMEmitter::Register> ConfiguredDynamicRegisterBase {};
-  std::span<const FEXCore::ARMEmitter::Register> StaticRegisters {};
-  std::span<const FEXCore::ARMEmitter::Register> GeneralRegisters {};
-  std::span<const std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>> GeneralPairRegisters {};
-  std::span<const FEXCore::ARMEmitter::VRegister> StaticFPRegisters {};
-  std::span<const FEXCore::ARMEmitter::VRegister> GeneralFPRegisters {};
+  std::span<const ARMEmitter::Register> ConfiguredDynamicRegisterBase {};
+  std::span<const ARMEmitter::Register> StaticRegisters {};
+  std::span<const ARMEmitter::Register> GeneralRegisters {};
+  std::span<const ARMEmitter::VRegister> StaticFPRegisters {};
+  std::span<const ARMEmitter::VRegister> GeneralFPRegisters {};
+  uint32_t PairRegisters = 0;

-  /**
-   * @name Register Allocation
-   * @{ */
-  constexpr static uint32_t RegisterClasses = 6;
-
-  constexpr static uint64_t GPRBase = (0ULL << 32);
-  constexpr static uint64_t FPRBase = (1ULL << 32);
-  constexpr static uint64_t GPRPairBase = (2ULL << 32);
-
-  /**  @} */
-
-  constexpr static uint8_t RA_32 = 0;
-  constexpr static uint8_t RA_64 = 1;
-  constexpr static uint8_t RA_FPR = 2;
-
-  void LoadConstant(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad = false);
+  void LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad = false);

+  void FillSpecialRegs(ARMEmitter::Register TmpReg, ARMEmitter::Register TmpReg2, bool SetFIZ, bool SetPredRegs);

  // NOTE: These functions WILL clobber the register TMP4 if AVX support is enabled
  //       and FPRs are being spilled or filled. If only GPRs are spilled/filled, then
  //       TMP4 is left alone.
-  void SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
-  void FillStaticRegs(bool FPRs = true, uint32_t GPRFillMask = ~0U, uint32_t FPRFillMask = ~0U);
+  void SpillStaticRegs(ARMEmitter::Register TmpReg, bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
+  void FillStaticRegs(bool FPRs = true, uint32_t GPRFillMask = ~0U, uint32_t FPRFillMask = ~0U,
+                      std::optional<ARMEmitter::Register> OptionalReg = std::nullopt,
+                      std::optional<ARMEmitter::Register> OptionalReg2 = std::nullopt);

  // Register 0-18 + 29 + 30 are caller saved
  static constexpr uint32_t CALLER_GPR_MASK = 0b0110'0000'0000'0111'1111'1111'1111'1111U;
@@ -124,13 +122,13 @@ protected:
  static constexpr uint32_t CALLER_FPR_MASK = ~0U;

  // Generic push and pop vector registers.
-  void PushVectorRegisters(FEXCore::ARMEmitter::Register TmpReg, bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs);
-  void PushGeneralRegisters(FEXCore::ARMEmitter::Register TmpReg, std::span<const FEXCore::ARMEmitter::Register> Regs);
+  void PushVectorRegisters(ARMEmitter::Register TmpReg, bool SVERegs, std::span<const ARMEmitter::VRegister> VRegs);
+  void PushGeneralRegisters(ARMEmitter::Register TmpReg, std::span<const ARMEmitter::Register> Regs);

-  void PopVectorRegisters(bool SVERegs, std::span<const FEXCore::ARMEmitter::VRegister> VRegs);
-  void PopGeneralRegisters(std::span<const FEXCore::ARMEmitter::Register> Regs);
+  void PopVectorRegisters(bool SVERegs, std::span<const ARMEmitter::VRegister> VRegs);
+  void PopGeneralRegisters(std::span<const ARMEmitter::Register> Regs);

-  void PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg);
+  void PushDynamicRegsAndLR(ARMEmitter::Register TmpReg);
  void PopDynamicRegsAndLR();

  void PushCalleeSavedRegisters();
@@ -146,10 +144,10 @@ protected:
  // Callee Saved:
  // - X9-X15, X19-X31
  // - Low 128-bits of v8-v31
-  void SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true);
+  void SpillForPreserveAllABICall(ARMEmitter::Register TmpReg, bool FPRs = true);
  void FillForPreserveAllABICall(bool FPRs = true);

-  void SpillForABICall(bool SupportsPreserveAllABI, FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true) {
+  void SpillForABICall(bool SupportsPreserveAllABI, ARMEmitter::Register TmpReg, bool FPRs = true) {
    if (SupportsPreserveAllABI) {
      SpillForPreserveAllABICall(TmpReg, FPRs);
    } else {
@@ -19,6 +19,10 @@ namespace CPU {
    {0x0000'0000'8000'0000ULL, 0x0000'0000'8000'0000ULL}, // NAMED_VECTOR_PADDSUBPS_INVERT_UPPER
    {0x8000'0000'0000'0000ULL, 0x0000'0000'0000'0000ULL}, // NAMED_VECTOR_PADDSUBPD_INVERT
    {0x8000'0000'0000'0000ULL, 0x0000'0000'0000'0000ULL}, // NAMED_VECTOR_PADDSUBPD_INVERT_UPPER
+    {0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPS_INVERT
+    {0x8000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPS_INVERT_UPPER
+    {0x0000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPD_INVERT
+    {0x0000'0000'0000'0000ULL, 0x8000'0000'0000'0000ULL}, // NAMED_VECTOR_PSUBADDPD_INVERT_UPPER
    {0x0000'0001'0000'0000ULL, 0x0000'0003'0000'0002ULL}, // NAMED_VECTOR_MOVMSKPS_SHIFT
    {0x040B'0E01'0B0E'0104ULL, 0x0C03'0609'0306'090CULL}, // NAMED_VECTOR_AESKEYGENASSIST_SWIZZLE
    {0x0706'0504'FFFF'FFFFULL, 0xFFFF'FFFF'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_0110B
@@ -34,12 +34,6 @@ namespace CodeSerialize {
 }

 namespace CPU {
-  struct CPUBackendFeatures {
-    bool SupportsFlags = false;
-    bool SupportsSaturatingRoundingShifts = false;
-    bool SupportsVTBL2 = false;
-  };
-
  class CPUBackend {
  public:
    struct CodeBuffer {
@@ -140,7 +134,7 @@ namespace CPU {
     */
    [[nodiscard]]
    virtual CompiledCode CompileCode(uint64_t Entry, const FEXCore::IR::IRListView* IR, FEXCore::Core::DebugData* DebugData,
-                                     FEXCore::IR::RegisterAllocationData* RAData) = 0;
+                                     const FEXCore::IR::RegisterAllocationData* RAData) = 0;

    /**
     * @brief Relocates a block of code from the JIT code object cache
@@ -34,6 +34,8 @@ namespace ProductNames {
  static const char ARM_A76AE[] = "Cortex-A76AE";
  static const char ARM_V1[] = "Neoverse V1";
  static const char ARM_V2[] = "Neoverse V2";
+  static const char ARM_V3[] = "Neoverse V3";
+  static const char ARM_V3AE[] = "Neoverse V3AE";
  static const char ARM_A77[] = "Cortex-A77";
  static const char ARM_A78[] = "Cortex-A78";
  static const char ARM_A78AE[] = "Cortex-A78AE";
@@ -41,13 +43,16 @@ namespace ProductNames {
  static const char ARM_A710[] = "Cortex-A710";
  static const char ARM_A715[] = "Cortex-A715";
  static const char ARM_A720[] = "Cortex-A720";
+  static const char ARM_A725[] = "Cortex-A725";
  static const char ARM_X1[] = "Cortex-X1";
  static const char ARM_X1C[] = "Cortex-X1C";
  static const char ARM_X2[] = "Cortex-X2";
  static const char ARM_X3[] = "Cortex-X3";
  static const char ARM_X4[] = "Cortex-X4";
+  static const char ARM_X925[] = "Cortex-X925";
  static const char ARM_N1[] = "Neoverse N1";
  static const char ARM_N2[] = "Neoverse N2";
+  static const char ARM_N3[] = "Neoverse N3";
  static const char ARM_E1[] = "Neoverse E1";
  static const char ARM_A35[] = "Cortex-A35";
  static const char ARM_A53[] = "Cortex-A53";
@@ -69,6 +74,8 @@ namespace ProductNames {

  static const char ARM_Firestorm[] = "Apple Firestorm";
  static const char ARM_Icestorm[] = "Apple Icestorm";
+
+  static const char ARM_ORYON_1[] = "Oryon-1";
 #else
 #endif
 } // namespace ProductNames
@@ -140,10 +147,17 @@ void CPUIDEmu::SetupHostHybridFlag() {
  // CPU priority order
  // This is mostly arbitrary but will sort by some sort of CPU priority by performance
  // Relative list so things they will commonly end up in big.little configurations sort of relate
-  static constexpr std::array<CPUMIDR, 42> CPUMIDRs = {{
+  static constexpr std::array<CPUMIDR, 48> CPUMIDRs = {{
    // Typically big CPU cores
+    {0x51, 0x001, 1, ProductNames::ARM_ORYON_1}, // Qualcomm Oryon-1
+
    {0x61, 0x023, 1, ProductNames::ARM_Firestorm}, // Apple M1 Firestorm

+    {0x41, 0xd85, 1, ProductNames::ARM_X925},    // X925
+    {0x41, 0xd87, 1, ProductNames::ARM_A725},    // A725
+    {0x41, 0xd84, 1, ProductNames::ARM_V3},      // V3
+    {0x41, 0xd83, 1, ProductNames::ARM_V3AE},    // V3AE
+    {0x41, 0xd8e, 1, ProductNames::ARM_N3},      // N3
    {0x41, 0xd82, 1, ProductNames::ARM_X4},      // X4
    {0x41, 0xd81, 1, ProductNames::ARM_A720},    // A720
    {0x41, 0xd4e, 1, ProductNames::ARM_X3},      // X3
@@ -343,8 +357,7 @@ void CPUIDEmu::SetupHostHybridFlag() {}


 void CPUIDEmu::SetupFeatures() {
-  // TODO: Enable once AVX is supported.
-  if (false && CTX->HostFeatures.SupportsAVX) {
+  if (CTX->HostFeatures.SupportsAVX) {
    XCR0 |= XCR0_AVX;
  }

@@ -355,14 +368,14 @@ void CPUIDEmu::SetupFeatures() {
    return;
  }

-#define ENABLE_DISABLE_OPTION(FeatureName, name, enum_name) \
-  do { \
-    const bool Disable##name = (CPUIDFeatures() & FEXCore::Config::CPUID::DISABLE##enum_name) != 0; \
-    const bool Enable##name = (CPUIDFeatures() & FEXCore::Config::CPUID::ENABLE##enum_name) != 0; \
+#define ENABLE_DISABLE_OPTION(FeatureName, name, enum_name)                                                                        \
+  do {                                                                                                                             \
+    const bool Disable##name = (CPUIDFeatures() & FEXCore::Config::CPUID::DISABLE##enum_name) != 0;                                \
+    const bool Enable##name = (CPUIDFeatures() & FEXCore::Config::CPUID::ENABLE##enum_name) != 0;                                  \
    LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive"); \
-    const bool AlreadyEnabled = Features.FeatureName; \
-    const bool Result = (AlreadyEnabled | Enable##name) & !Disable##name; \
-    Features.FeatureName = Result; \
+    const bool AlreadyEnabled = Features.FeatureName;                                                                              \
+    const bool Result = (AlreadyEnabled | Enable##name) & !Disable##name;                                                          \
+    Features.FeatureName = Result;                                                                                                 \
  } while (0)

  ENABLE_DISABLE_OPTION(SHA, SHA, SHA);
@@ -413,7 +426,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) const {
            (1 << 9) |                                      // SSSE3
            (0 << 10) |                                     // L1 context ID
            (0 << 11) |                                     // Silicon debug
-            (0 << 12) |                                     // FMA3
+            (SupportsAVX() << 12) |                         // FMA3
            (1 << 13) |                                     // CMPXCHG16B
            (0 << 14) |                                     // xTPR update control
            (0 << 15) |                                     // Perfmon and debug capability
@@ -430,7 +443,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) const {
            (SupportsAVX() << 26) |                         // XSAVE
            (SupportsAVX() << 27) |                         // OSXSAVE
            (SupportsAVX() << 28) |                         // AVX
-            (0 << 29) |                                     // F16C
+            (SupportsAVX() << 29) |                         // F16C
            (CTX->HostFeatures.SupportsRAND << 30) |        // RDRAND
            (Hypervisor << 31);

@@ -597,6 +610,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
    // This is due to LRCPC performance on Cortex being abysmal.
    // Only enable EnhancedREPMOVS if SoftwareTSO isn't required OR if MemcpySetTSO is not enabled.
    const uint32_t SupportsEnhancedREPMOVS = CTX->SoftwareTSORequired() == false || MemcpySetTSOEnabled() == false;
+    const uint32_t SupportsVPCLMULQDQ = CTX->HostFeatures.SupportsPMULL_128Bit && SupportsAVX();

    // Number of subfunctions
    Res.eax = 0x0;
@@ -605,7 +619,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
              (0 << 2) |                               // SGX
              (SupportsAVX() << 3) |                   // BMI1
              (0 << 4) |                               // Intel Hardware Lock Elison
-              (0 << 5) |                               // AVX2 support
+              (SupportsAVX() << 5) |                   // AVX2 support
              (1 << 6) |                               // FPU data pointer updated only on exception
              (1 << 7) |                               // SMEP support
              (SupportsAVX() << 8) |                   // BMI2
@@ -624,7 +638,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
              (0 << 21) |                              // Reserved
              (0 << 22) |                              // Reserved
              (1 << 23) |                              // CLFLUSHOPT instruction
-              (CTX->HostFeatures.SupportsCLWB << 24) | // CLWB instruction
+              (1 << 24) |                              // CLWB instruction
              (0 << 25) |                              // Intel processor trace
              (0 << 26) |                              // Reserved
              (0 << 27) |                              // Reserved
@@ -633,38 +647,38 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
              (0 << 30) |                              // Reserved
              (0 << 31);                               // Reserved

-    Res.ecx = (1 << 0) |  // PREFETCHWT1
-              (0 << 1) |  // AVX512VBMI
-              (0 << 2) |  // Usermode instruction prevention
-              (0 << 3) |  // Protection keys for user mode pages
-              (0 << 4) |  // OS protection keys
-              (0 << 5) |  // waitpkg
-              (0 << 6) |  // AVX512_VBMI2
-              (0 << 7) |  // CET shadow stack
-              (0 << 8) |  // GFNI
-              (0 << 9) |  // VAES
-              (0 << 10) | // VPCLMULQDQ
-              (0 << 11) | // AVX512_VNNI
-              (0 << 12) | // AVX512_BITALG
-              (0 << 13) | // Intel Total Memory Encryption
-              (0 << 14) | // AVX512_VPOPCNTDQ
-              (0 << 15) | // Reserved
-              (0 << 16) | // 5 Level page tables
-              (0 << 17) | // MPX MAWAU
-              (0 << 18) | // MPX MAWAU
-              (0 << 19) | // MPX MAWAU
-              (0 << 20) | // MPX MAWAU
-              (0 << 21) | // MPX MAWAU
-              (1 << 22) | // RDPID Read Processor ID
-              (0 << 23) | // Reserved
-              (0 << 24) | // Reserved
-              (0 << 25) | // CLDEMOTE
-              (0 << 26) | // Reserved
-              (0 << 27) | // MOVDIRI
-              (0 << 28) | // MOVDIR64B
-              (0 << 29) | // Reserved
-              (0 << 30) | // SGX Launch configuration
-              (0 << 31);  // Reserved
+    Res.ecx = (1 << 0) |                                // PREFETCHWT1
+              (0 << 1) |                                // AVX512VBMI
+              (0 << 2) |                                // Usermode instruction prevention
+              (0 << 3) |                                // Protection keys for user mode pages
+              (0 << 4) |                                // OS protection keys
+              (0 << 5) |                                // waitpkg
+              (0 << 6) |                                // AVX512_VBMI2
+              (0 << 7) |                                // CET shadow stack
+              (0 << 8) |                                // GFNI
+              (CTX->HostFeatures.SupportsAES256 << 9) | // VAES
+              (SupportsVPCLMULQDQ << 10) |              // VPCLMULQDQ
+              (0 << 11) |                               // AVX512_VNNI
+              (0 << 12) |                               // AVX512_BITALG
+              (0 << 13) |                               // Intel Total Memory Encryption
+              (0 << 14) |                               // AVX512_VPOPCNTDQ
+              (0 << 15) |                               // Reserved
+              (0 << 16) |                               // 5 Level page tables
+              (0 << 17) |                               // MPX MAWAU
+              (0 << 18) |                               // MPX MAWAU
+              (0 << 19) |                               // MPX MAWAU
+              (0 << 20) |                               // MPX MAWAU
+              (0 << 21) |                               // MPX MAWAU
+              (1 << 22) |                               // RDPID Read Processor ID
+              (0 << 23) |                               // Reserved
+              (0 << 24) |                               // Reserved
+              (0 << 25) |                               // CLDEMOTE
+              (0 << 26) |                               // Reserved
+              (0 << 27) |                               // MOVDIRI
+              (0 << 28) |                               // MOVDIR64B
+              (0 << 29) |                               // Reserved
+              (0 << 30) |                               // SGX Launch configuration
+              (0 << 31);                                // Reserved

    Res.edx = (0 << 0) |                   // Reserved
              (0 << 1) |                   // Reserved
@@ -883,7 +897,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h(uint32_t Leaf) con
            (0 << 18) | // Reserved
            (0 << 19) | // Reserved
            (0 << 20) | // Reserved
-            (0 << 21) | // Reserved
+            (0 << 21) | // XOP-TBM
            (0 << 22) | // Topology extensions support
            (0 << 23) | // Core performance counter extensions
            (0 << 24) | // NB performance counter extensions
@@ -891,7 +905,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h(uint32_t Leaf) con
            (0 << 26) | // Data breakpoints extensions
            (0 << 27) | // Performance TSC
            (0 << 28) | // L2 perf counter extensions
-            (0 << 29) | // Reserved
+            (0 << 29) | // MONITORX
            (0 << 30) | // Reserved
            (0 << 31);  // Reserved

@@ -38,7 +38,6 @@ $end_info$
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/HLE/SourcecodeResolver.h>
-#include <FEXCore/HLE/Linux/ThreadManagement.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/File.h>
@@ -75,8 +74,9 @@ $end_info$
 #include <xxhash.h>

 namespace FEXCore::Context {
-ContextImpl::ContextImpl()
-  : CPUID {this}
+ContextImpl::ContextImpl(const FEXCore::HostFeatures& Features)
+  : HostFeatures {Features}
+  , CPUID {this}
  , IRCaptureCache {this} {
 #ifdef BLOCKSTATS
  BlockData = std::make_unique<FEXCore::BlockSamplingData>();
@@ -216,6 +216,55 @@ uint32_t ContextImpl::ReconstructCompactedEFLAGS(FEXCore::Core::InternalThreadSt
  return EFLAGS;
 }

+void ContextImpl::ReconstructXMMRegisters(const FEXCore::Core::InternalThreadState* Thread, __uint128_t* XMM_Low, __uint128_t* YMM_High) {
+  const size_t MaximumRegisters = Config.Is64BitMode ? FEXCore::Core::CPUState::NUM_XMMS : 8;
+
+  if (YMM_High != nullptr && HostFeatures.SupportsAVX) {
+    const bool SupportsConvergedRegisters = HostFeatures.SupportsSVE256;
+
+    if (SupportsConvergedRegisters) {
+      ///< Output wants to de-interleave
+      for (size_t i = 0; i < MaximumRegisters; ++i) {
+        memcpy(&XMM_Low[i], &Thread->CurrentFrame->State.xmm.avx.data[i][0], sizeof(__uint128_t));
+        memcpy(&YMM_High[i], &Thread->CurrentFrame->State.xmm.avx.data[i][2], sizeof(__uint128_t));
+      }
+    } else {
+      ///< Matches what FEX wants with non-converged registers
+      for (size_t i = 0; i < MaximumRegisters; ++i) {
+        memcpy(&XMM_Low[i], &Thread->CurrentFrame->State.xmm.sse.data[i][0], sizeof(__uint128_t));
+        memcpy(&YMM_High[i], &Thread->CurrentFrame->State.avx_high[i][0], sizeof(__uint128_t));
+      }
+    }
+  } else {
+    // Only support SSE, no AVX here, even if requested.
+    memcpy(XMM_Low, Thread->CurrentFrame->State.xmm.sse.data, MaximumRegisters * sizeof(__uint128_t));
+  }
+}
+
+void ContextImpl::SetXMMRegistersFromState(FEXCore::Core::InternalThreadState* Thread, const __uint128_t* XMM_Low, const __uint128_t* YMM_High) {
+  const size_t MaximumRegisters = Config.Is64BitMode ? FEXCore::Core::CPUState::NUM_XMMS : 8;
+  if (YMM_High != nullptr && HostFeatures.SupportsAVX) {
+    const bool SupportsConvergedRegisters = HostFeatures.SupportsSVE256;
+
+    if (SupportsConvergedRegisters) {
+      ///< Output wants to de-interleave
+      for (size_t i = 0; i < MaximumRegisters; ++i) {
+        memcpy(&Thread->CurrentFrame->State.xmm.avx.data[i][0], &XMM_Low[i], sizeof(__uint128_t));
+        memcpy(&Thread->CurrentFrame->State.xmm.avx.data[i][2], &YMM_High[i], sizeof(__uint128_t));
+      }
+    } else {
+      ///< Matches what FEX wants with non-converged registers
+      for (size_t i = 0; i < MaximumRegisters; ++i) {
+        memcpy(&Thread->CurrentFrame->State.xmm.sse.data[i][0], &XMM_Low[i], sizeof(__uint128_t));
+        memcpy(&Thread->CurrentFrame->State.avx_high[i][0], &YMM_High[i], sizeof(__uint128_t));
+      }
+    }
+  } else {
+    // Only support SSE, no AVX here, even if requested.
+    memcpy(Thread->CurrentFrame->State.xmm.sse.data, XMM_Low, MaximumRegisters * sizeof(__uint128_t));
+  }
+}
+
 void ContextImpl::SetFlagsFromCompactedEFLAGS(FEXCore::Core::InternalThreadState* Thread, uint32_t EFLAGS) {
  const auto Frame = Thread->CurrentFrame;
  for (size_t i = 0; i < FEXCore::Core::CPUState::NUM_EFLAG_BITS; ++i) {
@@ -260,14 +309,6 @@ void ContextImpl::SetFlagsFromCompactedEFLAGS(FEXCore::Core::InternalThreadState

 bool ContextImpl::InitCore() {
  // Initialize the CPU core signal handlers & DispatcherConfig
-  switch (Config.Core) {
-  case FEXCore::Config::CONFIG_IRJIT: BackendFeatures = FEXCore::CPU::GetArm64JITBackendFeatures(); break;
-  case FEXCore::Config::CONFIG_CUSTOM:
-    // Do nothing
-    break;
-  default: LogMan::Msg::EFmt("Unknown core configuration"); return false;
-  }
-
  Dispatcher = FEXCore::CPU::Dispatcher::Create(this);

  // Set up the SignalDelegator config since core is initialized.
@@ -324,14 +365,15 @@ void ContextImpl::HandleCallback(FEXCore::Core::InternalThreadState* Thread, uin

 FEXCore::Context::ExitReason ContextImpl::RunUntilExit(FEXCore::Core::InternalThreadState* Thread) {
  ExecutionThread(Thread);
-  while (true) {
-    auto reason = Thread->ExitReason;

-    // Don't return if a custom exit handling the exit
-    if (!CustomExitHandler || reason == ExitReason::EXIT_SHUTDOWN) {
-      return reason;
-    }
+  CoreShuttingDown.store(true);
+
+  if (CustomExitHandler) {
+    CustomExitHandler(Thread, FEXCore::Context::ExitReason::EXIT_SHUTDOWN);
+    return Thread->ExitReason;
  }
+
+  return FEXCore::Context::ExitReason::EXIT_SHUTDOWN;
 }

 void ContextImpl::ExecuteThread(FEXCore::Core::InternalThreadState* Thread) {
@@ -341,9 +383,6 @@ void ContextImpl::ExecuteThread(FEXCore::Core::InternalThreadState* Thread) {

 void ContextImpl::InitializeThreadTLSData(FEXCore::Core::InternalThreadState* Thread) {
  // Let's do some initial bookkeeping here
-  Thread->ThreadManager.TID = FHU::Syscalls::gettid();
-  Thread->ThreadManager.PID = ::getpid();
-
  if (ThunkHandler) {
    ThunkHandler->RegisterTLSState(Thread);
  }
@@ -366,7 +405,7 @@ void ContextImpl::InitializeCompiler(FEXCore::Core::InternalThreadState* Thread)

  Thread->CTX = this;

-  Thread->PassManager->AddDefaultPasses(this, Config.Core == FEXCore::Config::CONFIG_IRJIT);
+  Thread->PassManager->AddDefaultPasses(this);
  Thread->PassManager->AddDefaultValidationPasses();

  Thread->PassManager->RegisterSyscallHandler(SyscallHandler);
@@ -374,7 +413,7 @@ void ContextImpl::InitializeCompiler(FEXCore::Core::InternalThreadState* Thread)
  // Create CPU backend
  switch (Config.Core) {
  case FEXCore::Config::CONFIG_IRJIT:
-    Thread->PassManager->InsertRegisterAllocationPass(HostFeatures.SupportsAVX);
+    Thread->PassManager->InsertRegisterAllocationPass();
    Thread->CPUBackend = FEXCore::CPU::CreateArm64JITCore(this, Thread);
    break;
  case FEXCore::Config::CONFIG_CUSTOM: Thread->CPUBackend = CustomCPUFactory(this, Thread); break;
@@ -397,14 +436,11 @@ ContextImpl::CreateThread(uint64_t InitialRIP, uint64_t StackPointer, FEXCore::C
  }

  // Set up the thread manager state
-  Thread->ThreadManager.parent_tid = ParentTID;
  Thread->CurrentFrame->Thread = Thread;

  InitializeCompiler(Thread);

  Thread->CurrentFrame->State.DeferredSignalRefCount.Store(0);
-  Thread->CurrentFrame->State.DeferredSignalFaultAddress =
-    reinterpret_cast<Core::NonAtomicRefCounter<uint64_t>*>(FEXCore::Allocator::VirtualAlloc(4096));

  if (Config.BlockJITNaming() || Config.GlobalJITNaming() || Config.LibraryJITNaming()) {
    // Allocate a JIT symbol buffer only if enabled.
@@ -421,7 +457,8 @@ void ContextImpl::DestroyThread(FEXCore::Core::InternalThreadState* Thread, bool
 #endif
  }

-  FEXCore::Allocator::VirtualFree(reinterpret_cast<void*>(Thread->CurrentFrame->State.DeferredSignalFaultAddress), 4096);
+  FEXCore::Allocator::VirtualProtect(&Thread->InterruptFaultPage, sizeof(Thread->InterruptFaultPage),
+                                     Allocator::ProtectOptions::Read | Allocator::ProtectOptions::Write);
  delete Thread;
 }

@@ -469,29 +506,39 @@ static void IRDumper(FEXCore::Core::InternalThreadState* Thread, IR::IREmitter*
  fextl::fmt::print(FD, "IR-ShouldDump-{} 0x{:x}:\n{}\n@@@@@\n", RA ? "post" : "pre", GuestRIP, out.str());
 };

-static void ValidateIR(ContextImpl* ctx, IR::IREmitter* IREmitter) {
-  // Convert to text, Parse, Convert to text again and make sure the texts match
-  fextl::stringstream out;
-  static auto compaction = IR::CreateIRCompaction(ctx->OpDispatcherAllocator);
-  compaction->Run(IREmitter);
-  auto NewIR = IREmitter->ViewIR();
-  Dump(&out, &NewIR, nullptr);
-  out.seekg(0);
-  FEXCore::Utils::PooledAllocatorMalloc Allocator;
-  auto reparsed = IR::Parse(Allocator, out);
-  if (reparsed == nullptr) {
-    LOGMAN_MSG_A_FMT("Failed to parse IR\n");
-  } else {
-    fextl::stringstream out2;
-    auto NewIR2 = reparsed->ViewIR();
-    Dump(&out2, &NewIR2, nullptr);
-    if (out.str() != out2.str()) {
-      LogMan::Msg::IFmt("one:\n {}", out.str());
-      LogMan::Msg::IFmt("two:\n {}", out2.str());
-      LOGMAN_MSG_A_FMT("Parsed IR doesn't match\n");
-    }
+// IRStorageBase with fully owned memory
+struct IRListCopy : public IR::IRStorageBase {
+  std::span<std::byte> IRData;
+  std::span<std::byte> ListData;
+
+  // TODO: Consider defaulting to empty RAData instead?
+  IR::RegisterAllocationData::UniquePtr RADataInternal;
+
+  IRListCopy(const IR::IRListView& view, IR::RegisterAllocationData::UniquePtr RAData)
+    : RADataInternal(std::move(RAData)) {
+    std::byte* Storage = reinterpret_cast<std::byte*>(FEXCore::Allocator::malloc(view.GetDataSize() + view.GetListSize()));
+
+    IRData = {Storage, Storage + view.GetDataSize()};
+    ListData = {Storage + view.GetDataSize(), Storage + view.GetDataSize() + view.GetListSize()};
+    memcpy(IRData.data(), (char*)view.GetData(), IRData.size());
+    memcpy(ListData.data(), (char*)view.GetListData(), ListData.size());
  }
-}
+
+  IRListCopy(const IRListCopy& other) = delete;
+  IRListCopy(IRListCopy&& other) = delete;
+
+  ~IRListCopy() {
+    FEXCore::Allocator::free(IRData.data());
+  }
+
+  const IR::RegisterAllocationData* RAData() override {
+    return RADataInternal.get();
+  }
+  IR::IRListView GetIRView() override {
+    return IR::IRListView {IRData.data(), ListData.data(), IRData.size(), ListData.size()};
+  }
+};
+

 ContextImpl::GenerateIRResult
 ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP, bool ExtendedDebugInfo, uint64_t MaxInst) {
@@ -556,6 +603,20 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
        DecodedInfo = &Block.DecodedInstructions[i];
        bool IsLocked = DecodedInfo->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_LOCK;

+        // Do a partial register cache flush before every instruction. This
+        // prevents cross-instruction static register caching, while allowing
+        // context load/stores to be optimized within a block. Theoretically,
+        // this flush is not required for correctness, all mandatory flushes are
+        // included in instruction-specific handlers. Instead, this is a blunt
+        // heuristic to make the register cache less aggressive, as the current
+        // RA generates bad code in common cases with tied registers otherwise.
+        //
+        // However, it makes our exception handling behaviour more predictable.
+        // It is potentially correctness bearing in that sense, but that is a
+        // side effect here and (if that behaviour is required) we should handle
+        // that more explicitly later.
+        Thread->OpDispatcher->FlushRegisterCache(true);
+
        if (ExtendedDebugInfo || Thread->OpDispatcher->CanHaveSideEffects(TableInfo, DecodedInfo)) {
          Thread->OpDispatcher->_GuestOpcode(Block.Entry + BlockInstructionsLength - GuestRIP);
        }
@@ -574,7 +635,7 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue

          Thread->OpDispatcher->SetCurrentCodeBlock(CodeWasChangedBlock);
          Thread->OpDispatcher->_ThreadRemoveCodeEntry();
-          Thread->OpDispatcher->_ExitFunction(
+          Thread->OpDispatcher->ExitFunction(
            Thread->OpDispatcher->_EntrypointOffset(IR::SizeToOpSize(GPRSize), Block.Entry + BlockInstructionsLength - GuestRIP));

          auto NextOpBlock = Thread->OpDispatcher->CreateNewCodeBlockAfter(CurrentBlock);
@@ -605,7 +666,7 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
          }
          // Invalid instruction
          Thread->OpDispatcher->InvalidOp(DecodedInfo);
-          Thread->OpDispatcher->_ExitFunction(Thread->OpDispatcher->_EntrypointOffset(IR::SizeToOpSize(GPRSize), Block.Entry - GuestRIP));
+          Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_EntrypointOffset(IR::SizeToOpSize(GPRSize), Block.Entry - GuestRIP));
        }

        const bool NeedsBlockEnd =
@@ -615,14 +676,14 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
        if (HadDispatchError && TotalInstructions == 0) {
          // Couldn't handle any instruction in op dispatcher
          Thread->OpDispatcher->ResetWorkingList();
-          return {nullptr, nullptr, 0, 0, 0, 0};
+          return {nullptr, 0, 0, 0, 0};
        }

        if (NeedsBlockEnd) {
          const uint8_t GPRSize = GetGPRSize();

          // We had some instructions. Early exit
-          Thread->OpDispatcher->_ExitFunction(
+          Thread->OpDispatcher->ExitFunction(
            Thread->OpDispatcher->_EntrypointOffset(IR::SizeToOpSize(GPRSize), Block.Entry + BlockInstructionsLength - GuestRIP));
          break;
        }
@@ -643,35 +704,26 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue

  auto ShouldDump = Thread->OpDispatcher->ShouldDumpIR();
  // Debug
-  {
-    if (ShouldDump) {
-      IRDumper(Thread, IREmitter, GuestRIP, nullptr);
-    }
-
-    if (static_cast<ContextImpl*>(Thread->CTX)->Config.ValidateIRarser) {
-      ValidateIR(this, IREmitter);
-    }
+  if (ShouldDump) {
+    IRDumper(Thread, IREmitter, GuestRIP, nullptr);
  }

  // Run the passmanager over the IR from the dispatcher
  Thread->PassManager->Run(IREmitter);

  // Debug
-  {
-    if (ShouldDump) {
-      IRDumper(Thread, IREmitter, GuestRIP,
-               Thread->PassManager->HasPass("RA") ? Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA")->GetAllocationData() : nullptr);
-    }
+  if (ShouldDump) {
+    IRDumper(Thread, IREmitter, GuestRIP,
+             Thread->PassManager->HasPass("RA") ? Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA")->GetAllocationData() : nullptr);
  }

  auto RAData = Thread->PassManager->HasPass("RA") ? Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA")->PullAllocationData() : nullptr;
-  auto IRList = IREmitter->CreateIRCopy();
+  auto IRList = fextl::make_unique<IRListCopy>(IREmitter->ViewIR(), std::move(RAData));

  IREmitter->DelayedDisownBuffer();

  return {
-    .IRList = IRList,
-    .RAData = std::move(RAData),
+    .IR = std::move(IRList),
    .TotalInstructions = TotalInstructions,
    .TotalInstructionsLength = TotalInstructionsLength,
    .StartAddr = Thread->FrontendDecoder->DecodedMinAddress,
@@ -680,13 +732,6 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
 }

 ContextImpl::CompileCodeResult ContextImpl::CompileCode(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP, uint64_t MaxInst) {
-  FEXCore::IR::IRListView* IRList {};
-  FEXCore::Core::DebugData* DebugData {};
-  FEXCore::IR::RegisterAllocationData::UniquePtr RAData {};
-  bool GeneratedIR {};
-  uint64_t StartAddr {};
-  uint64_t Length {};
-
  // JIT Code object cache lookup
  if (CodeObjectCacheService) {
    auto CodeCacheEntry = CodeObjectCacheService->FetchCodeObjectFromCache(GuestRIP);
@@ -695,9 +740,8 @@ ContextImpl::CompileCodeResult ContextImpl::CompileCode(FEXCore::Core::InternalT
      if (CompiledCode) {
        return {
          .CompiledCode = CompiledCode,
-          .IRData = nullptr,    // No IR data generated
+          .IR = nullptr,        // No IR/RA data generated
          .DebugData = nullptr, // nullptr here ensures that code serialization doesn't occur on from cache read
-          .RAData = nullptr,    // No RA data generated
          .GeneratedIR = false, // nullptr here ensures IR cache mechanisms won't run
          .StartAddr = 0,       // Unused
          .Length = 0,          // Unused
@@ -713,49 +757,47 @@ ContextImpl::CompileCodeResult ContextImpl::CompileCode(FEXCore::Core::InternalT
    }
  }

+  fextl::unique_ptr<FEXCore::IR::IRStorageBase> IR;
+  FEXCore::Core::DebugData* DebugData {};
+  uint64_t StartAddr {};
+  uint64_t Length {};
+
  // AOT IR bookkeeping and cache
  {
-    auto [IRCopy, RACopy, DebugDataCopy, _StartAddr, _Length, _GeneratedIR] = IRCaptureCache.PreGenerateIRFetch(Thread, GuestRIP, IRList);
-    if (_GeneratedIR) {
+    auto IRFromAOT = IRCaptureCache.PreGenerateIRFetch(Thread, GuestRIP);
+    if (IRFromAOT) {
      // Setup pointers to internal structures
-      IRList = IRCopy;
-      RAData = std::move(RACopy);
-      DebugData = DebugDataCopy;
-      StartAddr = _StartAddr;
-      Length = _Length;
-      GeneratedIR = _GeneratedIR;
+      IR = std::move(IRFromAOT->IR);
+      DebugData = IRFromAOT->DebugData;
+      StartAddr = IRFromAOT->StartAddr;
+      Length = IRFromAOT->Length;
    }
  }

-  if (IRList == nullptr) {
+  if (!IR) {
    // Generate IR + Meta Info
-    auto [IRCopy, RACopy, TotalInstructions, TotalInstructionsLength, _StartAddr, _Length] =
-      GenerateIR(Thread, GuestRIP, Config.GDBSymbols(), MaxInst);
+    auto [IRCopy, TotalInstructions, TotalInstructionsLength, _StartAddr, _Length] = GenerateIR(Thread, GuestRIP, Config.GDBSymbols(), MaxInst);

    // Setup pointers to internal structures
-    IRList = IRCopy;
-    RAData = std::move(RACopy);
+    IR = std::move(IRCopy);
    DebugData = new FEXCore::Core::DebugData();
    StartAddr = _StartAddr;
    Length = _Length;
-
-    // These blocks aren't already in the cache
-    GeneratedIR = true;
  }

-  if (IRList == nullptr) {
+  if (!IR) {
    return {};
  }
  // Attempt to get the CPU backend to compile this code
+  auto IRView = IR->GetIRView();
  return {
    // FEX currently throws away the CPUBackend::CompiledCode object other than the entrypoint
    // In the future with code caching getting wired up, we will pass the rest of the data forward.
    // TODO: Pass the data forward when code caching is wired up to this.
-    .CompiledCode = Thread->CPUBackend->CompileCode(GuestRIP, IRList, DebugData, RAData.get()).BlockEntry,
-    .IRData = IRList,
+    .CompiledCode = Thread->CPUBackend->CompileCode(GuestRIP, &IRView, DebugData, IR->RAData()).BlockEntry,
+    .IR = std::move(IR),
    .DebugData = DebugData,
-    .RAData = std::move(RAData),
-    .GeneratedIR = GeneratedIR,
+    .GeneratedIR = true,
    .StartAddr = StartAddr,
    .Length = Length,
  };
@@ -765,14 +807,6 @@ uintptr_t ContextImpl::CompileBlock(FEXCore::Core::CpuStateFrame* Frame, uint64_
  FEXCORE_PROFILE_SCOPED("CompileBlock");
  auto Thread = Frame->Thread;

-#ifdef _M_ARM_64EC
-  // If the target PC is EC code, mark it in the L2 and return straight to the dispatcher
-  // so it can handle the call/return.
-  if (Thread->LookupCache->CheckPageEC(GuestRIP)) {
-    return GuestRIP;
-  }
-#endif
-
  // Invalidate might take a unique lock on this, to guarantee that during invalidation no code gets compiled
  auto lk = GuardSignalDeferringSection<std::shared_lock>(CodeInvalidationMutex, Thread);

@@ -782,21 +816,7 @@ uintptr_t ContextImpl::CompileBlock(FEXCore::Core::CpuStateFrame* Frame, uint64_
    return HostCode;
  }

-  void* CodePtr {};
-  FEXCore::IR::IRListView* IRList {};
-  FEXCore::Core::DebugData* DebugData {};
-
-  bool GeneratedIR {};
-  uint64_t StartAddr {}, Length {};
-
-  auto [Code, IR, Data, RAData, Generated, _StartAddr, _Length] = CompileCode(Thread, GuestRIP, MaxInst);
-  CodePtr = Code;
-  IRList = IR;
-  DebugData = Data;
-  GeneratedIR = Generated;
-  StartAddr = _StartAddr;
-  Length = _Length;
-
+  auto [CodePtr, IR, DebugData, GeneratedIR, StartAddr, Length] = CompileCode(Thread, GuestRIP, MaxInst);
  if (CodePtr == nullptr) {
    return 0;
  }
@@ -847,7 +867,7 @@ uintptr_t ContextImpl::CompileBlock(FEXCore::Core::CpuStateFrame* Frame, uint64_
  // Clear any relocations that might have been generated
  Thread->CPUBackend->ClearRelocations();

-  if (IRCaptureCache.PostCompileCode(Thread, CodePtr, GuestRIP, StartAddr, Length, std::move(RAData), IRList, DebugData, GeneratedIR)) {
+  if (IRCaptureCache.PostCompileCode(Thread, CodePtr, GuestRIP, StartAddr, Length, std::move(IR), DebugData, GeneratedIR)) {
    // Early exit
    return (uintptr_t)CodePtr;
  }
@@ -893,15 +913,6 @@ void ContextImpl::ExecutionThread(FEXCore::Core::InternalThreadState* Thread) {
  // If it is the parent thread that died then just leave
  FEX_TODO("This doesn't make sense when the parent thread doesn't outlive its children");

-  if (Thread->ThreadManager.parent_tid == 0) {
-    CoreShuttingDown.store(true);
-    Thread->ExitReason = FEXCore::Context::ExitReason::EXIT_SHUTDOWN;
-
-    if (CustomExitHandler) {
-      CustomExitHandler(Thread->ThreadManager.TID, Thread->ExitReason);
-    }
-  }
-
 #ifndef _WIN32
  Alloc::OSAllocator::UninstallTLSData(Thread);
 #endif
@@ -996,7 +1007,7 @@ void ContextImpl::UnloadAOTIRCacheEntry(IR::AOTIRCacheEntry* Entry) {
  IRCaptureCache.UnloadAOTIRCacheEntry(Entry);
 }

-void ContextImpl::AppendThunkDefinitions(const fextl::vector<FEXCore::IR::ThunkDefinition>& Definitions) {
+void ContextImpl::AppendThunkDefinitions(std::span<const FEXCore::IR::ThunkDefinition> Definitions) {
  if (ThunkHandler) {
    ThunkHandler->AppendThunkDefinitions(Definitions);
  }
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: MIT

 #include "Interface/Context/Context.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/X86HelperGen.h"
@@ -17,6 +16,8 @@
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>

+#include <CodeEmitter/Emitter.h>
+
 #include <atomic>
 #include <condition_variable>
 #include <csignal>
@@ -61,9 +62,6 @@ void Dispatcher::EmitDispatcher() {

  ARMEmitter::ForwardLabel l_CTX;
  ARMEmitter::SingleUseForwardLabel l_Sleep;
-#ifdef _M_ARM_64EC
-  ARMEmitter::SingleUseForwardLabel ExitEC;
-#endif
  ARMEmitter::SingleUseForwardLabel l_CompileBlock;

  // Push all the register we need to save
@@ -82,20 +80,43 @@ void Dispatcher::EmitDispatcher() {
  AbsoluteLoopTopAddressFillSRA = GetCursorAddress<uint64_t>();

  FillStaticRegs();
+  ARMEmitter::BiDirectionalLabel LoopTop {};
+
+#ifdef _M_ARM_64EC
+  b(&LoopTop);
+
+  AbsoluteLoopTopAddressEnterECFillSRA = GetCursorAddress<uint64_t>();
+  ldr(STATE, EC_ENTRY_CPUAREA_REG, CPU_AREA_EMULATOR_DATA_OFFSET);
+  FillStaticRegs();
+
+  // Enter JIT
+  b(&LoopTop);
+
+  AbsoluteLoopTopAddressEnterEC = GetCursorAddress<uint64_t>();
+  // Load ThreadState and write the target PC there
+  ldr(STATE, EC_ENTRY_CPUAREA_REG, CPU_AREA_EMULATOR_DATA_OFFSET);
+  str(EC_CALL_CHECKER_PC_REG, STATE_PTR(CpuStateFrame, State.rip));
+
+  // Swap stacks to the emulator stack
+  ldr(TMP1, EC_ENTRY_CPUAREA_REG, CPU_AREA_EMULATOR_STACK_BASE_OFFSET);
+  add(ARMEmitter::Size::i64Bit, StaticRegisters[X86State::REG_RSP], ARMEmitter::Reg::rsp, 0);
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, TMP1, 0);
+
+  FillSpecialRegs(TMP1, TMP2, false, true);
+
+  // Enter JIT
+#endif

  // We want to ensure that we are 16 byte aligned at the top of this loop
  Align16B();
  ARMEmitter::BiDirectionalLabel FullLookup {};
  ARMEmitter::BiDirectionalLabel CallBlock {};
-  ARMEmitter::BackwardLabel LoopTop {};

  Bind(&LoopTop);
  AbsoluteLoopTopAddress = GetCursorAddress<uint64_t>();

  // Load in our RIP
  // Don't modify TMP3 since it contains our RIP once the block doesn't exist
-  // IMPORTANT: Pointers.Common.ExitFunctionEC callsites/implementations need to be
-  // adjusted accordingly if this changes.
  auto RipReg = TMP3;
  ldr(RipReg, STATE_PTR(CpuStateFrame, State.rip));

@@ -137,10 +158,6 @@ void Dispatcher::EmitDispatcher() {

    // If page pointer is zero then we have no block
    cbz(ARMEmitter::Size::i64Bit, TMP1, &NoBlock);
-#ifdef _M_ARM_64EC
-    // The LSB of an L2 page entry indicates if this page contains EC code
-    tbnz(TMP1, 0, &ExitEC);
-#endif

    // Steal the page offset
    and_(ARMEmitter::Size::i64Bit, TMP2, TMP4, 0x0FFF);
@@ -167,22 +184,13 @@ void Dispatcher::EmitDispatcher() {

      and_(ARMEmitter::Size::i64Bit, TMP2, RipReg.R(), LookupCache::L1_ENTRIES_MASK);
      add(TMP1, TMP1, TMP2, ARMEmitter::ShiftType::LSL, 4);
-      stp<ARMEmitter::IndexType::OFFSET>(TMP4, TMP3, TMP1);
+      stp<ARMEmitter::IndexType::OFFSET>(TMP4, RipReg, TMP1);

      // Jump to the block
      br(TMP4);
    }
  }

-#ifdef _M_ARM_64EC
-  {
-    Bind(&ExitEC);
-    // Target PC is already loaded into TMP3 at the start of the dispatcher
-    ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC));
-    br(TMP2);
-  }
-#endif
-
  {
    ThreadStopHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
    SpillStaticRegs(TMP1);
@@ -200,9 +208,17 @@ void Dispatcher::EmitDispatcher() {
    ExitFunctionLinkerAddress = GetCursorAddress<uint64_t>();
    SpillStaticRegs(TMP1);

+#ifndef _WIN32
    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+#endif
+
+#ifdef _M_ARM_64EC
+    ldr(ARMEmitter::XReg::x0, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
+    LoadConstant(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, 1);
+    strb(ARMEmitter::WReg::w1, ARMEmitter::XReg::x0, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
+#endif

    mov(ARMEmitter::XReg::x0, STATE);
    mov(ARMEmitter::XReg::x1, ARMEmitter::XReg::lr);
@@ -220,13 +236,20 @@ void Dispatcher::EmitDispatcher() {

    FillStaticRegs();

+#ifdef _M_ARM_64EC
+    ldr(TMP2, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
+    strb(ARMEmitter::WReg::zr, TMP2, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
+#endif
+
+#ifndef _WIN32
    ldr(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
    sub(ARMEmitter::Size::i64Bit, TMP2, TMP2, 1);
    str(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));

    // Trigger segfault if any deferred signals are pending
-    ldr(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
-    str(ARMEmitter::XReg::zr, TMP2, 0);
+    strb(ARMEmitter::XReg::zr, STATE,
+         offsetof(FEXCore::Core::InternalThreadState, InterruptFaultPage) - offsetof(FEXCore::Core::InternalThreadState, BaseFrameState));
+#endif

    br(TMP1);
  }
@@ -235,15 +258,44 @@ void Dispatcher::EmitDispatcher() {
  {
    Bind(&NoBlock);

+#ifdef _M_ARM_64EC
+    // Check the EC code bitmap incase we need to exit the JIT to call into native code.
+    ARMEmitter::SingleUseForwardLabel l_NotECCode;
+    ldr(TMP1, ARMEmitter::XReg::x18, TEB_PEB_OFFSET);
+    ldr(TMP1, TMP1, PEB_EC_CODE_BITMAP_OFFSET);
+
+    lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 15);
+    and_(ARMEmitter::Size::i64Bit, TMP2, TMP2, 0x1fffffffffff8);
+    ldr(TMP1, TMP1, TMP2, ARMEmitter::ExtendedType::LSL_64, 0);
+    lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 12);
+    lsrv(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP2);
+    tbz(TMP1, 0, &l_NotECCode);
+
+    add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, StaticRegisters[X86State::REG_RSP], 0);
+    mov(EC_CALL_CHECKER_PC_REG, RipReg);
+    ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC));
+    br(TMP2);
+
+    Bind(&l_NotECCode);
+#endif
+
    SpillStaticRegs(TMP1);

    if (!TMP_ABIARGS) {
-      mov(ARMEmitter::XReg::x2, TMP3);
+      mov(ARMEmitter::XReg::x2, RipReg);
    }

+#ifndef _WIN32
    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+#endif
+
+#ifdef _M_ARM_64EC
+    ldr(ARMEmitter::XReg::x0, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
+    LoadConstant(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, 1);
+    strb(ARMEmitter::WReg::w1, ARMEmitter::XReg::x0, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
+#endif

    ldr(ARMEmitter::XReg::x0, &l_CTX);
    mov(ARMEmitter::XReg::x1, STATE);
@@ -259,13 +311,20 @@ void Dispatcher::EmitDispatcher() {

    FillStaticRegs();

+#ifdef _M_ARM_64EC
+    ldr(TMP1, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
+    strb(ARMEmitter::WReg::zr, TMP1, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
+#endif
+
+#ifndef _WIN32
    ldr(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
    sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 1);
    str(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));

    // Trigger segfault if any deferred signals are pending
-    ldr(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
-    str(ARMEmitter::XReg::zr, TMP1, 0);
+    strb(ARMEmitter::XReg::zr, STATE,
+         offsetof(FEXCore::Core::InternalThreadState, InterruptFaultPage) - offsetof(FEXCore::Core::InternalThreadState, BaseFrameState));
+#endif

    b(&LoopTop);
  }
@@ -494,6 +553,8 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread)

    Common.DispatcherLoopTop = AbsoluteLoopTopAddress;
    Common.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA;
+    Common.DispatcherLoopTopEnterEC = AbsoluteLoopTopAddressEnterEC;
+    Common.DispatcherLoopTopEnterECFillSRA = AbsoluteLoopTopAddressEnterECFillSRA;
    Common.ExitFunctionLinker = ExitFunctionLinkerAddress;
    Common.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA;
    Common.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA;
@@ -47,6 +47,8 @@ public:
  uint64_t ThreadStopHandlerAddressSpillSRA {};
  uint64_t AbsoluteLoopTopAddress {};
  uint64_t AbsoluteLoopTopAddressFillSRA {};
+  uint64_t AbsoluteLoopTopAddressEnterEC {};
+  uint64_t AbsoluteLoopTopAddressEnterECFillSRA {};
  uint64_t ThreadPauseHandlerAddress {};
  uint64_t ThreadPauseHandlerAddressSpillSRA {};
  uint64_t ExitFunctionLinkerAddress {};
@@ -221,14 +221,16 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand* Operand, X86Tables::ModR
    {
      // If we have a VSIB byte (as opposed to SIB), then the index register is a vector.
      const bool IsIndexVector = (DecodeInst->TableInfo->Flags & InstFlags::FLAGS_VEX_VSIB) != 0;
+      uint8_t InvalidSIBIndex = 0b100; ///< SIB Index where there is no register encoding.
      if (IsIndexVector) {
        DecodeInst->Flags |= X86Tables::DecodeFlags::FLAG_VSIB_BYTE;
+        InvalidSIBIndex = ~0; ///< No Invalid SIB Index with Index Vectors.
      }

      const uint8_t IndexREX = (DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X) != 0 ? 1 : 0;
      const uint8_t BaseREX = (DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B) != 0 ? 1 : 0;

-      Operand->Data.SIB.Index = MapModRMToReg(IndexREX, SIB.index, false, false, IsIndexVector, false, 0b100);
+      Operand->Data.SIB.Index = MapModRMToReg(IndexREX, SIB.index, false, false, IsIndexVector, false, InvalidSIBIndex);
      Operand->Data.SIB.Base = MapModRMToReg(BaseREX, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
    }

@@ -630,7 +632,6 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
    uint16_t X87Op = ((Op - 0xD8) << 8) | ModRMByte;
    return NormalOp(&X87Ops[X87Op], X87Op);
  } else if (Info->Type == FEXCore::X86Tables::TYPE_VEX_TABLE_PREFIX) {
-    FEXCORE_TELEMETRY_SET(VEXOpTelem, 1);
    uint16_t map_select = 1;
    uint16_t pp = 0;
    const uint8_t Byte1 = ReadByte();
@@ -659,6 +660,9 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
      if (CTX->Config.Is64BitMode && (Byte1 & 0b00100000) == 0) {
        DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_B;
      }
+      if (options.w) {
+        DecodeInst->Flags |= DecodeFlags::FLAG_OPTION_AVX_W;
+      }
      if (!(map_select >= 1 && map_select <= 3)) {
        LogMan::Msg::EFmt("We don't understand a map_select of: {}", map_select);
        return false;
@@ -673,7 +677,6 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
    FEXCore::X86Tables::X86InstInfo* LocalInfo = &VEXTableOps[Op];

    if (LocalInfo->Type >= FEXCore::X86Tables::TYPE_VEX_GROUP_12 && LocalInfo->Type <= FEXCore::X86Tables::TYPE_VEX_GROUP_17) {
-      FEXCORE_TELEMETRY_SET(VEXOpTelem, 1);
      // We have ModRM
      uint8_t ModRMByte = ReadByte();
      DecodeInst->ModRM = ModRMByte;
@@ -941,14 +944,12 @@ void Decoder::BranchTargetInMultiblockRange() {
    // auto RIPOffset = LoadSource(Op, Op->Src[0], Op->Flags);
    // auto RIPTargetConst = _Constant(Op->PC + Op->InstSize);
    // Target offset is PC + InstSize + Literal
-    LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
-    TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
+    TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Literal();
    break;
  }
  case 0xE9:
  case 0xEB: // Both are unconditional JMP instructions
-    LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
-    TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
+    TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Literal();
    Conditional = false;
    break;
  case 0xE8: // Call - Immediate target, We don't want to inline calls
@@ -1000,8 +1001,7 @@ bool Decoder::BranchTargetCanContinue(bool FinalInstruction) const {

  if (DecodeInst->OP == 0xE8) { // Call - immediate target
    const uint64_t NextRIP = DecodeInst->PC + DecodeInst->InstSize;
-    LOGMAN_THROW_A_FMT(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
-    TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
+    TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Literal();

    if (GPRSize == 4) {
      // If we are running a 32bit guest then wrap around addresses that go above 32bit
@@ -120,7 +120,6 @@ private:

  const uint8_t* AdjustAddrForSpecialRegion(const uint8_t* _InstStream, uint64_t EntryPoint, uint64_t RIP);

-  FEXCORE_TELEMETRY_INIT(VEXOpTelem, TYPE_USES_VEX_OPS);
  FEXCORE_TELEMETRY_INIT(EVEXOpTelem, TYPE_USES_EVEX_OPS);
 };
 } // namespace FEXCore::Frontend
@@ -1,252 +0,0 @@
-// SPDX-License-Identifier: MIT
-#include "Interface/Core/CPUID.h"
-#include <FEXCore/Core/HostFeatures.h>
-
-#include "aarch64/assembler-aarch64.h"
-#include "aarch64/cpu-aarch64.h"
-#include "aarch64/disasm-aarch64.h"
-#include "aarch64/assembler-aarch64.h"
-
-#ifdef _M_X86_64
-#define XBYAK64
-#define XBYAK_NO_EXCEPTION
-#include <FEXCore/fextl/list.h>
-#include <FEXCore/fextl/unordered_map.h>
-#include <FEXCore/fextl/unordered_set.h>
-
-#include <xbyak/xbyak.h>
-#include <xbyak/xbyak_util.h>
-#endif
-
-namespace FEXCore {
-
-// Data Zero Prohibited flag
-// 0b0 = ZVA/GVA/GZVA permitted
-// 0b1 = ZVA/GVA/GZVA prohibited
-[[maybe_unused]] constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
-// Log2 of the blocksize in 32-bit words
-[[maybe_unused]] constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
-
-#ifdef _M_ARM_64
-[[maybe_unused]]
-static uint32_t GetDCZID() {
-  uint64_t Result {};
-  __asm("mrs %[Res], DCZID_EL0" : [Res] "=r"(Result));
-  return Result;
-}
-
-static uint32_t GetFPCR() {
-  uint64_t Result {};
-  __asm("mrs %[Res], FPCR" : [Res] "=r"(Result));
-  return Result;
-}
-
-static void SetFPCR(uint64_t Value) {
-  __asm("msr FPCR, %[Value]" ::[Value] "r"(Value));
-}
-#else
-static uint32_t GetDCZID() {
-  // Return unsupported
-  return DCZID_DZP_MASK;
-}
-#endif
-
-static void OverrideFeatures(HostFeatures* Features) {
-  // Override features if the user has specifically called for it.
-  FEX_CONFIG_OPT(HostFeatures, HOSTFEATURES);
-  if (!HostFeatures()) {
-    // Early exit if no features are overriden.
-    return;
-  }
-
-#define ENABLE_DISABLE_OPTION(FeatureName, name, enum_name) \
-  do { \
-    const bool Disable##name = (HostFeatures() & FEXCore::Config::HostFeatures::DISABLE##enum_name) != 0; \
-    const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0; \
-    LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive"); \
-    const bool AlreadyEnabled = Features->FeatureName; \
-    const bool Result = (AlreadyEnabled | Enable##name) & !Disable##name; \
-    Features->FeatureName = Result; \
-  } while (0)
-
-#define GET_SINGLE_OPTION(name, enum_name) \
-  const bool Disable##name = (HostFeatures() & FEXCore::Config::HostFeatures::DISABLE##enum_name) != 0; \
-  const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0; \
-  LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive");
-
-  ENABLE_DISABLE_OPTION(SupportsAVX, AVX, AVX);
-  ENABLE_DISABLE_OPTION(SupportsAVX2, AVX2, AVX2);
-  ENABLE_DISABLE_OPTION(SupportsSVE, SVE, SVE);
-  ENABLE_DISABLE_OPTION(SupportsAFP, AFP, AFP);
-  ENABLE_DISABLE_OPTION(SupportsRCPC, LRCPC, LRCPC);
-  ENABLE_DISABLE_OPTION(SupportsTSOImm9, LRCPC2, LRCPC2);
-  ENABLE_DISABLE_OPTION(SupportsCSSC, CSSC, CSSC);
-  ENABLE_DISABLE_OPTION(SupportsPMULL_128Bit, PMULL128, PMULL128);
-  ENABLE_DISABLE_OPTION(SupportsRAND, RNG, RNG);
-  ENABLE_DISABLE_OPTION(SupportsCLZERO, CLZERO, CLZERO);
-  ENABLE_DISABLE_OPTION(SupportsAtomics, Atomics, ATOMICS);
-  ENABLE_DISABLE_OPTION(SupportsFCMA, FCMA, FCMA);
-  ENABLE_DISABLE_OPTION(SupportsFlagM, FlagM, FLAGM);
-  ENABLE_DISABLE_OPTION(SupportsFlagM2, FlagM2, FLAGM2);
-  ENABLE_DISABLE_OPTION(SupportsRPRES, RPRES, RPRES);
-  ENABLE_DISABLE_OPTION(SupportsPreserveAllABI, PRESERVEALLABI, PRESERVEALLABI);
-  GET_SINGLE_OPTION(Crypto, CRYPTO);
-
-#undef ENABLE_DISABLE_OPTION
-#undef GET_SINGLE_OPTION
-
-  if (EnableCrypto) {
-    Features->SupportsAES = true;
-    Features->SupportsCRC = true;
-    Features->SupportsSHA = true;
-    Features->SupportsPMULL_128Bit = true;
-  } else if (DisableCrypto) {
-    Features->SupportsAES = false;
-    Features->SupportsCRC = false;
-    Features->SupportsSHA = false;
-    Features->SupportsPMULL_128Bit = false;
-  }
-}
-
-HostFeatures::HostFeatures() {
-#ifdef VIXL_SIMULATOR
-  auto Features = vixl::CPUFeatures::All();
-  // Vixl simulator doesn't support AFP.
-  Features.Remove(vixl::CPUFeatures::Feature::kAFP);
-  // Vixl simulator doesn't support RPRES.
-  Features.Remove(vixl::CPUFeatures::Feature::kRPRES);
-#elif !defined(_WIN32)
-  auto Features = vixl::CPUFeatures::InferFromOS();
-#else
-  // Need to use ID registers in WINE.
-  auto Features = vixl::CPUFeatures::InferFromIDRegisters();
-#endif
-
-  SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
-  SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
-  SupportsSHA = Features.Has(vixl::CPUFeatures::Feature::kSHA1) && Features.Has(vixl::CPUFeatures::Feature::kSHA2);
-  SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
-  SupportsRAND = Features.Has(vixl::CPUFeatures::Feature::kRNG);
-
-  // Only supported when FEAT_AFP is supported
-  SupportsAFP = Features.Has(vixl::CPUFeatures::Feature::kAFP);
-  SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
-  SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
-  SupportsPMULL_128Bit = Features.Has(vixl::CPUFeatures::Feature::kPmull1Q);
-  SupportsCSSC = Features.Has(vixl::CPUFeatures::Feature::kCSSC);
-  SupportsFCMA = Features.Has(vixl::CPUFeatures::Feature::kFcma);
-  SupportsFlagM = Features.Has(vixl::CPUFeatures::Feature::kFlagM);
-  SupportsFlagM2 = Features.Has(vixl::CPUFeatures::Feature::kAXFlag);
-  SupportsRPRES = Features.Has(vixl::CPUFeatures::Feature::kRPRES);
-
-  Supports3DNow = true;
-  SupportsSSE4A = true;
-#ifdef VIXL_SIMULATOR
-  // Hardcode enable SVE with 256-bit wide registers.
-  SupportsSVE = true;
-  SupportsAVX = true;
-#else
-  SupportsSVE = Features.Has(vixl::CPUFeatures::Feature::kSVE);
-  SupportsAVX = Features.Has(vixl::CPUFeatures::Feature::kSVE2) && vixl::aarch64::CPU::ReadSVEVectorLengthInBits() >= 256;
-#endif
-  // TODO: AVX2 is currently unsupported. Disable until the remaining features are implemented.
-  SupportsAVX2 = false;
-  SupportsBMI1 = true;
-  SupportsBMI2 = true;
-  SupportsCLWB = true;
-
-  // TODO: AFP is disabled until the scalar usage in the codebase can be audited to be working as expected.
-  SupportsAFP = false;
-  // RPRES has a dependency on AFP. Disable it until AFP is enabled.
-  SupportsRPRES = false;
-
-  if (!SupportsAtomics) {
-    WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
-  }
-
-#ifdef _M_ARM_64
-  // We need to get the CPU's cache line size
-  // We expect sane targets that have correct cacheline sizes across clusters
-  uint64_t CTR;
-  __asm volatile("mrs %[ctr], ctr_el0" : [ctr] "=r"(CTR));
-
-  DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
-  ICacheLineSize = 4 << (CTR & 0xF);
-
-  // Test if this CPU supports float exception trapping by attempting to enable
-  // On unsupported these bits are architecturally defined as RAZ/WI
-  constexpr uint32_t ExceptionEnableTraps = (1U << 8) |  // Invalid Operation float exception trap enable
-                                            (1U << 9) |  // Divide by zero float exception trap enable
-                                            (1U << 10) | // Overflow float exception trap enable
-                                            (1U << 11) | // Underflow float exception trap enable
-                                            (1U << 12) | // Inexact float exception trap enable
-                                            (1U << 15);  // Input Denormal float exception trap enable
-
-  uint32_t OriginalFPCR = GetFPCR();
-  uint32_t FPCR = OriginalFPCR | ExceptionEnableTraps;
-  SetFPCR(FPCR);
-  FPCR = GetFPCR();
-  SupportsFloatExceptions = (FPCR & ExceptionEnableTraps) == ExceptionEnableTraps;
-
-  // Set FPCR back to original just in case anything changed
-  SetFPCR(OriginalFPCR);
-#endif
-
-#ifdef VIXL_SIMULATOR
-  // simulator doesn't support dc(ZVA)
-  SupportsCLZERO = false;
-  // Simulator doesn't support SHA
-  SupportsSHA = false;
-#else
-  // Check if we can support cacheline clears
-  uint32_t DCZID = GetDCZID();
-  if ((DCZID & DCZID_DZP_MASK) == 0) {
-    uint32_t DCZID_Log2 = DCZID & DCZID_BS_MASK;
-    uint32_t DCZID_Bytes = (1 << DCZID_Log2) * sizeof(uint32_t);
-    // If the DC ZVA size matches the emulated cache line size
-    // This means we can use the instruction
-    SupportsCLZERO = DCZID_Bytes == CPUIDEmu::CACHELINE_SIZE;
-  }
-#endif
-
-#if defined(_M_X86_64)
-  // Hardcoded cacheline size.
-  DCacheLineSize = 64U;
-  ICacheLineSize = 64U;
-
-#if !defined(VIXL_SIMULATOR)
-  Xbyak::util::Cpu X86Features {};
-  SupportsAES = X86Features.has(Xbyak::util::Cpu::tAESNI);
-  SupportsCRC = X86Features.has(Xbyak::util::Cpu::tSSE42);
-  SupportsRAND = X86Features.has(Xbyak::util::Cpu::tRDRAND) && X86Features.has(Xbyak::util::Cpu::tRDSEED);
-  SupportsRCPC = true;
-  SupportsTSOImm9 = true;
-  Supports3DNow = X86Features.has(Xbyak::util::Cpu::t3DN) && X86Features.has(Xbyak::util::Cpu::tE3DN);
-  SupportsSSE4A = X86Features.has(Xbyak::util::Cpu::tSSE4a);
-  SupportsAVX = true;
-  SupportsAVX2 = true;
-  SupportsSHA = X86Features.has(Xbyak::util::Cpu::tSHA);
-  SupportsBMI1 = X86Features.has(Xbyak::util::Cpu::tBMI1);
-  SupportsBMI2 = X86Features.has(Xbyak::util::Cpu::tBMI2);
-  SupportsCLWB = X86Features.has(Xbyak::util::Cpu::tCLWB);
-  SupportsPMULL_128Bit = X86Features.has(Xbyak::util::Cpu::tPCLMULQDQ);
-
-  // xbyak doesn't know how to check for CLZero
-  // First ensure we support a new enough extended CPUID function range
-
-  uint32_t data[4];
-  Xbyak::util::Cpu::getCpuid(0x8000'0000, data);
-  if (data[0] >= 0x8000'0008U) {
-    // CLZero defined in 8000_00008_EBX[bit 0]
-    Xbyak::util::Cpu::getCpuid(0x8000'0008, data);
-    SupportsCLZERO = data[1] & 1;
-  }
-
-  SupportsAFP = true;
-  SupportsFloatExceptions = true;
-#endif
-#endif
-  SupportsPreserveAllABI = FEXCORE_HAS_PRESERVE_ALL_ATTR;
-  OverrideFeatures(this);
-}
-} // namespace FEXCore
@@ -6,54 +6,59 @@
 #include "Interface/IR/IR.h"

 namespace FEXCore::CPU {
-FEXCORE_PRESERVE_ALL_ATTR static void LoadDeferredFCW(uint16_t NewFCW) {
-  auto PC = (NewFCW >> 8) & 3;
+FEXCORE_PRESERVE_ALL_ATTR static softfloat_state SoftFloatStateFromFCW(uint16_t FCW) {
+  softfloat_state State;
+  State.detectTininess = softfloat_tininess_afterRounding;
+  State.exceptionFlags = 0;
+
+  auto PC = (FCW >> 8) & 3;
  switch (PC) {
-  case 0: extF80_roundingPrecision = 32; break;
-  case 2: extF80_roundingPrecision = 64; break;
-  case 3: extF80_roundingPrecision = 80; break;
+  case 0: State.roundingPrecision = 32; break;
+  case 2: State.roundingPrecision = 64; break;
+  case 3: State.roundingPrecision = 80; break;
  case 1: LOGMAN_MSG_A_FMT("Invalid x87 precision mode, {}", PC);
  }

-  auto RC = (NewFCW >> 10) & 3;
+  auto RC = (FCW >> 10) & 3;
  switch (RC) {
-  case 0: softfloat_roundingMode = softfloat_round_near_even; break;
-  case 1: softfloat_roundingMode = softfloat_round_min; break;
-  case 2: softfloat_roundingMode = softfloat_round_max; break;
-  case 3: softfloat_roundingMode = softfloat_round_minMag; break;
+  case 0: State.roundingMode = softfloat_round_near_even; break;
+  case 1: State.roundingMode = softfloat_round_min; break;
+  case 2: State.roundingMode = softfloat_round_max; break;
+  case 3: State.roundingMode = softfloat_round_minMag; break;
  }
+
+  return State;
 }

 template<>
 struct OpHandlers<IR::OP_F80CVTTO> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle4(uint16_t NewFCW, float src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle4(uint16_t FCW, float src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat(&State, src);
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle8(uint16_t NewFCW, double src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle8(uint16_t FCW, double src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat(&State, src);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80CMP> {
-  template<uint32_t Flags>
-  FEXCORE_PRESERVE_ALL_ATTR static uint64_t handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static uint64_t handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);

    bool eq, lt, nan;
    uint64_t ResultFlags = 0;

-    X80SoftFloat::FCMP(Src1, Src2, &eq, &lt, &nan);
-    if (Flags & (1 << IR::FCMP_FLAG_LT) && lt) {
+    X80SoftFloat::FCMP(&State, Src1, Src2, &eq, &lt, &nan);
+    if (lt) {
      ResultFlags |= (1 << IR::FCMP_FLAG_LT);
    }
-    if (Flags & (1 << IR::FCMP_FLAG_UNORDERED) && nan) {
+    if (nan) {
      ResultFlags |= (1 << IR::FCMP_FLAG_UNORDERED);
    }
-    if (Flags & (1 << IR::FCMP_FLAG_EQ) && eq) {
+    if (eq) {
      ResultFlags |= (1 << IR::FCMP_FLAG_EQ);
    }
    return ResultFlags;
@@ -62,275 +67,261 @@ struct OpHandlers<IR::OP_F80CMP> {

 template<>
 struct OpHandlers<IR::OP_F80CVT> {
-  FEXCORE_PRESERVE_ALL_ATTR static float handle4(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static float handle4(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return src.ToF32(&State);
  }

-  FEXCORE_PRESERVE_ALL_ATTR static double handle8(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static double handle8(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return src.ToF64(&State);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80CVTINT> {
-  FEXCORE_PRESERVE_ALL_ATTR static int16_t handle2(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static int16_t handle2(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return src.ToI16(&State);
  }

-  FEXCORE_PRESERVE_ALL_ATTR static int32_t handle4(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static int32_t handle4(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return src.ToI32(&State);
  }

-  FEXCORE_PRESERVE_ALL_ATTR static int64_t handle8(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return src;
+  FEXCORE_PRESERVE_ALL_ATTR static int64_t handle8(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return src.ToI64(&State);
  }

-  FEXCORE_PRESERVE_ALL_ATTR static int16_t handle2t(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    auto rv = extF80_to_i32(src, softfloat_round_minMag, false);
+  FEXCORE_PRESERVE_ALL_ATTR static int16_t handle2t(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    auto rv = extF80_to_i32(&State, src, softfloat_round_minMag, false);

-    if (rv > INT16_MAX) {
-      return INT16_MAX;
-    } else if (rv < INT16_MIN) {
+    if (rv > INT16_MAX || rv < INT16_MIN) {
+      ///< Indefinite value for 16-bit conversions.
      return INT16_MIN;
    } else {
      return rv;
    }
  }

-  FEXCORE_PRESERVE_ALL_ATTR static int32_t handle4t(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return extF80_to_i32(src, softfloat_round_minMag, false);
+  FEXCORE_PRESERVE_ALL_ATTR static int32_t handle4t(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return extF80_to_i32(&State, src, softfloat_round_minMag, false);
  }

-  FEXCORE_PRESERVE_ALL_ATTR static int64_t handle8t(uint16_t NewFCW, X80SoftFloat src) {
-    LoadDeferredFCW(NewFCW);
-    return extF80_to_i64(src, softfloat_round_minMag, false);
+  FEXCORE_PRESERVE_ALL_ATTR static int64_t handle8t(uint16_t FCW, X80SoftFloat src) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return extF80_to_i64(&State, src, softfloat_round_minMag, false);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80CVTTOINT> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle2(uint16_t NewFCW, int16_t src) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle2(uint16_t FCW, int16_t src) {
    return src;
  }

-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle4(uint16_t NewFCW, int32_t src) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle4(uint16_t FCW, int32_t src) {
    return src;
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80ROUND> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FRNDINT(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FRNDINT(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80F2XM1> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::F2XM1(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::F2XM1(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80TAN> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FTAN(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FTAN(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80SQRT> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FSQRT(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FSQRT(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80SIN> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FSIN(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FSIN(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80COS> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FCOS(Src1);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FCOS(&State, Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80XTRACT_EXP> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
    return X80SoftFloat::FXTRACT_EXP(Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80XTRACT_SIG> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
    return X80SoftFloat::FXTRACT_SIG(Src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80ADD> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FADD(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FADD(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80SUB> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FSUB(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FSUB(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80MUL> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FMUL(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FMUL(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80DIV> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FDIV(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FDIV(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80FYL2X> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FYL2X(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FYL2X(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80ATAN> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FATAN(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FATAN(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80FPREM1> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FREM1(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FREM1(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80FPREM> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FREM(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FREM(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F80SCALE> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1, X80SoftFloat Src2) {
-    LoadDeferredFCW(NewFCW);
-    return X80SoftFloat::FSCALE(Src1, Src2);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1, X80SoftFloat Src2) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
+    return X80SoftFloat::FSCALE(&State, Src1, Src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64SIN> {
-  static double handle(uint16_t NewFCW, double src) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src) {
    return sin(src);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64COS> {
-  static double handle(uint16_t NewFCW, double src) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src) {
    return cos(src);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64TAN> {
-  static double handle(uint16_t NewFCW, double src) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src) {
    return tan(src);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64F2XM1> {
-  static double handle(uint16_t NewFCW, double src) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src) {
    return exp2(src) - 1.0;
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64ATAN> {
-  static double handle(uint16_t NewFCW, double src1, double src2) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src1, double src2) {
    return atan2(src1, src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64FPREM> {
-  static double handle(uint16_t NewFCW, double src1, double src2) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src1, double src2) {
    return fmod(src1, src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64FPREM1> {
-  static double handle(uint16_t NewFCW, double src1, double src2) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src1, double src2) {
    return remainder(src1, src2);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64FYL2X> {
-  static double handle(uint16_t NewFCW, double src1, double src2) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src1, double src2) {
    return src2 * log2(src1);
  }
 };

 template<>
 struct OpHandlers<IR::OP_F64SCALE> {
-  static double handle(uint16_t NewFCW, double src1, double src2) {
-    LoadDeferredFCW(NewFCW);
+  static double handle(uint16_t FCW, double src1, double src2) {
    double trunc = (double)(int64_t)(src2); // truncate
    return src1 * exp2(trunc);
  }
@@ -338,16 +329,16 @@ struct OpHandlers<IR::OP_F64SCALE> {

 template<>
 struct OpHandlers<IR::OP_F80BCDSTORE> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src1) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src1) {
+    softfloat_state State = SoftFloatStateFromFCW(FCW);
    bool Negative = Src1.Sign;

-    Src1 = X80SoftFloat::FRNDINT(Src1);
+    Src1 = X80SoftFloat::FRNDINT(&State, Src1);

    // Clear the Sign bit
    Src1.Sign = 0;

-    uint64_t Tmp = Src1;
+    uint64_t Tmp = Src1.ToI64(&State);
    X80SoftFloat Rv;
    uint8_t* BCD = reinterpret_cast<uint8_t*>(&Rv);
    memset(BCD, 0, 10);
@@ -379,8 +370,7 @@ struct OpHandlers<IR::OP_F80BCDSTORE> {

 template<>
 struct OpHandlers<IR::OP_F80BCDLOAD> {
-  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t NewFCW, X80SoftFloat Src) {
-    LoadDeferredFCW(NewFCW);
+  FEXCORE_PRESERVE_ALL_ATTR static X80SoftFloat handle(uint16_t FCW, X80SoftFloat Src) {
    uint8_t* Src1 = reinterpret_cast<uint8_t*>(&Src);
    uint64_t BCD {};
    // We walk through each uint8_t and pull out the BCD encoding
@@ -35,14 +35,7 @@ void InterpreterOps::FillFallbackIndexPointers(uint64_t* Info) {
  Info[Core::OPINDEX_F80CVTINT_TRUNC2] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t);
  Info[Core::OPINDEX_F80CVTINT_TRUNC4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t);
  Info[Core::OPINDEX_F80CVTINT_TRUNC8] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t);
-  Info[Core::OPINDEX_F80CMP_0] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>);
-  Info[Core::OPINDEX_F80CMP_1] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<1>);
-  Info[Core::OPINDEX_F80CMP_2] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<2>);
-  Info[Core::OPINDEX_F80CMP_3] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<3>);
-  Info[Core::OPINDEX_F80CMP_4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<4>);
-  Info[Core::OPINDEX_F80CMP_5] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<5>);
-  Info[Core::OPINDEX_F80CMP_6] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<6>);
-  Info[Core::OPINDEX_F80CMP_7] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>);
+  Info[Core::OPINDEX_F80CMP] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle);
  Info[Core::OPINDEX_F80CVTTOINT_2] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2);
  Info[Core::OPINDEX_F80CVTTOINT_4] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4);

@@ -154,17 +147,8 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I
    break;
  }
  case IR::OP_F80CMP: {
-    auto Op = IROp->C<IR::IROp_F80Cmp>();
-
-    static constexpr std::array handlers {
-      &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<0>, &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<1>,
-      &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<2>, &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<3>,
-      &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<4>, &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<5>,
-      &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<6>, &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>,
-    };
-
-    *Info = {FABI_I64_I16_F80_F80, (void*)handlers[Op->Flags], (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP_0 + Op->Flags),
-             SupportsPreserveAllABI};
+    *Info = {FABI_I64_I16_F80_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle,
+             (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP), SupportsPreserveAllABI};
    return true;
  }

@@ -185,22 +169,22 @@ bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, const IR::I
    break;
  }

-#define COMMON_UNARY_X87_OP(OP) \
-  case IR::OP_F80##OP: { \
+#define COMMON_UNARY_X87_OP(OP)                                                                                                          \
+  case IR::OP_F80##OP: {                                                                                                                 \
    *Info = {FABI_F80_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP, SupportsPreserveAllABI}; \
-    return true; \
+    return true;                                                                                                                         \
  }

-#define COMMON_BINARY_X87_OP(OP) \
-  case IR::OP_F80##OP: { \
+#define COMMON_BINARY_X87_OP(OP)                                                                                                             \
+  case IR::OP_F80##OP: {                                                                                                                     \
    *Info = {FABI_F80_I16_F80_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP, SupportsPreserveAllABI}; \
-    return true; \
+    return true;                                                                                                                             \
  }

-#define COMMON_F64_OP(OP) \
-  case IR::OP_F64##OP: { \
+#define COMMON_F64_OP(OP)                                                                              \
+  case IR::OP_F64##OP: {                                                                               \
    *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64##OP>::handle, Core::OPINDEX_F64##OP); \
-    return true; \
+    return true;                                                                                       \
  }

    // Unary
@@ -50,22 +50,22 @@ struct OpHandlers<IR::OP_VPCMPESTRX> {

    // Bits are arranged as:
    // Bit #:   3    2    1    0
-    //         [OF | CF | SF | ZF]
+    //         [SF | ZF | CF | OF]
    uint32_t flags = 0;
-    flags |= (valid_rhs < upper_limit) ? 0b01 : 0b00;
-    flags |= (valid_lhs < upper_limit) ? 0b10 : 0b00;
+    flags |= (valid_rhs < upper_limit) ? 0b0100 : 0b0000;
+    flags |= (valid_lhs < upper_limit) ? 0b1000 : 0b0000;

    const uint32_t result = HandlePolarity(aggregation, control, upper_limit, valid_rhs);
    if (result != 0) {
-      flags |= 0b0100;
+      flags |= 0b0010;
    }
    if ((result & 1) != 0) {
-      flags |= 0b1000;
+      flags |= 0b0001;
    }

-    // We tack the flags on top of the result to avoid needing to handle
-    // multiple return values in the JITs.
-    return result | (flags << 16);
+    // We track the flags in the usual NZCV bit position so we can msr them
+    // later. Avoids handling flags natively in JIT.
+    return result | (flags << 28);
  }

  FEXCORE_PRESERVE_ALL_ATTR static int32_t GetExplicitLength(uint64_t reg, uint16_t control) {
@@ -6,7 +6,6 @@ $end_info$
 */

 #include "Interface/Context/Context.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"

@@ -69,8 +68,8 @@ DEF_OP(CASPair) {

 DEF_OP(CAS) {
  auto Op = IROp->C<IR::IROp_CAS>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);
  // DataSrc = *Src1
  // if (DataSrc == Src3) { *Src1 == Src2; } Src2 = DataSrc
  // This will write to memory! Careful!
@@ -79,13 +78,6 @@ DEF_OP(CAS) {
  auto Desired = GetReg(Op->Desired.ID());
  auto MemSrc = GetReg(Op->Addr.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    mov(EmitSize, TMP2, Expected);
    casal(SubEmitSize, TMP2, Desired, MemSrc);
@@ -96,9 +88,9 @@ DEF_OP(CAS) {
    ARMEmitter::SingleUseForwardLabel LoopExpected;
    Bind(&LoopTop);
    ldaxr(SubEmitSize, TMP2, MemSrc);
-    if (OpSize == 1) {
+    if (IROp->Size == 1) {
      cmp(EmitSize, TMP2, Expected, ARMEmitter::ExtendedType::UXTB, 0);
-    } else if (OpSize == 2) {
+    } else if (IROp->Size == 2) {
      cmp(EmitSize, TMP2, Expected, ARMEmitter::ExtendedType::UXTH, 0);
    } else {
      cmp(EmitSize, TMP2, Expected);
@@ -120,19 +112,12 @@ DEF_OP(CAS) {

 DEF_OP(AtomicAdd) {
  auto Op = IROp->C<IR::IROp_AtomicAdd>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    staddl(SubEmitSize, Src, MemSrc);
  } else {
@@ -147,19 +132,12 @@ DEF_OP(AtomicAdd) {

 DEF_OP(AtomicSub) {
  auto Op = IROp->C<IR::IROp_AtomicSub>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    neg(EmitSize, TMP2, Src);
    staddl(SubEmitSize, TMP2, MemSrc);
@@ -175,19 +153,12 @@ DEF_OP(AtomicSub) {

 DEF_OP(AtomicAnd) {
  auto Op = IROp->C<IR::IROp_AtomicAnd>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    mvn(EmitSize, TMP2, Src);
    stclrl(SubEmitSize, TMP2, MemSrc);
@@ -203,19 +174,12 @@ DEF_OP(AtomicAnd) {

 DEF_OP(AtomicCLR) {
  auto Op = IROp->C<IR::IROp_AtomicCLR>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    stclrl(SubEmitSize, Src, MemSrc);
  } else {
@@ -230,19 +194,12 @@ DEF_OP(AtomicCLR) {

 DEF_OP(AtomicOr) {
  auto Op = IROp->C<IR::IROp_AtomicOr>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    stsetl(SubEmitSize, Src, MemSrc);
  } else {
@@ -257,19 +214,12 @@ DEF_OP(AtomicOr) {

 DEF_OP(AtomicXor) {
  auto Op = IROp->C<IR::IROp_AtomicXor>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    steorl(SubEmitSize, Src, MemSrc);
  } else {
@@ -284,18 +234,11 @@ DEF_OP(AtomicXor) {

 DEF_OP(AtomicNeg) {
  auto Op = IROp->C<IR::IROp_AtomicNeg>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  ARMEmitter::BackwardLabel LoopTop;
  Bind(&LoopTop);
  ldaxr(SubEmitSize, TMP2, MemSrc);
@@ -312,7 +255,7 @@ DEF_OP(AtomicSwap) {
  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+  const auto EmitSize = ConvertSize(IROp);
  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
@@ -333,19 +276,12 @@ DEF_OP(AtomicSwap) {

 DEF_OP(AtomicFetchAdd) {
  auto Op = IROp->C<IR::IROp_AtomicFetchAdd>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    ldaddal(SubEmitSize, Src, GetReg(Node), MemSrc);
  } else {
@@ -361,19 +297,12 @@ DEF_OP(AtomicFetchAdd) {

 DEF_OP(AtomicFetchSub) {
  auto Op = IROp->C<IR::IROp_AtomicFetchSub>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    neg(EmitSize, TMP2, Src);
    ldaddal(SubEmitSize, TMP2, GetReg(Node), MemSrc);
@@ -390,19 +319,12 @@ DEF_OP(AtomicFetchSub) {

 DEF_OP(AtomicFetchAnd) {
  auto Op = IROp->C<IR::IROp_AtomicFetchAnd>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    mvn(EmitSize, TMP2, Src);
    ldclral(SubEmitSize, TMP2, GetReg(Node), MemSrc);
@@ -419,19 +341,12 @@ DEF_OP(AtomicFetchAnd) {

 DEF_OP(AtomicFetchCLR) {
  auto Op = IROp->C<IR::IROp_AtomicFetchCLR>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    ldclral(SubEmitSize, Src, GetReg(Node), MemSrc);
  } else {
@@ -447,19 +362,12 @@ DEF_OP(AtomicFetchCLR) {

 DEF_OP(AtomicFetchOr) {
  auto Op = IROp->C<IR::IROp_AtomicFetchOr>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    ldsetal(SubEmitSize, Src, GetReg(Node), MemSrc);
  } else {
@@ -475,19 +383,12 @@ DEF_OP(AtomicFetchOr) {

 DEF_OP(AtomicFetchXor) {
  auto Op = IROp->C<IR::IROp_AtomicFetchXor>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());
  auto Src = GetReg(Op->Value.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  if (CTX->HostFeatures.SupportsAtomics) {
    ldeoral(SubEmitSize, Src, GetReg(Node), MemSrc);
  } else {
@@ -503,18 +404,11 @@ DEF_OP(AtomicFetchXor) {

 DEF_OP(AtomicFetchNeg) {
  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
-  uint8_t OpSize = IROp->Size;
-  LOGMAN_THROW_AA_FMT(OpSize == 8 || OpSize == 4 || OpSize == 2 || OpSize == 1, "Unexpected CAS size");
+  const auto EmitSize = ConvertSize(IROp);
+  const auto SubEmitSize = ConvertSubRegSize8(IROp->Size);

  auto MemSrc = GetReg(Op->Addr.ID());

-  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
-  const auto SubEmitSize = OpSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           OpSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           OpSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                         ARMEmitter::SubRegSize::i8Bit;
-
  ARMEmitter::BackwardLabel LoopTop;
  Bind(&LoopTop);
  ldaxr(SubEmitSize, TMP2, MemSrc);
@@ -7,7 +7,6 @@ $end_info$

 #include "Interface/Context/Context.h"
 #include "FEXCore/IR/IR.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/LookupCache.h"

 #include "Interface/Core/JIT/Arm64/JITClass.h"
@@ -55,7 +54,8 @@ DEF_OP(ExitFunction) {
  if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
 #ifdef _M_ARM_64EC
    if (RtlIsEcCode(NewRIP)) {
-      LoadConstant(ARMEmitter::Size::i64Bit, TMP3, NewRIP);
+      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, StaticRegisters[X86State::REG_RSP], 0);
+      LoadConstant(ARMEmitter::Size::i64Bit, EC_CALL_CHECKER_PC_REG, NewRIP);
      ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC));
      br(TMP2);
    } else {
@@ -101,39 +101,13 @@ DEF_OP(Jump) {
  PendingTargetLabel = &JumpTargets.try_emplace(Target).first->second;
 }

-static ARMEmitter::Condition MapBranchCC(IR::CondClassType Cond) {
-  switch (Cond.Val) {
-  case FEXCore::IR::COND_EQ: return ARMEmitter::Condition::CC_EQ;
-  case FEXCore::IR::COND_NEQ: return ARMEmitter::Condition::CC_NE;
-  case FEXCore::IR::COND_SGE: return ARMEmitter::Condition::CC_GE;
-  case FEXCore::IR::COND_SLT: return ARMEmitter::Condition::CC_LT;
-  case FEXCore::IR::COND_SGT: return ARMEmitter::Condition::CC_GT;
-  case FEXCore::IR::COND_SLE: return ARMEmitter::Condition::CC_LE;
-  case FEXCore::IR::COND_UGE: return ARMEmitter::Condition::CC_CS;
-  case FEXCore::IR::COND_ULT: return ARMEmitter::Condition::CC_CC;
-  case FEXCore::IR::COND_UGT: return ARMEmitter::Condition::CC_HI;
-  case FEXCore::IR::COND_ULE: return ARMEmitter::Condition::CC_LS;
-  case FEXCore::IR::COND_FLU: return ARMEmitter::Condition::CC_LT;
-  case FEXCore::IR::COND_FGE: return ARMEmitter::Condition::CC_GE;
-  case FEXCore::IR::COND_FLEU: return ARMEmitter::Condition::CC_LE;
-  case FEXCore::IR::COND_FGT: return ARMEmitter::Condition::CC_GT;
-  case FEXCore::IR::COND_FU: return ARMEmitter::Condition::CC_VS;
-  case FEXCore::IR::COND_FNU: return ARMEmitter::Condition::CC_VC;
-  case FEXCore::IR::COND_VS:
-  case FEXCore::IR::COND_VC:
-  case FEXCore::IR::COND_MI: return ARMEmitter::Condition::CC_MI;
-  case FEXCore::IR::COND_PL: return ARMEmitter::Condition::CC_PL;
-  default: LOGMAN_MSG_A_FMT("Unsupported compare type"); return ARMEmitter::Condition::CC_NV;
-  }
-}
-
 DEF_OP(CondJump) {
  auto Op = IROp->C<IR::IROp_CondJump>();

  auto TrueTargetLabel = &JumpTargets.try_emplace(Op->TrueBlock.ID()).first->second;

  if (Op->FromNZCV) {
-    b(MapBranchCC(Op->Cond), TrueTargetLabel);
+    b(MapCC(Op->Cond), TrueTargetLabel);
  } else {
    [[maybe_unused]] uint64_t Const;
    [[maybe_unused]] const bool isConst = IsInlineConstant(Op->Cmp2, &Const);
@@ -210,7 +184,7 @@ DEF_OP(Syscall) {
  if ((Flags & FEXCore::IR::SyscallFlags::NORETURN) != FEXCore::IR::SyscallFlags::NORETURN) {
    // Result is now in x0
    // Fix the stack and any values that were stepped on
-    FillStaticRegs(true, GPRSpillMask, FPRSpillMask);
+    FillStaticRegs(true, GPRSpillMask, FPRSpillMask, ARMEmitter::Reg::r1, ARMEmitter::Reg::r2);

    // Now the registers we've spilled are back in their original host registers
    // We can safely claim we are no longer in a syscall
@@ -311,7 +285,7 @@ DEF_OP(InlineSyscall) {
  if ((Op->Flags & FEXCore::IR::SyscallFlags::NORETURN) != FEXCore::IR::SyscallFlags::NORETURN) {
    // Now that we are done in the syscall we need to carefully peel back the state
    // First unspill the registers from before
-    FillStaticRegs(false, SpillMask);
+    FillStaticRegs(false, SpillMask, ~0U, ARMEmitter::Reg::r8, ARMEmitter::Reg::r1);

    // Now the registers we've spilled are back in their original host registers
    // We can safely claim we are no longer in a syscall
@@ -5,7 +5,7 @@ tags: backend|arm64
 $end_info$
 */

-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
+#include "Interface/Context/Context.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"

 namespace FEXCore::CPU {
@@ -18,12 +18,7 @@ DEF_OP(VInsGPR) {
  const auto ElementSize = Op->Header.ElementSize;
  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;

-  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2 || ElementSize == 1, "Unexpected {} size", __func__);
-  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                              ARMEmitter::SubRegSize::i8Bit;
+  const auto SubEmitSize = ConvertSubRegSize8(IROp);
  const auto ElementsPer128Bit = 16 / ElementSize;

  const auto Dst = GetVReg(Node);
@@ -66,7 +61,7 @@ DEF_OP(VInsGPR) {
    // Inserts the GPR value into the given V register.
    // Also automatically adjusts the index in the case of using the
    // moved upper lane.
-    const auto Insert = [&](const FEXCore::ARMEmitter::VRegister& reg, int index) {
+    const auto Insert = [&](const ARMEmitter::VRegister& reg, int index) {
      if (InUpperLane) {
        index -= ElementsPer128Bit;
      }
@@ -117,16 +112,7 @@ DEF_OP(VDupFromGPR) {
  const auto Src = GetReg(Op->Src.ID());

  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-  const auto ElementSize = IROp->ElementSize;
-
-  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2 || ElementSize == 1, "Unexpected {} element size: {}",
-                      __func__, ElementSize);
-
-  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                           ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-                                              ARMEmitter::SubRegSize::i8Bit;
+  const auto SubEmitSize = ConvertSubRegSize8(IROp);

  if (HostSupportsSVE256 && Is256Bit) {
    dup(SubEmitSize, Dst.Z(), Src);
@@ -216,14 +202,9 @@ DEF_OP(Vector_SToF) {
  const auto OpSize = IROp->Size;

  const auto ElementSize = Op->Header.ElementSize;
+  const auto SubEmitSize = ConvertSubRegSize248(IROp);
  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;

-  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2, "Unexpected {} size", __func__);
-  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                                              ARMEmitter::SubRegSize::i16Bit;
-
  const auto Dst = GetVReg(Node);
  const auto Vector = GetVReg(Op->Vector.ID());
  if (HostSupportsSVE256 && Is256Bit) {
@@ -253,14 +234,9 @@ DEF_OP(Vector_FToZS) {
  const auto OpSize = IROp->Size;

  const auto ElementSize = Op->Header.ElementSize;
+  const auto SubEmitSize = ConvertSubRegSize248(IROp);
  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;

-  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2, "Unexpected {} size", __func__);
-  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                                              ARMEmitter::SubRegSize::i16Bit;
-
  const auto Dst = GetVReg(Node);
  const auto Vector = GetVReg(Op->Vector.ID());
  if (HostSupportsSVE256 && Is256Bit) {
@@ -289,14 +265,8 @@ DEF_OP(Vector_FToS) {
  const auto Op = IROp->C<IR::IROp_Vector_FToS>();
  const auto OpSize = IROp->Size;

-  const auto ElementSize = Op->Header.ElementSize;
  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-
-  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2, "Unexpected {} size", __func__);
-  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                                              ARMEmitter::SubRegSize::i16Bit;
+  const auto SubEmitSize = ConvertSubRegSize248(IROp);

  const auto Dst = GetVReg(Node);
  const auto Vector = GetVReg(Op->Vector.ID());
@@ -323,15 +293,10 @@ DEF_OP(Vector_FToF) {
  const auto OpSize = IROp->Size;

  const auto ElementSize = Op->Header.ElementSize;
+  const auto SubEmitSize = ConvertSubRegSize248(IROp);
  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
  const auto Conv = (ElementSize << 8) | Op->SrcElementSize;

-  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2, "Unexpected {} size", __func__);
-  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                                              ARMEmitter::SubRegSize::i16Bit;
-
  const auto Dst = GetVReg(Node);
  const auto Vector = GetVReg(Op->Vector.ID());

@@ -353,23 +318,23 @@ DEF_OP(Vector_FToF) {

    switch (Conv) {
    case 0x0402: { // Float <- Half
-      zip1(FEXCore::ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Vector.Z(), Vector.Z());
-      fcvtlt(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Mask, Dst.Z());
+      zip1(ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Vector.Z(), Vector.Z());
+      fcvtlt(ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Mask, Dst.Z());
      break;
    }
    case 0x0804: { // Double <- Float
-      zip1(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Vector.Z(), Vector.Z());
-      fcvtlt(FEXCore::ARMEmitter::SubRegSize::i64Bit, Dst.Z(), Mask, Dst.Z());
+      zip1(ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Vector.Z(), Vector.Z());
+      fcvtlt(ARMEmitter::SubRegSize::i64Bit, Dst.Z(), Mask, Dst.Z());
      break;
    }
    case 0x0204: { // Half <- Float
-      fcvtnt(FEXCore::ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Mask, Vector.Z());
-      uzp2(FEXCore::ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Dst.Z(), Dst.Z());
+      fcvtnt(ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Mask, Vector.Z());
+      uzp2(ARMEmitter::SubRegSize::i16Bit, Dst.Z(), Dst.Z(), Dst.Z());
      break;
    }
    case 0x0408: { // Float <- Double
-      fcvtnt(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Mask, Vector.Z());
-      uzp2(FEXCore::ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Dst.Z(), Dst.Z());
+      fcvtnt(ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Mask, Vector.Z());
+      uzp2(ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Dst.Z(), Dst.Z());
      break;
    }
    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToF Type : 0x{:04x}", Conv); break;
@@ -391,18 +356,46 @@ DEF_OP(Vector_FToF) {
  }
 }

+DEF_OP(VFCVTL2) {
+  const auto Op = IROp->C<IR::IROp_VFCVTL2>();
+
+  const auto SubEmitSize = ConvertSubRegSize248(IROp);
+
+  const auto Dst = GetVReg(Node);
+  const auto Vector = GetVReg(Op->Vector.ID());
+
+  fcvtl2(SubEmitSize, Dst.D(), Vector.D());
+}
+
+DEF_OP(VFCVTN2) {
+  const auto Op = IROp->C<IR::IROp_VFCVTN2>();
+
+  const auto SubEmitSize = ConvertSubRegSize248(IROp);
+
+  const auto Dst = GetVReg(Node);
+  const auto VectorLower = GetVReg(Op->VectorLower.ID());
+  const auto VectorUpper = GetVReg(Op->VectorUpper.ID());
+
+  auto Lower = VectorLower;
+  if (Dst != VectorLower) {
+    mov(VTMP1.Q(), VectorLower.Q());
+    Lower = VTMP1;
+  }
+
+  fcvtn2(SubEmitSize, Lower.Q(), VectorUpper.Q());
+
+  if (Dst != VectorLower) {
+    mov(Dst.Q(), Lower.Q());
+  }
+}
+
 DEF_OP(Vector_FToI) {
  const auto Op = IROp->C<IR::IROp_Vector_FToI>();
  const auto OpSize = IROp->Size;

  const auto ElementSize = Op->Header.ElementSize;
+  const auto SubEmitSize = ConvertSubRegSize248(IROp);
  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
-  LOGMAN_THROW_AA_FMT(ElementSize == 8 || ElementSize == 4 || ElementSize == 2, "Unexpected {} size", __func__);
-
-  const auto SubEmitSize = ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
-                           ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-                           ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-                                              ARMEmitter::SubRegSize::i16Bit;

  const auto Dst = GetVReg(Node);
  const auto Vector = GetVReg(Op->Vector.ID());
@@ -425,15 +418,15 @@ DEF_OP(Vector_FToI) {
 // frinti having AdvSIMD, AdvSIMD scalar, and an SVE version),
 // we can't just use a lambda without some seriously ugly casting.
 // This is fairly self-contained otherwise.
-#define ROUNDING_FN(name) \
-  if (ElementSize == 2) { \
-    name(Dst.H(), Vector.H()); \
+#define ROUNDING_FN(name)        \
+  if (ElementSize == 2) {        \
+    name(Dst.H(), Vector.H());   \
  } else if (ElementSize == 4) { \
-    name(Dst.S(), Vector.S()); \
+    name(Dst.S(), Vector.S());   \
  } else if (ElementSize == 8) { \
-    name(Dst.D(), Vector.D()); \
-  } else { \
-    FEX_UNREACHABLE; \
+    name(Dst.D(), Vector.D());   \
+  } else {                       \
+    FEX_UNREACHABLE;             \
  }

      switch (Op->Round) {
@@ -457,5 +450,63 @@ DEF_OP(Vector_FToI) {
  }
 }

+DEF_OP(Vector_F64ToI32) {
+  const auto Op = IROp->C<IR::IROp_Vector_F64ToI32>();
+  const auto OpSize = IROp->Size;
+  const auto Round = Op->Round;
+
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto Dst = GetVReg(Node);
+  const auto Vector = GetVReg(Op->Vector.ID());
+  if (HostSupportsSVE128 || HostSupportsSVE256) {
+    const auto Mask = Is256Bit ? PRED_TMP_32B.Merging() : PRED_TMP_16B.Merging();
+    // First step is to round the f64 values to integrals (frint*)
+    // Then convert to integers using fcvtzs.
+    auto CVTReg = Dst.Z();
+    switch (Round) {
+    case IR::Round_Nearest.Val: frintn(ARMEmitter::SubRegSize::i64Bit, Dst.Z(), Mask, Vector.Z()); break;
+    case IR::Round_Negative_Infinity.Val: frintm(ARMEmitter::SubRegSize::i64Bit, Dst.Z(), Mask, Vector.Z()); break;
+    case IR::Round_Positive_Infinity.Val: frintp(ARMEmitter::SubRegSize::i64Bit, Dst.Z(), Mask, Vector.Z()); break;
+    case IR::Round_Towards_Zero.Val: CVTReg = Vector.Z(); break;
+    case IR::Round_Host.Val: frinti(ARMEmitter::SubRegSize::i64Bit, Dst.Z(), Mask, Vector.Z()); break;
+    }
+
+    fcvtzs(Dst.Z(), ARMEmitter::SubRegSize::i32Bit, Mask, CVTReg, ARMEmitter::SubRegSize::i64Bit);
+
+    ///< Fixup format of register that fcvtzs returns.
+    uzp1(ARMEmitter::SubRegSize::i32Bit, Dst.Z(), Dst.Z(), Dst.Z());
+    if (Op->EnsureZeroUpperHalf) {
+      ///< Match CVTPD2DQ/CVTTPD2DQ behaviour if necessary by zeroing the upper bits here.
+      if (Is256Bit) {
+        mov(Dst.Q(), Dst.Q());
+      } else {
+        mov(Dst.D(), Dst.D());
+      }
+    }
+  } else {
+    // This has a known precision issue that isn't easily resolvable without throwing away performance.
+    // Doing the conversion in multi-stage steps has an issue that you can lose precision in the f32->i32 step if your source was f64.
+    // To get around this with ASIMD FEX needs to use fcvtzs (Scalar, Integer, to GPR) for each F64 to be directly converted to i32.
+    // This is a very costly transform that the SVE path doesn't need to do since it supports f64->i32 directly.
+    // If this precision issue is necessary then we can add an option for it in the future.
+
+    ///< Round float to integral depending on rounding mode.
+    switch (Round) {
+    case FEXCore::IR::Round_Nearest.Val: frintn(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Vector.Q()); break;
+    case FEXCore::IR::Round_Negative_Infinity.Val: frintm(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Vector.Q()); break;
+    case FEXCore::IR::Round_Positive_Infinity.Val: frintp(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Vector.Q()); break;
+    case FEXCore::IR::Round_Towards_Zero.Val: frintz(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Vector.Q()); break;
+    case FEXCore::IR::Round_Host.Val: frinti(ARMEmitter::SubRegSize::i64Bit, Dst.Q(), Vector.Q()); break;
+    }
+
+    // Now narrow from f64 to f32.
+    fcvtn(ARMEmitter::SubRegSize::i32Bit, Dst.Q(), Dst.Q());
+
+    ///< Convert the two F32 integrals to real integers.
+    fcvtzs(ARMEmitter::SubRegSize::i32Bit, Dst.D(), Dst.D());
+  }
+}
+
 #undef DEF_OP
 } // namespace FEXCore::CPU
@@ -5,9 +5,7 @@ tags: backend|arm64
 $end_info$
 */

-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
-#include "Interface/IR/Passes/RegisterAllocationPass.h"

 namespace FEXCore::CPU {
 #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: MIT
-/*
-$info$
-tags: backend|arm64
-$end_info$
-*/
-
-#include "Interface/Core/JIT/Arm64/JITClass.h"
-
-namespace FEXCore::CPU {
-#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
-DEF_OP(GetHostFlag) {
-  auto Op = IROp->C<IR::IROp_GetHostFlag>();
-  ubfx(ARMEmitter::Size::i64Bit, GetReg(Node), GetReg(Op->Value.ID()), Op->Flag, 1);
-}
-
-#undef DEF_OP
-} // namespace FEXCore::CPU
@@ -13,7 +13,6 @@ $end_info$

 #include "FEXCore/Utils/Telemetry.h"
 #include "Interface/Context/Context.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/LookupCache.h"

 #include "Interface/Core/Dispatcher/Dispatcher.h"
@@ -48,8 +47,8 @@ static uint64_t LUDIV(uint64_t SrcHigh, uint64_t SrcLow, uint64_t Divisor) {
  return Res;
 }

-static int64_t LDIV(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
-  __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
+static int64_t LDIV(uint64_t SrcHigh, uint64_t SrcLow, int64_t Divisor) {
+  __int128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
  __int128_t Res = Source / Divisor;
  return Res;
 }
@@ -60,8 +59,8 @@ static uint64_t LUREM(uint64_t SrcHigh, uint64_t SrcLow, uint64_t Divisor) {
  return Res;
 }

-static int64_t LREM(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
-  __int128_t Source = (static_cast<__int128_t>(SrcHigh) << 64) | SrcLow;
+static int64_t LREM(uint64_t SrcHigh, uint64_t SrcLow, int64_t Divisor) {
+  __int128_t Source = (static_cast<__uint128_t>(SrcHigh) << 64) | SrcLow;
  __int128_t Res = Source % Divisor;
  return Res;
 }
@@ -469,13 +468,13 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::NodeID Node) {
 static void DirectBlockDelinker(FEXCore::Core::CpuStateFrame* Frame, FEXCore::Context::ExitFunctionLinkData* Record) {
  auto LinkerAddress = Frame->Pointers.Common.ExitFunctionLinker;
  uintptr_t branch = (uintptr_t)(Record)-8;
-  FEXCore::ARMEmitter::Emitter emit((uint8_t*)(branch), 8);
-  FEXCore::ARMEmitter::SingleUseForwardLabel l_BranchHost;
+  ARMEmitter::Emitter emit((uint8_t*)(branch), 8);
+  ARMEmitter::SingleUseForwardLabel l_BranchHost;
  emit.ldr(TMP1, &l_BranchHost);
  emit.blr(TMP1);
  emit.Bind(&l_BranchHost);
  emit.dc64(LinkerAddress);
-  FEXCore::ARMEmitter::Emitter::ClearICache((void*)branch, 8);
+  ARMEmitter::Emitter::ClearICache((void*)branch, 8);
 }

 static void IndirectBlockDelinker(FEXCore::Core::CpuStateFrame* Frame, FEXCore::Context::ExitFunctionLinkData* Record) {
@@ -497,12 +496,12 @@ static uint64_t Arm64JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame* Fram
  uintptr_t branch = (uintptr_t)(Record)-8;

  auto offset = HostCode / 4 - branch / 4;
-  if (vixl::IsInt26(offset)) {
+  if (ARMEmitter::Emitter::IsInt26(offset)) {
    // optimal case - can branch directly
    // patch the code
-    FEXCore::ARMEmitter::Emitter emit((uint8_t*)(branch), 4);
+    ARMEmitter::Emitter emit((uint8_t*)(branch), 4);
    emit.b(offset);
-    FEXCore::ARMEmitter::Emitter::ClearICache((void*)branch, 4);
+    ARMEmitter::Emitter::ClearICache((void*)branch, 4);

    // Add de-linking handler
    Thread->LookupCache->AddBlockLink(GuestRip, Record, DirectBlockDelinker);
@@ -522,27 +521,20 @@ void Arm64JITCore::Op_NoOp(const IR::IROp_Header* IROp, IR::NodeID Node) {}
 Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::InternalThreadState* Thread)
  : CPUBackend(Thread, INITIAL_CODE_SIZE, MAX_CODE_SIZE)
  , Arm64Emitter(ctx)
-  , HostSupportsSVE128 {ctx->HostFeatures.SupportsSVE}
-  , HostSupportsSVE256 {ctx->HostFeatures.SupportsAVX}
+  , HostSupportsSVE128 {ctx->HostFeatures.SupportsSVE128}
+  , HostSupportsSVE256 {ctx->HostFeatures.SupportsSVE256}
+  , HostSupportsAVX256 {ctx->HostFeatures.SupportsAVX && ctx->HostFeatures.SupportsSVE256}
  , HostSupportsRPRES {ctx->HostFeatures.SupportsRPRES}
  , HostSupportsAFP {ctx->HostFeatures.SupportsAFP}
  , CTX {ctx} {

  RAPass = Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA");

-  RAPass->AllocateRegisterSet(RegisterClasses);
-
  RAPass->AddRegisters(FEXCore::IR::GPRClass, GeneralRegisters.size());
  RAPass->AddRegisters(FEXCore::IR::GPRFixedClass, StaticRegisters.size());
  RAPass->AddRegisters(FEXCore::IR::FPRClass, GeneralFPRegisters.size());
  RAPass->AddRegisters(FEXCore::IR::FPRFixedClass, StaticFPRegisters.size());
-  RAPass->AddRegisters(FEXCore::IR::GPRPairClass, GeneralPairRegisters.size());
-  RAPass->AddRegisters(FEXCore::IR::ComplexClass, 1);
-
-  for (uint32_t i = 0; i < GeneralPairRegisters.size(); ++i) {
-    RAPass->AddRegisterConflict(FEXCore::IR::GPRClass, i * 2, FEXCore::IR::GPRPairClass, i);
-    RAPass->AddRegisterConflict(FEXCore::IR::GPRClass, i * 2 + 1, FEXCore::IR::GPRPairClass, i);
-  }
+  RAPass->PairRegs = PairRegisters;

  {
    // Set up pointers that the JIT needs to load
@@ -669,7 +661,7 @@ bool Arm64JITCore::IsGPRPair(IR::NodeID Node) const {
 }

 CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, const FEXCore::IR::IRListView* IR, FEXCore::Core::DebugData* DebugData,
-                                                   FEXCore::IR::RegisterAllocationData* RAData) {
+                                                   const FEXCore::IR::RegisterAllocationData* RAData) {
  FEXCORE_PROFILE_SCOPED("Arm64::CompileCode");

  JumpTargets.clear();
@@ -732,14 +724,12 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, const FEXCore
         offsetof(FEXCore::Core::InternalThreadState, InterruptFaultPage) - offsetof(FEXCore::Core::InternalThreadState, BaseFrameState));
  }

-  // LOGMAN_THROW_A_FMT(RAData->HasFullRA(), "Arm64 JIT only works with RA");
-
  SpillSlots = RAData->SpillSlots();

  if (SpillSlots) {
    const auto TotalSpillSlotsSize = SpillSlots * MaxSpillSlotSize;

-    if (vixl::aarch64::Assembler::IsImmAddSub(TotalSpillSlotsSize)) {
+    if (ARMEmitter::IsImmAddSub(TotalSpillSlotsSize)) {
      sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, TotalSpillSlotsSize);
    } else {
      LoadConstant(ARMEmitter::Size::i64Bit, TMP1, TotalSpillSlotsSize);
@@ -882,7 +872,7 @@ void Arm64JITCore::ResetStack() {

  const auto TotalSpillSlotsSize = SpillSlots * MaxSpillSlotSize;

-  if (vixl::aarch64::Assembler::IsImmAddSub(TotalSpillSlotsSize)) {
+  if (ARMEmitter::IsImmAddSub(TotalSpillSlotsSize)) {
    add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, TotalSpillSlotsSize);
  } else {
    // Too big to fit in a 12bit immediate
@@ -895,12 +885,4 @@ fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl*
  return fextl::make_unique<Arm64JITCore>(ctx, Thread);
 }

-CPUBackendFeatures GetArm64JITBackendFeatures() {
-  return CPUBackendFeatures {
-    .SupportsFlags = true,
-    .SupportsSaturatingRoundingShifts = true,
-    .SupportsVTBL2 = true,
-  };
-}
-
 } // namespace FEXCore::CPU
@@ -8,7 +8,6 @@ $end_info$
 #pragma once

 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/IR/IR.h"
@@ -24,6 +23,8 @@ $end_info$
 #include <FEXCore/fextl/string.h>
 #include <FEXCore/fextl/vector.h>

+#include <CodeEmitter/Emitter.h>
+
 #include <array>
 #include <cstdint>
 #include <utility>
@@ -46,7 +47,7 @@ public:

  [[nodiscard]]
  CPUBackend::CompiledCode CompileCode(uint64_t Entry, const FEXCore::IR::IRListView* IR, FEXCore::Core::DebugData* DebugData,
-                                       FEXCore::IR::RegisterAllocationData* RAData) override;
+                                       const FEXCore::IR::RegisterAllocationData* RAData) override;

  [[nodiscard]]
  void* MapRegion(void* HostPtr, uint64_t, uint64_t) override {
@@ -71,6 +72,7 @@ private:

  const bool HostSupportsSVE128 {};
  const bool HostSupportsSVE256 {};
+  const bool HostSupportsAVX256 {};
  const bool HostSupportsRPRES {};
  const bool HostSupportsAFP {};

@@ -83,7 +85,7 @@ private:
  fextl::map<IR::NodeID, ARMEmitter::BiDirectionalLabel> JumpTargets;

  [[nodiscard]]
-  FEXCore::ARMEmitter::Register GetReg(IR::NodeID Node) const {
+  ARMEmitter::Register GetReg(IR::NodeID Node) const {
    const auto Reg = GetPhys(Node);

    LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRFixedClass.Val || Reg.Class == IR::GPRClass.Val, "Unexpected Class: {}", Reg.Class);
@@ -98,7 +100,7 @@ private:
  }

  [[nodiscard]]
-  FEXCore::ARMEmitter::VRegister GetVReg(IR::NodeID Node) const {
+  ARMEmitter::VRegister GetVReg(IR::NodeID Node) const {
    const auto Reg = GetPhys(Node);

    LOGMAN_THROW_AA_FMT(Reg.Class == IR::FPRFixedClass.Val || Reg.Class == IR::FPRClass.Val, "Unexpected Class: {}", Reg.Class);
@@ -113,12 +115,12 @@ private:
  }

  [[nodiscard]]
-  std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register> GetRegPair(IR::NodeID Node) const {
+  std::pair<ARMEmitter::Register, ARMEmitter::Register> GetRegPair(IR::NodeID Node) const {
    const auto Reg = GetPhys(Node);

    LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRPairClass.Val, "Unexpected Class: {}", Reg.Class);

-    return GeneralPairRegisters[Reg.Reg];
+    return std::make_pair(GeneralRegisters[Reg.Reg], GeneralRegisters[Reg.Reg + 1]);
  }

  [[nodiscard]]
@@ -134,7 +136,7 @@ private:
  }

  [[nodiscard]]
-  FEXCore::ARMEmitter::Register GetZeroableReg(IR::OrderedNodeWrapper Src) const {
+  ARMEmitter::Register GetZeroableReg(IR::OrderedNodeWrapper Src) const {
    uint64_t Const;
    if (IsInlineConstant(Src, &Const)) {
      LOGMAN_THROW_AA_FMT(Const == 0, "Only valid constant");
@@ -154,6 +156,99 @@ private:
                                         ARMEmitter::ShiftType::ROR;
  }

+  [[nodiscard]]
+  ARMEmitter::Size ConvertSize(const IR::IROp_Header* Op) {
+    return Op->Size == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+  }
+
+  [[nodiscard]]
+  ARMEmitter::Size ConvertSize48(const IR::IROp_Header* Op) {
+    LOGMAN_THROW_AA_FMT(Op->Size == 4 || Op->Size == 8, "Invalid size");
+    return ConvertSize(Op);
+  }
+
+  [[nodiscard]]
+  ARMEmitter::SubRegSize ConvertSubRegSize16(uint8_t ElementSize) {
+    LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8 || ElementSize == 16, "Invalid size");
+    return ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
+           ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
+           ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+           ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit :
+                              ARMEmitter::SubRegSize::i128Bit;
+  }
+
+  [[nodiscard]]
+  ARMEmitter::SubRegSize ConvertSubRegSize16(const IR::IROp_Header* Op) {
+    return ConvertSubRegSize16(Op->ElementSize);
+  }
+
+  [[nodiscard]]
+  ARMEmitter::SubRegSize ConvertSubRegSize8(uint8_t ElementSize) {
+    LOGMAN_THROW_AA_FMT(ElementSize != 16, "Invalid size");
+    return ConvertSubRegSize16(ElementSize);
+  }
+
+  [[nodiscard]]
+  ARMEmitter::SubRegSize ConvertSubRegSize8(const IR::IROp_Header* Op) {
+    return ConvertSubRegSize8(Op->ElementSize);
+  }
+
+  [[nodiscard]]
+  ARMEmitter::SubRegSize ConvertSubRegSize4(const IR::IROp_Header* Op) {
+    LOGMAN_THROW_AA_FMT(Op->ElementSize != 8, "Invalid size");
+    return ConvertSubRegSize8(Op);
+  }
+
+  [[nodiscard]]
+  ARMEmitter::SubRegSize ConvertSubRegSize248(const IR::IROp_Header* Op) {
+    LOGMAN_THROW_AA_FMT(Op->ElementSize != 1, "Invalid size");
+    return ConvertSubRegSize8(Op);
+  }
+
+  [[nodiscard]]
+  ARMEmitter::VectorRegSizePair ConvertSubRegSizePair16(const IR::IROp_Header* Op) {
+    return ARMEmitter::ToVectorSizePair(ConvertSubRegSize16(Op));
+  }
+
+  [[nodiscard]]
+  ARMEmitter::VectorRegSizePair ConvertSubRegSizePair8(const IR::IROp_Header* Op) {
+    LOGMAN_THROW_AA_FMT(Op->ElementSize != 16, "Invalid size");
+    return ConvertSubRegSizePair16(Op);
+  }
+
+  [[nodiscard]]
+  ARMEmitter::VectorRegSizePair ConvertSubRegSizePair248(const IR::IROp_Header* Op) {
+    LOGMAN_THROW_AA_FMT(Op->ElementSize != 1, "Invalid size");
+    return ConvertSubRegSizePair8(Op);
+  }
+
+  [[nodiscard]]
+  ARMEmitter::Condition MapCC(IR::CondClassType Cond) {
+    switch (Cond.Val) {
+    case FEXCore::IR::COND_EQ: return ARMEmitter::Condition::CC_EQ;
+    case FEXCore::IR::COND_NEQ: return ARMEmitter::Condition::CC_NE;
+    case FEXCore::IR::COND_SGE: return ARMEmitter::Condition::CC_GE;
+    case FEXCore::IR::COND_SLT: return ARMEmitter::Condition::CC_LT;
+    case FEXCore::IR::COND_SGT: return ARMEmitter::Condition::CC_GT;
+    case FEXCore::IR::COND_SLE: return ARMEmitter::Condition::CC_LE;
+    case FEXCore::IR::COND_UGE: return ARMEmitter::Condition::CC_CS;
+    case FEXCore::IR::COND_ULT: return ARMEmitter::Condition::CC_CC;
+    case FEXCore::IR::COND_UGT: return ARMEmitter::Condition::CC_HI;
+    case FEXCore::IR::COND_ULE: return ARMEmitter::Condition::CC_LS;
+    case FEXCore::IR::COND_FLU: return ARMEmitter::Condition::CC_LT;
+    case FEXCore::IR::COND_FGE: return ARMEmitter::Condition::CC_GE;
+    case FEXCore::IR::COND_FLEU: return ARMEmitter::Condition::CC_LE;
+    case FEXCore::IR::COND_FGT: return ARMEmitter::Condition::CC_GT;
+    case FEXCore::IR::COND_FU: return ARMEmitter::Condition::CC_VS;
+    case FEXCore::IR::COND_FNU: return ARMEmitter::Condition::CC_VC;
+    case FEXCore::IR::COND_VS:
+    case FEXCore::IR::COND_VC:
+    case FEXCore::IR::COND_MI: return ARMEmitter::Condition::CC_MI;
+    case FEXCore::IR::COND_PL: return ARMEmitter::Condition::CC_PL;
+    default: LOGMAN_MSG_A_FMT("Unsupported compare type"); return ARMEmitter::Condition::CC_NV;
+    }
+  }
+
  [[nodiscard]]
  bool IsFPR(IR::NodeID Node) const;
  [[nodiscard]]
@@ -162,8 +257,8 @@ private:
  bool IsGPRPair(IR::NodeID Node) const;

  [[nodiscard]]
-  FEXCore::ARMEmitter::ExtendedMemOperand GenerateMemOperand(
-    uint8_t AccessSize, FEXCore::ARMEmitter::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale);
+  ARMEmitter::ExtendedMemOperand GenerateMemOperand(uint8_t AccessSize, ARMEmitter::Register Base, IR::OrderedNodeWrapper Offset,
+                                                    IR::MemOffsetType OffsetType, uint8_t OffsetScale);

  // NOTE: Will use TMP1 as a way to encode immediates that happen to fall outside
  //       the limits of the scalar plus immediate variant of SVE load/stores.
@@ -171,8 +266,8 @@ private:
  //       TMP1 is safe to use again once this memory operand is used with its
  //       equivalent loads or stores that this was called for.
  [[nodiscard]]
-  FEXCore::ARMEmitter::SVEMemOperand GenerateSVEMemOperand(uint8_t AccessSize, FEXCore::ARMEmitter::Register Base,
-                                                           IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale);
+  ARMEmitter::SVEMemOperand GenerateSVEMemOperand(uint8_t AccessSize, ARMEmitter::Register Base, IR::OrderedNodeWrapper Offset,
+                                                  IR::MemOffsetType OffsetType, uint8_t OffsetScale);

  [[nodiscard]]
  bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr) const;
@@ -187,7 +282,7 @@ private:
  // This is purely a debugging aid for developers to see if they are in JIT code space when inspecting raw memory
  void EmitDetectionString();
  IR::RegisterAllocationPass* RAPass;
-  IR::RegisterAllocationData* RAData;
+  const IR::RegisterAllocationData* RAData;
  FEXCore::Core::DebugData* DebugData;

  void ResetStack();
@@ -250,6 +345,10 @@ private:
  uint32_t SpillSlots {};
  using OpType = void (Arm64JITCore::*)(const IR::IROp_Header* IROp, IR::NodeID Node);

+  using ScalarFMAOpCaller =
+    std::function<void(ARMEmitter::VRegister Dst, ARMEmitter::VRegister Src1, ARMEmitter::VRegister Src2, ARMEmitter::VRegister Src3)>;
+  void VFScalarFMAOperation(uint8_t OpSize, uint8_t ElementSize, ScalarFMAOpCaller ScalarEmit, ARMEmitter::VRegister Dst,
+                            ARMEmitter::VRegister Vector1, ARMEmitter::VRegister Vector2, ARMEmitter::VRegister Addend);
  using ScalarBinaryOpCaller = std::function<void(ARMEmitter::VRegister Dst, ARMEmitter::VRegister Src1, ARMEmitter::VRegister Src2)>;
  void VFScalarOperation(uint8_t OpSize, uint8_t ElementSize, bool ZeroUpperBits, ScalarBinaryOpCaller ScalarEmit,
                         ARMEmitter::VRegister Dst, ARMEmitter::VRegister Vector1, ARMEmitter::VRegister Vector2);
@@ -257,6 +356,10 @@ private:
  void VFScalarUnaryOperation(uint8_t OpSize, uint8_t ElementSize, bool ZeroUpperBits, ScalarUnaryOpCaller ScalarEmit, ARMEmitter::VRegister Dst,
                              ARMEmitter::VRegister Vector1, std::variant<ARMEmitter::VRegister, ARMEmitter::Register> Vector2);

+  void Emulate128BitGather(size_t Size, size_t ElementSize, ARMEmitter::VRegister Dst, ARMEmitter::VRegister IncomingDst,
+                           std::optional<ARMEmitter::Register> BaseAddr, ARMEmitter::VRegister VectorIndexLow,
+                           std::optional<ARMEmitter::VRegister> VectorIndexHigh, ARMEmitter::VRegister MaskReg, size_t VectorIndexSize,
+                           size_t DataElementOffsetStart, size_t IndexElementOffsetStart, uint8_t OffsetScale);
  // Runtime selection;
  // Load and store TSO memory style
  OpType RT_LoadMemTSO;
@@ -10,7 +10,6 @@ $end_info$
 #endif

 #include "Interface/Context/Context.h"
-#include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "FEXCore/Debug/InternalThreadState.h"

@@ -28,9 +27,9 @@ DEF_OP(GuestOpcode) {
 DEF_OP(Fence) {
  auto Op = IROp->C<IR::IROp_Fence>();
  switch (Op->Fence) {
-  case IR::Fence_Load.Val: dmb(FEXCore::ARMEmitter::BarrierScope::LD); break;
-  case IR::Fence_LoadStore.Val: dmb(FEXCore::ARMEmitter::BarrierScope::SY); break;
-  case IR::Fence_Store.Val: dmb(FEXCore::ARMEmitter::BarrierScope::ST); break;
+  case IR::Fence_Load.Val: dmb(ARMEmitter::BarrierScope::LD); break;
+  case IR::Fence_LoadStore.Val: dmb(ARMEmitter::BarrierScope::SY); break;
+  case IR::Fence_Store.Val: dmb(ARMEmitter::BarrierScope::ST); break;
  default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
  }
 }
@@ -99,6 +98,7 @@ DEF_OP(GetRoundingMode) {
 DEF_OP(SetRoundingMode) {
  auto Op = IROp->C<IR::IROp_SetRoundingMode>();
  auto Src = GetReg(Op->RoundMode.ID());
+  auto MXCSR = GetReg(Op->MXCSR.ID());

  // As above, setup the rounding flags in [31:30]
  rbit(ARMEmitter::Size::i32Bit, TMP2, Src);
@@ -117,10 +117,48 @@ DEF_OP(SetRoundingMode) {
  lsr(ARMEmitter::Size::i64Bit, TMP2, Src, 2);
  bfi(ARMEmitter::Size::i64Bit, TMP1, TMP2, 24, 1);

+  if (Op->SetDAZ && HostSupportsAFP) {
+    // Extract DAZ from MXCSR and insert to in FPCR.FIZ
+    bfxil(ARMEmitter::Size::i64Bit, TMP1, MXCSR, 6, 1);
+  }
+
  // Now save the new FPCR
  msr(ARMEmitter::SystemRegister::FPCR, TMP1);
 }

+DEF_OP(PushRoundingMode) {
+  auto Op = IROp->C<IR::IROp_PushRoundingMode>();
+  auto Dest = GetReg(Node);
+
+  // Save the old rounding mode
+  mrs(Dest, ARMEmitter::SystemRegister::FPCR);
+
+  // vixl simulator doesn't support anything beyond ties-to-even rounding
+  if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
+    return;
+  }
+
+  // Insert the rounding flags, reversing the mode bits as above
+  if (Op->RoundMode == 3) {
+    orr(ARMEmitter::Size::i64Bit, TMP1, Dest, 3 << 22);
+  } else if (Op->RoundMode == 0) {
+    and_(ARMEmitter::Size::i64Bit, TMP1, Dest, ~(3 << 22));
+  } else {
+    LOGMAN_THROW_AA_FMT(Op->RoundMode == 1 || Op->RoundMode == 2, "expect a valid round mode");
+
+    and_(ARMEmitter::Size::i64Bit, TMP1, Dest, ~(Op->RoundMode << 22));
+    orr(ARMEmitter::Size::i64Bit, TMP1, TMP1, (Op->RoundMode == 2 ? 1 : 2) << 22);
+  }
+
+  // Now save the new FPCR
+  msr(ARMEmitter::SystemRegister::FPCR, TMP1);
+}
+
+DEF_OP(PopRoundingMode) {
+  auto Op = IROp->C<IR::IROp_PopRoundingMode>();
+  msr(ARMEmitter::SystemRegister::FPCR, GetReg(Op->FPCR.ID()));
+}
+
 DEF_OP(Print) {
  auto Op = IROp->C<IR::IROp_Print>();

@@ -195,7 +233,7 @@ DEF_OP(ProcessorID) {

  // Now that we are done in the syscall we need to carefully peel back the state
  // First unspill the registers from before
-  FillStaticRegs(false, SpillMask);
+  FillStaticRegs(false, SpillMask, ~0U, ARMEmitter::Reg::r8, ARMEmitter::Reg::r2);

  // Now the registers we've spilled are back in their original host registers
  // We can safely claim we are no longer in a syscall
@@ -11,12 +11,14 @@ namespace FEXCore::CPU {
 #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
 DEF_OP(ExtractElementPair) {
  auto Op = IROp->C<IR::IROp_ExtractElementPair>();
-  LOGMAN_THROW_AA_FMT(Op->Header.Size == 4 || Op->Header.Size == 8, "Invalid size");
-  const auto EmitSize = Op->Header.Size == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;

-  const auto Src = GetRegPair(Op->Pair.ID());
-  const std::array<ARMEmitter::Register, 2> Regs = {Src.first, Src.second};
-  mov(EmitSize, GetReg(Node), Regs[Op->Element]);
+  const auto Dst = GetReg(Node);
+  const auto Pair = GetRegPair(Op->Pair.ID());
+  const auto Src = Op->Element == 0 ? Pair.first : Pair.second;
+
+  if (Dst != Src) {
+    mov(ConvertSize48(IROp), Dst, Src);
+  }
 }

 DEF_OP(CreateElementPair) {
@@ -42,5 +44,25 @@ DEF_OP(CreateElementPair) {
  }
 }

+DEF_OP(Copy) {
+  auto Op = IROp->C<IR::IROp_Copy>();
+
+  mov(ARMEmitter::Size::i64Bit, GetReg(Node), GetReg(Op->Source.ID()));
+}
+
+DEF_OP(Swap1) {
+  auto Op = IROp->C<IR::IROp_Swap1>();
+  auto A = GetReg(Op->A.ID()), B = GetReg(Op->B.ID());
+  LOGMAN_THROW_A_FMT(B == GetReg(Node), "Invariant");
+
+  mov(ARMEmitter::Size::i64Bit, TMP1, A);
+  mov(ARMEmitter::Size::i64Bit, A, B);
+  mov(ARMEmitter::Size::i64Bit, B, TMP1);
+}
+
+DEF_OP(Swap2) {
+  // Implemented above
+}
+
 #undef DEF_OP
 } // namespace FEXCore::CPU
@@ -17,6 +17,5 @@ class CPUBackend;

 [[nodiscard]]
 fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::InternalThreadState* Thread);
-CPUBackendFeatures GetArm64JITBackendFeatures();

 } // namespace FEXCore::CPU