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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2024-05-29 12:32:07 -04:00
1 parent 665491adf8
commit 11ec71a4ce
7 files changed
+487 -652
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unittests/InstructionCountCI/Atomics.json
+12 -20
View File
@@ -1517,7 +1517,7 @@
]
},
"lock dec dword [rax]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
@@ -1525,14 +1525,12 @@
"cset w20, hs",
"subs w26, w27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock dec qword [rax]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
@@ -1540,10 +1538,8 @@
"cset w20, hs",
"subs x26, x27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock inc byte [rax]": {
@@ -1577,7 +1573,7 @@
]
},
"lock inc dword [rax]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -1585,14 +1581,12 @@
"cset w20, hs",
"adds w26, w27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock inc qword [rax]": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -1600,10 +1594,8 @@
"cset w20, hs",
"adds x26, x27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
}
}
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+68 -88
View File
@@ -909,7 +909,7 @@
]
},
"rcl al, 2": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": "GROUP2 0xC0 /2",
"ExpectedArm64ASM": [
"uxtb w20, w4",
@@ -925,30 +925,26 @@
"bfi x21, x22, #36, #1",
"bfi x21, x20, #19, #8",
"bfi x21, x22, #27, #1",
"mov x0, x21",
"bfxil x0, x20, #0, #8",
"mov x20, x0",
"ror x21, x20, #62",
"bfxil x4, x21, #0, #8",
"ror x20, x20, #61",
"bfxil x21, x20, #0, #8",
"ror x20, x21, #62",
"bfxil x4, x20, #0, #8",
"ror x20, x21, #61",
"rmif x20, #63, #nzCv"
]
},
"rcr al, 2": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xC0 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"uxtb w21, w4",
"mov x0, x21",
"bfi x0, x20, #8, #1",
"mov x20, x0",
"bfi x20, x20, #9, #9",
"bfi x20, x20, #18, #18",
"bfi x20, x20, #36, #9",
"lsr w21, w20, #2",
"bfxil x4, x21, #0, #8",
"rmif x20, #0, #nzCv"
"bfi x21, x20, #8, #1",
"bfi x21, x21, #9, #9",
"bfi x21, x21, #18, #18",
"bfi x21, x21, #36, #9",
"lsr w20, w21, #2",
"bfxil x4, x20, #0, #8",
"rmif x21, #0, #nzCv"
]
},
"shl al, 2": {
@@ -1038,7 +1034,7 @@
]
},
"rcl ax, 2": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xC1 /2",
"ExpectedArm64ASM": [
"uxth w20, w4",
@@ -1050,12 +1046,10 @@
"bfi x21, x22, #46, #1",
"bfi x21, x20, #13, #16",
"bfi x21, x22, #29, #1",
"mov x0, x21",
"bfxil x0, x20, #0, #16",
"mov x20, x0",
"ror x21, x20, #62",
"bfxil x4, x21, #0, #16",
"ror x20, x20, #61",
"bfxil x21, x20, #0, #16",
"ror x20, x21, #62",
"bfxil x4, x20, #0, #16",
"ror x20, x21, #61",
"rmif x20, #63, #nzCv"
]
},
@@ -1082,19 +1076,17 @@
]
},
"rcr ax, 2": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP2 0xC1 /3",
"ExpectedArm64ASM": [
"cset w20, hs",
"uxth w21, w4",
"mov x0, x21",
"bfi x0, x20, #16, #1",
"mov x20, x0",
"bfi x20, x20, #17, #17",
"bfi x20, x20, #34, #17",
"lsr w21, w20, #2",
"bfxil x4, x21, #0, #16",
"rmif x20, #0, #nzCv"
"bfi x21, x20, #16, #1",
"bfi x21, x21, #17, #17",
"bfi x21, x21, #34, #17",
"lsr w20, w21, #2",
"bfxil x4, x20, #0, #16",
"rmif x21, #0, #nzCv"
]
},
"rcr eax, 2": {
@@ -1573,11 +1565,11 @@
]
},
"rcl al, cl": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 26,
"Comment": "GROUP2 0xd2 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x6c",
"cbz x20, #+0x64",
"and w20, w5, #0x1f",
"uxtb w21, w4",
"mov w22, #0x0",
@@ -1592,40 +1584,36 @@
"bfi x22, x23, #36, #1",
"bfi x22, x21, #19, #8",
"bfi x22, x23, #27, #1",
"mov x0, x22",
"bfxil x0, x21, #0, #8",
"mov x21, x0",
"neg w22, w20",
"ror x22, x21, x22",
"bfxil x4, x22, #0, #8",
"bfxil x22, x21, #0, #8",
"neg w21, w20",
"ror x21, x22, x21",
"bfxil x4, x21, #0, #8",
"mov w23, #0x3f",
"sub x20, x23, x20",
"ror x20, x21, x20",
"ror x20, x22, x20",
"rmif x20, #63, #nzCv",
"eor x20, x20, x22, lsr #7",
"eor x20, x20, x21, lsr #7",
"rmif x20, #0, #nzcV"
]
},
"rcr al, cl": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "GROUP2 0xd2 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x40",
"cbz x20, #+0x38",
"cset w20, hs",
"uxtb w21, w4",
"mov x0, x21",
"bfi x0, x20, #8, #1",
"mov x20, x0",
"bfi x20, x20, #9, #9",
"bfi x20, x20, #18, #18",
"bfi x20, x20, #36, #9",
"lsr w21, w20, w5",
"bfxil x4, x21, #0, #8",
"bfi x21, x20, #8, #1",
"bfi x21, x21, #9, #9",
"bfi x21, x21, #18, #18",
"bfi x21, x21, #36, #9",
"lsr w20, w21, w5",
"bfxil x4, x20, #0, #8",
"sub w22, w5, #0x1 (1)",
"lsr w20, w20, w22",
"rmif x20, #63, #nzCv",
"eor w20, w21, w21, lsr #1",
"lsr w21, w21, w22",
"rmif x21, #63, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x20, #6, #nzcV"
]
},
@@ -1760,11 +1748,11 @@
]
},
"rcl ax, cl": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 22,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x5c",
"cbz x20, #+0x54",
"and w20, w5, #0x1f",
"uxth w21, w4",
"mov w22, #0x0",
@@ -1775,17 +1763,15 @@
"bfi x22, x23, #46, #1",
"bfi x22, x21, #13, #16",
"bfi x22, x23, #29, #1",
"mov x0, x22",
"bfxil x0, x21, #0, #16",
"mov x21, x0",
"neg w22, w20",
"ror x22, x21, x22",
"bfxil x4, x22, #0, #16",
"bfxil x22, x21, #0, #16",
"neg w21, w20",
"ror x21, x22, x21",
"bfxil x4, x21, #0, #16",
"mov w23, #0x3f",
"sub x20, x23, x20",
"ror x20, x21, x20",
"ror x20, x22, x20",
"rmif x20, #63, #nzCv",
"eor x20, x20, x22, lsr #15",
"eor x20, x20, x21, lsr #15",
"rmif x20, #0, #nzcV"
]
},
@@ -1830,24 +1816,22 @@
]
},
"rcr ax, cl": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w5, #0x1f",
"cbz x20, #+0x3c",
"cbz x20, #+0x34",
"cset w20, hs",
"uxth w21, w4",
"mov x0, x21",
"bfi x0, x20, #16, #1",
"mov x20, x0",
"bfi x20, x20, #17, #17",
"bfi x20, x20, #34, #17",
"lsr w21, w20, w5",
"bfxil x4, x21, #0, #16",
"bfi x21, x20, #16, #1",
"bfi x21, x21, #17, #17",
"bfi x21, x21, #34, #17",
"lsr w20, w21, w5",
"bfxil x4, x20, #0, #16",
"sub w22, w5, #0x1 (1)",
"lsr w20, w20, w22",
"rmif x20, #63, #nzCv",
"eor w20, w21, w21, lsr #1",
"lsr w21, w21, w22",
"rmif x21, #63, #nzCv",
"eor w20, w20, w20, lsr #1",
"rmif x20, #14, #nzcV"
]
},
@@ -2080,7 +2064,7 @@
]
},
"div bl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xf6 /6",
"ExpectedArm64ASM": [
"uxtb w20, w7",
@@ -2092,14 +2076,12 @@
"uxth w1, w20",
"udiv w2, w0, w1",
"msub w20, w2, w1, w0",
"mov x0, x22",
"bfi x0, x20, #8, #8",
"mov x20, x0",
"bfxil x4, x20, #0, #16"
"bfi x22, x20, #8, #8",
"bfxil x4, x22, #0, #16"
]
},
"idiv bl": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf6 /7",
"ExpectedArm64ASM": [
"uxtb w20, w7",
@@ -2109,10 +2091,8 @@
"sdiv x22, x21, x20",
"sdiv x0, x21, x20",
"msub x20, x0, x20, x21",
"mov x0, x22",
"bfi x0, x20, #8, #8",
"mov x20, x0",
"bfxil x4, x20, #0, #16"
"bfi x22, x20, #8, #8",
"bfxil x4, x22, #0, #16"
]
},
"test bx, 1": {
unittests/InstructionCountCI/H0F38.json
+20 -32
View File
@@ -656,7 +656,7 @@
]
},
"sha1msg2 xmm0, xmm1": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 11,
"Comment": [
"0x66 0x0f 0x38 0xca"
],
@@ -665,17 +665,13 @@
"ext v2.16b, v2.16b, v17.16b, #12",
"eor v2.16b, v16.16b, v2.16b",
"shl v3.4s, v2.4s, #1",
"mov v0.16b, v3.16b",
"usra v0.4s, v2.4s, #31",
"mov v2.16b, v0.16b",
"dup v3.4s, v2.s[3]",
"eor v3.16b, v16.16b, v3.16b",
"shl v4.4s, v3.4s, #1",
"mov v0.16b, v4.16b",
"usra v0.4s, v3.4s, #31",
"mov v3.16b, v0.16b",
"mov v16.16b, v2.16b",
"mov v16.s[0], v3.s[0]"
"usra v3.4s, v2.4s, #31",
"dup v2.4s, v3.s[3]",
"eor v2.16b, v16.16b, v2.16b",
"shl v4.4s, v2.4s, #1",
"usra v4.4s, v2.4s, #31",
"mov v16.16b, v3.16b",
"mov v16.s[0], v4.s[0]"
]
},
"sha256rnds2 xmm0, xmm1": {
@@ -861,7 +857,7 @@
]
},
"adcx eax, ebx": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": [
"0x66 0x0f 0x38 0xf6"
],
@@ -878,14 +874,12 @@
"cset x21, ls",
"cmp x20, #0x1 (1)",
"csel x20, x21, x23, eq",
"mov w0, w22",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
"bfi w22, w20, #29, #1",
"msr nzcv, x22"
]
},
"adcx rax, rbx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0x66 REX.W 0x0f 0x38 0xf6"
],
@@ -900,14 +894,12 @@
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"adox eax, ebx": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": [
"0xf3 0x0f 0x38 0xf6"
],
@@ -924,14 +916,12 @@
"cset x21, ls",
"cmp x20, #0x1 (1)",
"csel x20, x21, x23, eq",
"mov w0, w22",
"bfi w0, w20, #28, #1",
"mov w20, w0",
"msr nzcv, x20"
"bfi w22, w20, #28, #1",
"msr nzcv, x22"
]
},
"adox rax, rbx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": [
"0xf3 REX.W 0x0f 0x38 0xf6"
],
@@ -946,10 +936,8 @@
"cset x23, ls",
"cmp x20, #0x1 (1)",
"csel x20, x23, x22, eq",
"mov w0, w21",
"bfi w0, w20, #28, #1",
"mov w20, w0",
"msr nzcv, x20"
"bfi w21, w20, #28, #1",
"msr nzcv, x21"
]
}
}
unittests/InstructionCountCI/Primary.json
+9 -11
View File
@@ -2652,7 +2652,7 @@
]
},
"sahf": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "0x9e",
"ExpectedArm64ASM": [
"ubfx w20, w4, #8, #8",
@@ -2661,16 +2661,14 @@
"orr x27, x20, #0x2",
"ubfx x20, x27, #0, #1",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"ubfx w21, w27, #2, #1",
"eor w26, w21, #0x1",
"ubfx x21, x27, #6, #1",
"bfi w20, w21, #30, #1",
"ubfx x21, x27, #7, #1",
"bfi w20, w21, #31, #1",
"msr nzcv, x20"
"bfi w21, w20, #29, #1",
"ubfx w20, w27, #2, #1",
"eor w26, w20, #0x1",
"ubfx x20, x27, #6, #1",
"bfi w21, w20, #30, #1",
"ubfx x20, x27, #7, #1",
"bfi w21, w20, #31, #1",
"msr nzcv, x21"
]
},
"lahf": {
unittests/InstructionCountCI/PrimaryGroup.json
+365 -483
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/Primary_32Bit.json
+6 -10
View File
@@ -199,18 +199,16 @@
]
},
"inc eax": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "0x40",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"bfi w21, w20, #29, #1",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x21"
]
},
"dec ax": {
@@ -244,18 +242,16 @@
]
},
"dec eax": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "0x48",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"bfi w21, w20, #29, #1",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x21"
]
},
"pusha": {
unittests/InstructionCountCI/VEX_map1.json
+7 -8
View File
@@ -5305,7 +5305,7 @@
]
},
"vpsadbw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 37,
"ExpectedInstructionCount": 36,
"Comment": [
"Map 1 0b01 0xf6 256-bit"
],
@@ -5330,18 +5330,17 @@
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.q, q2",
"mov z2.d, z4.d",
"not p0.b, p7/z, p6.b",
"mov z2.b, p0/m, z1.b",
"mov z1.d, z2.d[1]",
"mov z3.d, z2.d",
"mov z4.b, p0/m, z1.b",
"mov z1.d, z4.d[1]",
"mov z2.d, z4.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z3.d, p0/m, z1.d",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z2.d[2]",
"mov z16.d, z3.d",
"mov z1.d, z4.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",