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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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Alyssa Rosenzweig committed 2024-06-26 14:49:58 -04:00
1 parent a5b24bfe4c
commit 1b496cda8f
23 files changed
+2904 -2953
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unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
+2 -1
View File
@@ -1045,10 +1045,11 @@
"mov rax, gs:0x100",
"mov rbx, gs:0x14"
],
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"ldr x20, [x28, #960]",
"ldr x4, [x20, #256]",
"ldr x20, [x28, #960]",
"ldur x7, [x20, #20]"
]
}
unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
+2 -1
View File
@@ -323,10 +323,11 @@
"mov eax, gs:0x100",
"mov ebx, gs:0x14"
],
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"ExpectedArm64ASM": [
"ldr w20, [x28, #960]",
"ldr w4, [x20, #256]",
"ldr w20, [x28, #960]",
"ldr w7, [x20, #20]"
]
}
unittests/InstructionCountCI/FEXOpt/MultiInst.json
+103 -104
View File
@@ -69,11 +69,11 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"strb w20, [x28, #986]",
"ldrb w20, [x10]",
"strb w20, [x11]",
"ldrb w21, [x10]",
"strb w21, [x11]",
"add x10, x10, #0x1 (1)",
"add x11, x11, #0x1 (1)"
"add x11, x11, #0x1 (1)",
"strb w20, [x28, #986]"
]
},
"positive movsw": {
@@ -88,11 +88,11 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"strb w20, [x28, #986]",
"ldrh w20, [x10]",
"strh w20, [x11]",
"ldrh w21, [x10]",
"strh w21, [x11]",
"add x10, x10, #0x2 (2)",
"add x11, x11, #0x2 (2)"
"add x11, x11, #0x2 (2)",
"strb w20, [x28, #986]"
]
},
"positive movsd": {
@@ -107,11 +107,11 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"strb w20, [x28, #986]",
"ldr w20, [x10]",
"str w20, [x11]",
"ldr w21, [x10]",
"str w21, [x11]",
"add x10, x10, #0x4 (4)",
"add x11, x11, #0x4 (4)"
"add x11, x11, #0x4 (4)",
"strb w20, [x28, #986]"
]
},
"positive movsq": {
@@ -126,11 +126,11 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"strb w20, [x28, #986]",
"ldr x20, [x10]",
"str x20, [x11]",
"ldr x21, [x10]",
"str x21, [x11]",
"add x10, x10, #0x8 (8)",
"add x11, x11, #0x8 (8)"
"add x11, x11, #0x8 (8)",
"strb w20, [x28, #986]"
]
},
"negative movsb": {
@@ -145,11 +145,11 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"ldrb w20, [x10]",
"strb w20, [x11]",
"ldrb w21, [x10]",
"strb w21, [x11]",
"sub x10, x10, #0x1 (1)",
"sub x11, x11, #0x1 (1)"
"sub x11, x11, #0x1 (1)",
"strb w20, [x28, #986]"
]
},
"negative movsw": {
@@ -164,11 +164,11 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"ldrh w20, [x10]",
"strh w20, [x11]",
"ldrh w21, [x10]",
"strh w21, [x11]",
"sub x10, x10, #0x2 (2)",
"sub x11, x11, #0x2 (2)"
"sub x11, x11, #0x2 (2)",
"strb w20, [x28, #986]"
]
},
"negative movsd": {
@@ -183,11 +183,11 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"ldr w20, [x10]",
"str w20, [x11]",
"ldr w21, [x10]",
"str w21, [x11]",
"sub x10, x10, #0x4 (4)",
"sub x11, x11, #0x4 (4)"
"sub x11, x11, #0x4 (4)",
"strb w20, [x28, #986]"
]
},
"negative movsq": {
@@ -202,11 +202,11 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"ldr x20, [x10]",
"str x20, [x11]",
"ldr x21, [x10]",
"str x21, [x11]",
"sub x10, x10, #0x8 (8)",
"sub x11, x11, #0x8 (8)"
"sub x11, x11, #0x8 (8)",
"strb w20, [x28, #986]"
]
},
"positive rep movsb": {
@@ -222,7 +222,6 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -263,6 +262,7 @@
"add x23, x1, x2",
"mov x10, x23",
"mov x11, x22",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -279,7 +279,6 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -320,6 +319,7 @@
"add x23, x1, x2, lsl #1",
"mov x10, x23",
"mov x11, x22",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -336,7 +336,6 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -377,6 +376,7 @@
"add x23, x1, x2, lsl #2",
"mov x10, x23",
"mov x11, x22",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -393,7 +393,6 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -434,6 +433,7 @@
"add x23, x1, x2, lsl #3",
"mov x10, x23",
"mov x11, x22",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -449,7 +449,6 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -490,11 +489,12 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"sub x20, x0, x2",
"sub x21, x1, x2",
"mov x10, x21",
"mov x11, x20",
"mov w5, #0x0"
"sub x22, x0, x2",
"sub x23, x1, x2",
"mov x10, x23",
"mov x11, x22",
"mov w5, #0x0",
"strb w20, [x28, #986]"
]
},
"negative rep movsw": {
@@ -509,7 +509,6 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -550,11 +549,12 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"sub x20, x0, x2, lsl #1",
"sub x21, x1, x2, lsl #1",
"mov x10, x21",
"mov x11, x20",
"mov w5, #0x0"
"sub x22, x0, x2, lsl #1",
"sub x23, x1, x2, lsl #1",
"mov x10, x23",
"mov x11, x22",
"mov w5, #0x0",
"strb w20, [x28, #986]"
]
},
"negative rep movsd": {
@@ -569,7 +569,6 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -610,11 +609,12 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"sub x20, x0, x2, lsl #2",
"sub x21, x1, x2, lsl #2",
"mov x10, x21",
"mov x11, x20",
"mov w5, #0x0"
"sub x22, x0, x2, lsl #2",
"sub x23, x1, x2, lsl #2",
"mov x10, x23",
"mov x11, x22",
"mov w5, #0x0",
"strb w20, [x28, #986]"
]
},
"negative rep movsq": {
@@ -629,7 +629,6 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -670,11 +669,12 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"sub x20, x0, x2, lsl #3",
"sub x21, x1, x2, lsl #3",
"mov x10, x21",
"mov x11, x20",
"mov w5, #0x0"
"sub x22, x0, x2, lsl #3",
"sub x23, x1, x2, lsl #3",
"mov x10, x23",
"mov x11, x22",
"mov w5, #0x0",
"strb w20, [x28, #986]"
]
},
"positive rep stosb": {
@@ -690,14 +690,13 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"uxtb w21, w4",
"uxtb w22, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x20 (32)",
"tbnz x0, #63, #+0x3c",
"dup v1.16b, w21",
"dup v1.16b, w22",
"sub x0, x0, #0x20 (32)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #32",
@@ -713,10 +712,11 @@
"tbz x0, #63, #-0x8",
"add x0, x0, #0x20 (32)",
"cbz x0, #+0x10",
"strb w21, [x1], #1",
"strb w22, [x1], #1",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -733,14 +733,13 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"uxth w21, w4",
"uxth w22, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x10 (16)",
"tbnz x0, #63, #+0x3c",
"dup v1.8h, w21",
"dup v1.8h, w22",
"sub x0, x0, #0x10 (16)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #32",
@@ -756,10 +755,11 @@
"tbz x0, #63, #-0x8",
"add x0, x0, #0x10 (16)",
"cbz x0, #+0x10",
"strh w21, [x1], #2",
"strh w22, [x1], #2",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5, lsl #1",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -776,14 +776,13 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov w21, w4",
"mov w22, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x8 (8)",
"tbnz x0, #63, #+0x3c",
"dup v1.4s, w21",
"dup v1.4s, w22",
"sub x0, x0, #0x8 (8)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #32",
@@ -799,10 +798,11 @@
"tbz x0, #63, #-0x8",
"add x0, x0, #0x8 (8)",
"cbz x0, #+0x10",
"str w21, [x1], #4",
"str w22, [x1], #4",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5, lsl #2",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -819,7 +819,6 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x58",
@@ -845,6 +844,7 @@
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5, lsl #3",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -860,15 +860,14 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"uxtb w20, w4",
"uxtb w21, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x60",
"sub x1, x1, #0x1f (31)",
"sub x0, x0, #0x20 (32)",
"tbnz x0, #63, #+0x3c",
"dup v1.16b, w20",
"dup v1.16b, w21",
"sub x0, x0, #0x20 (32)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #-32",
@@ -885,11 +884,12 @@
"add x0, x0, #0x20 (32)",
"cbz x0, #+0x14",
"add x1, x1, #0x1f (31)",
"strb w20, [x1], #-1",
"strb w21, [x1], #-1",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5",
"mov w5, #0x0"
"mov w5, #0x0",
"strb w20, [x28, #986]"
]
},
"negative rep stosw": {
@@ -904,15 +904,14 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"uxth w20, w4",
"uxth w21, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x60",
"sub x1, x1, #0x1e (30)",
"sub x0, x0, #0x10 (16)",
"tbnz x0, #63, #+0x3c",
"dup v1.8h, w20",
"dup v1.8h, w21",
"sub x0, x0, #0x10 (16)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #-32",
@@ -929,11 +928,12 @@
"add x0, x0, #0x10 (16)",
"cbz x0, #+0x14",
"add x1, x1, #0x1e (30)",
"strh w20, [x1], #-2",
"strh w21, [x1], #-2",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5, lsl #1",
"mov w5, #0x0"
"mov w5, #0x0",
"strb w20, [x28, #986]"
]
},
"negative rep stosd": {
@@ -948,15 +948,14 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov w20, w4",
"mov w21, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x60",
"sub x1, x1, #0x1c (28)",
"sub x0, x0, #0x8 (8)",
"tbnz x0, #63, #+0x3c",
"dup v1.4s, w20",
"dup v1.4s, w21",
"sub x0, x0, #0x8 (8)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #-32",
@@ -973,11 +972,12 @@
"add x0, x0, #0x8 (8)",
"cbz x0, #+0x14",
"add x1, x1, #0x1c (28)",
"str w20, [x1], #-4",
"str w21, [x1], #-4",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5, lsl #2",
"mov w5, #0x0"
"mov w5, #0x0",
"strb w20, [x28, #986]"
]
},
"negative rep stosq": {
@@ -992,7 +992,6 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x60",
@@ -1020,11 +1019,12 @@
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5, lsl #3",
"mov w5, #0x0"
"mov w5, #0x0",
"strb w20, [x28, #986]"
]
},
"Sekiro spill block": {
"ExpectedInstructionCount": 148,
"ExpectedInstructionCount": 147,
"Comment": [
"This block of code came from the settings screen when it loaded",
"It was originally at RIP: 0x14232cca0 and has been deobfuscated"
@@ -1173,7 +1173,8 @@
"ldr w11, [x6, #32]",
"mov w20, #0x13",
"mul w4, w5, w20",
"str w5, [x8, #104]",
"mov w21, w5",
"str w21, [x8, #104]",
"mov w21, #0x1000000",
"add w4, w4, w21",
"lsr w4, w4, #25",
@@ -1258,33 +1259,31 @@
"sub w17, w17, w14",
"mov w20, w17",
"str w20, [x4, #20]",
"ldr w20, [x8, #112]",
"mov x21, x4",
"mov x4, x20",
"ldr w4, [x8, #112]",
"lsl w15, w15, #26",
"sub w4, w20, w15",
"sub w4, w4, w15",
"lsl w7, w7, #25",
"mov w20, w4",
"str w20, [x21, #24]",
"str w20, [x10, #24]",
"ldr w4, [x8, #120]",
"sub w4, w4, w7",
"lsl w11, w11, #26",
"mov w20, w4",
"str w20, [x21, #28]",
"str w20, [x10, #28]",
"ldr w4, [x8]",
"sub w4, w4, w11",
"mov w20, w4",
"str w20, [x21, #32]",
"mov x4, x5",
"and w4, w5, #0xfe000000",
"str w20, [x10, #32]",
"mov w4, w5",
"and w4, w4, #0xfe000000",
"sub w5, w5, w4",
"mov w20, w5",
"str w20, [x21, #36]",
"str w20, [x10, #36]",
"mvn w27, w8",
"adds x26, x8, #0x18 (24)",
"mov x8, x26",
"ldr x29, [x26]",
"add x8, x26, #0x8 (8)",
"ldr x29, [x8]",
"add x8, x8, #0x8 (8)",
"ldr x19, [x8]",
"add x8, x8, #0x8 (8)",
"ldr x17, [x8]",
unittests/InstructionCountCI/FEXOpt/libnss.json
+34 -35
View File
@@ -16,7 +16,7 @@
"Comment": [],
"Instructions": {
"libnss3 sha": {
"ExpectedInstructionCount": 2367,
"ExpectedInstructionCount": 2366,
"Comment": [
"This block of code comes from libnss3 which causes panic spilling in FEX's RA.",
"This code is hit in steamwebhelper calling in to this function.",
@@ -206,7 +206,7 @@
"ldr q22, [x11, #32]",
"ldr q21, [x11, #48]",
"mov v19.16b, v16.16b",
"ext v19.16b, v18.16b, v16.16b, #8",
"ext v19.16b, v18.16b, v19.16b, #8",
"mov v18.d[1], v16.d[1]",
"mov w20, #0x1000",
"movk w20, #0x1, lsl #16",
@@ -230,7 +230,7 @@
"unimplemented (Unimplemented)",
"mov w21, v19.s[1]",
"mov w22, v19.s[0]",
"mov w23, v18.s[1]",
"mov w23, v20.s[1]",
"and w24, w21, w22",
"bic w23, w23, w21",
"eor w23, w24, w23",
@@ -240,11 +240,11 @@
"add w23, w23, w24",
"mov w24, v16.s[0]",
"add w23, w23, w24",
"mov w24, v18.s[0]",
"mov w24, v20.s[0]",
"add w23, w23, w24",
"mov w24, v19.s[3]",
"mov w25, v19.s[2]",
"mov w30, v18.s[3]",
"mov w30, v20.s[3]",
"and w18, w25, w30",
"orr w30, w25, w30",
"and w30, w24, w30",
@@ -254,7 +254,7 @@
"eor w18, w18, w24, ror #13",
"eor w18, w18, w24, ror #22",
"add w30, w30, w18",
"mov w18, v18.s[2]",
"mov w18, v20.s[2]",
"add w23, w23, w18",
"and w21, w23, w21",
"bic w22, w22, w23",
@@ -265,7 +265,7 @@
"add w21, w21, w22",
"mov w22, v16.s[1]",
"add w21, w21, w22",
"mov w22, v18.s[1]",
"mov w22, v20.s[1]",
"add w21, w21, w22",
"and w22, w24, w25",
"orr w24, w24, w25",
@@ -276,9 +276,9 @@
"eor w24, w24, w30, ror #13",
"eor w24, w24, w30, ror #22",
"add w22, w22, w24",
"mov w24, v18.s[3]",
"mov w24, v20.s[3]",
"add w21, w21, w24",
"mov v4.16b, v18.16b",
"mov v4.16b, v20.16b",
"mov v4.s[3], w22",
"mov v4.s[2], w30",
"mov v4.s[1], w21",
@@ -289,7 +289,7 @@
"tbl v16.16b, {v16.16b}, v4.16b",
"mov w21, v20.s[1]",
"mov w22, v20.s[0]",
"mov w23, v19.s[1]",
"mov w23, v17.s[1]",
"and w24, w21, w22",
"bic w23, w23, w21",
"eor w23, w24, w23",
@@ -299,11 +299,11 @@
"add w23, w23, w24",
"mov w24, v16.s[0]",
"add w23, w23, w24",
"mov w24, v19.s[0]",
"mov w24, v17.s[0]",
"add w23, w23, w24",
"mov w24, v20.s[3]",
"mov w25, v20.s[2]",
"mov w30, v19.s[3]",
"mov w30, v17.s[3]",
"and w18, w25, w30",
"orr w30, w25, w30",
"and w30, w24, w30",
@@ -313,7 +313,7 @@
"eor w18, w18, w24, ror #13",
"eor w18, w18, w24, ror #22",
"add w30, w30, w18",
"mov w18, v19.s[2]",
"mov w18, v17.s[2]",
"add w23, w23, w18",
"and w21, w23, w21",
"bic w22, w22, w23",
@@ -324,7 +324,7 @@
"add w21, w21, w22",
"mov w22, v16.s[1]",
"add w21, w21, w22",
"mov w22, v19.s[1]",
"mov w22, v17.s[1]",
"add w21, w21, w22",
"and w22, w24, w25",
"orr w24, w24, w25",
@@ -335,16 +335,16 @@
"eor w24, w24, w30, ror #13",
"eor w24, w24, w30, ror #22",
"add w22, w22, w24",
"mov w24, v19.s[3]",
"mov w24, v17.s[3]",
"add w21, w21, w24",
"mov v5.16b, v19.16b",
"mov v5.16b, v17.16b",
"mov v5.s[3], w22",
"mov v5.s[2], w30",
"mov v5.s[1], w21",
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v21.16b",
"ext v16.16b, v22.16b, v21.16b, #4",
"ext v16.16b, v22.16b, v16.16b, #4",
"add v24.4s, v24.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v21.s[2]",
@@ -499,7 +499,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v24.16b",
"ext v16.16b, v21.16b, v24.16b, #4",
"ext v16.16b, v21.16b, v16.16b, #4",
"add v23.4s, v23.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v24.s[2]",
@@ -654,7 +654,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v23.16b",
"ext v16.16b, v24.16b, v23.16b, #4",
"ext v16.16b, v24.16b, v16.16b, #4",
"add v22.4s, v22.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v23.s[2]",
@@ -809,7 +809,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v22.16b",
"ext v16.16b, v23.16b, v22.16b, #4",
"ext v16.16b, v23.16b, v16.16b, #4",
"add v21.4s, v21.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v22.s[2]",
@@ -964,7 +964,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v21.16b",
"ext v16.16b, v22.16b, v21.16b, #4",
"ext v16.16b, v22.16b, v16.16b, #4",
"add v24.4s, v24.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v21.s[2]",
@@ -1119,7 +1119,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v24.16b",
"ext v16.16b, v21.16b, v24.16b, #4",
"ext v16.16b, v21.16b, v16.16b, #4",
"add v23.4s, v23.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v24.s[2]",
@@ -1274,7 +1274,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v23.16b",
"ext v16.16b, v24.16b, v23.16b, #4",
"ext v16.16b, v24.16b, v16.16b, #4",
"add v22.4s, v22.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v23.s[2]",
@@ -1429,7 +1429,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v22.16b",
"ext v16.16b, v23.16b, v22.16b, #4",
"ext v16.16b, v23.16b, v16.16b, #4",
"add v21.4s, v21.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v22.s[2]",
@@ -1584,7 +1584,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v21.16b",
"ext v16.16b, v22.16b, v21.16b, #4",
"ext v16.16b, v22.16b, v16.16b, #4",
"add v24.4s, v24.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v21.s[2]",
@@ -1739,7 +1739,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v24.16b",
"ext v16.16b, v21.16b, v24.16b, #4",
"ext v16.16b, v21.16b, v16.16b, #4",
"add v23.4s, v23.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v24.s[2]",
@@ -1894,7 +1894,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v23.16b",
"ext v16.16b, v24.16b, v23.16b, #4",
"ext v16.16b, v24.16b, v16.16b, #4",
"add v22.4s, v22.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v23.s[2]",
@@ -2049,7 +2049,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v22.16b",
"ext v16.16b, v23.16b, v22.16b, #4",
"ext v16.16b, v23.16b, v16.16b, #4",
"ldr q5, [x29, x20, sxtx]",
"add v23.4s, v23.4s, v5.4s",
"add v21.4s, v21.4s, v16.4s",
@@ -2219,7 +2219,7 @@
"eor w23, w23, w20, ror #11",
"eor w23, w23, w20, ror #25",
"add w22, w22, w23",
"mov w23, v23.s[0]",
"mov w23, v16.s[0]",
"add w22, w22, w23",
"mov w23, v20.s[0]",
"add w22, w22, w23",
@@ -2244,7 +2244,7 @@
"eor w21, w21, w22, ror #11",
"eor w21, w21, w22, ror #25",
"add w20, w20, w21",
"mov w21, v23.s[1]",
"mov w21, v16.s[1]",
"add w20, w20, w21",
"mov w21, v20.s[1]",
"add w20, w20, w21",
@@ -2333,7 +2333,7 @@
"eor w23, w23, w20, ror #11",
"eor w23, w23, w20, ror #25",
"add w22, w22, w23",
"mov w23, v22.s[0]",
"mov w23, v16.s[0]",
"add w22, w22, w23",
"mov w23, v20.s[0]",
"add w22, w22, w23",
@@ -2358,7 +2358,7 @@
"eor w21, w21, w22, ror #11",
"eor w21, w21, w22, ror #25",
"add w20, w20, w21",
"mov w21, v22.s[1]",
"mov w21, v16.s[1]",
"add w20, w20, w21",
"mov w21, v20.s[1]",
"add w20, w20, w21",
@@ -2447,7 +2447,7 @@
"eor w23, w23, w20, ror #11",
"eor w23, w23, w20, ror #25",
"add w22, w22, w23",
"mov w23, v21.s[0]",
"mov w23, v16.s[0]",
"add w22, w22, w23",
"mov w23, v20.s[0]",
"add w22, w22, w23",
@@ -2472,7 +2472,7 @@
"eor w21, w21, w22, ror #11",
"eor w21, w21, w22, ror #25",
"add w20, w20, w21",
"mov w21, v21.s[1]",
"mov w21, v16.s[1]",
"add w20, w20, w21",
"mov w21, v20.s[1]",
"add w20, w20, w21",
@@ -2555,7 +2555,6 @@
"tbl v20.16b, {v20.16b}, v2.16b",
"tbl v17.16b, {v17.16b}, v3.16b",
"mov v16.16b, v17.16b",
"mov v16.16b, v17.16b",
"mov v16.d[1], v20.d[1]",
"ext v20.16b, v17.16b, v20.16b, #8",
"str q16, [x11, #256]",
unittests/InstructionCountCI/FlagM/FlagOpts.json
+6 -5
View File
@@ -95,9 +95,9 @@
"ExpectedArm64ASM": [
"adds x4, x4, x7",
"cset w20, hs",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -124,9 +124,9 @@
"subs x4, x4, x7",
"cfinv",
"cset w20, hs",
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -263,15 +263,16 @@
]
},
"AND use only PF": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 9,
"x86Insts": [
"and eax, ebx",
"setp cl",
"test cl, cl"
],
"ExpectedArm64ASM": [
"and w4, w4, w7",
"eor w20, w4, w4, lsr #4",
"and w26, w4, w7",
"mov x4, x26",
"eor w20, w26, w26, lsr #4",
"eor w20, w20, w20, lsr #2",
"eon w20, w20, w20, lsr #1",
"and x20, x20, #0x1",
unittests/InstructionCountCI/FlagM/HotBlocks.json
+16 -18
View File
@@ -27,7 +27,7 @@
"mov w4, #0x1",
"ldaddal x4, x4, [x5]",
"mov x6, x4",
"and w6, w4, #0x1f",
"and w6, w6, #0x1f",
"add x6, x6, #0x1 (1)",
"lsl x6, x6, #6",
"eor w27, w6, w5",
@@ -81,11 +81,11 @@
"mov w10, w5",
"mov x6, x9",
"mov x4, x7",
"ldr s18, [x9]",
"add x4, x7, #0x20 (32)",
"ldr s18, [x6]",
"add x4, x4, #0x20 (32)",
"fmul s0, s18, s16",
"mov v18.s[0], v0.s[0]",
"add x6, x9, #0x20 (32)",
"add x6, x6, #0x20 (32)",
"ldur s2, [x4, #-32]",
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
@@ -139,9 +139,9 @@
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
"stur s18, [x4, #-4]",
"mov x27, x10",
"subs w26, w10, #0x1 (1)",
"cfinv",
"mov x27, x10",
"mov x10, x26"
]
},
@@ -168,7 +168,7 @@
]
},
"bytemark data xor loop": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": [
"Saw this in bytemark"
],
@@ -187,17 +187,15 @@
"mov x6, x4",
"mov x5, x4",
"mov x19, x10",
"add x20, x4, #0x1 (1)",
"mov x21, x4",
"mov x4, x20",
"lsr x6, x21, #6",
"and w5, w21, #0x3f",
"lsl x19, x10, x5",
"ldr x21, [x7, x6, sxtx #3]",
"eor x21, x21, x19",
"str x21, [x7, x6, sxtx #3]",
"eor w27, w11, w20",
"subs x26, x11, x20",
"add x4, x4, #0x1 (1)",
"lsr x6, x6, #6",
"and w5, w5, #0x3f",
"lsl x19, x19, x5",
"ldr x20, [x7, x6, sxtx #3]",
"eor x20, x20, x19",
"str x20, [x7, x6, sxtx #3]",
"eor w27, w11, w4",
"subs x26, x11, x4",
"cfinv"
]
},
@@ -215,7 +213,7 @@
"ExpectedArm64ASM": [
"ldr x17, [x10, x13, sxtx #3]",
"mov x15, x13",
"orr x15, x13, #0x1",
"orr x15, x15, #0x1",
"ldr x20, [x10, x15, sxtx #3]",
"eor w27, w17, w20",
"subs x26, x17, x20",
unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
+346 -415
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
+4 -4
View File
@@ -58,10 +58,10 @@
"mov w10, w5",
"mov x6, x9",
"mov x4, x7",
"ldr s18, [x9]",
"add x4, x7, #0x20 (32)",
"ldr s18, [x6]",
"add x4, x4, #0x20 (32)",
"fmul s18, s18, s16",
"add x6, x9, #0x20 (32)",
"add x6, x6, #0x20 (32)",
"ldur s2, [x4, #-32]",
"fadd s18, s18, s2",
"stur s18, [x4, #-32]",
@@ -100,9 +100,9 @@
"ldur s2, [x4, #-4]",
"fadd s18, s18, s2",
"stur s18, [x4, #-4]",
"mov x27, x10",
"subs w26, w10, #0x1 (1)",
"cfinv",
"mov x27, x10",
"mov x10, x26"
]
}
unittests/InstructionCountCI/FlagM/Primary.json
+165 -157
View File
@@ -105,35 +105,39 @@
]
},
"add al, 1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "0x04",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmn w0, w20, lsl #24",
"add w26, w4, #0x1 (1)",
"bfxil x4, x26, #0, #8"
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
]
},
"add ax, 1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "0x05",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x1 (1)",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"add eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x05",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -141,8 +145,8 @@
"ExpectedInstructionCount": 3,
"Comment": "0x05",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -221,18 +225,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr w7, w7, w5",
"mov x26, x7",
"tst w7, w7"
"orr w26, w7, w5",
"tst w26, w26",
"mov x7, x26"
]
},
"or rbx, rcx": {
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr x7, x7, x5",
"mov x26, x7",
"tst x7, x7"
"orr x26, x7, x5",
"tst x26, x26",
"mov x7, x26"
]
},
"db 0x0A, 0xcb": {
@@ -266,9 +270,9 @@
"or ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr w5, w5, w7",
"mov x26, x5",
"tst w5, w5"
"orr w26, w5, w7",
"tst w26, w26",
"mov x5, x26"
]
},
"db 0x48, 0x0B, 0xcb": {
@@ -278,9 +282,9 @@
"or rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr x5, x5, x7",
"mov x26, x5",
"tst x5, x5"
"orr x26, x5, x7",
"tst x26, x26",
"mov x5, x26"
]
},
"or al, 1": {
@@ -305,18 +309,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
]
},
"or al, -1": {
@@ -342,9 +346,9 @@
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, -1": {
@@ -352,9 +356,9 @@
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
]
},
"adc bl, cl": {
@@ -486,10 +490,9 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 16,
"Comment": "0x14",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -502,14 +505,16 @@
"eor w21, w26, w4",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
]
},
"adc ax, 1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 16,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -522,7 +527,10 @@
"eor w21, w26, w4",
"bic w20, w21, w20",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"adc eax, 1": {
@@ -530,8 +538,8 @@
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -540,8 +548,8 @@
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -746,10 +754,9 @@
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 15,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxtb w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -761,14 +768,16 @@
"rmif x21, #63, #nzCv",
"bic w20, w20, w26",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
]
},
"sbb ax, 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 15,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxth w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -780,7 +789,10 @@
"rmif x21, #63, #nzCv",
"bic w20, w20, w26",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"sbb eax, 1": {
@@ -788,10 +800,10 @@
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -800,10 +812,10 @@
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -1121,38 +1133,42 @@
]
},
"sub al, 1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 9,
"Comment": "0x2C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"cfinv",
"bfxil x4, x26, #0, #8"
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
]
},
"sub ax, 1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 9,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmp w0, w20, lsl #16",
"sub w26, w4, #0x1 (1)",
"cfinv",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"sub eax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -1160,9 +1176,9 @@
"ExpectedInstructionCount": 4,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -1235,18 +1251,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor w7, w7, w5",
"mov x26, x7",
"tst w7, w7"
"eor w26, w7, w5",
"tst w26, w26",
"mov x7, x26"
]
},
"xor rbx, rcx": {
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor x7, x7, x5",
"mov x26, x7",
"tst x7, x7"
"eor x26, x7, x5",
"tst x26, x26",
"mov x7, x26"
]
},
"db 0x32, 0xcb": {
@@ -1280,9 +1296,9 @@
"xor ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor w5, w5, w7",
"mov x26, x5",
"tst w5, w5"
"eor w26, w5, w7",
"tst w26, w26",
"mov x5, x26"
]
},
"db 0x48, 0x33, 0xcb": {
@@ -1292,9 +1308,9 @@
"xor rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor x5, x5, x7",
"mov x26, x5",
"tst x5, x5"
"eor x26, x5, x7",
"tst x26, x26",
"mov x5, x26"
]
},
"xor al, 1": {
@@ -1319,18 +1335,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp bl, cl": {
@@ -1367,9 +1383,9 @@
"Comment": "0x35",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"eor w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, -1": {
@@ -1377,9 +1393,9 @@
"Comment": "0x35",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"eor x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp bx, cx": {
@@ -1468,11 +1484,11 @@
"Comment": "0x3C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"cmp ax, 1": {
@@ -1480,29 +1496,29 @@
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmp w0, w20, lsl #16",
"sub w26, w4, #0x1 (1)",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"cmp eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"cmp rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"cmp al, -1": {
@@ -1766,24 +1782,24 @@
"strb w20, [x28, #985]",
"ubfx w20, w27, #10, #1",
"sub x20, x21, x20, lsl #1",
"strb w20, [x28, #986]",
"rmif x27, #11, #nzcV",
"ubfx w20, w27, #12, #1",
"strb w20, [x28, #988]",
"ubfx w20, w27, #14, #1",
"strb w20, [x28, #990]",
"ubfx w20, w27, #16, #1",
"strb w20, [x28, #992]",
"ubfx w20, w27, #17, #1",
"strb w20, [x28, #993]",
"ubfx w20, w27, #18, #1",
"strb w20, [x28, #994]",
"ubfx w20, w27, #19, #1",
"strb w20, [x28, #995]",
"ubfx w20, w27, #20, #1",
"strb w20, [x28, #996]",
"ubfx w20, w27, #21, #1",
"strb w20, [x28, #997]"
"ubfx w21, w27, #12, #1",
"strb w21, [x28, #988]",
"ubfx w21, w27, #14, #1",
"strb w21, [x28, #990]",
"ubfx w21, w27, #16, #1",
"strb w21, [x28, #992]",
"ubfx w21, w27, #17, #1",
"strb w21, [x28, #993]",
"ubfx w21, w27, #18, #1",
"strb w21, [x28, #994]",
"ubfx w21, w27, #19, #1",
"strb w21, [x28, #995]",
"ubfx w21, w27, #20, #1",
"strb w21, [x28, #996]",
"ubfx w21, w27, #21, #1",
"strb w21, [x28, #997]",
"strb w20, [x28, #986]"
]
},
"sahf": {
@@ -1893,10 +1909,10 @@
]
},
"repz cmpsb": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 26,
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"cbz x5, #+0x68",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -1917,19 +1933,18 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #24",
"lsl w0, w27, #24",
"cmp w0, w26, lsl #24",
"sub w26, w21, w26",
"cfinv"
"sub w26, w27, w26",
"cfinv",
"mov x27, x20"
]
},
"repz cmpsw": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 26,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"cbz x5, #+0x68",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -1950,19 +1965,18 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #16",
"lsl w0, w27, #16",
"cmp w0, w26, lsl #16",
"sub w26, w21, w26",
"cfinv"
"sub w26, w27, w26",
"cfinv",
"mov x27, x20"
]
},
"repz cmpsd": {
"ExpectedInstructionCount": 25,
"ExpectedInstructionCount": 24,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x64",
"cbz x5, #+0x60",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -1983,17 +1997,16 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"subs w26, w21, w26",
"cfinv"
"subs w26, w27, w26",
"cfinv",
"mov x27, x20"
]
},
"repz cmpsq": {
"ExpectedInstructionCount": 25,
"ExpectedInstructionCount": 24,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x64",
"cbz x5, #+0x60",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -2014,17 +2027,16 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"subs x26, x21, x26",
"cfinv"
"subs x26, x27, x26",
"cfinv",
"mov x27, x20"
]
},
"repnz cmpsb": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 26,
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"cbz x5, #+0x68",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -2045,19 +2057,18 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #24",
"lsl w0, w27, #24",
"cmp w0, w26, lsl #24",
"sub w26, w21, w26",
"cfinv"
"sub w26, w27, w26",
"cfinv",
"mov x27, x20"
]
},
"repnz cmpsw": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 26,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"cbz x5, #+0x68",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -2078,19 +2089,18 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #16",
"lsl w0, w27, #16",
"cmp w0, w26, lsl #16",
"sub w26, w21, w26",
"cfinv"
"sub w26, w27, w26",
"cfinv",
"mov x27, x20"
]
},
"repnz cmpsd": {
"ExpectedInstructionCount": 25,
"ExpectedInstructionCount": 24,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x64",
"cbz x5, #+0x60",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -2111,17 +2121,16 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"subs w26, w21, w26",
"cfinv"
"subs w26, w27, w26",
"cfinv",
"mov x27, x20"
]
},
"repnz cmpsq": {
"ExpectedInstructionCount": 25,
"ExpectedInstructionCount": 24,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x64",
"cbz x5, #+0x60",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -2142,10 +2151,9 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"subs x26, x21, x26",
"cfinv"
"subs x26, x27, x26",
"cfinv",
"mov x27, x20"
]
},
"test al, 1": {
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+139 -121
View File
@@ -13,15 +13,17 @@
},
"Instructions": {
"add al, 1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmn w0, w20, lsl #24",
"add w26, w4, #0x1 (1)",
"bfxil x4, x26, #0, #8"
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
]
},
"or al, 1": {
@@ -34,10 +36,9 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -50,14 +51,16 @@
"eor w21, w26, w4",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxtb w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -69,7 +72,10 @@
"rmif x21, #63, #nzCv",
"bic w20, w20, w26",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
]
},
"and al, 1": {
@@ -82,16 +88,18 @@
]
},
"sub al, 1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 9,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"cfinv",
"bfxil x4, x26, #0, #8"
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
]
},
"xor al, 1": {
@@ -108,11 +116,11 @@
"Comment": "GROUP1 0x80 /7",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"add al, -1": {
@@ -219,23 +227,25 @@
]
},
"add ax, 256": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x100 (256)",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"add eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds w26, w4, #0x100 (256)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -243,8 +253,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -252,18 +262,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w4, w4, #0x100",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, #0x100",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x4, x4, #0x100",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, #0x100",
"tst x26, x26",
"mov x4, x26"
]
},
"adc eax, 256": {
@@ -271,8 +281,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -281,8 +291,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -291,10 +301,10 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -303,10 +313,10 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -330,9 +340,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x100 (256)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -340,9 +350,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -350,48 +360,50 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w4, w4, #0x100",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, #0x100",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x4, x4, #0x100",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, #0x100",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x100 (256)",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"cmp rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"add ax, -256": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xff00",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, w20",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"add eax, -256": {
@@ -399,8 +411,8 @@
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"adds w26, w4, w20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -408,8 +420,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -417,18 +429,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w4, w4, #0xffffff00",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, #0xffffff00",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x4, x4, #0xffffffffffffff00",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, #0xffffffffffffff00",
"tst x26, x26",
"mov x4, x26"
]
},
"adc eax, -256": {
@@ -436,8 +448,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -446,8 +458,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -456,10 +468,10 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -468,10 +480,10 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -496,9 +508,9 @@
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"subs w26, w4, w20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -506,9 +518,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -516,18 +528,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w4, w4, #0xffffff00",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, #0xffffff00",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x4, x4, #0xffffffffffffff00",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, #0xffffffffffffff00",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp eax, -256": {
@@ -535,38 +547,40 @@
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"subs w26, w4, w20",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"cmp rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"add ax, 1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x1 (1)",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"add eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -574,8 +588,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -583,18 +597,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
]
},
"adc eax, 1": {
@@ -602,8 +616,8 @@
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -612,8 +626,8 @@
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -622,10 +636,10 @@
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -634,10 +648,10 @@
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -661,9 +675,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -671,9 +685,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -681,36 +695,36 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"cmp rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"cfinv"
"cfinv",
"mov x27, x4"
]
},
"add ax, -1": {
@@ -749,9 +763,9 @@
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, -1": {
@@ -759,9 +773,9 @@
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
]
},
"adc eax, -1": {
@@ -852,9 +866,9 @@
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"eor w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, -1": {
@@ -862,9 +876,9 @@
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"eor x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp eax, -1": {
@@ -2027,14 +2041,16 @@
]
},
"neg bl": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"mov x27, x7",
"cmp wzr, w7, lsl #24",
"neg w26, w7",
"cfinv",
"bfxil x7, x26, #0, #8"
"mov x20, x7",
"bfxil x20, x26, #0, #8",
"mov x27, x7",
"mov x7, x20"
]
},
"mul bl": {
@@ -2141,23 +2157,25 @@
]
},
"neg bx": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"cmp wzr, w7, lsl #16",
"neg w26, w7",
"cfinv",
"bfxil x7, x26, #0, #16"
"mov x20, x7",
"bfxil x20, x26, #0, #16",
"mov x27, x7",
"mov x7, x20"
]
},
"neg ebx": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"negs w26, w7",
"cfinv",
"mov x27, x7",
"mov x7, x26"
]
},
@@ -2165,9 +2183,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"negs x26, x7",
"cfinv",
"mov x27, x7",
"mov x7, x26"
]
},
@@ -2204,9 +2222,9 @@
"ExpectedArm64ASM": [
"mul x20, x7, x4",
"umulh x6, x7, x4",
"mov x4, x20",
"cmp x6, #0x0 (0)",
"ccmn xzr, #0, #nzCV, eq"
"ccmn xzr, #0, #nzCV, eq",
"mov x4, x20"
]
},
"imul bx": {
@@ -2310,9 +2328,9 @@
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -2321,9 +2339,9 @@
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -2344,9 +2362,9 @@
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -2355,9 +2373,9 @@
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
}
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+2 -2
View File
@@ -197,9 +197,9 @@
"Comment": "0x40",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -234,9 +234,9 @@
"Comment": "0x48",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
unittests/InstructionCountCI/FlagM/Secondary.json
+5 -3
View File
@@ -1059,13 +1059,15 @@
]
},
"cmpxchg rcx, rbx": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 7,
"ExpectedArm64ASM": [
"eor w27, w4, w5",
"subs x26, x4, x5",
"cfinv",
"mov x4, x5",
"csel x5, x7, x5, eq"
"csel x20, x7, x5, eq",
"mov x21, x5",
"mov x5, x20",
"mov x4, x21"
]
},
"cmpxchg [rax], rbx": {
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+78 -78
View File
@@ -1205,21 +1205,21 @@
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #1040]",
"ldr d2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr q2, [x28, #1056]",
"ldr d2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr q2, [x28, #1072]",
"ldr d2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr q2, [x28, #1088]",
"ldr d2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr q2, [x28, #1104]",
"ldr d2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr q2, [x28, #1120]",
"ldr d2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr q2, [x28, #1136]",
"ldr d2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr q2, [x28, #1152]",
"ldr d2, [x28, #1152]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
@@ -1280,23 +1280,14 @@
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1298]",
"ldr q2, [x4, #32]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #1152]",
"ldr q3, [x4, #48]",
"ldr q4, [x4, #64]",
"ldr q5, [x4, #80]",
"ldr q6, [x4, #96]",
"ldr q7, [x4, #112]",
"ldr q8, [x4, #128]",
"ldr q9, [x4, #144]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@@ -1313,15 +1304,24 @@
"ldr q29, [x4, #368]",
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"ldr w20, [x4, #24]",
"ubfx w20, w20, #13, #3",
"rbit w1, w20",
"ldr w21, [x4, #24]",
"ubfx w21, w21, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x20, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0"
"msr fpcr, x0",
"strb w20, [x28, #1298]",
"str d9, [x28, #1152]",
"str d8, [x28, #1136]",
"str d7, [x28, #1120]",
"str d6, [x28, #1104]",
"str d5, [x28, #1088]",
"str d4, [x28, #1072]",
"str d3, [x28, #1056]",
"str d2, [x28, #1040]"
]
},
"rdgsbase eax": {
@@ -1419,21 +1419,21 @@
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #1040]",
"ldr d2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr q2, [x28, #1056]",
"ldr d2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr q2, [x28, #1072]",
"ldr d2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr q2, [x28, #1088]",
"ldr d2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr q2, [x28, #1104]",
"ldr d2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr q2, [x28, #1120]",
"ldr d2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr q2, [x28, #1136]",
"ldr d2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr q2, [x28, #1152]",
"ldr d2, [x28, #1152]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
@@ -1499,23 +1499,23 @@
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1298]",
"ldr q2, [x4, #32]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #1152]",
"ldr q3, [x4, #48]",
"ldr q4, [x4, #64]",
"ldr q5, [x4, #80]",
"ldr q6, [x4, #96]",
"ldr q7, [x4, #112]",
"ldr q8, [x4, #128]",
"ldr q9, [x4, #144]",
"strb w20, [x28, #1298]",
"str d9, [x28, #1152]",
"str d8, [x28, #1136]",
"str d7, [x28, #1120]",
"str d6, [x28, #1104]",
"str d5, [x28, #1088]",
"str d4, [x28, #1072]",
"str d3, [x28, #1056]",
"str d2, [x28, #1040]",
"b #+0x4c",
"mov w20, #0x0",
"mov w21, #0x37f",
@@ -1525,16 +1525,16 @@
"strb w20, [x28, #1017]",
"strb w20, [x28, #1018]",
"strb w20, [x28, #1022]",
"strb w20, [x28, #1298]",
"movi v2.2d, #0x0",
"str q2, [x28, #1040]",
"str q2, [x28, #1056]",
"str q2, [x28, #1072]",
"str q2, [x28, #1088]",
"str q2, [x28, #1104]",
"str q2, [x28, #1120]",
"str q2, [x28, #1136]",
"str q2, [x28, #1152]",
"strb w20, [x28, #1298]",
"str d2, [x28, #1152]",
"str d2, [x28, #1136]",
"str d2, [x28, #1120]",
"str d2, [x28, #1104]",
"str d2, [x28, #1088]",
"str d2, [x28, #1072]",
"str d2, [x28, #1056]",
"str d2, [x28, #1040]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #1",
"cbnz x20, #+0x8",
@@ -1556,22 +1556,22 @@
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"b #+0x44",
"movi v16.2d, #0x0",
"mov v17.16b, v16.16b",
"mov v18.16b, v16.16b",
"mov v19.16b, v16.16b",
"mov v20.16b, v16.16b",
"mov v21.16b, v16.16b",
"mov v22.16b, v16.16b",
"mov v23.16b, v16.16b",
"mov v24.16b, v16.16b",
"mov v25.16b, v16.16b",
"mov v26.16b, v16.16b",
"mov v27.16b, v16.16b",
"mov v28.16b, v16.16b",
"mov v29.16b, v16.16b",
"mov v30.16b, v16.16b",
"mov v31.16b, v16.16b",
"movi v31.2d, #0x0",
"mov v30.16b, v31.16b",
"mov v29.16b, v31.16b",
"mov v28.16b, v31.16b",
"mov v27.16b, v31.16b",
"mov v26.16b, v31.16b",
"mov v25.16b, v31.16b",
"mov v24.16b, v31.16b",
"mov v23.16b, v31.16b",
"mov v22.16b, v31.16b",
"mov v21.16b, v31.16b",
"mov v20.16b, v31.16b",
"mov v19.16b, v31.16b",
"mov v18.16b, v31.16b",
"mov v17.16b, v31.16b",
"mov v16.16b, v31.16b",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #2",
"cbnz x20, #+0x8",
unittests/InstructionCountCI/FlagM/VEX_map2.json
+6 -6
View File
@@ -349,9 +349,9 @@
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w4, w5, w7",
"mov x26, x4",
"tst w4, w4"
"bic w26, w5, w7",
"tst w26, w26",
"mov x4, x26"
]
},
"andn rax, rbx, rcx": {
@@ -360,9 +360,9 @@
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x4, x5, x7",
"mov x26, x4",
"tst x4, x4"
"bic x26, x5, x7",
"tst x26, x26",
"mov x4, x26"
]
},
"bzhi eax, ebx, ecx": {
unittests/InstructionCountCI/FlagM/x87.json
+369 -375
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87_f64.json
+369 -377
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/Primary.json
+240 -237
View File
@@ -104,35 +104,39 @@
]
},
"add al, 1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "0x04",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmn w0, w20, lsl #24",
"add w26, w4, #0x1 (1)",
"bfxil x4, x26, #0, #8"
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
]
},
"add ax, 1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "0x05",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x1 (1)",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"add eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x05",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -140,8 +144,8 @@
"ExpectedInstructionCount": 3,
"Comment": "0x05",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -220,18 +224,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr w7, w7, w5",
"mov x26, x7",
"tst w7, w7"
"orr w26, w7, w5",
"tst w26, w26",
"mov x7, x26"
]
},
"or rbx, rcx": {
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr x7, x7, x5",
"mov x26, x7",
"tst x7, x7"
"orr x26, x7, x5",
"tst x26, x26",
"mov x7, x26"
]
},
"db 0x0A, 0xcb": {
@@ -265,9 +269,9 @@
"or ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr w5, w5, w7",
"mov x26, x5",
"tst w5, w5"
"orr w26, w5, w7",
"tst w26, w26",
"mov x5, x26"
]
},
"db 0x48, 0x0B, 0xcb": {
@@ -277,9 +281,9 @@
"or rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr x5, x5, x7",
"mov x26, x5",
"tst x5, x5"
"orr x26, x5, x7",
"tst x26, x26",
"mov x5, x26"
]
},
"or al, 1": {
@@ -304,18 +308,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
]
},
"or al, -1": {
@@ -341,9 +345,9 @@
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, -1": {
@@ -351,9 +355,9 @@
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
]
},
"adc bl, cl": {
@@ -497,10 +501,9 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 19,
"Comment": "0x14",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -515,15 +518,17 @@
"bic w21, w22, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
]
},
"adc ax, 1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 19,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -538,8 +543,11 @@
"bic w21, w22, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
"mov x21, x4",
"bfxil x21, x26, #0, #16",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
]
},
"adc eax, 1": {
@@ -547,8 +555,8 @@
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -557,8 +565,8 @@
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -687,8 +695,8 @@
"sbcs w26, w7, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x7, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x7, x26"
]
},
"sbb rbx, rcx": {
@@ -702,8 +710,8 @@
"sbcs x26, x7, x5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x7, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x7, x26"
]
},
"db 0x1A, 0xcb": {
@@ -774,8 +782,8 @@
"sbcs w26, w5, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x5, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x5, x26"
]
},
"db 0x48, 0x1B, 0xcb": {
@@ -792,15 +800,14 @@
"sbcs x26, x5, x7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x5, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x5, x26"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 18,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxtb w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -814,15 +821,17 @@
"bic w20, w20, w26",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
]
},
"sbb ax, 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 18,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxth w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -836,8 +845,11 @@
"bic w20, w20, w26",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
"mov x21, x4",
"bfxil x21, x26, #0, #16",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
]
},
"sbb eax, 1": {
@@ -845,15 +857,15 @@
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"sbb rax, 1": {
@@ -861,15 +873,15 @@
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"sbb al, -1": {
@@ -929,8 +941,8 @@
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x4, x26"
]
},
"sbb rax, -1": {
@@ -945,8 +957,8 @@
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x4, x26"
]
},
"and bl, cl": {
@@ -1135,8 +1147,8 @@
"subs w26, w7, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x7, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x7, x26"
]
},
"sub rbx, rcx": {
@@ -1147,8 +1159,8 @@
"subs x26, x7, x5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x7, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x7, x26"
]
},
"db 0x2A, 0xcb": {
@@ -1196,8 +1208,8 @@
"subs w26, w5, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x5, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x5, x26"
]
},
"db 0x48, 0x2B, 0xcb": {
@@ -1211,62 +1223,66 @@
"subs x26, x5, x7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x5, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x5, x26"
]
},
"sub al, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 11,
"Comment": "0x2C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
]
},
"sub ax, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 11,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmp w0, w20, lsl #16",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
"mov x21, x4",
"bfxil x21, x26, #0, #16",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
]
},
"sub eax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"sub rax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"sub al, -1": {
@@ -1308,8 +1324,8 @@
"subs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x4, x26"
]
},
"sub rax, -1": {
@@ -1320,8 +1336,8 @@
"adds x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x4, x26"
]
},
"xor bl, cl": {
@@ -1346,18 +1362,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor w7, w7, w5",
"mov x26, x7",
"tst w7, w7"
"eor w26, w7, w5",
"tst w26, w26",
"mov x7, x26"
]
},
"xor rbx, rcx": {
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor x7, x7, x5",
"mov x26, x7",
"tst x7, x7"
"eor x26, x7, x5",
"tst x26, x26",
"mov x7, x26"
]
},
"db 0x32, 0xcb": {
@@ -1391,9 +1407,9 @@
"xor ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor w5, w5, w7",
"mov x26, x5",
"tst w5, w5"
"eor w26, w5, w7",
"tst w26, w26",
"mov x5, x26"
]
},
"db 0x48, 0x33, 0xcb": {
@@ -1403,9 +1419,9 @@
"xor rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor x5, x5, x7",
"mov x26, x5",
"tst x5, x5"
"eor x26, x5, x7",
"tst x26, x26",
"mov x5, x26"
]
},
"xor al, 1": {
@@ -1430,18 +1446,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp bl, cl": {
@@ -1480,9 +1496,9 @@
"Comment": "0x35",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"eor w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, -1": {
@@ -1490,9 +1506,9 @@
"Comment": "0x35",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"eor x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp bx, cx": {
@@ -1595,13 +1611,13 @@
"Comment": "0x3C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"cmp ax, 1": {
@@ -1609,35 +1625,35 @@
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmp w0, w20, lsl #16",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"cmp eax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"cmp rax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"cmp al, -1": {
@@ -1908,14 +1924,13 @@
]
},
"xchg bl, cl": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "0x86",
"ExpectedArm64ASM": [
"mov x20, x5",
"bfxil x20, x7, #0, #8",
"mov x21, x5",
"mov x5, x20",
"bfxil x7, x21, #0, #8"
"bfxil x7, x5, #0, #8",
"mov x5, x20"
]
},
"xchg [rax], cl": {
@@ -1927,14 +1942,13 @@
]
},
"xchg bx, cx": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "0x87",
"ExpectedArm64ASM": [
"mov x20, x5",
"bfxil x20, x7, #0, #16",
"mov x21, x5",
"mov x5, x20",
"bfxil x7, x21, #0, #16"
"bfxil x7, x5, #0, #16",
"mov x5, x20"
]
},
"xchg [rax], cx": {
@@ -1946,13 +1960,12 @@
]
},
"xchg ebx, ecx": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "0x87",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov x21, x5",
"mov x5, x20",
"mov w7, w21"
"mov w7, w5",
"mov x5, x20"
]
},
"xchg [rax], ecx": {
@@ -1966,9 +1979,9 @@
"ExpectedInstructionCount": 3,
"Comment": "0x87",
"ExpectedArm64ASM": [
"mov x20, x5",
"mov x5, x7",
"mov x7, x20"
"mov x20, x7",
"mov x7, x5",
"mov x5, x20"
]
},
"xchg [rax], rcx": {
@@ -2431,24 +2444,22 @@
]
},
"xchg ax, bx": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "0x90",
"ExpectedArm64ASM": [
"mov x20, x7",
"bfxil x20, x4, #0, #16",
"mov x21, x7",
"mov x7, x20",
"bfxil x4, x21, #0, #16"
"bfxil x4, x7, #0, #16",
"mov x7, x20"
]
},
"xchg eax, ebx": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Comment": "0x90",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov x21, x7",
"mov x7, x20",
"mov w4, w21"
"mov w4, w7",
"mov x7, x20"
]
},
"xchg rax, rbx": {
@@ -2630,26 +2641,26 @@
"strb w21, [x28, #985]",
"ubfx w21, w27, #10, #1",
"sub x21, x22, x21, lsl #1",
"strb w21, [x28, #986]",
"ubfx x21, x27, #11, #1",
"orr w20, w20, w21, lsl #28",
"ubfx w21, w27, #12, #1",
"strb w21, [x28, #988]",
"ubfx w21, w27, #14, #1",
"strb w21, [x28, #990]",
"ubfx w21, w27, #16, #1",
"strb w21, [x28, #992]",
"ubfx w21, w27, #17, #1",
"strb w21, [x28, #993]",
"ubfx w21, w27, #18, #1",
"strb w21, [x28, #994]",
"ubfx w21, w27, #19, #1",
"strb w21, [x28, #995]",
"ubfx w21, w27, #20, #1",
"strb w21, [x28, #996]",
"ubfx w21, w27, #21, #1",
"strb w21, [x28, #997]",
"msr nzcv, x20"
"ubfx x22, x27, #11, #1",
"orr w20, w20, w22, lsl #28",
"ubfx w22, w27, #12, #1",
"strb w22, [x28, #988]",
"ubfx w22, w27, #14, #1",
"strb w22, [x28, #990]",
"ubfx w22, w27, #16, #1",
"strb w22, [x28, #992]",
"ubfx w22, w27, #17, #1",
"strb w22, [x28, #993]",
"ubfx w22, w27, #18, #1",
"strb w22, [x28, #994]",
"ubfx w22, w27, #19, #1",
"strb w22, [x28, #995]",
"ubfx w22, w27, #20, #1",
"strb w22, [x28, #996]",
"ubfx w22, w27, #21, #1",
"strb w22, [x28, #997]",
"msr nzcv, x20",
"strb w21, [x28, #986]"
]
},
"sahf": {
@@ -3236,10 +3247,10 @@
]
},
"repz cmpsb": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 28,
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x74",
"cbz x5, #+0x70",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3260,21 +3271,20 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #24",
"lsl w0, w27, #24",
"cmp w0, w26, lsl #24",
"sub w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"sub w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
]
},
"repz cmpsw": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 28,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x74",
"cbz x5, #+0x70",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3295,21 +3305,20 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #16",
"lsl w0, w27, #16",
"cmp w0, w26, lsl #16",
"sub w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"sub w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
]
},
"repz cmpsd": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 26,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"cbz x5, #+0x68",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3330,19 +3339,18 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"subs w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
]
},
"repz cmpsq": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 26,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"cbz x5, #+0x68",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3363,19 +3371,18 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"subs x26, x21, x26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs x26, x27, x26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
]
},
"repnz cmpsb": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 28,
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x74",
"cbz x5, #+0x70",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3396,21 +3403,20 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #24",
"lsl w0, w27, #24",
"cmp w0, w26, lsl #24",
"sub w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"sub w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
]
},
"repnz cmpsw": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 28,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x74",
"cbz x5, #+0x70",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3431,21 +3437,20 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #16",
"lsl w0, w27, #16",
"cmp w0, w26, lsl #16",
"sub w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"sub w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
]
},
"repnz cmpsd": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 26,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"cbz x5, #+0x68",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3466,19 +3471,18 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"subs w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
]
},
"repnz cmpsq": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 26,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x6c",
"cbz x5, #+0x68",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3499,12 +3503,11 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"mov x21, x27",
"mov x27, x20",
"subs x26, x21, x26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"subs x26, x27, x26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
]
},
"test al, 1": {
unittests/InstructionCountCI/PrimaryGroup.json
+190 -172
View File
@@ -16,15 +16,17 @@
],
"Instructions": {
"add al, 1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmn w0, w20, lsl #24",
"add w26, w4, #0x1 (1)",
"bfxil x4, x26, #0, #8"
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
]
},
"or al, 1": {
@@ -37,10 +39,9 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -55,15 +56,17 @@
"bic w21, w22, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxtb w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -77,8 +80,11 @@
"bic w20, w20, w26",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
]
},
"and al, 1": {
@@ -91,18 +97,20 @@
]
},
"sub al, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
]
},
"xor al, 1": {
@@ -119,13 +127,13 @@
"Comment": "GROUP1 0x80 /7",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"add al, -1": {
@@ -242,23 +250,25 @@
]
},
"add ax, 256": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x100 (256)",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"add eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds w26, w4, #0x100 (256)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -266,8 +276,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -275,18 +285,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w4, w4, #0x100",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, #0x100",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x4, x4, #0x100",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, #0x100",
"tst x26, x26",
"mov x4, x26"
]
},
"adc eax, 256": {
@@ -294,8 +304,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -304,8 +314,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -314,15 +324,15 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"sbb rax, 256": {
@@ -330,15 +340,15 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"and eax, 256": {
@@ -361,76 +371,78 @@
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"sub rax, 256": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"xor eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w4, w4, #0x100",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, #0x100",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x4, x4, #0x100",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, #0x100",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp eax, 256": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"cmp rax, 256": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"add ax, -256": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xff00",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, w20",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"add eax, -256": {
@@ -438,8 +450,8 @@
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"adds w26, w4, w20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -447,8 +459,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -456,18 +468,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w4, w4, #0xffffff00",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, #0xffffff00",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x4, x4, #0xffffffffffffff00",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, #0xffffffffffffff00",
"tst x26, x26",
"mov x4, x26"
]
},
"adc eax, -256": {
@@ -475,8 +487,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -485,8 +497,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -495,15 +507,15 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"sbb rax, -256": {
@@ -511,15 +523,15 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"and eax, -256": {
@@ -543,42 +555,42 @@
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"subs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"sub rax, -256": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"xor eax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w4, w4, #0xffffff00",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, #0xffffff00",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x4, x4, #0xffffffffffffff00",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, #0xffffffffffffff00",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp eax, -256": {
@@ -586,42 +598,44 @@
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"subs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"cmp rax, -256": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"add ax, 1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x1 (1)",
"bfxil x4, x26, #0, #16"
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
]
},
"add eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -629,8 +643,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -638,18 +652,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
]
},
"adc eax, 1": {
@@ -657,8 +671,8 @@
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -667,8 +681,8 @@
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -677,15 +691,15 @@
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"sbb rax, 1": {
@@ -693,15 +707,15 @@
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"and eax, 1": {
@@ -724,64 +738,64 @@
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"sub rax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
]
},
"xor eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp eax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"cmp rax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x4"
]
},
"add ax, -1": {
@@ -820,9 +834,9 @@
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
"orr w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
]
},
"or rax, -1": {
@@ -830,9 +844,9 @@
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
"orr x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
]
},
"adc eax, -1": {
@@ -867,8 +881,8 @@
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x4, x26"
]
},
"sbb rax, -1": {
@@ -883,8 +897,8 @@
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x4, x26"
]
},
"and eax, -1": {
@@ -914,8 +928,8 @@
"subs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x4, x26"
]
},
"sub rax, -1": {
@@ -926,8 +940,8 @@
"adds x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x4, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x4, x26"
]
},
"xor eax, -1": {
@@ -935,9 +949,9 @@
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"eor w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
"eor w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
]
},
"xor rax, -1": {
@@ -945,9 +959,9 @@
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"eor x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
"eor x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
]
},
"cmp eax, -1": {
@@ -1622,8 +1636,8 @@
"eor x21, x20, x4",
"lsr x21, x21, #63",
"bfi w22, w21, #28, #1",
"mov x4, x20",
"msr nzcv, x22"
"msr nzcv, x22",
"mov x4, x20"
]
},
"rcr ax, 1": {
@@ -2405,16 +2419,18 @@
]
},
"neg bl": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"mov x27, x7",
"cmp wzr, w7, lsl #24",
"neg w26, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"bfxil x7, x26, #0, #8",
"msr nzcv, x20"
"mov x21, x7",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x7",
"mov x7, x21"
]
},
"mul bl": {
@@ -2542,40 +2558,42 @@
]
},
"neg bx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"cmp wzr, w7, lsl #16",
"neg w26, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"bfxil x7, x26, #0, #16",
"msr nzcv, x20"
"mov x21, x7",
"bfxil x21, x26, #0, #16",
"msr nzcv, x20",
"mov x27, x7",
"mov x7, x21"
]
},
"neg ebx": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"negs w26, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x7, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x7",
"mov x7, x26"
]
},
"neg rbx": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"negs x26, x7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x7, x26",
"msr nzcv, x20"
"msr nzcv, x20",
"mov x27, x7",
"mov x7, x26"
]
},
"mul bx": {
@@ -2611,9 +2629,9 @@
"ExpectedArm64ASM": [
"mul x20, x7, x4",
"umulh x6, x7, x4",
"mov x4, x20",
"cmp x6, #0x0 (0)",
"ccmn xzr, #0, #nzCV, eq"
"ccmn xzr, #0, #nzCV, eq",
"mov x4, x20"
]
},
"imul bx": {
@@ -2851,12 +2869,12 @@
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"mov x4, x26",
"msr nzcv, x21"
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
]
},
"inc rax": {
@@ -2864,12 +2882,12 @@
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"mov x4, x26",
"msr nzcv, x21"
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
]
},
"dec ax": {
@@ -2893,12 +2911,12 @@
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"mov x4, x26",
"msr nzcv, x21"
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
]
},
"dec rax": {
@@ -2906,12 +2924,12 @@
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"mov x4, x26",
"msr nzcv, x21"
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
]
},
"push ax": {
unittests/InstructionCountCI/Primary_32Bit.json
+6 -6
View File
@@ -204,12 +204,12 @@
"Comment": "0x40",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"mov x4, x26",
"msr nzcv, x21"
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
]
},
"dec ax": {
@@ -247,12 +247,12 @@
"Comment": "0x48",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"mov x4, x26",
"msr nzcv, x21"
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
]
},
"pusha": {
unittests/InstructionCountCI/SecondaryGroup.json
+78 -78
View File
@@ -1389,21 +1389,21 @@
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #1040]",
"ldr d2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr q2, [x28, #1056]",
"ldr d2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr q2, [x28, #1072]",
"ldr d2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr q2, [x28, #1088]",
"ldr d2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr q2, [x28, #1104]",
"ldr d2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr q2, [x28, #1120]",
"ldr d2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr q2, [x28, #1136]",
"ldr d2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr q2, [x28, #1152]",
"ldr d2, [x28, #1152]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
@@ -1464,23 +1464,14 @@
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1298]",
"ldr q2, [x4, #32]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #1152]",
"ldr q3, [x4, #48]",
"ldr q4, [x4, #64]",
"ldr q5, [x4, #80]",
"ldr q6, [x4, #96]",
"ldr q7, [x4, #112]",
"ldr q8, [x4, #128]",
"ldr q9, [x4, #144]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@@ -1497,15 +1488,24 @@
"ldr q29, [x4, #368]",
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"ldr w20, [x4, #24]",
"ubfx w20, w20, #13, #3",
"rbit w1, w20",
"ldr w21, [x4, #24]",
"ubfx w21, w21, #13, #3",
"rbit w1, w21",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x20, #2",
"lsr x1, x21, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0"
"msr fpcr, x0",
"strb w20, [x28, #1298]",
"str d9, [x28, #1152]",
"str d8, [x28, #1136]",
"str d7, [x28, #1120]",
"str d6, [x28, #1104]",
"str d5, [x28, #1088]",
"str d4, [x28, #1072]",
"str d3, [x28, #1056]",
"str d2, [x28, #1040]"
]
},
"rdgsbase eax": {
@@ -1603,21 +1603,21 @@
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #1040]",
"ldr d2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr q2, [x28, #1056]",
"ldr d2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr q2, [x28, #1072]",
"ldr d2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr q2, [x28, #1088]",
"ldr d2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr q2, [x28, #1104]",
"ldr d2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr q2, [x28, #1120]",
"ldr d2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr q2, [x28, #1136]",
"ldr d2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr q2, [x28, #1152]",
"ldr d2, [x28, #1152]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
@@ -1683,23 +1683,23 @@
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1298]",
"ldr q2, [x4, #32]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #1152]",
"ldr q3, [x4, #48]",
"ldr q4, [x4, #64]",
"ldr q5, [x4, #80]",
"ldr q6, [x4, #96]",
"ldr q7, [x4, #112]",
"ldr q8, [x4, #128]",
"ldr q9, [x4, #144]",
"strb w20, [x28, #1298]",
"str d9, [x28, #1152]",
"str d8, [x28, #1136]",
"str d7, [x28, #1120]",
"str d6, [x28, #1104]",
"str d5, [x28, #1088]",
"str d4, [x28, #1072]",
"str d3, [x28, #1056]",
"str d2, [x28, #1040]",
"b #+0x4c",
"mov w20, #0x0",
"mov w21, #0x37f",
@@ -1709,16 +1709,16 @@
"strb w20, [x28, #1017]",
"strb w20, [x28, #1018]",
"strb w20, [x28, #1022]",
"strb w20, [x28, #1298]",
"movi v2.2d, #0x0",
"str q2, [x28, #1040]",
"str q2, [x28, #1056]",
"str q2, [x28, #1072]",
"str q2, [x28, #1088]",
"str q2, [x28, #1104]",
"str q2, [x28, #1120]",
"str q2, [x28, #1136]",
"str q2, [x28, #1152]",
"strb w20, [x28, #1298]",
"str d2, [x28, #1152]",
"str d2, [x28, #1136]",
"str d2, [x28, #1120]",
"str d2, [x28, #1104]",
"str d2, [x28, #1088]",
"str d2, [x28, #1072]",
"str d2, [x28, #1056]",
"str d2, [x28, #1040]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #1",
"cbnz x20, #+0x8",
@@ -1740,22 +1740,22 @@
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"b #+0x44",
"movi v16.2d, #0x0",
"mov v17.16b, v16.16b",
"mov v18.16b, v16.16b",
"mov v19.16b, v16.16b",
"mov v20.16b, v16.16b",
"mov v21.16b, v16.16b",
"mov v22.16b, v16.16b",
"mov v23.16b, v16.16b",
"mov v24.16b, v16.16b",
"mov v25.16b, v16.16b",
"mov v26.16b, v16.16b",
"mov v27.16b, v16.16b",
"mov v28.16b, v16.16b",
"mov v29.16b, v16.16b",
"mov v30.16b, v16.16b",
"mov v31.16b, v16.16b",
"movi v31.2d, #0x0",
"mov v30.16b, v31.16b",
"mov v29.16b, v31.16b",
"mov v28.16b, v31.16b",
"mov v27.16b, v31.16b",
"mov v26.16b, v31.16b",
"mov v25.16b, v31.16b",
"mov v24.16b, v31.16b",
"mov v23.16b, v31.16b",
"mov v22.16b, v31.16b",
"mov v21.16b, v31.16b",
"mov v20.16b, v31.16b",
"mov v19.16b, v31.16b",
"mov v18.16b, v31.16b",
"mov v17.16b, v31.16b",
"mov v16.16b, v31.16b",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #2",
"cbnz x20, #+0x8",
unittests/InstructionCountCI/VEX_map2.json
+6 -6
View File
@@ -3172,9 +3172,9 @@
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w4, w5, w7",
"mov x26, x4",
"tst w4, w4"
"bic w26, w5, w7",
"tst w26, w26",
"mov x4, x26"
]
},
"andn rax, rbx, rcx": {
@@ -3183,9 +3183,9 @@
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x4, x5, x7",
"mov x26, x4",
"tst x4, x4"
"bic x26, x5, x7",
"tst x26, x26",
"mov x4, x26"
]
},
"bzhi eax, ebx, ecx": {
unittests/InstructionCountCI/x87.json
+369 -375
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/x87_f64.json
+369 -377
View File
File diff suppressed because it is too large. Load diff