steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-14 09:00:40 +02:00
Code Issues Packages Projects Releases 67 Wiki Activity

Add x87 memcpy instcountci tests

Browse Source
This commit is contained in:
Paulo Matos committed 2024-07-19 09:09:34 +02:00
1 parent 17a55fbb39
commit c77a707dbe
4 files changed
+1584
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

unittests/InstructionCountCI/FlagM/x87.json
+604
View File
@@ -17853,6 +17853,610 @@
"strb w20, [x28, #1019]",
"strb w21, [x28, #1298]"
]
},
"memcpy4_32": {
"ExpectedInstructionCount": 287,
"x86Insts": [
"fld dword [rax]",
"fstp dword [rdx]",
"fld dword [rax + 4]",
"fstp dword [rdx + 4]",
"fld dword [rax + 8]",
"fstp dword [rdx + 8]",
"fld dword [rax + 12]",
"fstp dword [rdx + 12]"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldr s2, [x4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"fmov s0, s2",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1424]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1298]",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1440]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x6]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"fmov s0, s2",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1424]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1440]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x6, #4]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #8]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"fmov s0, s2",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1424]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1440]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x6, #8]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #12]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"fmov s0, s2",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1424]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1440]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x6, #12]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w21, [x28, #1298]"
]
},
"memcpy4_64": {
"ExpectedInstructionCount": 287,
"x86Insts": [
"fld qword [rax]",
"fstp qword [rdx]",
"fld qword [rax + 8]",
"fstp qword [rdx + 8]",
"fld qword [rax + 16]",
"fstp qword [rdx + 16]",
"fld qword [rax + 32]",
"fstp qword [rdx + 32]"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldr d2, [x4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"mov v0.8b, v2.8b",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1432]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1298]",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1448]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov v2.8b, v0.8b",
"str d2, [x6]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #8]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"mov v0.8b, v2.8b",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1432]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1448]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov v2.8b, v0.8b",
"str d2, [x6, #8]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #16]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"mov v0.8b, v2.8b",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1432]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1448]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov v2.8b, v0.8b",
"str d2, [x6, #16]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #32]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"mov v0.8b, v2.8b",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1432]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1448]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov v2.8b, v0.8b",
"str d2, [x6, #32]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w21, [x28, #1298]"
]
}
}
}
unittests/InstructionCountCI/FlagM/x87_f64.json
+188
View File
@@ -10274,6 +10274,194 @@
"strb w20, [x28, #1019]",
"strb w21, [x28, #1298]"
]
},
"memcpy4_32": {
"ExpectedInstructionCount": 83,
"x86Insts": [
"fld dword [rax]",
"fstp dword [rdx]",
"fld dword [rax + 4]",
"fstp dword [rdx + 4]",
"fld dword [rax + 8]",
"fstp dword [rdx + 8]",
"fld dword [rax + 12]",
"fstp dword [rdx + 12]"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldr s2, [x4]",
"fcvt d2, s2",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1298]",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"fcvt s2, d2",
"str s2, [x6]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #4]",
"fcvt d2, s2",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"fcvt s2, d2",
"str s2, [x6, #4]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #8]",
"fcvt d2, s2",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"fcvt s2, d2",
"str s2, [x6, #8]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #12]",
"fcvt d2, s2",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"fcvt s2, d2",
"str s2, [x6, #12]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w21, [x28, #1298]"
]
},
"memcpy4_64": {
"ExpectedInstructionCount": 75,
"x86Insts": [
"fld qword [rax]",
"fstp qword [rdx]",
"fld qword [rax + 8]",
"fstp qword [rdx + 8]",
"fld qword [rax + 16]",
"fstp qword [rdx + 16]",
"fld qword [rax + 32]",
"fstp qword [rdx + 32]"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldr d2, [x4]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1298]",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"str d2, [x6]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #8]",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"str d2, [x6, #8]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #16]",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"str d2, [x6, #16]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #32]",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"str d2, [x6, #32]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w21, [x28, #1298]"
]
}
}
}
unittests/InstructionCountCI/x87.json
+604
View File
@@ -17884,6 +17884,610 @@
"msr nzcv, x22",
"strb w21, [x28, #1298]"
]
},
"memcpy4_32": {
"ExpectedInstructionCount": 287,
"x86Insts": [
"fld dword [rax]",
"fstp dword [rdx]",
"fld dword [rax + 4]",
"fstp dword [rdx + 4]",
"fld dword [rax + 8]",
"fstp dword [rdx + 8]",
"fld dword [rax + 12]",
"fstp dword [rdx + 12]"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldr s2, [x4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"fmov s0, s2",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1424]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1298]",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1440]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x6]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"fmov s0, s2",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1424]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1440]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x6, #4]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #8]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"fmov s0, s2",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1424]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1440]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x6, #8]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #12]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"fmov s0, s2",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1424]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1440]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x6, #12]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w21, [x28, #1298]"
]
},
"memcpy4_64": {
"ExpectedInstructionCount": 287,
"x86Insts": [
"fld qword [rax]",
"fstp qword [rdx]",
"fld qword [rax + 8]",
"fstp qword [rdx + 8]",
"fld qword [rax + 16]",
"fstp qword [rdx + 16]",
"fld qword [rax + 32]",
"fstp qword [rdx + 32]"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldr d2, [x4]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"mov v0.8b, v2.8b",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1432]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1298]",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1448]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov v2.8b, v0.8b",
"str d2, [x6]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #8]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"mov v0.8b, v2.8b",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1432]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1448]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov v2.8b, v0.8b",
"str d2, [x6, #8]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #16]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"mov v0.8b, v2.8b",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1432]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1448]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov v2.8b, v0.8b",
"str d2, [x6, #16]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #32]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"mov v0.8b, v2.8b",
"ldrh w0, [x28, #1296]",
"ldr x1, [x28, #1432]",
"blr x1",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"eor v2.16b, v2.16b, v2.16b",
"mov v2.d[0], x0",
"mov v2.h[4], w1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1040]",
"mrs x0, nzcv",
"str w0, [x28, #1000]",
"stp x4, x5, [x28, #280]",
"stp x6, x7, [x28, #296]",
"str x8, [x28, #312]",
"stp x16, x17, [x28, #376]",
"sub sp, sp, #0x70 (112)",
"mov x0, sp",
"st1 {v2.2d, v3.2d}, [x0], #32",
"st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64",
"str x30, [x0], #16",
"ldrh w0, [x28, #1296]",
"mov x1, v2.d[0]",
"umov w2, v2.h[4]",
"ldr x3, [x28, #1448]",
"blr x3",
"ldr w4, [x28, #1000]",
"msr nzcv, x4",
"ldp x4, x5, [x28, #280]",
"ldp x6, x7, [x28, #296]",
"ldr x8, [x28, #312]",
"ldp x16, x17, [x28, #376]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ldr x30, [sp], #16",
"mov v2.8b, v0.8b",
"str d2, [x6, #32]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w21, [x28, #1298]"
]
}
}
}
unittests/InstructionCountCI/x87_f64.json
+188
View File
@@ -10508,6 +10508,194 @@
"msr nzcv, x22",
"strb w21, [x28, #1298]"
]
},
"memcpy4_32": {
"ExpectedInstructionCount": 83,
"x86Insts": [
"fld dword [rax]",
"fstp dword [rdx]",
"fld dword [rax + 4]",
"fstp dword [rdx + 4]",
"fld dword [rax + 8]",
"fstp dword [rdx + 8]",
"fld dword [rax + 12]",
"fstp dword [rdx + 12]"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldr s2, [x4]",
"fcvt d2, s2",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1298]",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"fcvt s2, d2",
"str s2, [x6]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #4]",
"fcvt d2, s2",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"fcvt s2, d2",
"str s2, [x6, #4]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #8]",
"fcvt d2, s2",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"fcvt s2, d2",
"str s2, [x6, #8]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr s2, [x4, #12]",
"fcvt d2, s2",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"fcvt s2, d2",
"str s2, [x6, #12]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w21, [x28, #1298]"
]
},
"memcpy4_64": {
"ExpectedInstructionCount": 75,
"x86Insts": [
"fld qword [rax]",
"fstp qword [rdx]",
"fld qword [rax + 8]",
"fstp qword [rdx + 8]",
"fld qword [rax + 16]",
"fstp qword [rdx + 16]",
"fld qword [rax + 32]",
"fstp qword [rdx + 32]"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1019]",
"ldr d2, [x4]",
"mov w21, #0x1",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldrb w22, [x28, #1298]",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"str d2, [x6]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #8]",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"str d2, [x6, #8]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #16]",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"str d2, [x6, #16]",
"lsl w23, w21, w20",
"bic w22, w22, w23",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"ldrb w20, [x28, #1019]",
"ldr d2, [x4, #32]",
"sub w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w23, w21, w20",
"orr w22, w22, w23",
"strb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"str d2, [x0, #1040]",
"ldrb w20, [x28, #1019]",
"add x0, x28, x20, lsl #4",
"ldr d2, [x0, #1040]",
"str d2, [x6, #32]",
"lsl w21, w21, w20",
"bic w21, w22, w21",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1019]",
"strb w21, [x28, #1298]"
]
}
}
}