steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-06 13:00:15 +02:00
Code Issues Packages Projects Releases 66 Wiki Activity

InstCountCI: Update

Browse Source 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2024-07-05 18:44:21 -04:00
1 parent b67343fc5a
commit 9b570de33f
4 files changed
+38 -63
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+6 -12
View File
@@ -1623,19 +1623,16 @@
]
},
"shl al, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd2 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"and w0, w5, #0x1f",
"cbz w0, #+0x24",
"cbz w0, #+0x18",
"cmn wzr, w20, lsl #24",
"mov x26, x20",
"mov w0, #0x8",
"sub w0, w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"rmif x0, #63, #nzCv",
"rmif x20, #7, #nzCv",
"rmif x2, #7, #nzcV",
"bfxil x4, x20, #0, #8"
]
@@ -1892,19 +1889,16 @@
]
},
"shl ax, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"and w0, w5, #0x1f",
"cbz w0, #+0x24",
"cbz w0, #+0x18",
"cmn wzr, w20, lsl #16",
"mov x26, x20",
"mov w0, #0x10",
"sub w0, w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"rmif x0, #63, #nzCv",
"rmif x20, #15, #nzCv",
"rmif x2, #15, #nzcV",
"bfxil x4, x20, #0, #16"
]
unittests/InstructionCountCI/FlagM/Secondary.json
+17 -22
View File
@@ -655,29 +655,27 @@
]
},
"shld ax, bx, 16": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x21, x21, #16",
"orr x26, x21, x20",
"cmn wzr, w26, lsl #16",
"bfxil x4, x26, #0, #16"
]
},
"shld ax, bx, 31": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #16",
"orr x26, x22, x20",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv",
"bfxil x4, x26, #0, #16"
]
},
"shld ax, bx, 31": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #31",
"lsl x21, x21, #31",
"lsr w20, w20, #17",
"orr x26, x22, x20",
"orr x26, x21, x20",
"cmn wzr, w26, lsl #16",
"rmif x21, #0, #nzCv",
"bfxil x4, x26, #0, #16"
]
},
@@ -766,7 +764,7 @@
]
},
"shld ax, bx, cl": {
"ExpectedInstructionCount": 23,
"ExpectedInstructionCount": 20,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -782,14 +780,11 @@
"csel x20, x21, x20, eq",
"msr nzcv, x23",
"and w0, w22, #0x1f",
"cbz w0, #+0x24",
"cbz w0, #+0x18",
"cmn wzr, w20, lsl #16",
"mov x26, x20",
"mov w0, #0x10",
"sub w0, w0, w22",
"lsr w0, w21, w0",
"eor w2, w21, w20",
"rmif x0, #63, #nzCv",
"rmif x20, #15, #nzCv",
"rmif x2, #15, #nzcV",
"bfxil x4, x20, #0, #16"
]
unittests/InstructionCountCI/PrimaryGroup.json
+6 -10
View File
@@ -1914,19 +1914,17 @@
]
},
"shl al, cl": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd2 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"and w0, w5, #0x1f",
"cbz w0, #+0x30",
"cbz w0, #+0x28",
"cmn wzr, w20, lsl #24",
"mov x26, x20",
"mov w0, #0x8",
"sub w0, w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"mrs x1, nzcv",
"lsr x0, x20, #8",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #7",
"bfi w1, w2, #28, #1",
@@ -2239,19 +2237,17 @@
]
},
"shl ax, cl": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"lsl w20, w4, w5",
"and w0, w5, #0x1f",
"cbz w0, #+0x30",
"cbz w0, #+0x28",
"cmn wzr, w20, lsl #16",
"mov x26, x20",
"mov w0, #0x10",
"sub w0, w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"mrs x1, nzcv",
"lsr x0, x20, #16",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #15",
"bfi w1, w2, #28, #1",
unittests/InstructionCountCI/Secondary.json
+9 -19
View File
@@ -1428,35 +1428,27 @@
]
},
"shld ax, bx, 16": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #16",
"orr x26, x22, x20",
"lsl x21, x21, #16",
"orr x26, x21, x20",
"cmn wzr, w26, lsl #16",
"ubfx x20, x21, #0, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20",
"bfxil x4, x26, #0, #16"
]
},
"shld ax, bx, 31": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #31",
"lsl x21, x21, #31",
"lsr w20, w20, #17",
"orr x26, x22, x20",
"orr x26, x21, x20",
"cmn wzr, w26, lsl #16",
"ubfx x20, x21, #1, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20",
"bfxil x4, x26, #0, #16"
]
},
@@ -1583,7 +1575,7 @@
]
},
"shld ax, bx, cl": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 24,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -1599,14 +1591,12 @@
"csel x20, x21, x20, eq",
"msr nzcv, x23",
"and w0, w22, #0x1f",
"cbz w0, #+0x30",
"cbz w0, #+0x28",
"cmn wzr, w20, lsl #16",
"mov x26, x20",
"mov w0, #0x10",
"sub w0, w0, w22",
"lsr w0, w21, w0",
"eor w2, w21, w20",
"mrs x1, nzcv",
"lsr x0, x20, #16",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #15",
"bfi w1, w2, #28, #1",