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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2024-05-20 10:33:15 -04:00
1 parent 769b2c2a46
commit ebfcc1e835
3 files changed
+206 -254
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unittests/InstructionCountCI/FEXOpt/MultiInst.json
+11 -21
View File
@@ -1024,7 +1024,7 @@
]
},
"Sekiro spill block": {
"ExpectedInstructionCount": 176,
"ExpectedInstructionCount": 166,
"Comment": [
"This block of code came from the settings screen when it loaded",
"It was originally at RIP: 0x14232cca0 and has been deobfuscated"
@@ -1176,8 +1176,7 @@
"str w5, [x8, #104]",
"mov w21, #0x1000000",
"add w4, w4, w21",
"mov w21, w4",
"lsr w4, w21, #25",
"lsr w4, w4, #25",
"add w4, w4, w10",
"mov w21, w4",
"asr w4, w21, #26",
@@ -1213,16 +1212,14 @@
"mov w4, w10",
"asr w4, w4, #26",
"add w9, w9, w4",
"mov w20, w4",
"lsl w4, w20, #26",
"lsl w4, w4, #26",
"sub w10, w10, w4",
"mov w5, w9",
"ldr x20, [x8, #96]",
"mov x4, x20",
"asr w5, w5, #25",
"add w19, w19, w5",
"mov w21, w5",
"lsl w5, w21, #25",
"lsl w5, w5, #25",
"mov w6, w19",
"sub w9, w9, w5",
"asr w6, w6, #26",
@@ -1230,23 +1227,20 @@
"mov w21, w10",
"str w21, [x20]",
"mov w12, w29",
"mov w21, w6",
"lsl w6, w21, #26",
"lsl w6, w6, #26",
"asr w12, w12, #25",
"sub w19, w19, w6",
"add w16, w16, w12",
"mov w21, w9",
"str w21, [x20, #4]",
"mov w13, w16",
"mov w21, w12",
"lsl w12, w21, #25",
"lsl w12, w12, #25",
"asr w13, w13, #26",
"sub w29, w29, w12",
"add w17, w17, w13",
"mov w21, w19",
"str w21, [x20, #8]",
"mov w21, w13",
"lsl w13, w21, #26",
"lsl w13, w13, #26",
"mov w14, w17",
"asr w14, w14, #25",
"sub w16, w16, w13",
@@ -1273,24 +1267,20 @@
"ldr w21, [x8, #104]",
"add w21, w21, w11",
"str w21, [x8, #104]",
"mov w21, w14",
"lsl w14, w21, #25",
"lsl w14, w14, #25",
"ldr w5, [x8, #104]",
"sub w17, w17, w14",
"mov w21, w17",
"str w21, [x20, #20]",
"ldr w4, [x8, #112]",
"mov w21, w15",
"lsl w15, w21, #26",
"lsl w15, w15, #26",
"sub w4, w4, w15",
"mov w21, w7",
"lsl w7, w21, #25",
"lsl w7, w7, #25",
"mov w21, w4",
"str w21, [x20, #24]",
"ldr w4, [x8, #120]",
"sub w4, w4, w7",
"mov w21, w11",
"lsl w11, w21, #26",
"lsl w11, w11, #26",
"mov w21, w4",
"str w21, [x20, #28]",
"ldr w4, [x8]",
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+90 -109
View File
@@ -959,13 +959,12 @@
]
},
"shl al, 2": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC0 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsl w26, w20, #2",
"lsl w26, w4, #2",
"cmn wzr, w26, lsl #24",
"rmif x20, #5, #nzCv",
"rmif x4, #5, #nzCv",
"bfxil x4, x26, #0, #8"
]
},
@@ -1129,24 +1128,22 @@
]
},
"shl ax, 2": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsl w26, w20, #2",
"lsl w26, w4, #2",
"cmn wzr, w26, lsl #16",
"rmif x20, #13, #nzCv",
"rmif x4, #13, #nzCv",
"bfxil x4, x26, #0, #16"
]
},
"shl eax, 2": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"lsl w26, w20, #2",
"lsl w26, w4, #2",
"tst w26, w26",
"rmif x20, #29, #nzCv",
"rmif x4, #29, #nzCv",
"mov x4, x26"
]
},
@@ -1172,13 +1169,12 @@
]
},
"shr eax, 2": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"lsr w26, w20, #2",
"lsr w26, w4, #2",
"tst w26, w26",
"rmif x20, #0, #nzCv",
"rmif x4, #0, #nzCv",
"mov x4, x26"
]
},
@@ -1280,14 +1276,13 @@
]
},
"shl al, 1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd0 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsl w26, w20, #1",
"lsl w26, w4, #1",
"cmn wzr, w26, lsl #24",
"rmif x20, #6, #nzCv",
"eor w20, w26, w20",
"rmif x4, #6, #nzCv",
"eor w20, w26, w4",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
@@ -1455,27 +1450,25 @@
]
},
"shl ax, 1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsl w26, w20, #1",
"lsl w26, w4, #1",
"cmn wzr, w26, lsl #16",
"rmif x20, #14, #nzCv",
"eor w20, w26, w20",
"rmif x4, #14, #nzCv",
"eor w20, w26, w4",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
},
"shl eax, 1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"lsl w26, w20, #1",
"lsl w26, w4, #1",
"tst w26, w26",
"rmif x20, #30, #nzCv",
"eor w20, w26, w20",
"rmif x4, #30, #nzCv",
"eor w20, w26, w4",
"rmif x20, #31, #nzcV",
"mov x4, x26"
]
@@ -1505,14 +1498,13 @@
]
},
"shr eax, 1": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xd1 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"lsr w26, w20, #1",
"lsr w26, w4, #1",
"tst w26, w26",
"rmif x20, #63, #nzCv",
"rmif x20, #31, #nzcV",
"rmif x4, #63, #nzCv",
"rmif x4, #31, #nzcV",
"mov x4, x26"
]
},
@@ -1651,57 +1643,53 @@
]
},
"shl al, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd2 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"lsl w22, w20, w21",
"cbz w21, #+0x24",
"cmn wzr, w22, lsl #24",
"mov x26, x22",
"lsl w20, w4, w5",
"cbz w5, #+0x24",
"cmn wzr, w20, lsl #24",
"mov x26, x20",
"mov w0, #0x8",
"sub w0, w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"sub w0, w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"rmif x0, #63, #nzCv",
"rmif x2, #7, #nzcV",
"bfxil x4, x22, #0, #8"
"bfxil x4, x20, #0, #8"
]
},
"shr al, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd2 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"lsr w22, w20, w21",
"cbz w21, #+0x20",
"cmn wzr, w22, lsl #24",
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"lsr w21, w20, w5",
"cbz w5, #+0x20",
"cmn wzr, w21, lsl #24",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"eor w2, w20, w21",
"rmif x0, #63, #nzCv",
"rmif x2, #7, #nzcV",
"bfxil x4, x22, #0, #8"
"bfxil x4, x21, #0, #8"
]
},
"sar al, cl": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd2 /7",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"sxtb x20, w20",
"asr w22, w20, w21",
"cbz w21, #+0x18",
"cmn wzr, w22, lsl #24",
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"asr w21, w20, w5",
"cbz w5, #+0x18",
"cmn wzr, w21, lsl #24",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv",
"bfxil x4, x22, #0, #8"
"bfxil x4, x21, #0, #8"
]
},
"rol ax, cl": {
@@ -1918,34 +1906,31 @@
]
},
"shl ax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"lsl w22, w20, w21",
"cbz w21, #+0x24",
"cmn wzr, w22, lsl #16",
"mov x26, x22",
"lsl w20, w4, w5",
"cbz w5, #+0x24",
"cmn wzr, w20, lsl #16",
"mov x26, x20",
"mov w0, #0x10",
"sub w0, w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"sub w0, w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV",
"bfxil x4, x22, #0, #16"
"bfxil x4, x20, #0, #16"
]
},
"shl eax, cl": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsl w4, w20, w21",
"cbz w21, #+0x1c",
"mov x20, x4",
"lsl w4, w20, w5",
"cbz w5, #+0x1c",
"ands w26, w4, w4",
"neg w0, w21",
"neg w0, w5",
"lsr w0, w20, w0",
"eor w2, w20, w4",
"rmif x0, #63, #nzCv",
@@ -1968,33 +1953,31 @@
]
},
"shr ax, cl": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 11,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"lsr w22, w20, w21",
"cbz w21, #+0x20",
"cmn wzr, w22, lsl #16",
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"lsr w21, w20, w5",
"cbz w5, #+0x20",
"cmn wzr, w21, lsl #16",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"eor w2, w20, w21",
"rmif x0, #63, #nzCv",
"rmif x2, #15, #nzcV",
"bfxil x4, x22, #0, #16"
"bfxil x4, x21, #0, #16"
]
},
"shr eax, cl": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsr w4, w20, w21",
"cbz w21, #+0x1c",
"mov x20, x4",
"lsr w4, w20, w5",
"cbz w5, #+0x1c",
"ands w26, w4, w4",
"sub x0, x21, #0x1 (1)",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w4",
"rmif x0, #63, #nzCv",
@@ -2017,32 +2000,30 @@
]
},
"sar ax, cl": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"sxth x20, w20",
"asr w22, w20, w21",
"cbz w21, #+0x18",
"cmn wzr, w22, lsl #16",
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"asr w21, w20, w5",
"cbz w5, #+0x18",
"cmn wzr, w21, lsl #16",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv",
"bfxil x4, x22, #0, #16"
"bfxil x4, x21, #0, #16"
]
},
"sar eax, cl": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"asr w4, w20, w21",
"cbz w21, #+0x14",
"asr w4, w20, w5",
"cbz w5, #+0x14",
"ands w26, w4, w4",
"sub x0, x21, #0x1 (1)",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"rmif x0, #63, #nzCv"
]
unittests/InstructionCountCI/PrimaryGroup.json
+105 -124
View File
@@ -1064,13 +1064,12 @@
]
},
"shl al, 2": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xC0 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsl w26, w20, #2",
"lsl w26, w4, #2",
"cmn wzr, w26, lsl #24",
"ubfx x20, x20, #6, #1",
"ubfx x20, x4, #6, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20",
@@ -1285,13 +1284,12 @@
]
},
"shl ax, 2": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsl w26, w20, #2",
"lsl w26, w4, #2",
"cmn wzr, w26, lsl #16",
"ubfx x20, x20, #14, #1",
"ubfx x20, x4, #14, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20",
@@ -1299,13 +1297,12 @@
]
},
"shl eax, 2": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xC1 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"lsl w26, w20, #2",
"lsl w26, w4, #2",
"tst w26, w26",
"ubfx x20, x20, #30, #1",
"ubfx x20, x4, #30, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20",
@@ -1340,13 +1337,12 @@
]
},
"shr eax, 2": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xC1 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"lsr w26, w20, #2",
"lsr w26, w4, #2",
"tst w26, w26",
"ubfx x20, x20, #1, #1",
"ubfx x20, x4, #1, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20",
@@ -1489,18 +1485,17 @@
]
},
"shl al, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd0 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"lsl w26, w20, #1",
"lsl w26, w4, #1",
"cmn wzr, w26, lsl #24",
"ubfx x21, x20, #7, #1",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w20, w26, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"ubfx x20, x4, #7, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w26, w4",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20",
"bfxil x4, x26, #0, #8"
]
@@ -1753,35 +1748,33 @@
]
},
"shl ax, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"lsl w26, w20, #1",
"lsl w26, w4, #1",
"cmn wzr, w26, lsl #16",
"ubfx x21, x20, #15, #1",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w20, w26, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"ubfx x20, x4, #15, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w26, w4",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20",
"bfxil x4, x26, #0, #16"
]
},
"shl eax, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xd1 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"lsl w26, w20, #1",
"lsl w26, w4, #1",
"tst w26, w26",
"ubfx x21, x20, #31, #1",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w20, w26, w20",
"ubfx x20, x20, #31, #1",
"orr w20, w21, w20, lsl #28",
"ubfx x20, x4, #31, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w26, w4",
"ubfx x21, x21, #31, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20",
"mov x4, x26"
]
@@ -1819,17 +1812,16 @@
]
},
"shr eax, 1": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd1 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"lsr w26, w20, #1",
"lsr w26, w4, #1",
"tst w26, w26",
"ubfx x21, x20, #0, #1",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"ubfx x20, x20, #31, #1",
"orr w20, w21, w20, lsl #28",
"ubfx x20, x4, #0, #1",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"ubfx x21, x4, #31, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20",
"mov x4, x26"
]
@@ -2006,65 +1998,61 @@
]
},
"shl al, cl": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd2 /4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"lsl w22, w20, w21",
"cbz w21, #+0x30",
"cmn wzr, w22, lsl #24",
"mov x26, x22",
"lsl w20, w4, w5",
"cbz w5, #+0x30",
"cmn wzr, w20, lsl #24",
"mov x26, x20",
"mov w0, #0x8",
"sub w0, w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"sub w0, w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #7",
"bfi w1, w2, #28, #1",
"msr nzcv, x1",
"bfxil x4, x22, #0, #8"
"bfxil x4, x20, #0, #8"
]
},
"shr al, cl": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd2 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"lsr w22, w20, w21",
"cbz w21, #+0x2c",
"cmn wzr, w22, lsl #24",
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"lsr w21, w20, w5",
"cbz w5, #+0x2c",
"cmn wzr, w21, lsl #24",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"eor w2, w20, w21",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #7",
"bfi w1, w2, #28, #1",
"msr nzcv, x1",
"bfxil x4, x22, #0, #8"
"bfxil x4, x21, #0, #8"
]
},
"sar al, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd2 /7",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w5",
"sxtb x20, w20",
"asr w22, w20, w21",
"cbz w21, #+0x20",
"cmn wzr, w22, lsl #24",
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"asr w21, w20, w5",
"cbz w5, #+0x20",
"cmn wzr, w21, lsl #24",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"msr nzcv, x1",
"bfxil x4, x22, #0, #8"
"bfxil x4, x21, #0, #8"
]
},
"rol ax, cl": {
@@ -2357,37 +2345,34 @@
]
},
"shl ax, cl": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"lsl w22, w20, w21",
"cbz w21, #+0x30",
"cmn wzr, w22, lsl #16",
"mov x26, x22",
"lsl w20, w4, w5",
"cbz w5, #+0x30",
"cmn wzr, w20, lsl #16",
"mov x26, x20",
"mov w0, #0x10",
"sub w0, w0, w21",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"sub w0, w0, w5",
"lsr w0, w4, w0",
"eor w2, w4, w20",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #15",
"bfi w1, w2, #28, #1",
"msr nzcv, x1",
"bfxil x4, x22, #0, #16"
"bfxil x4, x20, #0, #16"
]
},
"shl eax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd3 /4",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsl w4, w20, w21",
"cbz w21, #+0x28",
"mov x20, x4",
"lsl w4, w20, w5",
"cbz w5, #+0x28",
"ands w26, w4, w4",
"neg w0, w21",
"neg w0, w5",
"lsr w0, w20, w0",
"eor w2, w20, w4",
"mrs x1, nzcv",
@@ -2416,36 +2401,34 @@
]
},
"shr ax, cl": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"lsr w22, w20, w21",
"cbz w21, #+0x2c",
"cmn wzr, w22, lsl #16",
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"lsr w21, w20, w5",
"cbz w5, #+0x2c",
"cmn wzr, w21, lsl #16",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w22",
"eor w2, w20, w21",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"lsr w2, w2, #15",
"bfi w1, w2, #28, #1",
"msr nzcv, x1",
"bfxil x4, x22, #0, #16"
"bfxil x4, x21, #0, #16"
]
},
"shr eax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd3 /5",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"lsr w4, w20, w21",
"cbz w21, #+0x28",
"mov x20, x4",
"lsr w4, w20, w5",
"cbz w5, #+0x28",
"ands w26, w4, w4",
"sub x0, x21, #0x1 (1)",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"eor w2, w20, w4",
"mrs x1, nzcv",
@@ -2474,34 +2457,32 @@
]
},
"sar ax, cl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 12,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w5",
"sxth x20, w20",
"asr w22, w20, w21",
"cbz w21, #+0x20",
"cmn wzr, w22, lsl #16",
"mov x26, x22",
"sub x0, x21, #0x1 (1)",
"asr w21, w20, w5",
"cbz w5, #+0x20",
"cmn wzr, w21, lsl #16",
"mov x26, x21",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",
"msr nzcv, x1",
"bfxil x4, x22, #0, #16"
"bfxil x4, x21, #0, #16"
]
},
"sar eax, cl": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xd3 /7",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w5",
"asr w4, w20, w21",
"cbz w21, #+0x1c",
"asr w4, w20, w5",
"cbz w5, #+0x1c",
"ands w26, w4, w4",
"sub x0, x21, #0x1 (1)",
"sub x0, x5, #0x1 (1)",
"lsr w0, w20, w0",
"mrs x1, nzcv",
"bfi w1, w0, #29, #1",