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instcountci: Fixes AFP.NEP handling on scalar insertions

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This commit is contained in:
Paulo Matos committed 2024-06-19 10:02:54 +02:00
1 parent 2483329ef6
commit 9acd325aa4
10 files changed
+43 -34
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unittests/InstructionCountCI/AFP/SVE256/Secondary.json
+8 -4
View File
@@ -10,23 +10,27 @@
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 4,
"Comment": [
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"scvtf v16.2s, v2.2s"
"scvtf v0.2s, v2.2s",
"ptrue p0.d, vl1",
"mov z16.d, p0/m, z0.d"
]
},
"cvtpi2ps xmm0, mm0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 4,
"Comment": [
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"scvtf v16.2s, v2.2s"
"scvtf v0.2s, v2.2s",
"ptrue p0.d, vl1",
"mov z16.d, p0/m, z0.d"
]
}
}
unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json
+5 -4
View File
@@ -46,7 +46,7 @@
]
},
"rsqrtss xmm0, xmm1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": [
"FEAT_FPRES could make this more optimal",
"0xf3 0x0f 0x52"
@@ -54,7 +54,8 @@
"ExpectedArm64ASM": [
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s17",
"fdiv s16, s0, s1"
"fdiv s0, s0, s1",
"mov v16.s[0], v0.s[0]"
]
},
"rcpss xmm0, xmm1": {
@@ -143,7 +144,7 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq s16, s16, s17"
"fcmeq s16, s17, s16"
]
},
"cmpss xmm0, xmm1, 1": {
@@ -184,7 +185,7 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq s0, s16, s17",
"fcmeq s0, s17, s16",
"mvn v0.8b, v0.8b",
"ptrue p0.s, vl1",
"mov z16.s, p0/m, z0.s"
unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json
+2 -2
View File
@@ -135,7 +135,7 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq d16, d16, d17"
"fcmeq d16, d17, d16"
]
},
"cmpsd xmm0, xmm1, 1": {
@@ -176,7 +176,7 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq d0, d16, d17",
"fcmeq d0, d17, d16",
"mvn v0.8b, v0.8b",
"ptrue p0.d, vl1",
"mov z16.d, p0/m, z0.d"
unittests/InstructionCountCI/AFP/Secondary.json
+6 -4
View File
@@ -11,23 +11,25 @@
},
"Instructions": {
"cvtpi2ps xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": [
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"scvtf v16.2s, v2.2s"
"scvtf v0.2s, v2.2s",
"mov v16.d[0], v0.d[0]"
]
},
"cvtpi2ps xmm0, mm0": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 3,
"Comment": [
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #1040]",
"scvtf v16.2s, v2.2s"
"scvtf v0.2s, v2.2s",
"mov v16.d[0], v0.d[0]"
]
}
}
unittests/InstructionCountCI/AFP/Secondary_REP.json
+5 -4
View File
@@ -47,7 +47,7 @@
]
},
"rsqrtss xmm0, xmm1": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": [
"FEAT_FPRES could make this more optimal",
"0xf3 0x0f 0x52"
@@ -55,7 +55,8 @@
"ExpectedArm64ASM": [
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s17",
"fdiv s16, s0, s1"
"fdiv s0, s0, s1",
"mov v16.s[0], v0.s[0]"
]
},
"rcpss xmm0, xmm1": {
@@ -144,7 +145,7 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq s16, s16, s17"
"fcmeq s16, s17, s16"
]
},
"cmpss xmm0, xmm1, 1": {
@@ -184,7 +185,7 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq s0, s16, s17",
"fcmeq s0, s17, s16",
"mvn v0.8b, v0.8b",
"mov v16.s[0], v0.s[0]"
]
unittests/InstructionCountCI/AFP/Secondary_REPNE.json
+2 -2
View File
@@ -136,7 +136,7 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq d16, d16, d17"
"fcmeq d16, d17, d16"
]
},
"cmpsd xmm0, xmm1, 1": {
@@ -176,7 +176,7 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq d0, d16, d17",
"fcmeq d0, d17, d16",
"mvn v0.8b, v0.8b",
"mov v16.d[0], v0.d[0]"
]
unittests/InstructionCountCI/AFP/VEX_map1.json
+7 -6
View File
@@ -30,7 +30,7 @@
]
},
"vrsqrtss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": [
"FEAT_FPRES could make this more optimal",
"Map 1 0b10 0x52 128-bit"
@@ -39,7 +39,8 @@
"mov v16.16b, v17.16b",
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s18",
"fdiv s16, s0, s1"
"fdiv s0, s0, s1",
"mov v16.s[0], v0.s[0]"
]
},
"vrcpss xmm0, xmm1, xmm2": {
@@ -61,7 +62,7 @@
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq s16, s17, s18"
"fcmeq s16, s18, s17"
]
},
"vcmpss xmm0, xmm1, xmm2, 0x01": {
@@ -105,7 +106,7 @@
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq s0, s17, s18",
"fcmeq s0, s18, s17",
"mvn v0.8b, v0.8b",
"mov v16.s[0], v0.s[0]"
]
@@ -154,7 +155,7 @@
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq d16, d17, d18"
"fcmeq d16, d18, d17"
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x01": {
@@ -198,7 +199,7 @@
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq d0, d17, d18",
"fcmeq d0, d18, d17",
"mvn v0.8b, v0.8b",
"mov v16.d[0], v0.d[0]"
]
unittests/InstructionCountCI/Secondary_REP.json
+2 -2
View File
@@ -525,7 +525,7 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq s0, s16, s17",
"fcmeq s0, s17, s16",
"mov v16.s[0], v0.s[0]"
]
},
@@ -568,7 +568,7 @@
"0xf3 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq s0, s16, s17",
"fcmeq s0, s17, s16",
"mvn v0.8b, v0.8b",
"mov v16.s[0], v0.s[0]"
]
unittests/InstructionCountCI/Secondary_REPNE.json
+2 -2
View File
@@ -366,7 +366,7 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq d0, d16, d17",
"fcmeq d0, d17, d16",
"mov v16.d[0], v0.d[0]"
]
},
@@ -409,7 +409,7 @@
"0xf2 0x0f 0xc2"
],
"ExpectedArm64ASM": [
"fcmeq d0, d16, d17",
"fcmeq d0, d17, d16",
"mvn v0.8b, v0.8b",
"mov v16.d[0], v0.d[0]"
]
unittests/InstructionCountCI/VEX_map1.json
+4 -4
View File
@@ -2394,7 +2394,7 @@
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq s0, s17, s18",
"fcmeq s0, s18, s17",
"mov v16.s[0], v0.s[0]"
]
},
@@ -2441,7 +2441,7 @@
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq s0, s17, s18",
"fcmeq s0, s18, s17",
"mvn v0.8b, v0.8b",
"mov v16.s[0], v0.s[0]"
]
@@ -2490,7 +2490,7 @@
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq d0, d17, d18",
"fcmeq d0, d18, d17",
"mov v16.d[0], v0.d[0]"
]
},
@@ -2537,7 +2537,7 @@
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq d0, d17, d18",
"fcmeq d0, d18, d17",
"mvn v0.8b, v0.8b",
"mov v16.d[0], v0.d[0]"
]