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InstcountCI: Update

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Ryan Houdek committed 2024-07-02 20:24:58 -07:00
1 parent 0d06e3e47d
commit 2d617ad173
32 files changed
+44886 -39324
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unittests/InstructionCountCI/AVX128/VEX_map1.json
+46 -46
View File
@@ -1685,22 +1685,22 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #256]",
"str q2, [x28, #240]",
"str q2, [x28, #224]",
"str q2, [x28, #208]",
"str q2, [x28, #192]",
"str q2, [x28, #176]",
"str q2, [x28, #160]",
"str q2, [x28, #144]",
"str q2, [x28, #128]",
"str q2, [x28, #112]",
"str q2, [x28, #96]",
"str q2, [x28, #80]",
"str q2, [x28, #64]",
"str q2, [x28, #48]",
"str q2, [x28, #16]",
"str q2, [x28, #32]",
"str q2, [x28, #16]"
"str q2, [x28, #48]",
"str q2, [x28, #64]",
"str q2, [x28, #80]",
"str q2, [x28, #96]",
"str q2, [x28, #112]",
"str q2, [x28, #128]",
"str q2, [x28, #144]",
"str q2, [x28, #160]",
"str q2, [x28, #176]",
"str q2, [x28, #192]",
"str q2, [x28, #208]",
"str q2, [x28, #224]",
"str q2, [x28, #240]",
"str q2, [x28, #256]"
]
},
"vzeroall": {
@@ -1726,22 +1726,22 @@
"movi v29.2d, #0x0",
"movi v30.2d, #0x0",
"movi v31.2d, #0x0",
"str q31, [x28, #256]",
"str q31, [x28, #240]",
"str q31, [x28, #224]",
"str q31, [x28, #208]",
"str q31, [x28, #192]",
"str q31, [x28, #176]",
"str q31, [x28, #160]",
"str q31, [x28, #144]",
"str q31, [x28, #128]",
"str q31, [x28, #112]",
"str q31, [x28, #96]",
"str q31, [x28, #80]",
"str q31, [x28, #64]",
"str q31, [x28, #48]",
"str q31, [x28, #16]",
"str q31, [x28, #32]",
"str q31, [x28, #16]"
"str q31, [x28, #48]",
"str q31, [x28, #64]",
"str q31, [x28, #80]",
"str q31, [x28, #96]",
"str q31, [x28, #112]",
"str q31, [x28, #128]",
"str q31, [x28, #144]",
"str q31, [x28, #160]",
"str q31, [x28, #176]",
"str q31, [x28, #192]",
"str q31, [x28, #208]",
"str q31, [x28, #224]",
"str q31, [x28, #240]",
"str q31, [x28, #256]"
]
},
"vcmpps xmm0, xmm1, xmm2, 0x00": {
@@ -2692,8 +2692,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vmovaps ymm0, ymm1": {
@@ -2703,8 +2703,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vmovapd xmm0, [rax]": {
@@ -2736,8 +2736,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vmovapd ymm0, ymm1": {
@@ -2747,8 +2747,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vmovaps [rax], xmm0": {
@@ -3473,8 +3473,8 @@
"fcsel s0, s17, s18, mi",
"mov v16.s[0], v0.s[0]",
"movi v2.2d, #0x0",
"msr nzcv, x20",
"str q2, [x28, #16]"
"str q2, [x28, #16]",
"msr nzcv, x20"
]
},
"vminsd xmm0, xmm1, xmm2": {
@@ -3489,8 +3489,8 @@
"fcsel d0, d17, d18, mi",
"mov v16.d[0], v0.d[0]",
"movi v2.2d, #0x0",
"msr nzcv, x20",
"str q2, [x28, #16]"
"str q2, [x28, #16]",
"msr nzcv, x20"
]
},
"vdivps xmm0, xmm1, xmm2": {
@@ -3693,8 +3693,8 @@
"fcsel s0, s18, s17, mi",
"mov v16.s[0], v0.s[0]",
"movi v2.2d, #0x0",
"msr nzcv, x20",
"str q2, [x28, #16]"
"str q2, [x28, #16]",
"msr nzcv, x20"
]
},
"vmaxsd xmm0, xmm1, xmm2": {
@@ -3709,8 +3709,8 @@
"fcsel d0, d18, d17, mi",
"mov v16.d[0], v0.d[0]",
"movi v2.2d, #0x0",
"msr nzcv, x20",
"str q2, [x28, #16]"
"str q2, [x28, #16]",
"msr nzcv, x20"
]
},
"vpunpckhbw xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2.json
+126 -126
View File
@@ -2577,8 +2577,8 @@
"add x1, x4, w0, sxtw #1",
"ld1 {v16.s}[3], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherdd xmm0, [xmm1*4 + rax], xmm2": {
@@ -2608,8 +2608,8 @@
"add x1, x4, w0, sxtw #2",
"ld1 {v16.s}[3], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherdd xmm0, [xmm1*8 + rax], xmm2": {
@@ -2639,8 +2639,8 @@
"add x1, x4, w0, sxtw #3",
"ld1 {v16.s}[3], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherdd ymm0, [ymm1*1 + rax], ymm2": {
@@ -2692,9 +2692,9 @@
"smov x0, v3.s[3]",
"add x1, x4, w0, sxtw",
"ld1 {v2.s}[3], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherdd ymm0, [ymm1*2 + rax], ymm2": {
@@ -2746,9 +2746,9 @@
"smov x0, v3.s[3]",
"add x1, x4, w0, sxtw #1",
"ld1 {v2.s}[3], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherdd ymm0, [ymm1*4 + rax], ymm2": {
@@ -2800,9 +2800,9 @@
"smov x0, v3.s[3]",
"add x1, x4, w0, sxtw #2",
"ld1 {v2.s}[3], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherdd ymm0, [ymm1*8 + rax], ymm2": {
@@ -2854,9 +2854,9 @@
"smov x0, v3.s[3]",
"add x1, x4, w0, sxtw #3",
"ld1 {v2.s}[3], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherdq xmm0, [xmm1*1 + rax], xmm2": {
@@ -2876,8 +2876,8 @@
"add x1, x4, w0, sxtw",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherdq xmm0, [xmm1*2 + rax], xmm2": {
@@ -2897,8 +2897,8 @@
"add x1, x4, w0, sxtw #1",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherdq xmm0, [xmm1*4 + rax], xmm2": {
@@ -2918,8 +2918,8 @@
"add x1, x4, w0, sxtw #2",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherdq xmm0, [xmm1*8 + rax], xmm2": {
@@ -2939,8 +2939,8 @@
"add x1, x4, w0, sxtw #3",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherdq ymm0, [xmm1*1 + rax], ymm2": {
@@ -2972,9 +2972,9 @@
"smov x0, v17.s[3]",
"add x1, x4, w0, sxtw",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherdq ymm0, [xmm1*2 + rax], ymm2": {
@@ -3006,9 +3006,9 @@
"smov x0, v17.s[3]",
"add x1, x4, w0, sxtw #1",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherdq ymm0, [xmm1*4 + rax], ymm2": {
@@ -3040,9 +3040,9 @@
"smov x0, v17.s[3]",
"add x1, x4, w0, sxtw #2",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherdq ymm0, [xmm1*8 + rax], ymm2": {
@@ -3074,9 +3074,9 @@
"smov x0, v17.s[3]",
"add x1, x4, w0, sxtw #3",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherqd xmm0, [xmm1*1 + rax], xmm2": {
@@ -3098,8 +3098,8 @@
"ld1 {v2.s}[1], [x1]",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqd xmm0, [xmm1*2 + rax], xmm2": {
@@ -3121,8 +3121,8 @@
"ld1 {v2.s}[1], [x1]",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqd xmm0, [xmm1*4 + rax], xmm2": {
@@ -3144,8 +3144,8 @@
"ld1 {v2.s}[1], [x1]",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqd xmm0, [xmm1*8 + rax], xmm2": {
@@ -3167,8 +3167,8 @@
"ld1 {v2.s}[1], [x1]",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqd xmm0, [ymm1*1 + rax], xmm2": {
@@ -3201,8 +3201,8 @@
"ld1 {v3.s}[3], [x1]",
"mov v16.16b, v3.16b",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqd xmm0, [ymm1*2 + rax], xmm2": {
@@ -3235,8 +3235,8 @@
"ld1 {v3.s}[3], [x1]",
"mov v16.16b, v3.16b",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqd xmm0, [ymm1*4 + rax], xmm2": {
@@ -3269,8 +3269,8 @@
"ld1 {v3.s}[3], [x1]",
"mov v16.16b, v3.16b",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqd xmm0, [ymm1*8 + rax], xmm2": {
@@ -3303,8 +3303,8 @@
"ld1 {v3.s}[3], [x1]",
"mov v16.16b, v3.16b",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqq xmm0, [xmm1*1 + rax], xmm2": {
@@ -3324,8 +3324,8 @@
"add x1, x4, x0",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqq xmm0, [xmm1*2 + rax], xmm2": {
@@ -3345,8 +3345,8 @@
"add x1, x4, x0, lsl #1",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqq xmm0, [xmm1*4 + rax], xmm2": {
@@ -3366,8 +3366,8 @@
"add x1, x4, x0, lsl #2",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqq xmm0, [xmm1*8 + rax], xmm2": {
@@ -3387,8 +3387,8 @@
"add x1, x4, x0, lsl #3",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vpgatherqq ymm0, [ymm1*1 + rax], ymm2": {
@@ -3420,9 +3420,9 @@
"mov x0, v3.d[1]",
"add x1, x4, x0",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherqq ymm0, [ymm1*2 + rax], ymm2": {
@@ -3454,9 +3454,9 @@
"mov x0, v3.d[1]",
"add x1, x4, x0, lsl #1",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherqq ymm0, [ymm1*4 + rax], ymm2": {
@@ -3488,9 +3488,9 @@
"mov x0, v3.d[1]",
"add x1, x4, x0, lsl #2",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vpgatherqq ymm0, [ymm1*8 + rax], ymm2": {
@@ -3522,9 +3522,9 @@
"mov x0, v3.d[1]",
"add x1, x4, x0, lsl #3",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherdps xmm0, [xmm1*1 + rax], xmm2": {
@@ -3554,8 +3554,8 @@
"add x1, x4, w0, sxtw",
"ld1 {v16.s}[3], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherdps xmm0, [xmm1*2 + rax], xmm2": {
@@ -3585,8 +3585,8 @@
"add x1, x4, w0, sxtw #1",
"ld1 {v16.s}[3], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherdps xmm0, [xmm1*4 + rax], xmm2": {
@@ -3616,8 +3616,8 @@
"add x1, x4, w0, sxtw #2",
"ld1 {v16.s}[3], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherdps xmm0, [xmm1*8 + rax], xmm2": {
@@ -3647,8 +3647,8 @@
"add x1, x4, w0, sxtw #3",
"ld1 {v16.s}[3], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherdps ymm0, [ymm1*1 + rax], ymm2": {
@@ -3700,9 +3700,9 @@
"smov x0, v3.s[3]",
"add x1, x4, w0, sxtw",
"ld1 {v2.s}[3], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherdps ymm0, [ymm1*2 + rax], ymm2": {
@@ -3754,9 +3754,9 @@
"smov x0, v3.s[3]",
"add x1, x4, w0, sxtw #1",
"ld1 {v2.s}[3], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherdps ymm0, [ymm1*4 + rax], ymm2": {
@@ -3808,9 +3808,9 @@
"smov x0, v3.s[3]",
"add x1, x4, w0, sxtw #2",
"ld1 {v2.s}[3], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherdps ymm0, [ymm1*8 + rax], ymm2": {
@@ -3862,9 +3862,9 @@
"smov x0, v3.s[3]",
"add x1, x4, w0, sxtw #3",
"ld1 {v2.s}[3], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherdpd xmm0, [xmm1*1 + rax], xmm2": {
@@ -3884,8 +3884,8 @@
"add x1, x4, w0, sxtw",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherdpd xmm0, [xmm1*2 + rax], xmm2": {
@@ -3905,8 +3905,8 @@
"add x1, x4, w0, sxtw #1",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherdpd xmm0, [xmm1*4 + rax], xmm2": {
@@ -3926,8 +3926,8 @@
"add x1, x4, w0, sxtw #2",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherdpd xmm0, [xmm1*8 + rax], xmm2": {
@@ -3947,8 +3947,8 @@
"add x1, x4, w0, sxtw #3",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherdpd ymm0, [xmm1*1 + rax], ymm2": {
@@ -3980,9 +3980,9 @@
"smov x0, v17.s[3]",
"add x1, x4, w0, sxtw",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherdpd ymm0, [xmm1*2 + rax], ymm2": {
@@ -4014,9 +4014,9 @@
"smov x0, v17.s[3]",
"add x1, x4, w0, sxtw #1",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherdpd ymm0, [xmm1*4 + rax], ymm2": {
@@ -4048,9 +4048,9 @@
"smov x0, v17.s[3]",
"add x1, x4, w0, sxtw #2",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherdpd ymm0, [xmm1*8 + rax], ymm2": {
@@ -4082,9 +4082,9 @@
"smov x0, v17.s[3]",
"add x1, x4, w0, sxtw #3",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherqps xmm0, [xmm1*1 + rax], xmm2": {
@@ -4106,8 +4106,8 @@
"ld1 {v2.s}[1], [x1]",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqps xmm0, [xmm1*2 + rax], xmm2": {
@@ -4129,8 +4129,8 @@
"ld1 {v2.s}[1], [x1]",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqps xmm0, [xmm1*4 + rax], xmm2": {
@@ -4152,8 +4152,8 @@
"ld1 {v2.s}[1], [x1]",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqps xmm0, [xmm1*8 + rax], xmm2": {
@@ -4175,8 +4175,8 @@
"ld1 {v2.s}[1], [x1]",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqps xmm0, [ymm1*1 + rax], xmm2": {
@@ -4209,8 +4209,8 @@
"ld1 {v3.s}[3], [x1]",
"mov v16.16b, v3.16b",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqps xmm0, [ymm1*2 + rax], xmm2": {
@@ -4243,8 +4243,8 @@
"ld1 {v3.s}[3], [x1]",
"mov v16.16b, v3.16b",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqps xmm0, [ymm1*4 + rax], xmm2": {
@@ -4277,8 +4277,8 @@
"ld1 {v3.s}[3], [x1]",
"mov v16.16b, v3.16b",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqps xmm0, [ymm1*8 + rax], xmm2": {
@@ -4311,8 +4311,8 @@
"ld1 {v3.s}[3], [x1]",
"mov v16.16b, v3.16b",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqpd xmm0, [xmm1*1 + rax], xmm2": {
@@ -4332,8 +4332,8 @@
"add x1, x4, x0",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqpd xmm0, [xmm1*2 + rax], xmm2": {
@@ -4353,8 +4353,8 @@
"add x1, x4, x0, lsl #1",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqpd xmm0, [xmm1*4 + rax], xmm2": {
@@ -4374,8 +4374,8 @@
"add x1, x4, x0, lsl #2",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqpd xmm0, [xmm1*8 + rax], xmm2": {
@@ -4395,8 +4395,8 @@
"add x1, x4, x0, lsl #3",
"ld1 {v16.d}[1], [x1]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q18, [x28, #16]"
"str q18, [x28, #16]",
"str q18, [x28, #48]"
]
},
"vgatherqpd ymm0, [ymm1*1 + rax], ymm2": {
@@ -4428,9 +4428,9 @@
"mov x0, v3.d[1]",
"add x1, x4, x0",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherqpd ymm0, [ymm1*2 + rax], ymm2": {
@@ -4462,9 +4462,9 @@
"mov x0, v3.d[1]",
"add x1, x4, x0, lsl #1",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherqpd ymm0, [ymm1*4 + rax], ymm2": {
@@ -4496,9 +4496,9 @@
"mov x0, v3.d[1]",
"add x1, x4, x0, lsl #2",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vgatherqpd ymm0, [ymm1*8 + rax], ymm2": {
@@ -4530,9 +4530,9 @@
"mov x0, v3.d[1]",
"add x1, x4, x0, lsl #3",
"ld1 {v2.d}[1], [x1]",
"str q2, [x28, #16]",
"movi v18.2d, #0x0",
"str q18, [x28, #48]",
"str q2, [x28, #16]"
"str q18, [x28, #48]"
]
},
"vfmaddsub132ps xmm0, xmm1, xmm2": {
unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+260 -260
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json
+6 -6
View File
@@ -620,9 +620,9 @@
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w26, w5, w7",
"tst w26, w26",
"mov x4, x26"
"bic w4, w5, w7",
"mov x26, x4",
"tst w4, w4"
]
},
"andn rax, rbx, rcx": {
@@ -631,9 +631,9 @@
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x26, x5, x7",
"tst x26, x26",
"mov x4, x26"
"bic x4, x5, x7",
"mov x26, x4",
"tst x4, x4"
]
},
"bzhi eax, ebx, ecx": {
unittests/InstructionCountCI/AVX128/VEX_map3.json
+56 -56
View File
@@ -927,8 +927,8 @@
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"str q17, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q17, [x28, #16]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00000001b": {
@@ -947,8 +947,8 @@
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"str q17, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q17, [x28, #16]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00000011b": {
@@ -968,8 +968,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00010001b": {
@@ -989,8 +989,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q2, [x28, #16]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00010011b": {
@@ -1010,8 +1010,8 @@
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q18, [x28, #16]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00100001b": {
@@ -1030,8 +1030,8 @@
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q18, [x28, #16]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00100011b": {
@@ -1051,8 +1051,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00110001b": {
@@ -1073,8 +1073,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"str q2, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q2, [x28, #16]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00110011b": {
@@ -1146,8 +1146,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10000001b": {
@@ -1168,8 +1168,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q2, [x28, #16]"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10000011b": {
@@ -2166,8 +2166,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q2, [x28, #16]"
]
},
"vpalignr xmm0, xmm1, xmm2, 1": {
@@ -2211,8 +2211,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"str q2, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q2, [x28, #16]"
]
},
"vpalignr ymm0, ymm1, ymm2, 1": {
@@ -2389,8 +2389,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q2, [x28, #16]"
]
},
"vinsertf128 ymm0, ymm1, xmm2, 1": {
@@ -2399,8 +2399,8 @@
"Map 3 0b01 0x18 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q18, [x28, #16]"
]
},
"vextractf128 xmm0, ymm1, 0": {
@@ -2410,8 +2410,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vextractf128 xmm0, ymm1, 1": {
@@ -2732,8 +2732,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q2, [x28, #16]"
]
},
"vinserti128 ymm0, ymm1, xmm2, 1": {
@@ -2742,8 +2742,8 @@
"Map 3 0b01 0x38 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q18, [x28, #16]"
]
},
"vextracti128 xmm0, ymm1, 0": {
@@ -2753,8 +2753,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vextracti128 xmm0, ymm1, 1": {
@@ -3516,8 +3516,8 @@
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"str q17, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q17, [x28, #16]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00000001b": {
@@ -3536,8 +3536,8 @@
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"str q17, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q17, [x28, #16]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00000011b": {
@@ -3557,8 +3557,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00010001b": {
@@ -3578,8 +3578,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q2, [x28, #16]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00010011b": {
@@ -3599,8 +3599,8 @@
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q18, [x28, #16]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00100001b": {
@@ -3619,8 +3619,8 @@
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"str q18, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q18, [x28, #16]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00100011b": {
@@ -3640,8 +3640,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00110001b": {
@@ -3662,8 +3662,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #48]",
"str q2, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q2, [x28, #16]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00110011b": {
@@ -3735,8 +3735,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10000001b": {
@@ -3757,8 +3757,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v18.16b"
"mov v16.16b, v18.16b",
"str q2, [x28, #16]"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10000011b": {
unittests/InstructionCountCI/AVX128/VEX_map_group.json
+40 -40
View File
@@ -18,8 +18,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsrlw xmm0, xmm1, 15": {
@@ -51,8 +51,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsrlw ymm0, ymm1, 15": {
@@ -86,8 +86,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsraw xmm0, xmm1, 15": {
@@ -119,8 +119,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsraw ymm0, ymm1, 15": {
@@ -154,8 +154,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsllw xmm0, xmm1, 15": {
@@ -187,8 +187,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsllw ymm0, ymm1, 15": {
@@ -222,8 +222,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsrld xmm0, xmm1, 31": {
@@ -255,8 +255,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsrld ymm0, ymm1, 31": {
@@ -290,8 +290,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsrad xmm0, xmm1, 31": {
@@ -323,8 +323,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsrad ymm0, ymm1, 31": {
@@ -358,8 +358,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpslld xmm0, xmm1, 31": {
@@ -391,8 +391,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpslld ymm0, ymm1, 31": {
@@ -426,8 +426,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsrlq xmm0, xmm1, 63": {
@@ -459,8 +459,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsrlq ymm0, ymm1, 63": {
@@ -494,8 +494,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsrldq xmm0, xmm1, 15": {
@@ -526,8 +526,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsrldq ymm0, ymm1, 15": {
@@ -559,8 +559,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsllq xmm0, xmm1, 63": {
@@ -592,8 +592,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpsllq ymm0, ymm1, 63": {
@@ -627,8 +627,8 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpslldq xmm0, xmm1, 15": {
@@ -659,8 +659,8 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #32]",
"str q2, [x28, #16]",
"mov v16.16b, v17.16b"
"mov v16.16b, v17.16b",
"str q2, [x28, #16]"
]
},
"vpslldq ymm0, ymm1, 15": {
unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json
+1 -2
View File
@@ -1045,11 +1045,10 @@
"mov rax, gs:0x100",
"mov rbx, gs:0x14"
],
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"ldr x20, [x28, #960]",
"ldr x4, [x20, #256]",
"ldr x20, [x28, #960]",
"ldur x7, [x20, #20]"
]
}
unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json
+1 -2
View File
@@ -323,11 +323,10 @@
"mov eax, gs:0x100",
"mov ebx, gs:0x14"
],
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"ExpectedArm64ASM": [
"ldr w20, [x28, #960]",
"ldr w4, [x20, #256]",
"ldr w20, [x28, #960]",
"ldr w7, [x20, #20]"
]
}
unittests/InstructionCountCI/FEXOpt/MultiInst.json
+104 -103
View File
@@ -69,11 +69,11 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldrb w21, [x10]",
"strb w21, [x11]",
"strb w20, [x28, #986]",
"ldrb w20, [x10]",
"strb w20, [x11]",
"add x10, x10, #0x1 (1)",
"add x11, x11, #0x1 (1)",
"strb w20, [x28, #986]"
"add x11, x11, #0x1 (1)"
]
},
"positive movsw": {
@@ -88,11 +88,11 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldrh w21, [x10]",
"strh w21, [x11]",
"strb w20, [x28, #986]",
"ldrh w20, [x10]",
"strh w20, [x11]",
"add x10, x10, #0x2 (2)",
"add x11, x11, #0x2 (2)",
"strb w20, [x28, #986]"
"add x11, x11, #0x2 (2)"
]
},
"positive movsd": {
@@ -107,11 +107,11 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldr w21, [x10]",
"str w21, [x11]",
"strb w20, [x28, #986]",
"ldr w20, [x10]",
"str w20, [x11]",
"add x10, x10, #0x4 (4)",
"add x11, x11, #0x4 (4)",
"strb w20, [x28, #986]"
"add x11, x11, #0x4 (4)"
]
},
"positive movsq": {
@@ -126,11 +126,11 @@
],
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldr x21, [x10]",
"str x21, [x11]",
"strb w20, [x28, #986]",
"ldr x20, [x10]",
"str x20, [x11]",
"add x10, x10, #0x8 (8)",
"add x11, x11, #0x8 (8)",
"strb w20, [x28, #986]"
"add x11, x11, #0x8 (8)"
]
},
"negative movsb": {
@@ -145,11 +145,11 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ldrb w21, [x10]",
"strb w21, [x11]",
"strb w20, [x28, #986]",
"ldrb w20, [x10]",
"strb w20, [x11]",
"sub x10, x10, #0x1 (1)",
"sub x11, x11, #0x1 (1)",
"strb w20, [x28, #986]"
"sub x11, x11, #0x1 (1)"
]
},
"negative movsw": {
@@ -164,11 +164,11 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ldrh w21, [x10]",
"strh w21, [x11]",
"strb w20, [x28, #986]",
"ldrh w20, [x10]",
"strh w20, [x11]",
"sub x10, x10, #0x2 (2)",
"sub x11, x11, #0x2 (2)",
"strb w20, [x28, #986]"
"sub x11, x11, #0x2 (2)"
]
},
"negative movsd": {
@@ -183,11 +183,11 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ldr w21, [x10]",
"str w21, [x11]",
"strb w20, [x28, #986]",
"ldr w20, [x10]",
"str w20, [x11]",
"sub x10, x10, #0x4 (4)",
"sub x11, x11, #0x4 (4)",
"strb w20, [x28, #986]"
"sub x11, x11, #0x4 (4)"
]
},
"negative movsq": {
@@ -202,11 +202,11 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ldr x21, [x10]",
"str x21, [x11]",
"strb w20, [x28, #986]",
"ldr x20, [x10]",
"str x20, [x11]",
"sub x10, x10, #0x8 (8)",
"sub x11, x11, #0x8 (8)",
"strb w20, [x28, #986]"
"sub x11, x11, #0x8 (8)"
]
},
"positive rep movsb": {
@@ -222,6 +222,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -262,7 +263,6 @@
"add x23, x1, x2",
"mov x10, x23",
"mov x11, x22",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -279,6 +279,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -319,7 +320,6 @@
"add x23, x1, x2, lsl #1",
"mov x10, x23",
"mov x11, x22",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -336,6 +336,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -376,7 +377,6 @@
"add x23, x1, x2, lsl #2",
"mov x10, x23",
"mov x11, x22",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -393,6 +393,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -433,7 +434,6 @@
"add x23, x1, x2, lsl #3",
"mov x10, x23",
"mov x11, x22",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -449,6 +449,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -489,12 +490,11 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"sub x22, x0, x2",
"sub x23, x1, x2",
"mov x10, x23",
"mov x11, x22",
"mov w5, #0x0",
"strb w20, [x28, #986]"
"sub x20, x0, x2",
"sub x21, x1, x2",
"mov x10, x21",
"mov x11, x20",
"mov w5, #0x0"
]
},
"negative rep movsw": {
@@ -509,6 +509,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -549,12 +550,11 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"sub x22, x0, x2, lsl #1",
"sub x23, x1, x2, lsl #1",
"mov x10, x23",
"mov x11, x22",
"mov w5, #0x0",
"strb w20, [x28, #986]"
"sub x20, x0, x2, lsl #1",
"sub x21, x1, x2, lsl #1",
"mov x10, x21",
"mov x11, x20",
"mov w5, #0x0"
]
},
"negative rep movsd": {
@@ -569,6 +569,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -609,12 +610,11 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"sub x22, x0, x2, lsl #2",
"sub x23, x1, x2, lsl #2",
"mov x10, x23",
"mov x11, x22",
"mov w5, #0x0",
"strb w20, [x28, #986]"
"sub x20, x0, x2, lsl #2",
"sub x21, x1, x2, lsl #2",
"mov x10, x21",
"mov x11, x20",
"mov w5, #0x0"
]
},
"negative rep movsq": {
@@ -629,6 +629,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"mov x2, x10",
@@ -669,12 +670,11 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x5",
"sub x22, x0, x2, lsl #3",
"sub x23, x1, x2, lsl #3",
"mov x10, x23",
"mov x11, x22",
"mov w5, #0x0",
"strb w20, [x28, #986]"
"sub x20, x0, x2, lsl #3",
"sub x21, x1, x2, lsl #3",
"mov x10, x21",
"mov x11, x20",
"mov w5, #0x0"
]
},
"positive rep stosb": {
@@ -690,13 +690,14 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"uxtb w22, w4",
"strb w21, [x28, #986]",
"uxtb w21, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x20 (32)",
"tbnz x0, #63, #+0x3c",
"dup v1.16b, w22",
"dup v1.16b, w21",
"sub x0, x0, #0x20 (32)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #32",
@@ -712,11 +713,10 @@
"tbz x0, #63, #-0x8",
"add x0, x0, #0x20 (32)",
"cbz x0, #+0x10",
"strb w22, [x1], #1",
"strb w21, [x1], #1",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -733,13 +733,14 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"uxth w22, w4",
"strb w21, [x28, #986]",
"uxth w21, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x10 (16)",
"tbnz x0, #63, #+0x3c",
"dup v1.8h, w22",
"dup v1.8h, w21",
"sub x0, x0, #0x10 (16)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #32",
@@ -755,11 +756,10 @@
"tbz x0, #63, #-0x8",
"add x0, x0, #0x10 (16)",
"cbz x0, #+0x10",
"strh w22, [x1], #2",
"strh w21, [x1], #2",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5, lsl #1",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -776,13 +776,14 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov w22, w4",
"strb w21, [x28, #986]",
"mov w21, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x8 (8)",
"tbnz x0, #63, #+0x3c",
"dup v1.4s, w22",
"dup v1.4s, w21",
"sub x0, x0, #0x8 (8)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #32",
@@ -798,11 +799,10 @@
"tbz x0, #63, #-0x8",
"add x0, x0, #0x8 (8)",
"cbz x0, #+0x10",
"str w22, [x1], #4",
"str w21, [x1], #4",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5, lsl #2",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -819,6 +819,7 @@
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"strb w21, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x58",
@@ -844,7 +845,6 @@
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x5, lsl #3",
"strb w21, [x28, #986]",
"mov x5, x20"
]
},
@@ -860,14 +860,15 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"uxtb w21, w4",
"strb w20, [x28, #986]",
"uxtb w20, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x60",
"sub x1, x1, #0x1f (31)",
"sub x0, x0, #0x20 (32)",
"tbnz x0, #63, #+0x3c",
"dup v1.16b, w21",
"dup v1.16b, w20",
"sub x0, x0, #0x20 (32)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #-32",
@@ -884,12 +885,11 @@
"add x0, x0, #0x20 (32)",
"cbz x0, #+0x14",
"add x1, x1, #0x1f (31)",
"strb w21, [x1], #-1",
"strb w20, [x1], #-1",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5",
"mov w5, #0x0",
"strb w20, [x28, #986]"
"mov w5, #0x0"
]
},
"negative rep stosw": {
@@ -904,14 +904,15 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"uxth w21, w4",
"strb w20, [x28, #986]",
"uxth w20, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x60",
"sub x1, x1, #0x1e (30)",
"sub x0, x0, #0x10 (16)",
"tbnz x0, #63, #+0x3c",
"dup v1.8h, w21",
"dup v1.8h, w20",
"sub x0, x0, #0x10 (16)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #-32",
@@ -928,12 +929,11 @@
"add x0, x0, #0x10 (16)",
"cbz x0, #+0x14",
"add x1, x1, #0x1e (30)",
"strh w21, [x1], #-2",
"strh w20, [x1], #-2",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5, lsl #1",
"mov w5, #0x0",
"strb w20, [x28, #986]"
"mov w5, #0x0"
]
},
"negative rep stosd": {
@@ -948,14 +948,15 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"mov w21, w4",
"strb w20, [x28, #986]",
"mov w20, w4",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x60",
"sub x1, x1, #0x1c (28)",
"sub x0, x0, #0x8 (8)",
"tbnz x0, #63, #+0x3c",
"dup v1.4s, w21",
"dup v1.4s, w20",
"sub x0, x0, #0x8 (8)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #-32",
@@ -972,12 +973,11 @@
"add x0, x0, #0x8 (8)",
"cbz x0, #+0x14",
"add x1, x1, #0x1c (28)",
"str w21, [x1], #-4",
"str w20, [x1], #-4",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5, lsl #2",
"mov w5, #0x0",
"strb w20, [x28, #986]"
"mov w5, #0x0"
]
},
"negative rep stosq": {
@@ -992,6 +992,7 @@
],
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"strb w20, [x28, #986]",
"mov x0, x5",
"mov x1, x11",
"cbz x0, #+0x60",
@@ -1019,12 +1020,11 @@
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"sub x11, x11, x5, lsl #3",
"mov w5, #0x0",
"strb w20, [x28, #986]"
"mov w5, #0x0"
]
},
"Sekiro spill block": {
"ExpectedInstructionCount": 147,
"ExpectedInstructionCount": 148,
"Comment": [
"This block of code came from the settings screen when it loaded",
"It was originally at RIP: 0x14232cca0 and has been deobfuscated"
@@ -1173,8 +1173,7 @@
"ldr w11, [x6, #32]",
"mov w20, #0x13",
"mul w4, w5, w20",
"mov w21, w5",
"str w21, [x8, #104]",
"str w5, [x8, #104]",
"mov w21, #0x1000000",
"add w4, w4, w21",
"lsr w4, w4, #25",
@@ -1259,31 +1258,33 @@
"sub w17, w17, w14",
"mov w20, w17",
"str w20, [x4, #20]",
"ldr w4, [x8, #112]",
"ldr w20, [x8, #112]",
"mov x21, x4",
"mov x4, x20",
"lsl w15, w15, #26",
"sub w4, w4, w15",
"sub w4, w20, w15",
"lsl w7, w7, #25",
"mov w20, w4",
"str w20, [x10, #24]",
"str w20, [x21, #24]",
"ldr w4, [x8, #120]",
"sub w4, w4, w7",
"lsl w11, w11, #26",
"mov w20, w4",
"str w20, [x10, #28]",
"str w20, [x21, #28]",
"ldr w4, [x8]",
"sub w4, w4, w11",
"mov w20, w4",
"str w20, [x10, #32]",
"mov w4, w5",
"and w4, w4, #0xfe000000",
"str w20, [x21, #32]",
"mov x4, x5",
"and w4, w5, #0xfe000000",
"sub w5, w5, w4",
"mov w20, w5",
"str w20, [x10, #36]",
"str w20, [x21, #36]",
"mvn w27, w8",
"adds x26, x8, #0x18 (24)",
"mov x8, x26",
"ldr x29, [x8]",
"add x8, x8, #0x8 (8)",
"ldr x29, [x26]",
"add x8, x26, #0x8 (8)",
"ldr x19, [x8]",
"add x8, x8, #0x8 (8)",
"ldr x17, [x8]",
unittests/InstructionCountCI/FEXOpt/libnss.json
+35 -34
View File
@@ -16,7 +16,7 @@
"Comment": [],
"Instructions": {
"libnss3 sha": {
"ExpectedInstructionCount": 2366,
"ExpectedInstructionCount": 2367,
"Comment": [
"This block of code comes from libnss3 which causes panic spilling in FEX's RA.",
"This code is hit in steamwebhelper calling in to this function.",
@@ -206,7 +206,7 @@
"ldr q22, [x11, #32]",
"ldr q21, [x11, #48]",
"mov v19.16b, v16.16b",
"ext v19.16b, v18.16b, v19.16b, #8",
"ext v19.16b, v18.16b, v16.16b, #8",
"mov v18.d[1], v16.d[1]",
"mov w20, #0x1000",
"movk w20, #0x1, lsl #16",
@@ -230,7 +230,7 @@
"unimplemented (Unimplemented)",
"mov w21, v19.s[1]",
"mov w22, v19.s[0]",
"mov w23, v20.s[1]",
"mov w23, v18.s[1]",
"and w24, w21, w22",
"bic w23, w23, w21",
"eor w23, w24, w23",
@@ -240,11 +240,11 @@
"add w23, w23, w24",
"mov w24, v16.s[0]",
"add w23, w23, w24",
"mov w24, v20.s[0]",
"mov w24, v18.s[0]",
"add w23, w23, w24",
"mov w24, v19.s[3]",
"mov w25, v19.s[2]",
"mov w30, v20.s[3]",
"mov w30, v18.s[3]",
"and w18, w25, w30",
"orr w30, w25, w30",
"and w30, w24, w30",
@@ -254,7 +254,7 @@
"eor w18, w18, w24, ror #13",
"eor w18, w18, w24, ror #22",
"add w30, w30, w18",
"mov w18, v20.s[2]",
"mov w18, v18.s[2]",
"add w23, w23, w18",
"and w21, w23, w21",
"bic w22, w22, w23",
@@ -265,7 +265,7 @@
"add w21, w21, w22",
"mov w22, v16.s[1]",
"add w21, w21, w22",
"mov w22, v20.s[1]",
"mov w22, v18.s[1]",
"add w21, w21, w22",
"and w22, w24, w25",
"orr w24, w24, w25",
@@ -276,9 +276,9 @@
"eor w24, w24, w30, ror #13",
"eor w24, w24, w30, ror #22",
"add w22, w22, w24",
"mov w24, v20.s[3]",
"mov w24, v18.s[3]",
"add w21, w21, w24",
"mov v4.16b, v20.16b",
"mov v4.16b, v18.16b",
"mov v4.s[3], w22",
"mov v4.s[2], w30",
"mov v4.s[1], w21",
@@ -289,7 +289,7 @@
"tbl v16.16b, {v16.16b}, v4.16b",
"mov w21, v20.s[1]",
"mov w22, v20.s[0]",
"mov w23, v17.s[1]",
"mov w23, v19.s[1]",
"and w24, w21, w22",
"bic w23, w23, w21",
"eor w23, w24, w23",
@@ -299,11 +299,11 @@
"add w23, w23, w24",
"mov w24, v16.s[0]",
"add w23, w23, w24",
"mov w24, v17.s[0]",
"mov w24, v19.s[0]",
"add w23, w23, w24",
"mov w24, v20.s[3]",
"mov w25, v20.s[2]",
"mov w30, v17.s[3]",
"mov w30, v19.s[3]",
"and w18, w25, w30",
"orr w30, w25, w30",
"and w30, w24, w30",
@@ -313,7 +313,7 @@
"eor w18, w18, w24, ror #13",
"eor w18, w18, w24, ror #22",
"add w30, w30, w18",
"mov w18, v17.s[2]",
"mov w18, v19.s[2]",
"add w23, w23, w18",
"and w21, w23, w21",
"bic w22, w22, w23",
@@ -324,7 +324,7 @@
"add w21, w21, w22",
"mov w22, v16.s[1]",
"add w21, w21, w22",
"mov w22, v17.s[1]",
"mov w22, v19.s[1]",
"add w21, w21, w22",
"and w22, w24, w25",
"orr w24, w24, w25",
@@ -335,16 +335,16 @@
"eor w24, w24, w30, ror #13",
"eor w24, w24, w30, ror #22",
"add w22, w22, w24",
"mov w24, v17.s[3]",
"mov w24, v19.s[3]",
"add w21, w21, w24",
"mov v5.16b, v17.16b",
"mov v5.16b, v19.16b",
"mov v5.s[3], w22",
"mov v5.s[2], w30",
"mov v5.s[1], w21",
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v21.16b",
"ext v16.16b, v22.16b, v16.16b, #4",
"ext v16.16b, v22.16b, v21.16b, #4",
"add v24.4s, v24.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v21.s[2]",
@@ -499,7 +499,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v24.16b",
"ext v16.16b, v21.16b, v16.16b, #4",
"ext v16.16b, v21.16b, v24.16b, #4",
"add v23.4s, v23.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v24.s[2]",
@@ -654,7 +654,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v23.16b",
"ext v16.16b, v24.16b, v16.16b, #4",
"ext v16.16b, v24.16b, v23.16b, #4",
"add v22.4s, v22.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v23.s[2]",
@@ -809,7 +809,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v22.16b",
"ext v16.16b, v23.16b, v16.16b, #4",
"ext v16.16b, v23.16b, v22.16b, #4",
"add v21.4s, v21.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v22.s[2]",
@@ -964,7 +964,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v21.16b",
"ext v16.16b, v22.16b, v16.16b, #4",
"ext v16.16b, v22.16b, v21.16b, #4",
"add v24.4s, v24.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v21.s[2]",
@@ -1119,7 +1119,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v24.16b",
"ext v16.16b, v21.16b, v16.16b, #4",
"ext v16.16b, v21.16b, v24.16b, #4",
"add v23.4s, v23.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v24.s[2]",
@@ -1274,7 +1274,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v23.16b",
"ext v16.16b, v24.16b, v16.16b, #4",
"ext v16.16b, v24.16b, v23.16b, #4",
"add v22.4s, v22.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v23.s[2]",
@@ -1429,7 +1429,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v22.16b",
"ext v16.16b, v23.16b, v16.16b, #4",
"ext v16.16b, v23.16b, v22.16b, #4",
"add v21.4s, v21.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v22.s[2]",
@@ -1584,7 +1584,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v21.16b",
"ext v16.16b, v22.16b, v16.16b, #4",
"ext v16.16b, v22.16b, v21.16b, #4",
"add v24.4s, v24.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v21.s[2]",
@@ -1739,7 +1739,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v24.16b",
"ext v16.16b, v21.16b, v16.16b, #4",
"ext v16.16b, v21.16b, v24.16b, #4",
"add v23.4s, v23.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v24.s[2]",
@@ -1894,7 +1894,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v23.16b",
"ext v16.16b, v24.16b, v16.16b, #4",
"ext v16.16b, v24.16b, v23.16b, #4",
"add v22.4s, v22.4s, v16.4s",
"ldr q16, [x29, x20, sxtx]",
"mov w21, v23.s[2]",
@@ -2049,7 +2049,7 @@
"mov v17.16b, v5.16b",
"mov v17.s[0], w23",
"mov v16.16b, v22.16b",
"ext v16.16b, v23.16b, v16.16b, #4",
"ext v16.16b, v23.16b, v22.16b, #4",
"ldr q5, [x29, x20, sxtx]",
"add v23.4s, v23.4s, v5.4s",
"add v21.4s, v21.4s, v16.4s",
@@ -2219,7 +2219,7 @@
"eor w23, w23, w20, ror #11",
"eor w23, w23, w20, ror #25",
"add w22, w22, w23",
"mov w23, v16.s[0]",
"mov w23, v23.s[0]",
"add w22, w22, w23",
"mov w23, v20.s[0]",
"add w22, w22, w23",
@@ -2244,7 +2244,7 @@
"eor w21, w21, w22, ror #11",
"eor w21, w21, w22, ror #25",
"add w20, w20, w21",
"mov w21, v16.s[1]",
"mov w21, v23.s[1]",
"add w20, w20, w21",
"mov w21, v20.s[1]",
"add w20, w20, w21",
@@ -2333,7 +2333,7 @@
"eor w23, w23, w20, ror #11",
"eor w23, w23, w20, ror #25",
"add w22, w22, w23",
"mov w23, v16.s[0]",
"mov w23, v22.s[0]",
"add w22, w22, w23",
"mov w23, v20.s[0]",
"add w22, w22, w23",
@@ -2358,7 +2358,7 @@
"eor w21, w21, w22, ror #11",
"eor w21, w21, w22, ror #25",
"add w20, w20, w21",
"mov w21, v16.s[1]",
"mov w21, v22.s[1]",
"add w20, w20, w21",
"mov w21, v20.s[1]",
"add w20, w20, w21",
@@ -2447,7 +2447,7 @@
"eor w23, w23, w20, ror #11",
"eor w23, w23, w20, ror #25",
"add w22, w22, w23",
"mov w23, v16.s[0]",
"mov w23, v21.s[0]",
"add w22, w22, w23",
"mov w23, v20.s[0]",
"add w22, w22, w23",
@@ -2472,7 +2472,7 @@
"eor w21, w21, w22, ror #11",
"eor w21, w21, w22, ror #25",
"add w20, w20, w21",
"mov w21, v16.s[1]",
"mov w21, v21.s[1]",
"add w20, w20, w21",
"mov w21, v20.s[1]",
"add w20, w20, w21",
@@ -2555,6 +2555,7 @@
"tbl v20.16b, {v20.16b}, v2.16b",
"tbl v17.16b, {v17.16b}, v3.16b",
"mov v16.16b, v17.16b",
"mov v16.16b, v17.16b",
"mov v16.d[1], v20.d[1]",
"ext v20.16b, v17.16b, v20.16b, #8",
"str q16, [x11, #256]",
unittests/InstructionCountCI/FlagM/FlagOpts.json
+5 -6
View File
@@ -95,9 +95,9 @@
"ExpectedArm64ASM": [
"adds x4, x4, x7",
"cset w20, hs",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -124,9 +124,9 @@
"subs x4, x4, x7",
"cfinv",
"cset w20, hs",
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -263,16 +263,15 @@
]
},
"AND use only PF": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"x86Insts": [
"and eax, ebx",
"setp cl",
"test cl, cl"
],
"ExpectedArm64ASM": [
"and w26, w4, w7",
"mov x4, x26",
"eor w20, w26, w26, lsr #4",
"and w4, w4, w7",
"eor w20, w4, w4, lsr #4",
"eor w20, w20, w20, lsr #2",
"eon w20, w20, w20, lsr #1",
"and x20, x20, #0x1",
unittests/InstructionCountCI/FlagM/HotBlocks.json
+18 -16
View File
@@ -27,7 +27,7 @@
"mov w4, #0x1",
"ldaddal x4, x4, [x5]",
"mov x6, x4",
"and w6, w6, #0x1f",
"and w6, w4, #0x1f",
"add x6, x6, #0x1 (1)",
"lsl x6, x6, #6",
"eor w27, w6, w5",
@@ -81,11 +81,11 @@
"mov w10, w5",
"mov x6, x9",
"mov x4, x7",
"ldr s18, [x6]",
"add x4, x4, #0x20 (32)",
"ldr s18, [x9]",
"add x4, x7, #0x20 (32)",
"fmul s0, s18, s16",
"mov v18.s[0], v0.s[0]",
"add x6, x6, #0x20 (32)",
"add x6, x9, #0x20 (32)",
"ldur s2, [x4, #-32]",
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
@@ -139,9 +139,9 @@
"fadd s0, s18, s2",
"mov v18.s[0], v0.s[0]",
"stur s18, [x4, #-4]",
"mov x27, x10",
"subs w26, w10, #0x1 (1)",
"cfinv",
"mov x27, x10",
"mov x10, x26"
]
},
@@ -168,7 +168,7 @@
]
},
"bytemark data xor loop": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 15,
"Comment": [
"Saw this in bytemark"
],
@@ -187,15 +187,17 @@
"mov x6, x4",
"mov x5, x4",
"mov x19, x10",
"add x4, x4, #0x1 (1)",
"lsr x6, x6, #6",
"and w5, w5, #0x3f",
"lsl x19, x19, x5",
"ldr x20, [x7, x6, sxtx #3]",
"eor x20, x20, x19",
"str x20, [x7, x6, sxtx #3]",
"eor w27, w11, w4",
"subs x26, x11, x4",
"add x20, x4, #0x1 (1)",
"mov x21, x4",
"mov x4, x20",
"lsr x6, x21, #6",
"and w5, w21, #0x3f",
"lsl x19, x10, x5",
"ldr x21, [x7, x6, sxtx #3]",
"eor x21, x21, x19",
"str x21, [x7, x6, sxtx #3]",
"eor w27, w11, w20",
"subs x26, x11, x20",
"cfinv"
]
},
@@ -213,7 +215,7 @@
"ExpectedArm64ASM": [
"ldr x17, [x10, x13, sxtx #3]",
"mov x15, x13",
"orr x15, x15, #0x1",
"orr x15, x13, #0x1",
"ldr x20, [x10, x15, sxtx #3]",
"eor w27, w17, w20",
"subs x26, x17, x20",
unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json
+415 -346
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json
+4 -4
View File
@@ -58,10 +58,10 @@
"mov w10, w5",
"mov x6, x9",
"mov x4, x7",
"ldr s18, [x6]",
"add x4, x4, #0x20 (32)",
"ldr s18, [x9]",
"add x4, x7, #0x20 (32)",
"fmul s18, s18, s16",
"add x6, x6, #0x20 (32)",
"add x6, x9, #0x20 (32)",
"ldur s2, [x4, #-32]",
"fadd s18, s18, s2",
"stur s18, [x4, #-32]",
@@ -100,9 +100,9 @@
"ldur s2, [x4, #-4]",
"fadd s18, s18, s2",
"stur s18, [x4, #-4]",
"mov x27, x10",
"subs w26, w10, #0x1 (1)",
"cfinv",
"mov x27, x10",
"mov x10, x26"
]
}
unittests/InstructionCountCI/FlagM/Primary.json
+157 -165
View File
@@ -105,39 +105,35 @@
]
},
"add al, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "0x04",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmn w0, w20, lsl #24",
"add w26, w4, #0x1 (1)",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #8"
]
},
"add ax, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "0x05",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x1 (1)",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"add eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x05",
"ExpectedArm64ASM": [
"adds w26, w4, #0x1 (1)",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mov x4, x26"
]
},
@@ -145,8 +141,8 @@
"ExpectedInstructionCount": 3,
"Comment": "0x05",
"ExpectedArm64ASM": [
"adds x26, x4, #0x1 (1)",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mov x4, x26"
]
},
@@ -225,18 +221,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr w26, w7, w5",
"tst w26, w26",
"mov x7, x26"
"orr w7, w7, w5",
"mov x26, x7",
"tst w7, w7"
]
},
"or rbx, rcx": {
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr x26, x7, x5",
"tst x26, x26",
"mov x7, x26"
"orr x7, x7, x5",
"mov x26, x7",
"tst x7, x7"
]
},
"db 0x0A, 0xcb": {
@@ -270,9 +266,9 @@
"or ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr w26, w5, w7",
"tst w26, w26",
"mov x5, x26"
"orr w5, w5, w7",
"mov x26, x5",
"tst w5, w5"
]
},
"db 0x48, 0x0B, 0xcb": {
@@ -282,9 +278,9 @@
"or rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr x26, x5, x7",
"tst x26, x26",
"mov x5, x26"
"orr x5, x5, x7",
"mov x26, x5",
"tst x5, x5"
]
},
"or al, 1": {
@@ -309,18 +305,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
]
},
"or al, -1": {
@@ -346,9 +342,9 @@
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, -1": {
@@ -356,9 +352,9 @@
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
]
},
"adc bl, cl": {
@@ -490,9 +486,10 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "0x14",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -505,16 +502,14 @@
"eor w21, w26, w4",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #8"
]
},
"adc ax, 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -527,10 +522,7 @@
"eor w21, w26, w4",
"bic w20, w21, w20",
"rmif x20, #15, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"adc eax, 1": {
@@ -538,8 +530,8 @@
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adcs w26, w4, w20",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@@ -548,8 +540,8 @@
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adcs x26, x4, x20",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
@@ -754,9 +746,10 @@
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxtb w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -768,16 +761,14 @@
"rmif x21, #63, #nzCv",
"bic w20, w20, w26",
"rmif x20, #7, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #8"
]
},
"sbb ax, 1": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxth w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -789,10 +780,7 @@
"rmif x21, #63, #nzCv",
"bic w20, w20, w26",
"rmif x20, #15, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"sbb eax, 1": {
@@ -800,10 +788,10 @@
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -812,10 +800,10 @@
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -1133,42 +1121,38 @@
]
},
"sub al, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "0x2C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"cfinv",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #8"
]
},
"sub ax, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmp w0, w20, lsl #16",
"sub w26, w4, #0x1 (1)",
"cfinv",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"sub eax, 1": {
"ExpectedInstructionCount": 4,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -1176,9 +1160,9 @@
"ExpectedInstructionCount": 4,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -1251,18 +1235,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor w26, w7, w5",
"tst w26, w26",
"mov x7, x26"
"eor w7, w7, w5",
"mov x26, x7",
"tst w7, w7"
]
},
"xor rbx, rcx": {
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor x26, x7, x5",
"tst x26, x26",
"mov x7, x26"
"eor x7, x7, x5",
"mov x26, x7",
"tst x7, x7"
]
},
"db 0x32, 0xcb": {
@@ -1296,9 +1280,9 @@
"xor ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor w26, w5, w7",
"tst w26, w26",
"mov x5, x26"
"eor w5, w5, w7",
"mov x26, x5",
"tst w5, w5"
]
},
"db 0x48, 0x33, 0xcb": {
@@ -1308,9 +1292,9 @@
"xor rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor x26, x5, x7",
"tst x26, x26",
"mov x5, x26"
"eor x5, x5, x7",
"mov x26, x5",
"tst x5, x5"
]
},
"xor al, 1": {
@@ -1335,18 +1319,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp bl, cl": {
@@ -1383,9 +1367,9 @@
"Comment": "0x35",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"eor w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, -1": {
@@ -1393,9 +1377,9 @@
"Comment": "0x35",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"eor x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp bx, cx": {
@@ -1484,11 +1468,11 @@
"Comment": "0x3C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"cmp ax, 1": {
@@ -1496,29 +1480,29 @@
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmp w0, w20, lsl #16",
"sub w26, w4, #0x1 (1)",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"cmp eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"cmp rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"cmp al, -1": {
@@ -1782,24 +1766,24 @@
"strb w20, [x28, #985]",
"ubfx w20, w27, #10, #1",
"sub x20, x21, x20, lsl #1",
"strb w20, [x28, #986]",
"rmif x27, #11, #nzcV",
"ubfx w21, w27, #12, #1",
"strb w21, [x28, #988]",
"ubfx w21, w27, #14, #1",
"strb w21, [x28, #990]",
"ubfx w21, w27, #16, #1",
"strb w21, [x28, #992]",
"ubfx w21, w27, #17, #1",
"strb w21, [x28, #993]",
"ubfx w21, w27, #18, #1",
"strb w21, [x28, #994]",
"ubfx w21, w27, #19, #1",
"strb w21, [x28, #995]",
"ubfx w21, w27, #20, #1",
"strb w21, [x28, #996]",
"ubfx w21, w27, #21, #1",
"strb w21, [x28, #997]",
"strb w20, [x28, #986]"
"ubfx w20, w27, #12, #1",
"strb w20, [x28, #988]",
"ubfx w20, w27, #14, #1",
"strb w20, [x28, #990]",
"ubfx w20, w27, #16, #1",
"strb w20, [x28, #992]",
"ubfx w20, w27, #17, #1",
"strb w20, [x28, #993]",
"ubfx w20, w27, #18, #1",
"strb w20, [x28, #994]",
"ubfx w20, w27, #19, #1",
"strb w20, [x28, #995]",
"ubfx w20, w27, #20, #1",
"strb w20, [x28, #996]",
"ubfx w20, w27, #21, #1",
"strb w20, [x28, #997]"
]
},
"sahf": {
@@ -1909,10 +1893,10 @@
]
},
"repz cmpsb": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 27,
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x68",
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -1933,18 +1917,19 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"lsl w0, w27, #24",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #24",
"cmp w0, w26, lsl #24",
"sub w26, w27, w26",
"cfinv",
"mov x27, x20"
"sub w26, w21, w26",
"cfinv"
]
},
"repz cmpsw": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 27,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x68",
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -1965,18 +1950,19 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"lsl w0, w27, #16",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #16",
"cmp w0, w26, lsl #16",
"sub w26, w27, w26",
"cfinv",
"mov x27, x20"
"sub w26, w21, w26",
"cfinv"
]
},
"repz cmpsd": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 25,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x60",
"cbz x5, #+0x64",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -1997,16 +1983,17 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"subs w26, w27, w26",
"cfinv",
"mov x27, x20"
"mov x21, x27",
"mov x27, x20",
"subs w26, w21, w26",
"cfinv"
]
},
"repz cmpsq": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 25,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x60",
"cbz x5, #+0x64",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -2027,16 +2014,17 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"subs x26, x27, x26",
"cfinv",
"mov x27, x20"
"mov x21, x27",
"mov x27, x20",
"subs x26, x21, x26",
"cfinv"
]
},
"repnz cmpsb": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 27,
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x68",
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -2057,18 +2045,19 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"lsl w0, w27, #24",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #24",
"cmp w0, w26, lsl #24",
"sub w26, w27, w26",
"cfinv",
"mov x27, x20"
"sub w26, w21, w26",
"cfinv"
]
},
"repnz cmpsw": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 27,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x68",
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -2089,18 +2078,19 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"lsl w0, w27, #16",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #16",
"cmp w0, w26, lsl #16",
"sub w26, w27, w26",
"cfinv",
"mov x27, x20"
"sub w26, w21, w26",
"cfinv"
]
},
"repnz cmpsd": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 25,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x60",
"cbz x5, #+0x64",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -2121,16 +2111,17 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"subs w26, w27, w26",
"cfinv",
"mov x27, x20"
"mov x21, x27",
"mov x27, x20",
"subs w26, w21, w26",
"cfinv"
]
},
"repnz cmpsq": {
"ExpectedInstructionCount": 24,
"ExpectedInstructionCount": 25,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x60",
"cbz x5, #+0x64",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -2151,9 +2142,10 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"subs x26, x27, x26",
"cfinv",
"mov x27, x20"
"mov x21, x27",
"mov x27, x20",
"subs x26, x21, x26",
"cfinv"
]
},
"test al, 1": {
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+121 -139
View File
@@ -13,17 +13,15 @@
},
"Instructions": {
"add al, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmn w0, w20, lsl #24",
"add w26, w4, #0x1 (1)",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #8"
]
},
"or al, 1": {
@@ -36,9 +34,10 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -51,16 +50,14 @@
"eor w21, w26, w4",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #8"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxtb w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -72,10 +69,7 @@
"rmif x21, #63, #nzCv",
"bic w20, w20, w26",
"rmif x20, #7, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #8"
]
},
"and al, 1": {
@@ -88,18 +82,16 @@
]
},
"sub al, 1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"cfinv",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #8"
]
},
"xor al, 1": {
@@ -116,11 +108,11 @@
"Comment": "GROUP1 0x80 /7",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"add al, -1": {
@@ -227,25 +219,23 @@
]
},
"add ax, 256": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x100 (256)",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"add eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"adds w26, w4, #0x100 (256)",
"mov x27, x4",
"adds w26, w4, #0x100 (256)",
"mov x4, x26"
]
},
@@ -253,8 +243,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"adds x26, x4, #0x100 (256)",
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"mov x4, x26"
]
},
@@ -262,18 +252,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0x100",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, #0x100",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0x100",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, #0x100",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, 256": {
@@ -281,8 +271,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adcs w26, w4, w20",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@@ -291,8 +281,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adcs x26, x4, x20",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
@@ -301,10 +291,10 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -313,10 +303,10 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -340,9 +330,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x100 (256)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -350,9 +340,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -360,50 +350,48 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0x100",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, #0x100",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0x100",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, #0x100",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x100 (256)",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"cmp rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"add ax, -256": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xff00",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, w20",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"add eax, -256": {
@@ -411,8 +399,8 @@
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"adds w26, w4, w20",
"mov x27, x4",
"adds w26, w4, w20",
"mov x4, x26"
]
},
@@ -420,8 +408,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"subs x26, x4, #0x100 (256)",
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"mov x4, x26"
]
},
@@ -429,18 +417,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0xffffff00",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, #0xffffff00",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0xffffffffffffff00",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, #0xffffffffffffff00",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, -256": {
@@ -448,8 +436,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"adcs w26, w4, w20",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@@ -458,8 +446,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"adcs x26, x4, x20",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
@@ -468,10 +456,10 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -480,10 +468,10 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -508,9 +496,9 @@
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"subs w26, w4, w20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -518,9 +506,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -528,18 +516,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0xffffff00",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, #0xffffff00",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0xffffffffffffff00",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, #0xffffffffffffff00",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, -256": {
@@ -547,40 +535,38 @@
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"subs w26, w4, w20",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"cmp rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"add ax, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x1 (1)",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"add eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"adds w26, w4, #0x1 (1)",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mov x4, x26"
]
},
@@ -588,8 +574,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"adds x26, x4, #0x1 (1)",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mov x4, x26"
]
},
@@ -597,18 +583,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, 1": {
@@ -616,8 +602,8 @@
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adcs w26, w4, w20",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@@ -626,8 +612,8 @@
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adcs x26, x4, x20",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
@@ -636,10 +622,10 @@
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cfinv",
"sbcs w26, w4, w20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -648,10 +634,10 @@
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"cfinv",
"sbcs x26, x4, x20",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -675,9 +661,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -685,9 +671,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"cfinv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -695,36 +681,36 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"cmp rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"cfinv",
"mov x27, x4"
"cfinv"
]
},
"add ax, -1": {
@@ -763,9 +749,9 @@
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, -1": {
@@ -773,9 +759,9 @@
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, -1": {
@@ -866,9 +852,9 @@
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"eor w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, -1": {
@@ -876,9 +862,9 @@
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"eor x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, -1": {
@@ -2041,16 +2027,14 @@
]
},
"neg bl": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"mov x27, x7",
"cmp wzr, w7, lsl #24",
"neg w26, w7",
"cfinv",
"mov x20, x7",
"bfxil x20, x26, #0, #8",
"mov x27, x7",
"mov x7, x20"
"bfxil x7, x26, #0, #8"
]
},
"mul bl": {
@@ -2157,25 +2141,23 @@
]
},
"neg bx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"cmp wzr, w7, lsl #16",
"neg w26, w7",
"cfinv",
"mov x20, x7",
"bfxil x20, x26, #0, #16",
"mov x27, x7",
"mov x7, x20"
"bfxil x7, x26, #0, #16"
]
},
"neg ebx": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"negs w26, w7",
"cfinv",
"mov x27, x7",
"mov x7, x26"
]
},
@@ -2183,9 +2165,9 @@
"ExpectedInstructionCount": 4,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"negs x26, x7",
"cfinv",
"mov x27, x7",
"mov x7, x26"
]
},
@@ -2222,9 +2204,9 @@
"ExpectedArm64ASM": [
"mul x20, x7, x4",
"umulh x6, x7, x4",
"mov x4, x20",
"cmp x6, #0x0 (0)",
"ccmn xzr, #0, #nzCV, eq",
"mov x4, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul bx": {
@@ -2328,9 +2310,9 @@
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -2339,9 +2321,9 @@
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -2362,9 +2344,9 @@
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -2373,9 +2355,9 @@
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
}
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+2 -2
View File
@@ -197,9 +197,9 @@
"Comment": "0x40",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
@@ -234,9 +234,9 @@
"Comment": "0x48",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"rmif x20, #63, #nzCv",
"mov x27, x4",
"mov x4, x26"
]
},
unittests/InstructionCountCI/FlagM/Secondary.json
+3 -5
View File
@@ -1059,15 +1059,13 @@
]
},
"cmpxchg rcx, rbx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"ExpectedArm64ASM": [
"eor w27, w4, w5",
"subs x26, x4, x5",
"cfinv",
"csel x20, x7, x5, eq",
"mov x21, x5",
"mov x5, x20",
"mov x4, x21"
"mov x4, x5",
"csel x5, x7, x5, eq"
]
},
"cmpxchg [rax], rbx": {
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+126 -132
View File
@@ -1205,21 +1205,21 @@
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr d2, [x28, #1040]",
"ldr q2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr d2, [x28, #1056]",
"ldr q2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr d2, [x28, #1072]",
"ldr q2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr d2, [x28, #1088]",
"ldr q2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr d2, [x28, #1104]",
"ldr q2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr d2, [x28, #1120]",
"ldr q2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr d2, [x28, #1136]",
"ldr q2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr d2, [x28, #1152]",
"ldr q2, [x28, #1152]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
@@ -1280,14 +1280,23 @@
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1298]",
"ldr q2, [x4, #32]",
"ldr q3, [x4, #48]",
"ldr q4, [x4, #64]",
"ldr q5, [x4, #80]",
"ldr q6, [x4, #96]",
"ldr q7, [x4, #112]",
"ldr q8, [x4, #128]",
"ldr q9, [x4, #144]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #1152]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@@ -1304,24 +1313,15 @@
"ldr q29, [x4, #368]",
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"ldr w21, [x4, #24]",
"ubfx w21, w21, #13, #3",
"rbit w1, w21",
"ldr w20, [x4, #24]",
"ubfx w20, w20, #13, #3",
"rbit w1, w20",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x21, #2",
"lsr x1, x20, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"strb w20, [x28, #1298]",
"str d9, [x28, #1152]",
"str d8, [x28, #1136]",
"str d7, [x28, #1120]",
"str d6, [x28, #1104]",
"str d5, [x28, #1088]",
"str d4, [x28, #1072]",
"str d3, [x28, #1056]",
"str d2, [x28, #1040]"
"msr fpcr, x0"
]
},
"rdgsbase eax": {
@@ -1419,21 +1419,21 @@
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr d2, [x28, #1040]",
"ldr q2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr d2, [x28, #1056]",
"ldr q2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr d2, [x28, #1072]",
"ldr q2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr d2, [x28, #1088]",
"ldr q2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr d2, [x28, #1104]",
"ldr q2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr d2, [x28, #1120]",
"ldr q2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr d2, [x28, #1136]",
"ldr q2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr d2, [x28, #1152]",
"ldr q2, [x28, #1152]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
@@ -1513,10 +1513,9 @@
]
},
"xrstor [rax]": {
"ExpectedInstructionCount": 165,
"ExpectedInstructionCount": 159,
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
"sub sp, sp, #0x40 (64)",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #0, #1",
"cbnz x20, #+0x8",
@@ -1535,23 +1534,23 @@
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"ldr q2, [x4, #32]",
"ldr q3, [x4, #48]",
"ldr q4, [x4, #64]",
"ldr q5, [x4, #80]",
"ldr q6, [x4, #96]",
"ldr q7, [x4, #112]",
"ldr q8, [x4, #128]",
"ldr q9, [x4, #144]",
"strb w20, [x28, #1298]",
"str d9, [x28, #1152]",
"str d8, [x28, #1136]",
"str d7, [x28, #1120]",
"str d6, [x28, #1104]",
"str d5, [x28, #1088]",
"str d4, [x28, #1072]",
"str d3, [x28, #1056]",
"str d2, [x28, #1040]",
"ldr q2, [x4, #32]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #1152]",
"b #+0x4c",
"mov w20, #0x0",
"mov w21, #0x37f",
@@ -1561,16 +1560,16 @@
"strb w20, [x28, #1017]",
"strb w20, [x28, #1018]",
"strb w20, [x28, #1022]",
"movi v2.2d, #0x0",
"strb w20, [x28, #1298]",
"str d2, [x28, #1152]",
"str d2, [x28, #1136]",
"str d2, [x28, #1120]",
"str d2, [x28, #1104]",
"str d2, [x28, #1088]",
"str d2, [x28, #1072]",
"str d2, [x28, #1056]",
"str d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str q2, [x28, #1040]",
"str q2, [x28, #1056]",
"str q2, [x28, #1072]",
"str q2, [x28, #1088]",
"str q2, [x28, #1104]",
"str q2, [x28, #1120]",
"str q2, [x28, #1136]",
"str q2, [x28, #1152]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #1",
"cbnz x20, #+0x8",
@@ -1592,80 +1591,76 @@
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"b #+0x44",
"movi v31.2d, #0x0",
"mov v30.16b, v31.16b",
"mov v29.16b, v31.16b",
"mov v28.16b, v31.16b",
"mov v27.16b, v31.16b",
"mov v26.16b, v31.16b",
"mov v25.16b, v31.16b",
"mov v24.16b, v31.16b",
"mov v23.16b, v31.16b",
"mov v22.16b, v31.16b",
"mov v21.16b, v31.16b",
"mov v20.16b, v31.16b",
"mov v19.16b, v31.16b",
"mov v18.16b, v31.16b",
"mov v17.16b, v31.16b",
"mov v16.16b, v31.16b",
"movi v16.2d, #0x0",
"mov v17.16b, v16.16b",
"mov v18.16b, v16.16b",
"mov v19.16b, v16.16b",
"mov v20.16b, v16.16b",
"mov v21.16b, v16.16b",
"mov v22.16b, v16.16b",
"mov v23.16b, v16.16b",
"mov v24.16b, v16.16b",
"mov v25.16b, v16.16b",
"mov v26.16b, v16.16b",
"mov v27.16b, v16.16b",
"mov v28.16b, v16.16b",
"mov v29.16b, v16.16b",
"mov v30.16b, v16.16b",
"mov v31.16b, v16.16b",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #2, #1",
"cbnz x20, #+0x8",
"b #+0x98",
"b #+0x88",
"ldr q2, [x4, #576]",
"ldr q3, [x4, #592]",
"ldr q4, [x4, #608]",
"ldr q5, [x4, #624]",
"ldr q6, [x4, #640]",
"ldr q7, [x4, #656]",
"ldr q8, [x4, #672]",
"ldr q9, [x4, #688]",
"ldr q10, [x4, #704]",
"ldr q11, [x4, #720]",
"ldr q12, [x4, #736]",
"ldr q13, [x4, #752]",
"ldr q14, [x4, #768]",
"ldr q15, [x4, #784]",
"str q2, [sp]",
"ldr q2, [x4, #800]",
"str q3, [sp, #32]",
"ldr q3, [x4, #816]",
"str q3, [x28, #256]",
"str q2, [x28, #240]",
"str q15, [x28, #224]",
"str q14, [x28, #208]",
"str q13, [x28, #192]",
"str q12, [x28, #176]",
"str q11, [x28, #160]",
"str q10, [x28, #144]",
"str q9, [x28, #128]",
"str q8, [x28, #112]",
"str q7, [x28, #96]",
"str q6, [x28, #80]",
"str q5, [x28, #64]",
"str q4, [x28, #48]",
"ldr q2, [sp, #32]",
"str q2, [x28, #32]",
"ldr q2, [sp]",
"str q2, [x28, #16]",
"ldr q2, [x4, #592]",
"str q2, [x28, #32]",
"ldr q2, [x4, #608]",
"str q2, [x28, #48]",
"ldr q2, [x4, #624]",
"str q2, [x28, #64]",
"ldr q2, [x4, #640]",
"str q2, [x28, #80]",
"ldr q2, [x4, #656]",
"str q2, [x28, #96]",
"ldr q2, [x4, #672]",
"str q2, [x28, #112]",
"ldr q2, [x4, #688]",
"str q2, [x28, #128]",
"ldr q2, [x4, #704]",
"str q2, [x28, #144]",
"ldr q2, [x4, #720]",
"str q2, [x28, #160]",
"ldr q2, [x4, #736]",
"str q2, [x28, #176]",
"ldr q2, [x4, #752]",
"str q2, [x28, #192]",
"ldr q2, [x4, #768]",
"str q2, [x28, #208]",
"ldr q2, [x4, #784]",
"str q2, [x28, #224]",
"ldr q2, [x4, #800]",
"str q2, [x28, #240]",
"ldr q2, [x4, #816]",
"str q2, [x28, #256]",
"b #+0x48",
"movi v2.2d, #0x0",
"str q2, [x28, #256]",
"str q2, [x28, #240]",
"str q2, [x28, #224]",
"str q2, [x28, #208]",
"str q2, [x28, #192]",
"str q2, [x28, #176]",
"str q2, [x28, #160]",
"str q2, [x28, #144]",
"str q2, [x28, #128]",
"str q2, [x28, #112]",
"str q2, [x28, #96]",
"str q2, [x28, #80]",
"str q2, [x28, #64]",
"str q2, [x28, #48]",
"str q2, [x28, #32]",
"str q2, [x28, #16]",
"str q2, [x28, #32]",
"str q2, [x28, #48]",
"str q2, [x28, #64]",
"str q2, [x28, #80]",
"str q2, [x28, #96]",
"str q2, [x28, #112]",
"str q2, [x28, #128]",
"str q2, [x28, #144]",
"str q2, [x28, #160]",
"str q2, [x28, #176]",
"str q2, [x28, #192]",
"str q2, [x28, #208]",
"str q2, [x28, #224]",
"str q2, [x28, #240]",
"str q2, [x28, #256]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #2",
"cbnz x20, #+0x8",
@@ -1679,8 +1674,7 @@
"lsr x1, x20, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"b #+0x4",
"add sp, sp, #0x40 (64)"
"b #+0x4"
]
},
"mfence": {
unittests/InstructionCountCI/FlagM/VEX_map2.json
+6 -6
View File
@@ -349,9 +349,9 @@
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w26, w5, w7",
"tst w26, w26",
"mov x4, x26"
"bic w4, w5, w7",
"mov x26, x4",
"tst w4, w4"
]
},
"andn rax, rbx, rcx": {
@@ -360,9 +360,9 @@
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x26, x5, x7",
"tst x26, x26",
"mov x4, x26"
"bic x4, x5, x7",
"mov x26, x4",
"tst x4, x4"
]
},
"bzhi eax, ebx, ecx": {
unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+1706 -1471
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+14276 -12017
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+25321 -22290
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87.json
+375 -369
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87_f64.json
+377 -369
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/Primary.json
+237 -240
View File
@@ -104,39 +104,35 @@
]
},
"add al, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "0x04",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmn w0, w20, lsl #24",
"add w26, w4, #0x1 (1)",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #8"
]
},
"add ax, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "0x05",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x1 (1)",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"add eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x05",
"ExpectedArm64ASM": [
"adds w26, w4, #0x1 (1)",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mov x4, x26"
]
},
@@ -144,8 +140,8 @@
"ExpectedInstructionCount": 3,
"Comment": "0x05",
"ExpectedArm64ASM": [
"adds x26, x4, #0x1 (1)",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mov x4, x26"
]
},
@@ -224,18 +220,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr w26, w7, w5",
"tst w26, w26",
"mov x7, x26"
"orr w7, w7, w5",
"mov x26, x7",
"tst w7, w7"
]
},
"or rbx, rcx": {
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"orr x26, x7, x5",
"tst x26, x26",
"mov x7, x26"
"orr x7, x7, x5",
"mov x26, x7",
"tst x7, x7"
]
},
"db 0x0A, 0xcb": {
@@ -269,9 +265,9 @@
"or ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr w26, w5, w7",
"tst w26, w26",
"mov x5, x26"
"orr w5, w5, w7",
"mov x26, x5",
"tst w5, w5"
]
},
"db 0x48, 0x0B, 0xcb": {
@@ -281,9 +277,9 @@
"or rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"orr x26, x5, x7",
"tst x26, x26",
"mov x5, x26"
"orr x5, x5, x7",
"mov x26, x5",
"tst x5, x5"
]
},
"or al, 1": {
@@ -308,18 +304,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x0D",
"ExpectedArm64ASM": [
"orr x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
]
},
"or al, -1": {
@@ -345,9 +341,9 @@
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, -1": {
@@ -355,9 +351,9 @@
"Comment": "0x0D",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
]
},
"adc bl, cl": {
@@ -501,9 +497,10 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "0x14",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -518,17 +515,15 @@
"bic w21, w22, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"adc ax, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -543,11 +538,8 @@
"bic w21, w22, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"mov x21, x4",
"bfxil x21, x26, #0, #16",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
]
},
"adc eax, 1": {
@@ -555,8 +547,8 @@
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adcs w26, w4, w20",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@@ -565,8 +557,8 @@
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adcs x26, x4, x20",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
@@ -695,8 +687,8 @@
"sbcs w26, w7, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x7, x26"
"mov x7, x26",
"msr nzcv, x20"
]
},
"sbb rbx, rcx": {
@@ -710,8 +702,8 @@
"sbcs x26, x7, x5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x7, x26"
"mov x7, x26",
"msr nzcv, x20"
]
},
"db 0x1A, 0xcb": {
@@ -782,8 +774,8 @@
"sbcs w26, w5, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x5, x26"
"mov x5, x26",
"msr nzcv, x20"
]
},
"db 0x48, 0x1B, 0xcb": {
@@ -800,14 +792,15 @@
"sbcs x26, x5, x7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x5, x26"
"mov x5, x26",
"msr nzcv, x20"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 16,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxtb w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -821,17 +814,15 @@
"bic w20, w20, w26",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"sbb ax, 1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 16,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxth w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -845,11 +836,8 @@
"bic w20, w20, w26",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"mov x21, x4",
"bfxil x21, x26, #0, #16",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
]
},
"sbb eax, 1": {
@@ -857,15 +845,15 @@
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, 1": {
@@ -873,15 +861,15 @@
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb al, -1": {
@@ -941,8 +929,8 @@
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, -1": {
@@ -957,8 +945,8 @@
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"and bl, cl": {
@@ -1147,8 +1135,8 @@
"subs w26, w7, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x7, x26"
"mov x7, x26",
"msr nzcv, x20"
]
},
"sub rbx, rcx": {
@@ -1159,8 +1147,8 @@
"subs x26, x7, x5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x7, x26"
"mov x7, x26",
"msr nzcv, x20"
]
},
"db 0x2A, 0xcb": {
@@ -1208,8 +1196,8 @@
"subs w26, w5, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x5, x26"
"mov x5, x26",
"msr nzcv, x20"
]
},
"db 0x48, 0x2B, 0xcb": {
@@ -1223,66 +1211,62 @@
"subs x26, x5, x7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x5, x26"
"mov x5, x26",
"msr nzcv, x20"
]
},
"sub al, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "0x2C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"sub ax, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmp w0, w20, lsl #16",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x21, x4",
"bfxil x21, x26, #0, #16",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
]
},
"sub eax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sub rax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "0x2D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sub al, -1": {
@@ -1324,8 +1308,8 @@
"subs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sub rax, -1": {
@@ -1336,8 +1320,8 @@
"adds x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"xor bl, cl": {
@@ -1362,18 +1346,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor w26, w7, w5",
"tst w26, w26",
"mov x7, x26"
"eor w7, w7, w5",
"mov x26, x7",
"tst w7, w7"
]
},
"xor rbx, rcx": {
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"eor x26, x7, x5",
"tst x26, x26",
"mov x7, x26"
"eor x7, x7, x5",
"mov x26, x7",
"tst x7, x7"
]
},
"db 0x32, 0xcb": {
@@ -1407,9 +1391,9 @@
"xor ebx, ecx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor w26, w5, w7",
"tst w26, w26",
"mov x5, x26"
"eor w5, w5, w7",
"mov x26, x5",
"tst w5, w5"
]
},
"db 0x48, 0x33, 0xcb": {
@@ -1419,9 +1403,9 @@
"xor rbx, rcx but modrm.rm as source"
],
"ExpectedArm64ASM": [
"eor x26, x5, x7",
"tst x26, x26",
"mov x5, x26"
"eor x5, x5, x7",
"mov x26, x5",
"tst x5, x5"
]
},
"xor al, 1": {
@@ -1446,18 +1430,18 @@
"ExpectedInstructionCount": 3,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x35",
"ExpectedArm64ASM": [
"eor x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp bl, cl": {
@@ -1496,9 +1480,9 @@
"Comment": "0x35",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"eor w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, -1": {
@@ -1506,9 +1490,9 @@
"Comment": "0x35",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"eor x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp bx, cx": {
@@ -1611,13 +1595,13 @@
"Comment": "0x3C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"cmp ax, 1": {
@@ -1625,35 +1609,35 @@
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmp w0, w20, lsl #16",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"cmp eax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"cmp rax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "0x3D",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"cmp al, -1": {
@@ -1924,13 +1908,14 @@
]
},
"xchg bl, cl": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "0x86",
"ExpectedArm64ASM": [
"mov x20, x5",
"bfxil x20, x7, #0, #8",
"bfxil x7, x5, #0, #8",
"mov x5, x20"
"mov x21, x5",
"mov x5, x20",
"bfxil x7, x21, #0, #8"
]
},
"xchg [rax], cl": {
@@ -1942,13 +1927,14 @@
]
},
"xchg bx, cx": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "0x87",
"ExpectedArm64ASM": [
"mov x20, x5",
"bfxil x20, x7, #0, #16",
"bfxil x7, x5, #0, #16",
"mov x5, x20"
"mov x21, x5",
"mov x5, x20",
"bfxil x7, x21, #0, #16"
]
},
"xchg [rax], cx": {
@@ -1960,12 +1946,13 @@
]
},
"xchg ebx, ecx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "0x87",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w7, w5",
"mov x5, x20"
"mov x21, x5",
"mov x5, x20",
"mov w7, w21"
]
},
"xchg [rax], ecx": {
@@ -1979,9 +1966,9 @@
"ExpectedInstructionCount": 3,
"Comment": "0x87",
"ExpectedArm64ASM": [
"mov x20, x7",
"mov x7, x5",
"mov x5, x20"
"mov x20, x5",
"mov x5, x7",
"mov x7, x20"
]
},
"xchg [rax], rcx": {
@@ -2444,22 +2431,24 @@
]
},
"xchg ax, bx": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 5,
"Comment": "0x90",
"ExpectedArm64ASM": [
"mov x20, x7",
"bfxil x20, x4, #0, #16",
"bfxil x4, x7, #0, #16",
"mov x7, x20"
"mov x21, x7",
"mov x7, x20",
"bfxil x4, x21, #0, #16"
]
},
"xchg eax, ebx": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "0x90",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w4, w7",
"mov x7, x20"
"mov x21, x7",
"mov x7, x20",
"mov w4, w21"
]
},
"xchg rax, rbx": {
@@ -2641,26 +2630,26 @@
"strb w21, [x28, #985]",
"ubfx w21, w27, #10, #1",
"sub x21, x22, x21, lsl #1",
"ubfx x22, x27, #11, #1",
"orr w20, w20, w22, lsl #28",
"ubfx w22, w27, #12, #1",
"strb w22, [x28, #988]",
"ubfx w22, w27, #14, #1",
"strb w22, [x28, #990]",
"ubfx w22, w27, #16, #1",
"strb w22, [x28, #992]",
"ubfx w22, w27, #17, #1",
"strb w22, [x28, #993]",
"ubfx w22, w27, #18, #1",
"strb w22, [x28, #994]",
"ubfx w22, w27, #19, #1",
"strb w22, [x28, #995]",
"ubfx w22, w27, #20, #1",
"strb w22, [x28, #996]",
"ubfx w22, w27, #21, #1",
"strb w22, [x28, #997]",
"msr nzcv, x20",
"strb w21, [x28, #986]"
"strb w21, [x28, #986]",
"ubfx x21, x27, #11, #1",
"orr w20, w20, w21, lsl #28",
"ubfx w21, w27, #12, #1",
"strb w21, [x28, #988]",
"ubfx w21, w27, #14, #1",
"strb w21, [x28, #990]",
"ubfx w21, w27, #16, #1",
"strb w21, [x28, #992]",
"ubfx w21, w27, #17, #1",
"strb w21, [x28, #993]",
"ubfx w21, w27, #18, #1",
"strb w21, [x28, #994]",
"ubfx w21, w27, #19, #1",
"strb w21, [x28, #995]",
"ubfx w21, w27, #20, #1",
"strb w21, [x28, #996]",
"ubfx w21, w27, #21, #1",
"strb w21, [x28, #997]",
"msr nzcv, x20"
]
},
"sahf": {
@@ -3247,10 +3236,10 @@
]
},
"repz cmpsb": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 29,
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x70",
"cbz x5, #+0x74",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3271,20 +3260,21 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"lsl w0, w27, #24",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #24",
"cmp w0, w26, lsl #24",
"sub w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
"sub w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"repz cmpsw": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 29,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x70",
"cbz x5, #+0x74",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3305,20 +3295,21 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"lsl w0, w27, #16",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #16",
"cmp w0, w26, lsl #16",
"sub w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
"sub w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"repz cmpsd": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 27,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x68",
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3339,18 +3330,19 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"subs w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
"mov x21, x27",
"mov x27, x20",
"subs w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"repz cmpsq": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 27,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x68",
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3371,18 +3363,19 @@
"ccmp x27, x26, #nzcv, ne",
"b.eq #-0x18",
"eor w20, w27, w26",
"subs x26, x27, x26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
"mov x21, x27",
"mov x27, x20",
"subs x26, x21, x26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"repnz cmpsb": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 29,
"Comment": "0xa6",
"ExpectedArm64ASM": [
"cbz x5, #+0x70",
"cbz x5, #+0x74",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3403,20 +3396,21 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"lsl w0, w27, #24",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #24",
"cmp w0, w26, lsl #24",
"sub w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
"sub w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"repnz cmpsw": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 29,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x70",
"cbz x5, #+0x74",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3437,20 +3431,21 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"lsl w0, w27, #16",
"mov x21, x27",
"mov x27, x20",
"lsl w0, w21, #16",
"cmp w0, w26, lsl #16",
"sub w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
"sub w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"repnz cmpsd": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 27,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x68",
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3471,18 +3466,19 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"subs w26, w27, w26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
"mov x21, x27",
"mov x27, x20",
"subs w26, w21, w26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"repnz cmpsq": {
"ExpectedInstructionCount": 26,
"ExpectedInstructionCount": 27,
"Comment": "0xa7",
"ExpectedArm64ASM": [
"cbz x5, #+0x68",
"cbz x5, #+0x6c",
"ldrsb x20, [x28, #986]",
"lsr x20, x20, #63",
"cbz x20, #+0x8",
@@ -3503,11 +3499,12 @@
"ccmp x27, x26, #nZcv, ne",
"b.ne #-0x18",
"eor w20, w27, w26",
"subs x26, x27, x26",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"mov x27, x20"
"mov x21, x27",
"mov x27, x20",
"subs x26, x21, x26",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"test al, 1": {
unittests/InstructionCountCI/PrimaryGroup.json
+172 -190
View File
@@ -16,17 +16,15 @@
],
"Instructions": {
"add al, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmn w0, w20, lsl #24",
"add w26, w4, #0x1 (1)",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #8"
]
},
"or al, 1": {
@@ -39,9 +37,10 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov x27, x4",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w4, w20",
@@ -56,17 +55,15 @@
"bic w21, w22, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov x27, x4",
"uxtb w20, w4",
"cset w21, hs",
"sub w21, w20, w21",
@@ -80,11 +77,8 @@
"bic w20, w20, w26",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"and al, 1": {
@@ -97,20 +91,18 @@
]
},
"sub al, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x21, x4",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x21"
"bfxil x4, x26, #0, #8",
"msr nzcv, x20"
]
},
"xor al, 1": {
@@ -127,13 +119,13 @@
"Comment": "GROUP1 0x80 /7",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"sub w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"add al, -1": {
@@ -250,25 +242,23 @@
]
},
"add ax, 256": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x100 (256)",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"add eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"adds w26, w4, #0x100 (256)",
"mov x27, x4",
"adds w26, w4, #0x100 (256)",
"mov x4, x26"
]
},
@@ -276,8 +266,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"adds x26, x4, #0x100 (256)",
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"mov x4, x26"
]
},
@@ -285,18 +275,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0x100",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, #0x100",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0x100",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, #0x100",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, 256": {
@@ -304,8 +294,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adcs w26, w4, w20",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@@ -314,8 +304,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adcs x26, x4, x20",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
@@ -324,15 +314,15 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, 256": {
@@ -340,15 +330,15 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"and eax, 256": {
@@ -371,78 +361,76 @@
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sub rax, 256": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"xor eax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0x100",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, #0x100",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, 256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0x100",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, #0x100",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, 256": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"cmp rax, 256": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"add ax, -256": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xff00",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, w20",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"add eax, -256": {
@@ -450,8 +438,8 @@
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"adds w26, w4, w20",
"mov x27, x4",
"adds w26, w4, w20",
"mov x4, x26"
]
},
@@ -459,8 +447,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"subs x26, x4, #0x100 (256)",
"mov x27, x4",
"subs x26, x4, #0x100 (256)",
"mov x4, x26"
]
},
@@ -468,18 +456,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0xffffff00",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, #0xffffff00",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0xffffffffffffff00",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, #0xffffffffffffff00",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, -256": {
@@ -487,8 +475,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"adcs w26, w4, w20",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@@ -497,8 +485,8 @@
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"adcs x26, x4, x20",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
@@ -507,15 +495,15 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, -256": {
@@ -523,15 +511,15 @@
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffff00",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"and eax, -256": {
@@ -555,42 +543,42 @@
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"subs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sub rax, -256": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"xor eax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0xffffff00",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, #0xffffff00",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, -256": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0xffffffffffffff00",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, #0xffffffffffffff00",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, -256": {
@@ -598,44 +586,42 @@
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov w20, #0xffffff00",
"mov x27, x4",
"subs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"cmp rax, -256": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"adds x26, x4, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"add ax, 1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"lsl w0, w4, #16",
"cmn w0, w20, lsl #16",
"add w26, w4, #0x1 (1)",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
"mov x27, x4",
"mov x4, x20"
"bfxil x4, x26, #0, #16"
]
},
"add eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"adds w26, w4, #0x1 (1)",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mov x4, x26"
]
},
@@ -643,8 +629,8 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"adds x26, x4, #0x1 (1)",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mov x4, x26"
]
},
@@ -652,18 +638,18 @@
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"orr x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, 1": {
@@ -671,8 +657,8 @@
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adcs w26, w4, w20",
"mov x27, x4",
"adcs w26, w4, w20",
"mov x4, x26"
]
},
@@ -681,8 +667,8 @@
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adcs x26, x4, x20",
"mov x27, x4",
"adcs x26, x4, x20",
"mov x4, x26"
]
},
@@ -691,15 +677,15 @@
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, 1": {
@@ -707,15 +693,15 @@
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov x27, x4",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"and eax, 1": {
@@ -738,64 +724,64 @@
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sub rax, 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"xor eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor w26, w4, #0x1",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, #0x1",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"eor x26, x4, #0x1",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, #0x1",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"cmp rax, 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /7",
"ExpectedArm64ASM": [
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x4"
"msr nzcv, x20"
]
},
"add ax, -1": {
@@ -834,9 +820,9 @@
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"orr w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
"orr w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
]
},
"or rax, -1": {
@@ -844,9 +830,9 @@
"Comment": "GROUP1 0x83 /-1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"orr x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
"orr x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
]
},
"adc eax, -1": {
@@ -881,8 +867,8 @@
"sbcs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sbb rax, -1": {
@@ -897,8 +883,8 @@
"sbcs x26, x4, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"and eax, -1": {
@@ -928,8 +914,8 @@
"subs w26, w4, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"sub rax, -1": {
@@ -940,8 +926,8 @@
"adds x26, x4, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x20"
]
},
"xor eax, -1": {
@@ -949,9 +935,9 @@
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"eor w26, w4, w20",
"tst w26, w26",
"mov x4, x26"
"eor w4, w4, w20",
"mov x26, x4",
"tst w4, w4"
]
},
"xor rax, -1": {
@@ -959,9 +945,9 @@
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"eor x26, x4, x20",
"tst x26, x26",
"mov x4, x26"
"eor x4, x4, x20",
"mov x26, x4",
"tst x4, x4"
]
},
"cmp eax, -1": {
@@ -1636,8 +1622,8 @@
"eor x21, x20, x4",
"lsr x21, x21, #63",
"bfi w22, w21, #28, #1",
"msr nzcv, x22",
"mov x4, x20"
"mov x4, x20",
"msr nzcv, x22"
]
},
"rcr ax, 1": {
@@ -2419,18 +2405,16 @@
]
},
"neg bl": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"mov x27, x7",
"cmp wzr, w7, lsl #24",
"neg w26, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x21, x7",
"bfxil x21, x26, #0, #8",
"msr nzcv, x20",
"mov x27, x7",
"mov x7, x21"
"bfxil x7, x26, #0, #8",
"msr nzcv, x20"
]
},
"mul bl": {
@@ -2558,42 +2542,40 @@
]
},
"neg bx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"cmp wzr, w7, lsl #16",
"neg w26, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"mov x21, x7",
"bfxil x21, x26, #0, #16",
"msr nzcv, x20",
"mov x27, x7",
"mov x7, x21"
"bfxil x7, x26, #0, #16",
"msr nzcv, x20"
]
},
"neg ebx": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"negs w26, w7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x7",
"mov x7, x26"
"mov x7, x26",
"msr nzcv, x20"
]
},
"neg rbx": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x27, x7",
"negs x26, x7",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20",
"mov x27, x7",
"mov x7, x26"
"mov x7, x26",
"msr nzcv, x20"
]
},
"mul bx": {
@@ -2629,9 +2611,9 @@
"ExpectedArm64ASM": [
"mul x20, x7, x4",
"umulh x6, x7, x4",
"mov x4, x20",
"cmp x6, #0x0 (0)",
"ccmn xzr, #0, #nzCV, eq",
"mov x4, x20"
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul bx": {
@@ -2869,12 +2851,12 @@
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x21"
]
},
"inc rax": {
@@ -2882,12 +2864,12 @@
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds x26, x4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x21"
]
},
"dec ax": {
@@ -2911,12 +2893,12 @@
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x21"
]
},
"dec rax": {
@@ -2924,12 +2906,12 @@
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs x26, x4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x21"
]
},
"push ax": {
unittests/InstructionCountCI/Primary_32Bit.json
+6 -6
View File
@@ -204,12 +204,12 @@
"Comment": "0x40",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"adds w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x21"
]
},
"dec ax": {
@@ -247,12 +247,12 @@
"Comment": "0x48",
"ExpectedArm64ASM": [
"cset w20, hs",
"mov x27, x4",
"subs w26, w4, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21",
"mov x27, x4",
"mov x4, x26"
"mov x4, x26",
"msr nzcv, x21"
]
},
"pusha": {
unittests/InstructionCountCI/SecondaryGroup.json
+126 -132
View File
@@ -1389,21 +1389,21 @@
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr d2, [x28, #1040]",
"ldr q2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr d2, [x28, #1056]",
"ldr q2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr d2, [x28, #1072]",
"ldr q2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr d2, [x28, #1088]",
"ldr q2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr d2, [x28, #1104]",
"ldr q2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr d2, [x28, #1120]",
"ldr q2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr d2, [x28, #1136]",
"ldr q2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr d2, [x28, #1152]",
"ldr q2, [x28, #1152]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
@@ -1464,14 +1464,23 @@
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1298]",
"ldr q2, [x4, #32]",
"ldr q3, [x4, #48]",
"ldr q4, [x4, #64]",
"ldr q5, [x4, #80]",
"ldr q6, [x4, #96]",
"ldr q7, [x4, #112]",
"ldr q8, [x4, #128]",
"ldr q9, [x4, #144]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #1152]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@@ -1488,24 +1497,15 @@
"ldr q29, [x4, #368]",
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"ldr w21, [x4, #24]",
"ubfx w21, w21, #13, #3",
"rbit w1, w21",
"ldr w20, [x4, #24]",
"ubfx w20, w20, #13, #3",
"rbit w1, w20",
"lsr w1, w1, #30",
"mrs x0, fpcr",
"bfi x0, x1, #22, #2",
"lsr x1, x21, #2",
"lsr x1, x20, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"strb w20, [x28, #1298]",
"str d9, [x28, #1152]",
"str d8, [x28, #1136]",
"str d7, [x28, #1120]",
"str d6, [x28, #1104]",
"str d5, [x28, #1088]",
"str d4, [x28, #1072]",
"str d3, [x28, #1056]",
"str d2, [x28, #1040]"
"msr fpcr, x0"
]
},
"rdgsbase eax": {
@@ -1603,21 +1603,21 @@
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1298]",
"strb w20, [x4, #4]",
"ldr d2, [x28, #1040]",
"ldr q2, [x28, #1040]",
"str q2, [x4, #32]",
"ldr d2, [x28, #1056]",
"ldr q2, [x28, #1056]",
"str q2, [x4, #48]",
"ldr d2, [x28, #1072]",
"ldr q2, [x28, #1072]",
"str q2, [x4, #64]",
"ldr d2, [x28, #1088]",
"ldr q2, [x28, #1088]",
"str q2, [x4, #80]",
"ldr d2, [x28, #1104]",
"ldr q2, [x28, #1104]",
"str q2, [x4, #96]",
"ldr d2, [x28, #1120]",
"ldr q2, [x28, #1120]",
"str q2, [x4, #112]",
"ldr d2, [x28, #1136]",
"ldr q2, [x28, #1136]",
"str q2, [x4, #128]",
"ldr d2, [x28, #1152]",
"ldr q2, [x28, #1152]",
"str q2, [x4, #144]",
"ubfx x20, x4, #1, #1",
"cbnz x20, #+0x8",
@@ -1697,10 +1697,9 @@
]
},
"xrstor [rax]": {
"ExpectedInstructionCount": 165,
"ExpectedInstructionCount": 159,
"Comment": "GROUP15 0x0F 0xAE /5",
"ExpectedArm64ASM": [
"sub sp, sp, #0x40 (64)",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #0, #1",
"cbnz x20, #+0x8",
@@ -1719,23 +1718,23 @@
"strb w23, [x28, #1018]",
"strb w20, [x28, #1022]",
"ldrb w20, [x4, #4]",
"ldr q2, [x4, #32]",
"ldr q3, [x4, #48]",
"ldr q4, [x4, #64]",
"ldr q5, [x4, #80]",
"ldr q6, [x4, #96]",
"ldr q7, [x4, #112]",
"ldr q8, [x4, #128]",
"ldr q9, [x4, #144]",
"strb w20, [x28, #1298]",
"str d9, [x28, #1152]",
"str d8, [x28, #1136]",
"str d7, [x28, #1120]",
"str d6, [x28, #1104]",
"str d5, [x28, #1088]",
"str d4, [x28, #1072]",
"str d3, [x28, #1056]",
"str d2, [x28, #1040]",
"ldr q2, [x4, #32]",
"str q2, [x28, #1040]",
"ldr q2, [x4, #48]",
"str q2, [x28, #1056]",
"ldr q2, [x4, #64]",
"str q2, [x28, #1072]",
"ldr q2, [x4, #80]",
"str q2, [x28, #1088]",
"ldr q2, [x4, #96]",
"str q2, [x28, #1104]",
"ldr q2, [x4, #112]",
"str q2, [x28, #1120]",
"ldr q2, [x4, #128]",
"str q2, [x28, #1136]",
"ldr q2, [x4, #144]",
"str q2, [x28, #1152]",
"b #+0x4c",
"mov w20, #0x0",
"mov w21, #0x37f",
@@ -1745,16 +1744,16 @@
"strb w20, [x28, #1017]",
"strb w20, [x28, #1018]",
"strb w20, [x28, #1022]",
"movi v2.2d, #0x0",
"strb w20, [x28, #1298]",
"str d2, [x28, #1152]",
"str d2, [x28, #1136]",
"str d2, [x28, #1120]",
"str d2, [x28, #1104]",
"str d2, [x28, #1088]",
"str d2, [x28, #1072]",
"str d2, [x28, #1056]",
"str d2, [x28, #1040]",
"movi v2.2d, #0x0",
"str q2, [x28, #1040]",
"str q2, [x28, #1056]",
"str q2, [x28, #1072]",
"str q2, [x28, #1088]",
"str q2, [x28, #1104]",
"str q2, [x28, #1120]",
"str q2, [x28, #1136]",
"str q2, [x28, #1152]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #1",
"cbnz x20, #+0x8",
@@ -1776,80 +1775,76 @@
"ldr q30, [x4, #384]",
"ldr q31, [x4, #400]",
"b #+0x44",
"movi v31.2d, #0x0",
"mov v30.16b, v31.16b",
"mov v29.16b, v31.16b",
"mov v28.16b, v31.16b",
"mov v27.16b, v31.16b",
"mov v26.16b, v31.16b",
"mov v25.16b, v31.16b",
"mov v24.16b, v31.16b",
"mov v23.16b, v31.16b",
"mov v22.16b, v31.16b",
"mov v21.16b, v31.16b",
"mov v20.16b, v31.16b",
"mov v19.16b, v31.16b",
"mov v18.16b, v31.16b",
"mov v17.16b, v31.16b",
"mov v16.16b, v31.16b",
"movi v16.2d, #0x0",
"mov v17.16b, v16.16b",
"mov v18.16b, v16.16b",
"mov v19.16b, v16.16b",
"mov v20.16b, v16.16b",
"mov v21.16b, v16.16b",
"mov v22.16b, v16.16b",
"mov v23.16b, v16.16b",
"mov v24.16b, v16.16b",
"mov v25.16b, v16.16b",
"mov v26.16b, v16.16b",
"mov v27.16b, v16.16b",
"mov v28.16b, v16.16b",
"mov v29.16b, v16.16b",
"mov v30.16b, v16.16b",
"mov v31.16b, v16.16b",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #2, #1",
"cbnz x20, #+0x8",
"b #+0x98",
"b #+0x88",
"ldr q2, [x4, #576]",
"ldr q3, [x4, #592]",
"ldr q4, [x4, #608]",
"ldr q5, [x4, #624]",
"ldr q6, [x4, #640]",
"ldr q7, [x4, #656]",
"ldr q8, [x4, #672]",
"ldr q9, [x4, #688]",
"ldr q10, [x4, #704]",
"ldr q11, [x4, #720]",
"ldr q12, [x4, #736]",
"ldr q13, [x4, #752]",
"ldr q14, [x4, #768]",
"ldr q15, [x4, #784]",
"str q2, [sp]",
"ldr q2, [x4, #800]",
"str q3, [sp, #32]",
"ldr q3, [x4, #816]",
"str q3, [x28, #256]",
"str q2, [x28, #240]",
"str q15, [x28, #224]",
"str q14, [x28, #208]",
"str q13, [x28, #192]",
"str q12, [x28, #176]",
"str q11, [x28, #160]",
"str q10, [x28, #144]",
"str q9, [x28, #128]",
"str q8, [x28, #112]",
"str q7, [x28, #96]",
"str q6, [x28, #80]",
"str q5, [x28, #64]",
"str q4, [x28, #48]",
"ldr q2, [sp, #32]",
"str q2, [x28, #32]",
"ldr q2, [sp]",
"str q2, [x28, #16]",
"ldr q2, [x4, #592]",
"str q2, [x28, #32]",
"ldr q2, [x4, #608]",
"str q2, [x28, #48]",
"ldr q2, [x4, #624]",
"str q2, [x28, #64]",
"ldr q2, [x4, #640]",
"str q2, [x28, #80]",
"ldr q2, [x4, #656]",
"str q2, [x28, #96]",
"ldr q2, [x4, #672]",
"str q2, [x28, #112]",
"ldr q2, [x4, #688]",
"str q2, [x28, #128]",
"ldr q2, [x4, #704]",
"str q2, [x28, #144]",
"ldr q2, [x4, #720]",
"str q2, [x28, #160]",
"ldr q2, [x4, #736]",
"str q2, [x28, #176]",
"ldr q2, [x4, #752]",
"str q2, [x28, #192]",
"ldr q2, [x4, #768]",
"str q2, [x28, #208]",
"ldr q2, [x4, #784]",
"str q2, [x28, #224]",
"ldr q2, [x4, #800]",
"str q2, [x28, #240]",
"ldr q2, [x4, #816]",
"str q2, [x28, #256]",
"b #+0x48",
"movi v2.2d, #0x0",
"str q2, [x28, #256]",
"str q2, [x28, #240]",
"str q2, [x28, #224]",
"str q2, [x28, #208]",
"str q2, [x28, #192]",
"str q2, [x28, #176]",
"str q2, [x28, #160]",
"str q2, [x28, #144]",
"str q2, [x28, #128]",
"str q2, [x28, #112]",
"str q2, [x28, #96]",
"str q2, [x28, #80]",
"str q2, [x28, #64]",
"str q2, [x28, #48]",
"str q2, [x28, #32]",
"str q2, [x28, #16]",
"str q2, [x28, #32]",
"str q2, [x28, #48]",
"str q2, [x28, #64]",
"str q2, [x28, #80]",
"str q2, [x28, #96]",
"str q2, [x28, #112]",
"str q2, [x28, #128]",
"str q2, [x28, #144]",
"str q2, [x28, #160]",
"str q2, [x28, #176]",
"str q2, [x28, #192]",
"str q2, [x28, #208]",
"str q2, [x28, #224]",
"str q2, [x28, #240]",
"str q2, [x28, #256]",
"ldr x20, [x4, #512]",
"ubfx x20, x20, #1, #2",
"cbnz x20, #+0x8",
@@ -1863,8 +1858,7 @@
"lsr x1, x20, #2",
"bfi x0, x1, #24, #1",
"msr fpcr, x0",
"b #+0x4",
"add sp, sp, #0x40 (64)"
"b #+0x4"
]
},
"mfence": {
unittests/InstructionCountCI/VEX_map2.json
+6 -6
View File
@@ -5279,9 +5279,9 @@
"Map 2 0b00 0xf2 32-bit"
],
"ExpectedArm64ASM": [
"bic w26, w5, w7",
"tst w26, w26",
"mov x4, x26"
"bic w4, w5, w7",
"mov x26, x4",
"tst w4, w4"
]
},
"andn rax, rbx, rcx": {
@@ -5290,9 +5290,9 @@
"Map 2 0b00 0xf2 64-bit"
],
"ExpectedArm64ASM": [
"bic x26, x5, x7",
"tst x26, x26",
"mov x4, x26"
"bic x4, x5, x7",
"mov x26, x4",
"tst x4, x4"
]
},
"bzhi eax, ebx, ecx": {
unittests/InstructionCountCI/x87.json
+375 -369
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unittests/InstructionCountCI/x87_f64.json
+377 -369
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File diff suppressed because it is too large. Load diff