Docs: Update for release FEX-2404

Merge pull request #3556 from Sonicadvance1/move_app_config
FEXCore: Fixes priority of FEX_APP_CONFIG
2026-10-06 23:00:17 +02:00 · 2024-04-05 15:20:24 -07:00 · 2024-04-05 15:18:24 -07:00 · 2024-04-05 13:10:43 -07:00 · 2024-04-05 11:36:33 -04:00 · 2024-04-04 07:42:27 -04:00
470 changed files with 33419 additions and 41785 deletions
@@ -37,7 +37,6 @@ If applicable, add screenshots and video to help explain your problem.

 **Additional context**
 - Is this an x86 or x86-64 game: [x86/x86-64/Both]
- - Does this reproduce on x86-64 host with FEX: [Yes/No/Untested]
 - Does this reproduce on AArch64 with Radeon/Intel/Nvidia: [Yes/No/Untested]
 - Is this a Vulkan game: [Yes/No/Unknown]
   - If Yes, What is your Vulkan driver:
@@ -13,7 +13,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_FORCE32BITALLOCATOR: 1
  FEX_ENABLEAVX: 1

 jobs:
@@ -78,18 +77,6 @@ jobs:
      shell: bash
      run: cmake --build . --config $BUILD_TYPE --target install

-    - name: IR Tests
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      # Execute the unit tests
-      run: cmake --build . --config $BUILD_TYPE --target ir_tests
-
-    - name: IR Test Results move
-      if: ${{ always() }}
-      shell: bash
-      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
-
    - name: gcc target tests 64
      working-directory: ${{runner.workspace}}/build
      shell: bash
@@ -250,7 +237,7 @@ jobs:
      working-directory: ${{runner.workspace}}/build
      # Cap out the log files at 20M in case something crash spins and dumps fault text
      # ASM tests get quite close to 10MB
-      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+      run: truncate --size="<20M" ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true

    - name: Remove old SHM regions
      if: ${{ always() }}
@@ -20,7 +20,6 @@ env:
  BUILD_TYPE: Release
  CC: clang
  CXX: clang++
-  FEX_FORCE32BITALLOCATOR: 1
  FEX_ENABLEAVX: 1

 jobs:
@@ -85,18 +84,6 @@ jobs:
      shell: bash
      run: cmake --build . --config $BUILD_TYPE --target install

-    - name: IR Tests
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      # Execute the unit tests
-      run: cmake --build . --config $BUILD_TYPE --target ir_tests
-
-    - name: IR Test Results move
-      if: ${{ always() }}
-      shell: bash
-      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
-
    - name: gcc target tests 64
      working-directory: ${{runner.workspace}}/build
      shell: bash
@@ -184,7 +171,7 @@ jobs:
      working-directory: ${{runner.workspace}}/build
      # Cap out the log files at 20M in case something crash spins and dumps fault text
      # ASM tests get quite close to 10MB
-      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+      run: truncate --size="<20M" ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true

    - name: Remove old SHM regions
      if: ${{ always() }}
@@ -90,7 +90,7 @@ jobs:
      working-directory: ${{runner.workspace}}/build
      # Cap out the log files at 20M in case something crash spins and dumps fault text
      # ASM tests get quite close to 10MB
-      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+      run: truncate --size="<20M" ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true

    - name: Set runner name
      if: ${{ always() }}
@@ -121,7 +121,7 @@ jobs:
      working-directory: ${{runner.workspace}}/build
      # Cap out the log files at 20M in case something crash spins and dumps fault text
      # ASM tests get quite close to 10MB
-      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+      run: truncate --size="<20M" ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true

    - name: Set runner name
      if: ${{ always() }}
@@ -100,25 +100,13 @@ jobs:
      working-directory: ${{runner.workspace}}/build
      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM128bit.log || true

-    - name: IR Tests
-      working-directory: ${{runner.workspace}}/build
-      shell: bash
-      # Execute the unit tests
-      run: cmake --build . --config $BUILD_TYPE --target ir_tests
-
-    - name: IR Test Results move
-      if: ${{ always() }}
-      shell: bash
-      working-directory: ${{runner.workspace}}/build
-      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
-
    - name: Truncate test results
      if: ${{ always() }}
      shell: bash
      working-directory: ${{runner.workspace}}/build
      # Cap out the log files at 20M in case something crash spins and dumps fault text
      # ASM tests get quite close to 10MB
-      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+      run: truncate --size="<20M" ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true

    - name: Set runner name
      if: ${{ always() }}
@@ -15,19 +15,19 @@
 	path = External/tiny-json
 	url = https://github.com/Sonicadvance1/tiny-json.git
 [submodule "External/xbyak"]
-        shallow = true
+  shallow = true
 	path = External/xbyak
-	url = https://github.com/FEX-Emu/xbyak.git
+	url = https://github.com/herumi/xbyak.git
 [submodule "External/fex-posixtest-bins"]
-        shallow = true
+  shallow = true
 	path = External/fex-posixtest-bins
 	url = https://github.com/FEX-Emu/fex-posixtest-bins.git
 [submodule "External/fex-gvisor-tests-bins"]
-        shallow = true
+  shallow = true
 	path = External/fex-gvisor-tests-bins
 	url = https://github.com/FEX-Emu/fex-gvisor-tests-bins.git
 [submodule "External/fex-gcc-target-tests-bins"]
-        shallow = true
+  shallow = true
 	path = External/fex-gcc-target-tests-bins
 	url = https://github.com/FEX-Emu/fex-gcc-target-tests-bins.git
 [submodule "External/jemalloc"]
@@ -41,7 +41,7 @@
 	url = https://github.com/FEX-Emu/drm-headers.git
 [submodule "External/xxhash"]
 	path = External/xxhash
-	url = https://github.com/FEX-Emu/xxHash.git
+	url = https://github.com/Cyan4973/xxHash.git
 [submodule "External/Catch2"]
 	path = External/Catch2
 	url = https://github.com/catchorg/Catch2.git
@@ -26,7 +26,6 @@ option(ENABLE_OFFLINE_TELEMETRY "Enables FEX offline telemetry" TRUE)
 option(ENABLE_COMPILE_TIME_TRACE "Enables time trace compile option" FALSE)
 option(ENABLE_LIBCXX "Enables LLVM libc++" FALSE)
 option(ENABLE_CCACHE "Enables ccache for compile caching" TRUE)
-option(ENABLE_TERMUX_BUILD "Forces building for Termux on a non-Termux build machine" FALSE)
 option(ENABLE_VIXL_SIMULATOR "Forces the FEX JIT to use the VIXL simulator" FALSE)
 option(ENABLE_VIXL_DISASSEMBLER "Enables debug disassembler output with VIXL" FALSE)
 option(COMPILE_VIXL_DISASSEMBLER "Compiles the vixl disassembler in to vixl" FALSE)
@@ -122,6 +121,11 @@ if (CMAKE_SYSTEM_PROCESSOR MATCHES "^aarch64|^arm64|^armv8\.*")
  add_definitions(-D_M_ARM_64=1)
 endif()

+if (CMAKE_SYSTEM_PROCESSOR MATCHES "^arm64ec")
+  set(_M_ARM_64EC 1)
+  add_definitions(-D_M_ARM_64EC=1)
+endif()
+
 if (ENABLE_CCACHE)
  find_program(CCACHE_PROGRAM ccache)
  if(CCACHE_PROGRAM)
@@ -158,18 +162,6 @@ if (NOT ENABLE_OFFLINE_TELEMETRY)
  add_definitions(-DFEX_DISABLE_TELEMETRY=1)
 endif()

-if(DEFINED ENV{TERMUX_VERSION} OR ENABLE_TERMUX_BUILD)
-  add_definitions(-DTERMUX_BUILD=1)
-  set(TERMUX_BUILD 1)
-
-  # Termux doesn't support Jemalloc due to bad interactions between emutls, jemalloc, and scudo
-  set(ENABLE_JEMALLOC FALSE)
-
-  # Termux builds can't rely on X11 packages
-  # SDL2 isn't even compiled with GL support so our GUIs wouldn't even work
-  set(BUILD_FEXCONFIG FALSE)
-endif()
-
 if (ENABLE_ASAN)
  add_definitions(-DENABLE_ASAN=1)
  add_compile_options(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
@@ -232,8 +224,10 @@ endif()
 find_package(PkgConfig REQUIRED)
 find_package(Python 3.0 REQUIRED COMPONENTS Interpreter)

-add_subdirectory(External/xxhash/)
-include_directories(External/xxhash/)
+set(XXHASH_BUNDLED_MODE TRUE)
+set(XXHASH_BUILD_XXHSUM FALSE)
+set(BUILD_SHARED_LIBS OFF)
+add_subdirectory(External/xxhash/cmake_unofficial/)

 add_definitions(-Wno-trigraphs)
 add_definitions(-DGLOBAL_DATA_DIRECTORY="${DATA_DIRECTORY}/")
@@ -1,5 +0,0 @@
-{
-  "Config": {
-    "AdditionalArguments": "--no-sandbox"
-  }
-}
@@ -3,11 +3,12 @@ FROM ubuntu:20.04 as builder

 RUN DEBIAN_FRONTEND="noninteractive" apt-get update
 RUN DEBIAN_FRONTEND="noninteractive" apt install -y cmake \
-clang-10 llvm-10 nasm ninja-build \
-libcap-dev libglfw3-dev libepoxy-dev python3-dev \
-python3 linux-headers-generic
+clang-10 llvm-10 nasm ninja-build pkg-config \
+libcap-dev libglfw3-dev libepoxy-dev python3-dev libsdl2-dev \
+python3 linux-headers-generic \
+git

-COPY . /opt/FEX
+RUN git clone --recurse-submodules https://github.com/FEX-Emu/FEX.git

 CMD [ "mkdir /opt/FEX/build" ]

@@ -30,10 +30,11 @@ set(CMAKE_REQUIRED_FLAGS "-std=c++11 -Wattributes -Werror=attributes")
 check_cxx_source_compiles(
  "
  __attribute__((preserve_all))
-  void Testy() {
+  int Testy(int a, int b, int c, int d, int e, int f) {
+  return a + b + c + d + e + f;
  }
  int main() {
-  return 0;
+  return Testy(0, 1, 2, 3, 4, 5);
  }"
  HAS_CLANG_PRESERVE_ALL)
 unset(CMAKE_REQUIRED_FLAGS)
@@ -441,6 +441,24 @@ def print_parse_envloader_options(options):
                output_argloader.write("}\n")
    output_argloader.write("#endif\n")

+def print_parse_jsonloader_options(options):
+    output_argloader.write("#ifdef JSONLOADER\n")
+    output_argloader.write("#undef JSONLOADER\n")
+    output_argloader.write("if (false) {}\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            value_type = op_vals["Type"]
+            if (value_type == "strenum"):
+                output_argloader.write("else if (KeyName == \"{0}\") {{\n".format(op_key))
+                output_argloader.write("Set(KeyOption, FEXCore::Config::EnumParser<FEXCore::Config::{}ConfigPair>(FEXCore::Config::{}_EnumPairs, Value_View));\n".format(op_key, op_key, op_key))
+                output_argloader.write("}\n")
+
+    output_argloader.write("else {{\n".format(op_key))
+    output_argloader.write("Set(KeyOption, ConfigString);\n")
+    output_argloader.write("}\n")
+
+    output_argloader.write("#endif\n")
+
 def print_parse_enum_options(options):
    output_argloader.write("#ifdef ENUMDEFINES\n")
    output_argloader.write("#undef ENUMDEFINES\n")
@@ -556,6 +574,9 @@ print_parse_argloader_options(options);
 # Generate environment loader code
 print_parse_envloader_options(options);

+# Generate json loader code
+print_parse_jsonloader_options(options);
+
 # Generate enum variable options
 print_parse_enum_options(options);

@@ -7,6 +7,7 @@ set (FEXCORE_BASE_SRCS
  Utils/FileLoading.cpp
  Utils/ForcedAssert.cpp
  Utils/LogManager.cpp
+  Utils/SpinWaitLock.cpp
  )

 if (NOT MINGW_BUILD)
@@ -149,7 +150,6 @@ set (SRCS
  Interface/IR/Passes/DeadStoreElimination.cpp
  Interface/IR/Passes/RegisterAllocationPass.cpp
  Interface/IR/Passes/InlineCallOptimization.cpp
-  Utils/NetStream.cpp
  Utils/Telemetry.cpp
  Utils/Threads.cpp
  Utils/Profiler.cpp
@@ -194,7 +194,7 @@ endif()
 # Some defines for the softfloat library
 list(APPEND DEFINES "-DSOFTFLOAT_BUILTIN_CLZ")

-set (LIBS fmt::fmt vixl xxhash FEXHeaderUtils)
+set (LIBS fmt::fmt vixl xxHash::xxhash FEXHeaderUtils)

 if (NOT MINGW_BUILD)
  list (APPEND LIBS dl)
@@ -1,10 +1,10 @@
 // SPDX-License-Identifier: MIT
 #pragma once

-#include <FEXCore/Utils/BitUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/fextl/sstream.h>
 #include <FEXCore/fextl/string.h>
+#include <FEXHeaderUtils/BitUtils.h>

 #include <cmath>
 #include <cstring>
@@ -48,6 +48,7 @@ namespace DefaultValues {
    PATH_CONFIG_DIR_GLOBAL,
    PATH_CONFIG_FILE_LOCAL,
    PATH_CONFIG_FILE_GLOBAL,
+    PATH_CONFIG_TELEMETRY_FOLDER,
    PATH_LAST,
  };
  static std::array<fextl::string, Paths::PATH_LAST> Paths;
@@ -64,6 +65,22 @@ namespace DefaultValues {
    Paths[PATH_CONFIG_FILE_LOCAL + Global] = Path;
  }

+  fextl::string const& GetTelemetryDirectory() {
+    auto &Path = Paths[PATH_CONFIG_TELEMETRY_FOLDER];
+    if (Path.empty()) {
+      FEX_CONFIG_OPT(TelemetryDirectory, TELEMETRYDIRECTORY);
+      if (!TelemetryDirectory().empty()) {
+        Path = TelemetryDirectory;
+        Path += "/";
+      }
+      else {
+        Path = Config::GetDataDirectory() + "Telemetry/";
+      }
+    }
+
+    return Path;
+  }
+
  fextl::string const& GetDataDirectory() {
    return Paths[PATH_DATA_DIR];
  }
@@ -113,7 +130,7 @@ namespace DefaultValues {
  static fextl::map<FEXCore::Config::LayerType, fextl::unique_ptr<FEXCore::Config::Layer>> ConfigLayers;
  static FEXCore::Config::Layer *Meta{};

-  constexpr std::array<FEXCore::Config::LayerType, 9> LoadOrder = {
+  constexpr std::array<FEXCore::Config::LayerType, 10> LoadOrder = {
    FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN,
    FEXCore::Config::LayerType::LAYER_MAIN,
    FEXCore::Config::LayerType::LAYER_GLOBAL_STEAM_APP,
@@ -121,6 +138,7 @@ namespace DefaultValues {
    FEXCore::Config::LayerType::LAYER_LOCAL_STEAM_APP,
    FEXCore::Config::LayerType::LAYER_LOCAL_APP,
    FEXCore::Config::LayerType::LAYER_ARGUMENTS,
+    FEXCore::Config::LayerType::LAYER_USER_OVERRIDE,
    FEXCore::Config::LayerType::LAYER_ENVIRONMENT,
    FEXCore::Config::LayerType::LAYER_TOP
  };
@@ -77,7 +77,9 @@
          "ENABLECRYPTO": "enablecrypto",
          "DISABLECRYPTO": "disablecrypto",
          "ENABLERPRES": "enablerpres",
-          "DISABLERPRES": "disablerpres"
+          "DISABLERPRES": "disablerpres",
+          "ENABLEPRESERVEALLABI": "enablepreserveallabi",
+          "DISABLEPRESERVEALLABI": "disablepreserveallabi"
        },
        "Desc": [
          "Allows controlling of the CPU features in the JIT.",
@@ -97,7 +99,28 @@
          "\t{enable,disable}flagm: Will force enable or disable flagm even if the host doesn't support it",
          "\t{enable,disable}flagm2: Will force enable or disable flagm2 even if the host doesn't support it",
          "\t{enable,disable}crypto: Will force enable or disable crypto extensions even if the host doesn't support it",
-          "\t{enable,disable}rpres: Will force enable or disable rpres even if the host doesn't support it"
+          "\t{enable,disable}rpres: Will force enable or disable rpres even if the host doesn't support it",
+          "\t{enable,disable}preserveallabi: Will force enable or disable preserve_all abi even if the host doesn't support it"
+        ]
+      },
+      "CPUID": {
+        "Type": "strenum",
+        "Default": "FEXCore::Config::CPUID::OFF",
+        "Enums": {
+          "ENABLESHA": "enablesha",
+          "DISABLESHA": "disablesha"
+        },
+        "Desc": [
+          "Allows controlling of the CPU features are exposed in CPUID.",
+          "\toff: Default CPU features queried from CPU features",
+          "\t{enable,disable}sha: Will force enable or disable sha even if the host doesn't support it"
+        ]
+      },
+      "SmallTSCScale": {
+        "Type": "bool",
+        "Default": "true",
+        "Desc": [
+          "Scales the cycle counter on systems that have low frequencies."
        ]
      }
    },
@@ -247,23 +270,6 @@
          "Disables optimizations passes for debugging."
        ]
      },
-      "SRA": {
-        "Type": "bool",
-        "Default": "true",
-        "Desc": [
-          "Set to false to disable Static Register Allocation"
-        ]
-      },
-      "Force32BitAllocator": {
-        "Type": "bool",
-        "Default": "false",
-        "Desc": [
-          "Forces use of the 32-bit allocator on 32-bit applications",
-          "Used to work around ulimit problems of CI runner",
-          "Potentially useful for debugging memory problems",
-          "32-bit allocator is always used if your host kernel is older than 4.17"
-        ]
-      },
      "GlobalJITNaming": {
        "Type": "bool",
        "Default": "false",
@@ -362,6 +368,14 @@
          "File to write FEX output to.",
          "[stdout, stderr, server, <Filename>]"
        ]
+      },
+      "TelemetryDirectory": {
+        "Type": "str",
+        "Default": "",
+        "Desc": [
+          "Redirects the telemetry folder that FEX usually writes to.",
+          "By default telemetry data is stored in {$FEX_APP_DATA_LOCATION,{$XDG_DATA_HOME,$HOME}/.fex-emu/Telemetry/}"
+        ]
      }
    },
    "Hacks": {
@@ -373,9 +387,8 @@
        "Desc": [
          "Checks code for modification before execution.",
          "\tnone: No checks",
-          "\tmtrack: Page tracking based invalidation",
-          "\tfull: Validate code before every run (slow)",
-          "\tmman: Invalidate on mmap, mprotect, munmap (deprecated, use mtrack)"
+          "\tmtrack: Page tracking based invalidation (default)",
+          "\tfull: Validate code before every run (slow)"
        ]
      },
      "TSOEnabled": {
@@ -386,6 +399,21 @@
          "Highly likely to break any multithreaded application if disabled."
        ]
      },
+      "VectorTSOEnabled": {
+        "Type": "bool",
+        "Default": "true",
+        "Desc": [
+          "When TSO emulation is enabled, controls if vector loadstores should also be atomic."
+        ]
+      },
+      "MemcpySetTSOEnabled": {
+        "Type": "bool",
+        "Default": "true",
+        "Desc": [
+          "When TSO emulation is enabled, controls if memcpy and memset should also be atomic.",
+          "Only affects REP MOVS and REP STOS instructions"
+        ]
+      },
      "TSOAutoMigration": {
        "Type": "bool",
        "Default": "true",
@@ -433,6 +461,14 @@
          "Hides the hypervisor CPUID bit when set.",
          "Should only be used for applications that have issues with this set."
        ]
+      },
+      "StartupSleep": {
+        "Type": "uint32",
+        "Default": "0",
+        "Desc": [
+          "Sleeps the process at startup for a duration of seconds.",
+          "Useful if an application crashes too quickly to attach a debugger."
+        ]
      }
    },
    "Misc": {
@@ -12,10 +12,6 @@
 #include <string.h>
 #include <utility>

-namespace FEXCore::HLE {
-  class SyscallVisitor;
-}
-
 namespace FEXCore::Context {
  void InitializeStaticTables(OperatingMode Mode) {
    X86Tables::InitializeInfoTables(Mode);
@@ -34,10 +30,6 @@ namespace FEXCore::Context {
    return CustomExitHandler;
  }

-  void FEXCore::Context::ContextImpl::Stop() {
-    Stop(false);
-  }
-
  void FEXCore::Context::ContextImpl::CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
    CompileBlock(Thread->CurrentFrame, GuestRIP);
  }
@@ -46,10 +38,6 @@ namespace FEXCore::Context {
    CompileBlock(Thread->CurrentFrame, GuestRIP, MaxInst);
  }

-  bool FEXCore::Context::ContextImpl::IsDone() const {
-    return IsPaused();
-  }
-
  void FEXCore::Context::ContextImpl::SetCustomCPUBackendFactory(CustomCPUFactoryType Factory) {
    CustomCPUFactory = std::move(Factory);
  }
@@ -78,4 +66,8 @@ namespace FEXCore::Context {
  FEXCore::CPUID::FunctionResults FEXCore::Context::ContextImpl::RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
    return CPUID.RunFunctionName(Function, Leaf, CPU);
  }
+
+  bool FEXCore::Context::ContextImpl::IsAddressInCodeBuffer(FEXCore::Core::InternalThreadState *Thread, uintptr_t Address) const {
+    return Thread->CPUBackend->IsAddressInCodeBuffer(Address);
+  }
 }
@@ -13,6 +13,7 @@
 #include <FEXCore/Core/HostFeatures.h>
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Debug/InternalThreadState.h>
+#include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/SignalScopeGuards.h>
@@ -44,7 +45,6 @@ namespace CodeSerialize {

 namespace CPU {
  class Arm64JITCore;
-  class X86JITCore;
  class Dispatcher;
 }
 namespace HLE {
@@ -69,28 +69,30 @@ namespace FEXCore::Context {
    MODE_SINGLESTEP = 1,
  };

+  struct ExitFunctionLinkData {
+    uint64_t HostBranch;
+    uint64_t GuestRIP;
+  };
+
+  using BlockDelinkerFunc = void(*)(FEXCore::Core::CpuStateFrame *Frame, FEXCore::Context::ExitFunctionLinkData *Record);
+  constexpr uint32_t TSC_SCALE = 128;
+  constexpr uint32_t TSC_SCALE_MAXIMUM = 1'000'000'000; ///< 1Ghz
+
  class ContextImpl final : public FEXCore::Context::Context {
    public:
      // Context base class implementation.
-      FEXCore::Core::InternalThreadState* InitCore(uint64_t InitialRIP, uint64_t StackPointer) override;
+      bool InitCore() override;

      void SetExitHandler(ExitHandler handler) override;
      ExitHandler GetExitHandler() const override;

-      void Pause() override;
-      void Run() override;
-      void Stop() override;
-      void Step() override;
-
-      ExitReason RunUntilExit() override;
+      ExitReason RunUntilExit(FEXCore::Core::InternalThreadState *Thread) override;

      void ExecuteThread(FEXCore::Core::InternalThreadState *Thread) override;

      void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) override;
      void CompileRIPCount(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP, uint64_t MaxInst) override;

-      bool IsDone() const override;
-
      void SetCustomCPUBackendFactory(CustomCPUFactoryType Factory) override;

      HostFeatures GetHostFeatures() const override;
@@ -117,7 +119,8 @@ namespace FEXCore::Context {
       *    - CTX->RunUntilExit(Thread);
       *  OS thread Creation:
       *    - Thread = CreateThread(0, 0, NewState, PPID);
-       *    - InitializeThread(Thread);
+       *    - Thread->ExecutionThread = FEXCore::Threads::Thread::Create(ThreadHandler, Arg);
+       *    - ThreadHandler calls `CTX->ExecutionThread(Thread)`
       *  OS fork (New thread created with a clone of thread state):
       *    - clone{2, 3}
       *    - Thread = CreateThread(0, 0, CopyOfThreadState, PPID);
@@ -132,27 +135,13 @@ namespace FEXCore::Context {

      // Public for threading
      void ExecutionThread(FEXCore::Core::InternalThreadState *Thread) override;
-      /**
-       * @brief Initializes the OS thread object and prepares to start executing on that new OS thread
-       *
-       * @param Thread The internal FEX thread state object
-       *
-       * The OS thread will wait until RunThread is executed
-       */
-      void InitializeThread(FEXCore::Core::InternalThreadState *Thread) override;
-      /**
-       * @brief Starts the OS thread object to start executing guest code
-       *
-       * @param Thread The internal FEX thread state object
-       */
-      void RunThread(FEXCore::Core::InternalThreadState *Thread) override;
-      void StopThread(FEXCore::Core::InternalThreadState *Thread) override;
+
      /**
       * @brief Destroys this FEX thread object and stops tracking it internally
       *
       * @param Thread The internal FEX thread state object
       */
-      void DestroyThread(FEXCore::Core::InternalThreadState *Thread) override;
+      void DestroyThread(FEXCore::Core::InternalThreadState *Thread, bool NeedsTLSUninstall) override;

 #ifndef _WIN32
      void LockBeforeFork(FEXCore::Core::InternalThreadState *Thread) override;
@@ -184,13 +173,22 @@ namespace FEXCore::Context {
      void WriteFilesWithCode(AOTIRCodeFileWriterFn Writer) override {
        IRCaptureCache.WriteFilesWithCode(Writer);
      }
+
+      void ClearCodeCache(FEXCore::Core::InternalThreadState *Thread) override;
      void InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length) override;
      void InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length, CodeRangeInvalidationFn callback) override;
-      void MarkMemoryShared() override;
+      FEXCore::ForkableSharedMutex &GetCodeInvalidationMutex() override {
+        return CodeInvalidationMutex;
+      }
+
+      void MarkMemoryShared(FEXCore::Core::InternalThreadState *Thread) override;

      void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, fextl::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) override;
+
+      bool IsAddressInCodeBuffer(FEXCore::Core::InternalThreadState *Thread, uintptr_t Address) const override;
+
      // returns false if a handler was already registered
-      CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void *Creator = nullptr, void *Data = nullptr) override;
+      CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void *Creator = nullptr, void *Data = nullptr);

      void AppendThunkDefinitions(fextl::vector<FEXCore::IR::ThunkDefinition> const& Definitions) override;

@@ -199,9 +197,6 @@ namespace FEXCore::Context {
  #ifdef JIT_ARM64
    friend class FEXCore::CPU::Arm64JITCore;
  #endif
-  #ifdef JIT_X86_64
-    friend class FEXCore::CPU::X86JITCore;
-  #endif

    friend class FEXCore::IR::Validation::IRValidation;

@@ -232,7 +227,6 @@ namespace FEXCore::Context {
      FEX_CONFIG_OPT(ThunkHostLibsPath, THUNKHOSTLIBS);
      FEX_CONFIG_OPT(ThunkHostLibsPath32, THUNKHOSTLIBS32);
      FEX_CONFIG_OPT(ThunkConfigFile, THUNKCONFIG);
-      FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
      FEX_CONFIG_OPT(GlobalJITNaming, GLOBALJITNAMING);
      FEX_CONFIG_OPT(LibraryJITNaming, LIBRARYJITNAMING);
      FEX_CONFIG_OPT(BlockJITNaming, BLOCKJITNAMING);
@@ -242,25 +236,16 @@ namespace FEXCore::Context {
      FEX_CONFIG_OPT(x87ReducedPrecision, X87REDUCEDPRECISION);
      FEX_CONFIG_OPT(DisableTelemetry, DISABLETELEMETRY);
      FEX_CONFIG_OPT(DisableVixlIndirectCalls, DISABLE_VIXL_INDIRECT_RUNTIME_CALLS);
+      FEX_CONFIG_OPT(SmallTSCScale, SMALLTSCSCALE);
    } Config;

-    FEXCore::HostFeatures HostFeatures;

-    std::mutex ThreadCreationMutex;
-    FEXCore::Core::InternalThreadState* ParentThread{};
-    fextl::vector<FEXCore::Core::InternalThreadState*> Threads;
    std::atomic_bool CoreShuttingDown{false};
-    bool NeedToCheckXID{true};
-
-    std::mutex IdleWaitMutex;
-    std::condition_variable IdleWaitCV;
-    std::atomic<uint32_t> IdleWaitRefCount{};
-
-    Event PauseWait;
-    bool Running{};

    FEXCore::ForkableSharedMutex CodeInvalidationMutex;

+    FEXCore::HostFeatures HostFeatures;
+    // CPUID depends on HostFeatures so needs to be initialized after that.
    FEXCore::CPUIDEmu CPUID;
    FEXCore::HLE::SyscallHandler *SyscallHandler{};
    FEXCore::HLE::SourcecodeResolver *SourcecodeResolver{};
@@ -280,21 +265,15 @@ namespace FEXCore::Context {
    ContextImpl();
    ~ContextImpl();

-    bool IsPaused() const { return !Running; }
-    void WaitForThreadsToRun() override;
-    void Stop(bool IgnoreCurrentThread);
-    void WaitForIdle() override;
-    void SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event);
-
    static void ThreadRemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
-    static void ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker);
+    static void ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, FEXCore::Context::ExitFunctionLinkData *HostLink, const BlockDelinkerFunc &delinker);

    template<auto Fn>
-    static uint64_t ThreadExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, uint64_t *record) {
+    static uint64_t ThreadExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, ExitFunctionLinkData *Record) {
      auto Thread = Frame->Thread;
      auto lk = GuardSignalDeferringSection<std::shared_lock>(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);

-      return Fn(Frame, record);
+      return Fn(Frame, Record);
    }

    // Wrapper which takes CpuStateFrame instead of InternalThreadState and unique_locks CodeInvalidationMutex
@@ -302,7 +281,7 @@ namespace FEXCore::Context {
    static void ThreadRemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
      auto Thread = Frame->Thread;

-      LogMan::Throw::AFmt(Thread->ThreadManager.GetTID() == FHU::Syscalls::gettid(), "Must be called from owning thread {}, not {}", Thread->ThreadManager.GetTID(), FHU::Syscalls::gettid());
+      LOGMAN_THROW_A_FMT(Thread->ThreadManager.GetTID() == FHU::Syscalls::gettid(), "Must be called from owning thread {}, not {}", Thread->ThreadManager.GetTID(), FHU::Syscalls::gettid());
      auto lk = GuardSignalDeferringSection(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);

      ThreadRemoveCodeEntry(Thread, GuestRIP);
@@ -332,9 +311,6 @@ namespace FEXCore::Context {
    [[nodiscard]] CompileCodeResult CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP, uint64_t MaxInst = 0);
    uintptr_t CompileBlock(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP, uint64_t MaxInst = 0);

-    // same as CompileBlock, but aborts on failure
-    void CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);
-
    // Used for thread creation from syscalls
    /**
     * @brief Initializes TID, PID and TLS data for a thread
@@ -359,10 +335,6 @@ namespace FEXCore::Context {
      }
    }

-    void IncrementIdleRefCount() override {
-      ++IdleWaitRefCount;
-    }
-
    FEXCore::Utils::PooledAllocatorVirtual OpDispatcherAllocator;
    FEXCore::Utils::PooledAllocatorVirtual FrontendAllocator;

@@ -392,18 +364,9 @@ namespace FEXCore::Context {

    bool ExitOnHLTEnabled() const { return ExitOnHLT; }

-    ThreadsState GetThreads() override  {
-      return ThreadsState {
-        .ParentThread = ParentThread,
-        .Threads = &Threads,
-      };
-    }
-
    FEXCore::CPU::CPUBackendFeatures BackendFeatures;

  protected:
-    void ClearCodeCache(FEXCore::Core::InternalThreadState *Thread);
-
    void UpdateAtomicTSOEmulationConfig() {
      if (SupportsHardwareTSO) {
        // If the hardware supports TSO then we don't need to emulate it through atomics.
@@ -425,15 +388,8 @@ namespace FEXCore::Context {
     */
    void InitializeCompiler(FEXCore::Core::InternalThreadState* Thread);

-    void WaitForIdleWithTimeout();
-
-    void NotifyPause();
-
    void AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr);

-    // Entry Cache
-    std::mutex ExitMutex;
-
    IR::AOTIRCaptureCache IRCaptureCache;
    fextl::unique_ptr<FEXCore::CodeSerialize::CodeObjectSerializeService> CodeObjectCacheService;

@@ -445,9 +401,7 @@ namespace FEXCore::Context {
    FEX_CONFIG_OPT(AppFilename, APP_FILENAME);

    std::shared_mutex CustomIRMutex;
+    std::atomic<bool> HasCustomIRHandlers{};
    fextl::unordered_map<uint64_t, std::tuple<CustomIREntrypointHandler, void *, void *>> CustomIRHandlers;
-    FEXCore::CPU::DispatcherConfig DispatcherConfig;
  };
-
-  uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::CpuStateFrame *Frame, FEXCore::HLE::SyscallArguments *Args);
 }
@@ -9,10 +9,11 @@
 #include "Interface/HLE/Thunks/Thunks.h"

 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Utils/BitUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>

+#include <FEXHeaderUtils/BitUtils.h>
+
 #include <aarch64/cpu-aarch64.h>
 #include <aarch64/instructions-aarch64.h>
 #include <cpu-features.h>
@@ -28,6 +29,7 @@ namespace FEXCore::CPU {
 // TODO: Allow x18 register allocation on Linux in the future to gain one more register.

 namespace x64 {
+#ifndef _M_ARM_64EC
  // All but x19 and x29 are caller saved
  constexpr std::array<FEXCore::ARMEmitter::Register, 18> SRA = {
    FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5,
@@ -81,6 +83,54 @@ namespace x64 {
    FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
    FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
  };
+#else
+   constexpr std::array<FEXCore::ARMEmitter::Register, 18> SRA = {
+    FEXCore::ARMEmitter::Reg::r8, FEXCore::ARMEmitter::Reg::r0,
+    FEXCore::ARMEmitter::Reg::r1, FEXCore::ARMEmitter::Reg::r27,
+    // SP's register location isn't specified by the ARM64EC ABI, we choose to use r23
+    FEXCore::ARMEmitter::Reg::r23, FEXCore::ARMEmitter::Reg::r29,
+    FEXCore::ARMEmitter::Reg::r25, FEXCore::ARMEmitter::Reg::r26,
+    FEXCore::ARMEmitter::Reg::r2, FEXCore::ARMEmitter::Reg::r3,
+    FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5,
+    FEXCore::ARMEmitter::Reg::r19, FEXCore::ARMEmitter::Reg::r20,
+    FEXCore::ARMEmitter::Reg::r21, FEXCore::ARMEmitter::Reg::r22,
+    REG_PF, REG_AF,
+  };
+
+  constexpr std::array<FEXCore::ARMEmitter::Register, 7> RA = {
+    FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7,
+    FEXCore::ARMEmitter::Reg::r14,FEXCore::ARMEmitter::Reg::r15,
+    FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17,
+    FEXCore::ARMEmitter::Reg::r30,
+  };
+
+  constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 3> RAPair = {{
+    {FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7},
+    {FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15},
+    {FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17},
+  }};
+
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 16> SRAFPR = {
+    FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1,
+    FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
+    FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
+    FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
+    FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9,
+    FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11,
+    FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
+    FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+  };
+
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 14> RAFPR = {
+    FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19,
+    FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21,
+    FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23,
+    FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25,
+    FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27,
+    FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29,
+    FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31
+  };
+#endif

  // I wish this could get constexpr generated from SRA's definition but impossible until libstdc++12, libc++15.
  // SRA GPRs that need to be spilled when calling a function with `preserve_all` ABI.
@@ -340,7 +390,7 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl *ctx, void* EmissionPtr
  : Emitter(static_cast<uint8_t*>(EmissionPtr), size)
  , EmitterCTX {ctx}
 #ifdef VIXL_SIMULATOR
-  , Simulator {&SimDecoder}
+  , Simulator {&SimDecoder, stdout, vixl::aarch64::SimStack(SimulatorStackSize).Allocate()}
 #endif
 {
 #ifdef VIXL_SIMULATOR
@@ -353,8 +403,10 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl *ctx, void* EmissionPtr
  // Only setup the disassembler if enabled.
  // vixl's decoder is expensive to setup.
  if (Disassemble()) {
+    DisasmBuffer.resize(DISASM_BUFFER_SIZE);
+    Disasm = fextl::make_unique<vixl::aarch64::Disassembler>(DisasmBuffer.data(), DISASM_BUFFER_SIZE);
    DisasmDecoder = fextl::make_unique<vixl::aarch64::Decoder>();
-    DisasmDecoder->AppendVisitor(&Disasm);
+    DisasmDecoder->AppendVisitor(Disasm.get());
  }
 #endif

@@ -367,6 +419,9 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl *ctx, void* EmissionPtr
    GeneralPairRegisters = x64::RAPair;
    StaticFPRegisters = x64::SRAFPR;
    GeneralFPRegisters = x64::RAFPR;
+#ifdef _M_ARM_64EC
+    ConfiguredDynamicRegisterBase = std::span(x64::RA.begin(), 7);
+#endif
  }
  else {
    ConfiguredDynamicRegisterBase = std::span(x32::RA.begin() + 6, 8);
@@ -611,10 +666,6 @@ void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FP
  mrs(TmpReg, ARMEmitter::SystemRegister::NZCV);
  str(TmpReg.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));

-  if (!StaticRegisterAllocation()) {
-    return;
-  }
-
  // PF/AF are special, remove them from the mask
  uint32_t PFAFMask = ((1u << REG_PF.Idx()) | ((1u << REG_AF.Idx())));
  unsigned PFAFSpillMask = GPRSpillMask & PFAFMask;
@@ -728,10 +779,6 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
  ldr(TmpReg.W(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.flags[24]));
  msr(ARMEmitter::SystemRegister::NZCV, TmpReg);

-  if (!StaticRegisterAllocation()) {
-    return;
-  }
-
  if (FPRs) {
    // Set up predicate registers.
    // We don't bother spilling these in SpillStaticRegs,
@@ -936,7 +983,9 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
  // Push the general registers.
  PushGeneralRegisters(TmpReg, ConfiguredDynamicRegisterBase);

+#ifndef _M_ARM_64EC
  str(ARMEmitter::XReg::lr, TmpReg, 0);
+#endif
 }

 void Arm64Emitter::PopDynamicRegsAndLR() {
@@ -948,7 +997,9 @@ void Arm64Emitter::PopDynamicRegsAndLR() {
  // Pop GPRs second
  PopGeneralRegisters(ConfiguredDynamicRegisterBase);

+#ifndef _M_ARM_64EC
  ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
+#endif
 }

 void Arm64Emitter::SpillForPreserveAllABICall(FEXCore::ARMEmitter::Register TmpReg, bool FPRs) {
@@ -21,6 +21,7 @@
 #endif

 #include <FEXCore/Config/Config.h>
+#include <FEXCore/fextl/vector.h>

 #include <array>
 #include <cstddef>
@@ -36,16 +37,37 @@ namespace FEXCore::CPU {
 // Contains the address to the currently available CPU state
 constexpr auto STATE = FEXCore::ARMEmitter::XReg::x28;

+#ifndef _M_ARM_64EC
 // GPR temporaries. Only x3 can be used across spill boundaries
 // so if these ever need to change, be very careful about that.
 constexpr auto TMP1 = FEXCore::ARMEmitter::XReg::x0;
 constexpr auto TMP2 = FEXCore::ARMEmitter::XReg::x1;
 constexpr auto TMP3 = FEXCore::ARMEmitter::XReg::x2;
 constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x3;
+constexpr bool TMP_ABIARGS = true;
+
+// We pin r26/r27 as PF/AF respectively, this is internal FEX ABI.
+constexpr auto REG_PF = FEXCore::ARMEmitter::Reg::r26;
+constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r27;

 // Vector temporaries
 constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v0;
 constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v1;
+#else
+constexpr auto TMP1 = FEXCore::ARMEmitter::XReg::x10;
+constexpr auto TMP2 = FEXCore::ARMEmitter::XReg::x11;
+constexpr auto TMP3 = FEXCore::ARMEmitter::XReg::x12;
+constexpr auto TMP4 = FEXCore::ARMEmitter::XReg::x13;
+constexpr bool TMP_ABIARGS = false;
+
+// We pin r11/r12 as PF/AF respectively for arm64ec, as r26/r27 are used for SRA.
+constexpr auto REG_PF = FEXCore::ARMEmitter::Reg::r9;
+constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r24;
+
+// Vector temporaries
+constexpr auto VTMP1 = FEXCore::ARMEmitter::VReg::v16;
+constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v17;
+#endif

 // Predicate register temporaries (used when AVX support is enabled)
 // PRED_TMP_16B indicates a predicate register that indicates the first 16 bytes set to 1.
@@ -53,9 +75,6 @@ constexpr auto VTMP2 = FEXCore::ARMEmitter::VReg::v1;
 constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_16B = FEXCore::ARMEmitter::PReg::p6;
 constexpr FEXCore::ARMEmitter::PRegister PRED_TMP_32B = FEXCore::ARMEmitter::PReg::p7;

-// We pin r26/r27 as PF/AF respectively, this is internal FEX ABI.
-constexpr auto REG_PF = FEXCore::ARMEmitter::Reg::r26;
-constexpr auto REG_AF = FEXCore::ARMEmitter::Reg::r27;

 // This class contains common emitter utility functions that can
 // be used by both Arm64 JIT and ARM64 Dispatcher
@@ -230,15 +249,17 @@ protected:
 #ifdef VIXL_SIMULATOR
  vixl::aarch64::Decoder SimDecoder;
  vixl::aarch64::Simulator Simulator;
+  constexpr static size_t SimulatorStackSize = 8 * 1024 * 1024;
 #endif

 #ifdef VIXL_DISASSEMBLER
-  vixl::aarch64::Disassembler Disasm;
+  fextl::vector<char> DisasmBuffer;
+  constexpr static int DISASM_BUFFER_SIZE {256};
+  fextl::unique_ptr<vixl::aarch64::Disassembler> Disasm;
  fextl::unique_ptr<vixl::aarch64::Decoder> DisasmDecoder;

  FEX_CONFIG_OPT(Disassemble, DISASSEMBLE);
 #endif
-  FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
 };

 }
@@ -35,8 +35,10 @@ public:
    constexpr uint32_t Op = 0b0001'0000 << 24;
    DataProcessing_PCRel_Imm(Op, rd, Imm);
  }
-  void adr(FEXCore::ARMEmitter::Register rd, ForwardLabel *Label) {
-    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::ADR });
+  template<typename LabelType>
+  requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+  void adr(FEXCore::ARMEmitter::Register rd, LabelType *Label) {
+    AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::ADR });
    constexpr uint32_t Op = 0b0001'0000 << 24;
    DataProcessing_PCRel_Imm(Op, rd, 0);
  }
@@ -62,8 +64,10 @@ public:
    constexpr uint32_t Op = 0b1001'0000 << 24;
    DataProcessing_PCRel_Imm(Op, rd, Imm);
  }
-  void adrp(FEXCore::ARMEmitter::Register rd, ForwardLabel *Label) {
-    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::ADRP });
+  template<typename LabelType>
+  requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+  void adrp(FEXCore::ARMEmitter::Register rd, LabelType *Label) {
+    AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::ADRP });
    constexpr uint32_t Op = 0b1001'0000 << 24;
    DataProcessing_PCRel_Imm(Op, rd, 0);
  }
@@ -105,7 +109,7 @@ public:
    }
  }
  void LongAddressGen(FEXCore::ARMEmitter::Register rd, ForwardLabel* Label) {
-    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::LONG_ADDRESS_GEN });
+    Label->Insts.emplace_back(SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::LONG_ADDRESS_GEN });
    // Emit a register index and a nop. These will be backpatched.
    dc32(rd.Idx());
    nop();
@@ -18,8 +18,10 @@ public:
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 0, Cond, Imm >> 2);
    }
-    void b(FEXCore::ARMEmitter::Condition Cond, ForwardLabel *Label) {
-      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::BC });
+    template<typename LabelType>
+    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+    void b(FEXCore::ARMEmitter::Condition Cond, LabelType *Label) {
+      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 0, Cond, 0);
    }
@@ -45,8 +47,10 @@ public:
      Branch_Conditional(Op, 0, 1, Cond, Imm >> 2);
    }

-    void bc(FEXCore::ARMEmitter::Condition Cond, ForwardLabel *Label) {
-      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::BC });
+    template<typename LabelType>
+    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+    void bc(FEXCore::ARMEmitter::Condition Cond, LabelType *Label) {
+      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });
      constexpr uint32_t Op = 0b0101'010 << 25;
      Branch_Conditional(Op, 0, 1, Cond, 0);
    }
@@ -102,8 +106,10 @@ public:

      UnconditionalBranch(Op, Imm >> 2);
    }
-    void b(ForwardLabel *Label) {
-      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::B });
+    template<typename LabelType>
+    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+    void b(LabelType *Label) {
+      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::B });
      constexpr uint32_t Op = 0b0001'01 << 26;

      UnconditionalBranch(Op, 0);
@@ -131,8 +137,10 @@ public:

      UnconditionalBranch(Op, Imm >> 2);
    }
-    void bl(ForwardLabel *Label) {
-      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::B });
+    template<typename LabelType>
+    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+    void bl(LabelType *Label) {
+      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::B });
      constexpr uint32_t Op = 0b1001'01 << 26;

      UnconditionalBranch(Op, 0);
@@ -163,8 +171,10 @@ public:
      CompareAndBranch(Op, s, rt, Imm >> 2);
    }

-    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, ForwardLabel *Label) {
-      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::BC });
+    template<typename LabelType>
+    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+    void cbz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, LabelType *Label) {
+      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });

      constexpr uint32_t Op = 0b0011'0100 << 24;

@@ -195,8 +205,10 @@ public:
      CompareAndBranch(Op, s, rt, Imm >> 2);
    }

-    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, ForwardLabel *Label) {
-      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::BC });
+    template<typename LabelType>
+    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+    void cbnz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rt, LabelType *Label) {
+      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::BC });

      constexpr uint32_t Op = 0b0011'0101 << 24;

@@ -226,8 +238,11 @@ public:

      TestAndBranch(Op, rt, Bit, Imm >> 2);
    }
-    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, ForwardLabel *Label) {
-      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::TEST_BRANCH });
+
+    template<typename LabelType>
+    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+    void tbz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) {
+      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::TEST_BRANCH });

      constexpr uint32_t Op = 0b0011'0110 << 24;

@@ -256,8 +271,11 @@ public:

      TestAndBranch(Op, rt, Bit, Imm >> 2);
    }
-    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, ForwardLabel *Label) {
-      Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::TEST_BRANCH });
+
+    template<typename LabelType>
+    requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+    void tbnz(FEXCore::ARMEmitter::Register rt, uint32_t Bit, LabelType *Label) {
+      AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::TEST_BRANCH });
      constexpr uint32_t Op = 0b0011'0111 << 24;

      TestAndBranch(Op, rt, Bit, 0);
@@ -4,13 +4,14 @@
 #include "Interface/Core/ArchHelpers/CodeEmitter/Buffer.h"
 #include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"

-#include <FEXCore/Utils/BitUtils.h>
 #include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>
 #include <FEXCore/fextl/vector.h>

+#include <FEXHeaderUtils/BitUtils.h>
+
 #include <aarch64/assembler-aarch64.h>

 #include <array>
@@ -537,27 +538,29 @@ namespace FEXCore::ARMEmitter {
    uint8_t *Location{};
  };

-  /* This `ForwardLabel` struct used for retaining a location for PC-Relative instructions.
+  /* This `SingleUseForwardLabel` struct used for retaining a location for PC-Relative instructions.
   * This is specifically a label for a target that is logically `above` an instruction that uses it.
   * Which means that a branch would jump forwards.
   *
-   * This can be bound to multiple instructions, so it needs a vector for each bind instruction type.
+   * The `ForwardLabel` struct can be bound to multiple instructions, so it needs a vector for each bind instruction type.
   */
-  struct ForwardLabel {
-    struct Instructions {
-      enum class InstType {
-        ADR,
-        ADRP,
-        B,
-        BC,
-        TEST_BRANCH,
-        RELATIVE_LOAD,
-        LONG_ADDRESS_GEN,
-      };
-      uint8_t *Location{};
-      InstType Type;
+  struct SingleUseForwardLabel {
+    enum class InstType {
+      UNKNOWN,
+      ADR,
+      ADRP,
+      B,
+      BC,
+      TEST_BRANCH,
+      RELATIVE_LOAD,
+      LONG_ADDRESS_GEN,
    };
-    fextl::vector<Instructions> Insts{};
+    uint8_t *Location{};
+    InstType Type = InstType::UNKNOWN;
+  };
+
+  struct ForwardLabel {
+    fextl::vector<SingleUseForwardLabel> Insts{};
  };

  /* This `BiDirectionalLabel` struct used for retaining a location for PC-Relative instructions.
@@ -569,6 +572,15 @@ namespace FEXCore::ARMEmitter {
    ForwardLabel Forward;
  };

+  static inline void AddLocationToLabel(SingleUseForwardLabel *Label, SingleUseForwardLabel&& Location) {
+    LOGMAN_THROW_A_FMT(Label->Type == SingleUseForwardLabel::InstType::UNKNOWN, "Trying to bind a SingleUseForwardLabel to multiple locations. Use ForwardLabel instead.");
+    *Label = std::move(Location);
+  }
+
+  static inline void AddLocationToLabel(ForwardLabel *Label, SingleUseForwardLabel&& Location) {
+    Label->Insts.emplace_back(std::move(Location));
+  }
+
  // Some FCMA ASIMD instructions support a rotation argument.
  enum class Rotation : uint32_t {
    ROTATE_0   = 0b00,
@@ -628,6 +640,121 @@ namespace FEXCore::ARMEmitter {
      Label->Location = GetCursorAddress<uint8_t*>();
    }

+    void Bind(const SingleUseForwardLabel *Label) {
+      uint8_t *CurrentAddress = GetCursorAddress<uint8_t*>();
+      // Patch up the instructions
+      switch (Label->Type) {
+        case SingleUseForwardLabel::InstType::ADR: {
+          uint32_t *Instruction = reinterpret_cast<uint32_t*>(Label->Location);
+          int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+          LOGMAN_THROW_A_FMT(IsADRRange(Imm), "Unscaled offset too large");
+          uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
+          uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
+          uint32_t Inst = *Instruction & ~InstMask;
+          Inst |= (Offset & 0b11) << 29;
+          Inst |= (Offset >> 2) << 5;
+          *Instruction = Inst;
+          break;
+        }
+        case SingleUseForwardLabel::InstType::ADRP: {
+          uint32_t *Instruction = reinterpret_cast<uint32_t*>(Label->Location);
+          int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+          LOGMAN_THROW_A_FMT(IsADRPRange(Imm) && IsADRPAligned(Imm), "Unscaled offset too large");
+          Imm >>= 12;
+          uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
+          uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
+          uint32_t Inst = *Instruction & ~InstMask;
+          Inst |= (Offset & 0b11) << 29;
+          Inst |= (Offset >> 2) << 5;
+          *Instruction = Inst;
+          break;
+        }
+
+        case SingleUseForwardLabel::InstType::B: {
+          uint32_t *Instruction = reinterpret_cast<uint32_t*>(Label->Location);
+          int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+          LOGMAN_THROW_A_FMT(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+          Imm >>= 2;
+          uint32_t InstMask = 0x3FF'FFFF;
+          uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
+          uint32_t Inst = *Instruction & ~InstMask;
+          Inst |= Offset;
+          *Instruction = Inst;
+
+          break;
+        }
+
+        case SingleUseForwardLabel::InstType::TEST_BRANCH: {
+          uint32_t *Instruction = reinterpret_cast<uint32_t*>(Label->Location);
+          int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+          LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+          Imm >>= 2;
+          uint32_t InstMask = 0x3FFF;
+          uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
+          uint32_t Inst = *Instruction & ~(InstMask << 5);
+          Inst |= Offset << 5;
+          *Instruction = Inst;
+
+          break;
+        }
+        case SingleUseForwardLabel::InstType::BC:
+        case SingleUseForwardLabel::InstType::RELATIVE_LOAD: {
+          uint32_t *Instruction = reinterpret_cast<uint32_t*>(Label->Location);
+          int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
+          LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
+          Imm >>= 2;
+          uint32_t InstMask = 0x7'FFFF;
+          uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
+          uint32_t Inst = *Instruction & ~(InstMask << 5);
+          Inst |= Offset << 5;
+          *Instruction = Inst;
+          break;
+        }
+        case SingleUseForwardLabel::InstType::LONG_ADDRESS_GEN: {
+          uint32_t *Instructions = reinterpret_cast<uint32_t*>(Label->Location);
+          int64_t ImmInstOne = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(&Instructions[0]);
+          int64_t ImmInstTwo = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(&Instructions[1]);
+          auto OriginalOffset = GetCursorOffset();
+
+          auto InstOffset = GetCursorOffsetFromAddress(Instructions);
+          SetCursorOffset(InstOffset);
+
+          // We encoded the destination register in to the first instruction space.
+          // Read it back.
+          ARMEmitter::Register DestReg(Instructions[0]);
+
+          if (IsADRRange(ImmInstTwo)) {
+            // If within ADR range from the second instruction, then we can emit NOP+ADR
+            nop();
+            adr(DestReg, static_cast<uint32_t>(ImmInstTwo) & 0x7FFF);
+          }
+          else if (IsADRPRange(ImmInstOne)) {
+
+            // If within ADRP range from the first instruction, then we are /definitely/ in range for the second instruction.
+            // First check if we are in non-offset range for second instruction.
+            if (IsADRPAligned(reinterpret_cast<uint64_t>(CurrentAddress))) {
+              // We can emit nop + adrp
+              nop();
+              adrp(DestReg, static_cast<uint32_t>(ImmInstTwo >> 12) & 0x7FFF);
+            }
+            else {
+              // Not aligned, need adrp + add
+              adrp(DestReg, static_cast<uint32_t>(ImmInstOne >> 12) & 0x7FFF);
+              add(ARMEmitter::Size::i64Bit, DestReg, DestReg, ImmInstOne & 0xFFF);
+            }
+          }
+          else {
+            LOGMAN_MSG_A_FMT("Unscaled offset is too large");
+            FEX_UNREACHABLE;
+          }
+
+          SetCursorOffset(OriginalOffset);
+          break;
+        }
+        default: LOGMAN_MSG_A_FMT("Unexpected inst type in label fixup");
+      }
+    }
+
    // Bind a forward label to a location.
    // This walks all the instructions in the label's vector.
    // Then backpatching all instructions that have used the label.
@@ -636,119 +763,8 @@ namespace FEXCore::ARMEmitter {
      if constexpr (WarnAboutEmpty) {
        LOGMAN_THROW_A_FMT(Label->Insts.empty() == false, "Binding forward label that didn't have any instructions using it");
      }
-      uint8_t *CurrentAddress = GetCursorAddress<uint8_t*>();
-      for (const auto &Inst : Label->Insts) {
-        // Patch up the instructions
-        switch (Inst.Type) {
-          case ForwardLabel::Instructions::InstType::ADR: {
-            uint32_t *Instruction = reinterpret_cast<uint32_t*>(Inst.Location);
-            int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-            LOGMAN_THROW_A_FMT(IsADRRange(Imm), "Unscaled offset too large");
-            uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
-            uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
-            uint32_t Inst = *Instruction & ~InstMask;
-            Inst |= (Offset & 0b11) << 29;
-            Inst |= (Offset >> 2) << 5;
-            *Instruction = Inst;
-            break;
-          }
-          case ForwardLabel::Instructions::InstType::ADRP: {
-            uint32_t *Instruction = reinterpret_cast<uint32_t*>(Inst.Location);
-            int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-            LOGMAN_THROW_A_FMT(IsADRPRange(Imm) && IsADRPAligned(Imm), "Unscaled offset too large");
-            Imm >>= 12;
-            uint32_t InstMask = 0b11 << 29 | 0b1111'1111'1111'1111'111 << 5;
-            uint32_t Offset = static_cast<uint32_t>(Imm) & 0x3F'FFFF;
-            uint32_t Inst = *Instruction & ~InstMask;
-            Inst |= (Offset & 0b11) << 29;
-            Inst |= (Offset >> 2) << 5;
-            *Instruction = Inst;
-            break;
-          }
-
-          case ForwardLabel::Instructions::InstType::B: {
-            uint32_t *Instruction = reinterpret_cast<uint32_t*>(Inst.Location);
-            int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-            LOGMAN_THROW_A_FMT(Imm >= -134217728 && Imm <= 134217724 && ((Imm & 0b11) == 0), "Unscaled offset too large");
-            Imm >>= 2;
-            uint32_t InstMask = 0x3FF'FFFF;
-            uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
-            uint32_t Inst = *Instruction & ~InstMask;
-            Inst |= Offset;
-            *Instruction = Inst;
-
-            break;
-          }
-
-          case ForwardLabel::Instructions::InstType::TEST_BRANCH: {
-            uint32_t *Instruction = reinterpret_cast<uint32_t*>(Inst.Location);
-            int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-            LOGMAN_THROW_A_FMT(Imm >= -32768 && Imm <= 32764 && ((Imm & 0b11) == 0), "Unscaled offset too large");
-            Imm >>= 2;
-            uint32_t InstMask = 0x3FFF;
-            uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
-            uint32_t Inst = *Instruction & ~(InstMask << 5);
-            Inst |= Offset << 5;
-            *Instruction = Inst;
-
-            break;
-          }
-          case ForwardLabel::Instructions::InstType::BC:
-          case ForwardLabel::Instructions::InstType::RELATIVE_LOAD: {
-            uint32_t *Instruction = reinterpret_cast<uint32_t*>(Inst.Location);
-            int64_t Imm = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(Instruction);
-            LOGMAN_THROW_A_FMT(Imm >= -1048576 && Imm <= 1048575 && ((Imm & 0b11) == 0), "Unscaled offset too large");
-            Imm >>= 2;
-            uint32_t InstMask = 0x7'FFFF;
-            uint32_t Offset = static_cast<uint32_t>(Imm) & InstMask;
-            uint32_t Inst = *Instruction & ~(InstMask << 5);
-            Inst |= Offset << 5;
-            *Instruction = Inst;
-            break;
-          }
-          case ForwardLabel::Instructions::InstType::LONG_ADDRESS_GEN: {
-            uint32_t *Instructions = reinterpret_cast<uint32_t*>(Inst.Location);
-            int64_t ImmInstOne = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(&Instructions[0]);
-            int64_t ImmInstTwo = reinterpret_cast<int64_t>(CurrentAddress) - reinterpret_cast<int64_t>(&Instructions[1]);
-            auto OriginalOffset = GetCursorOffset();
-
-            auto InstOffset = GetCursorOffsetFromAddress(Instructions);
-            SetCursorOffset(InstOffset);
-
-            // We encoded the destination register in to the first instruction space.
-            // Read it back.
-            ARMEmitter::Register DestReg(Instructions[0]);
-
-            if (IsADRRange(ImmInstTwo)) {
-              // If within ADR range from the second instruction, then we can emit NOP+ADR
-              nop();
-              adr(DestReg, static_cast<uint32_t>(ImmInstTwo) & 0x7FFF);
-            }
-            else if (IsADRPRange(ImmInstOne)) {
-
-              // If within ADRP range from the first instruction, then we are /definitely/ in range for the second instruction.
-              // First check if we are in non-offset range for second instruction.
-              if (IsADRPAligned(reinterpret_cast<uint64_t>(CurrentAddress))) {
-                // We can emit nop + adrp
-                nop();
-                adrp(DestReg, static_cast<uint32_t>(ImmInstTwo >> 12) & 0x7FFF);
-              }
-              else {
-                // Not aligned, need adrp + add
-                adrp(DestReg, static_cast<uint32_t>(ImmInstOne >> 12) & 0x7FFF);
-                add(ARMEmitter::Size::i64Bit, DestReg, DestReg, ImmInstOne & 0xFFF);
-              }
-            }
-            else {
-              LOGMAN_MSG_A_FMT("Unscaled offset is too large");
-              FEX_UNREACHABLE;
-            }
-
-            SetCursorOffset(OriginalOffset);
-            break;
-          }
-          default: LOGMAN_MSG_A_FMT("Unexpected inst type in label fixup");
-        }
+      for (auto &Inst : Label->Insts) {
+        Bind(&Inst);
      }
    }

@@ -2121,38 +2121,58 @@ public:
    LoadStoreLiteral(Op, prfop, static_cast<uint32_t>(Imm >> 2) & 0x7'FFFF);
  }

-  void ldr(FEXCore::ARMEmitter::WRegister rt, ForwardLabel *Label) {
-    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::RELATIVE_LOAD });
+  template<typename LabelType>
+  requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+  void ldr(FEXCore::ARMEmitter::WRegister rt, LabelType *Label) {
+    AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD });
    constexpr uint32_t Op = 0b0001'1000 << 24;
    LoadStoreLiteral(Op, rt, 0);
  }
-  void ldr(FEXCore::ARMEmitter::SRegister rt, ForwardLabel *Label) {
-    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::RELATIVE_LOAD });
+
+  template<typename LabelType>
+  requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+  void ldr(FEXCore::ARMEmitter::SRegister rt, LabelType *Label) {
+    AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD });
    constexpr uint32_t Op = 0b0001'1100 << 24;
    LoadStoreLiteral(Op, rt, 0);
  }
-  void ldr(FEXCore::ARMEmitter::XRegister rt, ForwardLabel *Label) {
-    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::RELATIVE_LOAD });
+
+  template<typename LabelType>
+  requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+  void ldr(FEXCore::ARMEmitter::XRegister rt, LabelType *Label) {
+    AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD });
    constexpr uint32_t Op = 0b0101'1000 << 24;
    LoadStoreLiteral(Op, rt, 0);
  }
-  void ldr(FEXCore::ARMEmitter::DRegister rt, ForwardLabel *Label) {
-    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::RELATIVE_LOAD });
+
+  template<typename LabelType>
+  requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+  void ldr(FEXCore::ARMEmitter::DRegister rt, LabelType *Label) {
+    AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD });
    constexpr uint32_t Op = 0b0101'1100 << 24;
    LoadStoreLiteral(Op, rt, 0);
  }
-  void ldrsw(FEXCore::ARMEmitter::XRegister rt, ForwardLabel *Label) {
-    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::RELATIVE_LOAD });
+
+  template<typename LabelType>
+  requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+  void ldrsw(FEXCore::ARMEmitter::XRegister rt, LabelType *Label) {
+    AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD });
    constexpr uint32_t Op = 0b1001'1000 << 24;
    LoadStoreLiteral(Op, rt, 0);
  }
-  void ldr(FEXCore::ARMEmitter::QRegister rt, ForwardLabel *Label) {
-    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::RELATIVE_LOAD });
+
+  template<typename LabelType>
+  requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+  void ldr(FEXCore::ARMEmitter::QRegister rt, LabelType *Label) {
+    AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD });
    constexpr uint32_t Op = 0b1001'1100 << 24;
    LoadStoreLiteral(Op, rt, 0);
  }
-  void prfm(FEXCore::ARMEmitter::Prefetch prfop, ForwardLabel *Label) {
-    Label->Insts.emplace_back(ForwardLabel::Instructions{ .Location = GetCursorAddress<uint8_t*>(), .Type = ForwardLabel::Instructions::InstType::RELATIVE_LOAD });
+
+  template<typename LabelType>
+  requires (std::is_same_v<LabelType, ForwardLabel> || std::is_same_v<LabelType, SingleUseForwardLabel>)
+  void prfm(FEXCore::ARMEmitter::Prefetch prfop, LabelType *Label) {
+    AddLocationToLabel(Label, SingleUseForwardLabel{ .Location = GetCursorAddress<uint8_t*>(), .Type = SingleUseForwardLabel::InstType::RELATIVE_LOAD });
    constexpr uint32_t Op = 0b1101'1000 << 24;
    LoadStoreLiteral(Op, prfop, 0);
  }
@@ -3742,7 +3762,12 @@ public:
    }
    else {
      if (MemSrc.MetaType.ImmType.Index == ARMEmitter::IndexType::OFFSET) {
-        prfm(prfop, MemSrc.rn, MemSrc.MetaType.ImmType.Imm);
+        if ((MemSrc.MetaType.ImmType.Imm & 0b111) || MemSrc.MetaType.ImmType.Imm < 0) {
+          prfum<IndexType::OFFSET>(prfop, MemSrc.rn, MemSrc.MetaType.ImmType.Imm);
+        }
+        else {
+          prfm(prfop, MemSrc.rn, MemSrc.MetaType.ImmType.Imm);
+        }
      }
      else {
        LOGMAN_MSG_A_FMT("Unexpected loadstore index type");
@@ -2,8 +2,12 @@
 #include "FEXCore/IR/IR.h"
 #include "FEXCore/Utils/AllocatorHooks.h"
 #include "Interface/Context/Context.h"
+#include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
-#include <FEXCore/Core/CPUBackend.h>
+
+#ifndef _WIN32
+#include <sys/prctl.h>
+#endif

 namespace FEXCore {
 namespace CPU {
@@ -23,6 +27,8 @@ constexpr static uint64_t NamedVectorConstants[FEXCore::IR::NamedVectorConstant:
  {0x0706'0504'0302'0100ULL, 0x0F0E'0D0C'FFFF'FFFFULL}, // NAMED_VECTOR_BLENDPS_1011B
  {0xFFFF'FFFF'0302'0100ULL, 0x0F0E'0D0C'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_1101B
  {0x0706'0504'FFFF'FFFFULL, 0x0F0E'0D0C'0B0A'0908ULL}, // NAMED_VECTOR_BLENDPS_1110B
+  {0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB
+  {0x8040'2010'0804'0201ULL, 0x8040'2010'0804'0201ULL}, // NAMED_VECTOR_MOVMASKB_UPPER
 };

 constexpr static auto PSHUFLW_LUT {
@@ -349,6 +355,31 @@ auto CPUBackend::GetEmptyCodeBuffer() -> CodeBuffer * {
 }

 auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
+#ifndef _WIN32
+// MDWE (Memory-Deny-Write-Execute) is a new Linux 6.3 feature.
+// It's equivalent to systemd's `MemoryDenyWriteExecute` but implemented entirely in the kernel.
+//
+// MDWE prevents applications from creating RWX memory mappings.
+// This prevents FEX from doing anything JIT related, as FEX uses RWX for JIT memory mappings.
+//
+// A potential workaround to make FEX work with MDWE is to call mprotect every time we need to write or modify code.
+// Alternatively, FEX could use a memory mirror where one half is mapped as RW and the other is RX.
+//
+// Once MDWE is enabled with the prctl, the feature is sealed and it can /NOT/ be turned off.
+//
+// Status of MDWE is queried through prctl using `PR_GET_MDWE`:
+// -1: The kernel doesn't support MDWE
+// 0: MDWE is supported but disabled
+// >0: MDWE is enabled, hence prohibiting RWX mappings
+#ifndef PR_GET_MDWE
+#define PR_GET_MDWE 66
+#endif
+  int MDWE = ::prctl(PR_GET_MDWE, 0, 0, 0, 0);
+  if (MDWE != -1 && MDWE != 0) {
+    LogMan::Msg::EFmt("MDWE was set to 0x{:x} which means FEX can't allocate executable memory", MDWE);
+  }
+#endif
+
  CodeBuffer Buffer;
  Buffer.Size = Size;
  Buffer.Ptr = static_cast<uint8_t *>(
@@ -35,7 +35,6 @@ namespace CodeSerialize {

 namespace CPU {
  struct CPUBackendFeatures {
-    bool SupportsStaticRegisterAllocation = false;
    bool SupportsFlags = false;
    bool SupportsSaturatingRoundingShifts = false;
    bool SupportsVTBL2 = false;
@@ -99,6 +98,11 @@ namespace CPU {

      // Offset after this block to the start of the RIP entries.
      uint32_t OffsetToRIPEntries;
+
+      // Shared-code modification spin-loop futex.
+      uint32_t SpinLockFutex;
+
+      uint32_t _Pad;
    };

    // Entries that live after the JITCodeTail.
@@ -98,7 +98,7 @@ constexpr uint32_t FAMILY_IDENTIFIER =
 #endif

 #ifdef _M_ARM_64
-static uint32_t GetCycleCounterFrequency() {
+uint32_t GetCycleCounterFrequency() {
  uint64_t Result{};
  __asm("mrs %[Res], CNTFRQ_EL0"
      : [Res] "=r" (Result));
@@ -349,7 +349,7 @@ void CPUIDEmu::SetupHostHybridFlag() {
 }

 #else
-static uint32_t GetCycleCounterFrequency() {
+uint32_t GetCycleCounterFrequency() {
  return 0;
 }

@@ -358,6 +358,34 @@ void CPUIDEmu::SetupHostHybridFlag() {

 #endif

+
+void CPUIDEmu::SetupFeatures() {
+  // TODO: Enable once AVX is supported.
+  if (false && CTX->HostFeatures.SupportsAVX) {
+    XCR0 |= XCR0_AVX;
+  }
+
+  // Override features if the user has specifically called for it.
+  FEX_CONFIG_OPT(CPUIDFeatures, CPUID);
+  if (!CPUIDFeatures()) {
+    // Early exit if no features are overriden.
+    return;
+  }
+
+#define ENABLE_DISABLE_OPTION(FeatureName, name, enum_name) \
+    do { \
+    const bool Disable##name = (CPUIDFeatures() & FEXCore::Config::CPUID::DISABLE##enum_name) != 0; \
+    const bool Enable##name = (CPUIDFeatures() & FEXCore::Config::CPUID::ENABLE##enum_name) != 0;   \
+      LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive"); \
+      const bool AlreadyEnabled = Features.FeatureName; \
+      const bool Result = (AlreadyEnabled | Enable##name) & !Disable##name; \
+      Features.FeatureName = Result; \
+    } while (0)
+
+  ENABLE_DISABLE_OPTION(SHA, SHA, SHA);
+#undef ENABLE_DISABLE_OPTION
+}
+
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0h(uint32_t Leaf) const {
  FEXCore::CPUID::FunctionResults Res{};

@@ -639,7 +667,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
      (0 << 26) | // Reserved
      (0 << 27) | // Reserved
      (0 << 28) | // Reserved
-      (1 << 29) | // SHA instructions
+      (Features.SHA << 29) | // SHA instructions
      (0 << 30) | // Reserved
      (0 << 31);  // Reserved

@@ -666,7 +694,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
      (0 << 19) | // MPX MAWAU
      (0 << 20) | // MPX MAWAU
      (0 << 21) | // MPX MAWAU
-      (0 << 22) | // RDPID Read Processor ID
+      (1 << 22) | // RDPID Read Processor ID
      (0 << 23) | // Reserved
      (0 << 24) | // Reserved
      (0 << 25) | // CLDEMOTE
@@ -775,7 +803,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_15h(uint32_t Leaf) const {
  uint32_t FrequencyHz = GetCycleCounterFrequency();
  if (FrequencyHz) {
    Res.eax = 1;
-    Res.ebx = 1;
+    Res.ebx = CTX->Config.SmallTSCScale() ? FEXCore::Context::TSC_SCALE : 1;
    Res.ecx = FrequencyHz;
  }
  return Res;
@@ -1205,17 +1233,14 @@ FEXCore::CPUID::XCRResults CPUIDEmu::XCRFunction_0h() const {
  return Res;
 }

-void CPUIDEmu::Init(FEXCore::Context::ContextImpl *ctx) {
-  CTX = ctx;
+CPUIDEmu::CPUIDEmu(FEXCore::Context::ContextImpl const *ctx)
+  : CTX {ctx} {
  Cores = FEXCore::CPUInfo::CalculateNumberOfCPUs();

  // Setup some state tracking
  SetupHostHybridFlag();

-  // TODO: Enable once AVX is supported.
-  if (false && CTX->HostFeatures.SupportsAVX) {
-    XCR0 |= XCR0_AVX;
-  }
+  SetupFeatures();
 }
 }

@@ -14,6 +14,8 @@ namespace Context {
  class ContextImpl;
 }

+uint32_t GetCycleCounterFrequency();
+
 // Debugging define to switch what family of CPU we execute as.
 // Might be useful if an application makes an assumption about a CPU.
 // #define CPUID_AMD
@@ -28,12 +30,12 @@ private:
  constexpr static uint32_t CPUID_VENDOR_AMD3 = 0x444D4163; // "cAMD"

 public:
+  CPUIDEmu(FEXCore::Context::ContextImpl const *ctx);
+
  // X86 cacheline size effectively has to be hardcoded to 64
  // if we report anything differently then applications are likely to break
  constexpr static uint64_t CACHELINE_SIZE = 64;

-  void Init(FEXCore::Context::ContextImpl *ctx);
-
  FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function, uint32_t Leaf) const {
    if (Function < Primary.size()) {
      const auto Handler = Primary[Function];
@@ -111,10 +113,11 @@ public:
  }

 private:
-  FEXCore::Context::ContextImpl *CTX;
+  FEXCore::Context::ContextImpl const *CTX;
  bool Hybrid{};
  uint32_t Cores{};
  FEX_CONFIG_OPT(HideHypervisorBit, HIDEHYPERVISORBIT);
+  FEX_CONFIG_OPT(SmallTSCScale, SMALLTSCSCALE);

  // XFEATURE_ENABLED_MASK
  // Mask that configures what features are enabled on the CPU.
@@ -136,6 +139,15 @@ private:
  constexpr static uint64_t XCR0_SSE = 1ULL << 1;
  constexpr static uint64_t XCR0_AVX = 1ULL << 2;

+  struct FeaturesConfig {
+    uint64_t SHA  : 1;
+    uint64_t _pad : 63;
+  };
+
+  FeaturesConfig Features {
+    .SHA = 1,
+  };
+
  uint64_t XCR0 {
    XCR0_X87 |
    XCR0_SSE
@@ -189,6 +201,7 @@ private:
  FEXCore::CPUID::XCRResults XCRFunction_0h() const;

  void SetupHostHybridFlag();
+  void SetupFeatures();
  static constexpr size_t PRIMARY_FUNCTION_COUNT = 27;
  static constexpr size_t HYPERVISOR_FUNCTION_COUNT = 2;
  static constexpr size_t EXTENDED_FUNCTION_COUNT = 32;
@@ -12,6 +12,7 @@ $end_info$
 #include "Interface/Context/Context.h"
 #include "Interface/Core/ArchHelpers//Arm64Emitter.h"
 #include "Interface/Core/LookupCache.h"
+#include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/Frontend.h"
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
@@ -20,27 +21,24 @@ $end_info$
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/X86Tables/X86Tables.h"
 #include "Interface/HLE/Thunks/Thunks.h"
+#include "Interface/IR/IR.h"
+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 #include "Interface/IR/Passes.h"
 #include "Interface/IR/PassManager.h"
+#include "Interface/IR/RegisterAllocationData.h"
 #include "Utils/Allocator.h"
 #include "Utils/Allocator/HostAllocator.h"

 #include <FEXCore/Config/Config.h>
-#include <FEXCore/Core/CodeLoader.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/HLE/SourcecodeResolver.h>
 #include <FEXCore/HLE/Linux/ThreadManagement.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/File.h>
@@ -78,7 +76,8 @@ $end_info$

 namespace FEXCore::Context {
  ContextImpl::ContextImpl()
-  : IRCaptureCache {this} {
+  : CPUID {this}
+  , IRCaptureCache {this} {
 #ifdef BLOCKSTATS
    BlockData = std::make_unique<FEXCore::BlockSamplingData>();
 #endif
@@ -97,32 +96,19 @@ namespace FEXCore::Context {
      Symbols.InitFile();
    }

+    if (FEXCore::GetCycleCounterFrequency() >= FEXCore::Context::TSC_SCALE_MAXIMUM) {
+      Config.SmallTSCScale = false;
+    }
+
    // Track atomic TSO emulation configuration.
    UpdateAtomicTSOEmulationConfig();
-
-    CPUID.Init(this);
  }

  ContextImpl::~ContextImpl() {
-    if (ParentThread) {
-      DestroyThread(ParentThread);
-    }
-
    {
      if (CodeObjectCacheService) {
        CodeObjectCacheService->Shutdown();
      }
-
-      for (auto &Thread : Threads) {
-        if (Thread->ExecutionThread->joinable()) {
-          Thread->ExecutionThread->join(nullptr);
-        }
-      }
-
-      for (auto &Thread : Threads) {
-        delete Thread;
-      }
-      Threads.clear();
    }
  }

@@ -178,6 +164,7 @@ namespace FEXCore::Context {
        case X86State::RFLAG_ZF_RAW_LOC:
        case X86State::RFLAG_SF_RAW_LOC:
        case X86State::RFLAG_OF_RAW_LOC:
+        case X86State::RFLAG_DF_RAW_LOC:
          // Intentionally do nothing.
          // These contain multiple bits which can corrupt other members when compacted.
          break;
@@ -226,6 +213,11 @@ namespace FEXCore::Context {
    uint32_t AF = ((Frame->State.af_raw ^ PFByte) & (1 << 4)) ? 1 : 0;
    EFLAGS |= AF << X86State::RFLAG_AF_RAW_LOC;

+    // DF is pretransformed, undo the transform from 1/-1 back to 0/1
+    uint8_t DFByte = Frame->State.flags[X86State::RFLAG_DF_RAW_LOC];
+    if (DFByte & 0x80)
+      EFLAGS |= 1 << X86State::RFLAG_DF_RAW_LOC;
+
    return EFLAGS;
  }

@@ -249,6 +241,10 @@ namespace FEXCore::Context {
          // PF is inverted in our internal representation.
          Frame->State.pf_raw = (EFLAGS & (1U << i)) ? 0 : 1;
          break;
+        case X86State::RFLAG_DF_RAW_LOC:
+          // DF is encoded as 1/-1
+          Frame->State.flags[i] = (EFLAGS & (1U << i)) ? 0xff : 1;
+          break;
        default:
          Frame->State.flags[i] = (EFLAGS & (1U << i)) ? 1 : 0;
        break;
@@ -269,7 +265,7 @@ namespace FEXCore::Context {
    Frame->State.flags[X86State::RFLAG_IF_LOC] = 1;
  }

-  FEXCore::Core::InternalThreadState* ContextImpl::InitCore(uint64_t InitialRIP, uint64_t StackPointer) {
+  bool ContextImpl::InitCore() {
    // Initialize the CPU core signal handlers & DispatcherConfig
    switch (Config.Core) {
    case FEXCore::Config::CONFIG_IRJIT:
@@ -279,21 +275,20 @@ namespace FEXCore::Context {
      // Do nothing
      break;
    default:
-      ERROR_AND_DIE_FMT("Unknown core configuration");
-      break;
+      LogMan::Msg::EFmt("Unknown core configuration");
+      return false;
    }

-    DispatcherConfig.StaticRegisterAllocation = Config.StaticRegisterAllocation && BackendFeatures.SupportsStaticRegisterAllocation;
-    Dispatcher = FEXCore::CPU::Dispatcher::Create(this, DispatcherConfig);
+    Dispatcher = FEXCore::CPU::Dispatcher::Create(this);

    // Set up the SignalDelegator config since core is initialized.
    FEXCore::SignalDelegator::SignalDelegatorConfig SignalConfig {
-      .StaticRegisterAllocation = DispatcherConfig.StaticRegisterAllocation,
      .SupportsAVX = HostFeatures.SupportsAVX,

      .DispatcherBegin = Dispatcher->Start,
      .DispatcherEnd = Dispatcher->End,

+      .AbsoluteLoopTopAddress = Dispatcher->AbsoluteLoopTopAddress,
      .AbsoluteLoopTopAddressFillSRA = Dispatcher->AbsoluteLoopTopAddressFillSRA,
      .SignalHandlerReturnAddress = Dispatcher->SignalHandlerReturnAddress,
      .SignalHandlerReturnAddressRT = Dispatcher->SignalHandlerReturnAddressRT,
@@ -331,174 +326,17 @@ namespace FEXCore::Context {
      StartPaused = true;
    }

-    FEXCore::Core::InternalThreadState *Thread = CreateThread(InitialRIP, StackPointer, nullptr, 0);
-
-    // We are the parent thread
-    ParentThread = Thread;
-
-    return Thread;
+    return true;
  }

  void ContextImpl::HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) {
    static_cast<ContextImpl*>(Thread->CTX)->Dispatcher->ExecuteJITCallback(Thread->CurrentFrame, RIP);
  }

-  void ContextImpl::WaitForIdle() {
-    std::unique_lock<std::mutex> lk(IdleWaitMutex);
-    IdleWaitCV.wait(lk, [this] {
-      return IdleWaitRefCount.load() == 0;
-    });
-
-    Running = false;
-  }
-
-  void ContextImpl::WaitForIdleWithTimeout() {
-    std::unique_lock<std::mutex> lk(IdleWaitMutex);
-    bool WaitResult = IdleWaitCV.wait_for(lk, std::chrono::milliseconds(1500),
-      [this] {
-        return IdleWaitRefCount.load() == 0;
-    });
-
-    if (!WaitResult) {
-      // The wait failed, this will occur if we stepped in to a syscall
-      // That's okay, we just need to pause the threads manually
-      NotifyPause();
-    }
-
-    // We have sent every thread a pause signal
-    // Now wait again because they /will/ be going to sleep
-    WaitForIdle();
-  }
-
-  void ContextImpl::NotifyPause() {
-
-    // Tell all the threads that they should pause
-    std::lock_guard<std::mutex> lk(ThreadCreationMutex);
-    for (auto &Thread : Threads) {
-      SignalDelegation->SignalThread(Thread, FEXCore::Core::SignalEvent::Pause);
-    }
-  }
-
-  void ContextImpl::Pause() {
-    // If we aren't running, WaitForIdle will never compete.
-    if (Running) {
-      NotifyPause();
-
-      WaitForIdle();
-    }
-  }
-
-  void ContextImpl::Run() {
-    // Spin up all the threads
-    std::lock_guard<std::mutex> lk(ThreadCreationMutex);
-    for (auto &Thread : Threads) {
-      Thread->SignalReason.store(FEXCore::Core::SignalEvent::Return);
-    }
-
-    for (auto &Thread : Threads) {
-      Thread->StartRunning.NotifyAll();
-    }
-  }
-
-  void ContextImpl::WaitForThreadsToRun() {
-    size_t NumThreads{};
-    {
-      std::lock_guard<std::mutex> lk(ThreadCreationMutex);
-      NumThreads = Threads.size();
-    }
-
-    // Spin while waiting for the threads to start up
-    std::unique_lock<std::mutex> lk(IdleWaitMutex);
-    IdleWaitCV.wait(lk, [this, NumThreads] {
-      return IdleWaitRefCount.load() >= NumThreads;
-    });
-
-    Running = true;
-  }
-
-  void ContextImpl::Step() {
-    {
-      std::lock_guard<std::mutex> lk(ThreadCreationMutex);
-      // Walk the threads and tell them to clear their caches
-      // Useful when our block size is set to a large number and we need to step a single instruction
-      for (auto &Thread : Threads) {
-        ClearCodeCache(Thread);
-      }
-    }
-    CoreRunningMode PreviousRunningMode = this->Config.RunningMode;
-    int64_t PreviousMaxIntPerBlock = this->Config.MaxInstPerBlock;
-    this->Config.RunningMode = FEXCore::Context::CoreRunningMode::MODE_SINGLESTEP;
-    this->Config.MaxInstPerBlock = 1;
-    Run();
-    WaitForThreadsToRun();
-    WaitForIdle();
-    this->Config.RunningMode = PreviousRunningMode;
-    this->Config.MaxInstPerBlock = PreviousMaxIntPerBlock;
-  }
-
-  void ContextImpl::Stop(bool IgnoreCurrentThread) {
-    pid_t tid = FHU::Syscalls::gettid();
-    FEXCore::Core::InternalThreadState* CurrentThread{};
-
-    // Tell all the threads that they should stop
-    {
-      std::lock_guard<std::mutex> lk(ThreadCreationMutex);
-      for (auto &Thread : Threads) {
-        if (IgnoreCurrentThread &&
-            Thread->ThreadManager.TID == tid) {
-          // If we are callign stop from the current thread then we can ignore sending signals to this thread
-          // This means that this thread is already gone
-          continue;
-        }
-        else if (Thread->ThreadManager.TID == tid) {
-          // We need to save the current thread for last to ensure all threads receive their stop signals
-          CurrentThread = Thread;
-          continue;
-        }
-        if (Thread->RunningEvents.Running.load()) {
-          StopThread(Thread);
-        }
-
-        // If the thread is waiting to start but immediately killed then there can be a hang
-        // This occurs in the case of gdb attach with immediate kill
-        if (Thread->RunningEvents.WaitingToStart.load()) {
-          Thread->RunningEvents.EarlyExit = true;
-          Thread->StartRunning.NotifyAll();
-        }
-      }
-    }
-
-    // Stop the current thread now if we aren't ignoring it
-    if (CurrentThread) {
-      StopThread(CurrentThread);
-    }
-  }
-
-  void ContextImpl::StopThread(FEXCore::Core::InternalThreadState *Thread) {
-    if (Thread->RunningEvents.Running.exchange(false)) {
-      SignalDelegation->SignalThread(Thread, FEXCore::Core::SignalEvent::Stop);
-    }
-  }
-
-  void ContextImpl::SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event) {
-    if (Thread->RunningEvents.Running.load()) {
-      SignalDelegation->SignalThread(Thread, Event);
-    }
-  }
-
-  FEXCore::Context::ExitReason ContextImpl::RunUntilExit() {
-    if(!StartPaused) {
-      // We will only have one thread at this point, but just in case run notify everything
-      std::lock_guard lk(ThreadCreationMutex);
-      for (auto &Thread : Threads) {
-        Thread->StartRunning.NotifyAll();
-      }
-    }
-
-    ExecutionThread(ParentThread);
+  FEXCore::Context::ExitReason ContextImpl::RunUntilExit(FEXCore::Core::InternalThreadState *Thread) {
+    ExecutionThread(Thread);
    while(true) {
-      this->WaitForIdle();
-      auto reason = ParentThread->ExitReason;
+      auto reason = Thread->ExitReason;

      // Don't return if a custom exit handling the exit
      if (!CustomExitHandler || reason == ExitReason::EXIT_SHUTDOWN) {
@@ -511,61 +349,18 @@ namespace FEXCore::Context {
    Dispatcher->ExecuteDispatch(Thread->CurrentFrame);
  }

-  struct ExecutionThreadHandler {
-    ContextImpl *This;
-    FEXCore::Core::InternalThreadState *Thread;
-  };
-
-  static void *ThreadHandler(void* Data) {
-    ExecutionThreadHandler *Handler = reinterpret_cast<ExecutionThreadHandler*>(Data);
-    Handler->This->ExecutionThread(Handler->Thread);
-    FEXCore::Allocator::free(Handler);
-    return nullptr;
-  }
-
-  void ContextImpl::InitializeThread(FEXCore::Core::InternalThreadState *Thread) {
-    // This will create the execution thread but it won't actually start executing
-    ExecutionThreadHandler *Arg = reinterpret_cast<ExecutionThreadHandler*>(FEXCore::Allocator::malloc(sizeof(ExecutionThreadHandler)));
-    Arg->This = this;
-    Arg->Thread = Thread;
-    Thread->StartPaused = NeedToCheckXID;
-    Thread->ExecutionThread = FEXCore::Threads::Thread::Create(ThreadHandler, Arg);
-
-    // Wait for the thread to have started
-    Thread->ThreadWaiting.Wait();
-
-    if (NeedToCheckXID) {
-      // The first time an application creates a thread, GLIBC installs their SETXID signal handler.
-      // FEX needs to capture all signals and defer them to the guest.
-      // Once FEX creates its first guest thread, overwrite the GLIBC SETXID handler *again* to ensure
-      // FEX maintains control of the signal handler on this signal.
-      NeedToCheckXID = false;
-      SignalDelegation->CheckXIDHandler();
-      Thread->StartRunning.NotifyAll();
-    }
-  }

  void ContextImpl::InitializeThreadTLSData(FEXCore::Core::InternalThreadState *Thread) {
    // Let's do some initial bookkeeping here
    Thread->ThreadManager.TID = FHU::Syscalls::gettid();
    Thread->ThreadManager.PID = ::getpid();

-    if (Config.BlockJITNaming() ||
-        Config.GlobalJITNaming() ||
-        Config.LibraryJITNaming()) {
-      // Allocate a TLS JIT symbol buffer only if enabled.
-      Thread->SymbolBuffer = JITSymbols::AllocateBuffer();
-    }
-
-    SignalDelegation->RegisterTLSState(Thread);
    if (ThunkHandler) {
      ThunkHandler->RegisterTLSState(Thread);
    }
-  }
-
-  void ContextImpl::RunThread(FEXCore::Core::InternalThreadState *Thread) {
-    // Tell the thread to start executing
-    Thread->StartRunning.NotifyAll();
+#ifndef _WIN32
+    Alloc::OSAllocator::RegisterTLSData(Thread);
+#endif
  }

  void ContextImpl::InitializeCompiler(FEXCore::Core::InternalThreadState* Thread) {
@@ -574,9 +369,6 @@ namespace FEXCore::Context {
    Thread->LookupCache = fextl::make_unique<FEXCore::LookupCache>(this);
    Thread->FrontendDecoder = fextl::make_unique<FEXCore::Frontend::Decoder>(this);
    Thread->PassManager = fextl::make_unique<FEXCore::IR::PassManager>();
-    Thread->PassManager->RegisterExitHandler([this]() {
-        Stop(false /* Ignore current thread */);
-    });

    Thread->CurrentFrame->Pointers.Common.L1Pointer = Thread->LookupCache->GetL1Pointer();
    Thread->CurrentFrame->Pointers.Common.L2Pointer = Thread->LookupCache->GetPagePointer();
@@ -585,9 +377,7 @@ namespace FEXCore::Context {

    Thread->CTX = this;

-    bool DoSRA = DispatcherConfig.StaticRegisterAllocation;
-
-    Thread->PassManager->AddDefaultPasses(this, Config.Core == FEXCore::Config::CONFIG_IRJIT, DoSRA);
+    Thread->PassManager->AddDefaultPasses(this, Config.Core == FEXCore::Config::CONFIG_IRJIT);
    Thread->PassManager->AddDefaultValidationPasses();

    Thread->PassManager->RegisterSyscallHandler(SyscallHandler);
@@ -595,7 +385,7 @@ namespace FEXCore::Context {
    // Create CPU backend
    switch (Config.Core) {
    case FEXCore::Config::CONFIG_IRJIT:
-      Thread->PassManager->InsertRegisterAllocationPass(DoSRA, HostFeatures.SupportsAVX);
+      Thread->PassManager->InsertRegisterAllocationPass(HostFeatures.SupportsAVX);
      Thread->CPUBackend = FEXCore::CPU::CreateArm64JITCore(this, Thread);
      break;
    case FEXCore::Config::CONFIG_CUSTOM:
@@ -629,30 +419,21 @@ namespace FEXCore::Context {
    Thread->CurrentFrame->State.DeferredSignalRefCount.Store(0);
    Thread->CurrentFrame->State.DeferredSignalFaultAddress = reinterpret_cast<Core::NonAtomicRefCounter<uint64_t>*>(FEXCore::Allocator::VirtualAlloc(4096));

-    // Insert after the Thread object has been fully initialized
-    {
-      std::lock_guard lk(ThreadCreationMutex);
-      Threads.push_back(Thread);
+    if (Config.BlockJITNaming() ||
+        Config.GlobalJITNaming() ||
+        Config.LibraryJITNaming()) {
+      // Allocate a JIT symbol buffer only if enabled.
+      Thread->SymbolBuffer = JITSymbols::AllocateBuffer();
    }

    return Thread;
  }

-  void ContextImpl::DestroyThread(FEXCore::Core::InternalThreadState *Thread) {
-    // remove new thread object
-    {
-      std::lock_guard lk(ThreadCreationMutex);
-
-      auto It = std::find(Threads.begin(), Threads.end(), Thread);
-      LOGMAN_THROW_A_FMT(It != Threads.end(), "Thread wasn't in Threads");
-
-      Threads.erase(It);
-    }
-
-    if (Thread->ExecutionThread &&
-        Thread->ExecutionThread->IsSelf()) {
-      // To be able to delete a thread from itself, we need to detached the std::thread object
-      Thread->ExecutionThread->detach();
+  void ContextImpl::DestroyThread(FEXCore::Core::InternalThreadState *Thread, bool NeedsTLSUninstall) {
+    if (NeedsTLSUninstall) {
+#ifndef _WIN32
+      Alloc::OSAllocator::UninstallTLSData(Thread);
+#endif
    }

    FEXCore::Allocator::VirtualFree(reinterpret_cast<void*>(Thread->CurrentFrame->State.DeferredSignalFaultAddress), 4096);
@@ -670,43 +451,6 @@ namespace FEXCore::Context {
      CodeInvalidationMutex.unlock();
      return;
    }
-
-    // This function is called after fork
-    // We need to cleanup some of the thread data that is dead
-    for (auto &DeadThread : Threads) {
-      if (DeadThread == LiveThread) {
-        continue;
-      }
-
-      // Setting running to false ensures that when they are shutdown we won't send signals to kill them
-      DeadThread->RunningEvents.Running = false;
-
-      // Despite what google searches may susgest, glibc actually has special code to handle forks
-      // with multiple active threads.
-      // It cleans up the stacks of dead threads and marks them as terminated.
-      // It also cleans up a bunch of internal mutexes.
-
-      // FIXME: TLS is probally still alive. Investigate
-
-      // Deconstructing the Interneal thread state should clean up most of the state.
-      // But if anything on the now deleted stack is holding a refrence to the heap, it will be leaked
-      delete DeadThread;
-
-      // FIXME: Make sure sure nothing gets leaked via the heap. Ideas:
-      //         * Make sure nothing is allocated on the heap without ref in InternalThreadState
-      //         * Surround any code that heap allocates with a per-thread mutex.
-      //           Before forking, the the forking thread can lock all thread mutexes.
-    }
-
-    // Remove all threads but the live thread from Threads
-    Threads.clear();
-    Threads.push_back(LiveThread);
-
-    // We now only have one thread
-    IdleWaitRefCount = 1;
-
-    // Clean up dead stacks
-    FEXCore::Threads::Thread::CleanupAfterFork();
  }

  void ContextImpl::LockBeforeFork(FEXCore::Core::InternalThreadState *Thread) {
@@ -731,7 +475,6 @@ namespace FEXCore::Context {

    Thread->LookupCache->ClearCache();
    Thread->CPUBackend->ClearCache();
-    Thread->DebugStore.clear();
  }

  static void IRDumper(FEXCore::Core::InternalThreadState *Thread, IR::IREmitter *IREmitter, uint64_t GuestRIP, IR::RegisterAllocationData* RA) {
@@ -775,17 +518,20 @@ namespace FEXCore::Context {
    uint64_t TotalInstructions {0};
    uint64_t TotalInstructionsLength {0};

+    bool HasCustomIR{};

-    std::shared_lock lk(CustomIRMutex);
+    if (HasCustomIRHandlers.load(std::memory_order_relaxed)) {
+      std::shared_lock lk(CustomIRMutex);
+      auto Handler = CustomIRHandlers.find(GuestRIP);
+      if (Handler != CustomIRHandlers.end()) {
+        TotalInstructions = 1;
+        TotalInstructionsLength = 1;
+        std::get<0>(Handler->second)(GuestRIP, Thread->OpDispatcher.get());
+        HasCustomIR = true;
+      }
+    }

-    auto Handler = CustomIRHandlers.find(GuestRIP);
-    if (Handler != CustomIRHandlers.end()) {
-      TotalInstructions = 1;
-      TotalInstructionsLength = 1;
-      std::get<0>(Handler->second)(GuestRIP, Thread->OpDispatcher.get());
-      lk.unlock();
-    } else {
-      lk.unlock();
+    if (!HasCustomIR) {
      uint8_t const *GuestCode{};
      GuestCode = reinterpret_cast<uint8_t const*>(GuestRIP);

@@ -1027,17 +773,6 @@ namespace FEXCore::Context {
    };
  }

-  void ContextImpl::CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
-    auto NewBlock = CompileBlock(Frame, GuestRIP);
-
-    if (NewBlock == 0) {
-      LogMan::Msg::EFmt("CompileBlockJit: Failed to compile code {:X} - aborting process", GuestRIP);
-      // Return similar behaviour of SIGILL abort
-      Frame->Thread->StatusCode = 128 + SIGILL;
-      Stop(false /* Ignore current thread */);
-    }
-  }
-
  uintptr_t ContextImpl::CompileBlock(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP, uint64_t MaxInst) {
    FEXCORE_PROFILE_SCOPED("CompileBlock");
    auto Thread = Frame->Thread;
@@ -1142,16 +877,11 @@ namespace FEXCore::Context {
    Thread->ExitReason = FEXCore::Context::ExitReason::EXIT_WAITING;

    InitializeThreadTLSData(Thread);
-#ifndef _WIN32
-    Alloc::OSAllocator::RegisterTLSData(Thread);
-#endif
-
-    ++IdleWaitRefCount;

    // Now notify the thread that we are initialized
    Thread->ThreadWaiting.NotifyAll();

-    if (Thread != static_cast<ContextImpl*>(Thread->CTX)->ParentThread || StartPaused || Thread->StartPaused) {
+    if (StartPaused || Thread->StartPaused) {
      // Parent thread doesn't need to wait to run
      Thread->StartRunning.Wait();
    }
@@ -1186,18 +916,9 @@ namespace FEXCore::Context {
      }
    }

-    --IdleWaitRefCount;
-    IdleWaitCV.notify_all();
-
 #ifndef _WIN32
    Alloc::OSAllocator::UninstallTLSData(Thread);
 #endif
-    SignalDelegation->UninstallTLSState(Thread);
-
-    // If the parent thread is waiting to join, then we can't destroy our thread object
-    if (!Thread->DestroyedByParent && Thread != static_cast<ContextImpl*>(Thread->CTX)->ParentThread) {
-      Thread->CTX->DestroyThread(Thread);
-    }
  }

  static void InvalidateGuestThreadCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length) {
@@ -1214,55 +935,29 @@ namespace FEXCore::Context {
    }
  }

-  static void InvalidateGuestCodeRangeInternal(ContextImpl *CTX, uint64_t Start, uint64_t Length) {
-    std::lock_guard lk(static_cast<ContextImpl*>(CTX)->ThreadCreationMutex);
-
-    for (auto &Thread : static_cast<ContextImpl*>(CTX)->Threads) {
-      InvalidateGuestThreadCodeRange(Thread, Start, Length);
-    }
-  }
-
  void ContextImpl::InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length) {
-    // Potential deferred since Thread might not be valid.
-    // Thread object isn't valid very early in frontend's initialization.
-    // To be more optimal the frontend should provide this code with a valid Thread object earlier.
-    auto lk = GuardSignalDeferringSectionWithFallback(CodeInvalidationMutex, Thread);
-
-    InvalidateGuestCodeRangeInternal(this, Start, Length);
+    InvalidateGuestThreadCodeRange(Thread, Start, Length);
  }

  void ContextImpl::InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length, CodeRangeInvalidationFn CallAfter) {
-    // Potential deferred since Thread might not be valid.
-    // Thread object isn't valid very early in frontend's initialization.
-    // To be more optimal the frontend should provide this code with a valid Thread object earlier.
-    auto lk = GuardSignalDeferringSectionWithFallback(CodeInvalidationMutex, Thread);
-
-    InvalidateGuestCodeRangeInternal(this, Start, Length);
+    InvalidateGuestThreadCodeRange(Thread, Start, Length);
    CallAfter(Start, Length);
  }

-  void ContextImpl::MarkMemoryShared() {
+  void ContextImpl::MarkMemoryShared(FEXCore::Core::InternalThreadState *Thread) {
    if (!IsMemoryShared) {
      IsMemoryShared = true;
      UpdateAtomicTSOEmulationConfig();

      if (Config.TSOAutoMigration) {
-        std::lock_guard<std::mutex> lkThreads(ThreadCreationMutex);
-        LogMan::Throw::AFmt(Threads.size() == 1, "First MarkMemoryShared called must be before creating any threads");
-
-        auto Thread = Threads[0];
-
        // Only the lookup cache is cleared here, so that old code can keep running until next compilation
        std::lock_guard<std::recursive_mutex> lkLookupCache(Thread->LookupCache->WriteLock);
        Thread->LookupCache->ClearCache();
-
-        // DebugStore also needs to be cleared
-        Thread->DebugStore.clear();
      }
    }
  }

-  void ContextImpl::ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker) {
+  void ContextImpl::ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, FEXCore::Context::ExitFunctionLinkData *HostLink, const FEXCore::Context::BlockDelinkerFunc &delinker) {
    auto lk = GuardSignalDeferringSection<std::shared_lock>(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);

    Thread->LookupCache->AddBlockLink(GuestDestination, HostLink, delinker);
@@ -1273,8 +968,7 @@ namespace FEXCore::Context {

    std::lock_guard<std::recursive_mutex> lk(Thread->LookupCache->WriteLock);

-    Thread->DebugStore.erase(GuestRIP);
-    Thread->LookupCache->Erase(GuestRIP);
+    Thread->LookupCache->Erase(Thread->CurrentFrame, GuestRIP);
  }

  CustomIRResult ContextImpl::AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void *Creator, void *Data) {
@@ -1283,6 +977,7 @@ namespace FEXCore::Context {
    std::unique_lock lk(CustomIRMutex);

    auto InsertedIterator = CustomIRHandlers.emplace(Entrypoint, std::tuple(Handler, Creator, Data));
+    HasCustomIRHandlers = true;

    if (!InsertedIterator.second) {
      const auto &[fn, Creator, Data] = InsertedIterator.first->second;
@@ -1301,12 +996,8 @@ namespace FEXCore::Context {
    InvalidateGuestCodeRange(nullptr, Entrypoint, 1, [this](uint64_t Entrypoint, uint64_t) {
      CustomIRHandlers.erase(Entrypoint);
    });
-  }

-  uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::CpuStateFrame *Frame, FEXCore::HLE::SyscallArguments *Args) {
-    uint64_t Result{};
-    Result = Handler->HandleSyscall(Frame, Args);
-    return Result;
+    HasCustomIRHandlers = !CustomIRHandlers.empty();
  }

  IR::AOTIRCacheEntry *ContextImpl::LoadAOTIRCacheEntry(const fextl::string &filename) {
@@ -5,12 +5,14 @@
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/X86HelperGen.h"
+#include "Utils/MemberFunctionToPointer.h"

 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/InternalThreadState.h>
+#include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>
@@ -23,42 +25,15 @@

 namespace FEXCore::CPU {

-void Dispatcher::SleepThread(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::CpuStateFrame *Frame) {
-  auto Thread = Frame->Thread;
-
-  --ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-
-  Thread->RunningEvents.ThreadSleeping = true;
-
-  // Go to sleep
-  Thread->StartRunning.Wait();
-
-  Thread->RunningEvents.Running = true;
-  ++ctx->IdleWaitRefCount;
-  Thread->RunningEvents.ThreadSleeping = false;
-
-  ctx->IdleWaitCV.notify_all();
-}
-
-uint64_t Dispatcher::GetCompileBlockPtr() {
-  using ClassPtrType = void (FEXCore::Context::ContextImpl::*)(FEXCore::Core::CpuStateFrame *, uint64_t);
-  union PtrCast {
-    ClassPtrType ClassPtr;
-    uintptr_t Data;
-  };
-
-  PtrCast CompileBlockPtr;
-  CompileBlockPtr.ClassPtr = &FEXCore::Context::ContextImpl::CompileBlockJit;
-  return CompileBlockPtr.Data;
+static void SleepThread(FEXCore::Context::ContextImpl *CTX, FEXCore::Core::CpuStateFrame *Frame) {
+  CTX->SyscallHandler->SleepThread(CTX, Frame);
 }

 constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096 * 2;

-Dispatcher::Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &config)
+Dispatcher::Dispatcher(FEXCore::Context::ContextImpl *ctx)
  : Arm64Emitter(ctx, FEXCore::Allocator::VirtualAlloc(MAX_DISPATCHER_CODE_SIZE, true), MAX_DISPATCHER_CODE_SIZE)
-  , CTX {ctx}
-  , config {config} {
+  , CTX {ctx} {
  EmitDispatcher();
 }

@@ -85,8 +60,8 @@ void Dispatcher::EmitDispatcher() {
  // }

  ARMEmitter::ForwardLabel l_CTX;
-  ARMEmitter::ForwardLabel l_Sleep;
-  ARMEmitter::ForwardLabel l_CompileBlock;
+  ARMEmitter::SingleUseForwardLabel l_Sleep;
+  ARMEmitter::SingleUseForwardLabel l_CompileBlock;

  // Push all the register we need to save
  PushCalleeSavedRegisters();
@@ -103,9 +78,7 @@ void Dispatcher::EmitDispatcher() {

  AbsoluteLoopTopAddressFillSRA = GetCursorAddress<uint64_t>();

-  if (config.StaticRegisterAllocation) {
-    FillStaticRegs();
-  }
+  FillStaticRegs();

  // We want to ensure that we are 16 byte aligned at the top of this loop
  Align16B();
@@ -117,87 +90,86 @@ void Dispatcher::EmitDispatcher() {
  AbsoluteLoopTopAddress = GetCursorAddress<uint64_t>();

  // Load in our RIP
-  // Don't modify x2 since it contains our RIP once the block doesn't exist
+  // Don't modify TMP3 since it contains our RIP once the block doesn't exist

-  auto RipReg = ARMEmitter::XReg::x2;
+  auto RipReg = TMP3;
  ldr(RipReg, STATE_PTR(CpuStateFrame, State.rip));

  // L1 Cache
-  ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
+  ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));

-  and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, RipReg.R(), LookupCache::L1_ENTRIES_MASK);
-  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, ARMEmitter::Reg::r0, ARMEmitter::Reg::r3, ARMEmitter::ShiftType::LSL , 4);
-  ldp<ARMEmitter::IndexType::OFFSET>(ARMEmitter::XReg::x3, ARMEmitter::XReg::x0, ARMEmitter::Reg::r0, 0);
-  sub(ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, RipReg);
-  cbnz(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, &FullLookup);
+  and_(ARMEmitter::Size::i64Bit, TMP4, RipReg.R(), LookupCache::L1_ENTRIES_MASK);
+  add(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP4, ARMEmitter::ShiftType::LSL , 4);
+  ldp<ARMEmitter::IndexType::OFFSET>(TMP4, TMP1, TMP1, 0);
+  sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, RipReg);
+  cbnz(ARMEmitter::Size::i64Bit, TMP1, &FullLookup);

-  br(ARMEmitter::Reg::r3);
+  br(TMP4);

  // L1C check failed, do a full lookup
  Bind(&FullLookup);

  // This is the block cache lookup routine
  // It matches what is going on it LookupCache.h::FindBlock
-  ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.L2Pointer));
+  ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.L2Pointer));

  // Mask the address by the virtual address size so we can check for aliases
  uint64_t VirtualMemorySize = CTX->Config.VirtualMemSize;
  if (std::popcount(VirtualMemorySize) == 1) {
-    and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, RipReg.R(), VirtualMemorySize - 1);
+    and_(ARMEmitter::Size::i64Bit, TMP4, RipReg.R(), VirtualMemorySize - 1);
  }
  else {
-    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, VirtualMemorySize);
-    and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, RipReg.R(), ARMEmitter::Reg::r3);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP4, VirtualMemorySize);
+    and_(ARMEmitter::Size::i64Bit, TMP4, RipReg.R(), TMP4);
  }

  ARMEmitter::ForwardLabel NoBlock;

  {
    // Offset the address and add to our page pointer
-    lsr(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, ARMEmitter::Reg::r3, 12);
+    lsr(ARMEmitter::Size::i64Bit, TMP2, TMP4, 12);

    // Load the pointer from the offset
-    ldr(ARMEmitter::XReg::x0, ARMEmitter::Reg::r0, ARMEmitter::Reg::r1, ARMEmitter::ExtendedType::LSL_64, 3);
+    ldr(TMP1, TMP1, TMP2, ARMEmitter::ExtendedType::LSL_64, 3);

    // If page pointer is zero then we have no block
-    cbz(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, &NoBlock);
+    cbz(ARMEmitter::Size::i64Bit, TMP1, &NoBlock);

    // Steal the page offset
-    and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, ARMEmitter::Reg::r3, 0x0FFF);
+    and_(ARMEmitter::Size::i64Bit, TMP2, TMP4, 0x0FFF);

    // Shift the offset by the size of the block cache entry
-    add(ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, ARMEmitter::XReg::x1, ARMEmitter::ShiftType::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
+    add(TMP1, TMP1, TMP2, ARMEmitter::ShiftType::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));

    // The the full LookupCacheEntry with a single LDP.
    // Check the guest address first to ensure it maps to the address we are currently at.
    // This fixes aliasing problems
-    ldp<ARMEmitter::IndexType::OFFSET>(ARMEmitter::XReg::x3, ARMEmitter::XReg::x1, ARMEmitter::Reg::r0, 0);
+    ldp<ARMEmitter::IndexType::OFFSET>(TMP4, TMP2, TMP1, 0);

    // If the guest address doesn't match, Compile the block.
-    sub(ARMEmitter::XReg::x1, ARMEmitter::XReg::x1, RipReg);
-    cbnz(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, &NoBlock);
+    sub(TMP2, TMP2, RipReg);
+    cbnz(ARMEmitter::Size::i64Bit, TMP2, &NoBlock);

    // Check the host address to see if it matches, else compile the block.
-    cbz(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, &NoBlock);
+    cbz(ARMEmitter::Size::i64Bit, TMP4, &NoBlock);

    // If we've made it here then we have a real compiled block
    {
      // update L1 cache
-      ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.L1Pointer));

-      and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, RipReg.R(), LookupCache::L1_ENTRIES_MASK);
-      add(ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, ARMEmitter::XReg::x1, ARMEmitter::ShiftType::LSL, 4);
-      stp<ARMEmitter::IndexType::OFFSET>(ARMEmitter::XReg::x3, ARMEmitter::XReg::x2, ARMEmitter::Reg::r0);
+      and_(ARMEmitter::Size::i64Bit, TMP2, RipReg.R(), LookupCache::L1_ENTRIES_MASK);
+      add(TMP1, TMP1, TMP2, ARMEmitter::ShiftType::LSL, 4);
+      stp<ARMEmitter::IndexType::OFFSET>(TMP4, TMP3, TMP1);

      // Jump to the block
-      br(ARMEmitter::Reg::r3);
+      br(TMP4);
    }
  }

  {
    ThreadStopHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs(TMP1);
+    SpillStaticRegs(TMP1);

    ThreadStopHandlerAddress = GetCursorAddress<uint64_t>();

@@ -210,8 +182,7 @@ void Dispatcher::EmitDispatcher() {

  {
    ExitFunctionLinkerAddress = GetCursorAddress<uint64_t>();
-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs(TMP1);
+    SpillStaticRegs(TMP1);

    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
@@ -228,26 +199,32 @@ void Dispatcher::EmitDispatcher() {
      blr(ARMEmitter::Reg::r2);
    }

-    if (config.StaticRegisterAllocation)
-      FillStaticRegs();
+    if (!TMP_ABIARGS) {
+      mov(TMP1, ARMEmitter::XReg::x0);
+    }

-    ldr(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
-    sub(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x1, ARMEmitter::XReg::x1, 1);
-    str(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    FillStaticRegs();
+
+    ldr(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    sub(ARMEmitter::Size::i64Bit, TMP2, TMP2, 1);
+    str(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));

    // Trigger segfault if any deferred signals are pending
-    ldr(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
-    str(ARMEmitter::XReg::zr, ARMEmitter::XReg::x1, 0);
+    ldr(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
+    str(ARMEmitter::XReg::zr, TMP2, 0);

-    br(ARMEmitter::Reg::r0);
+    br(TMP1);
  }

  // Need to create the block
  {
    Bind(&NoBlock);

-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs(TMP1);
+    SpillStaticRegs(TMP1);
+
+    if (!TMP_ABIARGS) {
+      mov(ARMEmitter::XReg::x2, TMP3);
+    }

    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
@@ -255,22 +232,22 @@ void Dispatcher::EmitDispatcher() {

    ldr(ARMEmitter::XReg::x0, &l_CTX);
    mov(ARMEmitter::XReg::x1, STATE);
-    ldr(ARMEmitter::XReg::x3, &l_CompileBlock);
+    // x2 contains guest RIP
+    mov(ARMEmitter::XReg::x3, 0);
+    ldr(ARMEmitter::XReg::x4, &l_CompileBlock);

-    // X2 contains our guest RIP
    if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-      GenerateIndirectRuntimeCall<void, void *, uint64_t, void *>(ARMEmitter::Reg::r3);
+      GenerateIndirectRuntimeCall<uintptr_t, void *, void*, uint64_t, uint64_t>(ARMEmitter::Reg::r4);
    }
    else {
-      blr(ARMEmitter::Reg::r3); // { CTX, Frame, RIP}
+      blr(ARMEmitter::Reg::r4); // { CTX, Frame, RIP, MaxInst }
    }

-    if (config.StaticRegisterAllocation)
-      FillStaticRegs();
+    FillStaticRegs();

-    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
-    sub(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
-    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 1);
+    str(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));

    // Trigger segfault if any deferred signals are pending
    ldr(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
@@ -300,8 +277,7 @@ void Dispatcher::EmitDispatcher() {
    // Needs to be distinct from the SignalHandlerReturnAddress
    GuestSignal_SIGILL = GetCursorAddress<uint64_t>();

-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs(TMP1);
+    SpillStaticRegs(TMP1);

    hlt(0);
  }
@@ -311,8 +287,7 @@ void Dispatcher::EmitDispatcher() {
    // Needs to be distinct from the SignalHandlerReturnAddress
    GuestSignal_SIGTRAP  = GetCursorAddress<uint64_t>();

-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs(TMP1);
+    SpillStaticRegs(TMP1);

    brk(0);
  }
@@ -322,8 +297,7 @@ void Dispatcher::EmitDispatcher() {
    // Needs to be distinct from the SignalHandlerReturnAddress
    GuestSignal_SIGSEGV = GetCursorAddress<uint64_t>();

-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs(TMP1);
+    SpillStaticRegs(TMP1);

    // hlt/udf = SIGILL
    // brk = SIGTRAP
@@ -343,8 +317,7 @@ void Dispatcher::EmitDispatcher() {

  {
    ThreadPauseHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
-    if (config.StaticRegisterAllocation)
-      SpillStaticRegs(TMP1);
+    SpillStaticRegs(TMP1);

    ThreadPauseHandlerAddress = GetCursorAddress<uint64_t>();
    // We are pausing, this means the frontend should be waiting for this thread to idle
@@ -411,112 +384,59 @@ void Dispatcher::EmitDispatcher() {
    str(ARMEmitter::XReg::x1, STATE_PTR(CpuStateFrame, State.rip));

    // load static regs
-    if (config.StaticRegisterAllocation)
-      FillStaticRegs();
+    FillStaticRegs();

    // Now go back to the regular dispatcher loop
    b(&LoopTop);
  }

-  {
-    LUDIVHandlerAddress = GetCursorAddress<uint64_t>();
+  auto EmitLongALUOpHandler = [&](auto R, auto Offset) {
+    auto Address = GetCursorAddress<uint64_t>();

-    PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
-    SpillStaticRegs(ARMEmitter::Reg::r3);
+    PushDynamicRegsAndLR(TMP4);
+    SpillStaticRegs(TMP4);

-    ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LUDIV));
+    if (!TMP_ABIARGS) {
+      mov(ARMEmitter::XReg::x0, TMP1);
+      mov(ARMEmitter::XReg::x1, TMP2);
+      mov(ARMEmitter::XReg::x2, TMP3);
+    }
+
+    ldr(ARMEmitter::XReg::x3, R, Offset);
    if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
      GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
    }
    else {
      blr(ARMEmitter::Reg::r3);
    }
+    // Result is now in x0
+
+    if (!TMP_ABIARGS) {
+      mov(TMP1, ARMEmitter::XReg::x0);
+    }
+
    FillStaticRegs();

-    // Result is now in x0
    // Fix the stack and any values that were stepped on
    PopDynamicRegsAndLR();

    // Go back to our code block
    ret();
-  }
+    return Address;
+  };

-  {
-    LDIVHandlerAddress = GetCursorAddress<uint64_t>();
-
-    PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
-    SpillStaticRegs(ARMEmitter::Reg::r3);
-
-    ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LDIV));
-    if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-      GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
-    }
-    else {
-      blr(ARMEmitter::Reg::r3);
-    }
-    FillStaticRegs();
-
-    // Result is now in x0
-    // Fix the stack and any values that were stepped on
-    PopDynamicRegsAndLR();
-
-    // Go back to our code block
-    ret();
-  }
-
-  {
-    LUREMHandlerAddress = GetCursorAddress<uint64_t>();
-
-    PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
-    SpillStaticRegs(ARMEmitter::Reg::r3);
-
-    ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LUREM));
-    if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-      GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
-    }
-    else {
-      blr(ARMEmitter::Reg::r3);
-    }
-    FillStaticRegs();
-
-    // Result is now in x0
-    // Fix the stack and any values that were stepped on
-    PopDynamicRegsAndLR();
-
-    // Go back to our code block
-    ret();
-  }
-
-  {
-    LREMHandlerAddress = GetCursorAddress<uint64_t>();
-
-    PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
-    SpillStaticRegs(ARMEmitter::Reg::r3);
-
-    ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LREM));
-
-    if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
-      GenerateIndirectRuntimeCall<uint64_t, uint64_t, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
-    }
-    else {
-      blr(ARMEmitter::Reg::r3);
-    }
-    FillStaticRegs();
-
-    // Result is now in x0
-    // Fix the stack and any values that were stepped on
-    PopDynamicRegsAndLR();
-
-    // Go back to our code block
-    ret();
-  }
+  LUDIVHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.AArch64.LUDIV));
+  LDIVHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.AArch64.LDIV));
+  LUREMHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.AArch64.LUREM));
+  LREMHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.AArch64.LREM));

  Bind(&l_CTX);
  dc64(reinterpret_cast<uintptr_t>(CTX));
  Bind(&l_Sleep);
  dc64(reinterpret_cast<uint64_t>(SleepThread));
  Bind(&l_CompileBlock);
-  dc64(GetCompileBlockPtr());
+  FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::Context::ContextImpl::CompileBlock);
+  dc64(PMF.GetConvertedPointer());

  Start = reinterpret_cast<uint64_t>(DispatchPtr);
  End = GetCursorAddress<uint64_t>();
@@ -535,7 +455,7 @@ void Dispatcher::EmitDispatcher() {
    const auto DisasmEnd = GetCursorAddress<const vixl::aarch64::Instruction*>();
    for (auto PCToDecode = DisasmBegin; PCToDecode < DisasmEnd; PCToDecode += 4) {
      DisasmDecoder->Decode(PCToDecode);
-      auto Output = Disasm.GetOutput();
+      auto Output = Disasm->GetOutput();
      LogMan::Msg::IFmt("{}", Output);
    }
  }
@@ -580,8 +500,8 @@ void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread)
  }
 }

-fextl::unique_ptr<Dispatcher> Dispatcher::Create(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config) {
-  return fextl::make_unique<Dispatcher>(CTX, Config);
+fextl::unique_ptr<Dispatcher> Dispatcher::Create(FEXCore::Context::ContextImpl *CTX) {
+  return fextl::make_unique<Dispatcher>(CTX);
 }

 }
@@ -2,8 +2,8 @@
 #pragma once

 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Core/CPUBackend.h"

-#include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/fextl/memory.h>

 #ifdef VIXL_SIMULATOR
@@ -31,18 +31,14 @@ class ContextImpl;

 namespace FEXCore::CPU {

-struct DispatcherConfig {
-  bool StaticRegisterAllocation = false;
-};
-
 #define STATE_PTR(STATE_TYPE, FIELD) \
  STATE.R(), offsetof(FEXCore::Core::STATE_TYPE, FIELD)

 class Dispatcher final : public Arm64Emitter {
 public:
-  static fextl::unique_ptr<Dispatcher> Create(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config);
+  static fextl::unique_ptr<Dispatcher> Create(FEXCore::Context::ContextImpl *CTX);

-  Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &Config);
+  Dispatcher(FEXCore::Context::ContextImpl *ctx);
  ~Dispatcher();

  /**
@@ -106,15 +102,8 @@ public:
    }
  }

-  const DispatcherConfig& GetConfig() const { return config; }
-
 protected:
  FEXCore::Context::ContextImpl *CTX;
-  DispatcherConfig config;
-
-  static void SleepThread(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::CpuStateFrame *Frame);
-
-  static uint64_t GetCompileBlockPtr();

  using AsmDispatch = void(*)(FEXCore::Core::CpuStateFrame *Frame);
  using JITCallback = void(*)(FEXCore::Core::CpuStateFrame *Frame, uint64_t RIP);
@@ -20,8 +20,8 @@ $end_info$
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
 #include <FEXCore/Utils/Telemetry.h>
+#include <FEXCore/Utils/TypeDefines.h>
 #include <FEXCore/fextl/set.h>
-#include <FEXHeaderUtils/TypeDefines.h>

 namespace FEXCore::Frontend {
 #include "Interface/Core/VSyscall/VSyscall.inc"
@@ -284,7 +284,6 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
    if (DisplacementSize == 1) {
      Literal = static_cast<int8_t>(Literal);
    }
-    Displacement = DisplacementSize;

    Operand->Type = DecodedOperand::OpType::GPRIndirect;
    Operand->Data.GPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
@@ -1127,11 +1126,11 @@ void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC,
  // Entry is a jump target
  BlocksToDecode.emplace(PC);

-  uint64_t CurrentCodePage = PC & FHU::FEX_PAGE_MASK;
+  uint64_t CurrentCodePage = PC & FEXCore::Utils::FEX_PAGE_MASK;

  fextl::set<uint64_t> CodePages = { CurrentCodePage };

-  AddContainedCodePage(PC, CurrentCodePage, FHU::FEX_PAGE_SIZE);
+  AddContainedCodePage(PC, CurrentCodePage, FEXCore::Utils::FEX_PAGE_SIZE);

  if (MaxInst == 0) {
    MaxInst = CTX->Config.MaxInstPerBlock;
@@ -1157,8 +1156,8 @@ void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC,
      auto OpMinAddress = RIPToDecode + PCOffset;
      auto OpMaxAddress = OpMinAddress + MAX_INST_SIZE;

-      auto OpMinPage = OpMinAddress & FHU::FEX_PAGE_MASK;
-      auto OpMaxPage = OpMaxAddress & FHU::FEX_PAGE_MASK;
+      auto OpMinPage = OpMinAddress & FEXCore::Utils::FEX_PAGE_MASK;
+      auto OpMaxPage = OpMaxAddress & FEXCore::Utils::FEX_PAGE_MASK;

      if (OpMinPage != CurrentCodePage) {
        CurrentCodePage = OpMinPage;
@@ -1231,7 +1230,7 @@ void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC,
  }

  for (auto CodePage : CodePages) {
-    AddContainedCodePage(PC, CodePage, FHU::FEX_PAGE_SIZE);
+    AddContainedCodePage(PC, CodePage, FEXCore::Utils::FEX_PAGE_SIZE);
  }

  // sort for better branching
@@ -9,14 +9,6 @@

 #ifdef _M_X86_64
 #define XBYAK64
-#define XBYAK_CUSTOM_ALLOC
-#define XBYAK_CUSTOM_MALLOC FEXCore::Allocator::malloc
-#define XBYAK_CUSTOM_FREE FEXCore::Allocator::free
-#define XBYAK_CUSTOM_SETS
-#define XBYAK_STD_UNORDERED_SET fextl::unordered_set
-#define XBYAK_STD_UNORDERED_MAP fextl::unordered_map
-#define XBYAK_STD_UNORDERED_MULTIMAP fextl::unordered_multimap
-#define XBYAK_STD_LIST fextl::list
 #define XBYAK_NO_EXCEPTION
 #include <FEXCore/fextl/list.h>
 #include <FEXCore/fextl/unordered_map.h>
@@ -69,114 +61,42 @@ static void OverrideFeatures(HostFeatures *Features) {
    return;
  }

-#define ENABLE_DISABLE_OPTION(name, enum_name) \
+#define ENABLE_DISABLE_OPTION(FeatureName, name, enum_name) \
+    do { \
+      const bool Disable##name = (HostFeatures() & FEXCore::Config::HostFeatures::DISABLE##enum_name) != 0; \
+      const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0;   \
+      LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive"); \
+      const bool AlreadyEnabled = Features->FeatureName; \
+      const bool Result = (AlreadyEnabled | Enable##name) & !Disable##name; \
+      Features->FeatureName = Result; \
+    } while (0)
+
+#define GET_SINGLE_OPTION(name, enum_name) \
    const bool Disable##name = (HostFeatures() & FEXCore::Config::HostFeatures::DISABLE##enum_name) != 0; \
    const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0;   \
    LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive");

-  ENABLE_DISABLE_OPTION(AVX, AVX);
-  ENABLE_DISABLE_OPTION(AVX2, AVX2);
-  ENABLE_DISABLE_OPTION(SVE, SVE);
-  ENABLE_DISABLE_OPTION(AFP, AFP);
-  ENABLE_DISABLE_OPTION(LRCPC, LRCPC);
-  ENABLE_DISABLE_OPTION(LRCPC2, LRCPC2);
-  ENABLE_DISABLE_OPTION(CSSC, CSSC);
-  ENABLE_DISABLE_OPTION(PMULL128, PMULL128);
-  ENABLE_DISABLE_OPTION(RNG, RNG);
-  ENABLE_DISABLE_OPTION(CLZERO, CLZERO);
-  ENABLE_DISABLE_OPTION(Atomics, ATOMICS);
-  ENABLE_DISABLE_OPTION(FCMA, FCMA);
-  ENABLE_DISABLE_OPTION(FlagM, FLAGM);
-  ENABLE_DISABLE_OPTION(FlagM2, FLAGM2);
-  ENABLE_DISABLE_OPTION(Crypto, CRYPTO);
-  ENABLE_DISABLE_OPTION(RPRES, RPRES);
+  ENABLE_DISABLE_OPTION(SupportsAVX, AVX, AVX);
+  ENABLE_DISABLE_OPTION(SupportsAVX2, AVX2, AVX2);
+  ENABLE_DISABLE_OPTION(SupportsSVE, SVE, SVE);
+  ENABLE_DISABLE_OPTION(SupportsAFP, AFP, AFP);
+  ENABLE_DISABLE_OPTION(SupportsRCPC, LRCPC, LRCPC);
+  ENABLE_DISABLE_OPTION(SupportsTSOImm9, LRCPC2, LRCPC2);
+  ENABLE_DISABLE_OPTION(SupportsCSSC, CSSC, CSSC);
+  ENABLE_DISABLE_OPTION(SupportsPMULL_128Bit, PMULL128, PMULL128);
+  ENABLE_DISABLE_OPTION(SupportsRAND, RNG, RNG);
+  ENABLE_DISABLE_OPTION(SupportsCLZERO, CLZERO, CLZERO);
+  ENABLE_DISABLE_OPTION(SupportsAtomics, Atomics, ATOMICS);
+  ENABLE_DISABLE_OPTION(SupportsFCMA, FCMA, FCMA);
+  ENABLE_DISABLE_OPTION(SupportsFlagM, FlagM, FLAGM);
+  ENABLE_DISABLE_OPTION(SupportsFlagM2, FlagM2, FLAGM2);
+  ENABLE_DISABLE_OPTION(SupportsRPRES, RPRES, RPRES);
+  ENABLE_DISABLE_OPTION(SupportsPreserveAllABI, PRESERVEALLABI, PRESERVEALLABI);
+  GET_SINGLE_OPTION(Crypto, CRYPTO);

 #undef ENABLE_DISABLE_OPTION
+#undef GET_SINGLE_OPTION

-  if (EnableAVX) {
-    Features->SupportsAVX = true;
-  }
-  else if (DisableAVX) {
-    Features->SupportsAVX = false;
-  }
-  if (EnableAVX2) {
-    Features->SupportsAVX2 = true;
-  }
-  else if (DisableAVX2) {
-    Features->SupportsAVX2 = false;
-  }
-  if (EnableSVE) {
-    Features->SupportsSVE = true;
-  }
-  else if (DisableSVE) {
-    Features->SupportsSVE = false;
-  }
-  if (EnableAFP) {
-    Features->SupportsAFP = true;
-  }
-  else if (DisableAFP) {
-    Features->SupportsAFP = false;
-  }
-  if (EnableLRCPC) {
-    Features->SupportsRCPC = true;
-  }
-  else if (DisableLRCPC) {
-    Features->SupportsRCPC = false;
-  }
-  if (EnableLRCPC2) {
-    Features->SupportsTSOImm9 = true;
-  }
-  else if (DisableLRCPC2) {
-    Features->SupportsTSOImm9 = false;
-  }
-  if (EnableCSSC) {
-    Features->SupportsCSSC = true;
-  }
-  else if (DisableCSSC) {
-    Features->SupportsCSSC = false;
-  }
-  if (EnablePMULL128) {
-    Features->SupportsPMULL_128Bit = true;
-  }
-  else if (DisablePMULL128) {
-    Features->SupportsPMULL_128Bit = false;
-  }
-  if (EnableRNG) {
-    Features->SupportsRAND = true;
-  }
-  else if (DisableRNG) {
-    Features->SupportsRAND = false;
-  }
-  if (EnableCLZERO) {
-    Features->SupportsCLZERO = true;
-  }
-  else if (DisableCLZERO) {
-    Features->SupportsCLZERO = false;
-  }
-  if (EnableAtomics) {
-    Features->SupportsAtomics = true;
-  }
-  else if (DisableAtomics) {
-    Features->SupportsAtomics = false;
-  }
-  if (EnableFCMA) {
-    Features->SupportsFCMA = true;
-  }
-  else if (DisableFCMA) {
-    Features->SupportsFCMA = false;
-  }
-  if (EnableFlagM) {
-    Features->SupportsFlagM = true;
-  }
-  else if (DisableFlagM) {
-    Features->SupportsFlagM = false;
-  }
-  if (EnableFlagM2) {
-    Features->SupportsFlagM2 = true;
-  }
-  else if (DisableFlagM2) {
-    Features->SupportsFlagM2 = false;
-  }
  if (EnableCrypto) {
    Features->SupportsAES = true;
    Features->SupportsCRC = true;
@@ -189,12 +109,6 @@ static void OverrideFeatures(HostFeatures *Features) {
    Features->SupportsSHA = false;
    Features->SupportsPMULL_128Bit = false;
  }
-  if (EnableRPRES) {
-    Features->SupportsRPRES = true;
-  }
-  else if (DisableRPRES) {
-    Features->SupportsRPRES = false;
-  }
 }

 HostFeatures::HostFeatures() {
@@ -339,6 +253,7 @@ HostFeatures::HostFeatures() {
  SupportsFloatExceptions = true;
 #endif
 #endif
+  SupportsPreserveAllABI = FEXCORE_HAS_PRESERVE_ALL_ATTR;
  OverrideFeatures(this);
 }
 }
@@ -1,2 +0,0 @@
-// SPDX-License-Identifier: MIT
-#include <FEXCore/Debug/InternalThreadState.h>
@@ -2,9 +2,8 @@
 #include "Common/SoftFloat.h"
 #include "Common/SoftFloat-3e/softfloat.h"

-#include <FEXCore/IR/IR.h>
-
 #include "Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h"
+#include "Interface/IR/IR.h"

 namespace FEXCore::CPU {
 FEXCORE_PRESERVE_ALL_ATTR
@@ -85,7 +85,7 @@ void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) {
  Info[Core::OPINDEX_VPCMPISTRX] = reinterpret_cast<uint64_t>(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle);
 }

-bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInfo *Info) {
+bool InterpreterOps::GetFallbackHandler(bool SupportsPreserveAllABI, IR::IROp_Header const *IROp, FallbackInfo *Info) {
  uint8_t OpSize = IROp->Size;
  switch(IROp->Op) {
    case IR::OP_F80CVTTO: {
@@ -93,11 +93,11 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf

      switch (Op->SrcSize) {
        case 4: {
-          *Info = {FABI_F80_I16_F32, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+          *Info = {FABI_F80_I16_F32, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4, SupportsPreserveAllABI};
          return true;
        }
        case 8: {
-          *Info = {FABI_F80_I16_F64, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8, Core::OPINDEX_F80CVTTO_8, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+          *Info = {FABI_F80_I16_F64, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle8, Core::OPINDEX_F80CVTTO_8, SupportsPreserveAllABI};
          return true;
        }
      default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
@@ -107,11 +107,11 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
    case IR::OP_F80CVT: {
      switch (OpSize) {
        case 4: {
-          *Info = {FABI_F32_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4, Core::OPINDEX_F80CVT_4, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+          *Info = {FABI_F32_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle4, Core::OPINDEX_F80CVT_4, SupportsPreserveAllABI};
          return true;
        }
        case 8: {
-          *Info = {FABI_F64_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8, Core::OPINDEX_F80CVT_8, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+          *Info = {FABI_F64_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVT>::handle8, Core::OPINDEX_F80CVT_8, SupportsPreserveAllABI};
          return true;
        }
        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
@@ -124,28 +124,28 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
      switch (OpSize) {
        case 2: {
          if (Op->Truncate) {
-            *Info = {FABI_I16_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+            *Info = {FABI_I16_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2t, Core::OPINDEX_F80CVTINT_TRUNC2, SupportsPreserveAllABI};
          }
          else {
-            *Info = {FABI_I16_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2, Core::OPINDEX_F80CVTINT_2, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+            *Info = {FABI_I16_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle2, Core::OPINDEX_F80CVTINT_2, SupportsPreserveAllABI};
          }
          return true;
        }
        case 4: {
          if (Op->Truncate) {
-            *Info = {FABI_I32_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+            *Info = {FABI_I32_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4t, Core::OPINDEX_F80CVTINT_TRUNC4, SupportsPreserveAllABI};
          }
          else {
-            *Info = {FABI_I32_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4, Core::OPINDEX_F80CVTINT_4, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+            *Info = {FABI_I32_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle4, Core::OPINDEX_F80CVTINT_4, SupportsPreserveAllABI};
          }
          return true;
        }
        case 8: {
          if (Op->Truncate) {
-            *Info = {FABI_I64_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+            *Info = {FABI_I64_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8t, Core::OPINDEX_F80CVTINT_TRUNC8, SupportsPreserveAllABI};
          }
          else {
-            *Info = {FABI_I64_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8, Core::OPINDEX_F80CVTINT_8, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+            *Info = {FABI_I64_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTINT>::handle8, Core::OPINDEX_F80CVTINT_8, SupportsPreserveAllABI};
          }
          return true;
        }
@@ -167,7 +167,7 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
        &FEXCore::CPU::OpHandlers<IR::OP_F80CMP>::handle<7>,
      };

-      *Info = {FABI_I64_I16_F80_F80, (void*)handlers[Op->Flags], (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP_0 + Op->Flags), FEXCORE_HAS_PRESERVE_ALL_ATTR};
+      *Info = {FABI_I64_I16_F80_F80, (void*)handlers[Op->Flags], (Core::FallbackHandlerIndex)(Core::OPINDEX_F80CMP_0 + Op->Flags), SupportsPreserveAllABI};
      return true;
    }

@@ -176,11 +176,11 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf

      switch (Op->SrcSize) {
        case 2: {
-          *Info = {FABI_F80_I16_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2, Core::OPINDEX_F80CVTTOINT_2, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+          *Info = {FABI_F80_I16_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle2, Core::OPINDEX_F80CVTTOINT_2, SupportsPreserveAllABI};
          return true;
        }
        case 4: {
-          *Info = {FABI_F80_I16_I32, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4, Core::OPINDEX_F80CVTTOINT_4, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+          *Info = {FABI_F80_I16_I32, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTOINT>::handle4, Core::OPINDEX_F80CVTTOINT_4, SupportsPreserveAllABI};
          return true;
        }
        default: LogMan::Msg::DFmt("Unhandled size: {}", OpSize);
@@ -190,13 +190,13 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf

 #define COMMON_UNARY_X87_OP(OP) \
    case IR::OP_F80##OP: { \
-      *Info = {FABI_F80_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP, FEXCORE_HAS_PRESERVE_ALL_ATTR}; \
+      *Info = {FABI_F80_I16_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP, SupportsPreserveAllABI}; \
      return true; \
    }

 #define COMMON_BINARY_X87_OP(OP) \
    case IR::OP_F80##OP: { \
-      *Info = {FABI_F80_I16_F80_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP, FEXCORE_HAS_PRESERVE_ALL_ATTR}; \
+      *Info = {FABI_F80_I16_F80_F80, (void*)&FEXCore::CPU::OpHandlers<IR::OP_F80##OP>::handle, Core::OPINDEX_F80##OP, SupportsPreserveAllABI}; \
      return true; \
    }

@@ -244,10 +244,10 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf

    // SSE4.2 Fallbacks
    case IR::OP_VPCMPESTRX:
-      *Info = {FABI_I32_I64_I64_I128_I128_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+      *Info = {FABI_I32_I64_I64_I128_I128_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX, SupportsPreserveAllABI};
      return true;
    case IR::OP_VPCMPISTRX:
-      *Info = {FABI_I32_I128_I128_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX, FEXCORE_HAS_PRESERVE_ALL_ATTR};
+      *Info = {FABI_I32_I128_I128_I16, (void*)&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX, SupportsPreserveAllABI};
      return true;

    default:
@@ -7,7 +7,6 @@

 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IntrusiveIRList.h>

 namespace FEXCore::IR {
    class IRListView;
@@ -45,6 +44,6 @@ namespace FEXCore::CPU {
  class InterpreterOps {
    public:
      static void FillFallbackIndexPointers(uint64_t *Info);
-      static bool GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInfo *Info);
+      static bool GetFallbackHandler(bool SupportsPreserveAllABI, IR::IROp_Header const *IROp, FallbackInfo *Info);
  };
 } // namespace FEXCore::CPU
@@ -5,6 +5,7 @@ tags: backend|arm64
 $end_info$
 */

+#include "FEXCore/IR/IR.h"
 #include "Interface/Context/Context.h"
 #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
@@ -85,18 +86,51 @@ DEF_OP(Add) {
  }
 }

-DEF_OP(AddNZCV) {
-  auto Op = IROp->C<IR::IROp_AddNZCV>();
-  const auto OpSize = IROp->Size;
+DEF_OP(AddWithFlags) {
+  auto Op = IROp->C<IR::IROp_AddWithFlags>();
+  const uint8_t OpSize = IROp->Size;

-  LOGMAN_THROW_AA_FMT(OpSize == IR::i32Bit || OpSize == IR::i64Bit, "Unsupported {} size: {}", __func__, OpSize);
+  LOGMAN_THROW_AA_FMT(OpSize == 4 || OpSize == 8, "Unsupported {} size: {}", __func__, OpSize);
  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;

  uint64_t Const;
  if (IsInlineConstant(Op->Src2, &Const)) {
-    cmn(EmitSize, GetReg(Op->Src1.ID()), Const);
+    adds(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), Const);
  } else {
-    cmn(EmitSize, GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()));
+    adds(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()));
+  }
+}
+
+DEF_OP(AddShift) {
+  auto Op = IROp->C<IR::IROp_AddShift>();
+  const uint8_t OpSize = IROp->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == 4 || OpSize == 8, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  add(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()), ConvertIRShiftType(Op->Shift), Op->ShiftAmount);
+}
+
+DEF_OP(AddNZCV) {
+  auto Op = IROp->C<IR::IROp_AddNZCV>();
+  const uint8_t OpSize = IROp->Size;
+
+  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+  auto Src1 = GetReg(Op->Src1.ID());
+
+  uint64_t Const;
+  if (IsInlineConstant(Op->Src2, &Const)) {
+    LOGMAN_THROW_AA_FMT(OpSize >= 4, "Constant not allowed here");
+    cmn(EmitSize, Src1, Const);
+  } else {
+    unsigned Shift = OpSize < 4 ? (32 - (8 * OpSize)) : 0;
+
+    if (OpSize < 4) {
+      lsl(ARMEmitter::Size::i32Bit, TMP1, Src1, Shift);
+      cmn(EmitSize, TMP1, GetReg(Op->Src2.ID()), ARMEmitter::ShiftType::LSL, Shift);
+    } else {
+      cmn(EmitSize, Src1, GetReg(Op->Src2.ID()));
+    }
  }
 }

@@ -110,6 +144,36 @@ DEF_OP(AdcNZCV) {
  adcs(EmitSize, ARMEmitter::Reg::zr, GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()));
 }

+DEF_OP(AdcWithFlags) {
+  auto Op = IROp->C<IR::IROp_AdcWithFlags>();
+  const auto OpSize = IROp->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == IR::i32Bit || OpSize == IR::i64Bit, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  adcs(EmitSize, GetReg(Node), GetZeroableReg(Op->Src1), GetReg(Op->Src2.ID()));
+}
+
+DEF_OP(Adc) {
+  auto Op = IROp->C<IR::IROp_Adc>();
+  const auto OpSize = IROp->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == IR::i32Bit || OpSize == IR::i64Bit, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  adc(EmitSize, GetReg(Node), GetZeroableReg(Op->Src1), GetReg(Op->Src2.ID()));
+}
+
+DEF_OP(SbbWithFlags) {
+  auto Op = IROp->C<IR::IROp_SbbWithFlags>();
+  const auto OpSize = IROp->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == IR::i32Bit || OpSize == IR::i64Bit, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  sbcs(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()));
+}
+
 DEF_OP(SbbNZCV) {
  auto Op = IROp->C<IR::IROp_SbbNZCV>();
  const auto OpSize = IROp->Size;
@@ -120,6 +184,16 @@ DEF_OP(SbbNZCV) {
  sbcs(EmitSize, ARMEmitter::Reg::zr, GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()));
 }

+DEF_OP(Sbb) {
+  auto Op = IROp->C<IR::IROp_Sbb>();
+  const auto OpSize = IROp->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == IR::i32Bit || OpSize == IR::i64Bit, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  sbc(EmitSize, GetReg(Node), GetZeroableReg(Op->Src1), GetReg(Op->Src2.ID()));
+}
+
 DEF_OP(TestNZ) {
  auto Op = IROp->C<IR::IROp_TestNZ>();
  const uint8_t OpSize = IROp->Size;
@@ -168,7 +242,7 @@ DEF_OP(Sub) {
  if (IsInlineConstant(Op->Src2, &Const)) {
    sub(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), Const);
  } else {
-    sub(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()));
+    sub(EmitSize, GetReg(Node), GetZeroableReg(Op->Src1), GetReg(Op->Src2.ID()));
  }
 }

@@ -182,21 +256,72 @@ DEF_OP(SubShift) {
  sub(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()), ConvertIRShiftType(Op->Shift), Op->ShiftAmount);
 }

-DEF_OP(SubNZCV) {
-  auto Op = IROp->C<IR::IROp_SubNZCV>();
-  const auto OpSize = IROp->Size;
+DEF_OP(SubWithFlags) {
+  auto Op = IROp->C<IR::IROp_SubWithFlags>();
+  const uint8_t OpSize = IROp->Size;

-  LOGMAN_THROW_AA_FMT(OpSize == IR::i32Bit || OpSize == IR::i64Bit, "Unsupported {} size: {}", __func__, OpSize);
+  LOGMAN_THROW_AA_FMT(OpSize == 4 || OpSize == 8, "Unsupported {} size: {}", __func__, OpSize);
  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;

  uint64_t Const;
  if (IsInlineConstant(Op->Src2, &Const)) {
-    cmp(EmitSize, GetReg(Op->Src1.ID()), Const);
-  } else if (IsInlineConstant(Op->Src1, &Const)) {
-    LOGMAN_THROW_AA_FMT(Const == 0, "Only valid constant");
-    cmp(EmitSize, ARMEmitter::Reg::zr, GetReg(Op->Src2.ID()));
+    subs(EmitSize, GetReg(Node), GetZeroableReg(Op->Src1), Const);
  } else {
-    cmp(EmitSize, GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()));
+    subs(EmitSize, GetReg(Node), GetZeroableReg(Op->Src1), GetReg(Op->Src2.ID()));
+  }
+}
+
+DEF_OP(SubNZCV) {
+  auto Op = IROp->C<IR::IROp_SubNZCV>();
+  const uint8_t OpSize = IROp->Size;
+
+  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  uint64_t Const;
+  if (IsInlineConstant(Op->Src2, &Const)) {
+    LOGMAN_THROW_AA_FMT(OpSize >= 4, "Constant not allowed here");
+    cmp(EmitSize, GetReg(Op->Src1.ID()), Const);
+  } else {
+    unsigned Shift = OpSize < 4 ? (32 - (8 * OpSize)) : 0;
+    ARMEmitter::Register ShiftedSrc1 = GetZeroableReg(Op->Src1);
+
+    // Shift to fix flags for <32-bit ops.
+    // Any shift of zero is still zero so optimize out silly zero shifts.
+    if (OpSize < 4 && ShiftedSrc1 != ARMEmitter::Reg::zr) {
+      lsl(ARMEmitter::Size::i32Bit, TMP1, ShiftedSrc1, Shift);
+      ShiftedSrc1 = TMP1;
+    }
+
+    if (OpSize < 4) {
+      cmp(EmitSize, ShiftedSrc1, GetReg(Op->Src2.ID()), ARMEmitter::ShiftType::LSL, Shift);
+    } else {
+      cmp(EmitSize, ShiftedSrc1, GetReg(Op->Src2.ID()));
+    }
+  }
+}
+
+DEF_OP(CmpPairZ) {
+  auto Op = IROp->C<IR::IROp_CmpPairZ>();
+  const uint8_t OpSize = IROp->Size;
+
+  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  // Save NZCV
+  mrs(TMP1, ARMEmitter::SystemRegister::NZCV);
+
+  // Compare, setting Z and clobbering NzCV
+  const auto Src1 = GetRegPair(Op->Src1.ID());
+  const auto Src2 = GetRegPair(Op->Src2.ID());
+  cmp(EmitSize, Src1.first, Src2.first);
+  ccmp(EmitSize, Src1.second, Src2.second, ARMEmitter::StatusFlags::None, ARMEmitter::Condition::CC_EQ);
+
+  // Restore NzCV
+  if (CTX->HostFeatures.SupportsFlagM) {
+    rmif(TMP1, 0, 0xb /* NzCV */);
+  } else {
+    cset(ARMEmitter::Size::i32Bit, TMP2, ARMEmitter::Condition::CC_EQ);
+    bfi(ARMEmitter::Size::i32Bit, TMP1, TMP2, 30 /* lsb: Z */, 1);
+    msr(ARMEmitter::SystemRegister::NZCV, TMP1);
  }
 }

@@ -209,7 +334,21 @@ DEF_OP(RmifNZCV) {
  auto Op = IROp->C<IR::IROp_RmifNZCV>();
  LOGMAN_THROW_A_FMT(CTX->HostFeatures.SupportsFlagM, "Unsupported flagm op");

-  rmif(GetReg(Op->Src.ID()).X(), Op->Rotate, Op->Mask);
+  rmif(GetZeroableReg(Op->Src).X(), Op->Rotate, Op->Mask);
+}
+
+DEF_OP(SetSmallNZV) {
+  auto Op = IROp->C<IR::IROp_SetSmallNZV>();
+  LOGMAN_THROW_A_FMT(CTX->HostFeatures.SupportsFlagM, "Unsupported flagm op");
+
+  const uint8_t OpSize = IROp->Size;
+  LOGMAN_THROW_AA_FMT(OpSize == 1 || OpSize == 2, "Unsupported {} size: {}", __func__, OpSize);
+
+  if (OpSize == 1) {
+    setf8(GetReg(Op->Src.ID()).W());
+  } else {
+    setf16(GetReg(Op->Src.ID()).W());
+  }
 }

 DEF_OP(AXFlag) {
@@ -254,9 +393,7 @@ DEF_OP(CondAddNZCV) {

  ARMEmitter::StatusFlags Flags = (ARMEmitter::StatusFlags)Op->FalseNZCV;
  uint64_t Const = 0;
-  auto Src1 = IsInlineConstant(Op->Src1, &Const) ? ARMEmitter::Reg::zr :
-                                                   GetReg(Op->Src1.ID());
-  LOGMAN_THROW_A_FMT(Const == 0, "Unsupported inline constant");
+  auto Src1 = GetZeroableReg(Op->Src1);

  if (IsInlineConstant(Op->Src2, &Const)) {
    ccmn(EmitSize, Src1, Const, Flags, MapSelectCC(Op->Cond));
@@ -265,6 +402,24 @@ DEF_OP(CondAddNZCV) {
  }
 }

+DEF_OP(CondSubNZCV) {
+  auto Op = IROp->C<IR::IROp_CondSubNZCV>();
+  const auto OpSize = IROp->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == IR::i32Bit || OpSize == IR::i64Bit, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == IR::i64Bit ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  ARMEmitter::StatusFlags Flags = (ARMEmitter::StatusFlags)Op->FalseNZCV;
+  uint64_t Const = 0;
+  auto Src1 = GetZeroableReg(Op->Src1);
+
+  if (IsInlineConstant(Op->Src2, &Const)) {
+    ccmp(EmitSize, Src1, Const, Flags, MapSelectCC(Op->Cond));
+  } else {
+    ccmp(EmitSize, Src1, GetReg(Op->Src2.ID()), Flags, MapSelectCC(Op->Cond));
+  }
+}
+
 DEF_OP(Neg) {
  auto Op = IROp->C<IR::IROp_Neg>();
  const uint8_t OpSize = IROp->Size;
@@ -298,6 +453,16 @@ DEF_OP(UMul) {
  mul(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()));
 }

+DEF_OP(UMull) {
+  auto Op = IROp->C<IR::IROp_UMull>();
+  umull(GetReg(Node).X(), GetReg(Op->Src1.ID()).W(), GetReg(Op->Src2.ID()).W());
+}
+
+DEF_OP(SMull) {
+  auto Op = IROp->C<IR::IROp_SMull>();
+  smull(GetReg(Node).X(), GetReg(Op->Src1.ID()).W(), GetReg(Op->Src2.ID()).W());
+}
+
 DEF_OP(Div) {
  auto Op = IROp->C<IR::IROp_Div>();

@@ -543,6 +708,41 @@ DEF_OP(And) {
  }
 }

+DEF_OP(AndWithFlags) {
+  auto Op = IROp->C<IR::IROp_AndWithFlags>();
+  const uint8_t OpSize = IROp->Size;
+  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  uint64_t Const;
+  const auto Dst = GetReg(Node);
+  auto Src1 = GetReg(Op->Src1.ID());
+
+  // See TestNZ
+  if (OpSize < 4) {
+    if (IsInlineConstant(Op->Src2, &Const)) {
+      and_(EmitSize, Dst, Src1, Const);
+    } else {
+      auto Src2 = GetReg(Op->Src2.ID());
+
+      if (Src1 != Src2) {
+        and_(EmitSize, Dst, Src1, Src2);
+      } else if (Dst != Src1) {
+        mov(ARMEmitter::Size::i64Bit, Dst, Src1);
+      }
+    }
+
+    unsigned Shift = 32 - (OpSize * 8);
+    cmn(EmitSize, ARMEmitter::Reg::zr, Dst, ARMEmitter::ShiftType::LSL, Shift);
+  } else {
+    if (IsInlineConstant(Op->Src2, &Const)) {
+      ands(EmitSize, Dst, Src1, Const);
+    } else {
+      const auto Src2 = GetReg(Op->Src2.ID());
+      ands(EmitSize, Dst, Src1, Src2);
+    }
+  }
+}
+
 DEF_OP(Andn) {
  auto Op = IROp->C<IR::IROp_Andn>();
  const uint8_t OpSize = IROp->Size;
@@ -587,6 +787,16 @@ DEF_OP(XorShift) {
  eor(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()), ConvertIRShiftType(Op->Shift), Op->ShiftAmount);
 }

+DEF_OP(XornShift) {
+  auto Op = IROp->C<IR::IROp_XornShift>();
+  const uint8_t OpSize = IROp->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == 4 || OpSize == 8, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  eon(EmitSize, GetReg(Node), GetReg(Op->Src1.ID()), GetReg(Op->Src2.ID()), ConvertIRShiftType(Op->Shift), Op->ShiftAmount);
+}
+
 DEF_OP(Lshl) {
  auto Op = IROp->C<IR::IROp_Lshl>();
  const uint8_t OpSize = IROp->Size;
@@ -693,64 +903,58 @@ DEF_OP(PDep) {
  LOGMAN_THROW_AA_FMT(OpSize == 4 || OpSize == 8, "Unsupported {} size: {}", __func__, OpSize);
  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;

-  const auto Input = GetReg(Op->Input.ID());
-  const auto Mask = GetReg(Op->Mask.ID());
  const auto Dest = GetReg(Node);

-  const auto ShiftedBitReg = TMP1.R();
-  const auto BitReg        = TMP2.R();
-  const auto SubMaskReg    = TMP3.R();
-  const auto IndexReg      = TMP4.R();
-  const auto ZeroReg       = ARMEmitter::Reg::zr;
+  // PDep implementation follows the ideas from
+  // http://0x80.pl/articles/pdep-soft-emu.html ... Basically, iterate the *set*
+  // bits only, which will be faster than the naive implementation as long as
+  // there are enough holes in the mask.
+  //
+  // The specific arm64 assembly used is based on the sequence that clang
+  // generates for the C code, giving context to the scheduling yielding better
+  // ILP than I would do by hand. The registers are allocated by hand however,
+  // to fit within the tight constraints we have here withot spilling. Also, we
+  // use cbz/cbnz for conditional branching to avoid clobbering NZCV.

-  const auto InputReg = StaticRegisters[0];
-  const auto MaskReg  = StaticRegisters[1];
-  const auto DestReg  = StaticRegisters[2];
+  // We can't clobber these
+  const auto OrigInput = GetReg(Op->Input.ID());
+  const auto OrigMask = GetReg(Op->Mask.ID());

-  const auto SpillCode = 1U << InputReg.Idx() |
-                         1U << MaskReg.Idx() |
-                         1U << DestReg.Idx();
+  // So we have shadow as temporaries
+  const auto Input = TMP1.R();
+  const auto Mask  = TMP2.R();
+
+  // these get used variously as scratch
+  const auto T0    = TMP3.R();
+  const auto T1    = TMP4.R();

-  ARMEmitter::ForwardLabel EarlyExit;
  ARMEmitter::BackwardLabel NextBit;
-  ARMEmitter::ForwardLabel Done;
-  cbz(EmitSize, Mask, &EarlyExit);
-  mov(EmitSize, IndexReg, ZeroReg);
+  ARMEmitter::SingleUseForwardLabel Done;

-  // We sadly need to spill regs for this for the time being
-  // TODO: Remove when scratch registers can be allocated
-  //       explicitly.
-  SpillStaticRegs(TMP1, false, SpillCode);
+  // First, copy the input/mask, since we'll be clobbering. Copy as 64-bit to
+  // make this 0-uop on Firestorm.
+  mov(ARMEmitter::Size::i64Bit, Input, OrigInput);
+  mov(ARMEmitter::Size::i64Bit, Mask, OrigMask);

+  // Now, they're copied, so we can start setting Dest (even if it overlaps with
+  // one of them).  Handle early exit case
+  mov(EmitSize, Dest, 0);
+  cbz(EmitSize, OrigMask, &Done);

-  mov(EmitSize, InputReg, Input);
-  mov(EmitSize, MaskReg, Mask);
-  mov(EmitSize, DestReg, ZeroReg);
+  // Setup for first iteration
+  neg(EmitSize, T0, Mask);
+  and_(EmitSize, T0, T0, Mask);

  // Main loop
  Bind(&NextBit);
-  rbit(EmitSize, ShiftedBitReg, MaskReg);
-  clz(EmitSize, ShiftedBitReg, ShiftedBitReg);
-  lsrv(EmitSize, BitReg, InputReg, IndexReg);
-  and_(EmitSize, BitReg, BitReg, 1);
-  sub(EmitSize, SubMaskReg, MaskReg, 1);
-  add(EmitSize, IndexReg, IndexReg, 1);
-  ands(EmitSize, MaskReg, MaskReg, SubMaskReg);
-  lslv(EmitSize, ShiftedBitReg, BitReg, ShiftedBitReg);
-  orr(EmitSize, DestReg, DestReg, ShiftedBitReg);
-  b(ARMEmitter::Condition::CC_NE, &NextBit);
-  // Store result in a temp so it doesn't get clobbered.
-  // and restore it after the re-fill below.
-  mov(EmitSize, IndexReg, DestReg);
-  // Restore our registers before leaving
-  // TODO: Also remove along with above TODO.
-  FillStaticRegs(false, SpillCode);
-  mov(EmitSize, Dest, IndexReg);
-  b(&Done);
-
-  // Early exit
-  Bind(&EarlyExit);
-  mov(EmitSize, Dest, ZeroReg);
+  sbfx(EmitSize, T1, Input, 0, 1);
+  eor(EmitSize, Mask, Mask, T0);
+  and_(EmitSize, T0, T1, T0);
+  neg(EmitSize, T1, Mask);
+  orr(EmitSize, Dest, Dest, T0);
+  lsr(EmitSize, Input, Input, 1);
+  and_(EmitSize, T0, Mask, T1);
+  cbnz(EmitSize, T0, &NextBit);

  // All done with nothing to do.
  Bind(&Done);
@@ -772,9 +976,9 @@ DEF_OP(PExt) {
  const auto BitReg   = TMP2;
  const auto ValueReg = TMP3;

-  ARMEmitter::ForwardLabel EarlyExit;
+  ARMEmitter::SingleUseForwardLabel EarlyExit;
  ARMEmitter::BackwardLabel NextBit;
-  ARMEmitter::ForwardLabel Done;
+  ARMEmitter::SingleUseForwardLabel Done;

  cbz(EmitSize, Mask, &EarlyExit);
  mov(EmitSize, MaskReg, Mask);
@@ -828,8 +1032,8 @@ DEF_OP(LDiv) {
    break;
    }
    case 8: {
-      ARMEmitter::ForwardLabel Only64Bit{};
-      ARMEmitter::ForwardLabel LongDIVRet{};
+      ARMEmitter::SingleUseForwardLabel Only64Bit{};
+      ARMEmitter::SingleUseForwardLabel LongDIVRet{};

      // Check if the upper bits match the top bit of the lower 64-bits
      // Sign extend the top bit of lower bits
@@ -841,18 +1045,18 @@ DEF_OP(LDiv) {

      // Long divide
      {
-        mov(EmitSize, ARMEmitter::Reg::r0, Upper);
-        mov(EmitSize, ARMEmitter::Reg::r1, Lower);
-        mov(EmitSize, ARMEmitter::Reg::r2, Divisor);
+        mov(EmitSize, TMP1, Upper);
+        mov(EmitSize, TMP2, Lower);
+        mov(EmitSize, TMP3, Divisor);

-        ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LDIVHandler));
+        ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LDIVHandler));

        str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
-        blr(ARMEmitter::Reg::r3);
+        blr(TMP4);
        ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);

        // Move result to its destination register
-        mov(EmitSize, Dst, ARMEmitter::Reg::r0);
+        mov(EmitSize, Dst, TMP1);

        // Skip 64-bit path
        b(&LongDIVRet);
@@ -900,8 +1104,8 @@ DEF_OP(LUDiv) {
    break;
    }
    case 8: {
-      ARMEmitter::ForwardLabel Only64Bit{};
-      ARMEmitter::ForwardLabel LongDIVRet{};
+      ARMEmitter::SingleUseForwardLabel Only64Bit{};
+      ARMEmitter::SingleUseForwardLabel LongDIVRet{};

      // Check the upper bits for zero
      // If the upper bits are zero then we can do a 64-bit divide
@@ -909,18 +1113,18 @@ DEF_OP(LUDiv) {

      // Long divide
      {
-        mov(EmitSize, ARMEmitter::Reg::r0, Upper);
-        mov(EmitSize, ARMEmitter::Reg::r1, Lower);
-        mov(EmitSize, ARMEmitter::Reg::r2, Divisor);
+        mov(EmitSize, TMP1, Upper);
+        mov(EmitSize, TMP2, Lower);
+        mov(EmitSize, TMP3, Divisor);

-        ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUDIVHandler));
+        ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUDIVHandler));

        str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
-        blr(ARMEmitter::Reg::r3);
+        blr(TMP4);
        ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);

        // Move result to its destination register
-        mov(EmitSize, Dst, ARMEmitter::Reg::r0);
+        mov(EmitSize, Dst, TMP1);

        // Skip 64-bit path
        b(&LongDIVRet);
@@ -972,8 +1176,8 @@ DEF_OP(LRem) {
    break;
    }
    case 8: {
-      ARMEmitter::ForwardLabel Only64Bit{};
-      ARMEmitter::ForwardLabel LongDIVRet{};
+      ARMEmitter::SingleUseForwardLabel Only64Bit{};
+      ARMEmitter::SingleUseForwardLabel LongDIVRet{};

      // Check if the upper bits match the top bit of the lower 64-bits
      // Sign extend the top bit of lower bits
@@ -985,18 +1189,18 @@ DEF_OP(LRem) {

      // Long divide
      {
-        mov(EmitSize, ARMEmitter::Reg::r0, Upper);
-        mov(EmitSize, ARMEmitter::Reg::r1, Lower);
-        mov(EmitSize, ARMEmitter::Reg::r2, Divisor);
+        mov(EmitSize, TMP1, Upper);
+        mov(EmitSize, TMP2, Lower);
+        mov(EmitSize, TMP3, Divisor);

-        ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LREMHandler));
+        ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LREMHandler));

        str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
-        blr(ARMEmitter::Reg::r3);
+        blr(TMP4);
        ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);

        // Move result to its destination register
-        mov(EmitSize, Dst, ARMEmitter::Reg::r0);
+        mov(EmitSize, Dst, TMP1);

        // Skip 64-bit path
        b(&LongDIVRet);
@@ -1046,8 +1250,8 @@ DEF_OP(LURem) {
    break;
    }
    case 8: {
-      ARMEmitter::ForwardLabel Only64Bit{};
-      ARMEmitter::ForwardLabel LongDIVRet{};
+      ARMEmitter::SingleUseForwardLabel Only64Bit{};
+      ARMEmitter::SingleUseForwardLabel LongDIVRet{};

      // Check the upper bits for zero
      // If the upper bits are zero then we can do a 64-bit divide
@@ -1055,18 +1259,18 @@ DEF_OP(LURem) {

      // Long divide
      {
-        mov(EmitSize, ARMEmitter::Reg::r0, Upper);
-        mov(EmitSize, ARMEmitter::Reg::r1, Lower);
-        mov(EmitSize, ARMEmitter::Reg::r2, Divisor);
+        mov(EmitSize, TMP1, Upper);
+        mov(EmitSize, TMP2, Lower);
+        mov(EmitSize, TMP3, Divisor);

-        ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUREMHandler));
+        ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUREMHandler));

        str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
-        blr(ARMEmitter::Reg::r3);
+        blr(TMP4);
        ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);

        // Move result to its destination register
-        mov(EmitSize, Dst, ARMEmitter::Reg::r0);
+        mov(EmitSize, Dst, TMP1);

        // Skip 64-bit path
        b(&LongDIVRet);
@@ -1199,6 +1403,11 @@ DEF_OP(FindTrailingZeroes) {
  rbit(EmitSize, Dst, Src);

  if (OpSize == 2) {
+    // This orr does two things. First, if the (masked) source is zero, it
+    // reverses to zero in the top so it forces clz to return 16. Second, it
+    // ensures garbage in the upper bits of the source don't affect clz, because
+    // they'll rbit to garbage in the bottom below the 0x8000 and be ignored by
+    // the clz. So we handle Src upper garbage without explicitly masking.
    orr(EmitSize, Dst, Dst, 0x8000);
  }

@@ -1216,6 +1425,8 @@ DEF_OP(CountLeadingZeroes) {
  const auto Src = GetReg(Op->Src.ID());

  if (OpSize == 2) {
+    // Expressing as lsl+orr+clz clears away any garbage in the upper bits
+    // (alternatively could do uxth+clz+sub.. equal cost in total).
    lsl(EmitSize, Dst, Src, 16);
    orr(EmitSize, Dst, Dst, 0x8000);
    clz(EmitSize, Dst, Dst);
@@ -1414,11 +1625,8 @@ DEF_OP(NZCVSelect) {
      csetm(EmitSize, Dst, cc);
    else
      cset(EmitSize, Dst, cc);
-  } else if (is_const_false) {
-    LOGMAN_THROW_A_FMT(const_false == 0, "NZCVSelect: unsupported constant");
-    csel(EmitSize, Dst, GetReg(Op->TrueVal.ID()), ARMEmitter::Reg::zr, cc);
  } else {
-    csel(EmitSize, Dst, GetReg(Op->TrueVal.ID()), GetReg(Op->FalseVal.ID()), cc);
+    csel(EmitSize, Dst, GetReg(Op->TrueVal.ID()), GetZeroableReg(Op->FalseVal), cc);
  }
 }

@@ -31,11 +31,19 @@ DEF_OP(CASPair) {
    mov(EmitSize, Dst.second, TMP4.R());
  }
  else {
+    // Save NZCV so we don't have to mark this op as clobbering NZCV (the
+    // SupportsAtomics does not clobber atomics and this !SupportsAtomics path
+    // is so slow it's not worth the complexity of splitting the IR op.). We
+    // clobber NZCV inside the hot loop and we can't replace cmp/ccmp/b.ne with
+    // something NZCV-preserving without requiring an extra instruction.
+    mrs(TMP1, ARMEmitter::SystemRegister::NZCV);
+
    ARMEmitter::BackwardLabel LoopTop;
-    ARMEmitter::ForwardLabel LoopNotExpected;
-    ARMEmitter::ForwardLabel LoopExpected;
+    ARMEmitter::SingleUseForwardLabel LoopNotExpected;
+    ARMEmitter::SingleUseForwardLabel LoopExpected;
    Bind(&LoopTop);

+    // This instruction sequence must be synced with HandleCASPAL_Armv8.
    ldaxp(EmitSize, TMP2, TMP3, MemSrc);
    cmp(EmitSize, TMP2, Expected.first);
    ccmp(EmitSize, TMP3, Expected.second, ARMEmitter::StatusFlags::None, ARMEmitter::Condition::CC_EQ);
@@ -54,6 +62,9 @@ DEF_OP(CASPair) {
      // Might have hit the case where ldaxr was hit but stlxr wasn't
      clrex();
    Bind(&LoopExpected);
+
+    // Restore
+    msr(ARMEmitter::SystemRegister::NZCV, TMP1);
  }
 }

@@ -82,8 +93,8 @@ DEF_OP(CAS) {
  }
  else {
    ARMEmitter::BackwardLabel LoopTop;
-    ARMEmitter::ForwardLabel LoopNotExpected;
-    ARMEmitter::ForwardLabel LoopExpected;
+    ARMEmitter::SingleUseForwardLabel LoopNotExpected;
+    ARMEmitter::SingleUseForwardLabel LoopExpected;
    Bind(&LoopTop);
    ldaxr(SubEmitSize, TMP2, MemSrc);
    if (OpSize == 1) {
@@ -310,8 +321,7 @@ DEF_OP(AtomicSwap) {
    OpSize == 1 ? ARMEmitter::SubRegSize::i8Bit : ARMEmitter::SubRegSize::i8Bit;

  if (CTX->HostFeatures.SupportsAtomics) {
-    mov(EmitSize, TMP2, Src);
-    ldswpal(SubEmitSize, TMP2, GetReg(Node), MemSrc);
+    ldswpal(SubEmitSize, Src, GetReg(Node), MemSrc);
  }
  else {
    ARMEmitter::BackwardLabel LoopTop;
@@ -11,9 +11,9 @@ $end_info$
 #include "Interface/Core/LookupCache.h"

 #include "Interface/Core/JIT/Arm64/JITClass.h"
-#include "Interface/Core/InternalThreadState.h"

 #include <FEXCore/Core/X86Enums.h>
+#include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/Utils/MathUtils.h>
 #include <Interface/HLE/Thunks/Thunks.h>
@@ -53,33 +53,30 @@ DEF_OP(ExitFunction) {
  uint64_t NewRIP;

  if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
-    ARMEmitter::ForwardLabel l_BranchHost;
-    ARMEmitter::ForwardLabel l_BranchGuest;
+    ARMEmitter::SingleUseForwardLabel l_BranchHost;

-    ldr(ARMEmitter::XReg::x0, &l_BranchHost);
-    blr(ARMEmitter::Reg::r0);
+    ldr(TMP1, &l_BranchHost);
+    blr(TMP1);

    Bind(&l_BranchHost);
    dc64(ThreadState->CurrentFrame->Pointers.Common.ExitFunctionLinker);
-    Bind(&l_BranchGuest);
    dc64(NewRIP);
-
  } else {

-    ARMEmitter::ForwardLabel FullLookup;
+    ARMEmitter::SingleUseForwardLabel FullLookup;
    auto RipReg = GetReg(Op->NewRIP.ID());

    // L1 Cache
-    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.L1Pointer));
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.L1Pointer));

-    and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, RipReg, LookupCache::L1_ENTRIES_MASK);
-    add(ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, ARMEmitter::XReg::x3, ARMEmitter::ShiftType::LSL, 4);
+    and_(ARMEmitter::Size::i64Bit, TMP4, RipReg, LookupCache::L1_ENTRIES_MASK);
+    add(TMP1, TMP1, TMP4, ARMEmitter::ShiftType::LSL, 4);

    // Note: sub+cbnz used over cmp+br to preserve flags.
-    ldp<ARMEmitter::IndexType::OFFSET>(ARMEmitter::XReg::x1, ARMEmitter::XReg::x0, ARMEmitter::Reg::r0, 0);
-    sub(TMP1, ARMEmitter::XReg::x0, RipReg.X());
+    ldp<ARMEmitter::IndexType::OFFSET>(TMP2, TMP1, TMP1, 0);
+    sub(TMP1, TMP1, RipReg.X());
    cbnz(ARMEmitter::Size::i64Bit, TMP1, &FullLookup);
-    br(ARMEmitter::Reg::r1);
+    br(TMP2);

    Bind(&FullLookup);
    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop));
@@ -131,8 +128,8 @@ DEF_OP(CondJump) {
  if (Op->FromNZCV) {
    b(MapBranchCC(Op->Cond), TrueTargetLabel);
  } else {
-    uint64_t Const;
-    const bool isConst = IsInlineConstant(Op->Cmp2, &Const);
+    [[maybe_unused]] uint64_t Const;
+    [[maybe_unused]] const bool isConst = IsInlineConstant(Op->Cmp2, &Const);

    const auto Size = Op->CompareSize == 4 ? ARMEmitter::Size::i32Bit : ARMEmitter::Size::i64Bit;

@@ -353,58 +350,58 @@ DEF_OP(ValidateCode) {
  int idx = 0;

  LoadConstant(ARMEmitter::Size::i64Bit, GetReg(Node), 0);
-  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, Entry + Op->Offset);
-  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, 1);
+  LoadConstant(ARMEmitter::Size::i64Bit, TMP1, Entry + Op->Offset);
+  LoadConstant(ARMEmitter::Size::i64Bit, TMP2, 1);

  const auto Dst = GetReg(Node);

  while (len >= 8)
  {
-    ldr(ARMEmitter::XReg::x2, ARMEmitter::Reg::r0, idx);
-    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, *(const uint32_t *)(OldCode + idx));
-    cmp(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r3);
-    csel(ARMEmitter::Size::i64Bit, Dst, Dst, ARMEmitter::Reg::r1, ARMEmitter::Condition::CC_EQ);
+    ldr(ARMEmitter::XReg::x2, TMP1, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP4, *(const uint32_t *)(OldCode + idx));
+    cmp(ARMEmitter::Size::i64Bit, TMP3, TMP4);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, TMP2, ARMEmitter::Condition::CC_EQ);
    len -= 8;
    idx += 8;
  }
  while (len >= 4)
  {
-    ldr(ARMEmitter::WReg::w2, ARMEmitter::Reg::r0, idx);
-    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, *(const uint32_t *)(OldCode + idx));
-    cmp(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r3);
-    csel(ARMEmitter::Size::i64Bit, Dst, Dst, ARMEmitter::Reg::r1, ARMEmitter::Condition::CC_EQ);
+    ldr(ARMEmitter::WReg::w2, TMP1, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP4, *(const uint32_t *)(OldCode + idx));
+    cmp(ARMEmitter::Size::i32Bit, TMP3, TMP4);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, TMP2, ARMEmitter::Condition::CC_EQ);
    len -= 4;
    idx += 4;
  }
  while (len >= 2)
  {
-    ldrh(ARMEmitter::Reg::r2, ARMEmitter::Reg::r0, idx);
-    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, *(const uint16_t *)(OldCode + idx));
-    cmp(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r3);
-    csel(ARMEmitter::Size::i64Bit, Dst, Dst, ARMEmitter::Reg::r1, ARMEmitter::Condition::CC_EQ);
+    ldrh(TMP3, TMP1, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP4, *(const uint16_t *)(OldCode + idx));
+    cmp(ARMEmitter::Size::i32Bit, TMP3, TMP4);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, TMP2, ARMEmitter::Condition::CC_EQ);
    len -= 2;
    idx += 2;
  }
  while (len >= 1)
  {
-    ldrb(ARMEmitter::Reg::r2, ARMEmitter::Reg::r0, idx);
-    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, *(const uint8_t *)(OldCode + idx));
-    cmp(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r3);
-    csel(ARMEmitter::Size::i64Bit, Dst, Dst, ARMEmitter::Reg::r1, ARMEmitter::Condition::CC_EQ);
+    ldrb(TMP3, TMP1, idx);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP4, *(const uint8_t *)(OldCode + idx));
+    cmp(ARMEmitter::Size::i32Bit, TMP3, TMP4);
+    csel(ARMEmitter::Size::i64Bit, Dst, Dst, TMP2, ARMEmitter::Condition::CC_EQ);
    len -= 1;
    idx += 1;
  }
 }

 DEF_OP(ThreadRemoveCodeEntry) {
+  PushDynamicRegsAndLR(TMP4);
+  SpillStaticRegs(TMP4);
+
  // Arguments are passed as follows:
  // X0: Thread
  // X1: RIP
-
-  PushDynamicRegsAndLR(TMP1);
-  SpillStaticRegs(TMP1);
-
  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, STATE.R());
+
  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, Entry);

  ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadRemoveCodeEntryFromJIT));
@@ -423,16 +420,23 @@ DEF_OP(ThreadRemoveCodeEntry) {
 DEF_OP(CPUID) {
  auto Op = IROp->C<IR::IROp_CPUID>();

-  PushDynamicRegsAndLR(TMP1);
-  SpillStaticRegs(TMP1);
+  mov(ARMEmitter::Size::i64Bit, TMP2, GetReg(Op->Function.ID()));
+  mov(ARMEmitter::Size::i64Bit, TMP3, GetReg(Op->Leaf.ID()));
+
+  PushDynamicRegsAndLR(TMP4);
+  SpillStaticRegs(TMP4);

  // x0 = CPUID Handler
  // x1 = CPUID Function
  // x2 = CPUID Leaf
  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj));
  ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDFunction));
-  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, GetReg(Op->Function.ID()));
-  mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, GetReg(Op->Leaf.ID()));
+
+  if (!TMP_ABIARGS) {
+    mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, TMP2);
+    mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, TMP3);
+  }
+
  if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
    GenerateIndirectRuntimeCall<__uint128_t, void*, uint64_t, uint64_t>(ARMEmitter::Reg::r3);
  }
@@ -440,6 +444,11 @@ DEF_OP(CPUID) {
    blr(ARMEmitter::Reg::r3);
  }

+  if (!TMP_ABIARGS) {
+    mov(ARMEmitter::Size::i64Bit, TMP1, ARMEmitter::Reg::r0);
+    mov(ARMEmitter::Size::i64Bit, TMP2, ARMEmitter::Reg::r1);
+  }
+
  FillStaticRegs();

  PopDynamicRegsAndLR();
@@ -447,21 +456,22 @@ DEF_OP(CPUID) {
  // Results are in x0, x1
  // Results want to be in a i64v2 vector
  auto Dst = GetRegPair(Node);
-  mov(ARMEmitter::Size::i64Bit, Dst.first,  ARMEmitter::Reg::r0);
-  mov(ARMEmitter::Size::i64Bit, Dst.second, ARMEmitter::Reg::r1);
+  mov(ARMEmitter::Size::i64Bit, Dst.first,  TMP1);
+  mov(ARMEmitter::Size::i64Bit, Dst.second, TMP2);
 }

 DEF_OP(XGetBV) {
  auto Op = IROp->C<IR::IROp_XGetBV>();

-  PushDynamicRegsAndLR(TMP1);
-  SpillStaticRegs(TMP1);
+  PushDynamicRegsAndLR(TMP4);
+  SpillStaticRegs(TMP4);
+
+  mov(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, GetReg(Op->Function.ID()));

  // x0 = CPUID Handler
  // x1 = XCR Function
  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj));
  ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.XCRFunction));
-  mov(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, GetReg(Op->Function.ID()));
  if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
    GenerateIndirectRuntimeCall<uint64_t, void*, uint32_t>(ARMEmitter::Reg::r2);
  }
@@ -469,6 +479,10 @@ DEF_OP(XGetBV) {
    blr(ARMEmitter::Reg::r2);
  }

+  if (!TMP_ABIARGS) {
+    mov(ARMEmitter::Size::i64Bit, TMP1, ARMEmitter::Reg::r0);
+  }
+
  FillStaticRegs();

  PopDynamicRegsAndLR();
@@ -476,8 +490,8 @@ DEF_OP(XGetBV) {
  // Results are in x0
  // Results want to be in a i32v2 vector
  auto Dst = GetRegPair(Node);
-  mov(ARMEmitter::Size::i32Bit, Dst.first,  ARMEmitter::Reg::r0);
-  lsr(ARMEmitter::Size::i64Bit, Dst.second, ARMEmitter::Reg::r0, 32);
+  mov(ARMEmitter::Size::i32Bit, Dst.first,  TMP1);
+  lsr(ARMEmitter::Size::i64Bit, Dst.second, TMP1, 32);
 }

 #undef DEF_OP
@@ -201,7 +201,7 @@ DEF_OP(VSha256U0) {
  else {
    mov(VTMP1.Q(), Src1.Q());
    sha256su0(VTMP1, Src2);
-    mov(Dst.Q(), Src1.Q());
+    mov(Dst.Q(), VTMP1.Q());
  }
 }

@@ -18,17 +18,18 @@ $end_info$

 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
-#include "Interface/Core/InternalThreadState.h"

 #include "Interface/IR/Passes/RegisterAllocationPass.h"

 #include "Utils/MemberFunctionToPointer.h"

 #include <FEXCore/Core/X86Enums.h>
+#include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/Profiler.h>
+#include <FEXCore/HLE/SyscallHandler.h>

 #include "Interface/Core/Interpreter/InterpreterOps.h"

@@ -78,11 +79,45 @@ namespace FEXCore::CPU {

 void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
  FallbackInfo Info;
-  if (!InterpreterOps::GetFallbackHandler(IROp, &Info)) {
+  if (!InterpreterOps::GetFallbackHandler(CTX->HostFeatures.SupportsPreserveAllABI, IROp, &Info)) {
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
    LOGMAN_MSG_A_FMT("Unhandled IR Op: {}", FEXCore::IR::GetName(IROp->Op));
 #endif
  } else {
+    auto FillF80Result = [&]() {
+      if (!TMP_ABIARGS) {
+        mov(TMP1, ARMEmitter::XReg::x0);
+        mov(TMP2, ARMEmitter::XReg::x1);
+      }
+
+      FillForABICall(Info.SupportsPreserveAllABI, true);
+
+      const auto Dst = GetVReg(Node);
+      eor(Dst.Q(), Dst.Q(), Dst.Q());
+      ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, TMP1);
+      ins(ARMEmitter::SubRegSize::i16Bit, Dst, 4, TMP2);
+    };
+
+    auto FillF64Result = [&]() {
+      if (!TMP_ABIARGS) {
+        mov(VTMP1.D(), ARMEmitter::DReg::d0);
+      }
+      FillForABICall(Info.SupportsPreserveAllABI, true);
+
+      const auto Dst = GetVReg(Node);
+      mov(Dst.D(), VTMP1.D());
+    };
+
+    auto FillI32Result = [&]() {
+      if (!TMP_ABIARGS) {
+        mov(TMP1.W(), ARMEmitter::WReg::w0);
+      }
+      FillForABICall(Info.SupportsPreserveAllABI, true);
+
+      const auto Dst = GetReg(Node);
+      mov(Dst.W(), TMP1.W());
+    };
+
    switch(Info.ABI) {
      case FABI_F80_I16_F32:{
        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
@@ -98,12 +133,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r1);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetVReg(Node);
-        eor(Dst.Q(), Dst.Q(), Dst.Q());
-        ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, ARMEmitter::Reg::r0);
-        ins(ARMEmitter::SubRegSize::i16Bit, Dst, 4, ARMEmitter::Reg::r1);
+        FillF80Result();
      }
      break;

@@ -121,12 +151,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r1);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetVReg(Node);
-        eor(Dst.Q(), Dst.Q(), Dst.Q());
-        ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, ARMEmitter::Reg::r0);
-        ins(ARMEmitter::SubRegSize::i16Bit, Dst, 4, ARMEmitter::Reg::r1);
+        FillF80Result();
      }
      break;

@@ -135,13 +160,13 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);

        const auto Src1 = GetReg(IROp->Args[0].ID());
-        ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
        if (Info.ABI == FABI_F80_I16_I16) {
          sxth(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, Src1);
        }
        else {
          mov(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, Src1);
        }
+        ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
        ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
        if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
          GenerateIndirectRuntimeCall<__uint128_t, uint16_t, uint32_t>(ARMEmitter::Reg::r2);
@@ -150,12 +175,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r2);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetVReg(Node);
-        eor(Dst.Q(), Dst.Q(), Dst.Q());
-        ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, ARMEmitter::Reg::r0);
-        ins(ARMEmitter::SubRegSize::i16Bit, Dst, 4, ARMEmitter::Reg::r1);
+        FillF80Result();
      }
      break;

@@ -176,10 +196,13 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r3);
        }

+        if (!TMP_ABIARGS) {
+          fmov(VTMP1.S(), ARMEmitter::SReg::s0);
+        }
        FillForABICall(Info.SupportsPreserveAllABI, true);

        const auto Dst = GetVReg(Node);
-        fmov(Dst.S(), ARMEmitter::SReg::s0);
+        fmov(Dst.S(), VTMP1.S());
      }
      break;

@@ -200,10 +223,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r3);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetVReg(Node);
-        mov(Dst.D(), ARMEmitter::DReg::d0);
+        FillF64Result();
      }
      break;

@@ -222,21 +242,24 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r1);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetVReg(Node);
-        mov(Dst.D(), ARMEmitter::DReg::d0);
+        FillF64Result();
      }
      break;

      case FABI_F64_I16_F64_F64: {
-        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
-
        const auto Src1 = GetVReg(IROp->Args[0].ID());
        const auto Src2 = GetVReg(IROp->Args[1].ID());

-        mov(ARMEmitter::DReg::d0, Src1.D());
-        mov(ARMEmitter::DReg::d1, Src2.D());
+        mov(VTMP1.D(), Src1.D());
+        mov(VTMP2.D(), Src2.D());
+
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
+
+        if (!TMP_ABIARGS) {
+          mov(ARMEmitter::DReg::d0, VTMP1.D());
+          mov(ARMEmitter::DReg::d1, VTMP2.D());
+        }
+
        ldrh(ARMEmitter::WReg::w0, STATE, offsetof(FEXCore::Core::CPUState, FCW));
        ldr(ARMEmitter::XReg::x1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
        if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
@@ -246,10 +269,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r1);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetVReg(Node);
-        mov(Dst.D(), ARMEmitter::DReg::d0);
+        FillF64Result();
      }
      break;

@@ -270,10 +290,13 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r3);
        }

+        if (!TMP_ABIARGS) {
+          mov(TMP1, ARMEmitter::XReg::x0);
+        }
        FillForABICall(Info.SupportsPreserveAllABI, true);

        const auto Dst = GetReg(Node);
-        sxth(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0);
+        sxth(ARMEmitter::Size::i64Bit, Dst, TMP1);
      }
      break;
      case FABI_I32_I16_F80:{
@@ -293,10 +316,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r3);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetReg(Node);
-        mov(ARMEmitter::Size::i32Bit, Dst, ARMEmitter::Reg::r0);
+        FillI32Result();
      }
      break;
      case FABI_I64_I16_F80:{
@@ -315,10 +335,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
        else {
          blr(ARMEmitter::Reg::r3);
        }
+
+        if (!TMP_ABIARGS) {
+          mov(TMP1, ARMEmitter::XReg::x0);
+        }
        FillForABICall(Info.SupportsPreserveAllABI, true);

        const auto Dst = GetReg(Node);
-        mov(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0);
+        mov(ARMEmitter::Size::i64Bit, Dst, TMP1);
      }
      break;
      case FABI_I64_I16_F80_F80:{
@@ -341,10 +365,14 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
        else {
          blr(ARMEmitter::Reg::r5);
        }
+
+        if (!TMP_ABIARGS) {
+          mov(TMP1, ARMEmitter::XReg::x0);
+        }
        FillForABICall(Info.SupportsPreserveAllABI, true);

        const auto Dst = GetReg(Node);
-        mov(ARMEmitter::Size::i64Bit, Dst, ARMEmitter::Reg::r0);
+        mov(ARMEmitter::Size::i64Bit, Dst, TMP1);
      }
      break;
      case FABI_F80_I16_F80:{
@@ -364,12 +392,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r3);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetVReg(Node);
-        eor(Dst.Q(), Dst.Q(), Dst.Q());
-        ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, ARMEmitter::Reg::r0);
-        ins(ARMEmitter::SubRegSize::i16Bit, Dst, 4, ARMEmitter::Reg::r1);
+        FillF80Result();
      }
      break;
      case FABI_F80_I16_F80_F80:{
@@ -393,27 +416,28 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r5);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetVReg(Node);
-        eor(Dst.Q(), Dst.Q(), Dst.Q());
-        ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, ARMEmitter::Reg::r0);
-        ins(ARMEmitter::SubRegSize::i16Bit, Dst, 4, ARMEmitter::Reg::r1);
+        FillF80Result();
      }
      break;
      case FABI_I32_I64_I64_I128_I128_I16: {
-        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);
-
        const auto Op = IROp->C<IR::IROp_VPCMPESTRX>();
+        const auto SrcRAX = GetReg(Op->RAX.ID());
+        const auto SrcRDX = GetReg(Op->RDX.ID());
+
+        mov(TMP1, SrcRAX.X());
+        mov(TMP2, SrcRDX.X());
+
+        SpillForABICall(Info.SupportsPreserveAllABI, TMP3, true);
+
        const auto Control = Op->Control;

        const auto Src1 = GetVReg(Op->LHS.ID());
        const auto Src2 = GetVReg(Op->RHS.ID());
-        const auto SrcRAX = GetReg(Op->RAX.ID());
-        const auto SrcRDX = GetReg(Op->RDX.ID());

-        mov(ARMEmitter::XReg::x0, SrcRAX.X());
-        mov(ARMEmitter::XReg::x1, SrcRDX.X());
+        if (!TMP_ABIARGS) {
+          mov(ARMEmitter::XReg::x0, TMP1);
+          mov(ARMEmitter::XReg::x1, TMP2);
+        }

        umov<ARMEmitter::SubRegSize::i64Bit>(ARMEmitter::Reg::r2, Src1, 0);
        umov<ARMEmitter::SubRegSize::i64Bit>(ARMEmitter::Reg::r3, Src1, 1);
@@ -431,12 +455,9 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r7);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetReg(Node);
-        mov(Dst.W(), ARMEmitter::WReg::w0);
-        break;
+        FillI32Result();
      }
+      break;
      case FABI_I32_I128_I128_I16: {
        SpillForABICall(Info.SupportsPreserveAllABI, TMP1, true);

@@ -462,12 +483,9 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
          blr(ARMEmitter::Reg::r5);
        }

-        FillForABICall(Info.SupportsPreserveAllABI, true);
-
-        const auto Dst = GetReg(Node);
-        mov(Dst.W(), ARMEmitter::WReg::w0);
-        break;
+        FillI32Result();
      }
+      break;
      case FABI_UNKNOWN:
      default:
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
@@ -480,9 +498,26 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
 }


-static uint64_t Arm64JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, uint64_t *record) {
+static void DirectBlockDelinker(FEXCore::Core::CpuStateFrame *Frame, FEXCore::Context::ExitFunctionLinkData *Record) {
+  auto LinkerAddress = Frame->Pointers.Common.ExitFunctionLinker;
+  uintptr_t branch = (uintptr_t)(Record) - 8;
+  FEXCore::ARMEmitter::Emitter emit((uint8_t*)(branch), 8);
+  FEXCore::ARMEmitter::SingleUseForwardLabel l_BranchHost;
+  emit.ldr(TMP1, &l_BranchHost);
+  emit.blr(TMP1);
+  emit.Bind(&l_BranchHost);
+  emit.dc64(LinkerAddress);
+  FEXCore::ARMEmitter::Emitter::ClearICache((void*)branch, 8);
+}
+
+static void IndirectBlockDelinker(FEXCore::Core::CpuStateFrame *Frame, FEXCore::Context::ExitFunctionLinkData *Record) {
+  auto LinkerAddress = Frame->Pointers.Common.ExitFunctionLinker;
+  Record->HostBranch = LinkerAddress;
+}
+
+static uint64_t Arm64JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, FEXCore::Context::ExitFunctionLinkData *Record) {
  auto Thread = Frame->Thread;
-  auto GuestRip = record[1];
+  auto GuestRip = Record->GuestRIP;

  auto HostCode = Thread->LookupCache->FindBlock(GuestRip);

@@ -491,35 +526,24 @@ static uint64_t Arm64JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Fram
    return Frame->Pointers.Common.DispatcherLoopTop;
  }

-  uintptr_t branch = (uintptr_t)(record) - 8;
-  auto LinkerAddress = Frame->Pointers.Common.ExitFunctionLinker;
+  uintptr_t branch = (uintptr_t)(Record) - 8;

  auto offset = HostCode/4 - branch/4;
  if (vixl::IsInt26(offset)) {
    // optimal case - can branch directly
    // patch the code
-    FEXCore::ARMEmitter::Emitter emit((uint8_t*)(branch), 24);
+    FEXCore::ARMEmitter::Emitter emit((uint8_t*)(branch), 4);
    emit.b(offset);
-    FEXCore::ARMEmitter::Emitter::ClearICache((void*)branch, 24);
+    FEXCore::ARMEmitter::Emitter::ClearICache((void*)branch, 4);

    // Add de-linking handler
-    Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [branch, LinkerAddress]{
-      FEXCore::ARMEmitter::Emitter emit((uint8_t*)(branch), 24);
-      FEXCore::ARMEmitter::ForwardLabel l_BranchHost;
-      emit.ldr(FEXCore::ARMEmitter::XReg::x0, &l_BranchHost);
-      emit.blr(FEXCore::ARMEmitter::Reg::r0);
-      emit.Bind(&l_BranchHost);
-      emit.dc64(LinkerAddress);
-      FEXCore::ARMEmitter::Emitter::ClearICache((void*)branch, 24);
-    });
+    Thread->LookupCache->AddBlockLink(GuestRip, Record, DirectBlockDelinker);
  } else {
    // fallback case - do a soft-er link by patching the pointer
-    record[0] = HostCode;
+    Record->HostBranch = HostCode;

    // Add de-linking handler
-    Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [record, LinkerAddress]{
-      record[0] = LinkerAddress;
-    });
+    Thread->LookupCache->AddBlockLink(GuestRip, Record, IndirectBlockDelinker);
  }

  return HostCode;
@@ -574,8 +598,11 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::In
      Common.XCRFunction = PMF.GetConvertedPointer();
    }

-    Common.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
-    Common.SyscallHandlerFunc = reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall);
+    {
+      FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::HLE::SyscallHandler::HandleSyscall);
+      Common.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
+      Common.SyscallHandlerFunc = PMF.GetVTableEntry(CTX->SyscallHandler);
+    }
    Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadExitFunctionLink<Arm64JITCore_ExitFunctionLink>);

    // Fill in the fallback handlers
@@ -594,15 +621,6 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::In
  ClearCache();

  // Setup dynamic dispatch.
-  if (CTX->Dispatcher->GetConfig().StaticRegisterAllocation) {
-    RT_LoadRegister = &Arm64JITCore::Op_LoadRegisterSRA;
-    RT_StoreRegister = &Arm64JITCore::Op_StoreRegisterSRA;
-  }
-  else {
-    RT_LoadRegister = &Arm64JITCore::Op_LoadRegister;
-    RT_StoreRegister = &Arm64JITCore::Op_StoreRegister;
-  }
-
  if (ParanoidTSO()) {
    RT_LoadMemTSO = &Arm64JITCore::Op_ParanoidLoadMemTSO;
    RT_StoreMemTSO = &Arm64JITCore::Op_ParanoidStoreMemTSO;
@@ -762,8 +780,8 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
    if (vixl::aarch64::Assembler::IsImmAddSub(TotalSpillSlotsSize)) {
      sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, TotalSpillSlotsSize);
    } else {
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, TotalSpillSlotsSize);
-      sub(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::rsp, ARMEmitter::XReg::rsp, ARMEmitter::XReg::x0, ARMEmitter::ExtendedType::LSL_64, 0);
+      LoadConstant(ARMEmitter::Size::i64Bit, TMP1, TotalSpillSlotsSize);
+      sub(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::rsp, ARMEmitter::XReg::rsp, TMP1, ARMEmitter::ExtendedType::LSL_64, 0);
    }
  }

@@ -840,6 +858,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
  // TODO: This needs to be a data RIP relocation once code caching works.
  //   Current relocation code doesn't support this feature yet.
  JITBlockTail->RIP = Entry;
+  JITBlockTail->SpinLockFutex = 0;

  {
    // Store the RIP entries.
@@ -881,7 +900,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
    LogMan::Msg::IFmt("Disassemble Begin");
    for (auto PCToDecode = DisasmBegin; PCToDecode < DisasmEnd; PCToDecode += 4) {
      DisasmDecoder->Decode(PCToDecode);
-      auto Output = Disasm.GetOutput();
+      auto Output = Disasm->GetOutput();
      LogMan::Msg::IFmt("{}", Output);
    }
    LogMan::Msg::IFmt("Disassemble End");
@@ -909,8 +928,8 @@ void Arm64JITCore::ResetStack() {
    add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, TotalSpillSlotsSize);
  } else {
    // Too big to fit in a 12bit immediate
-    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, TotalSpillSlotsSize);
-    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::rsp, ARMEmitter::XReg::rsp, ARMEmitter::XReg::x0, ARMEmitter::ExtendedType::LSL_64, 0);
+    LoadConstant(ARMEmitter::Size::i64Bit, TMP1, TotalSpillSlotsSize);
+    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::rsp, ARMEmitter::XReg::rsp, TMP1, ARMEmitter::ExtendedType::LSL_64, 0);
  }
 }

@@ -920,7 +939,6 @@ fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl *

 CPUBackendFeatures GetArm64JITBackendFeatures() {
  return CPUBackendFeatures {
-    .SupportsStaticRegisterAllocation = true,
    .SupportsFlags = true,
    .SupportsSaturatingRoundingShifts = true,
    .SupportsVTBL2 = true,
@@ -9,16 +9,17 @@ $end_info$

 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
 #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
+#include "Interface/Core/CPUBackend.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/IR/IR.h"
+#include "Interface/IR/IntrusiveIRList.h"
+#include "Interface/IR/RegisterAllocationData.h"

 #include <aarch64/assembler-aarch64.h>
 #include <aarch64/disasm-aarch64.h>

 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/fextl/map.h>
 #include <FEXCore/fextl/string.h>
 #include <FEXCore/fextl/vector.h>
@@ -56,6 +57,8 @@ public:

 private:
  FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
+  FEX_CONFIG_OPT(VectorTSOEnabled, VECTORTSOENABLED);
+  FEX_CONFIG_OPT(MemcpySetTSOEnabled, MEMCPYSETTSOENABLED);

  const bool HostSupportsSVE128{};
  const bool HostSupportsSVE256{};
@@ -116,6 +119,16 @@ private:
    return PhyReg;
  }

+  [[nodiscard]] FEXCore::ARMEmitter::Register GetZeroableReg(IR::OrderedNodeWrapper Src) const {
+    uint64_t Const;
+    if (IsInlineConstant(Src, &Const)) {
+      LOGMAN_THROW_AA_FMT(Const == 0, "Only valid constant");
+      return ARMEmitter::Reg::zr;
+    } else {
+      return GetReg(Src.ID());
+    }
+  }
+
  // Converts IR-base shift type to ARMEmitter shift type.
  // Will be a no-op, only a type conversion since the two definitions match.
  [[nodiscard]] ARMEmitter::ShiftType ConvertIRShiftType(IR::ShiftType Shift) const {
@@ -226,9 +239,6 @@ private:
  void VFScalarUnaryOperation(uint8_t OpSize, uint8_t ElementSize, bool ZeroUpperBits, ScalarUnaryOpCaller ScalarEmit, ARMEmitter::VRegister Dst, ARMEmitter::VRegister Vector1, std::variant<ARMEmitter::VRegister, ARMEmitter::Register> Vector2);

  // Runtime selection;
-  // Load and store register style.
-  OpType RT_LoadRegister;
-  OpType RT_StoreRegister;
  // Load and store TSO memory style
  OpType RT_LoadMemTSO;
  OpType RT_StoreMemTSO;
@@ -236,9 +246,6 @@ private:
 #define DEF_OP(x) void Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)

  // Dynamic Dispatcher supporting operations
-  DEF_OP(LoadRegisterSRA);
-  DEF_OP(StoreRegisterSRA);
-
  DEF_OP(ParanoidLoadMemTSO);
  DEF_OP(ParanoidStoreMemTSO);

@@ -131,170 +131,6 @@ DEF_OP(LoadRegister) {
  const auto Op = IROp->C<IR::IROp_LoadRegister>();
  const auto OpSize = IROp->Size;

-  if (Op->Class == IR::GPRClass) {
-    [[maybe_unused]] const auto regId = (Op->Offset / Core::CPUState::GPR_REG_SIZE) - 1;
-    const auto regOffs = Op->Offset & 7;
-
-    LOGMAN_THROW_A_FMT(regId < StaticRegisters.size(), "out of range regId");
-
-    switch (OpSize) {
-      case 1:
-        LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
-        ldrb(GetReg(Node), STATE, Op->Offset);
-        break;
-
-      case 2:
-        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
-        ldrh(GetReg(Node), STATE, Op->Offset);
-        break;
-
-      case 4:
-        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
-        ldr(GetReg(Node).W(), STATE, Op->Offset);
-        break;
-
-      case 8:
-        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
-        ldr(GetReg(Node).X(), STATE, Op->Offset);
-        break;
-
-      default:
-        LOGMAN_MSG_A_FMT("Unhandled LoadRegister GPR size: {}", OpSize);
-        break;
-    }
-  }
-  else if (Op->Class == IR::FPRClass) {
-    const auto regSize = HostSupportsSVE256 ? Core::CPUState::XMM_AVX_REG_SIZE
-                                            : Core::CPUState::XMM_SSE_REG_SIZE;
-    [[maybe_unused]] const auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.xmm.avx.data[0][0])) / regSize;
-
-    LOGMAN_THROW_A_FMT(HostSupportsSVE256, "Unsupported code path!");
-    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "out of range regId");
-
-    const auto host = GetVReg(Node);
-
-    const auto regOffs = Op->Offset & 15;
-
-    switch (OpSize) {
-      case 1: {
-        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs: {}", regOffs);
-        ldrb(host, STATE, Op->Offset);
-        break;
-      }
-      case 2: {
-        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs: {}", regOffs);
-        ldrh(host, STATE, Op->Offset);
-        break;
-      }
-      case 4: {
-        LOGMAN_THROW_AA_FMT((regOffs & 3) == 0, "unexpected regOffs: {}", regOffs);
-        ldr(host.S(), STATE, Op->Offset);
-        break;
-      }
-
-      case 8: {
-        LOGMAN_THROW_AA_FMT((regOffs & 7) == 0, "unexpected regOffs: {}", regOffs);
-        ldr(host.D(), STATE, Op->Offset);
-        break;
-      }
-
-      case 16: {
-        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs: {}", regOffs);
-        ldr(host.Q(), STATE, Op->Offset);
-        break;
-      }
-    }
-  } else {
-    LOGMAN_THROW_AA_FMT(false, "Unhandled Op->Class {}", Op->Class);
-  }
-}
-
-DEF_OP(StoreRegister) {
-  const auto Op = IROp->C<IR::IROp_StoreRegister>();
-  const auto OpSize = IROp->Size;
-
-  if (Op->Class == IR::GPRClass) {
-    [[maybe_unused]] const auto regId = (Op->Offset / Core::CPUState::GPR_REG_SIZE) - 1;
-    const auto regOffs = Op->Offset & 7;
-
-    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "out of range regId");
-
-    const auto Src = GetReg(Op->Value.ID());
-
-    switch (OpSize) {
-      case 1:
-        LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
-        strb(Src, STATE, Op->Offset);
-        break;
-
-      case 2:
-        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
-        strh(Src, STATE, Op->Offset);
-        break;
-
-      case 4:
-        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
-        str(Src.W(), STATE, Op->Offset);
-        break;
-      case 8:
-        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
-        str(Src.X(), STATE, Op->Offset);
-        break;
-
-      default:
-        LOGMAN_MSG_A_FMT("Unhandled StoreRegister GPR size: {}", OpSize);
-        break;
-    }
-  } else if (Op->Class == IR::FPRClass) {
-    const auto regSize = HostSupportsSVE256 ? Core::CPUState::XMM_AVX_REG_SIZE
-                                            : Core::CPUState::XMM_SSE_REG_SIZE;
-    [[maybe_unused]] const auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.xmm.avx.data[0][0])) / regSize;
-
-    LOGMAN_THROW_A_FMT(HostSupportsSVE256, "Unsupported code path!");
-    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "regId out of range");
-
-    const auto host = GetVReg(Op->Value.ID());
-
-    const auto regOffs = Op->Offset & 15;
-
-    switch (OpSize) {
-      case 1:
-        strb(host, STATE, Op->Offset);
-        break;
-
-      case 2:
-        LOGMAN_THROW_AA_FMT((regOffs & 1) == 0, "unexpected regOffs: {}", regOffs);
-        strh(host, STATE, Op->Offset);
-        break;
-
-      case 4:
-        LOGMAN_THROW_AA_FMT((regOffs & 3) == 0, "unexpected regOffs: {}", regOffs);
-        str(host.S(), STATE, Op->Offset);
-        break;
-
-      case 8:
-        LOGMAN_THROW_AA_FMT((regOffs & 7) == 0, "unexpected regOffs: {}", regOffs);
-        str(host.D(), STATE, Op->Offset);
-        break;
-
-      case 16:
-        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs: {}", regOffs);
-        str(host.Q(), STATE, Op->Offset);
-        break;
-
-      default:
-        LOGMAN_MSG_A_FMT("Unhandled StoreRegister FPR size: {}", OpSize);
-        break;
-    }
-  } else {
-    LOGMAN_THROW_AA_FMT(false, "Unhandled Op->Class {}", Op->Class);
-  }
-}
-
-DEF_OP(LoadRegisterSRA) {
-  const auto Op = IROp->C<IR::IROp_LoadRegister>();
-  const auto OpSize = IROp->Size;
-
  if (Op->Class == IR::GPRClass) {
    const auto regId =
      Op->Offset == offsetof(Core::CpuStateFrame, State.pf_raw) ? (StaticRegisters.size() - 2) :
@@ -339,7 +175,7 @@ DEF_OP(LoadRegisterSRA) {
    if (HostSupportsSVE256) {
      const auto regOffs = Op->Offset & 31;

-      ARMEmitter::ForwardLabel DataLocation;
+      ARMEmitter::SingleUseForwardLabel DataLocation;
      const auto LoadPredicate = [this, &DataLocation] {
        const auto Predicate = ARMEmitter::PReg::p0;
        adr(TMP1, &DataLocation);
@@ -348,7 +184,7 @@ DEF_OP(LoadRegisterSRA) {
      };

      const auto EmitData = [this, &DataLocation](uint32_t Value) {
-        ARMEmitter::ForwardLabel PastConstant;
+        ARMEmitter::SingleUseForwardLabel PastConstant;
        b(&PastConstant);
        Bind(&DataLocation);
        dc32(Value);
@@ -473,7 +309,7 @@ DEF_OP(LoadRegisterSRA) {
  }
 }

-DEF_OP(StoreRegisterSRA) {
+DEF_OP(StoreRegister) {
  const auto Op = IROp->C<IR::IROp_StoreRegister>();
  const auto OpSize = IROp->Size;

@@ -528,7 +364,7 @@ DEF_OP(StoreRegisterSRA) {
      const auto regOffs = Op->Offset & 31;

      // Compartmentalized setting up of the predicate for the cases that need it.
-      ARMEmitter::ForwardLabel DataLocation;
+      ARMEmitter::SingleUseForwardLabel DataLocation;
      const auto LoadPredicate = [this, &DataLocation] {
        const auto Predicate = ARMEmitter::PReg::p0;
        adr(TMP1, &DataLocation);
@@ -541,7 +377,7 @@ DEF_OP(StoreRegisterSRA) {
      // It's helpful to treat LoadPredicate and EmitData as a prologue and epilogue
      // respectfully.
      const auto EmitData = [this, &DataLocation](uint32_t Data) {
-        ARMEmitter::ForwardLabel PastConstant;
+        ARMEmitter::SingleUseForwardLabel PastConstant;
        b(&PastConstant);
        Bind(&DataLocation);
        dc32(Data);
@@ -1052,6 +888,14 @@ DEF_OP(StoreNZCV) {
  msr(ARMEmitter::SystemRegister::NZCV, GetReg(Op->Value.ID()));
 }

+DEF_OP(LoadDF) {
+  auto Dst = GetReg(Node);
+  auto Flag = X86State::RFLAG_DF_RAW_LOC;
+
+  // DF needs sign extension to turn 0x1/0xFF into 1/-1
+  ldrsb(Dst.X(), STATE, offsetof(FEXCore::Core::CPUState, flags[Flag]));
+}
+
 DEF_OP(LoadFlag) {
  auto Op = IROp->C<IR::IROp_LoadFlag>();
  auto Dst = GetReg(Node);
@@ -1330,8 +1174,10 @@ DEF_OP(LoadMemTSO) {
        LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", OpSize);
        break;
    }
-    // Half-barrier.
-    dmb(FEXCore::ARMEmitter::BarrierScope::ISHLD);
+    if (VectorTSOEnabled()) {
+      // Half-barrier.
+      dmb(FEXCore::ARMEmitter::BarrierScope::ISHLD);
+    }
  }
 }

@@ -1479,7 +1325,7 @@ DEF_OP(VLoadVectorElement) {
  }

  // Emit a half-barrier if TSO is enabled.
-  if (CTX->IsAtomicTSOEnabled()) {
+  if (CTX->IsAtomicTSOEnabled() && VectorTSOEnabled()) {
    dmb(ARMEmitter::BarrierScope::ISHLD);
  }
 }
@@ -1499,7 +1345,7 @@ DEF_OP(VStoreVectorElement) {
                      ElementSize == 16, "Invalid element size");

  // Emit a half-barrier if TSO is enabled.
-  if (CTX->IsAtomicTSOEnabled()) {
+  if (CTX->IsAtomicTSOEnabled() && VectorTSOEnabled()) {
    dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
  }

@@ -1599,7 +1445,7 @@ DEF_OP(VBroadcastFromMem) {
  }

  // Emit a half-barrier if TSO is enabled.
-  if (CTX->IsAtomicTSOEnabled()) {
+  if (CTX->IsAtomicTSOEnabled() && VectorTSOEnabled()) {
    dmb(ARMEmitter::BarrierScope::ISHLD);
  }
 }
@@ -1817,8 +1663,10 @@ DEF_OP(StoreMemTSO) {
    }
  }
  else {
-    // Half-Barrier.
-    dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
+    if (VectorTSOEnabled()) {
+      // Half-Barrier.
+      dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
+    }
    const auto Src = GetVReg(Op->Value.ID());
    const auto MemSrc = GenerateMemOperand(OpSize, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
    switch (OpSize) {
@@ -1859,6 +1707,7 @@ DEF_OP(MemSet) {
  // that the value is zero, we can optimize any operation larger than 8-bit down to 8-bit to use the MOPS implementation.
  const auto Op = IROp->C<IR::IROp_MemSet>();

+  const bool IsAtomic = Op->IsAtomic && MemcpySetTSOEnabled();
  const int32_t Size = Op->Size;
  const auto MemReg = GetReg(Op->Addr.ID());
  const auto Value = GetReg(Op->Value.ID());
@@ -1872,15 +1721,15 @@ DEF_OP(MemSet) {
    DirectionReg = GetReg(Op->Direction.ID());
  }

-  // If Direction == 0 then:
+  // If Direction > 0 then:
  //   MemReg is incremented (by size)
  // else:
  //   MemReg is decremented (by size)
  //
  // Counter is decremented regardless.

-  ARMEmitter::ForwardLabel BackwardImpl{};
-  ARMEmitter::ForwardLabel Done{};
+  ARMEmitter::SingleUseForwardLabel BackwardImpl{};
+  ARMEmitter::SingleUseForwardLabel Done{};

  mov(TMP1, Length.X());
  if (Op->Prefix.IsInvalid()) {
@@ -1893,7 +1742,7 @@ DEF_OP(MemSet) {

  if (!DirectionIsInline) {
    // Backward or forwards implementation depends on flag
-    cbnz(ARMEmitter::Size::i64Bit, DirectionReg, &BackwardImpl);
+    tbnz(DirectionReg, 1, &BackwardImpl);
  }

  auto MemStore = [this](auto Value, uint32_t OpSize, int32_t Size) {
@@ -1948,18 +1797,73 @@ DEF_OP(MemSet) {
    }
  };

+  const auto SubRegSize =
+    Size == 1 ? ARMEmitter::SubRegSize::i8Bit :
+    Size == 2 ? ARMEmitter::SubRegSize::i16Bit :
+    Size == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    Size == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i8Bit;
+
  auto EmitMemset = [&](int32_t Direction) {
    const int32_t OpSize = Size;
    const int32_t SizeDirection = Size * Direction;

-    ARMEmitter::BackwardLabel AgainInternal{};
+    ARMEmitter::BiDirectionalLabel AgainInternal{};
    ARMEmitter::ForwardLabel DoneInternal{};

    // Early exit if zero count.
    cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);

+    if (!IsAtomic) {
+      ARMEmitter::ForwardLabel AgainInternal256Exit{};
+      ARMEmitter::BackwardLabel AgainInternal256{};
+      ARMEmitter::ForwardLabel AgainInternal128Exit{};
+      ARMEmitter::BackwardLabel AgainInternal128{};
+
+      if (Direction == -1) {
+        sub(ARMEmitter::Size::i64Bit, TMP2, TMP2, 32 - Size);
+      }
+
+      // Keep the counter one copy ahead, so that underflow can be used to detect when to fallback
+      // to the copy unit size copy loop for the last chunk.
+      // Do this in two parts, to fallback to the byte by byte loop if size < 32, and to the
+      // single copy loop if size < 64.
+      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
+      tbnz(TMP1, 63, &AgainInternal128Exit);
+
+      // Fill VTMP2 with the set pattern
+      dup(SubRegSize, VTMP2.Q(), Value);
+
+      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
+      tbnz(TMP1, 63, &AgainInternal256Exit);
+
+      Bind(&AgainInternal256);
+      stp<ARMEmitter::IndexType::POST>(VTMP2.Q(), VTMP2.Q(), TMP2, 32 * Direction);
+      stp<ARMEmitter::IndexType::POST>(VTMP2.Q(), VTMP2.Q(), TMP2, 32 * Direction);
+      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size);
+      tbz(TMP1, 63, &AgainInternal256);
+
+      Bind(&AgainInternal256Exit);
+      add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size);
+      cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+
+      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
+      tbnz(TMP1, 63, &AgainInternal128Exit);
+      Bind(&AgainInternal128);
+      stp<ARMEmitter::IndexType::POST>(VTMP2.Q(), VTMP2.Q(), TMP2, 32 * Direction);
+      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
+      tbz(TMP1, 63, &AgainInternal128);
+
+      Bind(&AgainInternal128Exit);
+      add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
+      cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+
+      if (Direction == -1) {
+        add(ARMEmitter::Size::i64Bit, TMP2, TMP2, 32 - Size);
+      }
+    }
+
    Bind(&AgainInternal);
-    if (Op->IsAtomic) {
+    if (IsAtomic) {
      MemStoreTSO(Value, OpSize, SizeDirection);
    }
    else {
@@ -2011,8 +1915,8 @@ DEF_OP(MemSet) {
  };

  if (DirectionIsInline) {
-    // If the direction constant is set then the direction is negative.
-    EmitMemset(DirectionConstant ? -1 : 1);
+    LOGMAN_THROW_AA_FMT(DirectionConstant == 1 || DirectionConstant == -1, "unexpected direction");
+    EmitMemset(DirectionConstant);
  }
  else {
    // Emit forward direction memset then backward direction memset.
@@ -2037,6 +1941,7 @@ DEF_OP(MemCpy) {
  // Assuming non-atomicity and non-faulting behaviour, this can accelerate this implementation.
  const auto Op = IROp->C<IR::IROp_MemCpy>();

+  const bool IsAtomic = Op->IsAtomic && MemcpySetTSOEnabled();
  const int32_t Size = Op->Size;
  const auto MemRegDest = GetReg(Op->AddrDest.ID());
  const auto MemRegSrc = GetReg(Op->AddrSrc.ID());
@@ -2050,7 +1955,7 @@ DEF_OP(MemCpy) {
  }

  auto Dst = GetRegPair(Node);
-  // If Direction == 0 then:
+  // If Direction > 0 then:
  //   MemRegDest is incremented (by size)
  //   MemRegSrc is incremented (by size)
  // else:
@@ -2059,8 +1964,8 @@ DEF_OP(MemCpy) {
  //
  // Counter is decremented regardless.

-  ARMEmitter::ForwardLabel BackwardImpl{};
-  ARMEmitter::ForwardLabel Done{};
+  ARMEmitter::SingleUseForwardLabel BackwardImpl{};
+  ARMEmitter::SingleUseForwardLabel Done{};

  mov(TMP1, Length.X());
  if (Op->PrefixDest.IsInvalid()) {
@@ -2086,7 +1991,7 @@ DEF_OP(MemCpy) {

  if (!DirectionIsInline) {
    // Backward or forwards implementation depends on flag
-    cbnz(ARMEmitter::Size::i64Bit, DirectionReg, &BackwardImpl);
+    tbnz(DirectionReg, 1, &BackwardImpl);
  }

  auto MemCpy = [this](uint32_t OpSize, int32_t Size) {
@@ -2107,6 +2012,10 @@ DEF_OP(MemCpy) {
        ldr<ARMEmitter::IndexType::POST>(TMP4, TMP3, Size);
        str<ARMEmitter::IndexType::POST>(TMP4, TMP2, Size);
        break;
+      case 32:
+        ldp<ARMEmitter::IndexType::POST>(VTMP1.Q(), VTMP2.Q(), TMP3, Size);
+        stp<ARMEmitter::IndexType::POST>(VTMP1.Q(), VTMP2.Q(), TMP2, Size);
+        break;
      default:
        LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
        break;
@@ -2213,14 +2122,69 @@ DEF_OP(MemCpy) {
    const int32_t OpSize = Size;
    const int32_t SizeDirection = Size * Direction;

-    ARMEmitter::BackwardLabel AgainInternal{};
+    ARMEmitter::BiDirectionalLabel AgainInternal{};
    ARMEmitter::ForwardLabel DoneInternal{};

    // Early exit if zero count.
    cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);

+    if (!IsAtomic) {
+      ARMEmitter::ForwardLabel AbsPos{};
+      ARMEmitter::ForwardLabel AgainInternal256Exit{};
+      ARMEmitter::ForwardLabel AgainInternal128Exit{};
+      ARMEmitter::BackwardLabel AgainInternal128{};
+      ARMEmitter::BackwardLabel AgainInternal256{};
+
+      sub(ARMEmitter::Size::i64Bit, TMP4, TMP2, TMP3);
+      tbz(TMP4, 63, &AbsPos);
+      neg(ARMEmitter::Size::i64Bit, TMP4, TMP4);
+      Bind(&AbsPos);
+      sub(ARMEmitter::Size::i64Bit, TMP4, TMP4, 32);
+      tbnz(TMP4, 63, &AgainInternal);
+
+      if (Direction == -1) {
+        sub(ARMEmitter::Size::i64Bit, TMP2, TMP2, 32 - Size);
+        sub(ARMEmitter::Size::i64Bit, TMP3, TMP3, 32 - Size);
+      }
+
+      // Keep the counter one copy ahead, so that underflow can be used to detect when to fallback
+      // to the copy unit size copy loop for the last chunk.
+      // Do this in two parts, to fallback to the byte by byte loop if size < 32, and to the
+      // single copy loop if size < 64.
+      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
+      tbnz(TMP1, 63, &AgainInternal128Exit);
+      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
+      tbnz(TMP1, 63, &AgainInternal256Exit);
+
+      Bind(&AgainInternal256);
+      MemCpy(32, 32 * Direction);
+      MemCpy(32, 32 * Direction);
+      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size);
+      tbz(TMP1, 63, &AgainInternal256);
+
+      Bind(&AgainInternal256Exit);
+      add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 64 / Size);
+      cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+
+      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
+      tbnz(TMP1, 63, &AgainInternal128Exit);
+      Bind(&AgainInternal128);
+      MemCpy(32, 32 * Direction);
+      sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
+      tbz(TMP1, 63, &AgainInternal128);
+
+      Bind(&AgainInternal128Exit);
+      add(ARMEmitter::Size::i64Bit, TMP1, TMP1, 32 / Size);
+      cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+
+      if (Direction == -1) {
+        add(ARMEmitter::Size::i64Bit, TMP2, TMP2, 32 - Size);
+        add(ARMEmitter::Size::i64Bit, TMP3, TMP3, 32 - Size);
+      }
+    }
+
    Bind(&AgainInternal);
-    if (Op->IsAtomic) {
+    if (IsAtomic) {
      MemCpyTSO(OpSize, SizeDirection);
    }
    else {
@@ -2285,8 +2249,8 @@ DEF_OP(MemCpy) {
  };

  if (DirectionIsInline) {
-    // If the direction constant is set then the direction is negative.
-    EmitMemcpy(DirectionConstant ? -1 : 1);
+    LOGMAN_THROW_AA_FMT(DirectionConstant == 1 || DirectionConstant == -1, "unexpected direction");
+    EmitMemcpy(DirectionConstant);
  }
  else {
    // Emit forward direction memset then backward direction memset.
@@ -2583,6 +2547,47 @@ DEF_OP(CacheLineZero) {
  }
 }

+DEF_OP(Prefetch) {
+  auto Op = IROp->C<IR::IROp_Prefetch>();
+  const auto MemReg = GetReg(Op->Addr.ID());
+
+  // Access size is only ever handled as 8-byte. Even though it is accesssed as a cacheline.
+  const auto MemSrc = GenerateMemOperand(8, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
+
+  size_t LUT =
+    (Op->Stream ? 1 : 0) |
+    ((Op->CacheLevel - 1) << 1) |
+    (Op->ForStore ? 1U << 3 : 0);
+
+  constexpr static std::array<ARMEmitter::Prefetch, 14> PrefetchType = {
+    ARMEmitter::Prefetch::PLDL1KEEP,
+    ARMEmitter::Prefetch::PLDL1STRM,
+
+    ARMEmitter::Prefetch::PLDL2KEEP,
+    ARMEmitter::Prefetch::PLDL2STRM,
+
+    ARMEmitter::Prefetch::PLDL3KEEP,
+    ARMEmitter::Prefetch::PLDL3STRM,
+
+    // Gap of two.
+    // 0b0'11'0
+    ARMEmitter::Prefetch::PLDL1STRM,
+    // 0b0'11'1
+    ARMEmitter::Prefetch::PLDL1STRM,
+
+    ARMEmitter::Prefetch::PSTL1KEEP,
+    ARMEmitter::Prefetch::PSTL1STRM,
+
+    ARMEmitter::Prefetch::PSTL2KEEP,
+    ARMEmitter::Prefetch::PSTL2STRM,
+
+    ARMEmitter::Prefetch::PSTL3KEEP,
+    ARMEmitter::Prefetch::PSTL3STRM,
+  };
+
+  prfm(PrefetchType[LUT], MemSrc);
+}
+
 #undef DEF_OP
 }

@@ -1372,6 +1372,32 @@ DEF_OP(VUMinV) {
  }
 }

+DEF_OP(VUMaxV) {
+  const auto Op = IROp->C<IR::IROp_VUMaxV>();
+  const auto OpSize = IROp->Size;
+
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto ElementSize = Op->Header.ElementSize;
+
+  const auto Dst = GetVReg(Node);
+  const auto Vector = GetVReg(Op->Vector.ID());
+
+  LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8, "Invalid size");
+  const auto SubRegSize =
+    ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i8Bit;
+
+  if (HostSupportsSVE256 && Is256Bit) {
+    const auto Pred = PRED_TMP_32B;
+    umaxv(SubRegSize, Dst, Pred, Vector.Z());
+  } else {
+    // Vector
+    umaxv(SubRegSize, Dst.Q(), Vector.Q());
+  }
+}
+
 DEF_OP(VURAvg) {
  const auto Op = IROp->C<IR::IROp_VURAvg>();
  const auto OpSize = IROp->Size;
@@ -5009,42 +5035,50 @@ DEF_OP(VTBX1) {
  if (Dst != VectorSrcDst) {
    switch (OpSize) {
      case 8: {
-        mov(Dst.D(), VectorSrcDst.D());
+        mov(VTMP1.D(), VectorSrcDst.D());
+        tbx(VTMP1.D(), VectorTable.Q(), VectorIndices.D());
+        mov(Dst.D(), VTMP1.D());
        break;
      }
      case 16: {
-        mov(Dst.Q(), VectorSrcDst.Q());
+        mov(VTMP1.Q(), VectorSrcDst.Q());
+        tbx(VTMP1.Q(), VectorTable.Q(), VectorIndices.Q());
+        mov(Dst.Q(), VTMP1.Q());
        break;
      }
      case 32: {
-        mov(Dst.Z(), VectorSrcDst.Z());
+        LOGMAN_THROW_AA_FMT(HostSupportsSVE256,
+                            "Host does not support SVE. Cannot perform 256-bit table lookup");
+        mov(VTMP1.Z(), VectorSrcDst.Z());
+        tbx(ARMEmitter::SubRegSize::i8Bit, VTMP1.Z(), VectorTable.Z(), VectorIndices.Z());
+        mov(Dst.Z(), VTMP1.Z());
        break;
      }
      default:
        LOGMAN_MSG_A_FMT("Unknown OpSize: {}", OpSize);
        break;
    }
-  }
+  } else {
+    switch (OpSize) {
+      case 8: {
+        tbx(VectorSrcDst.D(), VectorTable.Q(), VectorIndices.D());
+        break;
+      }
+      case 16: {
+        tbx(VectorSrcDst.Q(), VectorTable.Q(), VectorIndices.Q());
+        break;
+      }
+      case 32: {
+        LOGMAN_THROW_AA_FMT(HostSupportsSVE256,
+                            "Host does not support SVE. Cannot perform 256-bit table lookup");

-  switch (OpSize) {
-    case 8: {
-      tbx(Dst.D(), VectorTable.Q(), VectorIndices.D());
-      break;
+        tbx(ARMEmitter::SubRegSize::i8Bit, VectorSrcDst.Z(), VectorTable.Z(), VectorIndices.Z());
+        break;
+      }
+      default:
+        LOGMAN_MSG_A_FMT("Unknown OpSize: {}", OpSize);
+        break;
    }
-    case 16: {
-      tbx(Dst.Q(), VectorTable.Q(), VectorIndices.Q());
-      break;
-    }
-    case 32: {
-      LOGMAN_THROW_AA_FMT(HostSupportsSVE256,
-                          "Host does not support SVE. Cannot perform 256-bit table lookup");
-
-      tbx(ARMEmitter::SubRegSize::i8Bit, Dst.Z(), VectorTable.Z(), VectorIndices.Z());
-      break;
-    }
-    default:
-      LOGMAN_MSG_A_FMT("Unknown OpSize: {}", OpSize);
-      break;
  }
 }

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: MIT
 #pragma once

-#include <FEXCore/Core/CPUBackend.h>
+#include "Interface/Core/CPUBackend.h"
 #include <FEXCore/fextl/memory.h>

 namespace FEXCore::Context {
@@ -15,10 +15,6 @@ struct InternalThreadState;
 namespace FEXCore::CPU {
 class CPUBackend;

-[[nodiscard]] fextl::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::ContextImpl *ctx,
-                                                           FEXCore::Core::InternalThreadState *Thread);
-CPUBackendFeatures GetX86JITBackendFeatures();
-
 [[nodiscard]] fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl *ctx,
                                                             FEXCore::Core::InternalThreadState *Thread);
 CPUBackendFeatures GetArm64JITBackendFeatures();
@@ -100,15 +100,15 @@ public:
    L1Entry.HostCode = (uintptr_t)HostCode;
  }

-  void Erase(uint64_t Address) {
+  void Erase(FEXCore::Core::CpuStateFrame *Frame, uint64_t Address) {

    std::lock_guard<std::recursive_mutex> lk(WriteLock);

    // Sever any links to this block
-    auto lower = BlockLinks->lower_bound({Address, 0});
-    auto upper = BlockLinks->upper_bound({Address, UINTPTR_MAX});
+    auto lower = BlockLinks->lower_bound({Address, nullptr});
+    auto upper = BlockLinks->upper_bound({Address, reinterpret_cast<FEXCore::Context::ExitFunctionLinkData *>(UINTPTR_MAX)});
    for (auto it = lower; it != upper; it = BlockLinks->erase(it)) {
-      it->second();
+      it->second(Frame, it->first.HostLink);
    }

    // Remove from BlockList
@@ -141,8 +141,7 @@ public:
    BlockPointers[PageOffset].HostCode = 0;
  }

-
-  void AddBlockLink(uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker) {
+  void AddBlockLink(uint64_t GuestDestination, FEXCore::Context::ExitFunctionLinkData * HostLink, const FEXCore::Context::BlockDelinkerFunc &delinker) {
    std::lock_guard<std::recursive_mutex> lk(WriteLock);

    BlockLinks->insert({{GuestDestination, HostLink}, delinker});
@@ -158,7 +157,7 @@ public:
  constexpr static size_t L1_ENTRIES = 1 * 1024 * 1024; // Must be a power of 2
  constexpr static size_t L1_ENTRIES_MASK = L1_ENTRIES - 1;

-  // This needs to be taken before reads or writes to L2, L3, CodePages, Thread::DebugStore,
+  // This needs to be taken before reads or writes to L2, L3, CodePages,
  // and before writes to L1. Concurrent access from a thread that this LookupCache doesn't belong to
  // may only happen during cross thread invalidation (::Erase).
  // All other operations must be done from the owning thread.
@@ -224,7 +223,7 @@ private:

  struct BlockLinkTag {
    uint64_t GuestDestination;
-    uintptr_t HostLink;
+    FEXCore::Context::ExitFunctionLinkData *HostLink;

    bool operator <(const BlockLinkTag& other) const {
      if (GuestDestination < other.GuestDestination)
@@ -243,7 +242,7 @@ private:
  //
  // This makes `BlockLinks` look like a raw pointer that could memory leak, but since it is backed by the MBR, it won't.
  std::pmr::monotonic_buffer_resource BlockLinks_mbr;
-  using BlockLinksMapType = std::pmr::map<BlockLinkTag, std::function<void()>>;
+  using BlockLinksMapType = std::pmr::map<BlockLinkTag, FEXCore::Context::BlockDelinkerFunc>;
  fextl::unique_ptr<std::pmr::polymorphic_allocator<std::byte>> BlockLinks_pma;
  BlockLinksMapType *BlockLinks;

@@ -32,9 +32,6 @@ namespace FEXCore::CodeSerialize {
    // ABI local flag unsafe optimization
    unsigned ABILocalFlags : 1;

-    // Static register allocation enabled
-    unsigned SRA : 1;
-
    // Paranoid TSO mode enabled
    unsigned ParanoidTSO : 1;

@@ -49,7 +46,7 @@ namespace FEXCore::CodeSerialize {

    // Padding to remove uninitialized data warning from asan
    // Shows remaining amount of bits available for config
-    unsigned _Pad : 18;
+    unsigned _Pad : 19;

    bool operator==(CodeObjectSerializationConfig const &other) const {
      return Cookie == other.Cookie &&
@@ -59,7 +56,6 @@ namespace FEXCore::CodeSerialize {
        HardwareTSOEnabled == other.HardwareTSOEnabled &&
        TSOEnabled == other.TSOEnabled &&
        ABILocalFlags == other.ABILocalFlags &&
-        SRA == other.SRA &&
        ParanoidTSO == other.ParanoidTSO &&
        Is64BitMode == other.Is64BitMode &&
        SMCChecks == other.SMCChecks &&
@@ -75,7 +71,6 @@ namespace FEXCore::CodeSerialize {
      Hash <<= 1;  Hash |= other.HardwareTSOEnabled;
      Hash <<= 1;  Hash |= other.TSOEnabled;
      Hash <<= 1;  Hash |= other.ABILocalFlags;
-      Hash <<= 1;  Hash |= other.SRA;
      Hash <<= 1;  Hash |= other.ParanoidTSO;
      Hash <<= 1;  Hash |= other.Is64BitMode;
      Hash <<= 2;  Hash |= other.SMCChecks;
@@ -18,7 +18,6 @@ namespace FEXCore::CodeSerialize {
    DefaultSerializationConfig.MultiBlock = ctx->Config.Multiblock;
    DefaultSerializationConfig.TSOEnabled = ctx->Config.TSOEnabled;
    DefaultSerializationConfig.ABILocalFlags = ctx->Config.ABILocalFlags;
-    DefaultSerializationConfig.SRA = ctx->Config.StaticRegisterAllocation;
    DefaultSerializationConfig.ParanoidTSO = ctx->Config.ParanoidTSO;
    DefaultSerializationConfig.Is64BitMode = ctx->Config.Is64BitMode;
    DefaultSerializationConfig.SMCChecks = ctx->Config.SMCChecks;
@@ -4,13 +4,12 @@
 #include "Interface/Core/Frontend.h"
 #include "Interface/Core/X86Tables/X86Tables.h"
 #include "Interface/Context/Context.h"
+#include "Interface/IR/IREmitter.h"

 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>

 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>
@@ -78,10 +77,7 @@ friend class FEXCore::IR::PassManager;
 public:
  enum class FlagsGenerationType : uint8_t {
    TYPE_NONE,
-    TYPE_ADC,
-    TYPE_SBB,
    TYPE_SUB,
-    TYPE_ADD,
    TYPE_MUL,
    TYPE_UMUL,
    TYPE_LOGICAL,
@@ -92,18 +88,13 @@ public:
    TYPE_LSHRDI,
    TYPE_ASHR,
    TYPE_ASHRI,
-    TYPE_ROR,
-    TYPE_RORI,
-    TYPE_ROL,
-    TYPE_ROLI,
    TYPE_BEXTR,
    TYPE_BLSI,
    TYPE_BLSMSK,
    TYPE_BLSR,
    TYPE_POPCOUNT,
    TYPE_BZHI,
-    TYPE_TZCNT,
-    TYPE_LZCNT,
+    TYPE_ZCNT,
    TYPE_RDRAND,
  };

@@ -232,6 +223,32 @@ public:
    return CanHaveSideEffects;
  }

+  template <typename F>
+  void ForeachDirection(F&& Routine) {
+    // Otherwise, prepare to branch.
+    auto Zero = _Constant(0);
+
+    // If the shift is zero, do not touch the flags.
+    auto ForwardBlock = CreateNewCodeBlockAfter(GetCurrentBlock());
+    auto BackwardBlock = CreateNewCodeBlockAfter(ForwardBlock);
+    auto ExitBlock = CreateNewCodeBlockAfter(BackwardBlock);
+
+    auto DF = GetRFLAG(X86State::RFLAG_DF_RAW_LOC);
+    CondJump(DF, Zero, ForwardBlock, BackwardBlock, {COND_EQ});
+
+    for (auto D = 0; D < 2; ++D) {
+      SetCurrentCodeBlock(D ? BackwardBlock : ForwardBlock);
+      StartNewBlock();
+      {
+        Routine(D ? -1 : 1);
+        Jump(ExitBlock);
+      }
+    }
+
+    SetCurrentCodeBlock(ExitBlock);
+    StartNewBlock();
+  }
+
  OpDispatchBuilder(FEXCore::Context::ContextImpl *ctx);
  OpDispatchBuilder(FEXCore::Utils::IntrusivePooledAllocator &Allocator);

@@ -261,6 +278,7 @@ public:
  template<FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp>
  void ALUOp(OpcodeArgs);
  void INTOp(OpcodeArgs);
+  template<bool IsSyscallInst>
  void SyscallOp(OpcodeArgs);
  void ThunkOp(OpcodeArgs);
  void LEAOp(OpcodeArgs);
@@ -271,8 +289,9 @@ public:
  void SecondaryALUOp(OpcodeArgs);
  template<uint32_t SrcIndex>
  void ADCOp(OpcodeArgs);
-  template<uint32_t SrcIndex, bool SetFlags>
+  template<uint32_t SrcIndex>
  void SBBOp(OpcodeArgs);
+  void SALCOp(OpcodeArgs);
  void PUSHOp(OpcodeArgs);
  void PUSHREGOp(OpcodeArgs);
  void PUSHAOp(OpcodeArgs);
@@ -310,25 +329,22 @@ public:
  void CMOVOp(OpcodeArgs);
  void CPUIDOp(OpcodeArgs);
  void XGetBVOp(OpcodeArgs);
-  template<bool SHL1Bit>
+  uint32_t LoadConstantShift(X86Tables::DecodedOp Op, bool Is1Bit);
  void SHLOp(OpcodeArgs);
+  template<bool SHL1Bit>
  void SHLImmediateOp(OpcodeArgs);
-  template<bool SHR1Bit>
  void SHROp(OpcodeArgs);
+  template<bool SHR1Bit>
  void SHRImmediateOp(OpcodeArgs);
  void SHLDOp(OpcodeArgs);
  void SHLDImmediateOp(OpcodeArgs);
  void SHRDOp(OpcodeArgs);
  void SHRDImmediateOp(OpcodeArgs);
-  template<bool SHR1Bit>
  void ASHROp(OpcodeArgs);
+  template<bool SHR1Bit>
  void ASHRImmediateOp(OpcodeArgs);
-  template<bool Is1Bit>
-  void ROROp(OpcodeArgs);
-  void RORImmediateOp(OpcodeArgs);
-  template<bool Is1Bit>
-  void ROLOp(OpcodeArgs);
-  void ROLImmediateOp(OpcodeArgs);
+  template<bool Left, bool IsImmediate, bool Is1Bit>
+  void RotateOp(OpcodeArgs);
  void RCROp1Bit(OpcodeArgs);
  void RCROp8x1Bit(OpcodeArgs);
  void RCROp(OpcodeArgs);
@@ -352,6 +368,11 @@ public:
  void PUSHFOp(OpcodeArgs);
  void POPFOp(OpcodeArgs);

+  struct CycleCounterPair {
+    OrderedNode *CounterLow;
+    OrderedNode *CounterHigh;
+  };
+  CycleCounterPair CycleCounter();
  void RDTSCOp(OpcodeArgs);
  void INCOp(OpcodeArgs);
  void DECOp(OpcodeArgs);
@@ -806,6 +827,7 @@ public:
  void FXSaveOp(OpcodeArgs);
  void FXRStoreOp(OpcodeArgs);

+  OrderedNode *XSaveBase(X86Tables::DecodedOp Op);
  void XSaveOp(OpcodeArgs);

  void PAlignrOp(OpcodeArgs);
@@ -864,9 +886,15 @@ public:
  void StoreFenceOrCLFlush(OpcodeArgs);
  void CLZeroOp(OpcodeArgs);
  void RDTSCPOp(OpcodeArgs);
+  void RDPIDOp(OpcodeArgs);
+
+  template<bool ForStore, bool Stream, uint8_t Level>
+  void Prefetch(OpcodeArgs);

  void PSADBW(OpcodeArgs);

+  OrderedNode *BitwiseAtLeastTwo(OrderedNode *A, OrderedNode *B, OrderedNode *C);
+
  void SHA1NEXTEOp(OpcodeArgs);
  void SHA1MSG1Op(OpcodeArgs);
  void SHA1MSG2Op(OpcodeArgs);
@@ -972,16 +1000,7 @@ private:
  }

  static bool IsNZCV(unsigned BitOffset) {
-    switch (BitOffset) {
-      case FEXCore::X86State::RFLAG_CF_RAW_LOC:
-      case FEXCore::X86State::RFLAG_ZF_RAW_LOC:
-      case FEXCore::X86State::RFLAG_SF_RAW_LOC:
-      case FEXCore::X86State::RFLAG_OF_RAW_LOC:
-        return true;
-
-      default:
-        return false;
-    }
+    return ContainsNZCV(1U << BitOffset);
  }

  OrderedNode* CachedNZCV{};
@@ -995,7 +1014,7 @@ private:
  // Used during new op bringup
  bool ShouldDump{false};

-  void ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp);
+  void ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp, unsigned SrcIdx);

  // Opcode helpers for generalizing behavior across VEX and non-VEX variants.

@@ -1261,13 +1280,33 @@ private:
    return NZCVMask;
  }

-  OrderedNode *GetNZCV() {
-    if (!CachedNZCV) {
-      CachedNZCV = _LoadNZCV();
+  // Set flag tracking to prepare for an operation that directly writes NZCV. If
+  // some bits are known to be zeroed, the PossiblySetNZCVBits mask can be
+  // passed. Otherwise, it defaults to assuming all bits may be set after
+  // (this is conservative).
+  void HandleNZCVWrite(uint32_t _PossiblySetNZCVBits = ~0) {
+    InvalidateDeferredFlags();
+    CachedNZCV = nullptr;
+    PossiblySetNZCVBits = _PossiblySetNZCVBits;
+    NZCVDirty = false;
+  }

-      // We don't know what's set
-      PossiblySetNZCVBits = ~0;
-    }
+  // Set flag tracking to prepare for a read-modify-write operation on NZCV.
+  void HandleNZCV_RMW(uint32_t _PossiblySetNZCVBits = ~0) {
+    if (NZCVDirty && CachedNZCV)
+      _StoreNZCV(CachedNZCV);
+
+    HandleNZCVWrite(_PossiblySetNZCVBits);
+  }
+
+  // Special case of the above where we are known to zero C/V
+  void HandleNZ00Write() {
+    HandleNZCVWrite((1u << 31) | (1u << 30));
+  }
+
+  OrderedNode *GetNZCV() {
+    if (!CachedNZCV)
+      CachedNZCV = _LoadNZCV();

    return CachedNZCV;
  }
@@ -1295,10 +1334,8 @@ private:
  }

  void SetNZ_ZeroCV(unsigned SrcSize, OrderedNode *Res) {
+    HandleNZ00Write();
    _TestNZ(IR::SizeToOpSize(SrcSize), Res, Res);
-    CachedNZCV = _LoadNZCV();
-    PossiblySetNZCVBits = (1u << 31) | (1u << 30);
-    NZCVDirty = false;
  }

  void InsertNZCV(unsigned BitOffset, OrderedNode *Value, signed FlagOffset, bool MustMask) {
@@ -1372,6 +1409,11 @@ private:
      if (ValueOffset || MustMask)
        Value = _Bfe(OpSize::i32Bit, 1, ValueOffset, Value);

+      // For DF, we need to transform 0/1 into 1/-1
+      if (BitOffset == FEXCore::X86State::RFLAG_DF_RAW_LOC) {
+        Value = _SubShift(OpSize::i64Bit, _Constant(1), Value, ShiftType::LSL, 1);
+      }
+
      _StoreFlag(Value, BitOffset);
    }
  }
@@ -1384,7 +1426,7 @@ private:
    SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(_Constant(Constant << 4));
  }

-  void ZeroMultipleFlags(uint32_t BitMask);
+  void ZeroPF_AF();

  CondClassType CondForNZCVBit(unsigned BitOffset, bool Invert) {
    switch (BitOffset) {
@@ -1424,11 +1466,32 @@ private:
      return _LoadRegister(false, offsetof(FEXCore::Core::CPUState, pf_raw), GPRClass, GPRFixedClass, CTX->GetGPRSize());
    } else if (BitOffset == FEXCore::X86State::RFLAG_AF_RAW_LOC) {
      return _LoadRegister(false, offsetof(FEXCore::Core::CPUState, af_raw), GPRClass, GPRFixedClass, CTX->GetGPRSize());
+    } else if (BitOffset == FEXCore::X86State::RFLAG_DF_RAW_LOC) {
+      // Recover the sign bit, it is the logical DF value
+      return _Lshr(OpSize::i64Bit, _LoadDF(), _Constant(63));
    } else {
      return _LoadFlag(BitOffset);
    }
  }

+  // Returns (DF ? -Size : Size)
+  OrderedNode *LoadDir(const unsigned Size) {
+    auto Dir = _LoadDF();
+    auto Shift = FEXCore::ilog2(Size);
+
+    if (Shift)
+      return _Lshl(IR::SizeToOpSize(CTX->GetGPRSize()), Dir, _Constant(Shift));
+    else
+      return Dir;
+  }
+
+  // Returns DF ? (X - Size) : (X + Size)
+  OrderedNode *OffsetByDir(OrderedNode *X, const unsigned Size) {
+    auto Shift = FEXCore::ilog2(Size);
+
+    return _AddShift(OpSize::i64Bit, X, _LoadDF(), ShiftType::LSL, Shift);
+  }
+
  // Set SSE comparison flags based on the result set by Arm FCMP. This converts
  // NZCV from the Arm representation to an eXternal representation that's
  // totally not a euphemism for x86 or anything, nuh-uh.
@@ -1568,7 +1631,7 @@ private:
  }

  std::pair<bool, CondClassType> DecodeNZCVCondition(uint8_t OP) const;
-  OrderedNode *SelectBit(OrderedNode *Cmp, bool Invert, IR::OpSize ResultSize, OrderedNode *TrueValue, OrderedNode *FalseValue);
+  OrderedNode *SelectBit(OrderedNode *Cmp, IR::OpSize ResultSize, OrderedNode *TrueValue, OrderedNode *FalseValue);
  OrderedNode *SelectCC(uint8_t OP, IR::OpSize ResultSize, OrderedNode *TrueValue, OrderedNode *FalseValue);

  /**
@@ -1601,29 +1664,22 @@ private:
    OrderedNode *Res{};

    union {
-      // UMUL, BEXTR, BLSI, BLSMSK, POPCOUNT, TZCNT, LZCNT, RDRAND
+      // UMUL, BEXTR, BLSI, POPCOUNT, ZCNT, RDRAND
      struct {
      } NoSource;

-      // MUL, BLSR, BZHI
+      // MUL, BLSR, BLSMSKB, BZHI
      struct {
        OrderedNode *Src1;
      } OneSource;

-      // Logical, LSHL, LSHR, ASHR, ROR, ROL
+      // Logical, LSHL, LSHR, ASHR
      struct {
        OrderedNode *Src1;
        OrderedNode *Src2;
      } TwoSource;

-      // ADC, SBB
-      struct {
-        OrderedNode *Src1;
-        OrderedNode *Src2;
-        OrderedNode *Src3;
-      } ThreeSource;
-
-      // LSHLI, LSHRI, ASHRI, RORI, ROLI
+      // LSHLI, LSHRI, ASHRI
      struct {
        OrderedNode *Src1;
        uint64_t Imm;
@@ -1672,15 +1728,12 @@ private:
  }

  template <typename F>
-  void CalculateFlags_ShiftVariable(OrderedNode *Shift, F&& CalculateFlags) {
-    // We are the ones calculating the deferred flags. Don't recurse!
-    InvalidateDeferredFlags();
-
+  void Calculate_ShiftVariable(OrderedNode *Shift, F&& Calculate) {
    // RCR can call this with constants, so handle that without branching.
    uint64_t Const;
    if (IsValueConstant(WrapNode(Shift), &Const)) {
      if (Const)
-        CalculateFlags();
+        Calculate();

      return;
    }
@@ -1697,7 +1750,7 @@ private:
    SetCurrentCodeBlock(SetBlock);
    StartNewBlock();
    {
-      CalculateFlags();
+      Calculate();
      Jump(EndBlock);
    }

@@ -1706,20 +1759,29 @@ private:
    PossiblySetNZCVBits |= OldSetNZCVBits;
  }

+  template <typename F>
+  void CalculateFlags_ShiftVariable(OrderedNode *Shift, F&& CalculateFlags) {
+    // We are the ones calculating the deferred flags. Don't recurse!
+    InvalidateDeferredFlags();
+    Calculate_ShiftVariable(Shift, CalculateFlags);
+  }
+
  /**
   * @name These functions are used by the deferred flag handling while it is calculating and storing flags in to RFLAGs.
   * @{ */
-  OrderedNode *LoadPFRaw();
+  OrderedNode *LoadPFRaw(bool Invert);
  OrderedNode *LoadAF();
  void FixupAF();
+  void SetAFAndFixup(OrderedNode *AF);
+  OrderedNode *CalculateAFForDecimal(OrderedNode *A);
  void CalculatePF(OrderedNode *Res);
-  void CalculateAF(OpSize OpSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculateAF(OrderedNode *Src1, OrderedNode *Src2);

  void CalculateOF(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool Sub);
-  void CalculateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
-  void CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
-  void CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
-  void CalculateFlags_ADD(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
+  OrderedNode *CalculateFlags_ADC(uint8_t SrcSize, OrderedNode *Src1, OrderedNode *Src2);
+  OrderedNode *CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Src1, OrderedNode *Src2);
+  OrderedNode *CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
+  OrderedNode *CalculateFlags_ADD(uint8_t SrcSize, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
  void CalculateFlags_MUL(uint8_t SrcSize, OrderedNode *Res, OrderedNode *High);
  void CalculateFlags_UMUL(OrderedNode *High);
  void CalculateFlags_Logical(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
@@ -1731,18 +1793,13 @@ private:
  void CalculateFlags_ShiftRightImmediateCommon(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
  void CalculateFlags_SignShiftRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
  void CalculateFlags_SignShiftRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void CalculateFlags_RotateRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void CalculateFlags_RotateLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void CalculateFlags_RotateRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void CalculateFlags_RotateLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
  void CalculateFlags_BEXTR(OrderedNode *Src);
  void CalculateFlags_BLSI(uint8_t SrcSize, OrderedNode *Src);
-  void CalculateFlags_BLSMSK(OrderedNode *Src);
+  void CalculateFlags_BLSMSK(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src);
  void CalculateFlags_BLSR(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src);
  void CalculateFlags_POPCOUNT(OrderedNode *Src);
  void CalculateFlags_BZHI(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src);
-  void CalculateFlags_TZCNT(OrderedNode *Src);
-  void CalculateFlags_LZCNT(uint8_t SrcSize, OrderedNode *Src);
+  void CalculateFlags_ZCNT(uint8_t SrcSize, OrderedNode *Result);
  void CalculateFlags_RDRAND(OrderedNode *Src);
  /**  @} */

@@ -1751,37 +1808,7 @@ private:
   *
   * Depending on the operation it may force a RFLAGs calculation before storing the new deferred state.
   * @{ */
-  void GenerateFlags_ADC(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
-    CurrentDeferredFlags = DeferredFlagData {
-      .Type = FlagsGenerationType::TYPE_ADC,
-      .SrcSize = GetSrcSize(Op),
-      .Res = Res,
-      .Sources = {
-        .ThreeSource = {
-          .Src1 = Src1,
-          .Src2 = Src2,
-          .Src3 = CF,
-        },
-      },
-    };
-  }
-
-  void GenerateFlags_SBB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
-    CurrentDeferredFlags = DeferredFlagData {
-      .Type = FlagsGenerationType::TYPE_SBB,
-      .SrcSize = GetSrcSize(Op),
-      .Res = Res,
-      .Sources = {
-        .ThreeSource = {
-          .Src1 = Src1,
-          .Src2 = Src2,
-          .Src3 = CF,
-        },
-      },
-    };
-  }
-
-  void GenerateFlags_SUB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true) {
+  void GenerateFlags_SUB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true) {
    if (!UpdateCF) {
      // If we aren't updating CF then we need to calculate flags. Invalidation mask would make this not required.
      CalculateDeferredFlags();
@@ -1789,26 +1816,6 @@ private:
    CurrentDeferredFlags = DeferredFlagData {
      .Type = FlagsGenerationType::TYPE_SUB,
      .SrcSize = GetSrcSize(Op),
-      .Res = Res,
-      .Sources = {
-        .TwoSrcImmediate = {
-          .Src1 = Src1,
-          .Src2 = Src2,
-          .UpdateCF = UpdateCF,
-        },
-      },
-    };
-  }
-
-  void GenerateFlags_ADD(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true) {
-    if (!UpdateCF) {
-      // If we aren't updating CF then we need to calculate flags. Invalidation mask would make this not required.
-      CalculateDeferredFlags();
-    }
-    CurrentDeferredFlags = DeferredFlagData {
-      .Type = FlagsGenerationType::TYPE_ADD,
-      .SrcSize = GetSrcSize(Op),
-      .Res = Res,
      .Sources = {
        .TwoSrcImmediate = {
          .Src1 = Src1,
@@ -1973,78 +1980,6 @@ private:
    };
  }

-  void GenerateFlags_RotateRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
-    // Doesn't set all the flags, needs to calculate.
-    CalculateDeferredFlags();
-
-    CurrentDeferredFlags = DeferredFlagData {
-      .Type = FlagsGenerationType::TYPE_ROR,
-      .SrcSize = GetSrcSize(Op),
-      .Res = Res,
-      .Sources = {
-        .TwoSource = {
-          .Src1 = Src1,
-          .Src2 = Src2,
-        },
-      },
-    };
-  }
-
-  void GenerateFlags_RotateLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
-    // Doesn't set all the flags, needs to calculate.
-    CalculateDeferredFlags();
-
-    CurrentDeferredFlags = DeferredFlagData {
-      .Type = FlagsGenerationType::TYPE_ROL,
-      .SrcSize = GetSrcSize(Op),
-      .Res = Res,
-      .Sources = {
-        .TwoSource = {
-          .Src1 = Src1,
-          .Src2 = Src2,
-        },
-      },
-    };
-  }
-
-  void GenerateFlags_RotateRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
-    if (Shift == 0) return;
-
-    // Doesn't set all the flags, needs to calculate.
-    CalculateDeferredFlags();
-
-    CurrentDeferredFlags = DeferredFlagData {
-      .Type = FlagsGenerationType::TYPE_RORI,
-      .SrcSize = GetSrcSize(Op),
-      .Res = Res,
-      .Sources = {
-        .OneSrcImmediate = {
-          .Src1 = Src1,
-          .Imm = Shift,
-        },
-      },
-    };
-  }
-
-  void GenerateFlags_RotateLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
-    if (Shift == 0) return;
-
-    // Doesn't set all the flags, needs to calculate.
-    CalculateDeferredFlags();
-
-    CurrentDeferredFlags = DeferredFlagData {
-      .Type = FlagsGenerationType::TYPE_ROLI,
-      .SrcSize = GetSrcSize(Op),
-      .Res = Res,
-      .Sources = {
-        .OneSrcImmediate = {
-          .Src1 = Src1,
-          .Imm = Shift,
-        },
-      }
-    };
-  }
-
  void GenerateFlags_BEXTR(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
    CurrentDeferredFlags = DeferredFlagData {
      .Type = FlagsGenerationType::TYPE_BEXTR,
@@ -2061,11 +1996,16 @@ private:
    };
  }

-  void GenerateFlags_BLSMSK(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
+  void GenerateFlags_BLSMSK(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src) {
    CurrentDeferredFlags = DeferredFlagData {
      .Type = FlagsGenerationType::TYPE_BLSMSK,
      .SrcSize = GetSrcSize(Op),
-      .Res = Src,
+      .Res = Res,
+      .Sources = {
+        .OneSource = {
+          .Src1 = Src,
+        },
+      },
    };
  }

@@ -2103,17 +2043,9 @@ private:
    };
  }

-  void GenerateFlags_TZCNT(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
+  void GenerateFlags_ZCNT(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
    CurrentDeferredFlags = DeferredFlagData {
-      .Type = FlagsGenerationType::TYPE_TZCNT,
-      .SrcSize = GetSrcSize(Op),
-      .Res = Src,
-    };
-  }
-
-  void GenerateFlags_LZCNT(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Src) {
-    CurrentDeferredFlags = DeferredFlagData {
-      .Type = FlagsGenerationType::TYPE_LZCNT,
+      .Type = FlagsGenerationType::TYPE_ZCNT,
      .SrcSize = GetSrcSize(Op),
      .Res = Src,
    };
@@ -2127,6 +2059,16 @@ private:
    };
  }

+  OrderedNode *AndConst(FEXCore::IR::OpSize Size, OrderedNode *Node, uint64_t Const) {
+    uint64_t NodeConst;
+
+    if (IsValueConstant(WrapNode(Node), &NodeConst)) {
+      return _Constant(NodeConst & Const);
+    } else {
+      return _And(Size, Node, _Constant(Const));
+    }
+  }
+
  /**  @} */
  /**  @} */

@@ -2167,6 +2109,10 @@ private:
      return _LoadMem(Class, Size, ssa0, Invalid(), Align, MEM_OFFSET_SXTX, 1);
  }

+  OrderedNode* Prefetch(bool ForStore, bool Stream, uint8_t CacheLevel, OrderedNode *ssa0) {
+    return _Prefetch(ForStore, Stream, CacheLevel, ssa0, Invalid(), MEM_OFFSET_SXTX, 1);
+  }
+
  void InstallHostSpecificOpcodeHandlers();

  ///< Segment telemetry tracking
@@ -8,7 +8,6 @@ $end_info$

 #include "Interface/Core/X86Tables/X86Tables.h"

-#include <FEXCore/IR/IREmitter.h>
 #include <FEXCore/Utils/LogManager.h>
 #include "Interface/Core/OpcodeDispatcher.h"

@@ -104,7 +103,7 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
    return Self._Xor(OpSize::i32Bit, Self._Xor(OpSize::i32Bit, B, C), D);
  };
  const auto f2 = [](OpDispatchBuilder &Self, OrderedNode *B, OrderedNode *C, OrderedNode *D) -> OrderedNode* {
-    return Self._Xor(OpSize::i32Bit, Self._Xor(OpSize::i32Bit, Self._And(OpSize::i32Bit, B, C), Self._And(OpSize::i32Bit, B, D)), Self._And(OpSize::i32Bit, C, D));
+    return Self.BitwiseAtLeastTwo(B, C, D);
  };
  const auto f3 = [](OpDispatchBuilder &Self, OrderedNode *B, OrderedNode *C, OrderedNode *D) -> OrderedNode* {
    return Self._Xor(OpSize::i32Bit, Self._Xor(OpSize::i32Bit, B, C), D);
@@ -129,9 +128,6 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);

  auto W0E = _VExtractToGPR(16, 4, Src, 3);
-  auto W1  = _VExtractToGPR(16, 4, Src, 2);
-  auto W2  = _VExtractToGPR(16, 4, Src, 1);
-  auto W3  = _VExtractToGPR(16, 4, Src, 0);

  using RoundResult = std::tuple<OrderedNode*, OrderedNode*, OrderedNode*, OrderedNode*, OrderedNode*>;

@@ -150,8 +146,12 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
    return {A1, B1, C1, D1, E1};
  };
  const auto Round1To3 = [&](OrderedNode *A, OrderedNode *B, OrderedNode *C,
-                             OrderedNode *D, OrderedNode *E, OrderedNode *W) -> RoundResult {
-    auto ANext = _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, Fn(*this, B, C, D), _Ror(OpSize::i32Bit, A, _Constant(32, 27))), W), E), K);
+                             OrderedNode *D, OrderedNode *E, OrderedNode *Src, unsigned W_idx) -> RoundResult {
+    // Kill W and E at the beginning
+    auto W = _VExtractToGPR(16, 4, Src, W_idx);
+    auto Q = _Add(OpSize::i32Bit, W, E);
+
+    auto ANext = _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, Fn(*this, B, C, D), _Ror(OpSize::i32Bit, A, _Constant(32, 27))), Q), K);
    auto BNext = A;
    auto CNext = _Ror(OpSize::i32Bit, B, _Constant(32, 2));
    auto DNext = C;
@@ -161,9 +161,9 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
  };

  auto [A1, B1, C1, D1, E1] = Round0();
-  auto [A2, B2, C2, D2, E2] = Round1To3(A1, B1, C1, D1, E1, W1);
-  auto [A3, B3, C3, D3, E3] = Round1To3(A2, B2, C2, D2, E2, W2);
-  auto Final                = Round1To3(A3, B3, C3, D3, E3, W3);
+  auto [A2, B2, C2, D2, E2] = Round1To3(A1, B1, C1, D1, E1, Src, 2);
+  auto [A3, B3, C3, D3, E3] = Round1To3(A2, B2, C2, D2, E2, Src, 1);
+  auto Final                = Round1To3(A3, B3, C3, D3, E3, Src, 0);

  auto Dest3 = _VInsGPR(16, 4, 3, Dest,  std::get<0>(Final));
  auto Dest2 = _VInsGPR(16, 4, 2, Dest3, std::get<1>(Final));
@@ -230,18 +230,25 @@ void OpDispatchBuilder::SHA256MSG2Op(OpcodeArgs) {
  StoreResult(FPRClass, Op, D0, -1);
 }

+OrderedNode *OpDispatchBuilder::BitwiseAtLeastTwo(OrderedNode *A, OrderedNode *B, OrderedNode *C) {
+    // Returns whether at least 2/3 of A/B/C is true.
+    // Expressed as (A & (B | C)) | (B & C)
+    //
+    // Equivalent to expression in SHA calculations: (A & B) ^ (A & C) ^ (B & C)
+    auto And = _And(OpSize::i32Bit, B, C);
+    auto Or = _Or(OpSize::i32Bit, B, C);
+    return _Or(OpSize::i32Bit, _And(OpSize::i32Bit, A, Or), And);
+}
+
 void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) {
  const auto Ch = [this](OrderedNode *E, OrderedNode *F, OrderedNode *G) -> OrderedNode* {
    return _Xor(OpSize::i32Bit, _And(OpSize::i32Bit, E, F), _Andn(OpSize::i32Bit, G, E));
  };
-  const auto Major = [this](OrderedNode *A, OrderedNode *B, OrderedNode *C) -> OrderedNode* {
-    return _Xor(OpSize::i32Bit, _Xor(OpSize::i32Bit, _And(OpSize::i32Bit, A, B), _And(OpSize::i32Bit, A, C)), _And(OpSize::i32Bit, B, C));
-  };
  const auto Sigma0 = [this](OrderedNode *A) -> OrderedNode* {
-    return _Xor(OpSize::i32Bit, _Xor(OpSize::i32Bit, _Ror(OpSize::i32Bit, A, _Constant(32, 2)), _Ror(OpSize::i32Bit, A, _Constant(32, 13))), _Ror(OpSize::i32Bit, A, _Constant(32, 22)));
+    return _XorShift(OpSize::i32Bit, _XorShift(OpSize::i32Bit, _Ror(OpSize::i32Bit, A, _Constant(32, 2)), A, ShiftType::ROR, 13), A, ShiftType::ROR, 22);
  };
  const auto Sigma1 = [this](OrderedNode *E) -> OrderedNode* {
-    return _Xor(OpSize::i32Bit, _Xor(OpSize::i32Bit, _Ror(OpSize::i32Bit, E, _Constant(32, 6)), _Ror(OpSize::i32Bit, E, _Constant(32, 11))), _Ror(OpSize::i32Bit, E, _Constant(32, 25)));
+    return _XorShift(OpSize::i32Bit, _XorShift(OpSize::i32Bit, _Ror(OpSize::i32Bit, E, _Constant(32, 6)), E, ShiftType::ROR, 11), E, ShiftType::ROR, 25);
  };

  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
@@ -249,42 +256,44 @@ void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) {
  // Hardcoded to XMM0
  auto XMM0 = LoadXMMRegister(0);

-  auto A0 = _VExtractToGPR(16, 4, Src, 3);
-  auto B0 = _VExtractToGPR(16, 4, Src, 2);
-  auto C0 = _VExtractToGPR(16, 4, Dest, 3);
-  auto D0 = _VExtractToGPR(16, 4, Dest, 2);
  auto E0 = _VExtractToGPR(16, 4, Src, 1);
  auto F0 = _VExtractToGPR(16, 4, Src, 0);
  auto G0 = _VExtractToGPR(16, 4, Dest, 1);
-  auto H0 = _VExtractToGPR(16, 4, Dest, 0);
+  OrderedNode *Q0 = _Add(OpSize::i32Bit, Ch(E0, F0, G0), Sigma1(E0));
+
  auto WK0 = _VExtractToGPR(16, 4, XMM0, 0);
+  Q0 = _Add(OpSize::i32Bit, Q0, WK0);
+
+  auto H0 = _VExtractToGPR(16, 4, Dest, 0);
+  Q0 = _Add(OpSize::i32Bit, Q0, H0);
+
+  auto A0 = _VExtractToGPR(16, 4, Src, 3);
+  auto B0 = _VExtractToGPR(16, 4, Src, 2);
+  auto C0 = _VExtractToGPR(16, 4, Dest, 3);
+  auto A1 = _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, Q0, BitwiseAtLeastTwo(A0, B0, C0)), Sigma0(A0));
+
+  auto D0 = _VExtractToGPR(16, 4, Dest, 2);
+  auto E1 = _Add(OpSize::i32Bit, Q0, D0);
+
+  OrderedNode * Q1 = _Add(OpSize::i32Bit, Ch(E1, E0, F0), Sigma1(E1));
+
  auto WK1 = _VExtractToGPR(16, 4, XMM0, 1);
+  Q1 = _Add(OpSize::i32Bit, Q1, WK1);

-  using RoundResult = std::tuple<OrderedNode*, OrderedNode*, OrderedNode*, OrderedNode*,
-                                 OrderedNode*, OrderedNode*, OrderedNode*, OrderedNode*>;
-  const auto Round = [&](OrderedNode *A, OrderedNode *B, OrderedNode *C, OrderedNode *D,
-                         OrderedNode *E, OrderedNode *F, OrderedNode *G, OrderedNode *H,
-                         OrderedNode* WK) -> RoundResult {
-    auto ANext = _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, Ch(E, F, G), Sigma1(E)), WK), H), Major(A, B, C)), Sigma0(A));
-    auto BNext = A;
-    auto CNext = B;
-    auto DNext = C;
-    auto ENext = _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, Ch(E, F, G), Sigma1(E)), WK), H), D);
-    auto FNext = E;
-    auto GNext = F;
-    auto HNext = G;
+  // Rematerialize G0. Costs a move but saves spilling, coming out ahead.
+  G0 = _VExtractToGPR(16, 4, Dest, 1);
+  Q1 = _Add(OpSize::i32Bit, Q1, G0);

-    return {ANext, BNext, CNext, DNext, ENext, FNext, GNext, HNext};
-  };
+  auto A2 = _Add(OpSize::i32Bit, _Add(OpSize::i32Bit, Q1, BitwiseAtLeastTwo(A1, A0, B0)), Sigma0(A1));

+  // Rematerialize C0. As with G0.
+  C0 = _VExtractToGPR(16, 4, Dest, 3);
+  auto E2 = _Add(OpSize::i32Bit, Q1, C0);

-  auto [A1, B1, C1, D1, E1, F1, G1, H1] = Round(A0, B0, C0, D0, E0, F0, G0, H0, WK0);
-  auto Final                            = Round(A1, B1, C1, D1, E1, F1, G1, H1, WK1);
-
-  auto Res3 = _VInsGPR(16, 4, 3, Dest, std::get<0>(Final));
-  auto Res2 = _VInsGPR(16, 4, 2, Res3, std::get<1>(Final));
-  auto Res1 = _VInsGPR(16, 4, 1, Res2, std::get<4>(Final));
-  auto Res0 = _VInsGPR(16, 4, 0, Res1, std::get<5>(Final));
+  auto Res3 = _VInsGPR(16, 4, 3, Dest, A2);
+  auto Res2 = _VInsGPR(16, 4, 2, Res3, A1);
+  auto Res1 = _VInsGPR(16, 4, 1, Res2, E2);
+  auto Res0 = _VInsGPR(16, 4, 0, Res1, E1);

  StoreResult(FPRClass, Op, Res0, -1);
 }
@@ -13,7 +13,6 @@ $end_info$
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/IR/IR.h>

 #include <array>
 #include <cstdint>
@@ -27,7 +26,7 @@ constexpr std::array<uint32_t, 17> FlagOffsets = {
  FEXCore::X86State::RFLAG_SF_RAW_LOC,
  FEXCore::X86State::RFLAG_TF_LOC,
  FEXCore::X86State::RFLAG_IF_LOC,
-  FEXCore::X86State::RFLAG_DF_LOC,
+  FEXCore::X86State::RFLAG_DF_RAW_LOC,
  FEXCore::X86State::RFLAG_OF_RAW_LOC,
  FEXCore::X86State::RFLAG_IOPL_LOC,
  FEXCore::X86State::RFLAG_NT_LOC,
@@ -39,61 +38,10 @@ constexpr std::array<uint32_t, 17> FlagOffsets = {
  FEXCore::X86State::RFLAG_ID_LOC,
 };

-void OpDispatchBuilder::ZeroMultipleFlags(uint32_t FlagsMask) {
-  auto ZeroConst = _Constant(0);
-
-  if (ContainsNZCV(FlagsMask)) {
-    // NZCV is stored packed together.
-    // It's more optimal to zero NZCV with move+bic instead of multiple bics.
-    auto NZCVFlagsMask = FlagsMask & FullNZCVMask;
-    if (NZCVFlagsMask == FullNZCVMask) {
-      ZeroNZCV();
-    }
-    else {
-      const auto IndexMask = NZCVIndexMask(FlagsMask);
-
-      if (std::popcount(NZCVFlagsMask) == 1) {
-        // It's more optimal to store only one here.
-
-        for (size_t i = 0; NZCVFlagsMask && i < FlagOffsets.size(); ++i) {
-          const auto FlagOffset = FlagOffsets[i];
-          const auto FlagMask = 1U << FlagOffset;
-          if (!(FlagMask & NZCVFlagsMask)) {
-            continue;
-          }
-          SetRFLAG(ZeroConst, FlagOffset);
-          NZCVFlagsMask &= ~(FlagMask);
-        }
-      }
-      else {
-        auto IndexMaskConstant = _Constant(IndexMask);
-        auto NewNZCV = _Andn(OpSize::i64Bit, GetNZCV(), IndexMaskConstant);
-        SetNZCV(NewNZCV);
-      }
-      // Unset the possibly set bits.
-      PossiblySetNZCVBits &= ~IndexMask;
-    }
-
-    // Handled NZCV, so remove it from the mask.
-    FlagsMask &= ~FullNZCVMask;
-  }
-
+void OpDispatchBuilder::ZeroPF_AF() {
  // PF is stored inverted, so invert it when we zero.
-  if (FlagsMask & (1u << X86State::RFLAG_PF_RAW_LOC)) {
-    SetRFLAG<FEXCore::X86State::RFLAG_PF_RAW_LOC>(_Constant(1));
-    FlagsMask &= ~(1u << X86State::RFLAG_PF_RAW_LOC);
-  }
-
-  // Handle remaining masks.
-  for (size_t i = 0; FlagsMask && i < FlagOffsets.size(); ++i) {
-    const auto FlagOffset = FlagOffsets[i];
-    const auto FlagMask = 1U << FlagOffset;
-    if (!(FlagMask & FlagsMask)) {
-      continue;
-    }
-    SetRFLAG(ZeroConst, FlagOffset);
-    FlagsMask &= ~(FlagMask);
-  }
+  SetRFLAG<FEXCore::X86State::RFLAG_PF_RAW_LOC>(_Constant(1));
+  SetAF(0);
 }

 void OpDispatchBuilder::SetPackedRFLAG(bool Lower8, OrderedNode *Src) {
@@ -180,7 +128,7 @@ OrderedNode *OpDispatchBuilder::GetPackedRFLAG(uint32_t FlagsMask) {
  // instead.
  if (FlagsMask & (1 << FEXCore::X86State::RFLAG_PF_RAW_LOC)) {
    // Set every bit except the bottommost.
-    auto OnesInvPF = _Or(OpSize::i64Bit, LoadPFRaw(), _Constant(~1ull));
+    auto OnesInvPF = _Or(OpSize::i64Bit, LoadPFRaw(false), _Constant(~1ull));

    // Rotate the bottom bit to the appropriate location for PF, so we get
    // something like 111P1111. Then invert that to get 000p0000. Then OR that
@@ -238,18 +186,21 @@ void OpDispatchBuilder::CalculateOF(uint8_t SrcSize, OrderedNode *Res, OrderedNo
  SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(Anded, SrcSize * 8 - 1, true);
 }

-OrderedNode *OpDispatchBuilder::LoadPFRaw() {
+OrderedNode *OpDispatchBuilder::LoadPFRaw(bool Invert) {
  // Read the stored byte. This is the original result (up to 64-bits), it needs
  // parity calculated.
  auto Result = GetRFLAG(FEXCore::X86State::RFLAG_PF_RAW_LOC);

-  // Cast the input to a 32-bit FPR. Logically we only need 8-bit, but that would
-  // generate unwanted an ubfx instruction. VPopcount will ignore the upper bits anyway.
-  auto InputFPR = _VCastFromGPR(4, 4, Result);
+  // Cascade to calculate parity of bottom 8-bits to bottom bit.
+  Result = _XorShift(OpSize::i32Bit, Result, Result, ShiftType::LSR, 4);
+  Result = _XorShift(OpSize::i32Bit, Result, Result, ShiftType::LSR, 2);

-  // Calculate the popcount.
-  auto Count = _VPopcount(1, 1, InputFPR);
-  return _VExtractToGPR(8, 1, Count, 0);
+  if (Invert)
+    Result = _XornShift(OpSize::i32Bit, Result, Result, ShiftType::LSR, 1);
+  else
+    Result = _XorShift(OpSize::i32Bit, Result, Result, ShiftType::LSR, 1);
+
+  return Result;
 }

 OrderedNode *OpDispatchBuilder::LoadAF() {
@@ -277,24 +228,43 @@ void OpDispatchBuilder::FixupAF() {
  SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(XorRes);
 }

+void OpDispatchBuilder::SetAFAndFixup(OrderedNode *AF) {
+  // We have a value of AF, we shift into AF[4].  We need to fixup AF[4] so that
+  // we get the right value when we XOR in PF[4] later. The easiest solution is
+  // to XOR by PF[4], since:
+  //
+  //  (AF[4] ^ PF[4]) ^ PF[4] = AF[4]
+
+  auto PFRaw = GetRFLAG(FEXCore::X86State::RFLAG_PF_RAW_LOC);
+
+  OrderedNode *XorRes = _XorShift(OpSize::i32Bit, PFRaw, AF, ShiftType::LSL, 4);
+  SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(XorRes);
+}
+
 void OpDispatchBuilder::CalculatePF(OrderedNode *Res) {
  // Calculation is entirely deferred until load, just store the 8-bit result.
  SetRFLAG<FEXCore::X86State::RFLAG_PF_RAW_LOC>(Res);
 }

-void OpDispatchBuilder::CalculateAF(OpSize OpSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+void OpDispatchBuilder::CalculateAF(OrderedNode *Src1, OrderedNode *Src2) {
  // We only care about bit 4 in the subsequent XOR. If we'll XOR with 0,
-  // there's no sense XOR'ing at all. This affects INC.
+  // there's no sense XOR'ing at all. If we'll XOR with 1, that's just
+  // inverting.
  uint64_t Const;
-  if (IsValueConstant(WrapNode(Src2), &Const) && (Const & (1u << 4)) == 0) {
-    SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(Src1);
+  if (IsValueConstant(WrapNode(Src2), &Const)) {
+    if (Const & (1u << 4)) {
+      SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(_Not(OpSize::i32Bit, Src1));
+    } else {
+      SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(Src1);
+    }
+
    return;
  }

  // We store the XOR of the arguments. At read time, we XOR with the
  // appropriate bit of the result (available as the PF flag) and extract the
  // appropriate bit.
-  OrderedNode *XorRes = _Xor(OpSize, Src1, Src2);
+  OrderedNode *XorRes = _Xor(OpSize::i32Bit, Src1, Src2);
  SetRFLAG<FEXCore::X86State::RFLAG_AF_RAW_LOC>(XorRes);
 }

@@ -310,34 +280,9 @@ void OpDispatchBuilder::CalculateDeferredFlags(uint32_t FlagsToCalculateMask) {
  }

  switch (CurrentDeferredFlags.Type) {
-    case FlagsGenerationType::TYPE_ADC:
-      CalculateFlags_ADC(
-        CurrentDeferredFlags.SrcSize,
-        CurrentDeferredFlags.Res,
-        CurrentDeferredFlags.Sources.ThreeSource.Src1,
-        CurrentDeferredFlags.Sources.ThreeSource.Src2,
-        CurrentDeferredFlags.Sources.ThreeSource.Src3);
-      break;
-    case FlagsGenerationType::TYPE_SBB:
-      CalculateFlags_SBB(
-        CurrentDeferredFlags.SrcSize,
-        CurrentDeferredFlags.Res,
-        CurrentDeferredFlags.Sources.ThreeSource.Src1,
-        CurrentDeferredFlags.Sources.ThreeSource.Src2,
-        CurrentDeferredFlags.Sources.ThreeSource.Src3);
-      break;
    case FlagsGenerationType::TYPE_SUB:
      CalculateFlags_SUB(
        CurrentDeferredFlags.SrcSize,
-        CurrentDeferredFlags.Res,
-        CurrentDeferredFlags.Sources.TwoSrcImmediate.Src1,
-        CurrentDeferredFlags.Sources.TwoSrcImmediate.Src2,
-        CurrentDeferredFlags.Sources.TwoSrcImmediate.UpdateCF);
-      break;
-    case FlagsGenerationType::TYPE_ADD:
-      CalculateFlags_ADD(
-        CurrentDeferredFlags.SrcSize,
-        CurrentDeferredFlags.Res,
        CurrentDeferredFlags.Sources.TwoSrcImmediate.Src1,
        CurrentDeferredFlags.Sources.TwoSrcImmediate.Src2,
        CurrentDeferredFlags.Sources.TwoSrcImmediate.UpdateCF);
@@ -407,34 +352,6 @@ void OpDispatchBuilder::CalculateDeferredFlags(uint32_t FlagsToCalculateMask) {
        CurrentDeferredFlags.Sources.OneSrcImmediate.Src1,
        CurrentDeferredFlags.Sources.OneSrcImmediate.Imm);
      break;
-    case FlagsGenerationType::TYPE_ROR:
-      CalculateFlags_RotateRight(
-        CurrentDeferredFlags.SrcSize,
-        CurrentDeferredFlags.Res,
-        CurrentDeferredFlags.Sources.TwoSource.Src1,
-        CurrentDeferredFlags.Sources.TwoSource.Src2);
-      break;
-    case FlagsGenerationType::TYPE_RORI:
-      CalculateFlags_RotateRightImmediate(
-        CurrentDeferredFlags.SrcSize,
-        CurrentDeferredFlags.Res,
-        CurrentDeferredFlags.Sources.OneSrcImmediate.Src1,
-        CurrentDeferredFlags.Sources.OneSrcImmediate.Imm);
-      break;
-    case FlagsGenerationType::TYPE_ROL:
-      CalculateFlags_RotateLeft(
-        CurrentDeferredFlags.SrcSize,
-        CurrentDeferredFlags.Res,
-        CurrentDeferredFlags.Sources.TwoSource.Src1,
-        CurrentDeferredFlags.Sources.TwoSource.Src2);
-      break;
-    case FlagsGenerationType::TYPE_ROLI:
-      CalculateFlags_RotateLeftImmediate(
-        CurrentDeferredFlags.SrcSize,
-        CurrentDeferredFlags.Res,
-        CurrentDeferredFlags.Sources.OneSrcImmediate.Src1,
-        CurrentDeferredFlags.Sources.OneSrcImmediate.Imm);
-      break;
    case FlagsGenerationType::TYPE_BEXTR:
      CalculateFlags_BEXTR(CurrentDeferredFlags.Res);
      break;
@@ -444,7 +361,10 @@ void OpDispatchBuilder::CalculateDeferredFlags(uint32_t FlagsToCalculateMask) {
        CurrentDeferredFlags.Res);
      break;
    case FlagsGenerationType::TYPE_BLSMSK:
-      CalculateFlags_BLSMSK(CurrentDeferredFlags.Res);
+      CalculateFlags_BLSMSK(
+        CurrentDeferredFlags.SrcSize,
+        CurrentDeferredFlags.Res,
+        CurrentDeferredFlags.Sources.OneSource.Src1);
      break;
    case FlagsGenerationType::TYPE_BLSR:
      CalculateFlags_BLSR(
@@ -461,11 +381,8 @@ void OpDispatchBuilder::CalculateDeferredFlags(uint32_t FlagsToCalculateMask) {
        CurrentDeferredFlags.Res,
        CurrentDeferredFlags.Sources.OneSource.Src1);
      break;
-    case FlagsGenerationType::TYPE_TZCNT:
-      CalculateFlags_TZCNT(CurrentDeferredFlags.Res);
-      break;
-    case FlagsGenerationType::TYPE_LZCNT:
-      CalculateFlags_LZCNT(
+    case FlagsGenerationType::TYPE_ZCNT:
+      CalculateFlags_ZCNT(
        CurrentDeferredFlags.SrcSize,
        CurrentDeferredFlags.Res);
      break;
@@ -486,150 +403,126 @@ void OpDispatchBuilder::CalculateDeferredFlags(uint32_t FlagsToCalculateMask) {
  NZCVDirty = false;
 }

-void OpDispatchBuilder::CalculateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
+OrderedNode *OpDispatchBuilder::CalculateFlags_ADC(uint8_t SrcSize, OrderedNode *Src1, OrderedNode *Src2) {
  auto Zero = _Constant(0);
  auto One = _Constant(1);
  auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
+  OrderedNode *Res;

-  CalculateAF(OpSize, Res, Src1, Src2);
-  CalculatePF(Res);
+  CalculateAF(Src1, Src2);

  if (SrcSize >= 4) {
-    if (NZCVDirty && CachedNZCV)
-      _StoreNZCV(CachedNZCV);
-    CachedNZCV = nullptr;
-
-    _AdcNZCV(OpSize, Src1, Src2);
-    PossiblySetNZCVBits = ~0;
+    HandleNZCV_RMW();
+    Res = _AdcWithFlags(OpSize, Src1, Src2);
  } else {
-    // SF/ZF
+    auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC);
+    Res = _Adc(OpSize, Src1, Src2);
+    Res = _Bfe(OpSize, SrcSize * 8, 0, Res);
+
+    auto SelectOpLT = _Select(FEXCore::IR::COND_ULT, Res, Src2, One, Zero);
+    auto SelectOpLE = _Select(FEXCore::IR::COND_ULE, Res, Src2, One, Zero);
+    auto SelectCF   = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT);
+
    SetNZ_ZeroCV(SrcSize, Res);
-
-    // CF
-    // Unsigned
-    {
-      auto SelectOpLT = _Select(FEXCore::IR::COND_ULT, Res, Src2, One, Zero);
-      auto SelectOpLE = _Select(FEXCore::IR::COND_ULE, Res, Src2, One, Zero);
-      auto SelectCF   = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT);
-      SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(SelectCF);
-    }
-
-    // Signed
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(SelectCF);
    CalculateOF(SrcSize, Res, Src1, Src2, false);
  }
+
+  CalculatePF(Res);
+  return Res;
 }

-void OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
+OrderedNode *OpDispatchBuilder::CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Src1, OrderedNode *Src2) {
  auto Zero = _Constant(0);
  auto One = _Constant(1);
  auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;

-  CalculateAF(OpSize, Res, Src1, Src2);
-  CalculatePF(Res);
+  CalculateAF(Src1, Src2);

+  OrderedNode *Res;
  if (SrcSize >= 4) {
    // Rectify input carry
    CarryInvert();

-    if (NZCVDirty && CachedNZCV)
-      _StoreNZCV(CachedNZCV);
-    CachedNZCV = nullptr;
-    NZCVDirty = false;
-
-    _SbbNZCV(OpSize, Src1, Src2);
-    PossiblySetNZCVBits = ~0;
+    HandleNZCV_RMW();
+    Res = _SbbWithFlags(OpSize, Src1, Src2);

    // Rectify output carry
    CarryInvert();
  } else {
-    // SF/ZF
+    auto CF = GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC);
+    Res = _Sub(OpSize, Src1, _Add(OpSize, Src2, CF));
+    Res = _Bfe(OpSize, SrcSize * 8, 0, Res);
+
+    auto SelectOpLT = _Select(FEXCore::IR::COND_UGT, Res, Src1, One, Zero);
+    auto SelectOpLE = _Select(FEXCore::IR::COND_UGE, Res, Src1, One, Zero);
+    auto SelectCF   = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT);
+
    SetNZ_ZeroCV(SrcSize, Res);
-
-    // CF
-    // Unsigned
-    {
-      auto SelectOpLT = _Select(FEXCore::IR::COND_UGT, Res, Src1, One, Zero);
-      auto SelectOpLE = _Select(FEXCore::IR::COND_UGE, Res, Src1, One, Zero);
-      auto SelectCF   = _Select(FEXCore::IR::COND_EQ, CF, One, SelectOpLE, SelectOpLT);
-      SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(SelectCF);
-    }
-
-    // Signed
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(SelectCF);
    CalculateOF(SrcSize, Res, Src1, Src2, true);
  }
+
+  CalculatePF(Res);
+  return Res;
 }

-void OpDispatchBuilder::CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
-  auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
-
-  CalculateAF(OpSize, Res, Src1, Src2);
-  CalculatePF(Res);
-
+OrderedNode *OpDispatchBuilder::CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
  // Stash CF before stomping over it
  auto OldCF = UpdateCF ? nullptr : GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC);

-  // TODO: Could do this path for small sources if we have FEAT_FlagM
+  HandleNZCVWrite();
+
+  CalculateAF(Src1, Src2);
+
+  OrderedNode *Res;
  if (SrcSize >= 4) {
-    _SubNZCV(OpSize, Src1, Src2);
-    CachedNZCV = nullptr;
-    NZCVDirty = false;
-    PossiblySetNZCVBits = ~0;
-
-    // We only bother inverting CF if we're actually going to update CF.
-    if (UpdateCF)
-      CarryInvert();
+    Res = _SubWithFlags(IR::SizeToOpSize(SrcSize), Src1, Src2);
  } else {
-    // SF/ZF
-    SetNZ_ZeroCV(SrcSize, Res);
-
-    // CF
-    if (UpdateCF) {
-      // Grab carry bit from unmasked output.
-      SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Res, SrcSize * 8, true);
-    }
-
-    CalculateOF(SrcSize, Res, Src1, Src2, true);
+    _SubNZCV(IR::SizeToOpSize(SrcSize), Src1, Src2);
+    Res = _Sub(OpSize::i32Bit, Src1, Src2);
  }

+  CalculatePF(Res);
+
+  // If we're updating CF, we need to invert it for correctness. If we're not
+  // updating CF, we need to restore the CF since we stomped over it.
+  if (UpdateCF)
+    CarryInvert();
+  else
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(OldCF);
+
+  return Res;
+}
+
+OrderedNode *OpDispatchBuilder::CalculateFlags_ADD(uint8_t SrcSize, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
+  // Stash CF before stomping over it
+  auto OldCF = UpdateCF ? nullptr : GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC);
+
+  HandleNZCVWrite();
+
+  CalculateAF(Src1, Src2);
+
+  OrderedNode *Res;
+  if (SrcSize >= 4) {
+    Res = _AddWithFlags(IR::SizeToOpSize(SrcSize), Src1, Src2);
+  } else {
+    _AddNZCV(IR::SizeToOpSize(SrcSize), Src1, Src2);
+    Res = _Add(OpSize::i32Bit, Src1, Src2);
+  }
+
+  CalculatePF(Res);
+
  // We stomped over CF while calculation flags, restore it.
  if (!UpdateCF)
    SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(OldCF);
-}

-void OpDispatchBuilder::CalculateFlags_ADD(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
-  auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
-
-  CalculateAF(OpSize, Res, Src1, Src2);
-  CalculatePF(Res);
-
-  // Stash CF before stomping over it
-  auto OldCF = UpdateCF ? nullptr : GetRFLAG(FEXCore::X86State::RFLAG_CF_RAW_LOC);
-
-  // TODO: Could do this path for small sources if we have FEAT_FlagM
-  if (SrcSize >= 4) {
-    _AddNZCV(OpSize, Src1, Src2);
-    CachedNZCV = nullptr;
-    NZCVDirty = false;
-    PossiblySetNZCVBits = ~0;
-  } else {
-    // SF/ZF
-    SetNZ_ZeroCV(SrcSize, Res);
-
-    // CF
-    if (UpdateCF) {
-      // Grab carry bit from unmasked output
-      SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Res, SrcSize * 8, true);
-    }
-
-    CalculateOF(SrcSize, Res, Src1, Src2, false);
-  }
-
-  // We stomped over CF while calculation flags, restore it.
-  if (!UpdateCF)
-    SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(OldCF);
+  return Res;
 }

 void OpDispatchBuilder::CalculateFlags_MUL(uint8_t SrcSize, OrderedNode *Res, OrderedNode *High) {
+  HandleNZCVWrite();
+
  // PF/AF/ZF/SF
  // Undefined
  {
@@ -648,13 +541,12 @@ void OpDispatchBuilder::CalculateFlags_MUL(uint8_t SrcSize, OrderedNode *Res, Or
    // undefined, this does what we need.
    auto Zero = _Constant(0);
    _CondAddNZCV(OpSize::i64Bit, Zero, Zero, CondClassType{COND_EQ}, 0x3 /* nzCV */);
-    CachedNZCV = nullptr;
-    NZCVDirty = false;
-    PossiblySetNZCVBits = ~0;
  }
 }

 void OpDispatchBuilder::CalculateFlags_UMUL(OrderedNode *High) {
+  HandleNZCVWrite();
+
  auto Zero = _Constant(0);
  OpSize Size = IR::SizeToOpSize(GetOpSize(High));

@@ -674,9 +566,6 @@ void OpDispatchBuilder::CalculateFlags_UMUL(OrderedNode *High) {
    // If High = 0, then sets to nZcv. Else sets to nzCV. Since SF/ZF undefined,
    // this does what we need.
    _CondAddNZCV(Size, Zero, Zero, CondClassType{COND_EQ}, 0x3 /* nzCV */);
-    CachedNZCV = nullptr;
-    NZCVDirty = false;
-    PossiblySetNZCVBits = ~0;
  }
 }

@@ -817,8 +706,8 @@ void OpDispatchBuilder::CalculateFlags_SignShiftRightImmediate(uint8_t SrcSize,
 }

 void OpDispatchBuilder::CalculateFlags_ShiftRightImmediateCommon(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
-  // Stash OF before overwriting it
-  auto OldOF = Shift != 1 ? GetRFLAG(FEXCore::X86State::RFLAG_OF_RAW_LOC) : NULL;
+  // Set SF and PF. Clobbers OF, but OF only defined for Shift = 1 where it is
+  // set below.
  SetNZ_ZeroCV(SrcSize, Res);

  // CF
@@ -832,11 +721,6 @@ void OpDispatchBuilder::CalculateFlags_ShiftRightImmediateCommon(uint8_t SrcSize
  // AF
  // Undefined
  _InvalidateFlags(1 << X86State::RFLAG_AF_RAW_LOC);
-
-  // Preserve OF if it won't be written
-  if (Shift != 1) {
-    SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(OldOF);
-  }
 }

 void OpDispatchBuilder::CalculateFlags_ShiftRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
@@ -874,214 +758,66 @@ void OpDispatchBuilder::CalculateFlags_ShiftRightDoubleImmediate(uint8_t SrcSize
  }
 }

-void OpDispatchBuilder::CalculateFlags_RotateRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
-  CalculateFlags_ShiftVariable(Src2, [this, SrcSize, Res](){
-    auto SizeBits = SrcSize * 8;
-    const auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
-
-    // Ends up faster overall if we don't have FlagM, slower if we do...
-    // If Shift != 1, OF is undefined so we choose to zero here.
-    if (!CTX->HostFeatures.SupportsFlagM)
-      ZeroCV();
-
-    // Extract the last bit shifted in to CF
-    SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Res, SizeBits - 1, true);
-
-    // OF is set to the XOR of the new CF bit and the most significant bit of the result
-    // OF is architecturally only defined for 1-bit rotate, which is why this only happens when the shift is one.
-    auto NewOF = _XorShift(OpSize, Res, Res, ShiftType::LSR, 1);
-    SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(NewOF, SizeBits - 2, true);
-  });
-}
-
-void OpDispatchBuilder::CalculateFlags_RotateLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
-  CalculateFlags_ShiftVariable(Src2, [this, SrcSize, Res](){
-    const auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
-    auto SizeBits = SrcSize * 8;
-
-    // Ends up faster overall if we don't have FlagM, slower if we do...
-    // If Shift != 1, OF is undefined so we choose to zero here.
-    if (!CTX->HostFeatures.SupportsFlagM)
-      ZeroCV();
-
-    // Extract the last bit shifted in to CF
-    //auto Size = _Constant(GetSrcSize(Res) * 8);
-    //auto ShiftAmt = _Sub(OpSize::i64Bit, Size, Src2);
-    SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Res, 0, true);
-
-    // OF is the LSB and MSB XOR'd together.
-    // OF is set to the XOR of the new CF bit and the most significant bit of the result.
-    // OF is architecturally only defined for 1-bit rotate, which is why this only happens when the shift is one.
-    auto NewOF = _XorShift(OpSize, Res, Res, ShiftType::LSR, SizeBits - 1);
-    SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(NewOF, 0, true);
-  });
-}
-
-void OpDispatchBuilder::CalculateFlags_RotateRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
-  if (Shift == 0) return;
-
-  const auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
-  auto SizeBits = SrcSize * 8;
-
-  // Ends up faster overall if we don't have FlagM, slower if we do...
-  // If Shift != 1, OF is undefined so we choose to zero here.
-  if (!CTX->HostFeatures.SupportsFlagM)
-    ZeroCV();
-
-  // CF
-  {
-    // Extract the last bit shifted in to CF
-    SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Res, SizeBits - 1, true);
-  }
-
-  // OF
-  {
-    if (Shift == 1) {
-      // OF is the top two MSBs XOR'd together
-      // OF is architecturally only defined for 1-bit rotate, which is why this only happens when the shift is one.
-      auto NewOF = _XorShift(OpSize, Res, Res, ShiftType::LSR, 1);
-      SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(NewOF, SizeBits - 2, 1);
-    }
-  }
-}
-
-void OpDispatchBuilder::CalculateFlags_RotateLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
-  if (Shift == 0) return;
-
-  const auto OpSize = SrcSize == 8 ? OpSize::i64Bit : OpSize::i32Bit;
-  auto SizeBits = SrcSize * 8;
-
-  // Ends up faster overall if we don't have FlagM, slower if we do...
-  // If Shift != 1, OF is undefined so we choose to zero here.
-  if (!CTX->HostFeatures.SupportsFlagM)
-    ZeroCV();
-
-  // CF
-  {
-    // Extract the last bit shifted in to CF
-    SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Res, 0, true);
-  }
-
-  // OF
-  {
-    if (Shift == 1) {
-      // OF is the LSB and MSB XOR'd together.
-      // OF is set to the XOR of the new CF bit and the most significant bit of the result.
-      // OF is architecturally only defined for 1-bit rotate, which is why this only happens when the shift is one.
-      auto NewOF = _XorShift(OpSize, Res, Res, ShiftType::LSR, SizeBits - 1);
-
-      SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(NewOF, 0, true);
-    }
-  }
-}
-
 void OpDispatchBuilder::CalculateFlags_BEXTR(OrderedNode *Src) {
-  auto Zero = _Constant(0);
-  auto One = _Constant(1);
+  // ZF is set properly. CF and OF are defined as being set to zero. SF, PF, and
+  // AF are undefined.
+  SetNZ_ZeroCV(GetOpSize(Src), Src);

-  // Handle flag setting.
-  //
-  // All that matters primarily for this instruction is
-  // that we only set the ZF flag properly.
-  //
-  // CF and OF are defined as being set to zero
-  //
-  // Every other flag is considered undefined after a
-  // BEXTR instruction, but we opt to reliably clear them.
-  //
-  ZeroMultipleFlags(FullNZCVMask);
-
-  // PF/AF undefined
  _InvalidateFlags((1UL << X86State::RFLAG_PF_RAW_LOC) |
                   (1UL << X86State::RFLAG_AF_RAW_LOC));
-
-  // ZF
-  auto ZeroOp = _Select(IR::COND_EQ,
-                        Src, Zero,
-                        One, Zero);
-  SetRFLAG<X86State::RFLAG_ZF_RAW_LOC>(ZeroOp);
 }

-void OpDispatchBuilder::CalculateFlags_BLSI(uint8_t SrcSize, OrderedNode *Src) {
-  // Now for the flags:
+void OpDispatchBuilder::CalculateFlags_BLSI(uint8_t SrcSize, OrderedNode *Result) {
+  // CF is cleared if Src is zero, otherwise it's set. However, Src is zero iff
+  // Result is zero, so we can test the result instead. So, CF is just the
+  // inverted ZF.
  //
-  // Only CF, SF, ZF and OF are defined as being updated
-  // CF is cleared if Src is zero, otherwise it's set.
-  // SF is set to the value of the most significant operand bit of Result.
-  // OF is always cleared
-  // ZF is set, as usual, if Result is zero or not.
+  // ZF/SF/OF set as usual.
+  SetNZ_ZeroCV(SrcSize, Result);

-  auto Zero = _Constant(0);
-  auto One = _Constant(1);
-
-  SetNZ_ZeroCV(SrcSize, Src);
+  auto CFOp = GetRFLAG(X86State::RFLAG_ZF_RAW_LOC, true /* Invert */);
+  SetRFLAG<X86State::RFLAG_CF_RAW_LOC>(CFOp);

  // PF/AF undefined
  _InvalidateFlags((1UL << X86State::RFLAG_PF_RAW_LOC) |
                   (1UL << X86State::RFLAG_AF_RAW_LOC));
-
-
-  // CF
-  {
-    auto CFOp = _Select(IR::COND_NEQ, Src, Zero, One, Zero);
-    SetRFLAG<X86State::RFLAG_CF_RAW_LOC>(CFOp);
-  }
 }

-void OpDispatchBuilder::CalculateFlags_BLSMSK(OrderedNode *Src) {
-  // Now for the flags.
-
-  auto Zero = _Constant(0);
-  auto One = _Constant(1);
-
-  uint32_t FlagsMaskToZero =
-    (1U << X86State::RFLAG_ZF_RAW_LOC) |
-    (1U << X86State::RFLAG_OF_RAW_LOC);
-
-  ZeroMultipleFlags(FlagsMaskToZero);
-
+void OpDispatchBuilder::CalculateFlags_BLSMSK(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src) {
  // PF/AF undefined
  _InvalidateFlags((1UL << X86State::RFLAG_PF_RAW_LOC) |
                   (1UL << X86State::RFLAG_AF_RAW_LOC));

-  auto CFOp = _Select(IR::COND_NEQ, Src, Zero, One, Zero);
+  // CF set according to the Src
+  auto Zero = _Constant(0);
+  auto One = _Constant(1);
+  auto CFOp = _Select(IR::COND_EQ, Src, Zero, One, Zero);
+
+  // The output of BLSMSK is always nonzero, so TST will clear Z (along with C
+  // and O) while setting S.
+  SetNZ_ZeroCV(SrcSize, Result);
  SetRFLAG<X86State::RFLAG_CF_RAW_LOC>(CFOp);
 }

 void OpDispatchBuilder::CalculateFlags_BLSR(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src) {
-  // Now for flags.
  auto Zero = _Constant(0);
  auto One = _Constant(1);
+  auto CFOp = _Select(IR::COND_EQ, Src, Zero, One, Zero);

  SetNZ_ZeroCV(SrcSize, Result);
+  SetRFLAG<X86State::RFLAG_CF_RAW_LOC>(CFOp);

  // PF/AF undefined
  _InvalidateFlags((1UL << X86State::RFLAG_PF_RAW_LOC) |
                   (1UL << X86State::RFLAG_AF_RAW_LOC));
-
-  // CF
-  {
-    auto CFOp = _Select(IR::COND_NEQ, Src, Zero, One, Zero);
-    SetRFLAG<X86State::RFLAG_CF_RAW_LOC>(CFOp);
-  }
 }

-void OpDispatchBuilder::CalculateFlags_POPCOUNT(OrderedNode *Src) {
-  // Set ZF
-  auto Zero = _Constant(0);
-  auto ZFResult = _Select(FEXCore::IR::COND_EQ,
-      Src,  Zero,
-      _Constant(1), Zero);
-
-  // Set flags
-  uint32_t FlagsMaskToZero =
-    FullNZCVMask |
-    (1U << X86State::RFLAG_AF_RAW_LOC) |
-    (1U << X86State::RFLAG_PF_RAW_LOC);
-
-  ZeroMultipleFlags(FlagsMaskToZero);
-
-  SetRFLAG<FEXCore::X86State::RFLAG_ZF_RAW_LOC>(ZFResult);
+void OpDispatchBuilder::CalculateFlags_POPCOUNT(OrderedNode *Result) {
+  // We need to set ZF while clearing the rest of NZCV. The result of a popcount
+  // is in the range [0, 63]. In particular, it is always positive. So a
+  // combined NZ test will correctly zero SF/CF/OF while setting ZF.
+  SetNZ_ZeroCV(OpSize::i32Bit, Result);
+  ZeroPF_AF();
 }

 void OpDispatchBuilder::CalculateFlags_BZHI(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src) {
@@ -1093,45 +829,24 @@ void OpDispatchBuilder::CalculateFlags_BZHI(uint8_t SrcSize, OrderedNode *Result
  SetRFLAG<X86State::RFLAG_CF_RAW_LOC>(Src);
 }

-void OpDispatchBuilder::CalculateFlags_TZCNT(OrderedNode *Src) {
+void OpDispatchBuilder::CalculateFlags_ZCNT(uint8_t SrcSize, OrderedNode *Result) {
  // OF, SF, AF, PF all undefined
-  ZeroNZCV();
+  // Test ZF of result, SF is undefined so this is ok.
+  SetNZ_ZeroCV(SrcSize, Result);

-  auto Zero = _Constant(0);
-  auto ZFResult = _Select(FEXCore::IR::COND_EQ,
-      Src,  Zero,
-      _Constant(1), Zero);
-
-  // Set flags
-  SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(ZFResult);
-  SetRFLAG<FEXCore::X86State::RFLAG_ZF_RAW_LOC>(Src, 0, true);
-}
-
-void OpDispatchBuilder::CalculateFlags_LZCNT(uint8_t SrcSize, OrderedNode *Src) {
-  // OF, SF, AF, PF all undefined
-  ZeroNZCV();
-
-  auto Zero = _Constant(0);
-  auto ZFResult = _Select(FEXCore::IR::COND_EQ,
-      Src,  Zero,
-      _Constant(1), Zero);
-
-  // Set flags
-  SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(ZFResult);
-  SetRFLAG<FEXCore::X86State::RFLAG_ZF_RAW_LOC>(Src, SrcSize * 8 - 1, true);
+  // Now set CF if the Result = SrcSize * 8. Since SrcSize is a power-of-two and
+  // Result is <= SrcSize * 8, we equivalently check if the log2(SrcSize * 8)
+  // bit is set. No masking is needed because no higher bits could be set.
+  unsigned CarryBit = FEXCore::ilog2(SrcSize * 8u);
+  SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Result, CarryBit);
 }

 void OpDispatchBuilder::CalculateFlags_RDRAND(OrderedNode *Src) {
  // OF, SF, ZF, AF, PF all zero
+  ZeroNZCV();
+  ZeroPF_AF();
+
  // CF is set to the incoming source
-
-  uint32_t FlagsMaskToZero =
-    FullNZCVMask |
-    (1U << X86State::RFLAG_AF_RAW_LOC) |
-    (1U << X86State::RFLAG_PF_RAW_LOC);
-
-  ZeroMultipleFlags(FlagsMaskToZero);
-
  SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Src);
 }

@@ -13,7 +13,6 @@ $end_info$
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/LogManager.h>

 #include <array>
@@ -1104,7 +1103,7 @@ void OpDispatchBuilder::MOVMSKOpOne(OpcodeArgs) {
  const auto ExtractSize = Is256Bit ? 4 : 2;

  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
-  OrderedNode *VMask = _VDupFromGPR(SrcSize, 8, _Constant(0x80'40'20'10'08'04'02'01ULL));
+  OrderedNode *VMask = LoadAndCacheNamedVectorConstant(SrcSize, NAMED_VECTOR_MOVMASKB);

  auto VCMP = _VCMPLTZ(SrcSize, 1, Src);
  auto VAnd = _VAnd(SrcSize, 1, VCMP, VMask);
@@ -3001,16 +3000,15 @@ void OpDispatchBuilder::XSaveOp(OpcodeArgs) {
  XSaveOpImpl(Op);
 }

-void OpDispatchBuilder::XSaveOpImpl(OpcodeArgs) {
-  const auto XSaveBase = [this, Op] {
-    OrderedNode *Mem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.LoadData = false});
-    return AppendSegmentOffset(Mem, Op->Flags);
-  };
+OrderedNode *OpDispatchBuilder::XSaveBase(X86Tables::DecodedOp Op) {
+  OrderedNode *Mem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.LoadData = false});
+  return AppendSegmentOffset(Mem, Op->Flags);
+}

+void OpDispatchBuilder::XSaveOpImpl(OpcodeArgs) {
  // NOTE: Mask should be EAX and EDX concatenated, but we only need to test
  //       for features that are in the lower 32 bits, so EAX only is sufficient.
  OrderedNode *Mask = LoadGPRRegister(X86State::REG_RAX);
-  OrderedNode *Base = XSaveBase();
  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());

  const auto StoreIfFlagSet = [&](uint32_t BitIndex, auto fn, uint32_t FieldSize = 1){
@@ -3034,25 +3032,26 @@ void OpDispatchBuilder::XSaveOpImpl(OpcodeArgs) {

  // x87
  {
-    StoreIfFlagSet(0, [this, Op, Base] { SaveX87State(Op, Base); });
+    StoreIfFlagSet(0, [this, Op] { SaveX87State(Op, XSaveBase(Op)); });
  }
  // SSE
  {
-    StoreIfFlagSet(1, [this, Base] { SaveSSEState(Base); });
+    StoreIfFlagSet(1, [this, Op] { SaveSSEState(XSaveBase(Op)); });
  }
  // AVX
  if (CTX->HostFeatures.SupportsAVX)
  {
-    StoreIfFlagSet(2, [this, Base] { SaveAVXState(Base); });
+    StoreIfFlagSet(2, [this, Op] { SaveAVXState(XSaveBase(Op)); });
  }

  // We need to save MXCSR and MXCSR_MASK if either SSE or AVX are requested to be saved
  {
-    StoreIfFlagSet(1, [this, Base] { SaveMXCSRState(Base); }, 2);
+    StoreIfFlagSet(1, [this, Op] { SaveMXCSRState(XSaveBase(Op)); }, 2);
  }

  // Update XSTATE_BV region of the XSAVE header
  {
+    OrderedNode *Base = XSaveBase(Op);
    OrderedNode *HeaderOffset = _Add(OpSize, Base, _Constant(512));

    // NOTE: We currently only support the first 3 bits (x87, SSE, and AVX)
@@ -3210,14 +3209,11 @@ void OpDispatchBuilder::FXRStoreOp(OpcodeArgs) {
 void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) {
  const auto OpSize = IR::SizeToOpSize(CTX->GetGPRSize());

-  const auto XSaveBase = [this, Op] {
-    OrderedNode *Mem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.LoadData = false});
-    return AppendSegmentOffset(Mem, Op->Flags);
-  };
-
  // Set up base address for the XSAVE region to restore from, and also read the
  // XSTATE_BV bit flags out of the XSTATE header.
-  OrderedNode *Base = XSaveBase();
+  //
+  // Note: we rematerialize Base in each block to avoid crossblock liveness.
+  OrderedNode *Base = XSaveBase(Op);
  OrderedNode *Mask = _LoadMem(GPRClass, 8, _Add(OpSize, Base, _Constant(512)), 8);

  // If a bit in our XSTATE_BV is set, then we restore from that region of the XSAVE area,
@@ -3253,27 +3249,28 @@ void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) {
  // x87
  {
    RestoreIfFlagSetOrDefault(0,
-                              [this, Base] { RestoreX87State(Base); },
+                              [this, Op] { RestoreX87State(XSaveBase(Op)); },
                              [this, Op] { DefaultX87State(Op); });
  }
  // SSE
  {
    RestoreIfFlagSetOrDefault(1,
-                              [this, Base] { RestoreSSEState(Base); },
+                              [this, Op] { RestoreSSEState(XSaveBase(Op)); },
                              [this] { DefaultSSEState(); });
  }
  // AVX
  if (CTX->HostFeatures.SupportsAVX)
  {
    RestoreIfFlagSetOrDefault(2,
-                              [this, Base] { RestoreAVXState(Base); },
+                              [this, Op] { RestoreAVXState(XSaveBase(Op)); },
                              [this] { DefaultAVXState(); });
  }

  {
    // We need to restore the MXCSR if either SSE or AVX are requested to be saved
    RestoreIfFlagSetOrDefault(1,
-                              [this, Base, OpSize] {
+                              [this, Op, OpSize] {
+                                OrderedNode *Base = XSaveBase(Op);
                                OrderedNode *MXCSRLocation = _Add(OpSize, Base, _Constant(24));
                                OrderedNode *MXCSR = _LoadMem(GPRClass, 4, MXCSRLocation, 4);
                                RestoreMXCSRState(MXCSR);
@@ -3422,15 +3419,12 @@ void OpDispatchBuilder::VPALIGNROp(OpcodeArgs) {

 template<size_t ElementSize>
 void OpDispatchBuilder::UCOMISxOp(OpcodeArgs) {
-  InvalidateDeferredFlags();
-
  const auto SrcSize = Op->Src[0].IsGPR() ? GetGuestVectorLength() : GetSrcSize(Op);
  OrderedNode *Src1 = LoadSource_WithOpSize(FPRClass, Op, Op->Dest, GetGuestVectorLength(), Op->Flags);
  OrderedNode *Src2 = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags);

-  CachedNZCV = nullptr;
+  HandleNZCVWrite();
  _FCmp(ElementSize, Src1, Src2);
-  PossiblySetNZCVBits = ~0;
  ConvertNZCVToSSE();

  // Zero AF. Note that the comparison sets the raw PF to 0/1 above, so PF[4] is
@@ -4580,13 +4574,9 @@ void OpDispatchBuilder::PTestOp(OpcodeArgs) {
  OrderedNode *Test1 = _VAnd(Size, 1, Dest, Src);
  OrderedNode *Test2 = _VBic(Size, 1, Src, Dest);

-  Test1 = _VPopcount(Size, 1, Test1);
-  Test2 = _VPopcount(Size, 1, Test2);
-
-  // Element size doesn't matter here
-  // x86-64 doesn't support a horizontal byte add though
-  Test1 = _VAddV(Size, 2, Test1);
-  Test2 = _VAddV(Size, 2, Test2);
+  // Element size must be less than 32-bit for the sign bit tricks.
+  Test1 = _VUMaxV(Size, 2, Test1);
+  Test2 = _VUMaxV(Size, 2, Test2);

  Test1 = _VExtractToGPR(Size, 2, Test1, 0);
  Test2 = _VExtractToGPR(Size, 2, Test2, 0);
@@ -4594,22 +4584,17 @@ void OpDispatchBuilder::PTestOp(OpcodeArgs) {
  auto ZeroConst = _Constant(0);
  auto OneConst = _Constant(1);

-  Test1 = _Select(FEXCore::IR::COND_EQ,
-      Test1, ZeroConst, OneConst, ZeroConst);
-
  Test2 = _Select(FEXCore::IR::COND_EQ,
      Test2, ZeroConst, OneConst, ZeroConst);

  // Careful, these flags are different between {V,}PTEST and VTESTP{S,D}
-  ZeroNZCV();
-  SetRFLAG<FEXCore::X86State::RFLAG_ZF_RAW_LOC>(Test1);
+  // Set ZF according to Test1. SF will be zeroed since we do a 32-bit test on
+  // the results of a 16-bit value from the UMaxV, so the 32-bit sign bit is
+  // cleared even if the 16-bit scalars were negative.
+  SetNZ_ZeroCV(32, Test1);
  SetRFLAG<FEXCore::X86State::RFLAG_CF_RAW_LOC>(Test2);

-  uint32_t FlagsMaskToZero =
-    (1U << X86State::RFLAG_PF_RAW_LOC) |
-    (1U << X86State::RFLAG_AF_RAW_LOC);
-
-  ZeroMultipleFlags(FlagsMaskToZero);
+  ZeroPF_AF();
 }

 void OpDispatchBuilder::VTESTOpImpl(OpcodeArgs, size_t ElementSize) {
@@ -4630,33 +4615,23 @@ void OpDispatchBuilder::VTESTOpImpl(OpcodeArgs, size_t ElementSize) {
  OrderedNode *MaskedAnd = _VAnd(SrcSize, 1, AndTest, Mask);
  OrderedNode *MaskedAndNot = _VAnd(SrcSize, 1, AndNotTest, Mask);

-  OrderedNode *AndPopCount = _VPopcount(SrcSize, 1, MaskedAnd);
-  OrderedNode *AndNotPopCount = _VPopcount(SrcSize, 1, MaskedAndNot);
+  OrderedNode *MaxAnd = _VUMaxV(SrcSize, 2, MaskedAnd);
+  OrderedNode *MaxAndNot = _VUMaxV(SrcSize, 2, MaskedAndNot);

-  OrderedNode *SummedAnd = _VAddV(SrcSize, 2, AndPopCount);
-  OrderedNode *SummedAndNot = _VAddV(SrcSize, 2, AndNotPopCount);
-
-  OrderedNode *AndGPR = _VExtractToGPR(SrcSize, 2, SummedAnd, 0);
-  OrderedNode *AndNotGPR = _VExtractToGPR(SrcSize, 2, SummedAndNot, 0);
+  OrderedNode *AndGPR = _VExtractToGPR(SrcSize, 2, MaxAnd, 0);
+  OrderedNode *AndNotGPR = _VExtractToGPR(SrcSize, 2, MaxAndNot, 0);

  OrderedNode *ZeroConst = _Constant(0);
  OrderedNode *OneConst = _Constant(1);

-  OrderedNode *ZFResult = _Select(IR::COND_EQ, AndGPR, ZeroConst,
-                                  OneConst, ZeroConst);
  OrderedNode *CFResult = _Select(IR::COND_EQ, AndNotGPR, ZeroConst,
                                  OneConst, ZeroConst);

-  SetRFLAG<X86State::RFLAG_ZF_RAW_LOC>(ZFResult);
+  // As in PTest, this sets Z appropriately while zeroing the rest of NZCV.
+  SetNZ_ZeroCV(32, AndGPR);
  SetRFLAG<X86State::RFLAG_CF_RAW_LOC>(CFResult);

-  uint32_t FlagsMaskToZero =
-    (1U << X86State::RFLAG_PF_RAW_LOC) |
-    (1U << X86State::RFLAG_AF_RAW_LOC) |
-    (1U << X86State::RFLAG_SF_RAW_LOC) |
-    (1U << X86State::RFLAG_OF_RAW_LOC);
-
-  ZeroMultipleFlags(FlagsMaskToZero);
+  ZeroPF_AF();
 }

 template <size_t ElementSize>
@@ -5588,11 +5563,7 @@ void OpDispatchBuilder::PCMPXSTRXOpImpl(OpcodeArgs, bool IsExplicit, bool IsMask
  SetRFLAG<X86State::RFLAG_CF_RAW_LOC>(GetFlagBit(18));
  SetRFLAG<X86State::RFLAG_OF_RAW_LOC>(GetFlagBit(19));

-  uint32_t FlagsMaskToZero =
-    (1U << X86State::RFLAG_PF_RAW_LOC) |
-    (1U << X86State::RFLAG_AF_RAW_LOC);
-
-  ZeroMultipleFlags(FlagsMaskToZero);
+  ZeroPF_AF();
 }

 void OpDispatchBuilder::VPCMPESTRIOp(OpcodeArgs) {
@@ -14,7 +14,6 @@ $end_info$
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/FPState.h>
-#include <FEXCore/IR/IREmitter.h>

 #include <stddef.h>
 #include <stdint.h>
@@ -13,7 +13,6 @@ $end_info$
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/IR/IREmitter.h>

 #include <stddef.h>
 #include <stdint.h>
@@ -12,51 +12,16 @@ $end_info$

 namespace FEXCore::X86Tables {

-std::array<X86InstInfo, MAX_PRIMARY_TABLE_SIZE> BaseOps{};
-std::array<X86InstInfo, MAX_SECOND_TABLE_SIZE> SecondBaseOps{};
-std::array<X86InstInfo, MAX_REP_MOD_TABLE_SIZE> RepModOps{};
-std::array<X86InstInfo, MAX_REPNE_MOD_TABLE_SIZE> RepNEModOps{};
-std::array<X86InstInfo, MAX_OPSIZE_MOD_TABLE_SIZE> OpSizeModOps{};
-
-std::array<X86InstInfo, MAX_INST_GROUP_TABLE_SIZE> PrimaryInstGroupOps{};
-std::array<X86InstInfo, MAX_INST_SECOND_GROUP_TABLE_SIZE> SecondInstGroupOps{};
-std::array<X86InstInfo, MAX_SECOND_MODRM_TABLE_SIZE> SecondModRMTableOps{};
-std::array<X86InstInfo, MAX_X87_TABLE_SIZE> X87Ops{};
-std::array<X86InstInfo, MAX_3DNOW_TABLE_SIZE> DDDNowOps{};
-std::array<X86InstInfo, MAX_0F_38_TABLE_SIZE> H0F38TableOps{};
-std::array<X86InstInfo, MAX_0F_3A_TABLE_SIZE> H0F3ATableOps{};
-std::array<X86InstInfo, MAX_VEX_TABLE_SIZE> VEXTableOps{};
-std::array<X86InstInfo, MAX_VEX_GROUP_TABLE_SIZE> VEXTableGroupOps{};
-std::array<X86InstInfo, MAX_XOP_TABLE_SIZE> XOPTableOps{};
-std::array<X86InstInfo, MAX_XOP_GROUP_TABLE_SIZE> XOPTableGroupOps{};
-std::array<X86InstInfo, MAX_EVEX_TABLE_SIZE> EVEXTableOps{};
-
 void InitializeBaseTables(Context::OperatingMode Mode);
 void InitializeSecondaryTables(Context::OperatingMode Mode);
 void InitializePrimaryGroupTables(Context::OperatingMode Mode);
-void InitializeSecondaryGroupTables();
-void InitializeSecondaryModRMTables();
-void InitializeX87Tables();
-void InitializeDDDTables();
-void InitializeH0F38Tables();
 void InitializeH0F3ATables(Context::OperatingMode Mode);
-void InitializeVEXTables();
-void InitializeXOPTables();
-void InitializeEVEXTables();

 void InitializeInfoTables(Context::OperatingMode Mode) {
  InitializeBaseTables(Mode);
  InitializeSecondaryTables(Mode);
  InitializePrimaryGroupTables(Mode);
-  InitializeSecondaryGroupTables();
-  InitializeSecondaryModRMTables();
-  InitializeX87Tables();
-  InitializeDDDTables();
-  InitializeH0F38Tables();
  InitializeH0F3ATables(Mode);
-  InitializeVEXTables();
-  InitializeXOPTables();
-  InitializeEVEXTables();
 }

 }
@@ -14,8 +14,10 @@ $end_info$
 namespace FEXCore::X86Tables {
 using namespace InstFlags;

-void InitializeBaseTables(Context::OperatingMode Mode) {
-  static constexpr U8U8InfoStruct BaseOpTable[] = {
+std::array<X86InstInfo, MAX_PRIMARY_TABLE_SIZE> BaseOps = []() consteval {
+  std::array<X86InstInfo, MAX_PRIMARY_TABLE_SIZE> Table{};
+
+  constexpr U8U8InfoStruct BaseOpTable[] = {
    // Prefixes
    // Operand size overide
    {0x66, 1, X86InstInfo{"",      TYPE_PREFIX, FLAGS_NONE,        0, nullptr}},
@@ -233,6 +235,12 @@ void InitializeBaseTables(Context::OperatingMode Mode) {
    {0xC4, 2, X86InstInfo{"",   TYPE_VEX_TABLE_PREFIX, FLAGS_NONE, 0, nullptr}},
  };

+  GenerateTable(&Table.at(0), BaseOpTable, std::size(BaseOpTable));
+
+  return Table;
+}();
+
+void InitializeBaseTables(Context::OperatingMode Mode) {
  static constexpr U8U8InfoStruct BaseOpTable_64[] = {
    {0x06, 2, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                     0, nullptr}},
    {0x0E, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                     0, nullptr}},
@@ -291,8 +299,6 @@ void InitializeBaseTables(Context::OperatingMode Mode) {
    {0xEA, 1, X86InstInfo{"JMPF",   TYPE_INST, FLAGS_NONE,                                                        0, nullptr}},
  };

-  GenerateTable(&BaseOps.at(0), BaseOpTable, std::size(BaseOpTable));
-
  if (Mode == Context::MODE_64BIT) {
    GenerateTable(&BaseOps.at(0), BaseOpTable_64, std::size(BaseOpTable_64));
  }
@@ -12,8 +12,9 @@ $end_info$
 namespace FEXCore::X86Tables {
 using namespace InstFlags;

-void InitializeDDDTables() {
-  static constexpr U8U8InfoStruct DDDNowOpTable[] = {
+std::array<X86InstInfo, MAX_3DNOW_TABLE_SIZE> DDDNowOps = []() consteval {
+  std::array<X86InstInfo, MAX_3DNOW_TABLE_SIZE> Table{};
+  constexpr U8U8InfoStruct DDDNowOpTable[] = {
    {0x0C, 1, X86InstInfo{"PI2FW",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
    {0x0D, 1, X86InstInfo{"PI2FD",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
    {0x1C, 1, X86InstInfo{"PF2IW",    TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
@@ -52,6 +53,8 @@ void InitializeDDDTables() {
    {0xBF, 1, X86InstInfo{"PAVGUSB",  TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
  };

-  GenerateTable(&DDDNowOps.at(0), DDDNowOpTable, std::size(DDDNowOpTable));
-}
+  GenerateTable(&Table.at(0), DDDNowOpTable, std::size(DDDNowOpTable));
+  return Table;
+}();
+
 }
@@ -11,9 +11,9 @@ $end_info$

 namespace FEXCore::X86Tables {
 using namespace InstFlags;
-
-void InitializeEVEXTables() {
-  static constexpr U16U8InfoStruct EVEXTable[] = {
+std::array<X86InstInfo, MAX_EVEX_TABLE_SIZE> EVEXTableOps = []() consteval {
+  std::array<X86InstInfo, MAX_EVEX_TABLE_SIZE> Table{};
+  constexpr U16U8InfoStruct EVEXTable[] = {
    {0x10, 1, X86InstInfo{"VMOVUPS",         TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
    {0x11, 1, X86InstInfo{"VMOVUPS",         TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
    {0x18, 1, X86InstInfo{"VBROADCASTSS",    TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
@@ -29,6 +29,9 @@ void InitializeEVEXTables() {
    {0xE7, 1, X86InstInfo{"VMOVNTDQ",        TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
  };

-  GenerateTable(&EVEXTableOps.at(0), EVEXTable, std::size(EVEXTable));
-}
+  GenerateTable(&Table.at(0), EVEXTable, std::size(EVEXTable));
+
+  return Table;
+}();
+
 }
@@ -12,15 +12,16 @@ $end_info$

 namespace FEXCore::X86Tables {
 using namespace InstFlags;
+std::array<X86InstInfo, MAX_0F_38_TABLE_SIZE> H0F38TableOps = []() consteval {
+  std::array<X86InstInfo, MAX_0F_38_TABLE_SIZE> Table{};

-void InitializeH0F38Tables() {
 #define OPD(prefix, opcode) (((prefix) << 8) | opcode)
  constexpr uint16_t PF_38_NONE = 0;
  constexpr uint16_t PF_38_66   = (1U << 0);
  constexpr uint16_t PF_38_F2   = (1U << 1);
  constexpr uint16_t PF_38_F3   = (1U << 2);

-  static constexpr U16U8InfoStruct H0F38Table[] = {
+  constexpr U16U8InfoStruct H0F38Table[] = {
    {OPD(PF_38_NONE, 0x00), 1, X86InstInfo{"PSHUFB",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
    {OPD(PF_38_66,   0x00), 1, X86InstInfo{"PSHUFB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
    {OPD(PF_38_NONE, 0x01), 1, X86InstInfo{"PHADDW",     TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
@@ -117,6 +118,8 @@ void InitializeH0F38Tables() {
  };
 #undef OPD

-  GenerateTable(&H0F38TableOps.at(0), H0F38Table, std::size(H0F38Table));
-}
+  GenerateTable(&Table.at(0), H0F38Table, std::size(H0F38Table));
+  return Table;
+}();
+
 }
@@ -14,13 +14,13 @@ $end_info$

 namespace FEXCore::X86Tables {
 using namespace InstFlags;
-
-void InitializeH0F3ATables(Context::OperatingMode Mode) {
 #define OPD(REX, prefix, opcode) ((REX << 9) | (prefix << 8) | opcode)
-  constexpr uint16_t PF_3A_NONE = 0;
-  constexpr uint16_t PF_3A_66   = 1;
+constexpr uint16_t PF_3A_NONE = 0;
+constexpr uint16_t PF_3A_66   = 1;

-  static constexpr U16U8InfoStruct H0F3ATable[] = {
+std::array<X86InstInfo, MAX_0F_3A_TABLE_SIZE> H0F3ATableOps = []() consteval {
+  std::array<X86InstInfo, MAX_0F_3A_TABLE_SIZE> Table{};
+  constexpr U16U8InfoStruct H0F3ATable[] = {
    {OPD(0, PF_3A_NONE, 0x0F), 1, X86InstInfo{"PALIGNR",         TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
    {OPD(0, PF_3A_66,   0x08), 1, X86InstInfo{"ROUNDPS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
    {OPD(0, PF_3A_66,   0x09), 1, X86InstInfo{"ROUNDPD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
@@ -54,6 +54,11 @@ void InitializeH0F3ATables(Context::OperatingMode Mode) {
    {OPD(0, PF_3A_66,   0xDF), 1, X86InstInfo{"AESKEYGENASSIST", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
  };

+  GenerateTable(&Table.at(0), H0F3ATable, std::size(H0F3ATable));
+  return Table;
+}();
+
+void InitializeH0F3ATables(Context::OperatingMode Mode) {
  static constexpr U16U8InfoStruct H0F3ATable_64[] = {
    {OPD(1, PF_3A_66,   0x0F), 1, X86InstInfo{"PALIGNR",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
    {OPD(1, PF_3A_66,   0x16), 1, X86InstInfo{"PEXTRQ",          TYPE_INST, GenFlagsSizes(SIZE_64BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
@@ -62,8 +67,6 @@ void InitializeH0F3ATables(Context::OperatingMode Mode) {

 #undef OPD

-  GenerateTable(&H0F3ATableOps.at(0), H0F3ATable, std::size(H0F3ATable));
-
  if (Mode == Context::MODE_64BIT) {
    GenerateTable(&H0F3ATableOps.at(0), H0F3ATable_64, std::size(H0F3ATable_64));
  }
@@ -13,10 +13,10 @@ $end_info$

 namespace FEXCore::X86Tables {
 using namespace InstFlags;
-
-void InitializePrimaryGroupTables(Context::OperatingMode Mode) {
+std::array<X86InstInfo, MAX_INST_GROUP_TABLE_SIZE> PrimaryInstGroupOps = []() consteval {
+  std::array<X86InstInfo, MAX_INST_GROUP_TABLE_SIZE> Table{};
 #define OPD(group, prefix, Reg) (((group - FEXCore::X86Tables::TYPE_GROUP_1) << 6) | (prefix) << 3 | (Reg))
-  const U16U8InfoStruct PrimaryGroupOpTable[] = {
+  constexpr U16U8InfoStruct PrimaryGroupOpTable[] = {
    // GROUP_1 | 0x80 | reg
    {OPD(TYPE_GROUP_1, OpToIndex(0x80), 0), 1, X86InstInfo{"ADD",  TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                      1, nullptr}},
    {OPD(TYPE_GROUP_1, OpToIndex(0x80), 1), 1, X86InstInfo{"OR",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST,                                      1, nullptr}},
@@ -141,9 +141,13 @@ void InitializePrimaryGroupTables(Context::OperatingMode Mode) {
    {OPD(TYPE_GROUP_11, OpToIndex(0xC7), 0), 1, X86InstInfo{"MOV",  TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2,                                   4, nullptr}},
    {OPD(TYPE_GROUP_11, OpToIndex(0xC7), 1), 5, X86InstInfo{"",     TYPE_INVALID, FLAGS_NONE,                                                       0, nullptr}},
    {OPD(TYPE_GROUP_11, OpToIndex(0xC7), 7), 1, X86InstInfo{"XBEGIN", TYPE_INST, FLAGS_MODRM | FLAGS_SRC_SEXT | FLAGS_SETS_RIP | FLAGS_DISPLACE_SIZE_DIV_2,                                                       4, nullptr}},
-
  };

+  GenerateTable(&Table.at(0), PrimaryGroupOpTable, std::size(PrimaryGroupOpTable));
+  return Table;
+}();
+
+void InitializePrimaryGroupTables(Context::OperatingMode Mode) {
  const U16U8InfoStruct PrimaryGroupOpTable_64[] = {
    // Invalid in 64bit mode
    {OPD(TYPE_GROUP_1, OpToIndex(0x82), 0), 8, X86InstInfo{"",     TYPE_INVALID, FLAGS_NONE,                                                        0, nullptr}},
@@ -163,7 +167,6 @@ void InitializePrimaryGroupTables(Context::OperatingMode Mode) {

 #undef OPD

-  GenerateTable(&PrimaryInstGroupOps.at(0), PrimaryGroupOpTable, std::size(PrimaryGroupOpTable));
  if (Mode == Context::MODE_64BIT) {
    GenerateTable(&PrimaryInstGroupOps.at(0), PrimaryGroupOpTable_64, std::size(PrimaryGroupOpTable_64));
  }
@@ -12,15 +12,15 @@ $end_info$

 namespace FEXCore::X86Tables {
 using namespace InstFlags;
-
-void InitializeSecondaryGroupTables() {
+std::array<X86InstInfo, MAX_INST_SECOND_GROUP_TABLE_SIZE> SecondInstGroupOps = []() consteval {
+  std::array<X86InstInfo, MAX_INST_SECOND_GROUP_TABLE_SIZE> Table{};
 #define OPD(group, prefix, Reg) (((group - FEXCore::X86Tables::TYPE_GROUP_6) << 5) | (prefix) << 3 | (Reg))
  constexpr uint16_t PF_NONE = 0;
  constexpr uint16_t PF_F3   = 1;
  constexpr uint16_t PF_66   = 2;
  constexpr uint16_t PF_F2   = 3;

-  static constexpr U16U8InfoStruct SecondaryExtensionOpTable[] = {
+  constexpr U16U8InfoStruct SecondaryExtensionOpTable[] = {
    // GROUP 1
    // GROUP 2
    // GROUP 3
@@ -162,7 +162,7 @@ void InitializeSecondaryGroupTables() {
    {OPD(TYPE_GROUP_9, PF_F3, 4), 1, X86InstInfo{"",           TYPE_INVALID, FLAGS_NONE,     0, nullptr}},
    {OPD(TYPE_GROUP_9, PF_F3, 5), 1, X86InstInfo{"",           TYPE_INVALID, FLAGS_NONE,     0, nullptr}},
    {OPD(TYPE_GROUP_9, PF_F3, 6), 1, X86InstInfo{"",           TYPE_INVALID, FLAGS_NONE,     0, nullptr}},
-    {OPD(TYPE_GROUP_9, PF_F3, 7), 1, X86InstInfo{"RDPID",      TYPE_INVALID, FLAGS_NONE,     0, nullptr}},
+    {OPD(TYPE_GROUP_9, PF_F3, 7), 1, X86InstInfo{"RDPID",      TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_REG_ONLY, 0, nullptr}},

    {OPD(TYPE_GROUP_9, PF_66, 0), 1, X86InstInfo{"",           TYPE_INVALID, FLAGS_NONE,     0, nullptr}},
    {OPD(TYPE_GROUP_9, PF_66, 1), 1, X86InstInfo{"CMPXCHG8B/16B", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_MEM_ONLY, 0, nullptr}},
@@ -487,7 +487,8 @@ void InitializeSecondaryGroupTables() {
  };
 #undef OPD

-  GenerateTable(&SecondInstGroupOps.at(0), SecondaryExtensionOpTable, std::size(SecondaryExtensionOpTable));
-}
+  GenerateTable(&Table.at(0), SecondaryExtensionOpTable, std::size(SecondaryExtensionOpTable));
+  return Table;
+}();

 }
@@ -11,9 +11,9 @@ $end_info$

 namespace FEXCore::X86Tables {
 using namespace InstFlags;
-
-void InitializeSecondaryModRMTables() {
-  static constexpr U8U8InfoStruct SecondaryModRMExtensionOpTable[] = {
+std::array<X86InstInfo, MAX_SECOND_MODRM_TABLE_SIZE> SecondModRMTableOps = []() consteval {
+  std::array<X86InstInfo, MAX_SECOND_MODRM_TABLE_SIZE> Table{};
+  constexpr U8U8InfoStruct SecondaryModRMExtensionOpTable[] = {
    // REG /1
    {((0 << 3) | 0), 1, X86InstInfo{"MONITOR",  TYPE_PRIV,    FLAGS_NONE, 0, nullptr}},
    {((0 << 3) | 1), 1, X86InstInfo{"MWAIT",    TYPE_PRIV,    FLAGS_NONE, 0, nullptr}},
@@ -55,6 +55,8 @@ void InitializeSecondaryModRMTables() {
    {((3 << 3) | 7), 1, X86InstInfo{"",         TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
  };

-  GenerateTable(&SecondModRMTableOps.at(0), SecondaryModRMExtensionOpTable, std::size(SecondaryModRMExtensionOpTable));
-}
+  GenerateTable(&Table.at(0), SecondaryModRMExtensionOpTable, std::size(SecondaryModRMExtensionOpTable));
+  return Table;
+}();
+
 }
@@ -13,9 +13,10 @@ $end_info$

 namespace FEXCore::X86Tables {
 using namespace InstFlags;
+auto BaseOpsLambda = []() consteval {
+  std::array<X86InstInfo, MAX_SECOND_TABLE_SIZE> Table{};

-void InitializeSecondaryTables(Context::OperatingMode Mode) {
-  static constexpr U8U8InfoStruct TwoByteOpTable[] = {
+  constexpr U8U8InfoStruct TwoByteOpTable[] = {
    // Instructions
    {0x00, 1, X86InstInfo{"",           TYPE_GROUP_6, FLAGS_MODRM | FLAGS_NO_OVERLAY,                                                                                 0, nullptr}},
    {0x01, 1, X86InstInfo{"",           TYPE_GROUP_7, FLAGS_NO_OVERLAY,                                                                                 0, nullptr}},
@@ -166,11 +167,13 @@ void InitializeSecondaryTables(Context::OperatingMode Mode) {
    {0x9E, 1, X86InstInfo{"SETLE",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_NO_OVERLAY,                        0, nullptr}},
    {0x9F, 1, X86InstInfo{"SETNLE",  TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_NO_OVERLAY,                        0, nullptr}},

+    {0xA0, 2, X86InstInfo{"",        TYPE_COPY_OTHER, FLAGS_NONE,                                     0, nullptr}},
    {0xA2, 1, X86InstInfo{"CPUID",   TYPE_INST,     FLAGS_SF_SRC_RAX | FLAGS_NO_OVERLAY,                                              0, nullptr}},
    {0xA3, 1, X86InstInfo{"BT",      TYPE_INST,     FLAGS_DEBUG_MEM_ACCESS | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_NO_OVERLAY,                     0, nullptr}},
    {0xA4, 1, X86InstInfo{"SHLD",    TYPE_INST,     FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_NO_OVERLAY,                                              1, nullptr}},
    {0xA5, 1, X86InstInfo{"SHLD",    TYPE_INST,     FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_SRC_RCX | FLAGS_NO_OVERLAY,                           0, nullptr}},
    {0xA6, 2, X86InstInfo{"",        TYPE_INVALID,  FLAGS_NO_OVERLAY,                                                                               0, nullptr}},
+    {0xA8, 2, X86InstInfo{"",        TYPE_COPY_OTHER, FLAGS_NONE,                                     0, nullptr}},
    {0xAA, 1, X86InstInfo{"RSM",     TYPE_PRIV,     FLAGS_NO_OVERLAY,                                                                               0, nullptr}},
    {0xAB, 1, X86InstInfo{"BTS",     TYPE_INST,     FLAGS_DEBUG_MEM_ACCESS | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_NO_OVERLAY,                     0, nullptr}},
    {0xAC, 1, X86InstInfo{"SHRD",    TYPE_INST,     FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_NO_OVERLAY,                                              1, nullptr}},
@@ -265,23 +268,16 @@ void InitializeSecondaryTables(Context::OperatingMode Mode) {
    {0x3F, 1, X86InstInfo{"ALTINST",      TYPE_INST, FLAGS_BLOCK_END | FLAGS_NO_OVERLAY | FLAGS_SETS_RIP,                                                            0, nullptr}},
  };

-  static constexpr U8U8InfoStruct TwoByteOpTable_32[] = {
-    {0xA0, 1, X86InstInfo{"PUSH FS", TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                                               0, nullptr}},
-    {0xA1, 1, X86InstInfo{"POP FS",  TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_DEF) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                                               0, nullptr}},
+  GenerateTable(&Table.at(0), TwoByteOpTable, std::size(TwoByteOpTable));

-    {0xA8, 1, X86InstInfo{"PUSH GS", TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                                               0, nullptr}},
-    {0xA9, 1, X86InstInfo{"POP GS",  TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_DEF) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                                               0, nullptr}},
-  };
+  return Table;
+};

-  static constexpr U8U8InfoStruct TwoByteOpTable_64[] = {
-    {0xA0, 1, X86InstInfo{"PUSH FS", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                0, nullptr}},
-    {0xA1, 1, X86InstInfo{"POP FS",  TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_64BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                0, nullptr}},
+std::array<X86InstInfo, MAX_SECOND_TABLE_SIZE> SecondBaseOps = BaseOpsLambda();
+std::array<X86InstInfo, MAX_REP_MOD_TABLE_SIZE> RepModOps = []() consteval {
+  std::array<X86InstInfo, MAX_REP_MOD_TABLE_SIZE> Table{};

-    {0xA8, 1, X86InstInfo{"PUSH GS", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                0, nullptr}},
-    {0xA9, 1, X86InstInfo{"POP GS",  TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_64BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                0, nullptr}},
-  };
-
-  static constexpr U8U8InfoStruct RepModOpTable[] = {
+  constexpr U8U8InfoStruct RepModOpTable[] = {
    {0x0, 16, X86InstInfo{"",          TYPE_COPY_OTHER, FLAGS_NONE,                                     0, nullptr}},

    {0x10, 1, X86InstInfo{"MOVSS",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,                    0, nullptr}},
@@ -361,7 +357,15 @@ void InitializeSecondaryTables(Context::OperatingMode Mode) {
    {0xFF, 1, X86InstInfo{"",          TYPE_COPY_OTHER, FLAGS_NONE,                                     0, nullptr}},
  };

-  static constexpr U8U8InfoStruct RepNEModOpTable[] = {
+  GenerateTableWithCopy(&Table.at(0), RepModOpTable, std::size(RepModOpTable), &BaseOpsLambda().at(0));
+
+  return Table;
+}();
+
+std::array<X86InstInfo, MAX_REPNE_MOD_TABLE_SIZE> RepNEModOps = []() consteval {
+  std::array<X86InstInfo, MAX_REPNE_MOD_TABLE_SIZE> Table{};
+
+  constexpr U8U8InfoStruct RepNEModOpTable[] = {
    {0x0, 16, X86InstInfo{"",           TYPE_COPY_OTHER, FLAGS_NONE,                                                     0, nullptr}},

    {0x10, 1, X86InstInfo{"MOVSD",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,                  0, nullptr}},
@@ -434,7 +438,15 @@ void InitializeSecondaryTables(Context::OperatingMode Mode) {
    {0xF8, 8, X86InstInfo{"",          TYPE_INVALID, FLAGS_NONE,                                                         0, nullptr}},
  };

-  static constexpr U8U8InfoStruct OpSizeModOpTable[] = {
+  GenerateTableWithCopy(&Table.at(0), RepNEModOpTable,   std::size(RepNEModOpTable), &BaseOpsLambda().at(0));
+
+  return Table;
+}();
+
+std::array<X86InstInfo, MAX_OPSIZE_MOD_TABLE_SIZE> OpSizeModOps = []() consteval {
+  std::array<X86InstInfo, MAX_OPSIZE_MOD_TABLE_SIZE> Table{};
+
+  constexpr U8U8InfoStruct OpSizeModOpTable[] = {
    {0x0, 16, X86InstInfo{"",           TYPE_COPY_OTHER, FLAGS_NONE,                                                            0, nullptr}},

    {0x10, 1, X86InstInfo{"MOVUPD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,                         0, nullptr}},
@@ -581,19 +593,40 @@ void InitializeSecondaryTables(Context::OperatingMode Mode) {
    {0xFF, 1, X86InstInfo{"",           TYPE_COPY_OTHER, FLAGS_NONE,                                                            0, nullptr}},
  };

-  GenerateTable(&SecondBaseOps.at(0), TwoByteOpTable, std::size(TwoByteOpTable));
+  GenerateTableWithCopy(&Table.at(0), OpSizeModOpTable, std::size(OpSizeModOpTable), &BaseOpsLambda().at(0));
+
+  return Table;
+}();
+
+void InitializeSecondaryTables(Context::OperatingMode Mode) {
+  static constexpr U8U8InfoStruct TwoByteOpTable_32[] = {
+    {0xA0, 1, X86InstInfo{"PUSH FS", TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                                               0, nullptr}},
+    {0xA1, 1, X86InstInfo{"POP FS",  TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_DEF) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                                               0, nullptr}},
+
+    {0xA8, 1, X86InstInfo{"PUSH GS", TYPE_INST, GenFlagsSrcSize(SIZE_16BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                                               0, nullptr}},
+    {0xA9, 1, X86InstInfo{"POP GS",  TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_DEF) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                                               0, nullptr}},
+  };
+
+  static constexpr U8U8InfoStruct TwoByteOpTable_64[] = {
+    {0xA0, 1, X86InstInfo{"PUSH FS", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                0, nullptr}},
+    {0xA1, 1, X86InstInfo{"POP FS",  TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_64BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                0, nullptr}},
+
+    {0xA8, 1, X86InstInfo{"PUSH GS", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                0, nullptr}},
+    {0xA9, 1, X86InstInfo{"POP GS",  TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_64BIT) | FLAGS_DEBUG_MEM_ACCESS | FLAGS_NO_OVERLAY,                                                0, nullptr}},
+  };

  if (Mode == Context::MODE_64BIT) {
-    GenerateTable(&SecondBaseOps.at(0), TwoByteOpTable_64, std::size(TwoByteOpTable_64));
+    LateInitCopyTable(&SecondBaseOps.at(0), TwoByteOpTable_64, std::size(TwoByteOpTable_64));
+    LateInitCopyTable(&RepModOps.at(0), TwoByteOpTable_64, std::size(TwoByteOpTable_64));
+    LateInitCopyTable(&RepNEModOps.at(0), TwoByteOpTable_64, std::size(TwoByteOpTable_64));
+    LateInitCopyTable(&OpSizeModOps.at(0), TwoByteOpTable_64, std::size(TwoByteOpTable_64));
  }
  else {
-    GenerateTable(&SecondBaseOps.at(0), TwoByteOpTable_32, std::size(TwoByteOpTable_32));
+    LateInitCopyTable(&SecondBaseOps.at(0), TwoByteOpTable_32, std::size(TwoByteOpTable_32));
+    LateInitCopyTable(&RepModOps.at(0), TwoByteOpTable_32, std::size(TwoByteOpTable_32));
+    LateInitCopyTable(&RepNEModOps.at(0), TwoByteOpTable_32, std::size(TwoByteOpTable_32));
+    LateInitCopyTable(&OpSizeModOps.at(0), TwoByteOpTable_32, std::size(TwoByteOpTable_32));
  }
-
-  GenerateTableWithCopy(&RepModOps.at(0), RepModOpTable, std::size(RepModOpTable), &SecondBaseOps.at(0));
-  GenerateTableWithCopy(&RepNEModOps.at(0), RepNEModOpTable,   std::size(RepNEModOpTable), &SecondBaseOps.at(0));
-  GenerateTableWithCopy(&OpSizeModOps.at(0), OpSizeModOpTable, std::size(OpSizeModOpTable), &SecondBaseOps.at(0));
-
 }

 }
@@ -11,10 +11,10 @@ $end_info$

 namespace FEXCore::X86Tables {
 using namespace InstFlags;
-
-void InitializeVEXTables() {
+std::array<X86InstInfo, MAX_VEX_TABLE_SIZE> VEXTableOps = []() consteval {
+  std::array<X86InstInfo, MAX_VEX_TABLE_SIZE> Table{};
 #define OPD(map_select, pp, opcode) (((map_select - 1) << 10) | (pp << 8) | (opcode))
-  static constexpr U16U8InfoStruct VEXTable[] = {
+  constexpr U16U8InfoStruct VEXTable[] = {
    // Map 0 (Reserved)
    // VEX Map 1
    {OPD(1, 0b00, 0x10), 1, X86InstInfo{"VMOVUPS",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
@@ -488,8 +488,15 @@ void InitializeVEXTables() {
  };
 #undef OPD

+  GenerateTable(&Table.at(0), VEXTable, std::size(VEXTable));
+  return Table;
+}();
+
+std::array<X86InstInfo, MAX_VEX_GROUP_TABLE_SIZE> VEXTableGroupOps = []() consteval {
+  std::array<X86InstInfo, MAX_VEX_GROUP_TABLE_SIZE> Table{};
+
 #define OPD(group, pp, opcode) (((group - TYPE_VEX_GROUP_12) << 4) | (pp << 3) | (opcode))
-  static constexpr U8U8InfoStruct VEXGroupTable[] = {
+  constexpr U8U8InfoStruct VEXGroupTable[] = {
    {OPD(TYPE_VEX_GROUP_12, 1, 0b010), 1, X86InstInfo{"VPSRLW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
    {OPD(TYPE_VEX_GROUP_12, 1, 0b100), 1, X86InstInfo{"VPSRAW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
    {OPD(TYPE_VEX_GROUP_12, 1, 0b110), 1, X86InstInfo{"VPSLLW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_DST | FLAGS_XMM_FLAGS, 1, nullptr}},
@@ -512,7 +519,8 @@ void InitializeVEXTables() {
  };
 #undef OPD

-  GenerateTable(&VEXTableOps.at(0), VEXTable, std::size(VEXTable));
-  GenerateTable(&VEXTableGroupOps.at(0), VEXGroupTable, std::size(VEXGroupTable));
-}
+  GenerateTable(&Table.at(0), VEXGroupTable, std::size(VEXGroupTable));
+
+  return Table;
+}();
 }
@@ -507,26 +507,30 @@ using U8U8InfoStruct = X86TablesInfoStruct<uint8_t>;
 using U16U8InfoStruct = X86TablesInfoStruct<uint16_t>;

 template<typename OpcodeType>
-static inline void GenerateTable(X86InstInfo *FinalTable, X86TablesInfoStruct<OpcodeType> const *LocalTable, size_t TableSize) {
+constexpr static inline void GenerateTable(X86InstInfo *FinalTable, X86TablesInfoStruct<OpcodeType> const *LocalTable, size_t TableSize) {
  for (size_t j = 0; j < TableSize; ++j) {
    X86TablesInfoStruct<OpcodeType> const &Op = LocalTable[j];
    auto OpNum = Op.first;
    X86InstInfo const &Info = Op.Info;
    for (uint32_t i = 0; i < Op.second; ++i) {
-      LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
+      if (FinalTable[OpNum + i].Type != TYPE_UNKNOWN) {
+        ERROR_AND_DIE_FMT("Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
+      }
      FinalTable[OpNum + i] = Info;
    }
  }
 };

 template<typename OpcodeType>
-static inline void GenerateTableWithCopy(X86InstInfo *FinalTable, X86TablesInfoStruct<OpcodeType> const *LocalTable, size_t TableSize, X86InstInfo *OtherLocal) {
+constexpr static inline void GenerateTableWithCopy(X86InstInfo *FinalTable, X86TablesInfoStruct<OpcodeType> const *LocalTable, size_t TableSize, X86InstInfo *OtherLocal) {
  for (size_t j = 0; j < TableSize; ++j) {
    X86TablesInfoStruct<OpcodeType> const &Op = LocalTable[j];
    auto OpNum = Op.first;
    X86InstInfo const &Info = Op.Info;
    for (uint32_t i = 0; i < Op.second; ++i) {
-      LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
+      if (FinalTable[OpNum + i].Type != TYPE_UNKNOWN) {
+        ERROR_AND_DIE_FMT("Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
+      }
      if (Info.Type == TYPE_COPY_OTHER) {
        FinalTable[OpNum + i] = OtherLocal[OpNum + i];
      }
@@ -538,13 +542,30 @@ static inline void GenerateTableWithCopy(X86InstInfo *FinalTable, X86TablesInfoS
 };

 template<typename OpcodeType>
-static inline void GenerateX87Table(X86InstInfo *FinalTable, X86TablesInfoStruct<OpcodeType> const *LocalTable, size_t TableSize) {
+static inline void LateInitCopyTable(X86InstInfo *FinalTable, X86TablesInfoStruct<OpcodeType> const *OtherLocal, size_t OtherTableSize) {
+  for (size_t j = 0; j < OtherTableSize; ++j) {
+    X86TablesInfoStruct<OpcodeType> const &OtherOp = OtherLocal[j];
+    auto OtherOpNum = OtherOp.first;
+    X86InstInfo const &OtherInfo = OtherOp.Info;
+    for (uint32_t i = 0; i < OtherOp.second; ++i) {
+      X86InstInfo &FinalOp = FinalTable[OtherOpNum + i];
+      if (FinalOp.Type == TYPE_COPY_OTHER) {
+        FinalOp = OtherInfo;
+      }
+    }
+  }
+}
+
+template<typename OpcodeType>
+constexpr static inline void GenerateX87Table(X86InstInfo *FinalTable, X86TablesInfoStruct<OpcodeType> const *LocalTable, size_t TableSize) {
  for (size_t j = 0; j < TableSize; ++j) {
    X86TablesInfoStruct<OpcodeType> const &Op = LocalTable[j];
    auto OpNum = Op.first;
    X86InstInfo const &Info = Op.Info;
    for (uint32_t i = 0; i < Op.second; ++i) {
-      LOGMAN_THROW_AA_FMT(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
+      if (FinalTable[OpNum + i].Type != TYPE_UNKNOWN) {
+        ERROR_AND_DIE_FMT("Duplicate Entry {}->{}", FinalTable[OpNum + i].Name, Info.Name);
+      }
      if ((OpNum & 0b11'000'000) == 0b11'000'000) {
        // If the mod field is 0b11 then it is a regular op
        FinalTable[OpNum + i] = Info;
@@ -552,7 +573,9 @@ static inline void GenerateX87Table(X86InstInfo *FinalTable, X86TablesInfoStruct
      else {
        // If the mod field is !0b11 then this instruction is duplicated through the whole mod [0b00, 0b10] range
        // and the modrm.rm space because that is used part of the instruction encoding
-        LOGMAN_THROW_AA_FMT((OpNum & 0b11'000'000) == 0, "Only support mod field of zero in this path");
+        if ((OpNum & 0b11'000'000) != 0) {
+          ERROR_AND_DIE_FMT("Only support mod field of zero in this path");
+        }
        for (uint16_t mod = 0b00'000'000; mod < 0b11'000'000; mod += 0b01'000'000) {
          for (uint16_t rm = 0b000; rm < 0b1'000; ++rm) {
            FinalTable[(OpNum | mod | rm) + i] = Info;
@@ -11,11 +11,11 @@ $end_info$

 namespace FEXCore::X86Tables {
 using namespace InstFlags;
-
-void InitializeX87Tables() {
+std::array<X86InstInfo, MAX_X87_TABLE_SIZE> X87Ops = []() consteval {
+  std::array<X86InstInfo, MAX_X87_TABLE_SIZE> Table{};
 #define OPD(op, modrmop) (((op - 0xD8) << 8) | modrmop)
 #define OPDReg(op, reg) (((op - 0xD8) << 8) | (reg << 3))
-  static constexpr U16U8InfoStruct X87OpTable[] = {
+  constexpr U16U8InfoStruct X87OpTable[] = {
    // 0xD8
    {OPDReg(0xD8, 0), 1, X86InstInfo{"FADD",  TYPE_X87, FLAGS_MODRM, 0, nullptr}},
    {OPDReg(0xD8, 1), 1, X86InstInfo{"FMUL",  TYPE_X87, FLAGS_MODRM, 0, nullptr}},
@@ -263,6 +263,8 @@ void InitializeX87Tables() {
 #undef OPD
 #undef OPDReg

-  GenerateX87Table(&X87Ops.at(0), X87OpTable, std::size(X87OpTable));
-}
+  GenerateX87Table(&Table.at(0), X87OpTable, std::size(X87OpTable));
+  return Table;
+}();
+
 }
@@ -12,14 +12,14 @@ $end_info$

 namespace FEXCore::X86Tables {
 using namespace InstFlags;
-
-void InitializeXOPTables() {
+std::array<X86InstInfo, MAX_XOP_TABLE_SIZE> XOPTableOps = []() consteval {
+  std::array<X86InstInfo, MAX_XOP_TABLE_SIZE> Table{};
 #define OPD(group, pp, opcode) ( (group << 10) | (pp << 8) | (opcode))
  constexpr uint16_t XOP_GROUP_8 = 0;
  constexpr uint16_t XOP_GROUP_9 = 1;
  constexpr uint16_t XOP_GROUP_A = 2;

-  static constexpr U16U8InfoStruct XOPTable[] = {
+  constexpr U16U8InfoStruct XOPTable[] = {
    // Group 8
    {OPD(XOP_GROUP_8, 0, 0x85), 1, X86InstInfo{"VPMAXSSWW",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
    {OPD(XOP_GROUP_8, 0, 0x86), 1, X86InstInfo{"VPMACSSWD",  TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
@@ -104,8 +104,15 @@ void InitializeXOPTables() {
  };
 #undef OPD

+  GenerateTable(&Table.at(0), XOPTable, std::size(XOPTable));
+
+  return Table;
+}();
+
+std::array<X86InstInfo, MAX_XOP_GROUP_TABLE_SIZE> XOPTableGroupOps = []() consteval {
+  std::array<X86InstInfo, MAX_XOP_GROUP_TABLE_SIZE> Table{};
 #define OPD(subgroup, opcode)  (((subgroup - 1) << 3) | (opcode))
-  static constexpr U8U8InfoStruct XOPGroupTable[] = {
+  constexpr U8U8InfoStruct XOPGroupTable[] = {
    // Group 1
    {OPD(1, 1), 1, X86InstInfo{"BLCFILL",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
    {OPD(1, 2), 1, X86InstInfo{"BLSFILL",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
@@ -129,7 +136,8 @@ void InitializeXOPTables() {
  };
 #undef OPD

-  GenerateTable(&XOPTableOps.at(0), XOPTable, std::size(XOPTable));
-  GenerateTable(&XOPTableGroupOps.at(0), XOPGroupTable, std::size(XOPGroupTable));
-}
+  GenerateTable(&Table.at(0), XOPGroupTable, std::size(XOPGroupTable));
+  return Table;
+}();
+
 }
@@ -6,12 +6,13 @@ tags: glue|thunks
 $end_info$
 */

+#include "Interface/IR/IR.h"
+#include "Interface/IR/IREmitter.h"
+
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/LogManager.h>
-#include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
 #include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/fextl/set.h>
 #include <FEXCore/fextl/string.h>
@@ -180,6 +181,9 @@ namespace FEXCore {
            Thread->CurrentFrame->State.gregs[FEXCore::X86State::REG_RDI] = (uintptr_t)arg0;
            Thread->CurrentFrame->State.gregs[FEXCore::X86State::REG_RSI] = (uintptr_t)arg1;
          } else {
+            if ((reinterpret_cast<uintptr_t>(arg1) >> 32) != 0) {
+              ERROR_AND_DIE_FMT("Tried to call guest function with arguments packed to a 64-bit address");
+            }
            Thread->CurrentFrame->State.gregs[FEXCore::X86State::REG_RCX] = (uintptr_t)arg0;
            Thread->CurrentFrame->State.gregs[FEXCore::X86State::REG_RDX] = (uintptr_t)arg1;
          }
@@ -216,7 +220,7 @@ namespace FEXCore {
            LogMan::Msg::DFmt("Thunks: Adding guest trampoline from address {:#x} to guest function {:#x}",
                              args->original_callee, args->target_addr);

-            auto Result = Thread->CTX->AddCustomIREntrypoint(
+            auto Result = CTX->AddCustomIREntrypoint(
                    args->original_callee,
                    [CTX, GuestThunkEntrypoint = args->target_addr](uintptr_t Entrypoint, FEXCore::IR::IREmitter *emit) {
                        auto IRHeader = emit->_IRHeader(emit->Invalid(), Entrypoint, 0, 0);
@@ -483,6 +487,26 @@ namespace FEXCore {
      }
    }

+    FEX_DEFAULT_VISIBILITY void* GetGuestStack() {
+      if (!Thread) {
+        ERROR_AND_DIE_FMT("Thunked library attempted to query guest stack pointer asynchronously");
+      }
+
+      return (void*)(uintptr_t)((Thread->CurrentFrame->State.gregs[FEXCore::X86State::REG_RSP]));
+    }
+
+    FEX_DEFAULT_VISIBILITY void MoveGuestStack(uintptr_t NewAddress) {
+      if (!Thread) {
+        ERROR_AND_DIE_FMT("Thunked library attempted to query guest stack pointer asynchronously");
+      }
+
+      if (NewAddress >> 32) {
+         ERROR_AND_DIE_FMT("Tried to set stack pointer for 32-bit guest to a 64-bit address");
+      }
+
+      Thread->CurrentFrame->State.gregs[FEXCore::X86State::REG_RSP] = NewAddress;
+    }
+
 #else
    fextl::unique_ptr<ThunkHandler> ThunkHandler::Create() {
      ERROR_AND_DIE_FMT("Unsupported");
@@ -7,7 +7,8 @@ $end_info$

 #pragma once

-#include <FEXCore/IR/IR.h>
+#include "Interface/IR/IR.h"
+
 #include <FEXCore/fextl/memory.h>
 #include <FEXCore/fextl/vector.h>

@@ -2,9 +2,9 @@
 #include "FEXHeaderUtils/Filesystem.h"
 #include "Interface/Context/Context.h"
 #include "Interface/IR/AOTIR.h"
+#include "Interface/IR/IntrusiveIRList.h"
+#include "Interface/IR/RegisterAllocationData.h"

-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/fextl/fmt.h>
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: MIT
 #pragma once

-#include "FEXCore/IR/RegisterAllocationData.h"
+#include "Interface/IR/RegisterAllocationData.h"
+
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/fextl/map.h>
 #include <FEXCore/fextl/string.h>
@@ -0,0 +1,636 @@
+// SPDX-License-Identifier: MIT
+#pragma once
+
+#include <FEXCore/Utils/ThreadPoolAllocator.h>
+#include <FEXCore/IR/IR.h>
+
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/sstream.h>
+
+namespace FEXCore::IR {
+
+class OrderedNode;
+class RegisterAllocationPass;
+class RegisterAllocationData;
+
+/**
+ * @brief The IROp_Header is an dynamically sized array
+ * At the end it contains a uint8_t for the number of arguments that Op has
+ * Then there is an unsized array of NodeWrapper arguments for the number of arguments this op has
+ * The op structures that are including the header must ensure that they pad themselves correctly to the number of arguments used
+ */
+struct IROp_Header;
+
+/**
+ * @brief Represents the ID of a given IR node.
+ *
+ * Intended to provide strong typing from other integer values
+ * to prevent passing incorrect values to certain API functions.
+ */
+struct NodeID final {
+  using value_type = uint32_t;
+
+  constexpr NodeID() noexcept = default;
+  constexpr explicit NodeID(value_type Value_) noexcept : Value{Value_} {}
+
+  constexpr NodeID(const NodeID&) noexcept = default;
+  constexpr NodeID& operator=(const NodeID&) noexcept = default;
+
+  constexpr NodeID(NodeID&&) noexcept = default;
+  constexpr NodeID& operator=(NodeID&&) noexcept = default;
+
+  [[nodiscard]] constexpr bool IsValid() const noexcept {
+    return Value != 0;
+  }
+  [[nodiscard]] constexpr bool IsInvalid() const noexcept {
+    return !IsValid();
+  }
+  constexpr void Invalidate() noexcept {
+    Value = 0;
+  }
+
+  [[nodiscard]] friend constexpr bool operator==(NodeID, NodeID) noexcept = default;
+
+  [[nodiscard]] friend constexpr bool operator<(NodeID lhs, NodeID rhs) noexcept {
+    return lhs.Value < rhs.Value;
+  }
+  [[nodiscard]] friend constexpr bool operator>(NodeID lhs, NodeID rhs) noexcept {
+    return operator<(rhs, lhs);
+  }
+  [[nodiscard]] friend constexpr bool operator<=(NodeID lhs, NodeID rhs) noexcept {
+    return !operator>(lhs, rhs);
+  }
+  [[nodiscard]] friend constexpr bool operator>=(NodeID lhs, NodeID rhs) noexcept {
+    return !operator<(lhs, rhs);
+  }
+
+  friend std::ostream& operator<<(std::ostream& out, NodeID ID) {
+    out << ID.Value;
+    return out;
+  }
+  friend std::istream& operator>>(std::istream& in, NodeID& ID) {
+    in >> ID.Value;
+    return in;
+  }
+
+  value_type Value{};
+};
+
+/**
+ * @brief This is a very simple wrapper for our node pointers
+ * You probably don't want to use this directly
+ * Use OpNodeWrapper and OrderedNodeWrapper types below instead
+ *
+ * This is necessary to allow two things
+ *  - Reduce memory usage by having the pointer be an 32bit offset rather than the whole 64bit pointer
+ *  - Actually use an offset from a base so we aren't storing pointers for everything
+ *    - Makes IR list copying be as cheap as a memcpy
+ * Downsides
+ *  - The IR nodes have to be allocated out of a linear array of memory
+ *  - We currently only allow a 32bit offset, so *only* 4 million nodes per list
+ *  - We have to have the base offset live somewhere else
+ *  - Has to be POD and trivially copyable
+ *  - Makes every real node access turn in to a [Base + Offset] access
+ *  - Can be confusing if you're mixing OpNodeWrapper and OrderedNodeWrapper usage
+ */
+template<typename Type>
+struct NodeWrapperBase final {
+  // On x86-64 using a uint64_t type is more efficient since RIP addressing gives you [<Base> + <Index> + <imm offset>]
+  // On AArch64 using uint32_t is just more memory efficient. 32bit or 64bit offset doesn't matter
+  // We use uint32_t to be more memory efficient (Cuts our node list size in half)
+  using NodeOffsetType = uint32_t;
+  NodeOffsetType NodeOffset;
+
+  explicit NodeWrapperBase() = default;
+
+  [[nodiscard]] static NodeWrapperBase WrapOffset(NodeOffsetType Offset) {
+    NodeWrapperBase Wrapped;
+    Wrapped.NodeOffset = Offset;
+    return Wrapped;
+  }
+
+  [[nodiscard]] static NodeWrapperBase WrapPtr(uintptr_t Base, uintptr_t Value) {
+    NodeWrapperBase Wrapped;
+    Wrapped.SetOffset(Base, Value);
+    return Wrapped;
+  }
+
+  [[nodiscard]] static void *UnwrapNode(uintptr_t Base, NodeWrapperBase Node) {
+    return Node.GetNode(Base);
+  }
+
+  [[nodiscard]] NodeID ID() const;
+
+  [[nodiscard]] bool IsInvalid() const { return NodeOffset == 0; }
+
+  [[nodiscard]] Type *GetNode(uintptr_t Base) {
+    return reinterpret_cast<Type*>(Base + NodeOffset);
+  }
+  [[nodiscard]] const Type *GetNode(uintptr_t Base) const {
+    return reinterpret_cast<const Type*>(Base + NodeOffset);
+  }
+
+  void SetOffset(uintptr_t Base, uintptr_t Value) { NodeOffset = Value - Base; }
+
+  [[nodiscard]] friend constexpr bool operator==(const NodeWrapperBase<Type>&, const NodeWrapperBase<Type>&) = default;
+};
+
+static_assert(std::is_trivial_v<NodeWrapperBase<OrderedNode>>);
+
+static_assert(sizeof(NodeWrapperBase<OrderedNode>) == sizeof(uint32_t));
+
+using OpNodeWrapper = NodeWrapperBase<IROp_Header>;
+using OrderedNodeWrapper = NodeWrapperBase<OrderedNode>;
+
+struct OrderedNodeHeader {
+  OpNodeWrapper Value;
+  OrderedNodeWrapper Next;
+  OrderedNodeWrapper Previous;
+};
+
+static_assert(sizeof(OrderedNodeHeader) == sizeof(uint32_t) * 3);
+
+/**
+ * @brief This is a node in our IR representation
+ * Is a doubly linked list node that lives in a representation of a linearly allocated node list
+ * The links in the nodes can live in a list independent of the data IR data
+ *
+ * ex.
+ *  Region1 : ... <-> <OrderedNode> <-> <OrderedNode> <-> ...
+ *                    | *<Value>        |
+ *                    v                 v
+ *  Region2 : <IROp>..<IROp>..<IROp>..<IROp>
+ *
+ *  In this example the OrderedNodes are allocated in one linear memory region (Not necessarily contiguous with one another linking)
+ *  The second region is contiguous but they don't have any relationship with one another directly
+ */
+class OrderedNode final {
+  friend class NodeWrapperIterator;
+  friend class OrderedList;
+  public:
+    // These three values are laid out very specifically to make it fast to access the NodeWrappers specifically
+    OrderedNodeHeader Header;
+    uint32_t NumUses;
+
+    using value_type              = OrderedNodeWrapper;
+
+    OrderedNode() = default;
+
+    /**
+     * @brief Appends a node to this current node
+     *
+     * Before. <Prev> <-> <Current> <-> <Next>
+     * After.  <Prev> <-> <Current> <-> <Node> <-> Next
+     *
+     * @return Pointer to the node being added
+     */
+    value_type append(uintptr_t Base, value_type Node) {
+      // Set Next Node's Previous to incoming node
+      SetPrevious(Base, Header.Next, Node);
+
+      // Set Incoming node's links to this node's links
+      SetPrevious(Base, Node, Wrapped(Base));
+      SetNext(Base, Node, Header.Next);
+
+      // Set this node's next to the incoming node
+      SetNext(Base, Wrapped(Base), Node);
+
+      // Return the node we are appending
+      return Node;
+    }
+
+    OrderedNode *append(uintptr_t Base, OrderedNode *Node) {
+      value_type WNode = Node->Wrapped(Base);
+      // Set Next Node's Previous to incoming node
+      SetPrevious(Base, Header.Next, WNode);
+
+      // Set Incoming node's links to this node's links
+      SetPrevious(Base, WNode, Wrapped(Base));
+      SetNext(Base, WNode, Header.Next);
+
+      // Set this node's next to the incoming node
+      SetNext(Base, Wrapped(Base), WNode);
+
+      // Return the node we are appending
+      return Node;
+    }
+
+    /**
+     * @brief Prepends a node to the current node
+     * Before. <Prev> <-> <Current> <-> <Next>
+     * After.  <Prev> <-> <Node> <-> <Current> <-> Next
+     *
+     * @return Pointer to the node being added
+     */
+    value_type prepend(uintptr_t Base, value_type Node) {
+      // Set the previous node's next to the incoming node
+      SetNext(Base, Header.Previous, Node);
+
+      // Set the incoming node's links
+      SetPrevious(Base, Node, Header.Previous);
+      SetNext(Base, Node, Wrapped(Base));
+
+      // Set the current node's link
+      SetPrevious(Base, Wrapped(Base), Node);
+
+      // Return the node we are prepending
+      return Node;
+    }
+
+    OrderedNode *prepend(uintptr_t Base, OrderedNode *Node) {
+      value_type WNode = Node->Wrapped(Base);
+      // Set the previous node's next to the incoming node
+      SetNext(Base, Header.Previous, WNode);
+
+      // Set the incoming node's links
+      SetPrevious(Base, WNode, Header.Previous);
+      SetNext(Base, WNode, Wrapped(Base));
+
+      // Set the current node's link
+      SetPrevious(Base, Wrapped(Base), WNode);
+
+      // Return the node we are prepending
+      return Node;
+    }
+
+    /**
+     * @brief Gets the remaining size of the blocks from this point onward
+     *
+     * Doesn't find the head of the list
+     *
+     */
+    [[nodiscard]] size_t size(uintptr_t Base) const {
+      size_t Size = 1;
+      // Walk the list forward until we hit a sentinel
+      value_type Current = Header.Next;
+      while (Current.NodeOffset != 0) {
+        ++Size;
+        OrderedNode *RealNode = Current.GetNode(Base);
+        Current = RealNode->Header.Next;
+      }
+      return Size;
+    }
+
+    void Unlink(uintptr_t Base) {
+      // This removes the node from the list. Orphaning it
+      // Before: <Previous> <-> <Current> <-> <Next>
+      // After: <Previous <-> <Next>
+      SetNext(Base, Header.Previous, Header.Next);
+      SetPrevious(Base, Header.Next, Header.Previous);
+    }
+
+    [[nodiscard]] IROp_Header const* Op(uintptr_t Base) const {
+      return Header.Value.GetNode(Base);
+    }
+    [[nodiscard]] IROp_Header *Op(uintptr_t Base) {
+      return Header.Value.GetNode(Base);
+    }
+
+    [[nodiscard]] uint32_t GetUses() const { return NumUses; }
+
+    void AddUse() { ++NumUses; }
+    void RemoveUse() { --NumUses; }
+
+    [[nodiscard]] value_type Wrapped(uintptr_t Base) const {
+      value_type Tmp;
+      Tmp.SetOffset(Base, reinterpret_cast<uintptr_t>(this));
+      return Tmp;
+    }
+
+  private:
+    [[nodiscard]] value_type WrappedOffset(uint32_t Offset) const {
+      value_type Tmp;
+      Tmp.NodeOffset = Offset;
+      return Tmp;
+    }
+
+    static void SetPrevious(uintptr_t Base, value_type Node, value_type New) {
+      OrderedNode *RealNode = Node.GetNode(Base);
+      RealNode->Header.Previous = New;
+    }
+
+    static void SetNext(uintptr_t Base, value_type Node, value_type New) {
+      OrderedNode *RealNode = Node.GetNode(Base);
+      RealNode->Header.Next = New;
+    }
+
+    void SetUses(uint32_t Uses) { NumUses = Uses; }
+};
+
+static_assert(std::is_trivial_v<OrderedNode>);
+static_assert(std::is_trivially_copyable_v<OrderedNode>);
+static_assert(offsetof(OrderedNode, Header) == 0);
+static_assert(sizeof(OrderedNode) == (sizeof(OrderedNodeHeader) + sizeof(uint32_t)));
+
+struct RegisterClassType final {
+  using value_type = uint32_t;
+
+  value_type Val;
+  [[nodiscard]] constexpr operator value_type() const {
+    return Val;
+  }
+  [[nodiscard]] friend constexpr bool operator==(const RegisterClassType&, const RegisterClassType&) = default;
+};
+
+struct CondClassType final {
+  uint8_t Val;
+  [[nodiscard]] constexpr operator uint8_t() const {
+    return Val;
+  }
+  [[nodiscard]] friend constexpr bool operator==(const CondClassType&, const CondClassType&) = default;
+};
+
+struct MemOffsetType final {
+  uint8_t Val;
+  [[nodiscard]] constexpr operator uint8_t() const {
+    return Val;
+  }
+  [[nodiscard]] friend constexpr bool operator==(const MemOffsetType&, const MemOffsetType&) = default;
+};
+
+struct TypeDefinition final {
+  uint16_t Val;
+
+  [[nodiscard]] constexpr operator uint16_t() const {
+    return Val;
+  }
+
+  [[nodiscard]] static constexpr TypeDefinition Create(uint8_t Bytes) {
+    TypeDefinition Type{};
+    Type.Val = Bytes << 8;
+    return Type;
+  }
+
+  [[nodiscard]] static constexpr TypeDefinition Create(uint8_t Bytes, uint8_t Elements) {
+    TypeDefinition Type{};
+    Type.Val = (Bytes << 8) | (Elements & 255);
+    return Type;
+  }
+
+  [[nodiscard]] constexpr uint8_t Bytes() const {
+    return Val >> 8;
+  }
+
+  [[nodiscard]] constexpr uint8_t Elements() const {
+    return Val & 255;
+  }
+
+  [[nodiscard]] friend constexpr bool operator==(const TypeDefinition&, const TypeDefinition&) = default;
+};
+
+static_assert(std::is_trivial_v<TypeDefinition>);
+
+struct FenceType final {
+  using value_type = uint8_t;
+
+  value_type Val;
+  [[nodiscard]] constexpr operator value_type() const {
+    return Val;
+  }
+  [[nodiscard]] friend constexpr bool operator==(const FenceType&, const FenceType&) = default;
+};
+
+struct RoundType final {
+  uint8_t Val;
+  [[nodiscard]] constexpr operator uint8_t() const {
+    return Val;
+  }
+  [[nodiscard]] friend constexpr bool operator==(const RoundType&, const RoundType&) = default;
+};
+
+class NodeIterator;
+
+/* This iterator can be used to step though nodes.
+ * Due to how our IR is laid out, this can be used to either step
+ * though the CodeBlocks or though the code within a single block.
+ */
+class NodeIterator {
+public:
+  using value_type              = std::tuple<OrderedNode*, IROp_Header*>;
+  using size_type               = std::size_t;
+  using difference_type         = std::ptrdiff_t;
+  using reference               = value_type&;
+  using const_reference         = const value_type&;
+  using pointer                 = value_type*;
+  using const_pointer           = const value_type*;
+  using iterator                = NodeIterator;
+  using const_iterator          = const NodeIterator;
+  using reverse_iterator        = iterator;
+  using const_reverse_iterator  = const_iterator;
+  using iterator_category       = std::bidirectional_iterator_tag;
+
+  NodeIterator(uintptr_t Base, uintptr_t IRBase) : BaseList {Base}, IRList{ IRBase } {}
+  explicit NodeIterator(uintptr_t Base, uintptr_t IRBase, OrderedNodeWrapper Ptr) : BaseList {Base},  IRList{ IRBase }, Node {Ptr} {}
+
+  [[nodiscard]] bool operator==(const NodeIterator &rhs) const {
+    return Node.NodeOffset == rhs.Node.NodeOffset;
+  }
+
+  [[nodiscard]] bool operator!=(const NodeIterator &rhs) const {
+    return !operator==(rhs);
+  }
+
+  NodeIterator operator++() {
+    OrderedNodeHeader *RealNode = reinterpret_cast<OrderedNodeHeader*>(Node.GetNode(BaseList));
+    Node = RealNode->Next;
+    return *this;
+  }
+
+  NodeIterator operator--() {
+    OrderedNodeHeader *RealNode = reinterpret_cast<OrderedNodeHeader*>(Node.GetNode(BaseList));
+    Node = RealNode->Previous;
+    return *this;
+  }
+
+  [[nodiscard]] value_type operator*() {
+    OrderedNode *RealNode = Node.GetNode(BaseList);
+    return { RealNode, RealNode->Op(IRList) };
+  }
+
+  [[nodiscard]] value_type operator()() {
+    OrderedNode *RealNode = Node.GetNode(BaseList);
+    return { RealNode, RealNode->Op(IRList) };
+  }
+
+  [[nodiscard]] NodeID ID() const {
+    return Node.ID();
+  }
+
+  [[nodiscard]] static NodeIterator Invalid() {
+    return NodeIterator(0, 0);
+  }
+
+protected:
+  uintptr_t BaseList{};
+  uintptr_t IRList{};
+  OrderedNodeWrapper Node{};
+};
+
+// This must directly match bytes to the named opsize.
+// Implicit sized IR operations does math to get between sizes.
+enum OpSize : uint8_t {
+  i8Bit = 1,
+  i16Bit = 2,
+  i32Bit = 4,
+  i64Bit = 8,
+  i128Bit = 16,
+  i256Bit = 32,
+};
+
+enum class FloatCompareOp : uint8_t {
+  EQ = 0,
+  LT,
+  LE,
+  UNO,
+  NEQ,
+  ORD,
+};
+
+enum class ShiftType : uint8_t {
+  LSL = 0,
+  LSR,
+  ASR,
+  ROR,
+};
+
+
+// Converts a size stored as an integer in to an OpSize enum.
+// This is a nop operation and will be eliminated by the compiler.
+static inline OpSize SizeToOpSize(uint8_t Size) {
+  switch (Size) {
+    case 1: return OpSize::i8Bit;
+    case 2: return OpSize::i16Bit;
+    case 4: return OpSize::i32Bit;
+    case 8: return OpSize::i64Bit;
+    case 16: return OpSize::i128Bit;
+    case 32: return OpSize::i256Bit;
+    default: FEX_UNREACHABLE;
+  }
+}
+
+#define IROP_ENUM
+#define IROP_STRUCTS
+#define IROP_SIZES
+#define IROP_REG_CLASSES
+#include <FEXCore/IR/IRDefines.inc>
+
+/* This iterator can be used to step though every single node in a multi-block in SSA order.
+ *
+ * Iterates in the order of:
+ *
+ * end <-- CodeBlockA <--> BlockAInst1 <--> BlockAInst2 <--> CodeBlockB <--> BlockBInst1 <--> BlockBInst2 --> end
+ */
+class AllNodesIterator : public NodeIterator {
+public:
+  AllNodesIterator(uintptr_t Base, uintptr_t IRBase) : NodeIterator(Base, IRBase) {}
+  explicit AllNodesIterator(uintptr_t Base, uintptr_t IRBase, OrderedNodeWrapper Ptr) : NodeIterator(Base, IRBase, Ptr) {}
+  AllNodesIterator(NodeIterator other) : NodeIterator(other) {} // Allow NodeIterator to be upgraded
+
+  AllNodesIterator operator++() {
+    OrderedNodeHeader *RealNode = reinterpret_cast<OrderedNodeHeader*>(Node.GetNode(BaseList));
+    auto IROp = Node.GetNode(BaseList)->Op(IRList);
+
+    // If this is the last node of a codeblock, we need to continue to the next block
+    if (IROp->Op == OP_ENDBLOCK) {
+      auto EndBlock = IROp->C<IROp_EndBlock>();
+
+      auto CurrentBlock = EndBlock->BlockHeader.GetNode(BaseList);
+      Node = CurrentBlock->Header.Next;
+    } else if (IROp->Op == OP_CODEBLOCK) {
+      auto CodeBlock = IROp->C<IROp_CodeBlock>();
+
+      Node = CodeBlock->Begin;
+    } else {
+      Node = RealNode->Next;
+    }
+
+    return *this;
+  }
+
+  AllNodesIterator operator--() {
+    auto IROp = Node.GetNode(BaseList)->Op(IRList);
+
+    if (IROp->Op == OP_BEGINBLOCK) {
+      auto BeginBlock = IROp->C<IROp_EndBlock>();
+
+      Node = BeginBlock->BlockHeader;
+    } else if (IROp->Op == OP_CODEBLOCK) {
+      auto PrevBlockWrapper = Node.GetNode(BaseList)->Header.Previous;
+      auto PrevCodeBlock = PrevBlockWrapper.GetNode(BaseList)->Op(IRList)->C<IROp_CodeBlock>();
+
+      Node = PrevCodeBlock->Last;
+    } else {
+      Node = Node.GetNode(BaseList)->Header.Previous;
+    }
+
+    return *this;
+  }
+
+  [[nodiscard]] static AllNodesIterator Invalid() {
+    return AllNodesIterator(0, 0);
+  }
+};
+
+class IRListView;
+class IREmitter;
+
+template<typename Type>
+inline NodeID NodeWrapperBase<Type>::ID() const {
+  return NodeID(NodeOffset / sizeof(IR::OrderedNode));
+}
+
+bool IsFragmentExit(FEXCore::IR::IROps Op);
+bool IsBlockExit(FEXCore::IR::IROps Op);
+
+void Dump(fextl::stringstream *out, IRListView const* IR, IR::RegisterAllocationData *RAData);
+fextl::unique_ptr<IREmitter> Parse(FEXCore::Utils::IntrusivePooledAllocator &ThreadAllocator, fextl::stringstream &MapsStream);
+}
+
+template <>
+struct std::hash<FEXCore::IR::NodeID> {
+  size_t operator()(const FEXCore::IR::NodeID& ID) const noexcept {
+    return std::hash<FEXCore::IR::NodeID::value_type>{}(ID.Value);
+  }
+};
+
+template <>
+struct fmt::formatter<FEXCore::IR::NodeID> : fmt::formatter<FEXCore::IR::NodeID::value_type> {
+  using Base = fmt::formatter<FEXCore::IR::NodeID::value_type>;
+
+  // Pass-through the underlying value, so IDs can
+  // be formatted like any integral value.
+  template <typename FormatContext>
+  auto format(const FEXCore::IR::NodeID& ID, FormatContext& ctx) const {
+    return Base::format(ID.Value, ctx);
+  }
+};
+
+template <>
+struct fmt::formatter<FEXCore::IR::RegisterClassType> : fmt::formatter<FEXCore::IR::RegisterClassType::value_type> {
+  using Base = fmt::formatter<FEXCore::IR::RegisterClassType::value_type>;
+
+  template <typename FormatContext>
+  auto format(const FEXCore::IR::RegisterClassType& Class, FormatContext& ctx) const {
+    return Base::format(Class.Val, ctx);
+  }
+};
+
+template <>
+struct fmt::formatter<FEXCore::IR::FenceType> : fmt::formatter<FEXCore::IR::FenceType::value_type> {
+  using Base = fmt::formatter<FEXCore::IR::FenceType::value_type>;
+
+  template <typename FormatContext>
+  auto format(const FEXCore::IR::FenceType& Fence, FormatContext& ctx) const {
+    return Base::format(Fence.Val, ctx);
+  }
+};
+
+template <>
+struct fmt::formatter<FEXCore::IR::OpSize> : fmt::formatter<std::underlying_type_t<FEXCore::IR::OpSize>> {
+  using Base = fmt::formatter<std::underlying_type_t<FEXCore::IR::OpSize>>;
+
+  template <typename FormatContext>
+  auto format(const FEXCore::IR::OpSize& OpSize, FormatContext& ctx) const {
+    return Base::format(FEXCore::ToUnderlying(OpSize), ctx);
+  }
+};
@@ -347,8 +347,7 @@
        "Desc": ["Loads a value from the static-ra context with offset",
                 "Dest = Ctx[Offset]"
                ],
-        "DestSize": "Size",
-        "DynamicDispatch": true
+        "DestSize": "Size"
      },

      "StoreRegister SSA:$Value, i1:$IsPrewrite, u32:$Offset, RegisterClass:$Class, RegisterClass:$StaticClass, u8:#Size": {
@@ -359,7 +358,6 @@
                 "Truncates if value's type is too large"
                ],
        "DestSize": "Size",
-        "DynamicDispatch": true,
        "EmitValidation": [
          "WalkFindRegClass($Value) == $Class"
        ]
@@ -458,6 +456,13 @@
        "DestSize": "4"
      },

+      "GPR = LoadDF": {
+        "Desc": ["Loads the decimal flag from the context object in -1/1",
+                  "representation for easy consumption"
+                ],
+        "DestSize": "8"
+      },
+
      "GPR = LoadFlag u32:$Flag": {
        "Desc": ["Loads an x86-64 flag from the context object",
                 "Specialized to allow flexible implementation of flag handling"
@@ -598,6 +603,15 @@
                 "Ensures the memory operations are globally visible"
                ],
        "HasSideEffects": true
+      },
+      "Prefetch i1:$ForStore, i1:$Stream, i8:$CacheLevel, GPR:$Addr, GPR:$Offset, MemOffsetType:$OffsetType, u8:$OffsetScale": {
+        "Desc": ["Does a cacheline prefetch operation"
+                ],
+        "EmitValidation": [
+          "_CacheLevel > 0 && _CacheLevel < 4"
+        ],
+        "HasSideEffects": true,
+        "DestSize": "8"
      }
    },
    "Atomic": {
@@ -628,7 +642,6 @@
                ],
        "HasDest": true,
        "DestSize": "Size",
-        "ImplicitFlagClobber": true,
        "NumElements": "2",
        "EmitValidation": [
          "Size == FEXCore::IR::OpSize::i64Bit || Size == FEXCore::IR::OpSize::i128Bit"
@@ -953,14 +966,55 @@
          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
        ]
      },
-      "AddNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
-        "Desc": ["Set NZCV for the sum of two GPRs"],
-        "HasSideEffects": true,
+      "GPR = Adc OpSize:#Size, GPR:$Src1, GPR:$Src2": {
+        "Desc": [ "Integer Add with carry",
+                  "Will truncate to 64 or 32bits"
+                ],
        "DestSize": "Size",
        "EmitValidation": [
          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
        ]
      },
+      "GPR = Sbb OpSize:#Size, GPR:$Src1, GPR:$Src2": {
+        "Desc": [ "Integer Subtract with carry/borrow",
+                  "Will truncate to 64 or 32bits"
+                ],
+        "DestSize": "Size",
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
+        ]
+      },
+      "GPR = AddShift OpSize:#Size, GPR:$Src1, GPR:$Src2, ShiftType:$Shift{ShiftType::LSL}, u8:$ShiftAmount{0}": {
+        "Desc": [ "Integer Add with shifted register",
+                  "Will truncate to 64 or 32bits"
+                ],
+        "DestSize": "Size",
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit",
+          "_Shift != ShiftType::ROR"
+        ]
+      },
+      "GPR = AddWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
+        "Desc": [ "Integer add. Truncates and sets NZCV per AddNZCV"],
+        "DestSize": "Size",
+        "HasSideEffects": true,
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
+        ]
+      },
+      "AddNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
+        "Desc": ["Set NZCV for the sum of two GPRs"],
+        "HasSideEffects": true,
+        "DestSize": "Size"
+      },
+      "SetSmallNZV OpSize:#Size, GPR:$Src": {
+        "Desc": ["Set NZV with a SETF instruction. Preserves CF."],
+        "HasSideEffects": true,
+        "DestSize": "Size",
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit"
+        ]
+      },
      "CarryInvert": {
        "Desc": ["Invert carry flag in NZCV"],
        "HasSideEffects": true
@@ -981,6 +1035,30 @@
          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
        ]
      },
+      "CondSubNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2, CondClass:$Cond, u8:$FalseNZCV": {
+        "Desc": ["If condition is true, set NZCV per difference of GPRs, else force NZCV to a constant."],
+        "HasSideEffects": true,
+        "DestSize": "Size",
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
+        ]
+      },
+      "GPR = AdcWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
+        "Desc": ["Adds and set NZCV for the sum of two GPRs and carry-in given as NZCV"],
+        "HasSideEffects": true,
+        "DestSize": "Size",
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
+        ]
+      },
+      "GPR = SbbWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
+        "Desc": ["Subtracts and set NZCV for the difference of two GPRs and carry-in given as NZCV"],
+        "HasSideEffects": true,
+        "DestSize": "Size",
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
+        ]
+      },
      "AdcNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
        "Desc": ["Set NZCV for the sum of two GPRs and carry-in given as NZCV"],
        "HasSideEffects": true,
@@ -1016,16 +1094,26 @@
          "_Shift != ShiftType::ROR"
        ]
      },
-      "SubNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
-        "Desc": ["Set NZCV for the difference of two GPRs. ",
-                 "Carry flag uses arm64 definition, inverted x86.",
-                 ""],
+      "GPR = SubWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
+        "Desc": [ "Integer Sub. Truncates and sets NZCV per SubNZCV"],
        "DestSize": "Size",
        "HasSideEffects": true,
        "EmitValidation": [
          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
        ]
      },
+      "CmpPairZ OpSize:#Size, GPRPair:$Src1, GPRPair:$Src2": {
+        "Desc": ["Compares register pairs and sets Z accordingly, preserving N/Z/V.",
+                 "This accelerates cmpxchg."],
+        "HasSideEffects": true
+      },
+      "SubNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
+        "Desc": ["Set NZCV for the difference of two GPRs. ",
+                 "Carry flag uses arm64 definition, inverted x86.",
+                 ""],
+        "DestSize": "Size",
+        "HasSideEffects": true
+      },
      "GPR = Or OpSize:#Size, GPR:$Src1, GPR:$Src2": {
        "Desc": ["Integer binary or"
                ],
@@ -1073,6 +1161,13 @@
          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
        ]
      },
+      "GPR = XornShift OpSize:#Size, GPR:$Src1, GPR:$Src2, ShiftType:$Shift{ShiftType::LSL}, u8:$ShiftAmount{0}": {
+        "Desc": [ "Integer binary exclusive or not with shifted register"],
+        "DestSize": "Size",
+        "EmitValidation": [
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
+        ]
+      },
      "GPR = And OpSize:#Size, GPR:$Src1, GPR:$Src2": {
        "Desc": ["Integer binary and"
                ],
@@ -1081,6 +1176,12 @@
          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
        ]
      },
+      "GPR = AndWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
+        "Desc": ["Integer binary and"
+                ],
+        "DestSize": "Size",
+        "HasSideEffects": true
+      },
      "GPR = Andn OpSize:#Size, GPR:$Src1, GPR:$Src2": {
        "Desc": ["Integer binary AND NOT. Performs the equivalent of Src1 & ~Src2"],
        "DestSize": "Size",
@@ -1141,6 +1242,18 @@
          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
        ]
      },
+      "GPR = UMull GPR:$Src1, GPR:$Src2": {
+        "Desc": ["Integer unsigned multiplication long",
+                 "Multiplies two 32-bit numbers, returning a 64-bit destination register."
+                ],
+        "DestSize": "FEXCore::IR::OpSize::i64Bit"
+      },
+      "GPR = SMull GPR:$Src1, GPR:$Src2": {
+        "Desc": ["Integer signed multiplication long",
+                 "Multiplies two 32-bit numbers, returning a 64-bit destination register."
+                ],
+        "DestSize": "FEXCore::IR::OpSize::i64Bit"
+      },
      "GPR = Div OpSize:#Size, GPR:$Src1, GPR:$Src2": {
        "Desc": ["Integer signed division"
                ],
@@ -1592,7 +1705,13 @@
        "DestSize": "RegisterSize",
        "NumElements": "RegisterSize / ElementSize"
      },
-      
+      "FPR = VUMaxV u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
+        "Desc": ["Does a horizontal vector unsigned maximum of elements across the source vector",
+                 "Result is a zero extended scalar"
+                ],
+        "DestSize": "RegisterSize",
+        "NumElements": "RegisterSize / ElementSize"
+      },
      "FPR = VFAbs u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
        "DestSize": "RegisterSize",
        "NumElements": "RegisterSize / ElementSize"
@@ -6,9 +6,10 @@ tags: ir|dumper
 $end_info$
 */

+#include "Interface/IR/IntrusiveIRList.h"
+#include "Interface/IR/RegisterAllocationData.h"
+
 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/fextl/sstream.h>

 #include <algorithm>
@@ -6,9 +6,9 @@ tags: ir|emitter
 $end_info$
 */

+#include "Interface/IR/IREmitter.h"
+
 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>

@@ -1,7 +1,10 @@
 // SPDX-License-Identifier: MIT
 #pragma once
+
+#include "Interface/IR/IR.h"
+#include "Interface/IR/IntrusiveIRList.h"
+
 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/IR/IR.h>

 #include <FEXCore/Utils/LogManager.h>
@@ -6,9 +6,9 @@ tags: ir|parser
 $end_info$
 */

+#include "Interface/IR/IREmitter.h"
+
 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/IR/IREmitter.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/StringUtils.h>
 #include <FEXCore/fextl/sstream.h>
@@ -505,8 +505,8 @@ class IRParser: public FEXCore::IR::IREmitter {
      }

      if (Def.HasArgs) {
-        RemainingLine = FEXCore::StringUtils::Trim(RemainingLine.substr(CurrentPos));
-        CurrentPos = 0;
+        RemainingLine =
+            FEXCore::StringUtils::Trim(RemainingLine.substr(CurrentPos));
        if (RemainingLine.empty()) {
          // How did we get here?
          Def.HasArgs = false;
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: MIT
 #pragma once

-#include "FEXCore/IR/IR.h"
+#include "Interface/IR/IR.h"
+
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/LogManager.h>
@@ -66,7 +66,7 @@ void PassManager::Finalize() {
  }
 }

-void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl *ctx, bool InlineConstants, bool StaticRegisterAllocation) {
+void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl *ctx, bool InlineConstants) {
  FEX_CONFIG_OPT(DisablePasses, O0);

  if (!DisablePasses()) {
@@ -80,9 +80,10 @@ void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl *ctx, bool Inli

    InsertPass(CreateDeadStoreElimination(ctx->HostFeatures.SupportsAVX));
    InsertPass(CreatePassDeadCodeElimination());
-    InsertPass(CreateConstProp(InlineConstants, ctx->HostFeatures.SupportsTSOImm9));
+    InsertPass(CreateConstProp(
+        InlineConstants, ctx->HostFeatures.SupportsTSOImm9, Is64BitMode()));

-    ////// InsertPass(CreateDeadFlagCalculationEliminination());
+    InsertPass(CreateDeadFlagCalculationEliminination());

    InsertPass(CreateInlineCallOptimization(&ctx->CPUID));
    InsertPass(CreatePassDeadCodeElimination());
@@ -101,8 +102,8 @@ void PassManager::AddDefaultValidationPasses() {
 #endif
 }

-void PassManager::InsertRegisterAllocationPass(bool OptimizeSRA, bool SupportsAVX) {
-  InsertPass(IR::CreateRegisterAllocationPass(GetPass("Compaction"), OptimizeSRA, SupportsAVX), "RA");
+void PassManager::InsertRegisterAllocationPass(bool SupportsAVX) {
+  InsertPass(IR::CreateRegisterAllocationPass(GetPass("Compaction"), SupportsAVX), "RA");
 }

 bool PassManager::Run(IREmitter *IREmit) {
@@ -121,5 +122,4 @@ bool PassManager::Run(IREmitter *IREmit) {

  return Changed;
 }
-
 }
@@ -29,8 +29,6 @@ namespace FEXCore::IR {
 class PassManager;
 class IREmitter;

-using ShouldExitHandler = std::function<void(void)>;
-
 class Pass {
 public:
  virtual ~Pass() = default;
@@ -47,7 +45,7 @@ protected:
 class PassManager final {
  friend class InlineCallOptimization;
 public:
-  void AddDefaultPasses(FEXCore::Context::ContextImpl *ctx, bool InlineConstants, bool StaticRegisterAllocation);
+  void AddDefaultPasses(FEXCore::Context::ContextImpl *ctx, bool InlineConstants);
  void AddDefaultValidationPasses();
  Pass* InsertPass(fextl::unique_ptr<Pass> Pass, fextl::string Name = "") {
    auto PassPtr = InsertAt(Passes.end(), std::move(Pass))->get();
@@ -58,14 +56,10 @@ public:
    return PassPtr;
  }

-  void InsertRegisterAllocationPass(bool OptimizeSRA, bool SupportsAVX);
+  void InsertRegisterAllocationPass(bool SupportsAVX);

  bool Run(IREmitter *IREmit);

-  void RegisterExitHandler(ShouldExitHandler Handler) {
-    ExitHandler = std::move(Handler);
-  }
-
  bool HasPass(fextl::string Name) const {
    return NameToPassMaping.contains(Name);
  }
@@ -86,7 +80,6 @@ public:
  void Finalize();

 protected:
-  ShouldExitHandler ExitHandler;
  FEXCore::HLE::SyscallHandler *SyscallHandler;

 private:
@@ -16,16 +16,17 @@ class Pass;
 class RegisterAllocationPass;
 class RegisterAllocationData;

-fextl::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool InlineConstants, bool SupportsTSOImm9);
+fextl::unique_ptr<FEXCore::IR::Pass>
+CreateConstProp(bool InlineConstants, bool SupportsTSOImm9, bool Is64BitMode);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateContextLoadStoreElimination(bool SupportsAVX);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateInlineCallOptimization(const FEXCore::CPUIDEmu* CPUID);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateDeadFlagCalculationEliminination();
 fextl::unique_ptr<FEXCore::IR::Pass> CreateDeadStoreElimination(bool SupportsAVX);
 fextl::unique_ptr<FEXCore::IR::Pass> CreatePassDeadCodeElimination();
 fextl::unique_ptr<FEXCore::IR::Pass> CreateIRCompaction(FEXCore::Utils::IntrusivePooledAllocator &Allocator);
-fextl::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass(FEXCore::IR::Pass* CompactionPass,
-                                                                                  bool OptimizeSRA,
-                                                                                  bool SupportsAVX);
+fextl::unique_ptr<FEXCore::IR::RegisterAllocationPass>
+CreateRegisterAllocationPass(FEXCore::IR::Pass *CompactionPass,
+                             bool SupportsAVX);
 fextl::unique_ptr<FEXCore::IR::Pass> CreateLongDivideEliminationPass();

 namespace Validation {
@@ -13,11 +13,10 @@ $end_info$
 #include "aarch64/disasm-aarch64.h"
 #include "aarch64/assembler-aarch64.h"

+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/PassManager.h"

 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
 #include <FEXCore/fextl/map.h>
@@ -27,6 +26,7 @@ $end_info$
 #include <bit>
 #include <cstdint>
 #include <memory>
+#include <optional>
 #include <string.h>
 #include <tuple>
 #include <utility>
@@ -90,58 +90,132 @@ static bool IsTSOImm9(uint64_t imm) {
  }
 }

-static std::tuple<MemOffsetType, uint8_t, OrderedNode*, OrderedNode*> MemExtendedAddressing(IREmitter *IREmit, uint8_t AccessSize,  IROp_Header* AddressHeader) {
+using MemExtendedAddrResult =
+    std::tuple<MemOffsetType, uint8_t, OrderedNode *, OrderedNode *>;
+
+// If this optimization doesn't succeed, it will return the nullopt
+static std::optional<MemExtendedAddrResult>
+MemExtendedAddressing(IREmitter *IREmit, uint8_t AccessSize,
+                      IROp_Header *AddressHeader) {
+  // Try to optimize: AddShift Base, LSHL(Offset, Scale)
+  if (AddressHeader->Op == OP_ADDSHIFT) {
+    auto AddShift = AddressHeader->C<IROp_AddShift>();
+    if (AddShift->Shift == IR::ShiftType::LSL) {
+      auto Scale = 1U << AddShift->ShiftAmount;
+      if (IsMemoryScale(Scale, AccessSize)) {
+        // remove shift as it can be folded to the mem op
+        return std::make_optional(
+            std::make_tuple(MEM_OFFSET_SXTX, (uint8_t)Scale,
+                            IREmit->UnwrapNode(AddShift->Src2),
+                            IREmit->UnwrapNode(AddShift->Src1)));
+      } else if (Scale == 1) {
+        return std::make_optional(std::make_tuple(
+            MEM_OFFSET_SXTX, 1, IREmit->UnwrapNode(AddShift->Src2),
+            IREmit->UnwrapNode(AddShift->Src1)));
+      }
+    }
+
+    return std::nullopt;
+  }
+
+  LOGMAN_THROW_A_FMT(AddressHeader->Op == OP_ADD, "Invalid address Op");
  auto Src0Header = IREmit->GetOpHeader(AddressHeader->Args[0]);
  if (Src0Header->Size == 8) {
-    //Try to optimize: Base + MUL(Offset, Scale)
+    // Try to optimize: Base + MUL(Offset, Scale)
    if (Src0Header->Op == OP_MUL) {
      uint64_t Scale;
      if (IREmit->IsValueConstant(Src0Header->Args[1], &Scale)) {
        if (IsMemoryScale(Scale, AccessSize)) {
          // remove mul as it can be folded to the mem op
-          return { MEM_OFFSET_SXTX, (uint8_t)Scale, IREmit->UnwrapNode(AddressHeader->Args[1]), IREmit->UnwrapNode(Src0Header->Args[0]) };
+          return std::make_optional(
+              std::make_tuple(MEM_OFFSET_SXTX, (uint8_t)Scale,
+                              IREmit->UnwrapNode(AddressHeader->Args[1]),
+                              IREmit->UnwrapNode(Src0Header->Args[0])));
        } else if (Scale == 1) {
          // remove nop mul
-          return { MEM_OFFSET_SXTX, 1, IREmit->UnwrapNode(AddressHeader->Args[1]), IREmit->UnwrapNode(Src0Header->Args[0]) };
+          return std::make_optional(std::make_tuple(
+              MEM_OFFSET_SXTX, 1, IREmit->UnwrapNode(AddressHeader->Args[1]),
+              IREmit->UnwrapNode(Src0Header->Args[0])));
        }
      }
    }
-    //Try to optimize: Base + LSHL(Offset, Scale)
+    // Try to optimize: Base + LSHL(Offset, Scale)
    else if (Src0Header->Op == OP_LSHL) {
      uint64_t Constant2;
      if (IREmit->IsValueConstant(Src0Header->Args[1], &Constant2)) {
        uint64_t Scale = 1<<Constant2;
        if (IsMemoryScale(Scale, AccessSize)) {
          // remove shift as it can be folded to the mem op
-          return { MEM_OFFSET_SXTX, Scale, IREmit->UnwrapNode(AddressHeader->Args[1]), IREmit->UnwrapNode(Src0Header->Args[0]) };
+          return std::make_optional(
+              std::make_tuple(MEM_OFFSET_SXTX, Scale,
+                              IREmit->UnwrapNode(AddressHeader->Args[1]),
+                              IREmit->UnwrapNode(Src0Header->Args[0])));
        } else if (Scale == 1) {
          // remove nop shift
-          return { MEM_OFFSET_SXTX, 1, IREmit->UnwrapNode(AddressHeader->Args[1]), IREmit->UnwrapNode(Src0Header->Args[0]) };
+          return std::make_optional(std::make_tuple(
+              MEM_OFFSET_SXTX, 1, IREmit->UnwrapNode(AddressHeader->Args[1]),
+              IREmit->UnwrapNode(Src0Header->Args[0])));
        }
      }
    }
 #if defined(_M_ARM_64) // x86 can't sext or zext on mem ops
-    //Try to optimize: Base + (u32)Offset
+    // Try to optimize: Base + (u32)Offset
    else if (Src0Header->Op == OP_BFE) {
      auto Bfe = Src0Header->C<IROp_Bfe>();
      if (Bfe->lsb == 0 && Bfe->Width == 32) {
        //todo: arm can also scale here
-        return { MEM_OFFSET_UXTW, 1, IREmit->UnwrapNode(AddressHeader->Args[1]), IREmit->UnwrapNode(Src0Header->Args[0]) };
+        return std::make_optional(std::make_tuple(
+            MEM_OFFSET_UXTW, 1, IREmit->UnwrapNode(AddressHeader->Args[1]),
+            IREmit->UnwrapNode(Src0Header->Args[0])));
      }
    }
-    //Try to optimize: Base + (s32)Offset
+    // Try to optimize: Base + (s32)Offset
    else if (Src0Header->Op == OP_SBFE) {
      auto Sbfe = Src0Header->C<IROp_Sbfe>();
      if (Sbfe->lsb == 0 && Sbfe->Width == 32) {
-        //todo: arm can also scale here
-        return { MEM_OFFSET_SXTW, 1, IREmit->UnwrapNode(AddressHeader->Args[1]), IREmit->UnwrapNode(Src0Header->Args[0]) };
+        // todo: arm can also scale here
+        return std::make_optional(std::make_tuple(
+            MEM_OFFSET_SXTW, 1, IREmit->UnwrapNode(AddressHeader->Args[1]),
+            IREmit->UnwrapNode(Src0Header->Args[0])));
      }
    }
 #endif
  }

  // no match anywhere, just add
-  return { MEM_OFFSET_SXTX, 1, IREmit->UnwrapNode(AddressHeader->Args[0]), IREmit->UnwrapNode(AddressHeader->Args[1]) };
+  // However, if we have one 32bit negative constant, we need to sign extend it
+  auto Arg0_ = AddressHeader->Args[0];
+  auto Arg1_ = AddressHeader->Args[1];
+  auto Arg1H = IREmit->GetOpHeader(Arg1_);
+  auto Arg0 = IREmit->UnwrapNode(Arg0_);
+  auto Arg1 = IREmit->UnwrapNode(Arg1_);
+
+  uint64_t ConstVal = 0;
+  // Only optimize in 32bits reg+const where const < 16Kb.
+  if (Arg1H->Size == 4 && IREmit->IsValueConstant(Arg1_, &ConstVal)) {
+    // Base is Arg0, Constant (Displacement in Arg1)
+    OrderedNode *Base = Arg0;
+    OrderedNode *Cnt = Arg1;
+    int32_t Val32 = (int32_t)ConstVal;
+
+    if (Val32 > -16384 && Val32 < 0) {
+      return std::make_optional(std::make_tuple(MEM_OFFSET_SXTW, 1, Base, Cnt));
+    } else if (Val32 >= 0 && Val32 < 16384) {
+      return std::make_optional(std::make_tuple(MEM_OFFSET_SXTX, 1, Base, Cnt));
+    }
+  } else if (AddressHeader->Size == 4) {
+    // Do not optimize 32bit reg+reg.
+    // Something like :
+    //   add w20, w7, w5
+    //   ldr w7, [x20]
+    //
+    // cannot be simplified to (or any other single load instruction)
+    // ldr w7, [x5, w7, sxtx]
+    return std::nullopt;
+  } else {
+    return std::make_optional(std::make_tuple(MEM_OFFSET_SXTX, 1, Arg0, Arg1));
+  }
+  return std::nullopt;
 }

 static OrderedNodeWrapper RemoveUselessMasking(IREmitter *IREmit, OrderedNodeWrapper src, uint64_t mask) {
@@ -184,9 +258,10 @@ static bool IsBfeAlreadyDone(IREmitter *IREmit, OrderedNodeWrapper src, uint64_t

 class ConstProp final : public FEXCore::IR::Pass {
 public:
-  explicit ConstProp(bool DoInlineConstants, bool SupportsTSOImm9)
-    : InlineConstants(DoInlineConstants)
-    , SupportsTSOImm9 {SupportsTSOImm9} { }
+  explicit ConstProp(bool DoInlineConstants, bool SupportsTSOImm9,
+                     bool Is64BitMode)
+      : InlineConstants(DoInlineConstants), SupportsTSOImm9{SupportsTSOImm9},
+        Is64BitMode(Is64BitMode) {}

  bool Run(IREmitter *IREmit) override;

@@ -219,6 +294,7 @@ private:
    return Result.first->second;
  }
  bool SupportsTSOImm9{};
+  bool Is64BitMode;
  // This is a heuristic to limit constant pool live ranges to reduce RA interference pressure.
  // If the range is unbounded then RA interference pressure seems to increase to the point
  // that long blocks of constant usage can slow to a crawl.
@@ -439,50 +515,6 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
    bool Changed = false;

    switch (IROp->Op) {
-/*
-    case OP_UMUL:
-    case OP_DIV:
-    case OP_UDIV:
-    case OP_REM:
-    case OP_UREM:
-    case OP_MULH:
-    case OP_UMULH:
-    case OP_LSHR:
-    case OP_ASHR:
-    case OP_ROL:
-    case OP_ROR:
-    case OP_LDIV:
-    case OP_LUDIV:
-    case OP_LREM:
-    case OP_LUREM:
-    case OP_BFI:
-    {
-      uint64_t Constant1;
-      uint64_t Constant2;
-
-      if (IREmit->IsValueConstant(IROp->Args[0], &Constant1) &&
-          IREmit->IsValueConstant(IROp->Args[1], &Constant2)) {
-        LOGMAN_MSG_A_FMT("Could const prop op: {}", IR::GetName(IROp->Op));
-      }
-    break;
-    }
-
-    case OP_SEXT:
-    case OP_NEG:
-    case OP_POPCOUNT:
-    case OP_FINDLSB:
-    case OP_FINDMSB:
-    case OP_REV:
-    case OP_SBFE: {
-      uint64_t Constant1;
-
-      if (IREmit->IsValueConstant(IROp->Args[0], &Constant1)) {
-        LOGMAN_MSG_A_FMT("Could const prop op: {}", IR::GetName(IROp->Op));
-      }
-    break;
-    }
-*/
-
    case OP_LOADMEMTSO: {
      auto Op = IROp->CW<IR::IROp_LoadMemTSO>();
      auto AddressHeader = IREmit->GetOpHeader(Op->Addr);
@@ -490,8 +522,12 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
      if (Op->Class == FEXCore::IR::FPRClass && AddressHeader->Op == OP_ADD && AddressHeader->Size == 8) {
        // TODO: LRCPC3 supports a vector unscaled offset like LRCPC2.
        // Support once hardware is available to use this.
-        auto [OffsetType, OffsetScale, Arg0, Arg1] = MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
-
+        auto MaybeMemAddr =
+            MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
+        if (!MaybeMemAddr) {
+          break;
+        }
+        auto [OffsetType, OffsetScale, Arg0, Arg1] = *MaybeMemAddr;
        Op->OffsetType = OffsetType;
        Op->OffsetScale = OffsetScale;
        IREmit->ReplaceNodeArgument(CodeNode, Op->Addr_Index, Arg0); // Addr
@@ -509,8 +545,12 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
      if (Op->Class == FEXCore::IR::FPRClass && AddressHeader->Op == OP_ADD && AddressHeader->Size == 8) {
        // TODO: LRCPC3 supports a vector unscaled offset like LRCPC2.
        // Support once hardware is available to use this.
-        auto [OffsetType, OffsetScale, Arg0, Arg1] = MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
-
+        auto MaybeMemAddr =
+            MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
+        if (!MaybeMemAddr) {
+          break;
+        }
+        auto [OffsetType, OffsetScale, Arg0, Arg1] = *MaybeMemAddr;
        Op->OffsetType = OffsetType;
        Op->OffsetScale = OffsetScale;
        IREmit->ReplaceNodeArgument(CodeNode, Op->Addr_Index, Arg0); // Addr
@@ -525,12 +565,19 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
      auto Op = IROp->CW<IR::IROp_LoadMem>();
      auto AddressHeader = IREmit->GetOpHeader(Op->Addr);

-      if (AddressHeader->Op == OP_ADD && AddressHeader->Size == 8) {
-        auto [OffsetType, OffsetScale, Arg0, Arg1] = MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
+      if (AddressHeader->Op == OP_ADD &&
+          ((Is64BitMode && AddressHeader->Size == 8) ||
+           (!Is64BitMode && AddressHeader->Size == 4))) {
+        auto MaybeMemAddr =
+            MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
+        if (!MaybeMemAddr) {
+          break;
+        }
+        auto [OffsetType, OffsetScale, Arg0, Arg1] = *MaybeMemAddr;

        Op->OffsetType = OffsetType;
        Op->OffsetScale = OffsetScale;
-        IREmit->ReplaceNodeArgument(CodeNode, Op->Addr_Index, Arg0); // Addr
+        IREmit->ReplaceNodeArgument(CodeNode, Op->Addr_Index, Arg0);   // Addr
        IREmit->ReplaceNodeArgument(CodeNode, Op->Offset_Index, Arg1); // Offset

        Changed = true;
@@ -542,8 +589,15 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
      auto Op = IROp->CW<IR::IROp_StoreMem>();
      auto AddressHeader = IREmit->GetOpHeader(Op->Addr);

-      if (AddressHeader->Op == OP_ADD && AddressHeader->Size == 8) {
-        auto [OffsetType, OffsetScale, Arg0, Arg1] = MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
+      if (AddressHeader->Op == OP_ADD &&
+          ((Is64BitMode && AddressHeader->Size == 8) ||
+           (!Is64BitMode && AddressHeader->Size == 4))) {
+        auto MaybeMemAddr =
+            MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
+        if (!MaybeMemAddr) {
+          break;
+        }
+        auto [OffsetType, OffsetScale, Arg0, Arg1] = *MaybeMemAddr;

        Op->OffsetType = OffsetType;
        Op->OffsetScale = OffsetScale;
@@ -555,23 +609,65 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
      break;
    }

-    case OP_ADD: {
+    case OP_PREFETCH: {
+      auto Op = IROp->CW<IR::IROp_Prefetch>();
+      auto AddressHeader = IREmit->GetOpHeader(Op->Addr);
+
+      const bool SupportedOp =
+        AddressHeader->Op == OP_ADD ||
+        AddressHeader->Op == OP_ADDSHIFT;
+
+      if (SupportedOp &&
+          ((Is64BitMode && AddressHeader->Size == 8) ||
+           (!Is64BitMode && AddressHeader->Size == 4))) {
+        auto MaybeMemAddr =
+            MemExtendedAddressing(IREmit, IROp->Size, AddressHeader);
+        if (!MaybeMemAddr) {
+          break;
+        }
+        auto [OffsetType, OffsetScale, Arg0, Arg1] = *MaybeMemAddr;
+
+        Op->OffsetType = OffsetType;
+        Op->OffsetScale = OffsetScale;
+        IREmit->ReplaceNodeArgument(CodeNode, Op->Addr_Index, Arg0);   // Addr
+        IREmit->ReplaceNodeArgument(CodeNode, Op->Offset_Index, Arg1); // Offset
+
+        Changed = true;
+      }
+      break;
+    }
+
+    case OP_ADD:
+    case OP_SUB:
+    case OP_ADDWITHFLAGS:
+    case OP_SUBWITHFLAGS: {
      auto Op = IROp->C<IR::IROp_Add>();
      uint64_t Constant1{};
      uint64_t Constant2{};
      bool IsConstant1 = IREmit->IsValueConstant(Op->Header.Args[0], &Constant1);
      bool IsConstant2 = IREmit->IsValueConstant(Op->Header.Args[1], &Constant2);

-      if (IsConstant1 && IsConstant2) {
+      if (IsConstant1 && IsConstant2 && IROp->Op == OP_ADD) {
        uint64_t NewConstant = (Constant1 + Constant2) & getMask(Op) ;
        IREmit->ReplaceWithConstant(CodeNode, NewConstant);
        Changed = true;
+      } else if (IsConstant1 && IsConstant2 && IROp->Op == OP_SUB) {
+        uint64_t NewConstant = (Constant1 - Constant2) & getMask(Op) ;
+        IREmit->ReplaceWithConstant(CodeNode, NewConstant);
+        Changed = true;
      }
      else if (IsConstant2 && !IsImmAddSub(Constant2) && IsImmAddSub(-Constant2)) {
        // If the second argument is constant, the immediate is not ImmAddSub, but when negated is.
-        // This means we can convert the operation in to a subtract.
-        // Change the IR operation itself.
-        IROp->Op = OP_SUB;
+        // So, negate the operation to negate (and inline) the constant.
+        if (IROp->Op == OP_ADD)
+          IROp->Op = OP_SUB;
+        else if (IROp->Op == OP_SUB)
+          IROp->Op = OP_ADD;
+        else if (IROp->Op == OP_ADDWITHFLAGS)
+          IROp->Op = OP_SUBWITHFLAGS;
+        else if (IROp->Op == OP_SUBWITHFLAGS)
+          IROp->Op = OP_ADDWITHFLAGS;
+
        // Set the write cursor to just before this operation.
        auto CodeIter = CurrentIR.at(CodeNode);
        --CodeIter;
@@ -586,19 +682,6 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
      }
    break;
    }
-    case OP_SUB: {
-      auto Op = IROp->C<IR::IROp_Sub>();
-      uint64_t Constant1{};
-      uint64_t Constant2{};
-
-      if (IREmit->IsValueConstant(Op->Header.Args[0], &Constant1) &&
-          IREmit->IsValueConstant(Op->Header.Args[1], &Constant2)) {
-        uint64_t NewConstant = (Constant1 - Constant2) & getMask(Op) ;
-        IREmit->ReplaceWithConstant(CodeNode, NewConstant);
-        Changed = true;
-      }
-    break;
-    }
    case OP_SUBSHIFT: {
      auto Op = IROp->C<IR::IROp_SubShift>();

@@ -645,23 +728,6 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
      }
    break;
    }
-    /* TODO: restore this when we have rmif or something? */
-#if 0
-    case OP_TESTNZ: {
-      auto Op = IROp->CW<IR::IROp_TestNZ>();
-      uint64_t Constant1{};
-
-      if (IREmit->IsValueConstant(Op->Header.Args[0], &Constant1)) {
-        bool N = Constant1 & (1ull << ((Op->Size * 8) - 1));
-        bool Z = Constant1 == 0;
-        uint32_t NZVC = (N ? (1u << 31) : 0) | (Z ? (1u << 30) : 0);
-
-        IREmit->ReplaceWithConstant(CodeNode, NZVC);
-        Changed = true;
-      }
-    break;
-    }
-#endif
    case OP_OR: {
      auto Op = IROp->CW<IR::IROp_Or>();
      uint64_t Constant1{};
@@ -738,6 +804,17 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
      }
    break;
    }
+    case OP_NEG: {
+      auto Op = IROp->CW<IR::IROp_Neg>();
+      uint64_t Constant{};
+
+      if (IREmit->IsValueConstant(Op->Header.Args[0], &Constant)) {
+        uint64_t NewConstant = -Constant;
+        IREmit->ReplaceWithConstant(CodeNode, NewConstant);
+        Changed = true;
+      }
+    break;
+    }
    case OP_LSHL: {
      auto Op = IROp->CW<IR::IROp_Lshl>();
      uint64_t Constant1{};
@@ -833,12 +910,17 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
      uint64_t Constant;
      if (IREmit->IsValueConstant(Op->Src, &Constant)) {
        // SBFE of a constant can be converted to a constant.
-        uint64_t SourceMask = Op->Width == 64 ? ~0ULL : ((1ULL << Op->Width) - 1);
+        uint64_t SourceMask =
+            Op->Width == 64 ? ~0ULL : ((1ULL << Op->Width) - 1);
+        uint64_t DestSizeInBits = IROp->Size * 8;
+        uint64_t DestMask =
+            DestSizeInBits == 64 ? ~0ULL : ((1ULL << DestSizeInBits) - 1);
        SourceMask <<= Op->lsb;

        int64_t NewConstant = (Constant & SourceMask) >> Op->lsb;
        NewConstant <<= 64 - Op->Width;
        NewConstant >>= 64 - Op->Width;
+        NewConstant &= DestMask;
        IREmit->ReplaceWithConstant(CodeNode, NewConstant);

        Changed = true;
@@ -960,20 +1042,24 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR)
      case OP_SUB:
      case OP_ADDNZCV:
      case OP_SUBNZCV:
+      case OP_ADDWITHFLAGS:
+      case OP_SUBWITHFLAGS:
      {
        auto Op = IROp->C<IR::IROp_Add>();

        uint64_t Constant2{};
        if (IREmit->IsValueConstant(Op->Header.Args[1], &Constant2)) {
-          if (IsImmAddSub(Constant2)) {
+          // We don't allow 8/16-bit operations to have constants, since no
+          // constant would be in bounds after the JIT's 24/16 shift.
+          if (IsImmAddSub(Constant2) && Op->Header.Size >= 4) {
            IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Header.Args[1]));

            IREmit->ReplaceNodeArgument(CodeNode, 1, CreateInlineConstant(IREmit, Constant2));

            Changed = true;
          }
-        } else if (IROp->Op == OP_SUBNZCV) {
-          // If the first source is zero, we can use a NEGS instruction.
+        } else if (IROp->Op == OP_SUBNZCV || IROp->Op == OP_SUBWITHFLAGS || IROp->Op == OP_SUB) {
+          // TODO: Generalize this
          uint64_t Constant1{};
          if (IREmit->IsValueConstant(Op->Header.Args[0], &Constant1)) {
            if (Constant1 == 0) {
@@ -986,7 +1072,39 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR)

        break;
      }
+      case OP_ADC:
+      case OP_ADCWITHFLAGS:
+      {
+        auto Op = IROp->C<IR::IROp_Adc>();
+
+        uint64_t Constant1{};
+        if (IREmit->IsValueConstant(Op->Header.Args[0], &Constant1)) {
+          if (Constant1 == 0) {
+            IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Header.Args[0]));
+            IREmit->ReplaceNodeArgument(CodeNode, 0, CreateInlineConstant(IREmit, 0));
+            Changed = true;
+          }
+        }
+
+        break;
+      }
+      case OP_RMIFNZCV:
+      {
+        auto Op = IROp->C<IR::IROp_RmifNZCV>();
+
+        uint64_t Constant1{};
+        if (IREmit->IsValueConstant(Op->Header.Args[0], &Constant1)) {
+          if (Constant1 == 0) {
+            IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Header.Args[0]));
+            IREmit->ReplaceNodeArgument(CodeNode, 0, CreateInlineConstant(IREmit, 0));
+            Changed = true;
+          }
+        }
+
+        break;
+      }
      case OP_CONDADDNZCV:
+      case OP_CONDSUBNZCV:
      {
        auto Op = IROp->C<IR::IROp_CondAddNZCV>();

@@ -1043,17 +1161,12 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR)
        }

        uint64_t AllOnes = IROp->Size == 8 ? 0xffff'ffff'ffff'ffffull : 0xffff'ffffull;
-#ifdef JIT_ARM64
-        bool SupportsAllOnes = true;
-#else
-        bool SupportsAllOnes = false;
-#endif

        uint64_t Constant2{};
        uint64_t Constant3{};
        if (IREmit->IsValueConstant(Op->Header.Args[2], &Constant2) &&
            IREmit->IsValueConstant(Op->Header.Args[3], &Constant3) &&
-            (Constant2 == 1 || (SupportsAllOnes && Constant2 == AllOnes)) &&
+            (Constant2 == 1 || Constant2 == AllOnes) &&
            Constant3 == 0)
        {
          IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Header.Args[2]));
@@ -1134,6 +1247,7 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR)
      case OP_OR:
      case OP_XOR:
      case OP_AND:
+      case OP_ANDWITHFLAGS:
      case OP_ANDN:
      {
        auto Op = IROp->CW<IR::IROp_Or>();
@@ -1226,7 +1340,7 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR)
        if (IREmit->IsValueConstant(Op->Direction, &Constant)) {
          IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Direction));

-          IREmit->ReplaceNodeArgument(CodeNode, Op->Direction_Index, CreateInlineConstant(IREmit, Constant & 1));
+          IREmit->ReplaceNodeArgument(CodeNode, Op->Direction_Index, CreateInlineConstant(IREmit, Constant));

          Changed = true;
        }
@@ -1240,13 +1354,29 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR)
        if (IREmit->IsValueConstant(Op->Direction, &Constant)) {
          IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Direction));

-          IREmit->ReplaceNodeArgument(CodeNode, Op->Direction_Index, CreateInlineConstant(IREmit, Constant & 1));
+          IREmit->ReplaceNodeArgument(CodeNode, Op->Direction_Index, CreateInlineConstant(IREmit, Constant));

          Changed = true;
        }
        break;
      }

+      case OP_PREFETCH:
+      {
+        auto Op = IROp->CW<IR::IROp_Prefetch>();
+
+        uint64_t Constant2{};
+        if (Op->OffsetType == MEM_OFFSET_SXTX && IREmit->IsValueConstant(Op->Offset, &Constant2)) {
+          if (IsImmMemory(Constant2, IROp->Size)) {
+            IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Offset));
+
+            IREmit->ReplaceNodeArgument(CodeNode, Op->Offset_Index, CreateInlineConstant(IREmit, Constant2));
+
+            Changed = true;
+          }
+        }
+        break;
+      }
      default:
        break;
    }
@@ -1285,8 +1415,9 @@ bool ConstProp::Run(IREmitter *IREmit) {
  return Changed;
 }

-fextl::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool InlineConstants, bool SupportsTSOImm9) {
-  return fextl::make_unique<ConstProp>(InlineConstants, SupportsTSOImm9);
+fextl::unique_ptr<FEXCore::IR::Pass>
+CreateConstProp(bool InlineConstants, bool SupportsTSOImm9, bool Is64BitMode) {
+  return fextl::make_unique<ConstProp>(InlineConstants, SupportsTSOImm9,
+                                       Is64BitMode);
 }
-
 }
@@ -5,11 +5,10 @@ tags: ir|opts
 $end_info$
 */

+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/PassManager.h"

 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/Profiler.h>

 #include <memory>
@@ -6,13 +6,14 @@ desc: Transforms ContextLoad/Store to temporaries, similar to mem2reg
 $end_info$
 */

+#include "Interface/IR/IR.h"
+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/Passes.h"
 #include "Interface/IR/PassManager.h"

 #include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/EnumOperators.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
@@ -483,6 +484,8 @@ private:
  ContextMemberInfo *RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode = nullptr);
  ContextMemberInfo *RecordAccess(ContextInfo *ClassifiedInfo, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode = nullptr);

+  bool HandleLoadFlag(FEXCore::IR::IREmitter *IREmit, ContextInfo *LocalInfo, FEXCore::IR::OrderedNode *CodeNode, unsigned Flag);
+
  // Classify context loads and stores.
  bool ClassifyContextLoad(FEXCore::IR::IREmitter *IREmit, ContextInfo *LocalInfo, FEXCore::IR::RegisterClassType Class, uint32_t Offset, uint8_t Size, FEXCore::IR::OrderedNode *CodeNode, FEXCore::IR::NodeIterator BlockEnd);
  bool ClassifyContextStore(FEXCore::IR::IREmitter *IREmit, ContextInfo *LocalInfo, FEXCore::IR::RegisterClassType Class, uint32_t Offset, uint8_t Size, FEXCore::IR::OrderedNode *CodeNode, FEXCore::IR::OrderedNode *ValueNode);
@@ -544,9 +547,42 @@ bool RCLSE::ClassifyContextLoad(FEXCore::IR::IREmitter *IREmit, ContextInfo *Loc

 bool RCLSE::ClassifyContextStore(FEXCore::IR::IREmitter *IREmit, ContextInfo *LocalInfo, FEXCore::IR::RegisterClassType Class, uint32_t Offset, uint8_t Size, FEXCore::IR::OrderedNode *CodeNode, FEXCore::IR::OrderedNode *ValueNode) {
  auto Info = FindMemberInfo(LocalInfo, Offset, Size);
-  Info = RecordAccess(Info, Class, Offset, Size, LastAccessType::WRITE, ValueNode, CodeNode);
-  // TODO: Optimize redundant stores.
-  // ContextMemberInfo PreviousMemberInfoCopy = *Info;
+  ContextMemberInfo PreviousMemberInfoCopy = *Info;
+  RecordAccess(Info, Class, Offset, Size, LastAccessType::WRITE, ValueNode,
+               CodeNode);
+
+  if (PreviousMemberInfoCopy.AccessRegClass == Info->AccessRegClass &&
+      PreviousMemberInfoCopy.AccessOffset == Info->AccessOffset &&
+      PreviousMemberInfoCopy.AccessSize == Size &&
+      PreviousMemberInfoCopy.Accessed == LastAccessType::WRITE) {
+    // This optimizes redundant stores with no intervening load
+    IREmit->Remove(PreviousMemberInfoCopy.StoreNode);
+    return true;
+  }
+
+  // TODO: Optimize the case of partial stores.
+  return false;
+}
+
+bool RCLSE::HandleLoadFlag(FEXCore::IR::IREmitter *IREmit, ContextInfo *LocalInfo, FEXCore::IR::OrderedNode *CodeNode, unsigned Flag) {
+  const auto FlagOffset = offsetof(FEXCore::Core::CPUState, flags[Flag]);
+  auto Info = FindMemberInfo(LocalInfo, FlagOffset, 1);
+  LastAccessType LastAccess = Info->Accessed;
+  auto LastValueNode = Info->ValueNode;
+
+  if (IsWriteAccess(LastAccess)) { // 1 byte so always a full write
+    // If the last store matches this load value then we can replace the loaded value with the previous valid one
+    IREmit->SetWriteCursor(CodeNode);
+    IREmit->ReplaceAllUsesWith(CodeNode, LastValueNode);
+    RecordAccess(Info, FEXCore::IR::GPRClass, FlagOffset, 1, LastAccessType::READ, LastValueNode);
+    return true;
+  }
+  else if (IsReadAccess(LastAccess)) {
+    IREmit->ReplaceAllUsesWith(CodeNode, LastValueNode);
+    RecordAccess(Info, FEXCore::IR::GPRClass, FlagOffset, 1, LastAccessType::READ, LastValueNode);
+    return true;
+  }
+
  return false;
 }

@@ -659,23 +695,11 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
      }
      else if (IROp->Op == OP_LOADFLAG) {
        const auto Op = IROp->CW<IR::IROp_LoadFlag>();
-        const auto FlagOffset = offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag;
-        auto Info = FindMemberInfo(&LocalInfo, FlagOffset, 1);
-        LastAccessType LastAccess = Info->Accessed;
-        OrderedNode *LastValueNode = Info->ValueNode;

-        if (IsWriteAccess(LastAccess)) { // 1 byte so always a full write
-          // If the last store matches this load value then we can replace the loaded value with the previous valid one
-          IREmit->SetWriteCursor(CodeNode);
-          IREmit->ReplaceAllUsesWith(CodeNode, LastValueNode);
-          RecordAccess(Info, FEXCore::IR::GPRClass, FlagOffset, 1, LastAccessType::READ, LastValueNode);
-          Changed = true;
-        }
-        else if (IsReadAccess(LastAccess)) {
-          IREmit->ReplaceAllUsesWith(CodeNode, LastValueNode);
-          RecordAccess(Info, FEXCore::IR::GPRClass, FlagOffset, 1, LastAccessType::READ, LastValueNode);
-          Changed = true;
-        }
+        Changed |= HandleLoadFlag(IREmit, &LocalInfo, CodeNode, Op->Flag);
+      }
+      else if (IROp->Op == OP_LOADDF) {
+        Changed |= HandleLoadFlag(IREmit, &LocalInfo, CodeNode, X86State::RFLAG_DF_RAW_LOC);
      }
      else if (IROp->Op == OP_SYSCALL ||
               IROp->Op == OP_INLINESYSCALL) {
@@ -6,12 +6,12 @@ desc: Cross block store-after-store elimination
 $end_info$
 */

+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/PassManager.h"

 #include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
 #include <FEXCore/fextl/unordered_map.h>
@@ -211,6 +211,10 @@ bool DeadStoreElimination::Run(IREmitter *IREmit) {
          auto& BlockInfo = InfoMap[BlockNode];

          BlockInfo.flag.reads |= 1UL << Op->Flag;
+        } else if (IROp->Op == OP_LOADDF) {
+          auto& BlockInfo = InfoMap[BlockNode];
+
+          BlockInfo.flag.reads |= 1UL << X86State::RFLAG_DF_RAW_LOC;
        } else if (IROp->Op == OP_STOREREGISTER) {
          auto Op = IROp->C<IR::IROp_StoreRegister>();

@@ -6,12 +6,11 @@ desc: Sorts the ssa storage in memory, needed for RA and others
 $end_info$
 */

+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/PassManager.h"
 #include "Interface/Core/OpcodeDispatcher.h"

 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>
 #include <FEXCore/Utils/Profiler.h>
@@ -6,6 +6,8 @@ desc: Prints IR
 $end_info$
 */

+#include "Interface/IR/IR.h"
+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/PassManager.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 #include "Interface/Core/OpcodeDispatcher.h"
@@ -6,14 +6,14 @@ desc: Sanity checking pass
 $end_info$
 */

+#include "Interface/IR/IR.h"
+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/PassManager.h"
+#include "Interface/IR/RegisterAllocationData.h"
 #include "Interface/IR/Passes/IRValidation.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"

 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
 #include <FEXCore/fextl/sstream.h>
@@ -7,11 +7,10 @@ $end_info$
 */

 #include "Interface/Core/CPUID.h"
+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/PassManager.h"

 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/Utils/Profiler.h>

@@ -6,10 +6,9 @@ desc: Long divide elimination pass
 $end_info$
 */

+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/PassManager.h"
 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/Profiler.h>

 #include <memory>
@@ -1,12 +1,13 @@
 // SPDX-License-Identifier: MIT
+
+#include "Interface/IR/IR.h"
+#include "Interface/IR/IREmitter.h"
 #include "Interface/IR/PassManager.h"
+#include "Interface/IR/RegisterAllocationData.h"
 #include "Interface/IR/Passes/IRValidation.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"

 #include <FEXCore/IR/IR.h>
-#include <FEXCore/IR/IREmitter.h>
-#include <FEXCore/IR/IntrusiveIRList.h>
-#include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/Utils/Profiler.h>
 #include <FEXCore/fextl/deque.h>
 #include <FEXCore/fextl/fmt.h>