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InstCountCI: Update
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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Alyssa Rosenzweig committed
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@@ -472,75 +472,47 @@
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]
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},
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"pdep eax, ebx, ecx": {
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"ExpectedInstructionCount": 29,
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"ExpectedInstructionCount": 14,
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"Comment": [
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"Map 2 0b11 0xf5 32-bit"
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],
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"ExpectedArm64ASM": [
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"mov w20, w7",
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"mov w21, w5",
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"cbz w21, #+0x68",
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"mov w3, wzr",
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"mrs x0, nzcv",
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"str w0, [x28, #728]",
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"stp x4, x5, [x28, #8]",
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"str x6, [x28, #24]",
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"mov w4, w20",
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"mov w5, w21",
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"mov w6, wzr",
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"rbit w0, w5",
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"clz w0, w0",
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"lsr w1, w4, w3",
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"and w1, w1, #0x1",
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"sub w2, w5, #0x1 (1)",
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"add w3, w3, #0x1 (1)",
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"ands w5, w5, w2",
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"lsl w0, w1, w0",
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"orr w6, w6, w0",
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"b.ne #-0x24",
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"mov w3, w6",
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"ldr w4, [x28, #728]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #8]",
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"ldr x6, [x28, #24]",
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"mov w4, w3",
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"b #+0x8",
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"mov w4, wzr"
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"mov x0, x7",
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"mov x1, x5",
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"mov w4, #0x0",
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"cbz w5, #+0x2c",
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"neg w2, w1",
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"and w2, w2, w1",
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"sbfx w3, w0, #0, #1",
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"eor w1, w1, w2",
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"and w2, w3, w2",
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"neg w3, w1",
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"orr w4, w4, w2",
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"lsr w0, w0, #1",
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"and w2, w1, w3",
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"cbnz w2, #-0x1c"
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]
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},
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"pdep rax, rbx, rcx": {
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"ExpectedInstructionCount": 27,
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"ExpectedInstructionCount": 14,
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"Comment": [
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"Map 2 0b11 0xf5 64-bit"
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],
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"ExpectedArm64ASM": [
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"cbz x5, #+0x68",
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"mov x3, xzr",
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"mrs x0, nzcv",
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"str w0, [x28, #728]",
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"stp x4, x5, [x28, #8]",
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"str x6, [x28, #24]",
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"mov x4, x7",
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"mov x5, x5",
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"mov x6, xzr",
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"rbit x0, x5",
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"clz x0, x0",
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"lsr x1, x4, x3",
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"and x1, x1, #0x1",
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"sub x2, x5, #0x1 (1)",
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"add x3, x3, #0x1 (1)",
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"ands x5, x5, x2",
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"lsl x0, x1, x0",
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"orr x6, x6, x0",
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"b.ne #-0x24",
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"mov x3, x6",
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"ldr w4, [x28, #728]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #8]",
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"ldr x6, [x28, #24]",
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"mov x4, x3",
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"b #+0x8",
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"mov x4, xzr"
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"mov x0, x7",
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"mov x1, x5",
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"mov x4, #0x0",
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"cbz x5, #+0x2c",
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"neg x2, x1",
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"and x2, x2, x1",
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"sbfx x3, x0, #0, #1",
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"eor x1, x1, x2",
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"and x2, x3, x2",
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"neg x3, x1",
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"orr x4, x4, x2",
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"lsr x0, x0, #1",
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"and x2, x1, x3",
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"cbnz x2, #-0x1c"
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]
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},
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"bextr eax, ebx, ecx": {
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@@ -3329,75 +3329,47 @@
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]
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},
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"pdep eax, ebx, ecx": {
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"ExpectedInstructionCount": 29,
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"ExpectedInstructionCount": 14,
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"Comment": [
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"Map 2 0b11 0xf5 32-bit"
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],
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"ExpectedArm64ASM": [
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"mov w20, w7",
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"mov w21, w5",
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"cbz w21, #+0x68",
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"mov w3, wzr",
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"mrs x0, nzcv",
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"str w0, [x28, #728]",
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"stp x4, x5, [x28, #8]",
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"str x6, [x28, #24]",
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"mov w4, w20",
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"mov w5, w21",
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"mov w6, wzr",
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"rbit w0, w5",
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"clz w0, w0",
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"lsr w1, w4, w3",
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"and w1, w1, #0x1",
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"sub w2, w5, #0x1 (1)",
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"add w3, w3, #0x1 (1)",
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"ands w5, w5, w2",
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"lsl w0, w1, w0",
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"orr w6, w6, w0",
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"b.ne #-0x24",
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"mov w3, w6",
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"ldr w4, [x28, #728]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #8]",
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"ldr x6, [x28, #24]",
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"mov w4, w3",
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"b #+0x8",
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"mov w4, wzr"
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"mov x0, x7",
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"mov x1, x5",
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"mov w4, #0x0",
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"cbz w5, #+0x2c",
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"neg w2, w1",
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"and w2, w2, w1",
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"sbfx w3, w0, #0, #1",
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"eor w1, w1, w2",
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"and w2, w3, w2",
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"neg w3, w1",
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"orr w4, w4, w2",
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"lsr w0, w0, #1",
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"and w2, w1, w3",
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"cbnz w2, #-0x1c"
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]
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},
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"pdep rax, rbx, rcx": {
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"ExpectedInstructionCount": 27,
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"ExpectedInstructionCount": 14,
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"Comment": [
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"Map 2 0b11 0xf5 64-bit"
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],
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"ExpectedArm64ASM": [
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"cbz x5, #+0x68",
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"mov x3, xzr",
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"mrs x0, nzcv",
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"str w0, [x28, #728]",
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"stp x4, x5, [x28, #8]",
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"str x6, [x28, #24]",
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"mov x4, x7",
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"mov x5, x5",
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"mov x6, xzr",
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"rbit x0, x5",
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"clz x0, x0",
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"lsr x1, x4, x3",
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"and x1, x1, #0x1",
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"sub x2, x5, #0x1 (1)",
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"add x3, x3, #0x1 (1)",
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"ands x5, x5, x2",
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"lsl x0, x1, x0",
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"orr x6, x6, x0",
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"b.ne #-0x24",
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"mov x3, x6",
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"ldr w4, [x28, #728]",
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"msr nzcv, x4",
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"ldp x4, x5, [x28, #8]",
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"ldr x6, [x28, #24]",
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"mov x4, x3",
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"b #+0x8",
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"mov x4, xzr"
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"mov x0, x7",
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"mov x1, x5",
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"mov x4, #0x0",
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"cbz x5, #+0x2c",
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"neg x2, x1",
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"and x2, x2, x1",
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"sbfx x3, x0, #0, #1",
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"eor x1, x1, x2",
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"and x2, x3, x2",
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"neg x3, x1",
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"orr x4, x4, x2",
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"lsr x0, x0, #1",
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"and x2, x1, x3",
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"cbnz x2, #-0x1c"
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]
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},
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"mulx eax, ebx, ecx": {
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