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https://github.com/FEX-Emu/FEX.git
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InstCountCI: add hot scalar FMOD block
both AFP and non-AFP versions, since this is greatly affected by AFP opts. pulled from #2563 Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed
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commit
aac7fa9b58
2 files changed
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@@ -7,7 +7,8 @@
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],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256"
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"SVE256",
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"AFP"
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]
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},
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"Instructions": {
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@@ -35,6 +36,141 @@
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"mov x26, x6",
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"cmn x20, x5"
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]
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},
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"FMOD scalar loop": {
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"ExpectedInstructionCount": 90,
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"x86Insts": [
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"mov esi, ecx",
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"mov rdx, rbp",
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"mov rax, rbx",
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"movss xmm2, dword [rdx]",
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"add rax, 0x20",
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"mulss xmm2, xmm0",
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"add rdx, 0x20",
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"addss xmm2, dword [rax-0x20]",
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"movss dword [rax-0x20], xmm2",
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"movss xmm2, dword [rdx-0x1c]",
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"mulss xmm2, xmm1",
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"addss xmm2, dword [rax-0x1c]",
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"movss dword [rax-0x1c], xmm2",
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"movss xmm2, dword [rdx-0x18]",
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"mulss xmm2, xmm0",
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"addss xmm2, dword [rax-0x18]",
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"movss dword [rax-0x18], xmm2",
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"movss xmm2, dword [rdx-0x14]",
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"mulss xmm2, xmm1",
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"addss xmm2, dword [rax-0x14]",
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"movss dword [rax-0x14], xmm2",
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"movss xmm2, dword [rdx-0x10]",
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"mulss xmm2, xmm0",
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"addss xmm2, dword [rax-0x10]",
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"movss dword [rax-0x10], xmm2",
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"movss xmm2, dword [rdx-0xc]",
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"mulss xmm2, xmm1",
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"addss xmm2, dword [rax-0xc]",
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"movss dword [rax-0xc], xmm2",
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"movss xmm2, dword [rdx-0x8]",
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"mulss xmm2, xmm0",
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"addss xmm2, dword [rax-0x8]",
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"movss dword [rax-0x8], xmm2",
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"movss xmm2, dword [rdx-0x4]",
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"mulss xmm2, xmm1",
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"addss xmm2, dword [rax-0x4]",
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"movss dword [rax-0x4], xmm2",
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"sub esi, 0x1"
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],
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"ExpectedArm64ASM": [
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"mov w20, w5",
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"mov x10, x20",
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"mov x6, x9",
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"mov x4, x7",
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"ldr s18, [x6]",
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"add x4, x4, #0x20 (32)",
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"fmul s0, s18, s16",
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"mov v18.s[0], v0.s[0]",
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"add x6, x6, #0x20 (32)",
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"sub x21, x4, #0x20 (32)",
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"ldr s2, [x21]",
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"fadd s0, s18, s2",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x20 (32)",
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"str s18, [x21]",
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"sub x21, x6, #0x1c (28)",
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"ldr s18, [x21]",
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"fmul s0, s18, s17",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x1c (28)",
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"ldr s2, [x21]",
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"fadd s0, s18, s2",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x1c (28)",
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"str s18, [x21]",
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"sub x21, x6, #0x18 (24)",
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"ldr s18, [x21]",
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"fmul s0, s18, s16",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x18 (24)",
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"ldr s2, [x21]",
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"fadd s0, s18, s2",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x18 (24)",
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"str s18, [x21]",
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"sub x21, x6, #0x14 (20)",
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"ldr s18, [x21]",
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"fmul s0, s18, s17",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x14 (20)",
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"ldr s2, [x21]",
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"fadd s0, s18, s2",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x14 (20)",
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"str s18, [x21]",
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"sub x21, x6, #0x10 (16)",
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"ldr s18, [x21]",
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"fmul s0, s18, s16",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x10 (16)",
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"ldr s2, [x21]",
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"fadd s0, s18, s2",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x10 (16)",
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"str s18, [x21]",
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"sub x21, x6, #0xc (12)",
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"ldr s18, [x21]",
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"fmul s0, s18, s17",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0xc (12)",
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"ldr s2, [x21]",
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"fadd s0, s18, s2",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0xc (12)",
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"str s18, [x21]",
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"sub x21, x6, #0x8 (8)",
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"ldr s18, [x21]",
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"fmul s0, s18, s16",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x8 (8)",
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"ldr s2, [x21]",
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"fadd s0, s18, s2",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x8 (8)",
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"str s18, [x21]",
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"sub x21, x6, #0x4 (4)",
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"ldr s18, [x21]",
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"fmul s0, s18, s17",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x4 (4)",
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"ldr s2, [x21]",
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"fadd s0, s18, s2",
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"mov v18.s[0], v0.s[0]",
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"sub x21, x4, #0x4 (4)",
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"str s18, [x21]",
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"sub w10, w20, #0x1 (1)",
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"mov x27, x20",
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"mov x26, x10",
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"cmp w20, #0x1 (1)",
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"cfinv"
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]
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}
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}
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}
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@@ -0,0 +1,135 @@
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{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [
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"FLAGM",
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"FLAGM2",
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"AFP"
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],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256"
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]
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},
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"Instructions": {
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"FMOD scalar loop": {
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"ExpectedInstructionCount": 74,
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"x86Insts": [
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"mov esi, ecx",
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"mov rdx, rbp",
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"mov rax, rbx",
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"movss xmm2, dword [rdx]",
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"add rax, 0x20",
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"mulss xmm2, xmm0",
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"add rdx, 0x20",
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"addss xmm2, dword [rax-0x20]",
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"movss dword [rax-0x20], xmm2",
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"movss xmm2, dword [rdx-0x1c]",
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"mulss xmm2, xmm1",
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"addss xmm2, dword [rax-0x1c]",
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"movss dword [rax-0x1c], xmm2",
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"movss xmm2, dword [rdx-0x18]",
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"mulss xmm2, xmm0",
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"addss xmm2, dword [rax-0x18]",
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"movss dword [rax-0x18], xmm2",
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"movss xmm2, dword [rdx-0x14]",
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"mulss xmm2, xmm1",
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"addss xmm2, dword [rax-0x14]",
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"movss dword [rax-0x14], xmm2",
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"movss xmm2, dword [rdx-0x10]",
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"mulss xmm2, xmm0",
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"addss xmm2, dword [rax-0x10]",
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"movss dword [rax-0x10], xmm2",
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"movss xmm2, dword [rdx-0xc]",
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"mulss xmm2, xmm1",
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"addss xmm2, dword [rax-0xc]",
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"movss dword [rax-0xc], xmm2",
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"movss xmm2, dword [rdx-0x8]",
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"mulss xmm2, xmm0",
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"addss xmm2, dword [rax-0x8]",
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"movss dword [rax-0x8], xmm2",
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"movss xmm2, dword [rdx-0x4]",
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"mulss xmm2, xmm1",
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"addss xmm2, dword [rax-0x4]",
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"movss dword [rax-0x4], xmm2",
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"sub esi, 0x1"
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],
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"ExpectedArm64ASM": [
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"mov w20, w5",
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"mov x10, x20",
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"mov x6, x9",
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"mov x4, x7",
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"ldr s18, [x6]",
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"add x4, x4, #0x20 (32)",
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"fmul s18, s18, s16",
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"add x6, x6, #0x20 (32)",
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"sub x21, x4, #0x20 (32)",
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"ldr s2, [x21]",
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"fadd s18, s18, s2",
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"sub x21, x4, #0x20 (32)",
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"str s18, [x21]",
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"sub x21, x6, #0x1c (28)",
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"ldr s18, [x21]",
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"fmul s18, s18, s17",
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"sub x21, x4, #0x1c (28)",
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"ldr s2, [x21]",
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"fadd s18, s18, s2",
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"sub x21, x4, #0x1c (28)",
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"str s18, [x21]",
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"sub x21, x6, #0x18 (24)",
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"ldr s18, [x21]",
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"fmul s18, s18, s16",
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"sub x21, x4, #0x18 (24)",
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"ldr s2, [x21]",
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"fadd s18, s18, s2",
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"sub x21, x4, #0x18 (24)",
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"str s18, [x21]",
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"sub x21, x6, #0x14 (20)",
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"ldr s18, [x21]",
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"fmul s18, s18, s17",
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"sub x21, x4, #0x14 (20)",
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"ldr s2, [x21]",
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"fadd s18, s18, s2",
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"sub x21, x4, #0x14 (20)",
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"str s18, [x21]",
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"sub x21, x6, #0x10 (16)",
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"ldr s18, [x21]",
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"fmul s18, s18, s16",
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"sub x21, x4, #0x10 (16)",
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"ldr s2, [x21]",
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"fadd s18, s18, s2",
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"sub x21, x4, #0x10 (16)",
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"str s18, [x21]",
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"sub x21, x6, #0xc (12)",
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"ldr s18, [x21]",
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"fmul s18, s18, s17",
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"sub x21, x4, #0xc (12)",
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"ldr s2, [x21]",
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"fadd s18, s18, s2",
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"sub x21, x4, #0xc (12)",
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"str s18, [x21]",
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"sub x21, x6, #0x8 (8)",
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"ldr s18, [x21]",
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"fmul s18, s18, s16",
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"sub x21, x4, #0x8 (8)",
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"ldr s2, [x21]",
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"fadd s18, s18, s2",
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"sub x21, x4, #0x8 (8)",
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"str s18, [x21]",
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"sub x21, x6, #0x4 (4)",
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"ldr s18, [x21]",
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"fmul s18, s18, s17",
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"sub x21, x4, #0x4 (4)",
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"ldr s2, [x21]",
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"fadd s18, s18, s2",
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"sub x21, x4, #0x4 (4)",
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"str s18, [x21]",
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"sub w10, w20, #0x1 (1)",
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"mov x27, x20",
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"mov x26, x10",
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"cmp w20, #0x1 (1)",
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"cfinv"
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]
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}
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}
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}
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