mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 09:00:17 +02:00
InstCountCI: Update for segment changes
This commit is contained in:
Ryan Houdek committed
1 parent
ccf1402fe6
commit
45587278c9
23 files changed
+2638
-2678
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@@ -55,7 +55,7 @@
|
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"0x66 0x0f 0x3a 0xdf"
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],
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"ExpectedArm64ASM": [
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||||
"ldr q2, [x28, #2208]",
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||||
"ldr q2, [x28, #2080]",
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||||
"movi v3.2d, #0x0",
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"mov v16.16b, v17.16b",
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"unimplemented (Unimplemented)",
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@@ -68,7 +68,7 @@
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"0x66 0x0f 0x3a 0xdf"
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],
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"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2208]",
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||||
"ldr q2, [x28, #2080]",
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||||
"movi v3.2d, #0x0",
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"mov v16.16b, v17.16b",
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"unimplemented (Unimplemented)",
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@@ -199,10 +199,10 @@
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||||
"ldr q19, [x11, #272]",
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"ldr q24, [x11]",
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||||
"ldr q23, [x11, #16]",
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||||
"ldr x0, [x28, #1816]",
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||||
"ldr x0, [x28, #1688]",
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||||
"ldr q2, [x0, #2832]",
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"tbl v16.16b, {v18.16b}, v2.16b",
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"ldr x0, [x28, #1816]",
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"ldr x0, [x28, #1688]",
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"ldr q3, [x0, #432]",
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"tbl v18.16b, {v19.16b}, v3.16b",
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"ldr q22, [x11, #32]",
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@@ -346,7 +346,7 @@
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"mov v4.s[1], w21",
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"mov v20.16b, v4.16b",
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"mov v20.s[0], w23",
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"ldr x0, [x28, #1816]",
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"ldr x0, [x28, #1688]",
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"ldr q4, [x0, #224]",
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"tbl v16.16b, {v16.16b}, v4.16b",
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"mov w20, v20.s[3]",
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@@ -1200,7 +1200,7 @@
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"ExpectedInstructionCount": 58,
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||||
"Comment": "GROUP15 0x0F 0xAE /0",
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"ExpectedArm64ASM": [
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"ldrh w20, [x28, #1152]",
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"ldrh w20, [x28, #1024]",
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||||
"strh w20, [x4]",
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"mov w20, #0x0",
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"ldrb w21, [x28, #747]",
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@@ -1214,7 +1214,7 @@
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"orr x20, x20, x23, lsl #10",
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"orr x20, x20, x24, lsl #14",
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"strh w20, [x4, #2]",
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"ldrb w20, [x28, #1154]",
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"ldrb w20, [x28, #1026]",
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"strb w20, [x4, #4]",
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||||
"ldr q2, [x28, #768]",
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"str q2, [x4, #32]",
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@@ -1279,7 +1279,7 @@
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"Comment": "GROUP15 0x0F 0xAE /1",
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"ExpectedArm64ASM": [
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"ldrh w20, [x4]",
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"strh w20, [x28, #1152]",
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"strh w20, [x28, #1024]",
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"ldrh w20, [x4, #2]",
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"ubfx w21, w20, #11, #3",
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"strb w21, [x28, #747]",
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@@ -1292,7 +1292,7 @@
|
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"strb w23, [x28, #746]",
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||||
"strb w20, [x28, #750]",
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"ldrb w20, [x4, #4]",
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"strb w20, [x28, #1154]",
|
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"strb w20, [x28, #1026]",
|
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"ldr q2, [x4, #32]",
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"str q2, [x28, #768]",
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"ldr q2, [x4, #48]",
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@@ -1417,7 +1417,7 @@
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"ubfx x22, x20, #0, #1",
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"cbnz x22, #+0x8",
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"b #+0x84",
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"ldrh w22, [x28, #1152]",
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"ldrh w22, [x28, #1024]",
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"strh w22, [x21]",
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"mov w22, #0x0",
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"ldrb w23, [x28, #747]",
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@@ -1431,7 +1431,7 @@
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"orr x22, x22, x25, lsl #10",
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"orr x22, x22, x30, lsl #14",
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"strh w22, [x21, #2]",
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"ldrb w22, [x28, #1154]",
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"ldrb w22, [x28, #1026]",
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||||
"strb w22, [x21, #4]",
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"ldr q2, [x28, #768]",
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"str q2, [x21, #32]",
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@@ -1502,7 +1502,7 @@
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"cbnz x22, #+0x8",
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"b #+0x84",
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"ldrh w22, [x20]",
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"strh w22, [x28, #1152]",
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"strh w22, [x28, #1024]",
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"ldrh w22, [x20, #2]",
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"ubfx w23, w22, #11, #3",
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"strb w23, [x28, #747]",
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@@ -1515,7 +1515,7 @@
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"strb w25, [x28, #746]",
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"strb w22, [x28, #750]",
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"ldrb w22, [x20, #4]",
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"strb w22, [x28, #1154]",
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"strb w22, [x28, #1026]",
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"ldr q2, [x20, #32]",
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"str q2, [x28, #768]",
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"ldr q2, [x20, #48]",
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@@ -1535,13 +1535,13 @@
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"b #+0x4c",
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"mov w22, #0x0",
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"mov w23, #0x37f",
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"strh w23, [x28, #1152]",
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"strh w23, [x28, #1024]",
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"strb w22, [x28, #747]",
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"strb w22, [x28, #744]",
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"strb w22, [x28, #745]",
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"strb w22, [x28, #746]",
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"strb w22, [x28, #750]",
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"strb w22, [x28, #1154]",
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"strb w22, [x28, #1026]",
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"movi v2.2d, #0x0",
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"str q2, [x28, #768]",
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"str q2, [x28, #784]",
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@@ -42,8 +42,8 @@
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"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
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"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
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"mov w1, w5",
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"ldr x0, [x28, #1240]",
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"ldr x2, [x28, #1256]",
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"ldr x0, [x28, #1112]",
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"ldr x2, [x28, #1128]",
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"blr x2",
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"ldr w4, [x28, #728]",
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"msr nzcv, x4",
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@@ -85,7 +85,7 @@
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"str w0, [x28, #728]",
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"str x8, [x28, #40]",
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"mov w0, #0x100",
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"str x0, [x28, #1184]",
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"str x0, [x28, #1056]",
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"sub sp, sp, #0x10 (16)",
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"mov w8, #0xa8",
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"mov x0, sp",
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@@ -96,7 +96,7 @@
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"ldr w8, [x28, #728]",
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"msr nzcv, x8",
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"ldr x8, [x28, #40]",
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"str xzr, [x28, #1184]",
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"str xzr, [x28, #1056]",
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"orr x5, x0, x1, lsl #12"
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]
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}
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Load diff
File diff suppressed because it is too large.
Load diff
@@ -624,7 +624,7 @@
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||||
"0x66 0x0f 0x38 0x41"
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],
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"ExpectedArm64ASM": [
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||||
"ldr q2, [x28, #2096]",
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||||
"ldr q2, [x28, #1968]",
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||||
"zip1 v3.8h, v2.8h, v17.8h",
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"zip2 v2.8h, v2.8h, v17.8h",
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||||
"umin v2.4s, v3.4s, v2.4s",
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||||
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@@ -315,7 +315,7 @@
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||||
"0x66 0x0f 0x3a 0x0c"
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],
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"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2224]",
|
||||
"ldr q2, [x28, #2096]",
|
||||
"tbx v16.16b, {v17.16b}, v2.16b"
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]
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||||
},
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||||
@@ -325,7 +325,7 @@
|
||||
"0x66 0x0f 0x3a 0x0c"
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||||
],
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||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2240]",
|
||||
"ldr q2, [x28, #2112]",
|
||||
"tbx v16.16b, {v17.16b}, v2.16b"
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]
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||||
},
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||||
@@ -344,7 +344,7 @@
|
||||
"0x66 0x0f 0x3a 0x0c"
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],
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||||
"ExpectedArm64ASM": [
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||||
"ldr q2, [x28, #2256]",
|
||||
"ldr q2, [x28, #2128]",
|
||||
"tbx v16.16b, {v17.16b}, v2.16b"
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||||
]
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||||
},
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||||
@@ -364,7 +364,7 @@
|
||||
"0x66 0x0f 0x3a 0x0c"
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||||
],
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||||
"ExpectedArm64ASM": [
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||||
"ldr q2, [x28, #2272]",
|
||||
"ldr q2, [x28, #2144]",
|
||||
"tbx v16.16b, {v17.16b}, v2.16b"
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||||
]
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||||
},
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||||
@@ -383,7 +383,7 @@
|
||||
"0x66 0x0f 0x3a 0x0c"
|
||||
],
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||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2288]",
|
||||
"ldr q2, [x28, #2160]",
|
||||
"tbx v16.16b, {v17.16b}, v2.16b"
|
||||
]
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||||
},
|
||||
@@ -393,7 +393,7 @@
|
||||
"0x66 0x0f 0x3a 0x0c"
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||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2304]",
|
||||
"ldr q2, [x28, #2176]",
|
||||
"tbx v16.16b, {v17.16b}, v2.16b"
|
||||
]
|
||||
},
|
||||
@@ -462,7 +462,7 @@
|
||||
"0x66 0x0f 0x3a 0x0e"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1848]",
|
||||
"ldr x0, [x28, #1720]",
|
||||
"ldr q2, [x0, #3440]",
|
||||
"tbx v16.16b, {v17.16b}, v2.16b"
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||||
]
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||||
|
||||
@@ -2674,50 +2674,38 @@
|
||||
"Comment": "0x8e"
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||||
},
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||||
"mov es, ax": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "0x8e",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxth w20, w4",
|
||||
"strh w20, [x28, #136]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #3",
|
||||
"ldr x20, [x0, #896]",
|
||||
"lsr x21, x20, #32",
|
||||
"and w22, w21, #0xff000000",
|
||||
"orr w20, w22, w20, lsr #16",
|
||||
"bfi w20, w21, #16, #8",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
"ldr w20, [x0, #896]",
|
||||
"str w20, [x28, #152]"
|
||||
]
|
||||
},
|
||||
"mov ss, ax": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "0x8e",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxth w20, w4",
|
||||
"strh w20, [x28, #140]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #3",
|
||||
"ldr x20, [x0, #896]",
|
||||
"lsr x21, x20, #32",
|
||||
"and w22, w21, #0xff000000",
|
||||
"orr w20, w22, w20, lsr #16",
|
||||
"bfi w20, w21, #16, #8",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
"ldr w20, [x0, #896]",
|
||||
"str w20, [x28, #160]"
|
||||
]
|
||||
},
|
||||
"mov ds, ax": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "0x8e",
|
||||
"ExpectedArm64ASM": [
|
||||
"uxth w20, w4",
|
||||
"strh w20, [x28, #142]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #3",
|
||||
"ldr x20, [x0, #896]",
|
||||
"lsr x21, x20, #32",
|
||||
"and w22, w21, #0xff000000",
|
||||
"orr w20, w22, w20, lsr #16",
|
||||
"bfi w20, w21, #16, #8",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
"ldr w20, [x0, #896]",
|
||||
"str w20, [x28, #164]"
|
||||
]
|
||||
},
|
||||
|
||||
@@ -3052,7 +3052,7 @@
|
||||
"mov x0, x6",
|
||||
"mov x1, x20",
|
||||
"mov x2, x7",
|
||||
"ldr x3, [x28, #2352]",
|
||||
"ldr x3, [x28, #2224]",
|
||||
"str x30, [sp, #-16]!",
|
||||
"blr x3",
|
||||
"ldr x30, [sp], #16",
|
||||
@@ -3063,7 +3063,7 @@
|
||||
"mov x0, x6",
|
||||
"mov x1, x20",
|
||||
"mov x2, x7",
|
||||
"ldr x3, [x28, #2368]",
|
||||
"ldr x3, [x28, #2240]",
|
||||
"str x30, [sp, #-16]!",
|
||||
"blr x3",
|
||||
"ldr x30, [sp], #16",
|
||||
@@ -3124,7 +3124,7 @@
|
||||
"mov x0, x6",
|
||||
"mov x1, x20",
|
||||
"mov x2, x7",
|
||||
"ldr x3, [x28, #2360]",
|
||||
"ldr x3, [x28, #2232]",
|
||||
"str x30, [sp, #-16]!",
|
||||
"blr x3",
|
||||
"ldr x30, [sp], #16",
|
||||
@@ -3137,7 +3137,7 @@
|
||||
"mov x0, x6",
|
||||
"mov x1, x20",
|
||||
"mov x2, x7",
|
||||
"ldr x3, [x28, #2376]",
|
||||
"ldr x3, [x28, #2248]",
|
||||
"str x30, [sp, #-16]!",
|
||||
"blr x3",
|
||||
"ldr x30, [sp], #16",
|
||||
|
||||
@@ -19,19 +19,15 @@
|
||||
]
|
||||
},
|
||||
"pop es": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0x07",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr w20, [x8]",
|
||||
"add x8, x8, #0x4 (4)",
|
||||
"strh w20, [x28, #136]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #3",
|
||||
"ldr x20, [x0, #896]",
|
||||
"lsr x21, x20, #32",
|
||||
"and w22, w21, #0xff000000",
|
||||
"orr w20, w22, w20, lsr #16",
|
||||
"bfi w20, w21, #16, #8",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
"ldr w20, [x0, #896]",
|
||||
"str w20, [x28, #152]"
|
||||
]
|
||||
},
|
||||
@@ -52,19 +48,15 @@
|
||||
]
|
||||
},
|
||||
"pop ss": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0x17",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr w20, [x8]",
|
||||
"add x8, x8, #0x4 (4)",
|
||||
"strh w20, [x28, #140]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #3",
|
||||
"ldr x20, [x0, #896]",
|
||||
"lsr x21, x20, #32",
|
||||
"and w22, w21, #0xff000000",
|
||||
"orr w20, w22, w20, lsr #16",
|
||||
"bfi w20, w21, #16, #8",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
"ldr w20, [x0, #896]",
|
||||
"str w20, [x28, #160]"
|
||||
]
|
||||
},
|
||||
@@ -77,19 +69,15 @@
|
||||
]
|
||||
},
|
||||
"pop ds": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0x1f",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr w20, [x8]",
|
||||
"add x8, x8, #0x4 (4)",
|
||||
"strh w20, [x28, #142]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #3",
|
||||
"ldr x20, [x0, #896]",
|
||||
"lsr x21, x20, #32",
|
||||
"and w22, w21, #0xff000000",
|
||||
"orr w20, w22, w20, lsr #16",
|
||||
"bfi w20, w21, #16, #8",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
"ldr w20, [x0, #896]",
|
||||
"str w20, [x28, #164]"
|
||||
]
|
||||
},
|
||||
|
||||
@@ -23,7 +23,7 @@
|
||||
"Comment": "0x0f 0x0b",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x0",
|
||||
"strb w20, [x28, #1154]"
|
||||
"strb w20, [x28, #1026]"
|
||||
]
|
||||
},
|
||||
"movups xmm0, xmm0": {
|
||||
@@ -646,7 +646,7 @@
|
||||
"Comment": "0x0f 0x50",
|
||||
"ExpectedArm64ASM": [
|
||||
"ushr v2.4s, v16.4s, #31",
|
||||
"ldr q3, [x28, #2192]",
|
||||
"ldr q3, [x28, #2064]",
|
||||
"ushl v2.4s, v2.4s, v3.4s",
|
||||
"addv s2, v2.4s",
|
||||
"mov w4, v2.s[0]"
|
||||
@@ -657,7 +657,7 @@
|
||||
"Comment": "0x0f 0x50",
|
||||
"ExpectedArm64ASM": [
|
||||
"ushr v2.4s, v16.4s, #31",
|
||||
"ldr q3, [x28, #2192]",
|
||||
"ldr q3, [x28, #2064]",
|
||||
"ushl v2.4s, v2.4s, v3.4s",
|
||||
"addv s2, v2.4s",
|
||||
"mov w4, v2.s[0]"
|
||||
@@ -1041,7 +1041,7 @@
|
||||
"Comment": "0x0f 0x70",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr d2, [x28, #784]",
|
||||
"ldr x0, [x28, #1800]",
|
||||
"ldr x0, [x28, #1672]",
|
||||
"ldr d3, [x0, #16]",
|
||||
"tbl v2.8b, {v2.16b}, v3.8b",
|
||||
"str d2, [x28, #768]"
|
||||
@@ -1052,7 +1052,7 @@
|
||||
"Comment": "0x0f 0x70",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr d2, [x4]",
|
||||
"ldr x0, [x28, #1800]",
|
||||
"ldr x0, [x28, #1672]",
|
||||
"ldr d3, [x0, #16]",
|
||||
"tbl v2.8b, {v2.16b}, v3.8b",
|
||||
"str d2, [x28, #768]"
|
||||
@@ -1111,7 +1111,7 @@
|
||||
"Comment": "0x0f 0x77",
|
||||
"ExpectedArm64ASM": [
|
||||
"mov w20, #0x0",
|
||||
"strb w20, [x28, #1154]"
|
||||
"strb w20, [x28, #1026]"
|
||||
]
|
||||
},
|
||||
"movd eax, mm0": {
|
||||
@@ -1297,19 +1297,15 @@
|
||||
]
|
||||
},
|
||||
"pop fs": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0x0f 0xa1",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x20, [x8]",
|
||||
"add x8, x8, #0x8 (8)",
|
||||
"strh w20, [x28, #146]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #3",
|
||||
"ldr x20, [x0, #896]",
|
||||
"lsr x21, x20, #32",
|
||||
"and w22, w21, #0xff000000",
|
||||
"orr w20, w22, w20, lsr #16",
|
||||
"bfi w20, w21, #16, #8",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
"ldr w20, [x0, #896]",
|
||||
"str w20, [x28, #176]"
|
||||
]
|
||||
},
|
||||
@@ -1696,19 +1692,15 @@
|
||||
]
|
||||
},
|
||||
"pop gs": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0x0f 0xa9",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x20, [x8]",
|
||||
"add x8, x8, #0x8 (8)",
|
||||
"strh w20, [x28, #144]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #3",
|
||||
"ldr x20, [x0, #896]",
|
||||
"lsr x21, x20, #32",
|
||||
"and w22, w21, #0xff000000",
|
||||
"orr w20, w22, w20, lsr #16",
|
||||
"bfi w20, w21, #16, #8",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
"ldr w20, [x0, #896]",
|
||||
"str w20, [x28, #168]"
|
||||
]
|
||||
},
|
||||
@@ -3386,7 +3378,7 @@
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "0x0f 0xc6",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1824]",
|
||||
"ldr x0, [x28, #1696]",
|
||||
"ldr q2, [x0, #16]",
|
||||
"tbl v16.16b, {v16.16b, v17.16b}, v2.16b"
|
||||
]
|
||||
@@ -3395,7 +3387,7 @@
|
||||
"ExpectedInstructionCount": 5,
|
||||
"Comment": "0x0f 0xc6",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1824]",
|
||||
"ldr x0, [x28, #1696]",
|
||||
"ldr q2, [x0, #16]",
|
||||
"mov v0.16b, v17.16b",
|
||||
"mov v1.16b, v16.16b",
|
||||
@@ -3407,7 +3399,7 @@
|
||||
"Comment": "0x0f 0xc6",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x4]",
|
||||
"ldr x0, [x28, #1824]",
|
||||
"ldr x0, [x28, #1696]",
|
||||
"ldr q3, [x0, #16]",
|
||||
"mov v0.16b, v16.16b",
|
||||
"mov v1.16b, v2.16b",
|
||||
|
||||
@@ -1332,7 +1332,7 @@
|
||||
"ExpectedInstructionCount": 58,
|
||||
"Comment": "GROUP15 0x0F 0xAE /0",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrh w20, [x28, #1152]",
|
||||
"ldrh w20, [x28, #1024]",
|
||||
"strh w20, [x4]",
|
||||
"mov w20, #0x0",
|
||||
"ldrb w21, [x28, #747]",
|
||||
@@ -1346,7 +1346,7 @@
|
||||
"orr x20, x20, x23, lsl #10",
|
||||
"orr x20, x20, x24, lsl #14",
|
||||
"strh w20, [x4, #2]",
|
||||
"ldrb w20, [x28, #1154]",
|
||||
"ldrb w20, [x28, #1026]",
|
||||
"strb w20, [x4, #4]",
|
||||
"ldr q2, [x28, #768]",
|
||||
"str q2, [x4, #32]",
|
||||
@@ -1411,7 +1411,7 @@
|
||||
"Comment": "GROUP15 0x0F 0xAE /1",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldrh w20, [x4]",
|
||||
"strh w20, [x28, #1152]",
|
||||
"strh w20, [x28, #1024]",
|
||||
"ldrh w20, [x4, #2]",
|
||||
"ubfx w21, w20, #11, #3",
|
||||
"strb w21, [x28, #747]",
|
||||
@@ -1424,7 +1424,7 @@
|
||||
"strb w23, [x28, #746]",
|
||||
"strb w20, [x28, #750]",
|
||||
"ldrb w20, [x4, #4]",
|
||||
"strb w20, [x28, #1154]",
|
||||
"strb w20, [x28, #1026]",
|
||||
"ldr q2, [x4, #32]",
|
||||
"str q2, [x28, #768]",
|
||||
"ldr q2, [x4, #48]",
|
||||
@@ -1549,7 +1549,7 @@
|
||||
"ubfx x22, x20, #0, #1",
|
||||
"cbnz x22, #+0x8",
|
||||
"b #+0x84",
|
||||
"ldrh w22, [x28, #1152]",
|
||||
"ldrh w22, [x28, #1024]",
|
||||
"strh w22, [x21]",
|
||||
"mov w22, #0x0",
|
||||
"ldrb w23, [x28, #747]",
|
||||
@@ -1563,7 +1563,7 @@
|
||||
"orr x22, x22, x25, lsl #10",
|
||||
"orr x22, x22, x30, lsl #14",
|
||||
"strh w22, [x21, #2]",
|
||||
"ldrb w22, [x28, #1154]",
|
||||
"ldrb w22, [x28, #1026]",
|
||||
"strb w22, [x21, #4]",
|
||||
"ldr q2, [x28, #768]",
|
||||
"str q2, [x21, #32]",
|
||||
@@ -1634,7 +1634,7 @@
|
||||
"cbnz x22, #+0x8",
|
||||
"b #+0x84",
|
||||
"ldrh w22, [x20]",
|
||||
"strh w22, [x28, #1152]",
|
||||
"strh w22, [x28, #1024]",
|
||||
"ldrh w22, [x20, #2]",
|
||||
"ubfx w23, w22, #11, #3",
|
||||
"strb w23, [x28, #747]",
|
||||
@@ -1647,7 +1647,7 @@
|
||||
"strb w25, [x28, #746]",
|
||||
"strb w22, [x28, #750]",
|
||||
"ldrb w22, [x20, #4]",
|
||||
"strb w22, [x28, #1154]",
|
||||
"strb w22, [x28, #1026]",
|
||||
"ldr q2, [x20, #32]",
|
||||
"str q2, [x28, #768]",
|
||||
"ldr q2, [x20, #48]",
|
||||
@@ -1667,13 +1667,13 @@
|
||||
"b #+0x4c",
|
||||
"mov w22, #0x0",
|
||||
"mov w23, #0x37f",
|
||||
"strh w23, [x28, #1152]",
|
||||
"strh w23, [x28, #1024]",
|
||||
"strb w22, [x28, #747]",
|
||||
"strb w22, [x28, #744]",
|
||||
"strb w22, [x28, #745]",
|
||||
"strb w22, [x28, #746]",
|
||||
"strb w22, [x28, #750]",
|
||||
"strb w22, [x28, #1154]",
|
||||
"strb w22, [x28, #1026]",
|
||||
"movi v2.2d, #0x0",
|
||||
"str q2, [x28, #768]",
|
||||
"str q2, [x28, #784]",
|
||||
|
||||
@@ -42,8 +42,8 @@
|
||||
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
|
||||
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
|
||||
"mov w1, w5",
|
||||
"ldr x0, [x28, #1240]",
|
||||
"ldr x2, [x28, #1256]",
|
||||
"ldr x0, [x28, #1112]",
|
||||
"ldr x2, [x28, #1128]",
|
||||
"blr x2",
|
||||
"ldr w4, [x28, #728]",
|
||||
"msr nzcv, x4",
|
||||
@@ -85,7 +85,7 @@
|
||||
"str w0, [x28, #728]",
|
||||
"str x8, [x28, #40]",
|
||||
"mov w0, #0x100",
|
||||
"str x0, [x28, #1184]",
|
||||
"str x0, [x28, #1056]",
|
||||
"sub sp, sp, #0x10 (16)",
|
||||
"mov w8, #0xa8",
|
||||
"mov x0, sp",
|
||||
@@ -96,7 +96,7 @@
|
||||
"ldr w8, [x28, #728]",
|
||||
"msr nzcv, x8",
|
||||
"ldr x8, [x28, #40]",
|
||||
"str xzr, [x28, #1184]",
|
||||
"str xzr, [x28, #1056]",
|
||||
"orr x5, x0, x1, lsl #12"
|
||||
]
|
||||
},
|
||||
|
||||
@@ -17,19 +17,15 @@
|
||||
]
|
||||
},
|
||||
"pop fs": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0x0f 0xa1",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr w20, [x8]",
|
||||
"add x8, x8, #0x4 (4)",
|
||||
"strh w20, [x28, #146]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #3",
|
||||
"ldr x20, [x0, #896]",
|
||||
"lsr x21, x20, #32",
|
||||
"and w22, w21, #0xff000000",
|
||||
"orr w20, w22, w20, lsr #16",
|
||||
"bfi w20, w21, #16, #8",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
"ldr w20, [x0, #896]",
|
||||
"str w20, [x28, #176]"
|
||||
]
|
||||
},
|
||||
@@ -42,19 +38,15 @@
|
||||
]
|
||||
},
|
||||
"pop gs": {
|
||||
"ExpectedInstructionCount": 11,
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0x0f 0xa9",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr w20, [x8]",
|
||||
"add x8, x8, #0x4 (4)",
|
||||
"strh w20, [x28, #144]",
|
||||
"ubfx w20, w20, #3, #13",
|
||||
"add x0, x28, x20, lsl #3",
|
||||
"ldr x20, [x0, #896]",
|
||||
"lsr x21, x20, #32",
|
||||
"and w22, w21, #0xff000000",
|
||||
"orr w20, w22, w20, lsr #16",
|
||||
"bfi w20, w21, #16, #8",
|
||||
"add x0, x28, x20, lsl #2",
|
||||
"ldr w20, [x0, #896]",
|
||||
"str w20, [x28, #168]"
|
||||
]
|
||||
}
|
||||
|
||||
@@ -522,7 +522,7 @@
|
||||
"0x66 0x0f 0x70"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1816]",
|
||||
"ldr x0, [x28, #1688]",
|
||||
"ldr q2, [x0, #16]",
|
||||
"tbl v16.16b, {v17.16b}, v2.16b"
|
||||
]
|
||||
@@ -536,7 +536,7 @@
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x4]",
|
||||
"ldr x0, [x28, #1816]",
|
||||
"ldr x0, [x28, #1688]",
|
||||
"ldr q3, [x0, #16]",
|
||||
"tbl v16.16b, {v2.16b}, v3.16b"
|
||||
]
|
||||
@@ -1014,7 +1014,7 @@
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "0x66 0x0f 0xd0",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2160]",
|
||||
"ldr q2, [x28, #2032]",
|
||||
"eor v2.16b, v17.16b, v2.16b",
|
||||
"fadd v16.2d, v16.2d, v2.2d"
|
||||
]
|
||||
|
||||
@@ -354,7 +354,7 @@
|
||||
"0xf3 0x0f 0x70"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1808]",
|
||||
"ldr x0, [x28, #1680]",
|
||||
"ldr q2, [x0, #16]",
|
||||
"tbl v16.16b, {v17.16b}, v2.16b"
|
||||
]
|
||||
|
||||
@@ -296,7 +296,7 @@
|
||||
"0xf2 0x0f 0x70"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1800]",
|
||||
"ldr x0, [x28, #1672]",
|
||||
"ldr q2, [x0, #16]",
|
||||
"tbl v16.16b, {v17.16b}, v2.16b"
|
||||
]
|
||||
@@ -452,7 +452,7 @@
|
||||
"ExpectedInstructionCount": 3,
|
||||
"Comment": "0xf2 0x0f 0xd0",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2128]",
|
||||
"ldr q2, [x28, #2000]",
|
||||
"eor v2.16b, v17.16b, v2.16b",
|
||||
"fadd v16.4s, v16.4s, v2.4s"
|
||||
]
|
||||
|
||||
@@ -2755,7 +2755,7 @@
|
||||
"Map 1 0b00 0xC6 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1824]",
|
||||
"ldr x0, [x28, #1696]",
|
||||
"ldr q2, [x0, #16]",
|
||||
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
|
||||
]
|
||||
@@ -2824,7 +2824,7 @@
|
||||
"Map 1 0b00 0xC6 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1824]",
|
||||
"ldr x0, [x28, #1696]",
|
||||
"ldr q2, [x0, #32]",
|
||||
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
|
||||
]
|
||||
@@ -2893,7 +2893,7 @@
|
||||
"Map 1 0b00 0xC6 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1824]",
|
||||
"ldr x0, [x28, #1696]",
|
||||
"ldr q2, [x0, #48]",
|
||||
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
|
||||
]
|
||||
@@ -4338,7 +4338,7 @@
|
||||
"Map 1 0b01 0xd0 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2160]",
|
||||
"ldr q2, [x28, #2032]",
|
||||
"eor v2.16b, v18.16b, v2.16b",
|
||||
"fadd v16.2d, v17.2d, v2.2d"
|
||||
]
|
||||
@@ -4349,7 +4349,7 @@
|
||||
"Map 1 0b01 0xd0 256-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1720]",
|
||||
"ldr x0, [x28, #1592]",
|
||||
"ld1b {z2.b}, p7/z, [x0]",
|
||||
"eor z2.d, z18.d, z2.d",
|
||||
"fadd z16.d, z17.d, z2.d"
|
||||
@@ -4361,7 +4361,7 @@
|
||||
"Map 1 0b11 0xd0 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2128]",
|
||||
"ldr q2, [x28, #2000]",
|
||||
"eor v2.16b, v18.16b, v2.16b",
|
||||
"fadd v16.4s, v17.4s, v2.4s"
|
||||
]
|
||||
@@ -4372,7 +4372,7 @@
|
||||
"Map 1 0b11 0xd0 256-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #1704]",
|
||||
"ldr x0, [x28, #1576]",
|
||||
"ld1b {z2.b}, p7/z, [x0]",
|
||||
"eor z2.d, z18.d, z2.d",
|
||||
"fadd z16.s, z17.s, z2.s"
|
||||
|
||||
@@ -1575,7 +1575,7 @@
|
||||
"Map 2 0b01 0x41 256-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2096]",
|
||||
"ldr q2, [x28, #1968]",
|
||||
"zip1 v3.8h, v2.8h, v17.8h",
|
||||
"zip2 v2.8h, v2.8h, v17.8h",
|
||||
"umin v2.4s, v3.4s, v2.4s",
|
||||
|
||||
@@ -4799,7 +4799,7 @@
|
||||
"Map 3 0b01 0xdf 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2208]",
|
||||
"ldr q2, [x28, #2080]",
|
||||
"movi v3.2d, #0x0",
|
||||
"mov v16.16b, v17.16b",
|
||||
"unimplemented (Unimplemented)",
|
||||
@@ -4812,7 +4812,7 @@
|
||||
"Map 3 0b01 0xdf 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2208]",
|
||||
"ldr q2, [x28, #2080]",
|
||||
"movi v3.2d, #0x0",
|
||||
"mov v16.16b, v17.16b",
|
||||
"unimplemented (Unimplemented)",
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
Reference in new issue
Block a user