Docs: Update for release FEX-2106

Fixes 32-bit applications crashing

.github/workflows/ccpp.yml

@@ -13,18 +13,22 @@ env:
   BUILD_TYPE: Release
   CC: clang
   CXX: clang++
+  FEX_FORCE32BITALLOCATOR: 1
 
 jobs:
   build:
     runs-on: ${{ matrix.arch }}
     strategy:
       matrix:
-        arch: [[self-hosted, x64], [self-hosted, ARMv8.0], [self-hosted, ARMv8.2]]
+        arch: [[self-hosted, x64], [self-hosted, ARMv8.0], [self-hosted, ARMv8.2], [self-hosted, ARMv8.4]]
       fail-fast: false
 
     steps:
     - uses: actions/checkout@v2
 
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
     - name : submodule checkout
       # Need to update submodules
       run: git submodule update --init --depth 1
@@ -45,7 +49,7 @@ jobs:
       # Note the current convention is to use the -S and -B options here to specify source
       # and build directories, but this is only available with CMake 3.13 and higher.
       # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
 
     - name: Build
       working-directory: ${{runner.workspace}}/build
@@ -59,27 +63,100 @@ jobs:
       # Execute the unit tests
       run: cmake --build . --config $BUILD_TYPE --target asm_tests
 
+    - name: ASM Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
+
     - name: IR Tests
       working-directory: ${{runner.workspace}}/build
       shell: bash
       # Execute the unit tests
       run: cmake --build . --config $BUILD_TYPE --target ir_tests
 
+    - name: IR Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
+
     - name: Posix Tests
       working-directory: ${{runner.workspace}}/build
       shell: bash
       # Execute the posixtest
       run: cmake --build . --config $BUILD_TYPE --target posix_tests
 
+    - name: Posix Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_Posix.log || true
+
     - name: gvisor tests
       working-directory: ${{runner.workspace}}/build
       shell: bash
       # Execute the gvisor tests
       run: cmake --build . --config $BUILD_TYPE --target gvisor_tests
 
+    - name: GVisor Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GVisor.log || true
+
     - name: gcc target tests 64
       working-directory: ${{runner.workspace}}/build
       shell: bash
       # Execute the gvisor tests
       run: cmake --build . --config $BUILD_TYPE --target gcc_target_tests_64
 
+    - name: GCC64 Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC64.log || true
+
+    - name: gcc target tests 32
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the gvisor tests
+      run: cmake --build . --config $BUILD_TYPE --target gcc_target_tests_32
+
+    - name: GCC32 Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC32.log || true
+
+    - name: Struct verifier tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target struct_verifier
+
+    - name: Struct verifier Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_StructVerifier.log || true
+
+    - name: Truncate test results
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Cap out the log files at 20M in case something crash spins and dumps fault text
+      # ASM tests get quite close to 10MB
+      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+
+    - name: Set runner name
+      if: ${{ always() }}
+      run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
+
+    - name: Upload results
+      if: ${{ always() }}
+      uses: 'actions/upload-artifact@v2'
+      with:
+        name: Results-${{ env.runner_name }}
+        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
+        retention-days: 3
+

.gitmodules

@@ -30,3 +30,12 @@
         shallow = true
 	path = External/fex-gcc-target-tests-bins
 	url = https://github.com/FEX-Emu/fex-gcc-target-tests-bins.git
+[submodule "External/jemalloc"]
+	path = External/jemalloc
+	url = https://github.com/FEX-Emu/jemalloc.git
+[submodule "External/fmt"]
+	path = External/fmt
+	url = https://github.com/fmtlib/fmt.git
+[submodule "External/drm-headers"]
+	path = External/drm-headers
+	url = https://github.com/FEX-Emu/drm-headers.git

CMakeLists.txt

@@ -12,6 +12,8 @@ option(ENABLE_ASAN "Enables Clang ASAN" FALSE)
 option(ENABLE_TSAN "Enables Clang TSAN" FALSE)
 option(ENABLE_ASSERTIONS "Enables assertions in build" FALSE)
 option(ENABLE_VISUAL_DEBUGGER "Enables the visual debugger for compiling" FALSE)
+option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
+option(ENABLE_WERROR "Enables -Werror" FALSE)
 
 set (X86_C_COMPILER "x86_64-linux-gnu-gcc" CACHE STRING "c compiler for compiling x86 guest libs")
 set (X86_CXX_COMPILER "x86_64-linux-gnu-g++" CACHE STRING "c++ compiler for compiling x86 guest libs")
@@ -27,14 +29,6 @@ if (ENABLE_ASSERTIONS)
   add_definitions(-DASSERTIONS_ENABLED=1)
 endif()
 
-if (ENABLE_IWYU)
-  find_program(IWYU_EXE "iwyu")
-  if (IWYU_EXE)
-    message(STATUS "IWYU enabled")
-    set(CMAKE_CXX_INCLUDE_WHAT_YOU_USE "${IWYU_EXE}")
-  endif()
-endif()
-
 set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/Bin)
@@ -67,8 +61,8 @@ endif()
 
 if (ENABLE_ASAN)
   add_definitions(-DENABLE_ASAN=1)
-  add_compile_options(-fno-omit-frame-pointer -fsanitize=address)
-  link_libraries(-fno-omit-frame-pointer -fsanitize=address)
+  add_compile_options(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
+  link_libraries(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
 endif()
 
 if (ENABLE_TSAN)
@@ -83,6 +77,14 @@ set (CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -fomit-frame-pointer")
 set (CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-pointer")
 
 if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
+  option(ENABLE_X86_HOST_DEBUG "Enables compiling on x86_64 host" FALSE)
+  if (NOT ENABLE_X86_HOST_DEBUG)
+    message(FATAL_ERROR
+      " Be warned: FEX isn't optimized for x86_64 hosts!\n"
+      " Support for x86_64 hosts is only for debugging and convenience!\n"
+      " Don't expect amazing performance or optimal code generation!\n"
+      " Pass -DENABLE_X86_HOST_DEBUG=True to bypass this message!")
+  endif()
   set(_M_X86_64 1)
   add_definitions(-D_M_X86_64=1)
   set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
@@ -91,24 +93,31 @@ endif()
 if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
   set(_M_ARM_64 1)
   add_definitions(-D_M_ARM_64=1)
-  add_subdirectory(External/vixl/)
-  include_directories(External/vixl/src/)
-  if(CMAKE_BUILD_TYPE MATCHES DEBUG)
-    add_definitions(-DVIXL_DEBUG=1)
-  endif()
 endif()
 
+add_subdirectory(External/vixl/)
+include_directories(External/vixl/src/)
+
 if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
   # This means we were attempted to get compiled with GCC
   message(FATAL_ERROR "FEX doesn't support getting compiled with GCC!")
 endif()
 
+find_package(PkgConfig REQUIRED)
+find_package(Python 3.0 REQUIRED COMPONENTS Interpreter)
+pkg_check_modules(XXHASH libxxhash REQUIRED)
+
 add_definitions(-Wno-trigraphs)
 add_definitions(-DGLOBAL_DATA_DIRECTORY="${DATA_DIRECTORY}/")
 
+add_subdirectory(External/jemalloc/)
+include_directories(External/jemalloc/pregen/include/)
+
 add_subdirectory(External/cpp-optparse/)
 include_directories(External/cpp-optparse/)
 
+add_subdirectory(External/fmt/)
+
 add_subdirectory(External/imgui/)
 include_directories(External/imgui/)
 
@@ -147,32 +156,115 @@ if(COMPILER_SUPPORTS_MARCH_NATIVE)
   set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native")
 endif()
 
-if(_M_ARM_64)
-  # Due to an oversight in llvm, it declares any reasonably new Kryo CPU to only be ARMv8.0
-  # Manually detect newer CPU revisions until clang and llvm fixes their bug
-  # This script will either provide a supported CPU or 'native'
-  # Additionally -march doesn't work under AArch64+Clang, so you have to use -mcpu or -mtune
-  execute_process(COMMAND python3 "${PROJECT_SOURCE_DIR}/Scripts/aarch64_fit_native.py" "/proc/cpuinfo"
-    OUTPUT_VARIABLE AARCH64_CPU)
-
-  string(STRIP ${AARCH64_CPU} AARCH64_CPU)
-
-  check_cxx_compiler_flag("-mcpu=${AARCH64_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
-  if(COMPILER_SUPPORTS_CPU_TYPE)
-    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcpu=${AARCH64_CPU}")
+if(ENABLE_WERROR OR ENABLE_STRICT_WERROR)
+  add_compile_options(-Werror)
+  if (NOT ENABLE_STRICT_WERROR)
+    # Disable some Werror that can add frustration when developing
+    add_compile_options(-Wno-error=unused-variable)
   endif()
 endif()
 
+if(_M_ARM_64)
+  if (CMAKE_CXX_COMPILER_VERSION VERSION_GREATER_EQUAL 999999.0)
+    # Clang 12.0 fixed the -mcpu=native bug with mixed big.little implementers
+    # Clang can not currently check for native Apple M1 type in hypervisor. Currently disabled
+    check_cxx_compiler_flag("-mcpu=native" COMPILER_SUPPORTS_CPU_TYPE)
+    if(COMPILER_SUPPORTS_CPU_TYPE)
+      set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcpu=native")
+    endif()
+  else()
+    # Due to an oversight in llvm, it declares any reasonably new Kryo CPU to only be ARMv8.0
+    # Manually detect newer CPU revisions until clang and llvm fixes their bug
+    # This script will either provide a supported CPU or 'native'
+    # Additionally -march doesn't work under AArch64+Clang, so you have to use -mcpu or -mtune
+    execute_process(COMMAND python3 "${PROJECT_SOURCE_DIR}/Scripts/aarch64_fit_native.py" "/proc/cpuinfo" "${CMAKE_CXX_COMPILER_VERSION}"
+      OUTPUT_VARIABLE AARCH64_CPU)
+
+    string(STRIP ${AARCH64_CPU} AARCH64_CPU)
+
+    check_cxx_compiler_flag("-mcpu=${AARCH64_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
+    if(COMPILER_SUPPORTS_CPU_TYPE)
+      set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcpu=${AARCH64_CPU}")
+    endif()
+  endif()
+endif()
+
+if (ENABLE_IWYU)
+  find_program(IWYU_EXE "iwyu")
+  if (IWYU_EXE)
+    message(STATUS "IWYU enabled")
+    set(CMAKE_CXX_INCLUDE_WHAT_YOU_USE "${IWYU_EXE}")
+  endif()
+endif()
+
+if (ENABLE_CLANG_FORMAT)
+  find_program(CLANG_TIDY_EXE "clang-tidy")
+  if (NOT CLANG_TIDY_EXE)
+    message(FATAL_ERROR "Couldn't find clang-tidy")
+  endif()
+
+  set(CLANG_TIDY_FLAGS
+    "-checks=*"
+    "-fuchsia*"
+    "-bugprone-macro-parentheses"
+    "-clang-analyzer-core.*"
+    "-cppcoreguidelines-pro-type-*"
+    "-cppcoreguidelines-pro-bounds-array-to-pointer-decay"
+    "-cppcoreguidelines-pro-bounds-pointer-arithmetic"
+    "-cppcoreguidelines-avoid-c-arrays"
+    "-cppcoreguidelines-avoid-magic-numbers"
+    "-cppcoreguidelines-pro-bounds-constant-array-index"
+    "-cppcoreguidelines-no-malloc"
+    "-cppcoreguidelines-special-member-functions"
+    "-cppcoreguidelines-owning-memory"
+    "-cppcoreguidelines-macro-usage"
+    "-cppcoreguidelines-avoid-goto"
+    "-google-readability-function-size"
+    "-google-readability-namespace-comments"
+    "-google-readability-braces-around-statements"
+    "-google-build-using-namespace"
+    "-hicpp-*"
+    "-llvm-namespace-comment"
+    "-llvm-include-order" # Messes up with case sensitivity
+    "-llvmlibc-*"
+    "-misc-unused-parameters"
+    "-modernize-loop-convert"
+    "-modernize-use-auto"
+    "-modernize-avoid-c-arrays"
+    "-modernize-use-nodiscard"
+    "readability-*"
+    "-readability-function-size"
+    "-readability-implicit-bool-conversion"
+    "-readability-braces-around-statements"
+    "-readability-else-after-return"
+    "-readability-magic-numbers"
+    "-readability-named-parameter"
+    "-readability-uppercase-literal-suffix"
+    "-cert-err34-c"
+    "-cert-err58-cpp"
+    "-bugprone-exception-escape"
+    )
+  string(REPLACE ";" "," CLANG_TIDY_FLAGS "${CLANG_TIDY_FLAGS}")
+  set(CMAKE_CXX_CLANG_TIDY ${CLANG_TIDY_EXE} "${CLANG_TIDY_FLAGS}")
+endif()
+
 add_compile_options(-Wall)
 
-add_subdirectory(External/FEXCore)
-
-add_subdirectory(Source/)
+configure_file(
+  ${CMAKE_CURRENT_SOURCE_DIR}/include/Config.h.in
+  ${CMAKE_BINARY_DIR}/generated/Config.h)
 
 if (BUILD_TESTS)
   include(CTest)
   enable_testing()
   message(STATUS "Unit tests are enabled")
+endif()
+add_subdirectory(External/FEXCore)
+
+add_subdirectory(Source/)
+add_subdirectory(Data/AppConfig/)
+
+if (BUILD_TESTS)
   add_subdirectory(unittests/)
 endif()
 
@@ -183,16 +275,35 @@ if (BUILD_THUNKS)
     PREFIX host-libs
     SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/ThunkLibs/HostLibs"
     BINARY_DIR "Host"
+    CMAKE_ARGS "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
     INSTALL_COMMAND ""
     BUILD_ALWAYS ON
   )
 
+  install(
+    CODE "MESSAGE(\"-- Installing: host-libs\")"
+    CODE "
+    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target ThunkHostsInstall
+    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Host
+    )"
+    DEPENDS host-libs
+  )
+
   ExternalProject_Add(guest-libs
     PREFIX guest-libs
     SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/ThunkLibs/GuestLibs"
     BINARY_DIR "Guest"
-    CMAKE_ARGS "-DX86_C_COMPILER:STRING=${X86_C_COMPILER}" "-DX86_CXX_COMPILER:STRING=${X86_CXX_COMPILER}"
+    CMAKE_ARGS "-DX86_C_COMPILER:STRING=${X86_C_COMPILER}" "-DX86_CXX_COMPILER:STRING=${X86_CXX_COMPILER}" "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
     INSTALL_COMMAND ""
     BUILD_ALWAYS ON
   )
+
+  install(
+    CODE "MESSAGE(\"-- Installing: guest-libs\")"
+    CODE "
+    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target ThunkGuestsInstall
+    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest
+    )"
+    DEPENDS guest-libs
+  )
 endif()

Data/AppConfig/CMakeLists.txt

@@ -0,0 +1,25 @@
+file(GLOB CONFIG_SOURCES CONFIGURE_DEPENDS *.json)
+file(GLOB GEN_CONFIG_SOURCES CONFIGURE_DEPENDS *.json.in)
+
+# Any application configuration json file gets installed
+foreach(CONFIG_SRC ${CONFIG_SOURCES})
+  install(FILES ${CONFIG_SRC}
+    DESTINATION ${DATA_DIRECTORY}/AppConfig/)
+endforeach()
+
+# Any configuration file json file that needs to be generated
+# First generate then install it
+foreach(GEN_CONFIG_SRC ${GEN_CONFIG_SOURCES})
+  # Get the filename only component
+  get_filename_component(CONFIG_NAME ${GEN_CONFIG_SRC} NAME_WE)
+
+  # Configure it
+  configure_file(
+    ${GEN_CONFIG_SRC}
+    ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}.json)
+
+  # Then install the configured json
+  install(
+    FILES ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}.json
+    DESTINATION ${DATA_DIRECTORY}/AppConfig/)
+endforeach()

Data/AppConfig/steam.json.in

@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "Env": "STEAM_GAME_LAUNCH_SHELL=@CMAKE_INSTALL_PREFIX@/bin/FEXBash"
+  }
+}

Dockerfile

@@ -4,7 +4,8 @@ FROM ubuntu:20.04 as builder
 RUN DEBIAN_FRONTEND="noninteractive" apt-get update
 RUN DEBIAN_FRONTEND="noninteractive" apt install -y cmake \
 clang-10 llvm-10 nasm ninja-build libnuma-dev \
-libcap-dev libglfw3-dev libepoxy-dev
+libcap-dev libglfw3-dev libepoxy-dev python3-dev \
+python3 linux-headers-generic
 
 COPY . /opt/FEX
 

External/FEXCore/CMakeLists.txt

@@ -4,6 +4,17 @@ project(${PROJECT_NAME}
   VERSION 0.01
   LANGUAGES CXX)
 
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
+  set(_M_X86_64 1)
+  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
+endif()
+
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
+  set(_M_ARM_64 1)
+endif()
+
+set(ENABLE_JIT_X86_64 ${_M_X86_64} CACHE BOOL "Enable the x86_64 JIT")
+set(ENABLE_JIT_ARM64 ${_M_ARM_64} CACHE BOOL "Enable the ARM64 JIT")
 option(ENABLE_CLANG_FORMAT "Run clang format over the source" FALSE)
 option(ENABLE_JITSYMBOLS "Enable visibility of JITSymbols in profiling tools" FALSE)
 
@@ -17,23 +28,11 @@ set(CMAKE_INCLUDE_CURRENT_DIR ON)
 include(CheckCXXCompilerFlag)
 include(CheckIncludeFileCXX)
 
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
-  set(_M_X86_64 1)
-  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-operator-names -mcx16")
-  set(CMAKE_REQUIRED_DEFINITIONS "-fno-operator-names")
-  message(STATUS "Enabling x86-64 JIT")
-  set(ENABLE_JIT 1)
-endif()
 
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
-  message(STATUS "Enabling AArch64 JIT")
-  set(_M_ARM_64 1)
-  set(ENABLE_JIT 1)
-  if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
+if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
     # Useful to have for freestanding libFEXCore
     add_subdirectory(External/vixl/)
     include_directories(External/vixl/src/)
-  endif()
 endif()
 
 set(CMAKE_CXX_STANDARD 20)

External/FEXCore/Scripts/config_generator.py

@@ -0,0 +1,467 @@
+import datetime
+import json
+import sys
+
+def print_header():
+    header = '''#ifndef OPT_BASE
+#define OPT_BASE(type, group, enum, json, default)
+#endif
+#ifndef OPT_BOOL
+#define OPT_BOOL(group, enum, json, default) OPT_BASE(bool, group, enum, json, default)
+#endif
+#ifndef OPT_UINT8
+#define OPT_UINT8(group, enum, json, default) OPT_BASE(uint8_t, group, enum, json, default)
+#endif
+#ifndef OPT_INT32
+#define OPT_INT32(group, enum, json, default) OPT_BASE(int32_t, group, enum, json, default)
+#endif
+#ifndef OPT_UINT32
+#define OPT_UINT32(group, enum, json, default) OPT_BASE(uint32_t, group, enum, json, default)
+#endif
+#ifndef OPT_UINT64
+#define OPT_UINT64(group, enum, json, default) OPT_BASE(uint64_t, group, enum, json, default)
+#endif
+#ifndef OPT_STR
+#define OPT_STR(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#endif
+#ifndef OPT_STRARRAY
+#define OPT_STRARRAY(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#endif
+
+'''
+    output_file.write(header)
+
+def print_tail():
+    tail = '''#undef OPT_BASE
+#undef OPT_BOOL
+#undef OPT_UINT8
+#undef OPT_INT32
+#undef OPT_UINT32
+#undef OPT_UINT64
+#undef OPT_STR
+#undef OPT_STRARRAY
+'''
+    output_file.write(tail)
+
+def print_config(type, group_name, json_name, default_value):
+    output_file.write("OPT_{0} ({1}, {2}, {3}, {4})\n".format(type.upper(), group_name.upper(), json_name.upper(), json_name, default_value))
+
+def print_options(options):
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "\"" + default + "\""
+
+            print_config(
+                op_vals["Type"],
+                op_group,
+                op_key,
+                default)
+
+        output_file.write("\n")
+
+def print_unnamed_options(options):
+    output_file.write("// Unnamed configuration options\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "\"" + default + "\""
+
+            print_config(
+                op_vals["Type"],
+                op_group,
+                op_key.upper(), # KEY is the enum here, there is no json configuration for these
+                default)
+
+        output_file.write("\n")
+
+def print_man_option(short, long, desc, default):
+    if (short != None):
+        output_man.write(".It Fl {0} , ".format(short))
+    else:
+        output_man.write(".It ")
+
+    output_man.write("Fl Fl {0}=".format(long))
+
+    output_man.write("\n");
+
+    # Print description
+    for line in desc:
+        output_man.write(".Pp\n")
+        output_man.write("{0}\n".format(line))
+
+    output_man.write(".Pp\n")
+    output_man.write("\\fBdefault:\\fR {0}\n".format(default))
+    output_man.write(".Pp\n\n")
+
+def print_man_env_option(name, desc, default):
+    output_man.write("\\fBFEX_{0}\\fR\n".format(name))
+
+    # Print description
+    for line in desc:
+        output_man.write(".Pp\n")
+        output_man.write("{0}\n".format(line))
+
+    output_man.write(".Pp\n")
+    output_man.write("\\fBdefault:\\fR {0}\n".format(default))
+    output_man.write(".Pp\n\n")
+
+def print_man_options(options):
+    output_man.write(".Sh OPTIONS\n")
+    output_man.write(".Bl -tag -width -indent\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            short = None
+            long = op_key.lower()
+
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+
+            default = op_vals["Default"]
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = op_vals["TextDefault"]
+
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "'" + default + "'"
+            print_man_option(
+                short,
+                long,
+                op_vals["Desc"],
+                default
+            )
+
+    output_man.write(".El\n")
+
+def print_man_environment(options):
+    output_man.write(".Sh ENVIRONMENT\n")
+    output_man.write(".Bl -tag -width -indent\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = op_vals["TextDefault"]
+
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "'" + default + "'"
+            print_man_env_option(
+                op_key.upper(),
+                op_vals["Desc"],
+                default
+            )
+
+    print_man_environment_tail()
+    output_man.write(".El\n")
+
+def print_man_environment_tail():
+
+    # Additional environment variables that live outside of the normal loop
+    print_man_env_option(
+    "FEX_APP_CONFIG_LOCATION",
+    [
+    "Allows the user to override where FEX looks for configuration files",
+    "By default FEX will look in {$HOME, $XDG_CONFIG_HOME}/.fex-emu/",
+    "This will override the full path",
+    ],
+    "''")
+
+    print_man_env_option(
+    "FEX_APP_CONFIG",
+    [
+    "Allows the user to override where FEX looks for only the application config file",
+    "By default FEX will look in {$HOME, $XDG_CONFIG_HOME}/.fex-emu/Config.json",
+    "This will override this file location",
+    "One must be careful with this option as it will override any applications that load with execve as well"
+    "If you need to support applications that execve then use FEX_APP_CONFIG_LOCATION instead"
+    ],
+    "''")
+
+    print_man_env_option(
+    "FEX_APP_DATA_LOCATION",
+    [
+    "Allows the user to override where FEX looks for data files",
+    "By default FEX will look in {$HOME, $XDG_DATA_HOME}/.fex-emu/",
+    "This will override the full path",
+    "This is the folder where FEX stores generated files like IR cache"
+    ],
+    "''")
+
+def print_man_header():
+    header ='''.Dd {0}
+.Dt FEX
+.Os Linux
+.Sh NAME
+.Nm FEXLoader
+.Nm FEXInterpreter
+.Nm FEXBash
+.Nd Fast x86-64 and x86 emulation.
+.Sh SYNOPSIS
+.Nm
+.Op options
+.Op Ar --
+.Ar Application
+<args> ...
+.Pp
+.Nm FEXInterpreter
+.Ar Application
+<args> ...
+.Pp
+.Nm FEXBash
+.Ar <args> ...
+.Sh DESCRIPTION
+FEX allows you to run x86 and x86-64 binaries on an AArch64 host, similar to qemu-user and box86.
+It has native support for a rootfs overlay, so you don't need to chroot, as well as some thunklibs so it can forward things like GL to the host.
+FEX presents a Linux 5.0 interface to the guest, and supports both AArch64 and x86-64 as hosts.
+FEX is very much work in progress, so expect things to change.
+'''
+    output_man.write(header.format(datetime.datetime.now().strftime("%d-%m-%Y")))
+
+def print_man_tail():
+    tail ='''.Sh FILES
+.Bl -tag -width "$prefix/share/fex-emu/GuestThunks" -compact
+.It Pa $XDG_HOME_DIR/.fex-emu
+Default FEX user configuration directory
+.It Pa $prefix/share/fex-emu/AppConfig
+System level application configuration files
+.It Pa $prefix/share/fex-emu/GuestThunks
+guest-side thunk data libraries
+.It Pa $prefix/lib/fex-emu/HostThunks
+host-side thunks for guest communication
+.El
+'''
+    output_man.write(tail)
+
+def print_config_option(type, group_name, json_name, default_value, short, choices, desc):
+    if (type == "bool"):
+        # Bool gets some special handling to add an inverted case
+        output_argloader.write("{0}Group".format(group_name))
+
+        options = ""
+        AddedArg = False
+        if (short != None):
+            AddedArg = True
+            options += "\"-{0}\"".format(short)
+
+        if (AddedArg):
+            options += ", "
+        options += "\"--{0}\"".format(json_name.lower())
+
+        output_argloader.write(".add_option({0})".format(options))
+
+        output_argloader.write("\n")
+
+        output_argloader.write("\t.action(\"store_true\")\n")
+
+        output_argloader.write("\t.dest(\"{0}\")\n".format(json_name));
+
+        # help
+        output_argloader.write("\t.help(\n")
+        desc_line_ender = ""
+        if (len(desc) > 1):
+            desc_line_ender = "\\n"
+
+        for line in desc:
+            output_argloader.write("\t\t\"{0}{1}\"\n".format(line, desc_line_ender))
+        output_argloader.write("\t)\n")
+
+        output_argloader.write("\t.set_default({0});\n\n".format(default_value));
+
+        output_argloader.write("{0}Group".format(group_name))
+        output_argloader.write(".add_option(\"--no-{0}\")\n".format(json_name.lower()))
+
+        # Inverted case sets the bool to false
+        output_argloader.write("\t.action(\"store_false\")\n")
+
+        output_argloader.write("\t.dest(\"{0}\");\n".format(json_name));
+    else:
+        output_argloader.write("{0}Group".format(group_name))
+        options = ""
+        AddedArg = False
+        if (short != None):
+            AddedArg = True
+            options += "\"-{0}\"".format(short)
+
+        if (AddedArg):
+            options += ", "
+        options += "\"--{0}\"".format(json_name.lower())
+
+        output_argloader.write(".add_option({0})".format(options))
+
+        output_argloader.write("\n")
+
+        output_argloader.write("\t.dest(\"{0}\")\n".format(json_name));
+
+        if (choices != None):
+            output_argloader.write("\t.choices({\n")
+            for choice in choices:
+                output_argloader.write("\t\t\"{0}\",\n".format(choice))
+            output_argloader.write("\t})\n")
+
+
+        # help
+        output_argloader.write("\t.help(\n")
+        desc_line_ender = ""
+        if (len(desc) > 1):
+            desc_line_ender = "\\n"
+
+        for line in desc:
+            output_argloader.write("\t\t\"{0}{1}\"\n".format(line, desc_line_ender))
+        output_argloader.write("\t)\n")
+
+        output_argloader.write("\t.set_default({0});\n".format(default_value));
+
+    output_argloader.write("\n");
+
+def print_argloader_options(options):
+    output_argloader.write("#ifdef BEFORE_PARSE\n")
+    output_argloader.write("#undef BEFORE_PARSE\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "\"" + default + "\""
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = "\"" + op_vals["TextDefault"] + "\""
+
+            short = None
+            choices = None
+
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+            if ("Choices" in op_vals):
+                choices = op_vals["Choices"]
+
+            print_config_option(
+                op_vals["Type"],
+                op_group,
+                op_key,
+                default,
+                short,
+                choices,
+                op_vals["Desc"])
+
+        output_argloader.write("\n")
+    output_argloader.write("#endif\n")
+
+def print_parse_argloader_options(options):
+    output_argloader.write("#ifdef AFTER_PARSE\n")
+    output_argloader.write("#undef AFTER_PARSE\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            output_argloader.write("if (Options.is_set_by_user(\"{0}\")) {{\n".format(op_key))
+
+            value_type = op_vals["Type"]
+            NeedsString = False
+            conversion_func = "std::to_string"
+            if ("ArgumentHandler" in op_vals):
+                NeedsString = True
+                conversion_func = "FEX::Handler::{0}".format(op_vals["ArgumentHandler"])
+            if (value_type == "str"):
+                NeedsString = True
+                conversion_func = ""
+
+            if (value_type == "strarray"):
+                # these need a bit more help
+                output_argloader.write("\tauto Array = Options.all(\"{0}\");\n".format(op_key))
+                output_argloader.write("\tfor (auto iter = Array.begin(); iter != Array.end(); ++iter) {\n")
+                output_argloader.write("\t\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, *iter);\n".format(op_key.upper()))
+                output_argloader.write("\t}\n")
+            else:
+                if (NeedsString):
+                    output_argloader.write("\tstd::string UserValue = Options[\"{0}\"];\n".format(op_key))
+                else:
+                    output_argloader.write("\t{0} UserValue = Options.get(\"{1}\");\n".format(value_type, op_key))
+
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, {1}(UserValue));\n".format(op_key.upper(), conversion_func))
+            output_argloader.write("}\n")
+
+    output_argloader.write("#endif\n")
+
+def check_for_duplicate_options(options):
+    short_map = []
+    long_map = []
+
+    # Spin through all the items and see if we have a duplicate option
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            short = None
+            long = op_key.lower()
+            long_invert = None
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+            if (op_vals["Type"] == "bool"):
+                long_invert = "no-" + long
+
+            # Check for short key duplication
+            if (short != None):
+                if (short in short_map):
+                    raise Exception("Short config '{0}' for option '{1}' has duplicate entry!".format(short, op_key))
+                else:
+                    short_map.append(short)
+
+            # Check for long key duplication
+            if (long in long_map):
+                raise Exception("Long config '{0}' has duplicate entry!".format(long))
+            else:
+                long_map.append(long)
+
+            # Check for long key duplication
+            if (long_invert != None):
+                if (long_invert in long_map):
+                    raise Exception("Long config '{0}' has duplicate entry!".format(long_invert))
+                else:
+                    long_map.append(long_invert)
+
+if (len(sys.argv) < 5):
+    sys.exit()
+
+output_filename = sys.argv[2]
+output_man_page = sys.argv[3]
+output_argumentloader_filename = sys.argv[4]
+
+json_file = open(sys.argv[1], "r")
+json_text = json_file.read()
+json_file.close()
+
+json_object = json.loads(json_text)
+
+options = json_object["Options"]
+unnamed_options = json_object["UnnamedOptions"]
+
+check_for_duplicate_options(options)
+
+# Generate config include file
+output_file = open(output_filename, "w")
+print_header()
+print_options(options)
+print_unnamed_options(unnamed_options)
+print_tail()
+output_file.close()
+
+# Generate man file
+output_man = open(output_man_page, "w")
+print_man_header()
+print_man_options(options)
+print_man_environment(options)
+print_man_tail()
+
+output_man.close()
+
+# Generate argument loader code
+output_argloader = open(output_argumentloader_filename, "w")
+print_argloader_options(options);
+print_parse_argloader_options(options);
+output_argloader.close()

External/FEXCore/Scripts/json_ir_generator.py

@@ -108,10 +108,10 @@ def print_ir_sizes(ops, defines):
 
     output_file.write("[[maybe_unused]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }\n\n")
 
-    output_file.write("std::string_view const& GetName(IROps Op);\n")
-    output_file.write("uint8_t GetArgs(IROps Op);\n")
-    output_file.write("FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
-    output_file.write("bool HasSideEffects(IROps Op);\n")
+    output_file.write("__attribute__((const)) __attribute__((visibility(\"default\"))) std::string_view const& GetName(IROps Op);\n")
+    output_file.write("__attribute__((const)) __attribute__((visibility(\"default\"))) uint8_t GetArgs(IROps Op);\n")
+    output_file.write("__attribute__((const)) __attribute__((visibility(\"default\"))) FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
+    output_file.write("__attribute__((const)) __attribute__((visibility(\"default\"))) bool HasSideEffects(IROps Op);\n")
 
     output_file.write("#undef IROP_SIZES\n")
     output_file.write("#endif\n\n")
@@ -277,7 +277,7 @@ def print_ir_allocator_helpers(ops, defines):
     output_file.write("\tusing IRPair = Wrapper<T>;\n\n")
 
     output_file.write("\tIRPair<IROp_Header> AllocateRawOp(size_t HeaderSize) {\n")
-    output_file.write("\t\tauto Op = reinterpret_cast<IROp_Header*>(Data.Allocate(HeaderSize));\n")
+    output_file.write("\t\tauto Op = reinterpret_cast<IROp_Header*>(DualListData.DataAllocate(HeaderSize));\n")
     output_file.write("\t\tmemset(Op, 0, HeaderSize);\n")
     output_file.write("\t\tOp->Op = IROps::OP_DUMMY;\n")
     output_file.write("\t\treturn IRPair<IROp_Header>{Op, CreateNode(Op)};\n")
@@ -286,7 +286,7 @@ def print_ir_allocator_helpers(ops, defines):
     output_file.write("\ttemplate<class T, IROps T2>\n")
     output_file.write("\tT *AllocateOrphanOp() {\n")
     output_file.write("\t\tsize_t Size = FEXCore::IR::GetSize(T2);\n")
-    output_file.write("\t\tauto Op = reinterpret_cast<T*>(Data.Allocate(Size));\n")
+    output_file.write("\t\tauto Op = reinterpret_cast<T*>(DualListData.DataAllocate(Size));\n")
     output_file.write("\t\tmemset(Op, 0, Size);\n")
     output_file.write("\t\tOp->Header.Op = T2;\n")
     output_file.write("\t\treturn Op;\n")
@@ -295,25 +295,25 @@ def print_ir_allocator_helpers(ops, defines):
     output_file.write("\ttemplate<class T, IROps T2>\n")
     output_file.write("\tIRPair<T> AllocateOp() {\n")
     output_file.write("\t\tsize_t Size = FEXCore::IR::GetSize(T2);\n")
-    output_file.write("\t\tauto Op = reinterpret_cast<T*>(Data.Allocate(Size));\n")
+    output_file.write("\t\tauto Op = reinterpret_cast<T*>(DualListData.DataAllocate(Size));\n")
     output_file.write("\t\tmemset(Op, 0, Size);\n")
     output_file.write("\t\tOp->Header.Op = T2;\n")
     output_file.write("\t\treturn IRPair<T>{Op, CreateNode(&Op->Header)};\n")
     output_file.write("\t}\n\n")
 
     output_file.write("\tuint8_t GetOpSize(OrderedNode *Op) const {\n")
-    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(Data.Begin());\n")
+    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
     output_file.write("\t\treturn HeaderOp->Size;\n")
     output_file.write("\t}\n\n")
 
     output_file.write("\tuint8_t GetOpElements(OrderedNode *Op) const {\n")
-    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(Data.Begin());\n")
-    output_file.write("\t\tLogMan::Throw::A(HeaderOp->HasDest, \"Op %s has no dest\\n\", GetName(HeaderOp->Op));\n")
+    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
+    output_file.write("\t\tLOGMAN_THROW_A(HeaderOp->HasDest, \"Op %s has no dest\\n\", GetName(HeaderOp->Op));\n")
     output_file.write("\t\treturn HeaderOp->Size / HeaderOp->ElementSize;\n")
     output_file.write("\t}\n\n")
 
     output_file.write("\tbool OpHasDest(OrderedNode *Op) const {\n")
-    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(Data.Begin());\n")
+    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
     output_file.write("\t\treturn HeaderOp->HasDest;\n")
     output_file.write("\t}\n\n")
 
@@ -387,11 +387,14 @@ def print_ir_allocator_helpers(ops, defines):
             output_file.write(") {\n")
 
             output_file.write("\t\tauto Op = AllocateOp<IROp_%s, IROps::OP_%s>();\n" % (op_key, op_key.upper()))
-            output_file.write("\t\tOp.first->Header.NumArgs = %d;\n" % (SSAArgs))
+
+            if (SSAArgs != 0):
+                output_file.write("\t\tauto ListDataBegin = DualListData.ListBegin();\n")
+                for i in range(0, SSAArgs):
+                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(ListDataBegin);\n" % (i, i))
 
             if (SSAArgs != 0):
                 for i in range(0, SSAArgs):
-                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(ListData.Begin());\n" % (i, i))
                     output_file.write("\t\tssa%d->AddUse();\n" % (i))
 
             if (HasArgs):
@@ -399,11 +402,6 @@ def print_ir_allocator_helpers(ops, defines):
                     data_name = op_vals["Args"][i]
                     output_file.write("\t\tOp.first->%s = %s;\n" % (data_name, data_name))
 
-            if (HasFixedDestSize):
-                output_file.write("\t\tOp.first->Header.Size = %d;\n" % FixedDestSize)
-            if (HasDestSize):
-                output_file.write("\t\tOp.first->Header.Size = %s;\n" % DestSize)
-
             if (HasDest):
                 # We can only infer a size if we have arguments
                 if not (HasFixedDestSize or HasDestSize):
@@ -412,10 +410,18 @@ def print_ir_allocator_helpers(ops, defines):
                     if (SSAArgs != 0):
                         for i in range(0, SSAArgs):
                             output_file.write("\t\tuint8_t Size%d = GetOpSize(ssa%s);\n" % (i, i))
+                        for i in range(0, SSAArgs):
                             output_file.write("\t\tInferSize = std::max(InferSize, Size%d);\n" % (i))
 
                     output_file.write("\t\tOp.first->Header.Size = InferSize;\n")
 
+            output_file.write("\t\tOp.first->Header.NumArgs = %d;\n" % (SSAArgs))
+
+            if (HasFixedDestSize):
+                output_file.write("\t\tOp.first->Header.Size = %d;\n" % FixedDestSize)
+            if (HasDestSize):
+                output_file.write("\t\tOp.first->Header.Size = %s;\n" % DestSize)
+
             output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / (%s);\n" % NumElements)
 
             if (HasDest):
@@ -499,7 +505,7 @@ def print_ir_parser_allocator_helpers(ops, defines):
 
             if (SSAArgs != 0):
                 for i in range(0, SSAArgs):
-                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(ListData.Begin());\n" % (i, i))
+                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(DualListData.ListBegin());\n" % (i, i))
                     output_file.write("\t\tssa%d->AddUse();\n" % (i))
 
             if (HasArgs):

External/FEXCore/Source/CMakeLists.txt

@@ -1,49 +1,4 @@
-if (ENABLE_CLANG_FORMAT)
-  find_program(CLANG_TIDY_EXE "clang-tidy")
-  set(CLANG_TIDY_FLAGS
-    "-checks=*"
-    "-fuchsia*"
-    "-bugprone-macro-parentheses"
-    "-clang-analyzer-core.*"
-    "-cppcoreguidelines-pro-type-*"
-    "-cppcoreguidelines-pro-bounds-array-to-pointer-decay"
-    "-cppcoreguidelines-pro-bounds-pointer-arithmetic"
-    "-cppcoreguidelines-avoid-c-arrays"
-    "-cppcoreguidelines-avoid-magic-numbers"
-    "-cppcoreguidelines-pro-bounds-constant-array-index"
-    "-cppcoreguidelines-no-malloc"
-    "-cppcoreguidelines-special-member-functions"
-    "-cppcoreguidelines-owning-memory"
-    "-cppcoreguidelines-macro-usage"
-    "-cppcoreguidelines-avoid-goto"
-    "-google-readability-function-size"
-    "-google-readability-namespace-comments"
-    "-google-readability-braces-around-statements"
-    "-google-build-using-namespace"
-    "-hicpp-*"
-    "-llvm-namespace-comment"
-    "-llvm-include-order" # Messes up with case sensitivity
-    "-misc-unused-parameters"
-    "-modernize-loop-convert"
-    "-modernize-use-auto"
-    "-modernize-avoid-c-arrays"
-    "-modernize-use-nodiscard"
-    "readability-*"
-    "-readability-function-size"
-    "-readability-implicit-bool-conversion"
-    "-readability-braces-around-statements"
-    "-readability-else-after-return"
-    "-readability-magic-numbers"
-    "-readability-named-parameter"
-    "-readability-uppercase-literal-suffix"
-    "-cert-err34-c"
-    "-cert-err58-cpp"
-    "-bugprone-exception-escape"
-    )
-  string(REPLACE ";" "," CLANG_TIDY_FLAGS "${CLANG_TIDY_FLAGS}")
-
-  set(CMAKE_CXX_CLANG_TIDY ${CLANG_TIDY_EXE} "${CLANG_TIDY_FLAGS}")
-endif()
+set (MAN_DIR ${CMAKE_INSTALL_PREFIX}/share/man CACHE PATH "MAN_DIR")
 
 set (SRCS
   Common/Paths.cpp
@@ -130,6 +85,11 @@ set (SRCS
   Interface/Core/X86Tables.cpp
   Interface/Core/X86DebugInfo.cpp
   Interface/Core/X86HelperGen.cpp
+  Interface/Core/ArchHelpers/Arm64_stubs.cpp
+  Interface/Core/ArchHelpers/Arm64Emitter.cpp
+  Interface/Core/Dispatcher/Dispatcher.cpp
+  Interface/Core/Dispatcher/X86Dispatcher.cpp
+  Interface/Core/Dispatcher/Arm64Dispatcher.cpp
   Interface/Core/Interpreter/InterpreterCore.cpp
   Interface/Core/Interpreter/InterpreterOps.cpp
   Interface/Core/X86Tables/BaseTables.cpp
@@ -154,6 +114,7 @@ set (SRCS
   Interface/IR/Passes/DeadContextStoreElimination.cpp
   Interface/IR/Passes/IRCompaction.cpp
   Interface/IR/Passes/IRValidation.cpp
+  Interface/IR/Passes/LongDivideRemovalPass.cpp
   Interface/IR/Passes/ValueDominanceValidation.cpp
   Interface/IR/Passes/PhiValidation.cpp
   Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
@@ -161,61 +122,63 @@ set (SRCS
   Interface/IR/Passes/StaticRegisterAllocationPass.cpp
   Interface/IR/Passes/RegisterAllocationPass.cpp
   Interface/IR/Passes/SyscallOptimization.cpp
-  Utils/ELFLoader.cpp
+  Utils/Allocator.cpp
+  Utils/Allocator/64BitAllocator.cpp
+  Utils/ELFContainer.cpp
   Utils/ELFSymbolDatabase.cpp
   Utils/LogManager.cpp
+  Utils/Threads.cpp
   )
 
-if (_M_X86_64)
-  list(APPEND SRCS Interface/Core/Interpreter/x86_64Dispatcher.cpp)
-endif()
 if(_M_ARM_64)
   list(APPEND SRCS
-    Interface/Core/ArchHelpers/Arm64.cpp
-    Interface/Core/Interpreter/Arm64Dispatcher.cpp)
+    Interface/Core/ArchHelpers/Arm64.cpp)
 endif()
 
-set (JIT_LIBS )
-if (ENABLE_JIT)
-  if (_M_X86_64)
-    add_definitions(-D_M_X86_64=1)
-    if (NOT FORCE_AARCH64)
-      list(APPEND SRCS
-        Interface/Core/JIT/x86_64/JIT.cpp
-        Interface/Core/JIT/x86_64/ALUOps.cpp
-        Interface/Core/JIT/x86_64/AtomicOps.cpp
-        Interface/Core/JIT/x86_64/BranchOps.cpp
-        Interface/Core/JIT/x86_64/ConversionOps.cpp
-        Interface/Core/JIT/x86_64/EncryptionOps.cpp
-        Interface/Core/JIT/x86_64/FlagOps.cpp
-        Interface/Core/JIT/x86_64/MemoryOps.cpp
-        Interface/Core/JIT/x86_64/MiscOps.cpp
-        Interface/Core/JIT/x86_64/MoveOps.cpp
-        Interface/Core/JIT/x86_64/VectorOps.cpp)
-    endif()
-  endif()
-  if(_M_ARM_64)
-    add_definitions(-D_M_ARM_64=1)
-    add_definitions(-DVIXL_INCLUDE_TARGET_AARCH64=1)
-    add_definitions(-DVIXL_CODE_BUFFER_MMAP=1)
-    list(APPEND SRCS
-      Interface/Core/JIT/Arm64/JIT.cpp
-      Interface/Core/JIT/Arm64/ALUOps.cpp
-      Interface/Core/JIT/Arm64/AtomicOps.cpp
-      Interface/Core/JIT/Arm64/BranchOps.cpp
-      Interface/Core/JIT/Arm64/ConversionOps.cpp
-      Interface/Core/JIT/Arm64/EncryptionOps.cpp
-      Interface/Core/JIT/Arm64/FlagOps.cpp
-      Interface/Core/JIT/Arm64/MemoryOps.cpp
-      Interface/Core/JIT/Arm64/MiscOps.cpp
-      Interface/Core/JIT/Arm64/MoveOps.cpp
-      Interface/Core/JIT/Arm64/VectorOps.cpp)
-    list(APPEND JIT_LIBS vixl)
-  endif()
+set(DEFINES )
+
+if (_M_X86_64)
+  list(APPEND DEFINES -D_M_X86_64=1)
+endif()
+
+if (_M_ARM_64)
+  list(APPEND DEFINES -D_M_ARM_64=1)
+endif()
+
+if (ENABLE_JIT_X86_64)
+  list(APPEND SRCS
+    Interface/Core/JIT/x86_64/JIT.cpp
+    Interface/Core/JIT/x86_64/ALUOps.cpp
+    Interface/Core/JIT/x86_64/AtomicOps.cpp
+    Interface/Core/JIT/x86_64/BranchOps.cpp
+    Interface/Core/JIT/x86_64/ConversionOps.cpp
+    Interface/Core/JIT/x86_64/EncryptionOps.cpp
+    Interface/Core/JIT/x86_64/FlagOps.cpp
+    Interface/Core/JIT/x86_64/MemoryOps.cpp
+    Interface/Core/JIT/x86_64/MiscOps.cpp
+    Interface/Core/JIT/x86_64/MoveOps.cpp
+    Interface/Core/JIT/x86_64/VectorOps.cpp)
+  list(APPEND DEFINES -DJIT_X86_64)
+endif()
+
+if (ENABLE_JIT_ARM64)
+  list(APPEND DEFINES -DJIT_ARM64)
+  list(APPEND SRCS
+    Interface/Core/JIT/Arm64/JIT.cpp
+    Interface/Core/JIT/Arm64/ALUOps.cpp
+    Interface/Core/JIT/Arm64/AtomicOps.cpp
+    Interface/Core/JIT/Arm64/BranchOps.cpp
+    Interface/Core/JIT/Arm64/ConversionOps.cpp
+    Interface/Core/JIT/Arm64/EncryptionOps.cpp
+    Interface/Core/JIT/Arm64/FlagOps.cpp
+    Interface/Core/JIT/Arm64/MemoryOps.cpp
+    Interface/Core/JIT/Arm64/MiscOps.cpp
+    Interface/Core/JIT/Arm64/MoveOps.cpp
+    Interface/Core/JIT/Arm64/VectorOps.cpp)
 endif()
 
 if (ENABLE_JITSYMBOLS)
-  add_definitions(-DENABLE_JITSYMBOLS=1)
+  list(APPEND DEFINES -DENABLE_JITSYMBOLS=1)
 endif()
 
 # Generate IR include file
@@ -251,21 +214,64 @@ add_custom_command(
 set_source_files_properties(${OUTPUT_IR_NAME} PROPERTIES
   GENERATED TRUE)
 
-# Create teh target
+# Create the target
 add_custom_target(IR_INC
   DEPENDS "${OUTPUT_NAME}"
   DEPENDS "${OUTPUT_IR_DOC}")
 
+# Generate the configuration include file
+set(OUTPUT_CONFIG_FOLDER "${CMAKE_BINARY_DIR}/include/FEXCore/Config")
+set(OUTPUT_CONFIG_NAME "${OUTPUT_CONFIG_FOLDER}/ConfigValues.inl")
+set(OUTPUT_CONFIG_OPTION_NAME "${OUTPUT_CONFIG_FOLDER}/ConfigOptions.inl")
+set(INPUT_CONFIG_NAME "${CMAKE_CURRENT_SOURCE_DIR}/Interface/Config/Config.json")
+set(OUTPUT_MAN_NAME "${CMAKE_BINARY_DIR}/generated/FEX.1")
+
+add_custom_target(CREATE_CONFIG_FOLDER ALL
+  COMMAND ${CMAKE_COMMAND} -E make_directory "${OUTPUT_CONFIG_FOLDER}")
+
+add_custom_command(
+  OUTPUT "${OUTPUT_CONFIG_NAME}"
+  OUTPUT "${OUTPUT_CONFIG_OPTION_NAME}"
+  OUTPUT "${OUTPUT_MAN_NAME}"
+  DEPENDS "${INPUT_CONFIG_NAME}"
+  DEPENDS CREATE_CONFIG_FOLDER
+  DEPENDS "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/config_generator.py"
+  COMMAND "python3" "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/config_generator.py" "${INPUT_CONFIG_NAME}" "${OUTPUT_CONFIG_NAME}" "${OUTPUT_MAN_NAME}"
+  "${OUTPUT_CONFIG_OPTION_NAME}"
+  )
+
+set_source_files_properties(${OUTPUT_CONFIG_NAME} PROPERTIES
+  GENERATED TRUE)
+set_source_files_properties(${OUTPUT_CONFIG_OPTION_NAME} PROPERTIES
+  GENERATED TRUE)
+
+set_source_files_properties(${OUTPUT_MAN_NAME} PROPERTIES
+  GENERATED TRUE)
+
+# Create the target
+add_custom_target(CONFIG_INC
+  DEPENDS "${OUTPUT_CONFIG_NAME}"
+  DEPENDS "${OUTPUT_CONFIG_OPTION_NAME}"
+  DEPENDS "${OUTPUT_MAN_NAME}")
+
+# Install the man page
+install(FILES ${OUTPUT_MAN_NAME} DESTINATION ${MAN_DIR}/man1)
+
 # Add in diagnostic colours if the option is available.
 # Ninja code generator will kill colours if this isn't here
 check_cxx_compiler_flag(-fdiagnostics-color=always GCC_COLOR)
 check_cxx_compiler_flag(-fcolor-diagnostics CLANG_COLOR)
 
-function(AddLibrary Name Type)
+function(AddObject Name Type)
   add_library(${Name} ${Type} ${SRCS})
   add_dependencies(${Name} IR_INC)
-  target_link_libraries(${Name} pthread rt ${JIT_LIBS} ${LINUX_LIBS} dl)
+  add_dependencies(${Name} CONFIG_INC)
+
+  target_link_libraries(${Name} pthread vixl dl fmt::fmt xxhash FEX_jemalloc)
   set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+  set_target_properties(${Name} PROPERTIES C_VISIBILITY_PRESET hidden)
+  set_target_properties(${Name} PROPERTIES CXX_VISIBILITY_PRESET hidden)
+  set_target_properties(${Name} PROPERTIES VISIBILITY_INLINES_HIDDEN TRUE)
 
   target_include_directories(${Name} PUBLIC "${CMAKE_CURRENT_BINARY_DIR}")
 
@@ -275,9 +281,16 @@ function(AddLibrary Name Type)
   target_include_directories(${Name} PUBLIC "${PROJECT_SOURCE_DIR}/include/")
   target_include_directories(${Name} PUBLIC "${CMAKE_BINARY_DIR}/include/")
 
+  target_compile_definitions(${Name} PRIVATE ${DEFINES})
+
   target_compile_options(${Name}
     PRIVATE
-    -Wno-trigraphs -Wall)
+    -Wall
+    -Werror=implicit-fallthrough
+
+    -Wno-trigraphs
+    -ffunction-sections
+  )
 
   if (GCC_COLOR)
     target_compile_options(${Name}
@@ -291,6 +304,29 @@ function(AddLibrary Name Type)
   endif()
 endfunction()
 
+function(AddLibrary Name Type)
+  add_library(${Name} ${Type} $<TARGET_OBJECTS:${PROJECT_NAME}_object>)
+  target_link_libraries(${Name} pthread vixl dl fmt::fmt xxhash FEX_jemalloc)
+  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+  set_target_properties(${Name} PROPERTIES C_VISIBILITY_PRESET hidden)
+  set_target_properties(${Name} PROPERTIES CXX_VISIBILITY_PRESET hidden)
+  set_target_properties(${Name} PROPERTIES VISIBILITY_INLINES_HIDDEN TRUE)
+
+  target_include_directories(${Name} PUBLIC "${CMAKE_CURRENT_BINARY_DIR}")
+  target_include_directories(${Name} PUBLIC "${PROJECT_SOURCE_DIR}/include/")
+  target_include_directories(${Name} PUBLIC "${CMAKE_BINARY_DIR}/include/")
+
+  if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
+    target_link_options(${Name}
+      PRIVATE
+      "LINKER:--gc-sections"
+      "LINKER:--strip-all"
+      "LINKER:--as-needed"
+    )
+  endif()
+endfunction()
+
+AddObject(${PROJECT_NAME}_object OBJECT)
 AddLibrary(${PROJECT_NAME} STATIC)
 AddLibrary(${PROJECT_NAME}_shared SHARED)
 

External/FEXCore/Source/Common/BitSet.h

@@ -1,5 +1,6 @@
 #pragma once
 #include "Common/MathUtils.h"
+#include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/LogManager.h>
 
 #include <cstring>
@@ -16,16 +17,16 @@ struct BitSet final {
   ElementType *Memory;
   void Allocate(size_t Elements) {
     size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
-    LogMan::Throw::A((AllocateSize * MinimumSize) >= Elements, "Fail");
-    Memory = static_cast<ElementType*>(malloc(AllocateSize));
+    LOGMAN_THROW_A((AllocateSize * MinimumSize) >= Elements, "Fail");
+    Memory = static_cast<ElementType*>(FEXCore::Allocator::malloc(AllocateSize));
   }
   void Realloc(size_t Elements) {
     size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
-    LogMan::Throw::A((AllocateSize * MinimumSize) >= Elements, "Fail");
-    Memory = static_cast<ElementType*>(realloc(Memory, AllocateSize));
+    LOGMAN_THROW_A((AllocateSize * MinimumSize) >= Elements, "Fail");
+    Memory = static_cast<ElementType*>(FEXCore::Allocator::realloc(Memory, AllocateSize));
   }
   void Free() {
-    free(Memory);
+    FEXCore::Allocator::free(Memory);
     Memory = nullptr;
   }
   bool Get(T Element) {
@@ -60,7 +61,7 @@ struct BitSetView final {
   ElementType *Memory;
 
   void GetView(BitSet<T> &Set, uint64_t ElementOffset) {
-    LogMan::Throw::A((ElementOffset % MinimumSize) == 0,
+    LOGMAN_THROW_A((ElementOffset % MinimumSize) == 0,
         "Bitset view offset needs to be aligned to size of backing element");
     Memory = &Set.Memory[ElementOffset / MinimumSizeBits];
   }

External/FEXCore/Source/Common/Paths.cpp

@@ -6,10 +6,13 @@
 #include <sys/stat.h>
 
 namespace FEXCore::Paths {
-  std::string CachePath;
-  std::string EntryCache;
+  std::unique_ptr<std::string> CachePath;
+  std::unique_ptr<std::string> EntryCache;
 
   void InitializePaths() {
+    CachePath = std::make_unique<std::string>();
+    EntryCache = std::make_unique<std::string>();
+
     char const *HomeDir = getenv("HOME");
 
     if (!HomeDir) {
@@ -22,29 +25,34 @@ namespace FEXCore::Paths {
 
     char *XDGDataDir = getenv("XDG_DATA_DIR");
     if (XDGDataDir) {
-      CachePath = XDGDataDir;
+      *CachePath = XDGDataDir;
     }
     else {
       if (HomeDir) {
-        CachePath = HomeDir;
+        *CachePath = HomeDir;
       }
     }
 
-    CachePath += "/.fex-emu/";
-    EntryCache = CachePath + "/EntryCache/";
+    *CachePath += "/.fex-emu/";
+    *EntryCache = *CachePath + "/EntryCache/";
 
     // Ensure the folder structure is created for our Data
-    if (!std::filesystem::exists(EntryCache) &&
-        !std::filesystem::create_directories(EntryCache)) {
-      LogMan::Msg::D("Couldn't create EntryCache directory: '%s'", EntryCache.c_str());
+    if (!std::filesystem::exists(*EntryCache) &&
+        !std::filesystem::create_directories(*EntryCache)) {
+      LogMan::Msg::D("Couldn't create EntryCache directory: '%s'", EntryCache->c_str());
     }
   }
 
+  void ShutdownPaths() {
+    CachePath.reset();
+    EntryCache.reset();
+  }
+
   std::string GetCachePath() {
-    return CachePath;
+    return *CachePath;
   }
 
   std::string GetEntryCachePath() {
-    return EntryCache;
+    return *EntryCache;
   }
 }

External/FEXCore/Source/Common/Paths.h

@@ -3,6 +3,7 @@
 
 namespace FEXCore::Paths {
   void InitializePaths();
+  void ShutdownPaths();
   std::string GetCachePath();
   std::string GetEntryCachePath();
 }

External/FEXCore/Source/Common/SoftFloat-3e/extF80_roundToInt.c

@@ -96,6 +96,7 @@ extFloat80_t
         switch ( roundingMode ) {
          case softfloat_round_near_even:
             if ( !(sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) break;
+            __attribute__((fallthrough));
          case softfloat_round_near_maxMag:
             if ( exp == 0x3FFE ) goto mag1;
             break;

External/FEXCore/Source/Common/SoftFloat.h

@@ -77,7 +77,7 @@ struct X80SoftFloat {
   }
 
   static X80SoftFloat FRNDINT(X80SoftFloat const &lhs) {
-    return extF80_roundToInt(lhs, softfloat_round_near_even, false);
+    return extF80_roundToInt(lhs, softfloat_roundingMode, false);
   }
 
   static X80SoftFloat FXTRACT_SIG(X80SoftFloat const &lhs) {
@@ -173,19 +173,26 @@ struct X80SoftFloat {
   }
 
   operator int16_t() const {
-    return extF80_to_i32(*this, softfloat_round_near_even, false);
+    auto rv = extF80_to_i32(*this, softfloat_roundingMode, false);
+    if (rv > INT16_MAX) {
+      return INT16_MAX;
+    } else if (rv < INT16_MIN) {
+      return INT16_MIN;
+    } else {
+      return rv;
+    }
   }
 
   operator int32_t() const {
-    return extF80_to_i32(*this, softfloat_round_near_even, false);
+    return extF80_to_i32(*this, softfloat_roundingMode, false);
   }
 
   operator int64_t() const {
-    return extF80_to_i64(*this, softfloat_round_near_even, false);
+    return extF80_to_i64(*this, softfloat_roundingMode, false);
   }
 
   operator uint64_t() const {
-    return extF80_to_ui64(*this, softfloat_round_near_even, false);
+    return extF80_to_ui64(*this, softfloat_roundingMode, false);
   }
 
   void operator=(const float rhs) {

External/FEXCore/Source/Common/StringConv.h

@@ -38,4 +38,11 @@ namespace FEXCore::StrConv {
     *Result = Value;
     return true;
   }
+  template <typename T,
+    typename = std::enable_if<std::is_enum<T>::value, T>>
+  [[maybe_unused]] static bool Conv(std::string_view Value, T *Result) {
+    *Result = static_cast<T>(std::stoull(std::string(Value), nullptr, 0));
+    return true;
+  }
+
 }

External/FEXCore/Source/Interface/Config/Config.cpp

@@ -4,106 +4,123 @@
 #include "Interface/Context/Context.h"
 
 #include <FEXCore/Config/Config.h>
+#include <filesystem>
+#include <pwd.h>
 #include <map>
+#include <sys/sysinfo.h>
+#include <unistd.h>
 
 namespace FEXCore::Config {
-  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, uint64_t Config) {
-    switch (Option) {
-    case FEXCore::Config::CONFIG_MULTIBLOCK:
-      CTX->Config.Multiblock = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_MAXBLOCKINST:
-      CTX->Config.MaxInstPerBlock = Config;
-    break;
-    case FEXCore::Config::CONFIG_DEFAULTCORE:
-      CTX->Config.Core = static_cast<FEXCore::Config::ConfigCore>(Config);
-    break;
-    case FEXCore::Config::CONFIG_VIRTUALMEMSIZE:
-      CTX->Config.VirtualMemSize = Config;
-    break;
-    case FEXCore::Config::CONFIG_SINGLESTEP:
-      CTX->Config.RunningMode = Config != 0 ? FEXCore::Context::CoreRunningMode::MODE_SINGLESTEP : FEXCore::Context::CoreRunningMode::MODE_RUN;
-    break;
-    case FEXCore::Config::CONFIG_GDBSERVER:
-      Config != 0 ? CTX->StartGdbServer() : CTX->StopGdbServer();
-    break;
-    case FEXCore::Config::CONFIG_IS64BIT_MODE:
-      CTX->Config.Is64BitMode = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_TSO_ENABLED:
-      CTX->Config.TSOEnabled = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_SMC_CHECKS:
-      CTX->Config.SMCChecks = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_ABI_LOCAL_FLAGS:
-      CTX->Config.ABILocalFlags = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_ABI_NO_PF:
-      CTX->Config.ABINoPF = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_VALIDATE_IR_PARSER:
-      CTX->Config.ValidateIRarser = Config != 0;
-    break;
-    default: LogMan::Msg::A("Unknown configuration option");
+  char const* FindUserHomeThroughUID() {
+    auto passwd = getpwuid(geteuid());
+    if (passwd) {
+      return passwd->pw_dir;
     }
+    return nullptr;
+  }
+
+  const char *GetHomeDirectory() {
+    char const *HomeDir = getenv("HOME");
+
+    // Try to get home directory from uid
+    if (!HomeDir) {
+      HomeDir = FindUserHomeThroughUID();
+    }
+
+    // try the PWD
+    if (!HomeDir) {
+      HomeDir = getenv("PWD");
+    }
+
+    // Still doesn't exit? You get local
+    if (!HomeDir) {
+      HomeDir = ".";
+    }
+
+    return HomeDir;
+  }
+
+  std::string GetConfigDirectory(bool Global) {
+    std::string ConfigDir;
+    if (Global) {
+      ConfigDir = GLOBAL_DATA_DIRECTORY;
+    }
+    else {
+      char const *HomeDir = GetHomeDirectory();
+      char const *ConfigXDG = getenv("XDG_CONFIG_HOME");
+      char const *ConfigOverride = getenv("FEX_APP_CONFIG_LOCATION");
+      if (ConfigOverride) {
+        // Config override completely overrides the config directory
+        ConfigDir = ConfigOverride;
+      }
+      else {
+        ConfigDir = ConfigXDG ? ConfigXDG : HomeDir;
+        ConfigDir += "/.fex-emu/";
+      }
+
+      // Ensure the folder structure is created for our configuration
+      if (!std::filesystem::exists(ConfigDir) &&
+          !std::filesystem::create_directories(ConfigDir)) {
+        LogMan::Msg::D("Couldn't create config directory: '%s'", ConfigDir.c_str());
+        // Let's go local in this case
+        return "./";
+      }
+    }
+
+    return ConfigDir;
+  }
+
+  std::string GetConfigFileLocation() {
+    std::string ConfigFile{};
+    const char *AppConfig = getenv("FEX_APP_CONFIG");
+    if (AppConfig) {
+      // App config environment variable overwrites only the config file
+      ConfigFile = AppConfig;
+    }
+    else {
+      ConfigFile = GetConfigDirectory(false) + "Config.json";
+    }
+    return ConfigFile;
+  }
+
+  std::string GetApplicationConfig(const std::string &Filename, bool Global) {
+    std::string ConfigFile = GetConfigDirectory(Global);
+    if (!Global &&
+        !std::filesystem::exists(ConfigFile) &&
+        !std::filesystem::create_directories(ConfigFile)) {
+      LogMan::Msg::D("Couldn't create config directory: '%s'", ConfigFile.c_str());
+      // Let's go local in this case
+      return "./";
+    }
+
+    ConfigFile += "AppConfig/" + Filename + ".json";
+    return ConfigFile;
+  }
+
+  std::string GetDataDirectory() {
+    std::string DataDir{};
+
+    char const *HomeDir = GetHomeDirectory();
+    char const *DataXDG = getenv("XDG_DATA_HOME");
+    char const *DataOverride = getenv("FEX_APP_DATA_LOCATION");
+    if (DataOverride) {
+      // Data override will override the complete directory
+      DataDir = DataOverride;
+    }
+    else {
+      DataDir = DataXDG ?: HomeDir;
+      DataDir += "/.fex-emu/";
+    }
+    return DataDir;
+  }
+
+  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, uint64_t Config) {
   }
 
   void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, std::string const &Config) {
-    switch (Option) {
-    case CONFIG_ROOTFSPATH:
-      CTX->Config.RootFSPath = Config;
-      break;
-    case CONFIG_THUNKLIBSPATH:
-      CTX->Config.ThunkLibsPath = Config;
-      break;
-    case FEXCore::Config::CONFIG_DUMPIR:
-      CTX->Config.DumpIR = Config;
-      break;
-    default: LogMan::Msg::A("Unknown configuration option");
-    }
   }
 
   uint64_t GetConfig(FEXCore::Context::Context *CTX, ConfigOption Option) {
-    switch (Option) {
-    case FEXCore::Config::CONFIG_MULTIBLOCK:
-      return CTX->Config.Multiblock;
-    break;
-    case FEXCore::Config::CONFIG_MAXBLOCKINST:
-      return CTX->Config.MaxInstPerBlock;
-    break;
-    case FEXCore::Config::CONFIG_DEFAULTCORE:
-      return CTX->Config.Core;
-    break;
-    case FEXCore::Config::CONFIG_VIRTUALMEMSIZE:
-      return CTX->Config.VirtualMemSize;
-    break;
-    case FEXCore::Config::CONFIG_SINGLESTEP:
-      return CTX->Config.RunningMode == FEXCore::Context::CoreRunningMode::MODE_SINGLESTEP ? 1 : 0;
-    case FEXCore::Config::CONFIG_GDBSERVER:
-      return CTX->GetGdbServerStatus();
-    break;
-    case FEXCore::Config::CONFIG_IS64BIT_MODE:
-      return CTX->Config.Is64BitMode;
-    break;
-    case FEXCore::Config::CONFIG_TSO_ENABLED:
-      return CTX->Config.TSOEnabled;
-    break;
-    case FEXCore::Config::CONFIG_SMC_CHECKS:
-      return CTX->Config.SMCChecks;
-    break;
-    case FEXCore::Config::CONFIG_ABI_LOCAL_FLAGS:
-      return CTX->Config.ABILocalFlags;
-    break;
-    case FEXCore::Config::CONFIG_ABI_NO_PF:
-      return CTX->Config.ABINoPF;
-    break;
-    case FEXCore::Config::CONFIG_VALIDATE_IR_PARSER:
-      return CTX->Config.ValidateIRarser;
-    break;
-    default: LogMan::Msg::A("Unknown configuration option");
-    }
-
     return 0;
   }
 
@@ -137,6 +154,7 @@ namespace FEXCore::Config {
 
   private:
     void MergeConfigMap(const LayerOptions &Options);
+    void MergeEnvironmentVariables(ConfigOption const &Option, LayerValue const &Value);
   };
 
   void MetaLayer::Load() {
@@ -151,10 +169,56 @@ namespace FEXCore::Config {
     }
   }
 
+
+  void MetaLayer::MergeEnvironmentVariables(ConfigOption const &Option, LayerValue const &Value) {
+    // Environment variables need a bit of additional work
+    // We want to merge the arrays rather than overwrite entirely
+    auto MetaEnvironment = OptionMap.find(Option);
+    if (MetaEnvironment == OptionMap.end()) {
+      // Doesn't exist, just insert
+      OptionMap.insert_or_assign(Option, Value);
+      return;
+    }
+
+    // If an environment variable exists in both current meta and in the incoming layer then the meta layer value is overwritten
+    std::unordered_map<std::string, std::string> LookupMap;
+    const auto AddToMap = [&LookupMap](FEXCore::Config::LayerValue const &Value) {
+      for (const auto &EnvVar : Value) {
+        const auto ItEq = EnvVar.find_first_of('=');
+        if (ItEq == std::string::npos) {
+          // Broken environment variable
+          // Skip
+          continue;
+        }
+        auto Key = std::string(EnvVar.begin(), EnvVar.begin() + ItEq);
+        auto Value = std::string(EnvVar.begin() + ItEq + 1, EnvVar.end());
+
+        // Add the key to the map, overwriting whatever previous value was there
+        LookupMap.insert_or_assign(std::move(Key), std::move(Value));
+      }
+    };
+
+    AddToMap(MetaEnvironment->second);
+    AddToMap(Value);
+
+    // Now with the two layers merged in the map
+    // Add all the values to the option
+    Erase(Option);
+    for (auto &Val : LookupMap) {
+      // Set will emplace multiple options in to its list
+      Set(Option, Val.first + "=" + Val.second);
+    }
+  }
+
   void MetaLayer::MergeConfigMap(const LayerOptions &Options) {
     // Insert this layer's options, overlaying previous options that exist here
     for (auto &it : Options) {
-      OptionMap.insert_or_assign(it.first, it.second);
+      if (it.first == FEXCore::Config::ConfigOption::CONFIG_ENV) {
+        MergeEnvironmentVariables(it.first, it.second);
+      }
+      else {
+        OptionMap.insert_or_assign(it.first, it.second);
+      }
     }
   }
 
@@ -177,8 +241,91 @@ namespace FEXCore::Config {
     }
   }
 
+  std::string ExpandPath(std::string PathName) {
+    if (PathName.empty()) {
+      return {};
+    }
+
+    std::filesystem::path Path{PathName};
+
+    // Expand home if it exists
+    if (Path.is_relative()) {
+      std::string Home = getenv("HOME") ?: "";
+      // Home expansion only works if it is the first character
+      // This matches bash behaviour
+      if (PathName.at(0) == '~') {
+        PathName.replace(0, 1, Home);
+        return PathName;
+      }
+
+      // Expand relative path to absolute
+      Path = std::filesystem::absolute(Path);
+
+      // Only return if it exists
+      if (std::filesystem::exists(Path)) {
+        return Path;
+      }
+    }
+    return {};
+  }
+
   void ReloadMetaLayer() {
     Meta->Load();
+
+    // Do configuration option fix ups after everything is reloaded
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THREADS)) {
+      FEX_CONFIG_OPT(Cores, THREADS);
+      if (Cores == 0) {
+        // When the number of emulated CPU cores is zero then auto detect
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THREADS, std::to_string(get_nprocs_conf()));
+      }
+    }
+
+    auto ExpandPathIfExists = [](FEXCore::Config::ConfigOption Config, std::string PathName) {
+      auto NewPath = ExpandPath(PathName);
+      if (!NewPath.empty()) {
+        FEXCore::Config::EraseSet(Config, NewPath);
+      }
+    };
+
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_ROOTFS)) {
+      FEX_CONFIG_OPT(PathName, ROOTFS);
+      auto ExpandedString = ExpandPath(PathName());
+      if (!ExpandedString.empty()) {
+        // Adjust the path if it ended up being relative
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, ExpandedString);
+      }
+      else if (!PathName().empty()) {
+        // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
+        std::string NamedRootFS = GetDataDirectory() + "RootFS/" + PathName();
+        if (std::filesystem::exists(NamedRootFS)) {
+          FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, NamedRootFS);
+        }
+      }
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKHOSTLIBS)) {
+      FEX_CONFIG_OPT(PathName, THUNKHOSTLIBS);
+      ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKHOSTLIBS, PathName());
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKGUESTLIBS)) {
+      FEX_CONFIG_OPT(PathName, THUNKGUESTLIBS);
+      ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKGUESTLIBS, PathName());
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKCONFIG)) {
+      FEX_CONFIG_OPT(PathName, THUNKCONFIG);
+      ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKCONFIG, PathName());
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_OUTPUTLOG)) {
+      FEX_CONFIG_OPT(PathName, OUTPUTLOG);
+      if (PathName() != "stdout" && PathName() != "stderr") {
+        ExpandPathIfExists(FEXCore::Config::CONFIG_OUTPUTLOG, PathName());
+      }
+    }
+
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_SINGLESTEP)) {
+      // Single stepping also enforces single instruction size blocks
+      Set(FEXCore::Config::ConfigOption::CONFIG_MAXINST, std::to_string(1u));
+    }
   }
 
   void AddLayer(std::unique_ptr<FEXCore::Config::Layer> _Layer) {
@@ -201,6 +348,10 @@ namespace FEXCore::Config {
     Meta->Set(Option, Data);
   }
 
+  void Erase(ConfigOption Option) {
+    Meta->Erase(Option);
+  }
+
   void EraseSet(ConfigOption Option, std::string Data) {
     Meta->EraseSet(Option, Data);
   }
@@ -240,8 +391,14 @@ namespace FEXCore::Config {
     }
   }
 
-  template bool Value<bool>::GetIfExists(FEXCore::Config::ConfigOption Option, bool Default);
-  template uint8_t Value<uint8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint8_t Default);
+  template bool     Value<bool>::GetIfExists(FEXCore::Config::ConfigOption Option, bool Default);
+  template int8_t   Value<int8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int8_t Default);
+  template uint8_t  Value<uint8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint8_t Default);
+  template int16_t   Value<int16_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int16_t Default);
+  template uint16_t  Value<uint16_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint16_t Default);
+  template int32_t  Value<int32_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int32_t Default);
+  template uint32_t Value<uint32_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint32_t Default);
+  template int64_t  Value<int64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int64_t Default);
   template uint64_t Value<uint64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint64_t Default);
 
   // Constructor
@@ -258,5 +415,6 @@ namespace FEXCore::Config {
       *List = **Value;
     }
   }
+  template void Value<std::string>::GetListIfExists(FEXCore::Config::ConfigOption Option, std::list<std::string> *List);
 }
 

External/FEXCore/Source/Interface/Config/Config.json

@@ -0,0 +1,259 @@
+{
+  "Options": {
+    "CPU": {
+      "Core": {
+        "Type": "uint32",
+        "Default": "FEXCore::Config::ConfigCore::CONFIG_IRJIT",
+        "TextDefault": "irjit",
+        "ShortArg": "c",
+        "Choices": [ "irint", "irjit", "host" ],
+        "ArgumentHandler": "CoreHandler",
+        "Desc": [
+          "Which CPU core to use",
+          "host only exists on x86_64",
+          "[irint, irjit, host]"
+        ]
+      },
+      "Multiblock": {
+        "Type": "bool",
+        "Default": "true",
+        "ShortArg": "m",
+        "Desc": [
+          "Controls multiblock code compilation"
+        ]
+      },
+      "MaxInst": {
+        "Type": "int32",
+        "Default": "5000",
+        "ShortArg": "n",
+        "Desc": [
+          "Maximum number of instruction to store in a block"
+        ]
+      },
+      "Threads": {
+        "Type": "uint32",
+        "Default": "1",
+        "ShortArg": "T",
+        "Desc": [
+          "Number of physical hardware threads to tell the process we have.",
+          "0 will auto detect."
+        ]
+      }
+    },
+    "Emulation": {
+      "RootFS": {
+        "Type": "str",
+        "Default": "",
+        "ShortArg": "R",
+        "Desc": [
+          "Which Root filesystem prefix to use",
+          "This can be a filesystem path",
+          "\teg: ~/RootFS/Debian_x86_64",
+          "Or this can be a name of a rootfs",
+          "If the named rootfs exists in the FEX data folder then it will use that one",
+          "\teg: $HOME/.fex-emu/RootFS/<RootFS name>/",
+          "Or if you have XDG_DATA_HOME the config will search in that directory",
+          "\teg: $XDG_DATA_HOME/.fex-emu/RootFS/<RootFS name>/"
+        ]
+      },
+      "ThunkHostLibs": {
+        "Type": "str",
+        "Default": "",
+        "ShortArg": "t",
+        "Desc": [
+          "Folder to find the host-side thunking libraries."
+        ]
+      },
+      "ThunkGuestLibs": {
+        "Type": "str",
+        "Default": "",
+        "ShortArg": "j",
+        "Desc": [
+          "Folder to find the guest-side thunking libraries."
+        ]
+      },
+      "ThunkConfig": {
+        "Type": "str",
+        "Default": "",
+        "ShortArg": "k",
+        "Desc": [
+          "A json file specifying where to overlay the thunks."
+        ]
+      },
+      "Env": {
+        "Type": "strarray",
+        "Default": "",
+        "ShortArg": "E",
+        "Desc": [
+          "Adds an environment variable to the emulated environment."
+        ]
+      }
+    },
+    "Debug": {
+      "SingleStep": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "S",
+        "Desc": [
+          "Single stepping configuration."
+        ]
+      },
+      "GdbServer": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "G",
+        "Desc": [
+          "Enables the GDB server."
+        ]
+      },
+      "DumpIR": {
+        "Type": "str",
+        "Default": "no",
+        "Desc": [
+          "Folder to dump the IR in to.",
+          "[no, stdout, stderr, <Folder>]"
+        ]
+      },
+      "DumpGPRs": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "g",
+        "Desc": [
+          "When the test harness ends, print the GPR state."
+        ]
+      },
+      "O0": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "O0",
+        "Desc": [
+          "Disables optimizations passes for debugging."
+        ]
+      },
+      "Force32BitAllocator": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Forces use of the 32-bit allocator on 32-bit applications",
+          "Used to work around ulimit problems of CI runner",
+          "Potentially useful for debugging memory problems",
+          "32-bit allocator is always used if your host kernel is older than 4.17"
+        ]
+      }
+
+    },
+    "Logging": {
+      "SilentLog": {
+        "Type": "bool",
+        "Default": "true",
+        "ShortArg": "s",
+        "Desc": [
+          "Disables logging"
+        ]
+      },
+      "OutputLog": {
+        "Type": "str",
+        "Default": "stderr",
+        "ShortArg": "o",
+        "Desc": [
+          "File to write FEX output to.",
+          "[stdout, stderr, <Filename>]"
+        ]
+      }
+    },
+    "Hacks": {
+      "SMCChecks": {
+        "Type": "uint8",
+        "Default": "FEXCore::Config::CONFIG_SMC_MMAN",
+        "TextDefault": "mman",
+        "ArgumentHandler": "SMCCheckHandler",
+        "Desc": [
+          "Checks code for modification before execution.",
+          "\tnone: No checks",
+          "\tmman: Invalidate on mmap, mprotect, munmap",
+          "\tfull: Validate code before every run (slow)"
+        ]
+      },
+      "TSOEnabled": {
+        "Type": "bool",
+        "Default": "true",
+        "Desc": [
+          "Controls TSO IR ops.",
+          "Highly likely to break any multithreaded application if disabled."
+        ]
+      },
+      "ABILocalFlags": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "When enabled enables an optimization around flags.",
+          "Assumes flags are not used across cals.",
+          "Hand-written assembly can violate this assumption."
+        ]
+      },
+      "ABINoPF": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "When enabled enables an optimization around parity flag calculation.",
+          "Removes the calculation of the parity flag from GPR instructions.",
+          "Assuming no uses rely on it"
+        ]
+      },
+      "ParanoidTSO": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Makes TSO operations even more strict.",
+          "Forces vector loadstores to also become atomic."
+        ]
+      }
+    },
+    "Misc": {
+      "AOTIRCapture": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Captures IR and generates an AOT IR cache.",
+          "Captures both the loaded executable and libraries it loads."
+        ]
+      },
+      "AOTIRGenerate": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Scans file for executable code and generates an AOT IR cache.",
+          "Does not run the executable."
+        ]
+      },
+      "AOTIRLoad": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Loads an AOT IR cache for the loaded executable."
+        ]
+      }
+    }
+  },
+  "UnnamedOptions": {
+    "Misc": {
+      "IS_INTERPRETER": {
+        "Type": "bool",
+        "Default": "false"
+      },
+      "INTERPRETER_INSTALLED": {
+        "Type": "bool",
+        "Default": "false"
+      },
+      "APP_FILENAME": {
+        "Type": "str",
+        "Default": ""
+      },
+      "IS64BIT_MODE": {
+        "Type": "bool",
+        "Default": "false"
+      }
+    }
+  }
+}
+

External/FEXCore/Source/Interface/Context/Context.cpp

@@ -14,6 +14,10 @@ namespace FEXCore::Context {
     IR::InstallOpcodeHandlers(Mode);
   }
 
+  void ShutdownStaticTables() {
+    FEXCore::Paths::ShutdownPaths();
+  }
+
   FEXCore::Context::Context *CreateNewContext() {
     return new FEXCore::Context::Context{};
   }
@@ -23,6 +27,9 @@ namespace FEXCore::Context {
   }
 
   void DestroyContext(FEXCore::Context::Context *CTX) {
+    if (CTX->ParentThread) {
+      CTX->DestroyThread(CTX->ParentThread);
+    }
     delete CTX;
   }
 
@@ -47,6 +54,9 @@ namespace FEXCore::Context {
     CTX->Step();
   }
 
+  void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
+    Thread->CTX->CompileBlock(Thread->CurrentFrame, GuestRIP);
+  }
 
   FEXCore::Context::ExitReason RunUntilExit(FEXCore::Context::Context *CTX) {
     return CTX->RunUntilExit();
@@ -65,11 +75,11 @@ namespace FEXCore::Context {
   }
 
   void GetCPUState(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
-    memcpy(State, &CTX->ParentThread->State.State, sizeof(FEXCore::Core::CPUState));
+    memcpy(State, CTX->ParentThread->CurrentFrame, sizeof(FEXCore::Core::CPUState));
   }
 
   void SetCPUState(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
-    memcpy(&CTX->ParentThread->State.State, State, sizeof(FEXCore::Core::CPUState));
+    memcpy(CTX->ParentThread->CurrentFrame, State, sizeof(FEXCore::Core::CPUState));
   }
 
   void Pause(FEXCore::Context::Context *CTX) {
@@ -84,10 +94,6 @@ namespace FEXCore::Context {
     CTX->CustomCPUFactory = std::move(Factory);
   }
 
-  void SetFallbackCPUBackendFactory(FEXCore::Context::Context *CTX, CustomCPUFactoryType Factory) {
-    CTX->FallbackCPUFactory = std::move(Factory);
-  }
-
   bool AddVirtualMemoryMapping([[maybe_unused]] FEXCore::Context::Context *CTX, [[maybe_unused]] uint64_t VirtualAddress, [[maybe_unused]] uint64_t PhysicalAddress, [[maybe_unused]] uint64_t Size) {
     return false;
   }
@@ -123,20 +129,12 @@ namespace FEXCore::Context {
     CTX->StopThread(Thread);
   }
 
-  void DeleteForkedThreads(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    // This function is called after fork
-    // We need to cleanup some of the thread data that is dead
-    for (auto &DeadThread : CTX->Threads) {
-      if (DeadThread == Thread) {
-        continue;
-      }
+  void DestroyThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
+    CTX->DestroyThread(Thread);
+  }
 
-      // Setting running to false ensures that when they are shutdown we won't send signals to kill them
-      DeadThread->State.RunningEvents.Running = false;
-    }
-
-    // We now only have one thread
-    CTX->IdleWaitRefCount = 1;
+  void CleanupAfterFork(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
+    CTX->CleanupAfterFork(Thread);
   }
 
   void SetSignalDelegator(FEXCore::Context::Context *CTX, FEXCore::SignalDelegator *SignalDelegation) {
@@ -147,8 +145,31 @@ namespace FEXCore::Context {
     CTX->SyscallHandler = Handler;
   }
 
-  FEXCore::CPUID::FunctionResults RunCPUIDFunction(FEXCore::Context::Context *CTX, uint32_t Function, [[maybe_unused]] uint32_t Leaf) {
-    return CTX->CPUID.RunFunction(Function);
+  FEXCore::CPUID::FunctionResults RunCPUIDFunction(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf) {
+    return CTX->CPUID.RunFunction(Function, Leaf);
+  }
+
+  void SetAOTIRLoader(FEXCore::Context::Context *CTX, std::function<int(const std::string&)> CacheReader) {
+    CTX->AOTIRLoader = CacheReader;
+  }
+
+  void SetAOTIRWriter(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::ostream>(const std::string&)> CacheWriter) {
+    CTX->AOTIRWriter = CacheWriter;
+  }
+
+  void FinalizeAOTIRCache(FEXCore::Context::Context *CTX) {
+    CTX->FinalizeAOTIRCache();
+  }
+
+  void WriteFilesWithCode(FEXCore::Context::Context *CTX, std::function<void(const std::string& fileid, const std::string& filename)> Writer) {
+    CTX->WriteFilesWithCode(Writer);
+  }
+
+  void AddNamedRegion(FEXCore::Context::Context *CTX, uintptr_t Base, uintptr_t Length, uintptr_t Offset, const std::string& Name) {
+    return CTX->AddNamedRegion(Base, Length, Offset, Name);
+  }
+  void RemoveNamedRegion(FEXCore::Context::Context *CTX, uintptr_t Base, uintptr_t Length) {
+    return CTX->RemoveNamedRegion(Base, Length);
   }
 
 namespace Debug {
@@ -163,10 +184,6 @@ namespace Debug {
     return CTX->GetRuntimeStatsForThread(Thread);
   }
 
-  FEXCore::Core::CPUState GetCPUState(FEXCore::Context::Context *CTX) {
-    return CTX->GetCPUState();
-  }
-
   bool GetDebugDataForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::Core::DebugData *Data) {
     return CTX->GetDebugDataForRIP(RIP, Data);
   }
@@ -183,10 +200,6 @@ namespace Debug {
   // void SetIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList *const ir) {
   //   CTX->SetIRForRIP(RIP, ir);
   // }
-
-  FEXCore::Core::ThreadState *GetThreadState(FEXCore::Context::Context *CTX) {
-    return CTX->GetThreadState();
-  }
 }
 
 }

External/FEXCore/Source/Interface/Context/Context.h

@@ -1,4 +1,5 @@
 #pragma once
+
 #include "Common/JitSymbols.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/Frontend.h"
@@ -6,13 +7,24 @@
 #include "Interface/Core/InternalThreadState.h"
 #include "Interface/Core/X86HelperGen.h"
 #include "Interface/IR/PassManager.h"
+#include "Interface/IR/Passes/RegisterAllocationPass.h"
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/Event.h>
 #include <stdint.h>
 
+#include <functional>
+#include <istream>
+#include <map>
 #include <memory>
 #include <mutex>
+#include <optional>
+#include <ostream>
+#include <set>
+#include <shared_mutex>
+#include <unordered_map>
+#include <queue>
 
 namespace FEXCore {
 class ThunkHandler;
@@ -21,7 +33,8 @@ class GdbServer;
 class SiganlDelegator;
 
 namespace CPU {
-  class JITCore;
+  class Arm64JITCore;
+  class X86JITCore;
 }
 namespace HLE {
 class SyscallHandler;
@@ -30,6 +43,8 @@ class SyscallHandler;
 
 namespace FEXCore::IR {
   class RegisterAllocationPass;
+  class RegisterAllocationData;
+  class IRListView;
 namespace Validation {
   class IRValidation;
 }
@@ -41,36 +56,75 @@ namespace FEXCore::Context {
     MODE_SINGLESTEP = 1,
   };
 
+  struct AOTIRInlineEntry {
+    uint64_t GuestHash;
+    uint64_t GuestLength;
+
+    /* RAData followed by IRData */
+    uint8_t InlineData[0];
+
+    IR::RegisterAllocationData *GetRAData();
+    IR::IRListView *GetIRData();
+  };
+
+  struct AOTIRInlineIndexEntry {
+    uint64_t GuestStart;
+    uint64_t DataOffset;
+  };
+
+  struct AOTIRInlineIndex {
+    uint64_t Count;
+    uint64_t DataBase;
+    AOTIRInlineIndexEntry Entries[0];
+
+    AOTIRInlineEntry *Find(uint64_t GuestStart);
+    AOTIRInlineEntry *GetInlineEntry(uint64_t DataOffset);
+  };
+
+  struct AOTIRCaptureCacheEntry {
+    std::unique_ptr<std::ostream> Stream;
+    std::map<uint64_t, uint64_t> Index;
+
+    void AppendAOTIRCaptureCache(uint64_t GuestRIP, uint64_t Start, uint64_t Length, uint64_t Hash, FEXCore::IR::IRListView *IRList, FEXCore::IR::RegisterAllocationData *RAData);
+  };
+
   struct Context {
     friend class FEXCore::HLE::SyscallHandler;
-    friend class FEXCore::CPU::JITCore;
+  #ifdef JIT_ARM64
+    friend class FEXCore::CPU::Arm64JITCore;
+  #endif
+  #ifdef JIT_X86_64
+    friend class FEXCore::CPU::X86JITCore;
+  #endif
+
     friend class FEXCore::IR::Validation::IRValidation;
 
     struct {
-      bool Multiblock {false};
-      bool BreakOnFrontendFailure {true};
-      int64_t MaxInstPerBlock {-1LL};
-      uint64_t VirtualMemSize {1ULL << 36};
       CoreRunningMode RunningMode {CoreRunningMode::MODE_RUN};
-      FEXCore::Config::ConfigCore Core {FEXCore::Config::CONFIG_INTERPRETER};
-      bool GdbServer {false};
-      std::string RootFSPath;
-      std::string ThunkLibsPath;
-
-      bool Is64BitMode {true};
-      bool TSOEnabled {true};
-      bool SMCChecks {false};
-      bool ABILocalFlags {false};
-      bool ABINoPF {false};
-
-      std::string DumpIR;
+      uint64_t VirtualMemSize{1ULL << 36};
 
       // this is for internal use
       bool ValidateIRarser { false };
 
+      FEX_CONFIG_OPT(Multiblock, MULTIBLOCK);
+      FEX_CONFIG_OPT(SingleStepConfig, SINGLESTEP);
+      FEX_CONFIG_OPT(GdbServer, GDBSERVER);
+      FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
+      FEX_CONFIG_OPT(TSOEnabled, TSOENABLED);
+      FEX_CONFIG_OPT(ABILocalFlags, ABILOCALFLAGS);
+      FEX_CONFIG_OPT(ABINoPF, ABINOPF);
+      FEX_CONFIG_OPT(AOTIRCapture, AOTIRCAPTURE);
+      FEX_CONFIG_OPT(AOTIRGenerate, AOTIRGENERATE);
+      FEX_CONFIG_OPT(AOTIRLoad, AOTIRLOAD);
+      FEX_CONFIG_OPT(SMCChecks, SMCCHECKS);
+      FEX_CONFIG_OPT(Core, CORE);
+      FEX_CONFIG_OPT(MaxInstPerBlock, MAXINST);
+      FEX_CONFIG_OPT(RootFSPath, ROOTFS);
+      FEX_CONFIG_OPT(ThunkHostLibsPath, THUNKHOSTLIBS);
+      FEX_CONFIG_OPT(DumpIR, DUMPIR);
     } Config;
 
-    using IntCallbackReturn =  __attribute__((naked)) void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
+    using IntCallbackReturn =  FEX_NAKED void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
     IntCallbackReturn InterpreterCallbackReturn;
 
     FEXCore::HostFeatures HostFeatures;
@@ -93,9 +147,32 @@ namespace FEXCore::Context {
     std::unique_ptr<FEXCore::ThunkHandler> ThunkHandler;
 
     CustomCPUFactoryType CustomCPUFactory;
-    CustomCPUFactoryType FallbackCPUFactory;
     std::function<void(uint64_t ThreadId, FEXCore::Context::ExitReason)> CustomExitHandler;
 
+    struct AOTIRCacheEntry {
+      AOTIRInlineIndex *Array;
+      void *mapping;
+      size_t size;
+    };
+
+    std::unordered_map<std::string, AOTIRCacheEntry> AOTIRCache;
+    std::function<int(const std::string&)> AOTIRLoader;
+    std::function<std::unique_ptr<std::ostream>(const std::string&)> AOTIRWriter;
+    std::unordered_map<std::string, AOTIRCaptureCacheEntry> AOTIRCaptureCache;
+
+    struct AddrToFileEntry {
+      uint64_t Start;
+      uint64_t Len;
+      uint64_t Offset;
+      std::string fileid;
+      std::string filename;
+      void *CachedFileEntry;
+      bool ContainsCode;
+    };
+
+    std::map<uint64_t, AddrToFileEntry> AddrToFile;
+    std::map<std::string, std::string> FilesWithCode;
+
 #ifdef BLOCKSTATS
     std::unique_ptr<FEXCore::BlockSamplingData> BlockData;
 #endif
@@ -108,7 +185,7 @@ namespace FEXCore::Context {
 
     bool InitCore(FEXCore::CodeLoader *Loader);
     FEXCore::Context::ExitReason RunUntilExit();
-    int GetProgramStatus();
+    int GetProgramStatus() const;
     bool IsPaused() const { return !Running; }
     void Pause();
     void Run();
@@ -119,7 +196,7 @@ namespace FEXCore::Context {
     void StopThread(FEXCore::Core::InternalThreadState *Thread);
     void SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event);
 
-    bool GetGdbServerStatus() { return (bool)DebugServer; }
+    bool GetGdbServerStatus() const { return DebugServer != nullptr; }
     void StartGdbServer();
     void StopGdbServer();
     void HandleCallback(uint64_t RIP);
@@ -128,25 +205,30 @@ namespace FEXCore::Context {
 
     static void RemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
 
+    // Wrapper which takes CpuStateFrame instead of InternalThreadState
+    static void RemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
+      RemoveCodeEntry(Frame->Thread, GuestRIP);
+    }
+
     // Debugger interface
     void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
     uint64_t GetThreadCount() const;
     FEXCore::Core::RuntimeStats *GetRuntimeStatsForThread(uint64_t Thread);
-    FEXCore::Core::CPUState GetCPUState();
     bool GetDebugDataForRIP(uint64_t RIP, FEXCore::Core::DebugData *Data);
     bool FindHostCodeForRIP(uint64_t RIP, uint8_t **Code);
 
-    // XXX:
-    // bool FindIRForRIP(uint64_t RIP, FEXCore::IR::IntrusiveIRList **ir);
-    // void SetIRForRIP(uint64_t RIP, FEXCore::IR::IntrusiveIRList *const ir);
-    FEXCore::Core::ThreadState *GetThreadState();
-    void LoadEntryList();
+    std::tuple<FEXCore::IR::IRListView *, FEXCore::IR::RegisterAllocationData *, uint64_t, uint64_t, uint64_t, uint64_t> GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
 
-    std::tuple<FEXCore::IR::IRListView<true> *, FEXCore::IR::RegisterAllocationData *, uint64_t, uint64_t> GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
-
-    std::tuple<void *, FEXCore::IR::IRListView<true> *, FEXCore::Core::DebugData *, FEXCore::IR::RegisterAllocationData *, bool> CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
-    uintptr_t CompileBlock(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
+    std::tuple<void *, FEXCore::IR::IRListView *, FEXCore::Core::DebugData *, FEXCore::IR::RegisterAllocationData *, bool, uint64_t, uint64_t> CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
+    uintptr_t CompileBlock(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);
+    
+    // same as CompileBlock, but aborts on failure
+    void CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);
 
+    bool LoadAOTIRCache(int streamfd);
+    void FinalizeAOTIRCache();
+    void WriteFilesWithCode(std::function<void(const std::string& fileid, const std::string& filename)> Writer);
+    
     // Used for thread creation from syscalls
     void InitializeCompiler(FEXCore::Core::InternalThreadState* State, bool CompileThread);
     FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID);
@@ -155,38 +237,48 @@ namespace FEXCore::Context {
     void CopyMemoryMapping(FEXCore::Core::InternalThreadState *ParentThread, FEXCore::Core::InternalThreadState *ChildThread);
     void RunThread(FEXCore::Core::InternalThreadState *Thread);
 
+    void DestroyThread(FEXCore::Core::InternalThreadState *Thread);
+    void CleanupAfterFork(FEXCore::Core::InternalThreadState *ExceptForThread);
+
     std::vector<FEXCore::Core::InternalThreadState*> *const GetThreads() { return &Threads; }
 
+    void AddNamedRegion(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const std::string &filename);
+    void RemoveNamedRegion(uintptr_t Base, uintptr_t Size);
+
 #if ENABLE_JITSYMBOLS
     FEXCore::JITSymbols Symbols;
 #endif
 
+    // Public for threading
+    void ExecutionThread(FEXCore::Core::InternalThreadState *Thread);
+
   protected:
     void ClearCodeCache(FEXCore::Core::InternalThreadState *Thread, bool AlsoClearIRCache);
 
   private:
     void WaitForIdleWithTimeout();
 
-    void ExecutionThread(FEXCore::Core::InternalThreadState *Thread);
     void NotifyPause();
 
-    void AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr);
-
+    void AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr, uint64_t Start, uint64_t Length);
     FEXCore::CodeLoader *LocalLoader{};
 
     // Entry Cache
-    bool GetFilenameHash(std::string const &Filename, std::string &Hash);
-    void AddThreadRIPsToEntryList(FEXCore::Core::InternalThreadState *Thread);
-    void SaveEntryList();
-    std::set<uint64_t> EntryList;
-    std::vector<uint64_t> InitLocations;
     uint64_t StartingRIP;
     std::mutex ExitMutex;
     std::unique_ptr<GdbServer> DebugServer;
 
+    std::shared_mutex AOTIRCacheLock;
+    std::shared_mutex AOTIRCaptureCacheWriteoutLock;
+    std::atomic<bool> AOTIRCaptureCacheWriteoutFlusing;
+
+    std::queue<std::function<void()>> AOTIRCaptureCacheWriteoutQueue;
+    void AOTIRCaptureCacheWriteoutQueue_Flush();
+    void AOTIRCaptureCacheWriteoutQueue_Append(const std::function<void()> &fn);
+
     bool StartPaused = false;
-    FEXCore::Config::Value<std::string> AppFilename{FEXCore::Config::CONFIG_APP_FILENAME, ""};
+    FEX_CONFIG_OPT(AppFilename, APP_FILENAME);
   };
 
-  uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::InternalThreadState *Thread, FEXCore::HLE::SyscallArguments *Args);
+  uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::CpuStateFrame *Frame, FEXCore::HLE::SyscallArguments *Args);
 }

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64.h

@@ -9,6 +9,28 @@ namespace FEXCore::ArchHelpers::Arm64 {
   constexpr uint32_t CASAL_MASK = 0x3F'E0'FC'00;
   constexpr uint32_t CASAL_INST = 0x08'E0'FC'00;
 
-  bool HandleCASPAL(void *_mcontext, void *_info, uint32_t Instr);
-  bool HandleCASAL(void *_mcontext, void *_info, uint32_t Instr);
+  constexpr uint32_t ATOMIC_MEM_MASK = 0x3B200C00;
+  constexpr uint32_t ATOMIC_MEM_INST = 0x38200000;
+
+  constexpr uint32_t LDAXP_MASK = 0xBF'FF'80'00;
+  constexpr uint32_t LDAXP_INST = 0x88'7F'80'00;
+
+  constexpr uint32_t STLXP_MASK = 0xBF'E0'80'00;
+  constexpr uint32_t STLXP_INST = 0x88'20'80'00;
+
+  // Load ops are 4 bits
+  // Acquire and release bits are independent on the instruction
+  constexpr uint32_t ATOMIC_ADD_OP  = 0b0000;
+  constexpr uint32_t ATOMIC_CLR_OP  = 0b0001;
+  constexpr uint32_t ATOMIC_EOR_OP  = 0b0010;
+  constexpr uint32_t ATOMIC_SET_OP  = 0b0011;
+  constexpr uint32_t ATOMIC_SMAX_OP = 0b0100;
+  constexpr uint32_t ATOMIC_SMIN_OP = 0b0101;
+  constexpr uint32_t ATOMIC_UMAX_OP = 0b0110;
+  constexpr uint32_t ATOMIC_UMIN_OP = 0b0111;
+  constexpr uint32_t ATOMIC_SWAP_OP = 0b1000;
+
+  bool HandleCASPAL(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleCASAL(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr);
 }

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp

@@ -0,0 +1,231 @@
+#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Core/CoreState.h>
+
+#include "aarch64/cpu-aarch64.h"
+
+namespace FEXCore::CPU {
+#define STATE x28
+
+// We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one.
+Arm64Emitter::Arm64Emitter(size_t size) : vixl::aarch64::Assembler(size, vixl::aarch64::PositionDependentCode) {
+  CPU.SetUp();
+
+  auto Features = vixl::CPUFeatures::InferFromOS();
+  SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
+  // RCPC is bugged on Snapdragon 865
+  // Causes glibc cond16 test to immediately throw assert
+  // __pthread_mutex_cond_lock: Assertion `mutex->__data.__owner == 0'
+  SupportsRCPC = false; //Features.Has(vixl::CPUFeatures::Feature::kRCpc);
+
+  if (SupportsAtomics) {
+    // Hypervisor can hide this on the c630?
+    Features.Combine(vixl::CPUFeatures::Feature::kLORegions);
+  }
+
+  SetCPUFeatures(Features);
+
+  if (!SupportsAtomics) {
+    WARN_ONCE("Host CPU doesn't support atomics. Expect bad performance");
+  }
+
+#ifdef _M_ARM_64
+  // We need to get the CPU's cache line size
+  // We expect sane targets that have correct cacheline sizes across clusters
+  uint64_t CTR;
+  __asm volatile ("mrs %[ctr], ctr_el0"
+    : [ctr] "=r"(CTR));
+
+  DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
+  ICacheLineSize = 4 << (CTR & 0xF);
+#endif
+}
+
+void Arm64Emitter::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant) {
+  bool Is64Bit = Reg.IsX();
+  int Segments = Is64Bit ? 4 : 2;
+
+  if (Is64Bit && ((~Constant)>> 16) == 0) {
+    movn(Reg, (~Constant) & 0xFFFF);
+    return;
+  }
+
+  movz(Reg, (Constant) & 0xFFFF, 0);
+  for (int i = 1; i < Segments; ++i) {
+    uint16_t Part = (Constant >> (i * 16)) & 0xFFFF;
+    if (Part) {
+      movk(Reg, Part, i * 16);
+    }
+  }
+}
+
+void Arm64Emitter::PushCalleeSavedRegisters() {
+  // We need to save pairs of registers
+  // We save r19-r30
+  MemOperand PairOffset(sp, -16, PreIndex);
+  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
+    {x19, x20},
+    {x21, x22},
+    {x23, x24},
+    {x25, x26},
+    {x27, x28},
+    {x29, x30},
+  }};
+
+  for (auto &RegPair : CalleeSaved) {
+    stp(RegPair.first, RegPair.second, PairOffset);
+  }
+
+  // Additionally we need to store the lower 64bits of v8-v15
+  // Here's a fun thing, we can use two ST4 instructions to store everything
+  // We just need a single sub to sp before that
+  const std::array<
+    std::tuple<vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister>, 2> FPRs = {{
+    {v8, v9, v10, v11},
+    {v12, v13, v14, v15},
+  }};
+
+  uint32_t VectorSaveSize = sizeof(uint64_t) * 8;
+  sub(sp, sp, VectorSaveSize);
+  // SP supporting move
+  // We just saved x19 so it is safe
+  add(x19, sp, 0);
+
+  MemOperand QuadOffset(x19, 32, PostIndex);
+  for (auto &RegQuad : FPRs) {
+    st4(std::get<0>(RegQuad).D(),
+        std::get<1>(RegQuad).D(),
+        std::get<2>(RegQuad).D(),
+        std::get<3>(RegQuad).D(),
+        0,
+        QuadOffset);
+  }
+}
+
+void Arm64Emitter::PopCalleeSavedRegisters() {
+  const std::array<
+    std::tuple<vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister>, 2> FPRs = {{
+    {v12, v13, v14, v15},
+    {v8, v9, v10, v11},
+  }};
+
+  MemOperand QuadOffset(sp, 32, PostIndex);
+  for (auto &RegQuad : FPRs) {
+    ld4(std::get<0>(RegQuad).D(),
+        std::get<1>(RegQuad).D(),
+        std::get<2>(RegQuad).D(),
+        std::get<3>(RegQuad).D(),
+        0,
+        QuadOffset);
+  }
+
+  MemOperand PairOffset(sp, 16, PostIndex);
+  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
+    {x29, x30},
+    {x27, x28},
+    {x25, x26},
+    {x23, x24},
+    {x21, x22},
+    {x19, x20},
+  }};
+
+  for (auto &RegPair : CalleeSaved) {
+    ldp(RegPair.first, RegPair.second, PairOffset);
+  }
+}
+
+
+void Arm64Emitter::SpillStaticRegs() {
+  for (size_t i = 0; i < SRA64.size(); i+=2) {
+      stp(SRA64[i], SRA64[i+1], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+  }
+
+  for (size_t i = 0; i < SRAFPR.size(); i+=2) {
+    stp(SRAFPR[i].Q(), SRAFPR[i+1].Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+  }
+}
+
+void Arm64Emitter::FillStaticRegs() {
+  for (size_t i = 0; i < SRA64.size(); i+=2) {
+    ldp(SRA64[i], SRA64[i+1], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+  }
+
+  for (size_t i = 0; i < SRAFPR.size(); i+=2) {
+    ldp(SRAFPR[i].Q(), SRAFPR[i+1].Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+  }
+}
+
+void Arm64Emitter::PushDynamicRegsAndLR() {
+  uint64_t SPOffset = AlignUp((RA64.size() + 1) * 8 + RAFPR.size() * 16, 16);
+
+  sub(sp, sp, SPOffset);
+  int i = 0;
+
+  for (auto RA : RAFPR)
+  {
+    str(RA.Q(), MemOperand(sp, i * 8));
+    i+=2;
+  }
+
+#if 0 // All GPRs should be caller saved
+  for (auto RA : RA64)
+  {
+    str(RA, MemOperand(sp, i * 8));
+    i++;
+  }
+#endif
+
+  str(lr, MemOperand(sp, i * 8));
+}
+
+void Arm64Emitter::PopDynamicRegsAndLR() {
+  uint64_t SPOffset = AlignUp((RA64.size() + 1) * 8 + RAFPR.size() * 16, 16);
+  int i = 0;
+
+  for (auto RA : RAFPR)
+  {
+    ldr(RA.Q(), MemOperand(sp, i * 8));
+    i+=2;
+  }
+
+#if 0 // All GPRs should be caller saved
+  for (auto RA : RA64)
+  {
+    ldr(RA, MemOperand(sp, i * 8));
+    i++;
+  }
+#endif
+
+  ldr(lr, MemOperand(sp, i * 8));
+
+  add(sp, sp, SPOffset);
+}
+
+void Arm64Emitter::ResetStack() {
+  if (SpillSlots == 0)
+    return;
+
+  if (IsImmAddSub(SpillSlots * 16)) {
+    add(sp, sp, SpillSlots * 16);
+  } else {
+   // Too big to fit in a 12bit immediate
+   LoadConstant(x0, SpillSlots * 16);
+   add(sp, sp, x0);
+  }
+}
+
+void Arm64Emitter::Align16B() {
+  uint64_t CurrentOffset = GetBuffer()->GetOffsetAddress<uint64_t>(GetCursorOffset());
+  for (uint64_t i = (16 - (CurrentOffset & 0xF)); i != 0; i -= 4) {
+      nop();
+  }
+}
+
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h

@@ -0,0 +1,77 @@
+#pragma once
+
+#include "aarch64/assembler-aarch64.h"
+#include "aarch64/cpu-aarch64.h"
+
+namespace FEXCore::CPU {
+using namespace vixl;
+using namespace vixl::aarch64;
+
+// All but x29 are caller saved
+const std::array<aarch64::Register, 16> SRA64 = {
+  x4, x5, x6, x7, x8, x9, x10, x11,
+  x12, x18, x17, x16, x15, x14, x13, x29
+};
+
+// All are callee saved
+const std::array<aarch64::Register, 9> RA64 = {
+  x20, x21, x22, x23, x24, x25, x26, x27,
+  x19
+};
+
+const std::array<std::pair<aarch64::Register, aarch64::Register>, 4>  RA64Pair = {{
+  {x20, x21},
+  {x22, x23},
+  {x24, x25},
+  {x26, x27},
+}};
+
+const std::array<std::pair<aarch64::Register, aarch64::Register>, 4> RA32Pair = {{
+  {w20, w21},
+  {w22, w23},
+  {w24, w25},
+  {w26, w27},
+}};
+
+// All are caller saved
+const std::array<aarch64::VRegister, 16> SRAFPR = {
+  v16, v17, v18, v19, v20, v21, v22, v23,
+  v24, v25, v26, v27, v28, v29, v30, v31
+};
+
+//  v8..v15 = (lower 64bits) Callee saved
+const std::array<aarch64::VRegister, 12> RAFPR = {
+/*v0,  v1,  v2,  v3,*/v4,  v5,  v6,  v7,  // v0 ~ v3 are used as temps
+  v8,  v9,  v10, v11, v12, v13, v14, v15
+};
+
+// This class contains common emitter utility functions that can
+// be used by both Arm64 JIT and ARM64 Dispatcher
+class Arm64Emitter : public vixl::aarch64::Assembler {
+protected:
+  Arm64Emitter(size_t size);
+
+  vixl::aarch64::CPU CPU;
+  bool SupportsAtomics{};
+  bool SupportsRCPC{};
+
+  void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant);
+  void SpillStaticRegs();
+  void FillStaticRegs();
+
+  void PushDynamicRegsAndLR();
+  void PopDynamicRegsAndLR();
+
+  void PushCalleeSavedRegisters();
+  void PopCalleeSavedRegisters();
+
+  void ResetStack();
+  void Align16B();
+
+  uint32_t SpillSlots{};
+
+  uint32_t DCacheLineSize{};
+  uint32_t ICacheLineSize{};
+};
+
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64_stubs.cpp

@@ -0,0 +1,26 @@
+#include "Interface/Core/ArchHelpers/Arm64.h"
+
+#include <FEXCore/Utils/LogManager.h>
+
+namespace FEXCore::ArchHelpers::Arm64 {
+
+#ifndef _M_ARM_64
+// These are stub implementations that exist only to allow instantiating the arm64 jit
+// on non arm platforms.
+
+// Obvously such a configuration can't do the actual arm64-specific stuff
+
+bool HandleCASPAL(void *_ucontext, void *_info, uint32_t Instr) {
+    ERROR_AND_DIE("HandleCASPAL Not Implemented");
+}
+
+bool HandleCASAL(void *_ucontext, void *_info, uint32_t Instr) {
+    ERROR_AND_DIE("HandleCASAL Not Implemented");
+}
+
+bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr) {
+    ERROR_AND_DIE("HandleAtomicMemOp Not Implemented");
+}
+#endif
+
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/MContext.h

@@ -0,0 +1,212 @@
+#pragma once
+
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/UContext.h>
+
+#include <signal.h>
+#include <string.h>
+#include <ucontext.h>
+#include <stdint.h>
+#include <type_traits>
+
+
+namespace FEXCore::ArchHelpers::Context {
+
+struct X86ContextBackup {
+  // Host State
+  // RIP and RSP is stored in GPRs here
+  uint64_t GPRs[23];
+  FEXCore::x86_64::_libc_fpstate FPRState;
+
+  // Guest state
+  int Signal;
+  FEXCore::Core::CPUState GuestState;
+
+  static constexpr int RedZoneSize = 128;
+};
+
+struct ArmContextBackup {
+  // Host State
+  uint64_t GPRs[31];
+  uint64_t PrevSP;
+  uint64_t PrevPC;
+  uint64_t PState;
+  uint32_t FPSR;
+  uint32_t FPCR;
+  __uint128_t FPRs[32];
+
+  // Guest state
+  int Signal;
+  FEXCore::Core::CPUState GuestState;
+
+  // Arm64 doesn't have a red zone
+  static constexpr int RedZoneSize = 0;
+};
+
+static inline mcontext_t* GetMContext(void* ucontext) {
+  ucontext_t* _context = (ucontext_t*)ucontext;
+  return &_context->uc_mcontext;
+}
+
+
+#ifdef _M_ARM_64
+
+static inline uint64_t GetSp(void* ucontext) {
+  return GetMContext(ucontext)->sp;
+}
+
+static inline uint64_t GetPc(void* ucontext) {
+  return GetMContext(ucontext)->pc;
+}
+
+static inline void SetSp(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->sp = val;
+}
+
+static inline void SetPc(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->pc = val;
+}
+
+static inline uint64_t GetState(void* ucontext) {
+  return GetMContext(ucontext)->regs[28];
+}
+
+static inline void SetState(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->regs[28] = val;
+}
+
+static inline uint64_t GetArmReg(void* ucontext, uint32_t id) {
+  return GetMContext(ucontext)->regs[id];
+}
+
+static inline void SetArmReg(void* ucontext, uint32_t id, uint64_t val) {
+  GetMContext(ucontext)->regs[id] = val;
+}
+
+constexpr uint32_t FPR_MAGIC = 0x46508001U;
+
+struct HostCTXHeader {
+  uint32_t Magic;
+  uint32_t Size;
+};
+
+struct HostFPRState {
+  HostCTXHeader Head;
+  uint32_t FPSR;
+  uint32_t FPCR;
+  __uint128_t FPRs[32];
+};
+
+using ContextBackup = ArmContextBackup;
+template <typename T>
+static inline void BackupContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, ArmContextBackup>::value) {
+    auto _mcontext = GetMContext(ucontext);
+
+    memcpy(&Backup->GPRs[0], &_mcontext->regs[0], 31 * sizeof(uint64_t));
+    Backup->PrevSP = ArchHelpers::Context::GetSp(ucontext);
+    Backup->PrevPC = ArchHelpers::Context::GetPc(ucontext);
+    Backup->PState = _mcontext->pstate;
+
+    // Host FPR state starts at _mcontext->reserved[0];
+    HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
+    LOGMAN_THROW_A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
+    Backup->FPSR = HostState->FPSR;
+    Backup->FPCR = HostState->FPCR;
+    memcpy(&Backup->FPRs[0], &HostState->FPRs[0], 32 * sizeof(__uint128_t));
+  } else {
+      ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+  }
+}
+
+template <typename T>
+static inline void RestoreContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, ArmContextBackup>::value) {
+   auto _mcontext = GetMContext(ucontext);
+
+    HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
+    LOGMAN_THROW_A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
+    memcpy(&HostState->FPRs[0], &Backup->FPRs[0], 32 * sizeof(__uint128_t));
+    HostState->FPCR = Backup->FPCR;
+    HostState->FPSR = Backup->FPSR;
+
+    // Restore GPRs and other state
+    _mcontext->pstate = Backup->PState;
+    ArchHelpers::Context::SetPc(ucontext, Backup->PrevPC);
+    ArchHelpers::Context::SetSp(ucontext, Backup->PrevSP);
+    memcpy(&_mcontext->regs[0], &Backup->GPRs[0], 31 * sizeof(uint64_t));
+  } else {
+      ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+  }
+}
+
+#endif
+
+#ifdef _M_X86_64
+
+static inline uint64_t GetSp(void* ucontext) {
+  return GetMContext(ucontext)->gregs[REG_RSP];
+}
+
+static inline uint64_t GetPc(void* ucontext) {
+  return GetMContext(ucontext)->gregs[REG_RIP];
+  }
+
+static inline void SetSp(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->gregs[REG_RSP] = val;
+}
+
+static inline void SetPc(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->gregs[REG_RIP] = val;
+}
+
+static inline uint64_t GetState(void* ucontext) {
+  return GetMContext(ucontext)->gregs[REG_R14];
+}
+
+static inline void SetState(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->gregs[REG_R14] = val;
+}
+
+static inline uint64_t GetArmReg(void* ucontext, uint32_t id) {
+  ERROR_AND_DIE("Not impelented for x86 host");
+}
+
+static inline void SetArmReg(void* ucontext, uint32_t id, uint64_t val) {
+  ERROR_AND_DIE("Not impelented for x86 host");
+}
+
+using ContextBackup = X86ContextBackup;
+template <typename T>
+static inline void BackupContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, X86ContextBackup>::value) {
+    auto _mcontext = GetMContext(ucontext);
+
+    // Copy the GPRs
+    memcpy(&Backup->GPRs[0], &_mcontext->gregs[0], sizeof(X86ContextBackup::GPRs));
+    // Copy the FPRState
+    memcpy(&Backup->FPRState, _mcontext->fpregs, sizeof(X86ContextBackup::FPRState));
+    // XXX: Save 256bit and 512bit AVX register state
+  } else {
+    ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+  }
+}
+
+template <typename T>
+static inline void RestoreContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, X86ContextBackup>::value) {
+    auto _mcontext = GetMContext(ucontext);
+
+    // Copy the GPRs
+    memcpy(&_mcontext->gregs[0], &Backup->GPRs[0], sizeof(X86ContextBackup::GPRs));
+    // Copy the FPRState
+    memcpy(_mcontext->fpregs, &Backup->FPRState, sizeof(X86ContextBackup::FPRState));
+  } else {
+    ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+  }
+}
+
+#endif
+
+} // namespace FEXCore::ArchHelpers::Context

External/FEXCore/Source/Interface/Core/CPUID.cpp

@@ -1,11 +1,42 @@
+/*
+$info$
+tags: opcodes|cpuid
+desc: Handles presented capability bits for guest cpu
+$end_info$
+*/
+
 #include "Interface/Context/Context.h"
 #include "Interface/Core/CPUID.h"
 #include "git_version.h"
 
 #include <cstring>
+#ifdef _M_X86_64
+#include <cpuid.h>
+#endif
 
 namespace FEXCore {
 //#define CPUID_AMD
+#ifdef _M_ARM_64
+static uint32_t GetCycleCounterFrequency() {
+  uint64_t Result{};
+  __asm("mrs %[Res], CNTFRQ_EL0"
+      : [Res] "=r" (Result));
+  return Result;
+}
+#else
+static uint32_t GetCycleCounterFrequency() {
+  uint32_t eax, ebx, ecx, edx;
+  __cpuid(0, eax, ebx, ecx, edx);
+  if (eax >= 0x15) {
+    __cpuid(0x15, eax, ebx, ecx, edx);
+
+    if (eax && ebx && ecx) {
+      return ecx * ebx / eax;
+    }
+  }
+  return 0;
+}
+#endif
 
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0h() {
   FEXCore::CPUID::FunctionResults Res{};
@@ -59,7 +90,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h() {
     (0 << 16) | // Reserved
     (0 << 17) | // Process-context identifiers
     (1 << 18) | // Prefetching from memory mapped device
-    (0 << 19) | // SSE4.1
+    (1 << 19) | // SSE4.1
     (0 << 20) | // SSE4.2
     (0 << 21) | // X2APIC
     (1 << 22) | // MOVBE
@@ -93,7 +124,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h() {
     (1 << 16) | // Page Attribute Table
     (1 << 17) | // 36bit page size extension
     (0 << 18) | // Processor serial number
-    (0 << 19) | // CLFLUSH
+    (1 << 19) | // CLFLUSH
     (0 << 20) | // Reserved
     (0 << 21) | // Debug store
     (0 << 22) | // Thermal monitor and software controled clock
@@ -109,6 +140,31 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h() {
   return Res;
 }
 
+// 2: Cache and TLB information
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_02h() {
+  FEXCore::CPUID::FunctionResults Res{};
+
+  // returns default values from i7 model 1Ah
+  Res.eax = 0x1 | // Number of iterations needed for all descriptors
+    (0x5A << 8) |
+    (0x03 << 16) |
+    (0x55 << 24);
+
+  Res.ebx = 0xE4 |
+    (0xB2 << 8)  |
+    (0xF0 << 16) |
+    (0 << 24);
+
+  Res.ecx = 0; // null descriptors
+
+  Res.edx = 0x2C |
+    (0x21 << 8)  |
+    (0xCA << 16) |
+    (0x09 << 24);
+
+  return Res;
+}
+
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_06h() {
   FEXCore::CPUID::FunctionResults Res{};
   Res.eax = (1 << 2); // Always running APIC
@@ -226,6 +282,18 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h() {
   return Res;
 }
 
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_15h() {
+  FEXCore::CPUID::FunctionResults Res{};
+  // TSC frequency = ECX * EBX / EAX
+  uint32_t FrequencyHz = GetCycleCounterFrequency();
+  if (FrequencyHz) {
+    Res.eax = 1;
+    Res.ebx = 1;
+    Res.ecx = FrequencyHz;
+  }
+  return Res;
+}
+
 // Highest extended function implemented
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0000h() {
   FEXCore::CPUID::FunctionResults Res{};
@@ -350,10 +418,120 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0004h() {
   return Res;
 }
 
+// L1 Cache and TLB identifiers
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0005h() {
+  FEXCore::CPUID::FunctionResults Res{};
+
+  // L1 TLB Information for 2MB and 4MB pages
+  Res.eax =
+    (64 << 0)  | // Number of TLB instruction entries
+    (255 << 8) | // instruction TLB associativity type (full)
+    (64 << 16) | // Number of TLB data entries
+    (255 << 24); // data TLB associativity type (full)
+
+  // L1 TLB Information for 4KB pages
+  Res.ebx =
+    (64 << 0)  | // Number of TLB instruction entries
+    (255 << 8) | // instruction TLB associativity type (full)
+    (64 << 16) | // Number of TLB data entries
+    (255 << 24); // data TLB associativity type (full)
+
+  // L1 data cache identifiers
+  Res.ecx =
+    (64 << 0) | // L1 data cache size line in bytes
+    (1 << 8)  | // L1 data cachelines per tag
+    (8 << 16) | // L1 data cache associativity
+    (32 << 24); // L1 data cache size in KB
+
+  // L1 instruction cache identifiers
+  Res.edx =
+    (64 << 0) | // L1 instruction cache line size in bytes
+    (1 << 8)  | // L1 instruction cachelines per tag
+    (4 << 16) | // L1 instruction cache associativity
+    (64 << 24); // L1 instruction cache size in KB
+
+  return Res;
+}
+
+// L2 Cache identifiers
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0006h() {
+  FEXCore::CPUID::FunctionResults Res{};
+
+  // L2 TLB Information for 2MB and 4MB pages
+  Res.eax =
+    (1024 << 0)  | // Number of TLB instruction entries
+    (6 << 12)    | // instruction TLB associativity type
+    (1536 << 16) | // Number of TLB data entries
+    (3 << 28);     // data TLB associativity type
+
+  // L2 TLB Information for 4KB pages
+  Res.ebx =
+    (1024 << 0)  | // Number of TLB instruction entries
+    (6 << 12)    | // instruction TLB associativity type
+    (1536 << 16) | // Number of TLB data entries
+    (5 << 28);     // data TLB associativity type
+
+  // L2 cache identifiers
+  Res.ecx =
+    (64 << 0) |  // cacheline size
+    (1 << 8)  |  // cachelines per tag
+    (6 << 12) |  // cache associativity
+    (512 << 16); // L2 cache size in KB
+
+  // L3 cache identifiers
+  Res.edx =
+    (64 << 0) | // cacheline size
+    (1 << 8)  | // cachelines per tag
+    (6 << 12) | // cache associativity
+    (16 << 18); // L2 cache size in KB
+  return Res;
+}
+
 // Advanced power management
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0007h() {
   FEXCore::CPUID::FunctionResults Res{};
   Res.eax = (1 << 2); // APIC timer not affected by p-state
+  Res.edx =
+    (1 << 8); // Invariant TSC
+  return Res;
+}
+
+// Virtual and physical address sizes
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0008h() {
+  FEXCore::CPUID::FunctionResults Res{};
+  Res.eax =
+    (48 << 0) | // PhysAddrSize = 48-bit
+    (48 << 8) | // LinAddrSize = 48-bit
+    (0 << 16); // GuestPhysAddrSize == PhysAddrSize
+
+  Res.ebx =
+    (0 << 2) | // XSaveErPtr: Saving and restoring error pointers
+    (0 << 1) | // IRPerf: Instructions retired count support
+    (0 << 0);  // CLZERO support
+
+  uint32_t CoreCount = Cores() - 1;
+  Res.ecx =
+    (0 << 16) |       // PerfTscSize: Performance timestamp count size
+    (0 << 12) |       // ApicIdSize: Number of bits in ApicID
+    (CoreCount << 0); // Count count subtract one
+
+  return Res;
+}
+
+// TLB 1GB page identifiers
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0019h() {
+  FEXCore::CPUID::FunctionResults Res{};
+  Res.eax =
+    (0xF << 28) | // L1 DTLB associativity for 1GB pages
+    (64 << 16) |  // L1 DTLB entry count for 1GB pages
+    (0xF << 12) | // L1 ITLB associativity for 1GB pages
+    (64 << 0);    // L1 ITLB entry count for 1GB pages
+
+  Res.ebx =
+    (0 << 28) | // L2 DTLB associativity for 1GB pages
+    (0 << 16) | // L2 DTLB entry count for 1GB pages
+    (0 << 12) | // L2 ITLB associativity for 1GB pages
+    (0 << 0);   // L2 ITLB entry count for 1GB pages
   return Res;
 }
 
@@ -366,7 +544,7 @@ void CPUIDEmu::Init(FEXCore::Context::Context *ctx) {
   CTX = ctx;
   RegisterFunction(0, std::bind(&CPUIDEmu::Function_0h, this));
   RegisterFunction(1, std::bind(&CPUIDEmu::Function_01h, this));
-  // 2: Cache and TLB information
+  RegisterFunction(2, std::bind(&CPUIDEmu::Function_02h, this));
   // 3: Serial Number(previously), now reserved
   // 4: Deterministic cache parameters for each level
   // 5: Monitor/mwait
@@ -383,7 +561,11 @@ void CPUIDEmu::Init(FEXCore::Context::Context *ctx) {
   // 0x12: Intel SGX capability enumeration
   // 0x13: Reserved
   // 0x14: Intel Processor trace
-  // 0x15: Timestamp counter information
+#ifndef CPUID_AMD
+  // Timestamp counter information
+  // Doesn't exist on AMD hardware
+  RegisterFunction(0x15, std::bind(&CPUIDEmu::Function_15h, this));
+#endif
   // 0x16: Processor frequency information
   // 0x17: SoC vendor attribute enumeration
 
@@ -398,12 +580,23 @@ void CPUIDEmu::Init(FEXCore::Context::Context *ctx) {
   // Processor brand string continued
   RegisterFunction(0x8000'0004, std::bind(&CPUIDEmu::Function_8000_0004h, this));
   // 0x8000'0005: L1 Cache and TLB identifiers
+#ifdef CPUID_AMD
+  RegisterFunction(0x8000'0005, std::bind(&CPUIDEmu::Function_8000_0005h, this));
+#else
+  // This is full reserved on Intel platforms
+  RegisterFunction(0x8000'0005, std::bind(&CPUIDEmu::Function_Reserved, this));
+#endif
   // 0x8000'0006: L2 Cache identifiers
+  RegisterFunction(0x8000'0006, std::bind(&CPUIDEmu::Function_8000_0006h, this));
   // Advanced power management information
   RegisterFunction(0x8000'0007, std::bind(&CPUIDEmu::Function_8000_0007h, this));
-  // 0x8000'0008: Virtual and physical address sizes
+  // Virtual and physical address sizes
+  RegisterFunction(0x8000'0008, std::bind(&CPUIDEmu::Function_8000_0008h, this));
+
   // 0x8000'000A: SVM Revision
-  // 0x8000'0019: TLB 1GB page identifiers
+  // TLB 1GB page identifiers
+  RegisterFunction(0x8000'0019, std::bind(&CPUIDEmu::Function_8000_0019h, this));
+
   // 0x8000'001A: Performance optimization identifiers
   // 0x8000'001B: Instruction based sampling identifiers
   // 0x8000'001C: Lightweight profiling capabilities

External/FEXCore/Source/Interface/Core/CPUID.h

@@ -3,6 +3,8 @@
 #include <unordered_map>
 
 #include <FEXCore/Core/CPUID.h>
+#include <FEXCore/Config/Config.h>
+#include <FEXCore/Utils/LogManager.h>
 
 namespace FEXCore {
 namespace Context {
@@ -22,16 +24,21 @@ private:
 public:
   void Init(FEXCore::Context::Context *ctx);
 
-  FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function) {
+  FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function, [[maybe_unused]] uint32_t Leaf) {
     auto Handler = FunctionHandlers.find(Function);
 
-    if (Handler == FunctionHandlers.end())
+    if (Handler == FunctionHandlers.end()) {
+      #ifndef NDEBUG
+        LogMan::Msg::E("Unhandled CPU ID function, 0x%x", Function);
+      #endif
       return Function_Reserved();
+    }
 
     return Handler->second();
   }
 private:
   FEXCore::Context::Context *CTX;
+  FEX_CONFIG_OPT(Cores, THREADS);
 
   using FunctionHandler = std::function<FEXCore::CPUID::FunctionResults()>;
   void RegisterFunction(uint32_t Function, FunctionHandler Handler) {
@@ -43,15 +50,21 @@ private:
   // Functions
   FEXCore::CPUID::FunctionResults Function_0h();
   FEXCore::CPUID::FunctionResults Function_01h();
+  FEXCore::CPUID::FunctionResults Function_02h();
   FEXCore::CPUID::FunctionResults Function_06h();
   FEXCore::CPUID::FunctionResults Function_07h();
+  FEXCore::CPUID::FunctionResults Function_15h();
   FEXCore::CPUID::FunctionResults Function_8000_0000h();
   FEXCore::CPUID::FunctionResults Function_8000_0001h();
   FEXCore::CPUID::FunctionResults Function_8000_0002h();
   FEXCore::CPUID::FunctionResults Function_8000_0003h();
   FEXCore::CPUID::FunctionResults Function_8000_0004h();
+  FEXCore::CPUID::FunctionResults Function_8000_0005h();
+  FEXCore::CPUID::FunctionResults Function_8000_0006h();
   FEXCore::CPUID::FunctionResults Function_8000_0007h();
-
+  FEXCore::CPUID::FunctionResults Function_8000_0008h();
+  FEXCore::CPUID::FunctionResults Function_8000_0009h();
+  FEXCore::CPUID::FunctionResults Function_8000_0019h();
   FEXCore::CPUID::FunctionResults Function_Reserved();
 };
 }

External/FEXCore/Source/Interface/Core/CompileService.cpp

@@ -5,6 +5,12 @@
 #include "Interface/Core/OpcodeDispatcher.h"
 
 namespace FEXCore {
+  static void* ThreadHandler(void *Arg) {
+    FEXCore::CompileService *This = reinterpret_cast<FEXCore::CompileService*>(Arg);
+    This->ExecutionThread();
+    return nullptr;
+  }
+
   CompileService::CompileService(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
     : CTX {ctx}
     , ParentThread {Thread} {
@@ -16,9 +22,7 @@ namespace FEXCore {
     CTX->InitializeCompiler(CompileThreadData.get(), true);
     CompileThreadData->CPUBackend->CopyNecessaryDataForCompileThread(ParentThread->CPUBackend.get());
 
-    WorkerThread = std::thread([this]() {
-      ExecutionThread();
-    });
+    WorkerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
   }
 
   void CompileService::Initialize() {
@@ -30,7 +34,7 @@ namespace FEXCore {
     ShuttingDown = true;
     // Kick the working thread
     StartWork.NotifyAll();
-    WorkerThread.join();
+    WorkerThread->join(nullptr);
   }
 
   void CompileService::ClearCache(FEXCore::Core::InternalThreadState *Thread) {
@@ -57,9 +61,7 @@ namespace FEXCore {
         }
       }
 
-      LogMan::Throw::A(CompileThreadData->IRLists.size() == 0, "Compile service must never have IRLists");
-      LogMan::Throw::A(CompileThreadData->RALists.size() == 0, "Compile service must never have RALists");
-      LogMan::Throw::A(CompileThreadData->DebugData.size() == 0, "Compile service must never have DebugData");
+      LOGMAN_THROW_A(CompileThreadData->LocalIRCache.size() == 0, "Compile service must never have LocalIRCache");
 
       CompileMutex.unlock();
     }
@@ -94,7 +96,7 @@ namespace FEXCore {
 
     // Set our thread name so we can see its relation
     char ThreadName[16]{};
-    snprintf(ThreadName, 16, "%ld-CS", ParentThread->State.ThreadManager.TID.load());
+    snprintf(ThreadName, 16, "%ld-CS", ParentThread->ThreadManager.TID.load());
     pthread_setname_np(pthread_self(), ThreadName);
 
     while (true) {
@@ -122,15 +124,15 @@ namespace FEXCore {
         // If we had a work item then work on it
         if (Item) {
           // Make sure it's not in lookup cache by accident
-          LogMan::Throw::A(CompileThreadData->LookupCache->FindBlock(Item->RIP) == 0, "Compile Service must never have entries in the LookupCache");
-          
+          LOGMAN_THROW_A(CompileThreadData->LookupCache->FindBlock(Item->RIP) == 0, "Compile Service must never have entries in the LookupCache");
+
           // Code isn't in cache, compile now
           // Set our thread state's RIP
-          CompileThreadData->State.State.rip = Item->RIP;
+          CompileThreadData->CurrentFrame->State.rip = Item->RIP;
 
-          auto [CodePtr, IRList, DebugData, RAData, Generated] = CTX->CompileCode(CompileThreadData.get(), Item->RIP);
+          auto [CodePtr, IRList, DebugData, RAData, Generated, StartAddr, Length] = CTX->CompileCode(CompileThreadData.get(), Item->RIP);
 
-          LogMan::Throw::A(Generated == true, "Compile Service doesn't have IR Cache");
+          LOGMAN_THROW_A(Generated == true, "Compile Service doesn't have IR Cache");
 
           if (!CodePtr) {
             // XXX: We currently have the expectation that compile service code will be significantly smaller than regular thread's code
@@ -141,6 +143,8 @@ namespace FEXCore {
           Item->IRList = IRList;
           Item->DebugData = DebugData;
           Item->RAData = RAData;
+          Item->StartAddr = StartAddr;
+          Item->Length = Length;
 
           GCArray.emplace_back(Item);
           Item->ServiceWorkDone.NotifyAll();

External/FEXCore/Source/Interface/Core/CompileService.h

@@ -2,6 +2,7 @@
 
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Utils/Event.h>
+#include <FEXCore/Utils/Threads.h>
 
 #include <memory>
 #include <thread>
@@ -31,9 +32,11 @@ class CompileService final {
 
       // Outgoing
       void *CodePtr{};
-      FEXCore::IR::IRListView<true> *IRList{};
+      FEXCore::IR::IRListView *IRList{};
       FEXCore::IR::RegisterAllocationData *RAData{};
       FEXCore::Core::DebugData *DebugData{};
+      uint64_t StartAddr;
+      uint64_t Length;
 
       // Communication
       Event ServiceWorkDone{};
@@ -43,12 +46,14 @@ class CompileService final {
     WorkItem *CompileCode(uint64_t RIP);
     void ClearCache(FEXCore::Core::InternalThreadState *Thread);
 
+    // Public for threading
+    void ExecutionThread();
+
   private:
     FEXCore::Context::Context *CTX;
     FEXCore::Core::InternalThreadState *ParentThread;
 
-    void ExecutionThread();
-    std::thread WorkerThread;
+    std::unique_ptr<FEXCore::Threads::Thread> WorkerThread;
     std::unique_ptr<FEXCore::Core::InternalThreadState> CompileThreadData;
 
     std::mutex QueueMutex{};

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp

@@ -0,0 +1,365 @@
+#include "Interface/Core/ArchHelpers/MContext.h"
+#include "Interface/Core/Dispatcher/Arm64Dispatcher.h"
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Context/Context.h"
+
+#include <FEXCore/Core/X86Enums.h>
+#include <bit>
+#include <cmath>
+
+#include "aarch64/assembler-aarch64.h"
+#include "aarch64/cpu-aarch64.h"
+#include "aarch64/disasm-aarch64.h"
+
+namespace FEXCore::CPU {
+
+using namespace vixl;
+using namespace vixl::aarch64;
+
+static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
+#define STATE x28
+
+Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config)
+  : Dispatcher(ctx, Thread), Arm64Emitter(MAX_DISPATCHER_CODE_SIZE) {
+  SRAEnabled = config.StaticRegisterAssignment;
+  SetAllowAssembler(true);
+
+  auto Buffer = GetBuffer();
+  DispatchPtr = Buffer->GetOffsetAddress<CPUBackend::AsmDispatch>(GetCursorOffset());
+
+  // while (true) {
+  //    Ptr = FindBlock(RIP)
+  //    if (!Ptr)
+  //      Ptr = CTX->CompileBlock(RIP);
+  //
+  //    Ptr();
+  // }
+
+  uint64_t VirtualMemorySize = Thread->LookupCache->GetVirtualMemorySize();
+  Literal l_VirtualMemory {VirtualMemorySize};
+  Literal l_PagePtr {Thread->LookupCache->GetPagePointer()};
+  Literal l_L1Ptr {Thread->LookupCache->GetL1Pointer()};
+  Literal l_CTX {reinterpret_cast<uintptr_t>(CTX)};
+  Literal l_Sleep {reinterpret_cast<uint64_t>(SleepThread)};
+  Literal l_CompileBlock {GetCompileBlockPtr()};
+  Literal l_ExitFunctionLink {config.ExitFunctionLink};
+  Literal l_ExitFunctionLinkThis {config.ExitFunctionLinkThis};
+
+  // Push all the register we need to save
+  PushCalleeSavedRegisters();
+
+  // Push our memory base to the correct register
+  // Move our thread pointer to the correct register
+  // This is passed in to parameter 0 (x0)
+  mov(STATE, x0);
+
+  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
+  // regardless of where we were in the stack
+  add(x0, sp, 0);
+  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)));
+
+  AbsoluteLoopTopAddressFillSRA = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+
+  if (SRAEnabled) {
+    FillStaticRegs();
+  }
+
+  // We want to ensure that we are 16 byte aligned at the top of this loop
+  Align16B();
+  aarch64::Label FullLookup{};
+  aarch64::Label CallBlock{};
+  aarch64::Label LoopTop{};
+  aarch64::Label ExitSpillSRA{};
+  aarch64::Label ThreadPauseHandler{};
+
+  bind(&LoopTop);
+  AbsoluteLoopTopAddress = GetLabelAddress<uint64_t>(&LoopTop);
+
+  // Load in our RIP
+  // Don't modify x2 since it contains our RIP once the block doesn't exist
+  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
+  auto RipReg = x2;
+
+  // L1 Cache
+  ldr(x0, &l_L1Ptr);
+
+  and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
+  add(x0, x0, Operand(x3, Shift::LSL, 4));
+  ldp(x3, x0, MemOperand(x0));
+  cmp(x0, RipReg);
+  b(&FullLookup, Condition::ne);
+
+  if (!config.ExecuteBlocksWithCall) {
+    br(x3);
+  } else {
+    b(&CallBlock);
+  }
+
+  // L1C check failed, do a full lookup
+  bind(&FullLookup);
+
+  // This is the block cache lookup routine
+  // It matches what is going on it LookupCache.h::FindBlock
+  ldr(x0, &l_PagePtr);
+
+  // Mask the address by the virtual address size so we can check for aliases
+  if (std::popcount(VirtualMemorySize) == 1) {
+    and_(x3, RipReg, Thread->LookupCache->GetVirtualMemorySize() - 1);
+  }
+  else {
+    ldr(x3, &l_VirtualMemory);
+    and_(x3, RipReg, x3);
+  }
+
+  aarch64::Label NoBlock;
+  {
+    // Offset the address and add to our page pointer
+    lsr(x1, x3, 12);
+
+    // Load the pointer from the offset
+    ldr(x0, MemOperand(x0, x1, Shift::LSL, 3));
+
+    // If page pointer is zero then we have no block
+    cbz(x0, &NoBlock);
+
+    // Steal the page offset
+    and_(x1, x3, 0x0FFF);
+
+    // Shift the offset by the size of the block cache entry
+    add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry))));
+
+    // Load the guest address first to ensure it maps to the address we are currently at
+    // This fixes aliasing problems
+    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)));
+    cmp(x1, RipReg);
+    b(&NoBlock, Condition::ne);
+
+    // Now load the actual host block to execute if we can
+    ldr(x3, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)));
+    cbz(x3, &NoBlock);
+
+    // If we've made it here then we have a real compiled block
+    {
+      // update L1 cache
+      ldr(x0, &l_L1Ptr);
+
+      and_(x1, RipReg, LookupCache::L1_ENTRIES_MASK);
+      add(x0, x0, Operand(x1, Shift::LSL, 4));
+      stp(x3, x2, MemOperand(x0));
+
+      // Jump to the block
+      if (!config.ExecuteBlocksWithCall) {
+        br(x3);
+      } else {
+        bind(&CallBlock);
+        mov(x0, STATE);
+        blr(x3);
+
+        if (CTX->GetGdbServerStatus()) {
+          // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
+          // This happens when single stepping
+
+          static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
+          ldr(x0, &l_CTX);
+          ldr(w0, MemOperand(x0, offsetof(FEXCore::Context::Context, Config.RunningMode)));
+          // If the value == 0 then branch to the top
+          cbz(x0, &LoopTop);
+          // Else we need to pause now
+          b(&ThreadPauseHandler);
+        } else {
+          // Unconditionally loop to the top
+          // We will only stop on error when compiling a block or signal
+          b(&LoopTop);
+        }
+      }
+    }
+  }
+
+  {
+    bind(&ExitSpillSRA);
+    ThreadStopHandlerAddressSpillSRA = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    ThreadStopHandlerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+
+    PopCalleeSavedRegisters();
+
+    // Return from the function
+    // LR is set to the correct return location now
+    ret();
+  }
+
+  {
+    ExitFunctionLinkerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    ldr(x0, &l_ExitFunctionLinkThis);
+    mov(x1, STATE);
+    mov(x2, lr);
+
+    ldr(x3, &l_ExitFunctionLink);
+    blr(x3);
+
+    if (SRAEnabled)
+      FillStaticRegs();
+    br(x0);
+  }
+
+  // Need to create the block
+  {
+    bind(&NoBlock);
+
+    ldr(x0, &l_CTX);
+    mov(x1, STATE);
+    ldr(x3, &l_CompileBlock);
+
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    // X2 contains our guest RIP
+    blr(x3); // { CTX, Frame, RIP}
+
+    if (SRAEnabled)
+      FillStaticRegs();
+
+    b(&LoopTop);
+  }
+
+  {
+    SignalHandlerReturnAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+
+    // Now to get back to our old location we need to do a fault dance
+    // We can't use SIGTRAP here since gdb catches it and never gives it to the application!
+    hlt(0);
+  }
+
+  {
+    ThreadPauseHandlerAddressSpillSRA = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    bind(&ThreadPauseHandler);
+    ThreadPauseHandlerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+    // We are pausing, this means the frontend should be waiting for this thread to idle
+    // We will have faulted and jumped to this location at this point
+
+    // Call our sleep handler
+    ldr(x0, &l_CTX);
+    mov(x1, STATE);
+    ldr(x2, &l_Sleep);
+    blr(x2);
+
+    PauseReturnInstruction = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+    // Fault to start running again
+    hlt(0);
+  }
+
+  {
+    // The expectation here is that a thunked function needs to call back in to the JIT in a reentrant safe way
+    // To do this safely we need to do some state tracking and register saving
+    //
+    // eg:
+    // JIT Call->
+    //  Thunk->
+    //    Thunk callback->
+    //
+    // The thunk callback needs to execute JIT code and when it returns, it needs to safely return to the thunk rather than JIT space
+    // This is handled by pushing a return address trampoline to the stack so when the guest address returns it hits our custom thunk return
+    //  - This will safely return us to the thunk
+    //
+    // On return to the thunk, the thunk can get whatever its return value is from the thread context depending on ABI handling on its end
+    // When the thunk itself returns, it'll do its regular return logic there
+    // void ReentrantCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
+    CallbackPtr = Buffer->GetOffsetAddress<CPUBackend::JITCallback>(GetCursorOffset());
+
+    // We expect the thunk to have previously pushed the registers it was using
+    PushCalleeSavedRegisters();
+
+    // First thing we need to move the thread state pointer back in to our register
+    mov(STATE, x0);
+
+    // Make sure to adjust the refcounter so we don't clear the cache now
+    LoadConstant(x0, reinterpret_cast<uint64_t>(&SignalHandlerRefCounter));
+    ldr(w2, MemOperand(x0));
+    add(w2, w2, 1);
+    str(w2, MemOperand(x0));
+
+    // Now push the callback return trampoline to the guest stack
+    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
+    LoadConstant(x0, CTX->X86CodeGen.CallbackReturn);
+
+    ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
+    sub(x2, x2, 16);
+    str(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
+
+    // Store the trampoline to the guest stack
+    // Guest stack is now correctly misaligned after a regular call instruction
+    str(x0, MemOperand(x2));
+
+    // Store RIP to the context state
+    str(x1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
+
+    // load static regs
+    if (SRAEnabled)
+      FillStaticRegs();
+
+    // Now go back to the regular dispatcher loop
+    b(&LoopTop);
+  }
+
+  place(&l_VirtualMemory);
+  place(&l_PagePtr);
+  place(&l_L1Ptr);
+  place(&l_CTX);
+  place(&l_Sleep);
+  place(&l_CompileBlock);
+  place(&l_ExitFunctionLink);
+  place(&l_ExitFunctionLinkThis);
+
+
+  FinalizeCode();
+  Start = reinterpret_cast<uint64_t>(DispatchPtr);
+  End = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
+  GetBuffer()->SetExecutable();
+
+#if ENABLE_JITSYMBOLS
+  std::string Name = "Dispatch_" + std::to_string(::gettid());
+  CTX->Symbols.Register(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr), Name);
+#endif
+}
+
+void Arm64Dispatcher::SpillSRA(void *ucontext) {
+  for(int i = 0; i < SRA64.size(); i++) {
+    ThreadState->CurrentFrame->State.gregs[i] = ArchHelpers::Context::GetArmReg(ucontext, SRA64[i].GetCode());
+  }
+  // TODO: Also recover FPRs, not sure where the neon context is
+  // This is usually not needed
+  /*
+  for(int i = 0; i < SRAFPR.size(); i++) {
+      State->State.State.xmm[i][0] = _mcontext.neon[SRAFPR[i].GetCode()];
+      State->State.State.xmm[i][0] = _mcontext.neon[SRAFPR[i].GetCode()];
+  }
+  */
+}
+
+#ifdef _M_ARM_64
+
+void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  DispatcherConfig config;
+  config.ExecuteBlocksWithCall = true;
+
+  Dispatcher = std::make_unique<Arm64Dispatcher>(ctx, Thread, config);
+  DispatchPtr = Dispatcher->DispatchPtr;
+  CallbackPtr = Dispatcher->CallbackPtr;
+
+  // TODO: It feels wrong to initialize this way
+  ctx->InterpreterCallbackReturn = Dispatcher->ReturnPtr;
+}
+
+#endif
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.h

@@ -0,0 +1,18 @@
+#pragma once
+
+#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+
+#include "aarch64/assembler-aarch64.h"
+
+namespace FEXCore::CPU {
+
+class Arm64Dispatcher final : public Dispatcher, public Arm64Emitter {
+  public:
+    Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config);
+
+  protected:
+    void SpillSRA(void *ucontext) override;
+};
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -0,0 +1,367 @@
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+
+#include "Common/MathUtils.h"
+#include "Interface/Core/ArchHelpers/MContext.h"
+#include <FEXCore/Core/X86Enums.h>
+
+namespace FEXCore::CPU {
+
+void Dispatcher::SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuStateFrame *Frame) {
+  auto Thread = Frame->Thread;
+
+  --ctx->IdleWaitRefCount;
+  ctx->IdleWaitCV.notify_all();
+
+  // Go to sleep
+  Thread->StartRunning.Wait();
+
+  Thread->RunningEvents.Running = true;
+  ++ctx->IdleWaitRefCount;
+  ctx->IdleWaitCV.notify_all();
+}
+
+void Dispatcher::StoreThreadState(int Signal, void *ucontext) {
+  // We can end up getting a signal at any point in our host state
+  // Jump to a handler that saves all state so we can safely return
+  uint64_t OldSP = ArchHelpers::Context::GetSp(ucontext);
+  uintptr_t NewSP = OldSP;
+
+  size_t StackOffset = sizeof(ArchHelpers::Context::ContextBackup);
+
+  // We need to back up behind the host's red zone
+  // We do this on the guest side as well
+  // (does nothing on arm hosts)
+  NewSP -= ArchHelpers::Context::ContextBackup::RedZoneSize;
+
+  NewSP -= StackOffset;
+  NewSP = AlignDown(NewSP, 16);
+
+  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
+  ArchHelpers::Context::BackupContext(ucontext, Context);
+
+  // Retain the action pointer so we can see it when we return
+  Context->Signal = Signal;
+
+  // Save guest state
+  // We can't guarantee if registers are in context or host GPRs
+  // So we need to save everything
+  memcpy(&Context->GuestState, ThreadState->CurrentFrame, sizeof(FEXCore::Core::CPUState));
+
+  // Set the new SP
+  ArchHelpers::Context::SetSp(ucontext, NewSP);
+
+  SignalFrames.push(NewSP);
+}
+
+void Dispatcher::RestoreThreadState(void *ucontext) {
+  uint64_t OldSP = SignalFrames.top();
+  SignalFrames.pop();
+  uintptr_t NewSP = OldSP;
+  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
+
+  // First thing, reset the guest state
+  memcpy(ThreadState->CurrentFrame, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
+
+  // Now restore host state
+  ArchHelpers::Context::RestoreContext(ucontext, Context);
+
+  // Restore the previous signal state
+  // This allows recursive signals to properly handle signal masking as we are walking back up the list of signals
+  CTX->SignalDelegation->SetCurrentSignal(Context->Signal);
+}
+
+bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
+  StoreThreadState(Signal, ucontext);
+  auto Frame = ThreadState->CurrentFrame;
+
+  // Ref count our faults
+  // We use this to track if it is safe to clear cache
+  ++SignalHandlerRefCounter;
+
+  // Set the new PC
+  ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
+  // Set our state register to point to our guest thread data
+  ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
+
+
+  uint64_t OldGuestSP = Frame->State.gregs[X86State::REG_RSP];
+  uint64_t NewGuestSP = OldGuestSP;
+
+  if (!(GuestStack->ss_flags & SS_DISABLE)) {
+    // If our guest is already inside of the alternative stack
+    // Then that means we are hitting recursive signals and we need to walk back the stack correctly
+    uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
+    uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
+    if (OldGuestSP >= AltStackBase &&
+        OldGuestSP <= AltStackEnd) {
+      // We are already in the alt stack, the rest of the code will handle adjusting this
+    }
+    else {
+      NewGuestSP = AltStackEnd;
+    }
+  }
+
+  // Back up past the redzone, which is 128bytes
+  // Don't need this offset if we aren't going to be putting siginfo in to it
+  NewGuestSP -= 128;
+
+  if (GuestAction->sa_flags & SA_SIGINFO) {
+    if (SRAEnabled) {
+      if (!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), false)) {
+        LOGMAN_THROW_A(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true), "Signals in dispatcher have unsynchronized context");
+      } else {
+        // We are in jit, SRA must be spilled
+        SpillSRA(ucontext);
+      }
+    }
+
+    // Setup ucontext a bit
+    if (CTX->Config.Is64BitMode) {
+
+      NewGuestSP -= sizeof(FEXCore::x86_64::ucontext_t);
+      uint64_t UContextLocation = NewGuestSP;
+
+      NewGuestSP -= sizeof(siginfo_t);
+      uint64_t SigInfoLocation = NewGuestSP;
+
+      FEXCore::x86_64::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86_64::ucontext_t*>(UContextLocation);
+      siginfo_t *guest_siginfo = reinterpret_cast<siginfo_t*>(SigInfoLocation);
+
+      // We have extended float information
+      guest_uctx->uc_flags |= FEXCore::x86_64::UC_FP_XSTATE;
+
+      // Pointer to where the fpreg memory is
+      guest_uctx->uc_mcontext.fpregs = &guest_uctx->__fpregs_mem;
+
+#define COPY_REG(x) \
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
+      COPY_REG(R8);
+      COPY_REG(R9);
+      COPY_REG(R10);
+      COPY_REG(R11);
+      COPY_REG(R12);
+      COPY_REG(R13);
+      COPY_REG(R14);
+      COPY_REG(R15);
+      COPY_REG(RDI);
+      COPY_REG(RSI);
+      COPY_REG(RBP);
+      COPY_REG(RBX);
+      COPY_REG(RDX);
+      COPY_REG(RAX);
+      COPY_REG(RCX);
+      COPY_REG(RSP);
+#undef COPY_REG
+
+      // Copy float registers
+      memcpy(guest_uctx->__fpregs_mem._st, Frame->State.mm, sizeof(Frame->State.mm));
+      memcpy(guest_uctx->__fpregs_mem._xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+
+      // FCW store default
+      guest_uctx->__fpregs_mem.fcw = Frame->State.FCW;
+
+      // Reconstruct FSW
+      guest_uctx->__fpregs_mem.fsw =
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] << 11) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] << 8) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] << 9) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] << 10) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] << 14);
+
+      // Copy over signal stack information
+      guest_uctx->uc_stack.ss_flags = GuestStack->ss_flags;
+      guest_uctx->uc_stack.ss_sp = GuestStack->ss_sp;
+      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
+
+      // siginfo_t
+      siginfo_t *HostSigInfo = reinterpret_cast<siginfo_t*>(info);
+      if (HostSigInfo->si_code == SI_USER) {
+        // If the signal was a user signal then we need to pass this struct through unaltered
+        // Guest might be doing something with it
+        *guest_siginfo = *HostSigInfo;
+      }
+      else {
+        guest_siginfo->si_signo = Signal;
+        switch (Signal) {
+        case SIGSEGV:
+        case SIGBUS:
+          guest_siginfo->si_code = HostSigInfo->si_code;
+          guest_siginfo->si_errno = HostSigInfo->si_errno;
+          // Macro expansion to get the si_addr
+          guest_siginfo->si_addr = HostSigInfo->si_addr;
+          break;
+        default: LogMan::Msg::D("Unhandled siginfo_t signal: %d", Signal); break;
+        }
+      }
+
+      Frame->State.gregs[X86State::REG_RSI] = SigInfoLocation;
+      Frame->State.gregs[X86State::REG_RDX] = UContextLocation;
+    }
+    else {
+      // XXX: 32bit Support
+      NewGuestSP -= sizeof(FEXCore::x86::ucontext_t);
+      uint64_t UContextLocation = 0; // NewGuestSP;
+      NewGuestSP -= sizeof(FEXCore::x86::siginfo_t);
+      uint64_t SigInfoLocation = 0; // NewGuestSP;
+
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = UContextLocation;
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = SigInfoLocation;
+    }
+
+    Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
+  }
+  else {
+    Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
+  }
+
+  if (CTX->Config.Is64BitMode) {
+    Frame->State.gregs[X86State::REG_RDI] = Signal;
+
+    // Set up the new SP for stack handling
+    NewGuestSP -= 8;
+    *(uint64_t*)NewGuestSP = CTX->X86CodeGen.SignalReturn;
+    Frame->State.gregs[X86State::REG_RSP] = NewGuestSP;
+  }
+  else {
+    NewGuestSP -= 4;
+    *(uint32_t*)NewGuestSP = CTX->X86CodeGen.SignalReturn;
+    LOGMAN_THROW_A(CTX->X86CodeGen.SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB");
+    Frame->State.gregs[X86State::REG_RSP] = NewGuestSP;
+  }
+
+  return true;
+}
+
+bool Dispatcher::HandleSIGILL(int Signal, void *info, void *ucontext) {
+
+  if (ArchHelpers::Context::GetPc(ucontext) == SignalHandlerReturnAddress) {
+    RestoreThreadState(ucontext);
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    --SignalHandlerRefCounter;
+    return true;
+  }
+
+  if (ArchHelpers::Context::GetPc(ucontext) == PauseReturnInstruction) {
+    RestoreThreadState(ucontext);
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    --SignalHandlerRefCounter;
+    return true;
+  }
+
+  return false;
+}
+
+bool Dispatcher::HandleSignalPause(int Signal, void *info, void *ucontext) {
+  FEXCore::Core::SignalEvent SignalReason = ThreadState->SignalReason.load();
+  auto Frame = ThreadState->CurrentFrame;
+
+  if (SignalReason == FEXCore::Core::SignalEvent::Pause) {
+    // Store our thread state so we can come back to this
+    StoreThreadState(Signal, ucontext);
+
+    if (SRAEnabled && IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), false)) {
+      // We are in jit, SRA must be spilled
+      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddressSpillSRA);
+    } else {
+      if (SRAEnabled) {
+        // We are in non-jit, SRA is already spilled
+        LOGMAN_THROW_A(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true), "Signals in dispatcher have unsynchronized context");
+      }
+      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddress);
+    }
+
+    // Set the new PC
+    ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddress);
+
+    // Set our state register to point to our guest thread data
+    ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    ++SignalHandlerRefCounter;
+
+    ThreadState->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
+    return true;
+  }
+
+  if (SignalReason == FEXCore::Core::SignalEvent::Stop) {
+    // Our thread is stopping
+    // We don't care about anything at this point
+    // Set the stack to our starting location when we entered the core and get out safely
+    ArchHelpers::Context::SetSp(ucontext, Frame->ReturningStackLocation);
+
+    // Our ref counting doesn't matter anymore
+    SignalHandlerRefCounter = 0;
+
+    // Set the new PC
+    if (SRAEnabled && IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), false)) {
+      // We are in jit, SRA must be spilled
+      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddressSpillSRA);
+    } else {
+      if (SRAEnabled) {
+        // We are in non-jit, SRA is already spilled
+        LOGMAN_THROW_A(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true), "Signals in dispatcher have unsynchronized context");
+      }
+      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddress);
+    }
+
+    ThreadState->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
+    return true;
+  }
+
+  if (SignalReason == FEXCore::Core::SignalEvent::Return) {
+    RestoreThreadState(ucontext);
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    --SignalHandlerRefCounter;
+
+    ThreadState->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
+    return true;
+  }
+
+  return false;
+}
+
+uint64_t Dispatcher::GetCompileBlockPtr() {
+  using ClassPtrType = void (FEXCore::Context::Context::*)(FEXCore::Core::CpuStateFrame *, uint64_t);
+  union PtrCast {
+    ClassPtrType ClassPtr;
+    uintptr_t Data;
+  };
+
+  PtrCast CompileBlockPtr;
+  CompileBlockPtr.ClassPtr = &FEXCore::Context::Context::CompileBlockJit;
+  return CompileBlockPtr.Data;
+}
+
+void Dispatcher::RemoveCodeBuffer(uint8_t* start_to_remove) {
+  for (auto iter = CodeBuffers.begin(); iter != CodeBuffers.end(); ++iter) {
+    auto [start, end] = *iter;
+    if (start == reinterpret_cast<uint64_t>(start_to_remove)) {
+      CodeBuffers.erase(iter);
+      return;
+    }
+  }
+}
+
+bool Dispatcher::IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher) const {
+  for (auto [start, end] : CodeBuffers) {
+    if (Address >= start && Address < end) {
+      return true;
+    }
+  }
+
+  if (IncludeDispatcher) {
+    return IsAddressInDispatcher(Address);
+  }
+  return false;
+}
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h

@@ -0,0 +1,85 @@
+#pragma once
+
+#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/Core/SignalDelegator.h>
+
+#include "Interface/Context/Context.h"
+
+#include <stack>
+
+namespace FEXCore::CPU {
+
+struct DispatcherConfig {
+  bool ExecuteBlocksWithCall = false;
+  uintptr_t ExitFunctionLink = 0;
+  uintptr_t ExitFunctionLinkThis = 0;
+  bool StaticRegisterAssignment = false;
+};
+
+class Dispatcher {
+public:
+  virtual ~Dispatcher() = default;
+  CPUBackend::AsmDispatch DispatchPtr;
+  CPUBackend::JITCallback CallbackPtr;
+  FEXCore::Context::Context::IntCallbackReturn ReturnPtr;
+
+  /**
+   * @name Dispatch Helper functions
+   * @{ */
+  uint64_t ThreadStopHandlerAddress{};
+  uint64_t ThreadStopHandlerAddressSpillSRA{};
+  uint64_t AbsoluteLoopTopAddress{};
+  uint64_t AbsoluteLoopTopAddressFillSRA{};
+  uint64_t ThreadPauseHandlerAddress{};
+  uint64_t ThreadPauseHandlerAddressSpillSRA{};
+  uint64_t ExitFunctionLinkerAddress{};
+  uint64_t SignalHandlerReturnAddress{};
+  uint64_t PauseReturnInstruction{};
+
+  /**  @} */
+
+  uint32_t SignalHandlerRefCounter{};
+
+  uint64_t Start{};
+  uint64_t End{};
+
+  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
+  bool HandleSIGILL(int Signal, void *info, void *ucontext);
+  bool HandleSignalPause(int Signal, void *info, void *ucontext);
+
+  void RegisterCodeBuffer(uint8_t* start, size_t size) {
+    CodeBuffers.emplace_back(reinterpret_cast<uint64_t>(start),
+        reinterpret_cast<uint64_t>(start + size));
+  }
+
+  void RemoveCodeBuffer(uint8_t* start);
+
+  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true) const;
+  bool IsAddressInDispatcher(uint64_t Address) const {
+    return Address >= Start && Address < End;
+  }
+
+protected:
+  Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
+    : CTX {ctx}
+    , ThreadState {Thread} {}
+
+  void StoreThreadState(int Signal, void *ucontext);
+  void RestoreThreadState(void *ucontext);
+  std::stack<uint64_t> SignalFrames;
+
+  bool SRAEnabled = false;
+  virtual void SpillSRA(void *ucontext) {}
+
+  FEXCore::Context::Context *CTX;
+  FEXCore::Core::InternalThreadState *ThreadState;
+
+  static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuStateFrame *Frame);
+
+  static uint64_t GetCompileBlockPtr();
+
+private:
+  std::vector<std::tuple<uint64_t, uint64_t>> CodeBuffers; // Start, End
+};
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp

@@ -0,0 +1,320 @@
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Context/Context.h"
+
+#include <FEXCore/Core/X86Enums.h>
+#include <cmath>
+
+namespace FEXCore::CPU {
+static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
+#define STATE r14
+
+X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config)
+  : Dispatcher(ctx, Thread)
+  , Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE, nullptr, this) {
+
+  using namespace Xbyak;
+  using namespace Xbyak::util;
+  DispatchPtr = getCurr<CPUBackend::AsmDispatch>();
+
+  // Temp registers
+  // rax, rcx, rdx, rsi, r8, r9,
+  // r10, r11
+  //
+  // Callee Saved
+  // rbx, rbp, r12, r13, r14, r15
+  //
+  // 1St Argument: rdi <ThreadState>
+  // XMM:
+  // All temp
+
+  // while (true) {
+  //    Ptr = FindBlock(RIP)
+  //    if (!Ptr)
+  //      Ptr = CTX->CompileBlock(RIP);
+  //
+  //    if (Ptr)
+  //      Ptr();
+  //    else
+  //    {
+  //      Ptr = FallbackCore->CompileBlock()
+  //      if (Ptr)
+  //        Ptr()
+  //      else {
+  //        ShouldStop = true;
+  //      }
+  //    }
+  // }
+  // Bunch of exit state stuff
+
+  // x86-64 ABI has the stack aligned when /call/ happens
+  // Which means the destination has a misaligned stack at that point
+  push(rbx);
+  push(rbp);
+  push(r12);
+  push(r13);
+  push(r14);
+  push(r15);
+  sub(rsp, 8);
+
+  mov(STATE, rdi);
+
+  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
+  // regardless of where we were in the stack
+  mov(qword [rdi + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)], rsp);
+
+  Label LoopTop;
+  Label FullLookup;
+  Label CallBlock;
+  Label NoBlock;
+  Label ExitBlock;
+  Label ThreadPauseHandler;
+
+  L(LoopTop);
+  AbsoluteLoopTopAddressFillSRA = AbsoluteLoopTopAddress = getCurr<uint64_t>();
+
+  {
+    // Load our RIP
+    mov(rdx, qword [STATE + offsetof(FEXCore::Core::CPUState, rip)]);
+
+    // L1 Cache
+    mov(r13, Thread->LookupCache->GetL1Pointer());
+    mov(rax, rdx);
+
+    and_(rax, LookupCache::L1_ENTRIES_MASK);
+    shl(rax, 4);
+    cmp(qword[r13 + rax + 8], rdx);
+    jne(FullLookup);
+
+    if (!config.ExecuteBlocksWithCall) {
+      jmp(qword[r13 + rax + 0]);
+    } else {
+      mov(rax, qword[r13 + rax + 0]);
+      jmp(CallBlock);
+    }
+
+    L(FullLookup);
+    mov(r13, Thread->LookupCache->GetPagePointer());
+
+    // Full lookup
+    mov(rax, rdx);
+    mov(rbx, Thread->LookupCache->GetVirtualMemorySize() - 1);
+    and_(rax, rbx);
+    shr(rax, 12);
+
+    // Load page pointer
+    mov(rdi, qword [r13 + rax * 8]);
+
+    cmp(rdi, 0);
+    je(NoBlock);
+
+    mov (rax, rdx);
+    and_(rax, 0x0FFF);
+
+    shl(rax, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
+
+    // check for aliasing
+    mov(rcx, qword [rdi + rax + 8]);
+    cmp(rcx, rdx);
+    jne(NoBlock);
+
+    // Load the block pointer
+    mov(rax, qword [rdi + rax]);
+
+    cmp(rax, 0);
+    je(NoBlock);
+
+    // Update L1
+    
+    mov(r13, Thread->LookupCache->GetL1Pointer());
+    mov(rcx, rdx);
+    and_(rcx, LookupCache::L1_ENTRIES_MASK);
+    shl(rcx, 1);
+    mov(qword[r13 + rcx*8 + 8], rdx);
+    mov(qword[r13 + rcx*8 + 0], rax);
+
+    // Real block if we made it here
+    if (!config.ExecuteBlocksWithCall) {
+      jmp(rax);
+    } else {
+      L(CallBlock);
+      mov(rdi, STATE);
+      call(rax);
+
+      if (CTX->GetGdbServerStatus()) {
+        // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
+        // This happens when single stepping
+        static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
+        mov(rax, qword [STATE + (offsetof(FEXCore::Core::InternalThreadState, CTX))]);
+
+        // If the value == 0 then branch to the top
+        cmp(dword [rax + (offsetof(FEXCore::Context::Context, Config.RunningMode))], 0);
+        je(LoopTop);
+        // Else we need to pause now
+        jmp(ThreadPauseHandler);
+        ud2();
+      }
+      else {
+        jmp(LoopTop);
+      }
+    }
+  }
+
+  {
+    L(ExitBlock);
+    ThreadStopHandlerAddress = getCurr<uint64_t>();
+
+    add(rsp, 8);
+
+    pop(r15);
+    pop(r14);
+    pop(r13);
+    pop(r12);
+    pop(rbp);
+    pop(rbx);
+
+    ret();
+  }
+
+  // Block creation
+  {
+    L(NoBlock);
+
+    // {rdi, rsi, rdx}
+    mov(rdi, reinterpret_cast<uint64_t>(CTX));
+    mov(rsi, STATE);
+    mov(rax, GetCompileBlockPtr());
+
+    call(rax);
+
+    // rdx already contains RIP here
+    jmp(LoopTop);
+  }
+
+  {
+    ExitFunctionLinkerAddress = getCurr<uint64_t>();
+    // {rdi, rsi, rdx}
+    mov(rdi, config.ExitFunctionLinkThis);
+    mov(rsi, STATE);
+    mov(rdx, rax); // rax is set at the block end
+
+    mov(rax, config.ExitFunctionLink);
+    call(rax);
+    jmp(rax);
+  }
+
+  {
+    // Pause handler
+    ThreadPauseHandlerAddress = getCurr<uint64_t>();
+    L(ThreadPauseHandler);
+
+    mov(rdi, reinterpret_cast<uintptr_t>(CTX));
+    mov(rsi, STATE);
+    mov(rax, reinterpret_cast<uint64_t>(SleepThread));
+
+    call(rax);
+
+    // XXX: Unsupported atm
+    PauseReturnInstruction = getCurr<uint64_t>();
+    ud2();
+  }
+
+  {
+    CallbackPtr = getCurr<CPUBackend::JITCallback>();
+
+    push(rbx);
+    push(rbp);
+    push(r12);
+    push(r13);
+    push(r14);
+    push(r15);
+    sub(rsp, 8);
+
+    // First thing we need to move the thread state pointer back in to our register
+    mov(STATE, rdi);
+    // XXX: XMM?
+
+    // Make sure to adjust the refcounter so we don't clear the cache now
+    mov(rax, reinterpret_cast<uint64_t>(&SignalHandlerRefCounter));
+    add(dword [rax], 1);
+
+    // Now push the callback return trampoline to the guest stack
+    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
+    mov(rax, CTX->X86CodeGen.CallbackReturn);
+
+    // Store the trampoline to the guest stack
+    // Guest stack is now correctly misaligned after a regular call instruction
+    sub(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])], 16);
+    mov(rbx, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])]);
+    mov(qword [rbx], rax);
+
+    // Store RIP to the context state
+    mov(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.rip)], rsi);
+
+    // Back to the loop top now
+    jmp(LoopTop);
+  }
+
+  {
+    // Signal return handler
+    SignalHandlerReturnAddress = getCurr<uint64_t>();
+
+    ud2();
+  }
+
+
+  {
+    ReturnPtr = getCurr<FEXCore::Context::Context::IntCallbackReturn>();
+//  using CallbackReturn =  FEX_NAKED void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
+
+    // rdi = thread
+    // rsi = rsp
+
+    mov(rsp, rsi);
+
+    // Now jump back to the thunk
+    // XXX: XMM?
+    add(rsp, 8);
+
+    pop(r15);
+    pop(r14);
+    pop(r13);
+    pop(r12);
+    pop(rbp);
+    pop(rbx);
+
+    ret();
+  }
+  ready();
+
+  Start = reinterpret_cast<uint64_t>(getCode());
+  End = Start + getSize();
+
+  #if ENABLE_JITSYMBOLS
+    std::string Name = "Dispatch_" + std::to_string(::gettid());
+    CTX->Symbols.Register(reinterpret_cast<void*>(Start), End-Start, Name);
+  #endif
+}
+
+X86Dispatcher::~X86Dispatcher() {
+
+}
+
+#ifdef _M_X86_64
+
+void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  DispatcherConfig config;
+  config.ExecuteBlocksWithCall = true;
+
+  Dispatcher = std::make_unique<X86Dispatcher>(ctx, Thread, config);
+  DispatchPtr = Dispatcher->DispatchPtr;
+  CallbackPtr = Dispatcher->CallbackPtr;
+
+  // TODO: It feels wrong to initialize this way
+  ctx->InterpreterCallbackReturn = Dispatcher->ReturnPtr;
+}
+
+#endif
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.h

@@ -0,0 +1,27 @@
+#pragma once
+
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+
+#include <FEXCore/Utils/Allocator.h>
+
+#define XBYAK64
+#include <xbyak/xbyak.h>
+
+namespace FEXCore::CPU {
+
+class X86Dispatcher final : public Dispatcher, public Xbyak::CodeGenerator, public Xbyak::Allocator {
+  public:
+    X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config);
+
+    virtual ~X86Dispatcher() override;
+
+    // Xbyak::Allocator
+    Xbyak::uint8 *alloc(size_t size) override { Size = size; return reinterpret_cast<uint8_t*>(FEXCore::Allocator::mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0)); }
+    void free(Xbyak::uint8 *p) override { FEXCore::Allocator::munmap(p, Size); }
+    bool useProtect() const override { return false; }
+
+  private:
+    size_t Size{};
+};
+
+}

External/FEXCore/Source/Interface/Core/Frontend.cpp

@@ -1,3 +1,10 @@
+/*
+$info$
+tags: frontend|x86-meta-blocks
+desc: Extracts instruction & block meta info, frontend multiblock logic
+$end_info$
+*/
+
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Frontend.h"
 #include "Interface/Core/InternalThreadState.h"
@@ -8,6 +15,7 @@
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <set>
 
 namespace FEXCore::Frontend {
 using namespace FEXCore::X86Tables;
@@ -117,38 +125,29 @@ Decoder::Decoder(FEXCore::Context::Context *ctx)
 
 uint8_t Decoder::ReadByte() {
   uint8_t Byte = InstStream[InstructionSize];
-  LogMan::Throw::A(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
+  LOGMAN_THROW_A(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
   Instruction[InstructionSize] = Byte;
   InstructionSize++;
   return Byte;
 }
 
-uint8_t Decoder::PeekByte(uint8_t Offset) {
+uint8_t Decoder::PeekByte(uint8_t Offset) const {
   uint8_t Byte = InstStream[InstructionSize + Offset];
   return Byte;
 }
 
 uint64_t Decoder::ReadData(uint8_t Size) {
-  uint64_t Res{};
-#define READ_DATA(x, y) \
-  case x: { \
-    y const *Data = reinterpret_cast<y const*>(&InstStream[InstructionSize]); \
-    Res = *Data; \
-  } \
-  break
-
-  switch (Size) {
-  case 0: return 0;
-  READ_DATA(1, uint8_t);
-  READ_DATA(2, uint16_t);
-  case 3: memcpy(&Res, &InstStream[InstructionSize], Size);
-  READ_DATA(4, uint32_t);
-  READ_DATA(8, uint64_t);
-  default:
-  LogMan::Msg::A("Unknown data size to read");
-  return 0;
+  if (Size == 0) {
+    return 0;
   }
-#undef READ_DATA
+
+  if (Size > sizeof(uint64_t)) {
+    LOGMAN_MSG_A("Unknown data size to read");
+    return 0;
+  }
+
+  uint64_t Res = 0;
+  std::memcpy(&Res, &InstStream[InstructionSize], Size);
 
 #ifndef NDEBUG
   for(size_t i = 0; i < Size; ++i) {
@@ -157,6 +156,7 @@ uint64_t Decoder::ReadData(uint8_t Size) {
 #else
   SkipBytes(Size);
 #endif
+
   return Res;
 }
 
@@ -197,9 +197,9 @@ void Decoder::DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     }
   }
 
-  Operand->TypeSIB.Type = DecodedOperand::TYPE_SIB;
-  Operand->TypeSIB.Scale = 1;
-  Operand->TypeSIB.Offset = Literal;
+  Operand->Type = DecodedOperand::OpType::SIB;
+  Operand->Data.SIB.Scale = 1;
+  Operand->Data.SIB.Offset = Literal;
 
   // Only called when ModRM.mod != 0b11
   struct Encodings {
@@ -238,8 +238,8 @@ void Decoder::DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModR
 
   uint8_t LookupIndex = ModRM.mod << 3 | ModRM.rm;
   auto it = Lookup[LookupIndex];
-  Operand->TypeSIB.Base = it.Base;
-  Operand->TypeSIB.Index = it.Index;
+  Operand->Data.SIB.Base = it.Base;
+  Operand->Data.SIB.Index = it.Index;
 }
 
 void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM) {
@@ -277,21 +277,21 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     }
 
     // SIB
-    Operand->TypeSIB.Type = DecodedOperand::TYPE_SIB;
-    Operand->TypeSIB.Scale = 1 << SIB.scale;
+    Operand->Type = DecodedOperand::OpType::SIB;
+    Operand->Data.SIB.Scale = 1 << SIB.scale;
 
     // The invalid encoding types are described at Table 1-12. "promoted nsigned is always non-zero"
-    Operand->TypeSIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
-    Operand->TypeSIB.Base  = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
+    Operand->Data.SIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
+    Operand->Data.SIB.Base  = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
 
     uint64_t Literal {0};
-    LogMan::Throw::A(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
+    LOGMAN_THROW_A(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
 
     Literal = ReadData(Displacement);
     if (Displacement == 1) {
       Literal = static_cast<int8_t>(Literal);
     }
-    Operand->TypeSIB.Offset = Literal;
+    Operand->Data.SIB.Offset = Literal;
   }
   else if (ModRM.mod == 0) {
     // Explained in Table 1-14. "Operand Addressing Using ModRM and SIB Bytes"
@@ -300,13 +300,13 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
       uint32_t Literal;
       Literal = ReadData(4);
 
-      Operand->TypeRIPLiteral.Type = DecodedOperand::TYPE_RIP_RELATIVE;
-      Operand->TypeRIPLiteral.Literal.u = Literal;
+      Operand->Type = DecodedOperand::OpType::RIPRelative;
+      Operand->Data.RIPLiteral.Value.u = Literal;
     }
     else {
       // Register-direct addressing
-      Operand->TypeGPR.Type = DecodedOperand::TYPE_GPR_DIRECT;
-      Operand->TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
+      Operand->Type = DecodedOperand::OpType::GPRDirect;
+      Operand->Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
     }
   }
   else {
@@ -318,9 +318,9 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     }
     Displacement = DisplacementSize;
 
-    Operand->TypeGPRIndirect.Type = DecodedOperand::TYPE_GPR_INDIRECT;
-    Operand->TypeGPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
-    Operand->TypeGPRIndirect.Displacement = Literal;
+    Operand->Type = DecodedOperand::OpType::GPRIndirect;
+    Operand->Data.GPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
+    Operand->Data.GPRIndirect.Displacement = Literal;
   }
 }
 
@@ -344,7 +344,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
     return false;
   }
 
-  LogMan::Throw::A(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P),
+  LOGMAN_THROW_A(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P),
     "Group Ops should have been decoded before this!");
 
   uint8_t DestSize{};
@@ -460,22 +460,25 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ||
       HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RDX)) {
     // Some instructions hardcode their destination as RAX
-    CurrentDest->TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    CurrentDest->TypeGPR.HighBits = false;
-    CurrentDest->TypeGPR.GPR = HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ? FEXCore::X86State::REG_RAX : FEXCore::X86State::REG_RDX;
+    CurrentDest->Type = DecodedOperand::OpType::GPR;
+    CurrentDest->Data.GPR.HighBits = false;
+    CurrentDest->Data.GPR.GPR = HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ? FEXCore::X86State::REG_RAX : FEXCore::X86State::REG_RDX;
     CurrentDest = &DecodeInst->Src[0];
   }
 
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_REX_IN_BYTE)) {
-    LogMan::Throw::A(!HasMODRM, "This instruction shouldn't have ModRM!");
+    LOGMAN_THROW_A(!HasMODRM, "This instruction shouldn't have ModRM!");
 
     // If the REX is in the byte that means the lower nibble of the OP contains the destination GPR
     // This also means that the destination is always a GPR on these ones
     // ADDITIONALLY:
     // If there is a REX prefix then that allows extended GPR usage
-    CurrentDest->TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    DecodeInst->Dest.TypeGPR.HighBits = (Is8BitDest && !HasREX && (Op & 0b111) >= 0b100) || HasHighXMM;
-    CurrentDest->TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, Op & 0b111, Is8BitDest, HasREX, false, false);
+    CurrentDest->Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Dest.Data.GPR.HighBits = (Is8BitDest && !HasREX && (Op & 0b111) >= 0b100) || HasHighXMM;
+    CurrentDest->Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, Op & 0b111, Is8BitDest, HasREX, false, false);
+
+    if (CurrentDest->Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
+      return false;
   }
 
   uint8_t Bytes = Info->MoreBytes;
@@ -498,55 +501,63 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
     ModRM.Hex = DecodeInst->ModRM;
 
     // Decode the GPR source first
-    GPR.TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    GPR.TypeGPR.HighBits = (GPR8Bit && ModRM.reg >= 0b100 && !HasREX) || HasHighXMM;
-    GPR.TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_R ? 1 : 0, ModRM.reg, GPR8Bit, HasREX, HasXMMGPR, HasMMGPR);
+    GPR.Type = DecodedOperand::OpType::GPR;
+    GPR.Data.GPR.HighBits = (GPR8Bit && ModRM.reg >= 0b100 && !HasREX) || HasHighXMM;
+    GPR.Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_R ? 1 : 0, ModRM.reg, GPR8Bit, HasREX, HasXMMGPR, HasMMGPR);
+
+    if (GPR.Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
+      return false;
 
     // ModRM.mod == 0b11 == Register
     // ModRM.Mod != 0b11 == Register-direct addressing
     if (ModRM.mod == 0b11) {
-      NonGPR.TypeGPR.Type = DecodedOperand::TYPE_GPR;
-      NonGPR.TypeGPR.HighBits = (NonGPR8Bit && ModRM.rm >= 0b100 && !HasREX) || HasHighXMM;
-      NonGPR.TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, NonGPR8Bit, HasREX, HasXMMNonGPR, HasMMNonGPR);
+      NonGPR.Type = DecodedOperand::OpType::GPR;
+      NonGPR.Data.GPR.HighBits = (NonGPR8Bit && ModRM.rm >= 0b100 && !HasREX) || HasHighXMM;
+      NonGPR.Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, NonGPR8Bit, HasREX, HasXMMNonGPR, HasMMNonGPR);
+      if (NonGPR.Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
+        return false;
     }
     else {
       auto Disp = DecodeModRMs_Disp[Has16BitAddressing];
       (this->*Disp)(&NonGPR, ModRM);
     }
+
+    return true;
   };
 
   size_t CurrentSrc = 0;
 
   if (Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM) {
     if (Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SF_MOD_DST) {
-      ModRMOperand(DecodeInst->Src[CurrentSrc], DecodeInst->Dest, HasXMMSrc, HasXMMDst, HasMMSrc, HasMMDst, Is8BitSrc, Is8BitDest);
+      if (!ModRMOperand(DecodeInst->Src[CurrentSrc], DecodeInst->Dest, HasXMMSrc, HasXMMDst, HasMMSrc, HasMMDst, Is8BitSrc, Is8BitDest))
+        return false;
     }
     else {
-      ModRMOperand(DecodeInst->Dest, DecodeInst->Src[CurrentSrc], HasXMMDst, HasXMMSrc, HasMMDst, HasMMSrc, Is8BitDest, Is8BitSrc);
+      if (!ModRMOperand(DecodeInst->Dest, DecodeInst->Src[CurrentSrc], HasXMMDst, HasXMMSrc, HasMMDst, HasMMSrc, Is8BitDest, Is8BitSrc))
+        return false;
     }
     ++CurrentSrc;
   }
 
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_RAX)) {
-    DecodeInst->Src[CurrentSrc].TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    DecodeInst->Src[CurrentSrc].TypeGPR.HighBits = false;
-    DecodeInst->Src[CurrentSrc].TypeGPR.GPR = FEXCore::X86State::REG_RAX;
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
+    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = FEXCore::X86State::REG_RAX;
     ++CurrentSrc;
   }
   else if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_RCX)) {
-    DecodeInst->Src[CurrentSrc].TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    DecodeInst->Src[CurrentSrc].TypeGPR.HighBits = false;
-    DecodeInst->Src[CurrentSrc].TypeGPR.GPR = FEXCore::X86State::REG_RCX;
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
+    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = FEXCore::X86State::REG_RCX;
     ++CurrentSrc;
   }
 
   if (Bytes != 0) {
-    LogMan::Throw::A(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
+    LOGMAN_THROW_A(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
 
-    DecodeInst->Src[CurrentSrc].TypeLiteral.Size = Bytes;
+    DecodeInst->Src[CurrentSrc].Data.Literal.Size = Bytes;
 
-    uint64_t Literal {0};
-    Literal = ReadData(Bytes);
+    uint64_t Literal = ReadData(Bytes);
 
     if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SRC_SEXT) ||
         (DecodeFlags::GetSizeDstFlags(DecodeInst->Flags) == DecodeFlags::SIZE_64BIT && Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SRC_SEXT64BIT)) {
@@ -559,15 +570,15 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
       else {
         Literal = static_cast<int32_t>(Literal);
       }
-      DecodeInst->Src[CurrentSrc].TypeLiteral.Size = DestSize;
+      DecodeInst->Src[CurrentSrc].Data.Literal.Size = DestSize;
     }
 
     Bytes = 0;
-    DecodeInst->Src[CurrentSrc].TypeLiteral.Type = DecodedOperand::TYPE_LITERAL;
-    DecodeInst->Src[CurrentSrc].TypeLiteral.Literal = Literal;
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::Literal;
+    DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal;
   }
 
-  LogMan::Throw::A(Bytes == 0, "Inst at 0x%lx: 0x%04x '%s' Had an instruction of size %d with %d remaining", DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name, InstructionSize, Bytes);
+  LOGMAN_THROW_A(Bytes == 0, "Inst at 0x%lx: 0x%04x '%s' Had an instruction of size %d with %d remaining", DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name, InstructionSize, Bytes);
   DecodeInst->InstSize = InstructionSize;
   return true;
 }
@@ -592,7 +603,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
     return false;
   }
 
-  LogMan::Throw::A(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX, "REX PREFIX should have been decoded before this!");
+  LOGMAN_THROW_A(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX, "REX PREFIX should have been decoded before this!");
 
   if (Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 &&
       Info->Type <= FEXCore::X86Tables::TYPE_GROUP_11) {
@@ -648,7 +659,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
         3,
       };
       uint8_t Field = RegToField[ModRM.reg];
-      LogMan::Throw::A(Field != 255, "Invalid field selected!");
+      LOGMAN_THROW_A(Field != 255, "Invalid field selected!");
 
       LocalOp = (Field << 3) | ModRM.rm;
       return NormalOp(&SecondModRMTableOps[LocalOp], LocalOp);
@@ -682,7 +693,10 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
       uint8_t Byte2 = ReadByte();
       pp = Byte2 & 0b11;
       map_select = Byte1 & 0b11111;
-      LogMan::Throw::A(map_select >= 1 && map_select <= 3, "We don't understand a map_select of: %d", map_select);
+      if (!(map_select >= 1 && map_select <= 3)) {
+        LogMan::Msg::E("We don't understand a map_select of: %d", map_select);
+        return false;
+      }
     }
 
     uint16_t VEXOp = ReadByte();
@@ -730,6 +744,8 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
   DecodeInst->PC = PC;
 
   for(;;) {
+    if (InstructionSize >= MAX_INST_SIZE)
+      return false;
     uint8_t Op = ReadByte();
     switch (Op) {
     case 0x0F: {// Escape Op
@@ -880,7 +896,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
       auto Info = &FEXCore::X86Tables::BaseOps[Op];
 
       if (Info->Type == FEXCore::X86Tables::TYPE_REX_PREFIX) {
-        LogMan::Throw::A(CTX->Config.Is64BitMode, "Got REX prefix in 32bit mode");
+        LOGMAN_THROW_A(CTX->Config.Is64BitMode, "Got REX prefix in 32bit mode");
         DecodeInst->Flags |= DecodeFlags::FLAG_REX_PREFIX;
 
         // Widening displacement
@@ -910,6 +926,10 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
 
   }
 
+  if (DecodeInst->Dest.IsGPR()) {
+    assert(DecodeInst->Dest.Data.GPR.GPR != 255);
+  }
+
   return true;
 }
 
@@ -919,6 +939,7 @@ void Decoder::BranchTargetInMultiblockRange() {
 
   // If the RIP setting is conditional AND within our symbol range then it can be considered for multiblock
   uint64_t TargetRIP = 0;
+  uint8_t GPRSize = CTX->Config.Is64BitMode ? 8 : 4;
   bool Conditional = true;
 
   switch (DecodeInst->OP) {
@@ -928,24 +949,33 @@ void Decoder::BranchTargetInMultiblockRange() {
       // auto RIPOffset = LoadSource(Op, Op->Src[0], Op->Flags);
       // auto RIPTargetConst = _Constant(Op->PC + Op->InstSize);
       // Target offset is PC + InstSize + Literal
-      LogMan::Throw::A(DecodeInst->Src[0].TypeNone.Type == DecodedOperand::TYPE_LITERAL, "Had wrong operand type");
-      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].TypeLiteral.Literal;
+      LOGMAN_THROW_A(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
+      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
     break;
     }
     case 0xE9:
     case 0xEB: // Both are unconditional JMP instructions
-      LogMan::Throw::A(DecodeInst->Src[0].TypeNone.Type == DecodedOperand::TYPE_LITERAL, "Had wrong operand type");
-      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].TypeLiteral.Literal;
+      LOGMAN_THROW_A(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
+      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
       Conditional = false;
     break;
+    case 0xE8: // Call - Immediate target, We don't want to inline calls
+      if (ExternalBranches) {
+        ExternalBranches->insert(DecodeInst->PC + DecodeInst->InstSize);
+      }
+      [[fallthrough]];
     case 0xC2: // RET imm
     case 0xC3: // RET
-    case 0xE8: // Call - Immediate target, We don't want to inline calls
     default:
       return;
     break;
   }
 
+  if (GPRSize == 4) {
+    // If we are running a 32bit guest then wrap around addresses that go above 32bit
+    TargetRIP &= 0xFFFFFFFFU;
+  }
+
   // If the target RIP is within the symbol ranges then we are golden
   if (TargetRIP >= SymbolMinAddress && TargetRIP < SymbolMaxAddress) {
     // Update our conditional branch ranges before we return
@@ -965,6 +995,10 @@ void Decoder::BranchTargetInMultiblockRange() {
         BlocksToDecode.find(TargetRIP) == BlocksToDecode.end()) {
       BlocksToDecode.emplace(TargetRIP);
     }
+  } else {
+    if (ExternalBranches) {
+      ExternalBranches->insert(TargetRIP);
+    }
   }
 }
 
@@ -988,10 +1022,13 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
   // If we don't have symbols available then we become a bit optimistic about multiblock ranges
   if (!SymbolAvailable) {
     // If we don't have a symbol available then assume all branches are valid for multiblock
-    SymbolMaxAddress = ~0ULL;
+    SymbolMaxAddress = SectionMaxAddress;
     SymbolMinAddress = EntryPoint;
   }
 
+  DecodedMinAddress = EntryPoint;
+  DecodedMaxAddress = EntryPoint;
+
   // Entry is a jump target
   BlocksToDecode.emplace(PC);
 
@@ -1015,11 +1052,20 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
 
       if (ErrorDuringDecoding) {
         LogMan::Msg::D("Couldn't Decode something at 0x%lx, Started at 0x%lx", PC + PCOffset, PC);
-        LogMan::Throw::A(EntryPoint != (RIPToDecode + PCOffset), "Trying to execute invalid code");
+        if (Blocks.size() == 1) {
+          return false;
+        }
+        LOGMAN_THROW_A(Blocks.size() != 1, "Decode Error in entry block");
+
         CurrentBlockDecoding.HasInvalidInstruction = true;
+        if (ErrorDuringDecoding && Blocks.size() != 1) {
+          ErrorDuringDecoding = false;
+        }
         break;
       }
 
+      DecodedMinAddress = std::min(DecodedMinAddress, RIPToDecode + PCOffset);
+      DecodedMaxAddress = std::max(DecodedMaxAddress, RIPToDecode + PCOffset + DecodeInst->InstSize);
       ++TotalInstructions;
       ++BlockNumberOfInstructions;
       ++DecodedSize;

External/FEXCore/Source/Interface/Core/Frontend.h

@@ -26,10 +26,15 @@ public:
   Decoder(FEXCore::Context::Context *ctx);
   bool DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC);
 
-  std::vector<DecodedBlocks> const *GetDecodedBlocks() {
+  std::vector<DecodedBlocks> const *GetDecodedBlocks() const {
     return &Blocks;
   }
 
+  uint64_t DecodedMinAddress {};
+  uint64_t DecodedMaxAddress {~0ULL};
+  
+  void SetSectionMaxAddress(uint64_t v) { SectionMaxAddress = v; }
+  void SetExternalBranches(std::set<uint64_t> *v) { ExternalBranches = v; }
 private:
   FEXCore::Context::Context *CTX;
 
@@ -38,7 +43,7 @@ private:
   void BranchTargetInMultiblockRange();
 
   uint8_t ReadByte();
-  uint8_t PeekByte(uint8_t Offset);
+  uint8_t PeekByte(uint8_t Offset) const;
   uint64_t ReadData(uint8_t Size);
   void SkipBytes(uint8_t Size) { InstructionSize += Size; }
   bool NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op);
@@ -62,10 +67,12 @@ private:
   uint64_t MaxCondBranchBackwards {~0ULL};
   uint64_t SymbolMaxAddress {};
   uint64_t SymbolMinAddress {~0ULL};
+  uint64_t SectionMaxAddress {~0ULL};
 
   std::vector<DecodedBlocks> Blocks;
   std::set<uint64_t> BlocksToDecode;
   std::set<uint64_t> HasBlocks;
+  std::set<uint64_t> *ExternalBranches {nullptr};
 
   // ModRM rm decoding
   using DecodeModRMPtr = void (FEXCore::Frontend::Decoder::*)(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);

External/FEXCore/Source/Interface/Core/GdbServer.cpp

@@ -1,3 +1,10 @@
+/*
+$info$
+tags: glue|gdbserver
+desc: Provides a gdb interface to the guest state
+$end_info$
+*/
+
 #include <cstdlib>
 #include <cstdio>
 #include <iomanip>
@@ -8,15 +15,19 @@
 #include <optional>
 #include "Common/NetStream.h"
 #include "Common/SoftFloat.h"
+
+#include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/LogManager.h>
 
-#include <sys/types.h>
-#include <sys/socket.h>
-#include <netdb.h>
-#include <string.h>
+#include <cstring>
 #include <fcntl.h>
-#include <unistd.h>
+#include <fmt/format.h>
 #include <fstream>
+#include <netdb.h>
+#include <sys/socket.h>
+#include <sys/types.h>
+#include <unistd.h>
+
 
 #include "GdbServer.h"
 #include <FEXCore/Core/CodeLoader.h>
@@ -27,12 +38,12 @@ namespace FEXCore
 
 void GdbServer::Break(int signal) {
     std::lock_guard lk(sendMutex);
+    if (!CommsStream) {
+      return;
+    }
 
-    std::ostringstream ss;
-    ss << "S" << std::setfill('0') << std::setw(2) << std::hex << signal;
-
-    if (CommsStream)
-        SendPacket(*CommsStream, ss.str());
+    const auto str = fmt::format("S{:02x}", signal);
+    SendPacket(*CommsStream, str);
 }
 
 GdbServer::GdbServer(FEXCore::Context::Context *ctx) : CTX(ctx) {
@@ -58,7 +69,7 @@ GdbServer::GdbServer(FEXCore::Context::Context *ctx) : CTX(ctx) {
     StartThread();
 }
 
-static int calculateChecksum(std::string &packet) {
+static int calculateChecksum(const std::string &packet) {
     unsigned char checksum = 0;
     for (const char &c : packet) {
         checksum += c;
@@ -92,11 +103,9 @@ static std::string encodeHex(unsigned char *data, size_t length) {
 }
 
 static std::string getThreadName(uint32_t ThreadID) {
-  std::fstream fs;
-  std::ostringstream ThreadFile;
-  ThreadFile << "/proc/" << getpid() << "/task/" << ThreadID << "/comm";
+  const auto ThreadFile = fmt::format("/proc/{}/task/{}/comm", getpid(), ThreadID);
+  std::fstream fs(ThreadFile, std::fstream::in | std::fstream::binary);
 
-  fs.open(ThreadFile.str(), std::fstream::in | std::fstream::binary);
   if (fs.is_open()) {
     std::string ThreadName;
     fs >> ThreadName;
@@ -128,7 +137,7 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
         switch(c) {
         case '$': // start of packet
             if (packet.size() != 0)
-                LogMan::Msg::E("Dropping unexpected data: \"%s\"", packet.c_str());
+                LogMan::Msg::EFmt("Dropping unexpected data: \"{}\"", packet);
 
             // clear any existing data, must have been a mistake.
             packet = std::string();
@@ -149,7 +158,7 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
             if (calculateChecksum(packet) == expected_checksum) {
                 return packet;
             } else {
-                LogMan::Msg::E("Received Invalid Packet: $%s#%02x %c%c", packet.c_str(), expected_checksum);
+                LogMan::Msg::EFmt("Received Invalid Packet: ${}#{:02x}", packet, expected_checksum);
             }
             break;
         }
@@ -162,10 +171,10 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
     return "";
 }
 
-static std::string escapePacket(std::string packet) {
+static std::string escapePacket(const std::string& packet) {
     std::ostringstream ss;
 
-    for(auto &c : packet) {
+    for(const auto &c : packet) {
         switch (c) {
         case '$':
         case '#':
@@ -184,13 +193,11 @@ static std::string escapePacket(std::string packet) {
     return ss.str();
 }
 
-void GdbServer::SendPacket(std::ostream &stream, std::string packet) {
-  auto escaped = escapePacket(packet);
-  std::ostringstream ss;
+void GdbServer::SendPacket(std::ostream &stream, const std::string& packet) {
+  const auto escaped = escapePacket(packet);
+  const auto str = fmt::format("${}#{:02x}", escaped, calculateChecksum(escaped));
 
-  ss << '$' << escaped << '#';
-  ss << std::setfill('0') << std::setw(2) << std::hex << (int)calculateChecksum(escaped);
-  stream << ss.str() << std::flush;
+  stream << str << std::flush;
 }
 
 void GdbServer::SendACK(std::ostream &stream, bool NACK) {
@@ -211,7 +218,7 @@ void GdbServer::SendACK(std::ostream &stream, bool NACK) {
   }
 }
 
-struct __attribute__((packed)) GDBContextDefinition {
+struct FEX_PACKED GDBContextDefinition {
   uint64_t gregs[16];
   uint64_t rip;
   uint32_t eflags;
@@ -232,17 +239,17 @@ std::string GdbServer::readRegs() {
   bool Found = false;
 
   for (auto &Thread : *Threads) {
-    if (Thread->State.ThreadManager.GetTID() != CurrentDebuggingThread) {
+    if (Thread->ThreadManager.GetTID() != CurrentDebuggingThread) {
       continue;
     }
-    state = Thread->State.State;
+    memcpy(&state, Thread->CurrentFrame, sizeof(state));
     Found = true;
     break;
   }
 
   if (!Found) {
     // If set to an invalid thread then just get the parent thread ID
-    state = CTX->GetCPUState();
+    memcpy(&state, CTX->ParentThread->CurrentFrame, sizeof(state));
   }
 
   // Encode the GDB context definition
@@ -272,7 +279,7 @@ std::string GdbServer::readRegs() {
   return encodeHex((unsigned char *)&GDB, sizeof(GDBContextDefinition));
 }
 
-GdbServer::HandledPacketType GdbServer::readReg(std::string& packet) {
+GdbServer::HandledPacketType GdbServer::readReg(const std::string& packet) {
 	size_t addr;
 	auto ss = std::istringstream(packet);
 	ss.get(); // Drop first letter
@@ -284,17 +291,17 @@ GdbServer::HandledPacketType GdbServer::readReg(std::string& packet) {
   bool Found = false;
 
   for (auto &Thread : *Threads) {
-    if (Thread->State.ThreadManager.GetTID() != CurrentDebuggingThread) {
+    if (Thread->ThreadManager.GetTID() != CurrentDebuggingThread) {
       continue;
     }
-    state = Thread->State.State;
+    memcpy(&state, Thread->CurrentFrame, sizeof(state));
     Found = true;
     break;
   }
 
   if (!Found) {
     // If set to an invalid thread then just get the parent thread ID
-    state = CTX->GetCPUState();
+    memcpy(&state, CTX->ParentThread->CurrentFrame, sizeof(state));
   }
 
 
@@ -350,7 +357,7 @@ GdbServer::HandledPacketType GdbServer::readReg(std::string& packet) {
     return {encodeHex((unsigned char *)(&Empty), sizeof(uint32_t)), HandledPacketType::TYPE_ACK};
   }
 
-  LogMan::Msg::E("Unknown GDB register 0x%lx", addr);
+  LogMan::Msg::EFmt("Unknown GDB register 0x{:x}", addr);
   return {"E00", HandledPacketType::TYPE_ACK};
 }
 
@@ -455,7 +462,7 @@ std::string buildTargetXML() {
     return xml.str();
 }
 
-GdbServer::HandledPacketType GdbServer::handleXfer(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
     std::string object;
     std::string rw;
     std::string annex;
@@ -525,7 +532,7 @@ GdbServer::HandledPacketType GdbServer::handleXfer(std::string &packet) {
         ss << "<threads>\n";
         for (size_t i = 0; i < Threads->size(); ++i) {
           auto Thread = Threads->at(i);
-          ss << "\t<thread id=\"" << std::hex << Thread->State.ThreadManager.GetTID() << "\" core=\"" << i << "\" name=\"" <<  getThreadName(Thread->State.ThreadManager.GetTID()) << "\">\n";
+          ss << "\t<thread id=\"" << std::hex << Thread->ThreadManager.GetTID() << "\" core=\"" << i << "\" name=\"" <<  getThreadName(Thread->ThreadManager.GetTID()) << "\">\n";
           ss << "\t</thread>\n";
         }
 
@@ -541,10 +548,9 @@ GdbServer::HandledPacketType GdbServer::handleXfer(std::string &packet) {
 
 static size_t CheckMemMapping(uint64_t Address, size_t Size) {
   uint64_t AddressEnd = Address + Size;
-
-  std::fstream fs;
-  fs.open("/proc/self/maps", std::fstream::in | std::fstream::binary);
+  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
   std::string Line;
+
   while (std::getline(fs, Line)) {
     if (fs.eof()) break;
     uint64_t Begin, End;
@@ -561,32 +567,29 @@ static size_t CheckMemMapping(uint64_t Address, size_t Size) {
     }
   }
 
-  fs.close();
   return 0;
 }
 
 GdbServer::HandledPacketType GdbServer::handleProgramOffsets() {
-  std::fstream fs;
-  fs.open("/proc/self/maps", std::fstream::in | std::fstream::binary);
+  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
   std::string Line;
   std::string const &RuntimeExecutable = Filename();
+
   while (std::getline(fs, Line)) {
     uint64_t Begin, End;
     char Filename[255];
     if (sscanf(Line.c_str(), "%lx-%lx %*c%*c%*c%*c %*x %*x:%*x %*d%s", &Begin, &End, Filename) == 3) {
       if (RuntimeExecutable == Filename) {
-        std::ostringstream ss;
-        ss << "Text=" << std::hex << Begin << ";Data=" << std::hex << Begin << ";Bss=" << std::hex << Begin;
-        ss << std::flush;
-        return {ss.str(), HandledPacketType::TYPE_ACK};
+        auto str = fmt::format("Text={:x};Data={:x};Bss={:x}", Begin, Begin, Begin);
+        return {std::move(str), HandledPacketType::TYPE_ACK};
       }
     }
   }
-  fs.close();
+
   return {"Text=0;Data=0;Bss=0", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::handleMemory(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleMemory(const std::string &packet) {
     bool write;
     size_t addr;
     size_t length;
@@ -627,8 +630,8 @@ GdbServer::HandledPacketType GdbServer::handleMemory(std::string &packet) {
 }
 
 
-GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
-  auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
+GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
+  const auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
 
   if (match("qSupported")) {
     return {"PacketSize=5000;xmlRegisters=i386;qXfer:exec-file:read+;qXfer:features:read+;", HandledPacketType::TYPE_ACK};
@@ -653,7 +656,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
     ss << "m";
     for (size_t i = 0; i < Threads->size(); ++i) {
       auto Thread = Threads->at(i);
-      ss << std::hex << Thread->State.ThreadManager.TID << ",";
+      ss << std::hex << Thread->ThreadManager.TID << ",";
     }
     return {ss.str(), HandledPacketType::TYPE_ACK};
   }
@@ -672,7 +675,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
   if (match("qC")) {
     // Returns the current Thread ID
     std::ostringstream ss;
-    ss << "m" <<  std::hex << CTX->ParentThread->State.ThreadManager.TID;
+    ss << "m" <<  std::hex << CTX->ParentThread->ThreadManager.TID;
     return {ss.str(), HandledPacketType::TYPE_ACK};
   }
   if (match("QStartNoAckMode")) {
@@ -686,8 +689,8 @@ GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
   return {"", HandledPacketType::TYPE_UNKNOWN};
 }
 
-GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
-    auto match = [&](std::string str) -> std::optional<std::istringstream> {
+GdbServer::HandledPacketType GdbServer::handleV(const std::string& packet) {
+    const auto match = [&](const std::string& str) -> std::optional<std::istringstream> {
         if (packet.rfind(str, 0) == 0) {
             auto ss = std::istringstream(packet);
             ss.seekg(str.size());
@@ -696,18 +699,11 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
         return std::nullopt;
     };
 
-    auto F = [](int result) {
-        std::ostringstream ss;
-        ss << "F" << std::hex << result;
-        return ss.str(); };
-    auto F_error = [&]() {
-        std::ostringstream ss;
-        ss << "F-1," << std::hex << errno;
-        return ss.str(); };
-    auto F_data = [&](int result, std::string data) {
-        std::ostringstream ss;
-        ss << "F" << std::hex << result << ";" << data;
-        return ss.str(); };
+    const auto F       = [](int result) { return fmt::format("F{:x}", result); };
+    const auto F_error = [] { return fmt::format("F-1,{:x}", errno); };
+    const auto F_data  = [](int result, const std::string& data) {
+        return fmt::format("F{:x};{}", result, data);
+    };
 
     std::optional<std::istringstream> ss;
     if((ss = match("vFile:open:"))) {
@@ -729,11 +725,11 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
         return {F(pid == 0 ? 0 : -1), HandledPacketType::TYPE_ACK}; // Only support the common filesystem
     }
     if((ss = match("vFile:close:"))) {
-			int fd;
-			*ss >> std::hex >> fd;
-			close(fd);
-			return {F(0), HandledPacketType::TYPE_ACK};
-		}
+      int fd;
+      *ss >> std::hex >> fd;
+      close(fd);
+      return {F(0), HandledPacketType::TYPE_ACK};
+    }
     if((ss = match("vFile:pread:"))) {
         int fd, count, offset;
 
@@ -770,7 +766,7 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
         }
 
         if (ss->fail()) {
- 						return {"E00", HandledPacketType::TYPE_ACK};
+            return {"E00", HandledPacketType::TYPE_ACK};
         }
 
         switch (action) {
@@ -780,27 +776,25 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
           }
         case 's': {
             CTX->Step();
-						SendPacketPair({"OK", HandledPacketType::TYPE_ACK});
-            std::ostringstream ss;
-            ss << "T05thread:" << std::setfill('0') << std::setw(2) << std::hex << getpid() << ";core:2c;";
-
-            SendPacketPair({ss.str(), HandledPacketType::TYPE_ACK});
+            SendPacketPair({"OK", HandledPacketType::TYPE_ACK});
+            auto str = fmt::format("T05thread:{:02x};core:2c;", getpid());
+            SendPacketPair({std::move(str), HandledPacketType::TYPE_ACK});
             return {"OK", HandledPacketType::TYPE_ACK};
           }
         case 't':
             // This thread isn't part of the thread pool
             CTX->Stop(false /* Ignore current thread */);
- 						return {"OK", HandledPacketType::TYPE_ACK};
+            return {"OK", HandledPacketType::TYPE_ACK};
         default:
- 						return {"E00", HandledPacketType::TYPE_ACK};
+            return {"E00", HandledPacketType::TYPE_ACK};
         }
 
     }
-		return {"", HandledPacketType::TYPE_ACK};
+    return {"", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::handleThreadOp(std::string &packet) {
-  auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
+GdbServer::HandledPacketType GdbServer::handleThreadOp(const std::string &packet) {
+  const auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
 
   if (match("Hc")) {
     // Sets thread to this ID for stepping
@@ -816,7 +810,7 @@ GdbServer::HandledPacketType GdbServer::handleThreadOp(std::string &packet) {
   if (match("Hg")) {
     // Sets thread for "other" operations
     auto ss = std::istringstream(packet);
-    ss.seekg(std::string("Hg").size());
+    ss.seekg(std::string_view("Hg").size());
     ss >> std::hex >> CurrentDebuggingThread;
 
     // This must return quick otherwise IDA complains
@@ -827,7 +821,7 @@ GdbServer::HandledPacketType GdbServer::handleThreadOp(std::string &packet) {
   return {"", HandledPacketType::TYPE_UNKNOWN};
 }
 
-GdbServer::HandledPacketType GdbServer::handleBreakpoint(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleBreakpoint(const std::string &packet) {
   auto ss = std::istringstream(packet);
 
   bool Set{};
@@ -843,17 +837,15 @@ GdbServer::HandledPacketType GdbServer::handleBreakpoint(std::string &packet) {
   return {"OK", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::ProcessPacket(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::ProcessPacket(const std::string &packet) {
   switch (packet[0]) {
     case '?': {
       // Indicates the reason that the thread has stopped
       // Behaviour changes if the target is in non-stop mode
       // Binja doesn't support S response here
       //return {"S00", HandledPacketType::TYPE_ACK};
-      std::ostringstream ss;
-      ss << "T00thread:" << std::setfill('0') << std::setw(2) << std::hex << getpid() << ";core:2c;";
-
-      return {ss.str(), HandledPacketType::TYPE_ACK};
+      auto str = fmt::format("T00thread:{:02x};core:2c;", getpid());
+      return {std::move(str), HandledPacketType::TYPE_ACK};
     }
     case 'g':
       return {readRegs(), HandledPacketType::TYPE_ACK};
@@ -883,14 +875,14 @@ GdbServer::HandledPacketType GdbServer::ProcessPacket(std::string &packet) {
   }
 }
 
-void GdbServer::SendPacketPair(HandledPacketType response) {
+void GdbServer::SendPacketPair(const HandledPacketType& response) {
   std::lock_guard lk(sendMutex);
   if (response.TypeResponse == HandledPacketType::TYPE_ACK ||
       response.TypeResponse == HandledPacketType::TYPE_ONLYACK) {
     SendACK(*CommsStream, false);
   }
   else if (response.TypeResponse == HandledPacketType::TYPE_NACK ||
-      response.TypeResponse == HandledPacketType::TYPE_ONLYNACK) {
+           response.TypeResponse == HandledPacketType::TYPE_ONLYNACK) {
     SendACK(*CommsStream, true);
   }
 
@@ -898,8 +890,8 @@ void GdbServer::SendPacketPair(HandledPacketType response) {
     SendPacket(*CommsStream, "");
   }
   else if (response.TypeResponse != HandledPacketType::TYPE_ONLYNACK &&
-      response.TypeResponse != HandledPacketType::TYPE_ONLYACK &&
-      response.TypeResponse != HandledPacketType::TYPE_NONE) {
+           response.TypeResponse != HandledPacketType::TYPE_ONLYACK &&
+           response.TypeResponse != HandledPacketType::TYPE_NONE) {
     SendPacket(*CommsStream, response.Response);
   }
 }
@@ -920,7 +912,7 @@ void GdbServer::GdbServerLoop() {
             response = ProcessPacket(packet);
             SendPacketPair(response);
             if (response.TypeResponse == HandledPacketType::TYPE_UNKNOWN) {
-              LogMan::Msg::D("Unknown packet %s", packet.c_str());
+              LogMan::Msg::DFmt("Unknown packet {}", packet);
             }
             break;
         }
@@ -936,13 +928,12 @@ void GdbServer::GdbServerLoop() {
             break;
         case '\x03': { // ASCII EOT
             CTX->Pause();
-            std::ostringstream ss;
-            ss << "T02thread:" << std::setfill('0') << std::setw(2) << std::hex << getpid() << ";core:2c;";
-            SendPacketPair({ss.str(), HandledPacketType::TYPE_ACK});
+            auto str = fmt::format("T02thread:{:02x};core:2c;", getpid());
+            SendPacketPair({std::move(str), HandledPacketType::TYPE_ACK});
             break;
           }
         default:
-            LogMan::Msg::D("GdbServer: Unexpected byte %c (%02x)", c, c);
+            LogMan::Msg::DFmt("GdbServer: Unexpected byte {} ({:02x})", static_cast<char>(c), c);
         }
     }
 
@@ -952,9 +943,14 @@ void GdbServer::GdbServerLoop() {
     }
   }
 }
+static void* ThreadHandler(void *Arg) {
+  FEXCore::GdbServer *This = reinterpret_cast<FEXCore::GdbServer*>(Arg);
+  This->GdbServerLoop();
+  return nullptr;
+}
 
 void GdbServer::StartThread() {
-    gdbServerThread = std::thread(&GdbServer::GdbServerLoop, this);
+    gdbServerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
 }
 
 std::unique_ptr<std::iostream> GdbServer::OpenSocket() {
@@ -991,7 +987,7 @@ std::unique_ptr<std::iostream> GdbServer::OpenSocket() {
 
     // Block until a connection arrives
 
-    LogMan::Msg::I("GdbServer, waiting for connection on localhost:8086");
+    LogMan::Msg::IFmt("GdbServer, waiting for connection on localhost:8086");
     listen(sockfd, 1);
 
     new_fd = accept(sockfd, (struct sockaddr *)&their_addr, &addr_size);

External/FEXCore/Source/Interface/Core/GdbServer.h

@@ -1,25 +1,36 @@
+/*
+$info$
+tags: glue|gdbserver
+$end_info$
+*/
+#pragma once
 
 #include <mutex>
 #include <thread>
 
 #include "Interface/Context/Context.h"
-
 #include "Common/NetStream.h"
 
+#include <FEXCore/Utils/Threads.h>
+
+#include <mutex>
+
 namespace FEXCore {
 
 class GdbServer {
 public:
     GdbServer(FEXCore::Context::Context *ctx);
 
+    // Public for threading
+    void GdbServerLoop();
+
 private:
     void Break(int signal);
 
     std::unique_ptr<std::iostream> OpenSocket();
     void StartThread();
-    void GdbServerLoop();
     std::string ReadPacket(std::iostream &stream);
-    void SendPacket(std::ostream &stream, std::string packet);
+    void SendPacket(std::ostream &stream, const std::string& packet);
 
     void SendACK(std::ostream &stream, bool NACK);
 
@@ -36,28 +47,28 @@ private:
       ResponseType TypeResponse{};
     };
 
-    void SendPacketPair(HandledPacketType packetPair);
-    HandledPacketType ProcessPacket(std::string &packet);
-    HandledPacketType handleQuery(std::string &packet);
-    HandledPacketType handleXfer(std::string &packet);
-    HandledPacketType handleMemory(std::string &packet);
-    HandledPacketType handleV(std::string& packet);
-    HandledPacketType handleThreadOp(std::string &packet);
-    HandledPacketType handleBreakpoint(std::string &packet);
+    void SendPacketPair(const HandledPacketType& packetPair);
+    HandledPacketType ProcessPacket(const std::string &packet);
+    HandledPacketType handleQuery(const std::string &packet);
+    HandledPacketType handleXfer(const std::string &packet);
+    HandledPacketType handleMemory(const std::string &packet);
+    HandledPacketType handleV(const std::string& packet);
+    HandledPacketType handleThreadOp(const std::string &packet);
+    HandledPacketType handleBreakpoint(const std::string &packet);
     HandledPacketType handleProgramOffsets();
 
     std::string readRegs();
-    HandledPacketType readReg(std::string& packet);
+    HandledPacketType readReg(const std::string& packet);
 
     FEXCore::Context::Context *CTX;
-    std::thread gdbServerThread;
+    std::unique_ptr<FEXCore::Threads::Thread> gdbServerThread;
     std::unique_ptr<std::iostream> CommsStream;
     std::mutex sendMutex;
     bool SettingNoAckMode{false};
     bool NoAckMode{false};
     std::string ThreadString{};
     uint32_t CurrentDebuggingThread{};
-    FEXCore::Config::Value<std::string> Filename{FEXCore::Config::CONFIG_APP_FILENAME, ""};
+    FEX_CONFIG_OPT(Filename, APP_FILENAME);
 };
 
 }

External/FEXCore/Source/Interface/Core/Interpreter/Arm64Dispatcher.cpp

@@ -1,563 +0,0 @@
-#include "Common/MathUtils.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include <FEXCore/Core/X86Enums.h>
-
-#include <cmath>
-
-#include "aarch64/assembler-aarch64.h"
-#include "aarch64/cpu-aarch64.h"
-#include "aarch64/disasm-aarch64.h"
-#include "aarch64/assembler-aarch64.h"
-
-namespace FEXCore::CPU {
-static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  --ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-
-  // Go to sleep
-  Thread->StartRunning.Wait();
-
-  Thread->State.RunningEvents.Running = true;
-  ++ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-}
-
-using namespace vixl;
-using namespace vixl::aarch64;
-
-#define STATE x28
-static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
-
-class DispatchGenerator : public vixl::aarch64::Assembler {
-  public:
-    DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread);
-    bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
-    bool HandleSignalPause(int Signal, void *info, void *ucontext);
-
-  CPUBackend::AsmDispatch DispatchPtr;
-  CPUBackend::JITCallback CallbackPtr;
-
-  uint64_t ThreadStopHandlerAddress;
-  uint64_t AbsoluteLoopTopAddress;
-  uint64_t ThreadPauseHandlerAddress;
-  FEXCore::Context::Context *CTX;
-  FEXCore::Core::InternalThreadState *State;
-  private:
-    void StoreThreadState(int Signal, void *ucontext);
-    void RestoreThreadState(void *ucontext);
-    void PushCalleeSavedRegisters();
-    void PopCalleeSavedRegisters();
-    void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant);
-    std::stack<uint64_t> SignalFrames;
-};
-
-void DispatchGenerator::PushCalleeSavedRegisters() {
-  // We need to save pairs of registers
-  // We save r19-r30
-  MemOperand PairOffset(sp, -16, PreIndex);
-  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
-    {x19, x20},
-    {x21, x22},
-    {x23, x24},
-    {x25, x26},
-    {x27, x28},
-    {x29, x30},
-  }};
-
-  for (auto &RegPair : CalleeSaved) {
-    stp(RegPair.first, RegPair.second, PairOffset);
-  }
-
-  // Additionally we need to store the lower 64bits of v8-v15
-  // Here's a fun thing, we can use two ST4 instructions to store everything
-  // We just need a single sub to sp before that
-  const std::array<
-    std::tuple<vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister>, 2> FPRs = {{
-    {v8, v9, v10, v11},
-    {v12, v13, v14, v15},
-  }};
-
-  uint32_t VectorSaveSize = sizeof(uint64_t) * 8;
-  sub(sp, sp, VectorSaveSize);
-  // SP supporting move
-  // We just saved x19 so it is safe
-  add(x19, sp, 0);
-
-  MemOperand QuadOffset(x19, 32, PostIndex);
-  for (auto &RegQuad : FPRs) {
-    st4(std::get<0>(RegQuad).D(),
-        std::get<1>(RegQuad).D(),
-        std::get<2>(RegQuad).D(),
-        std::get<3>(RegQuad).D(),
-        0,
-        QuadOffset);
-  }
-}
-
-void DispatchGenerator::PopCalleeSavedRegisters() {
-  const std::array<
-    std::tuple<vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister>, 2> FPRs = {{
-    {v12, v13, v14, v15},
-    {v8, v9, v10, v11},
-  }};
-
-  MemOperand QuadOffset(sp, 32, PostIndex);
-  for (auto &RegQuad : FPRs) {
-    ld4(std::get<0>(RegQuad).D(),
-        std::get<1>(RegQuad).D(),
-        std::get<2>(RegQuad).D(),
-        std::get<3>(RegQuad).D(),
-        0,
-        QuadOffset);
-  }
-
-  MemOperand PairOffset(sp, 16, PostIndex);
-  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
-    {x29, x30},
-    {x27, x28},
-    {x25, x26},
-    {x23, x24},
-    {x21, x22},
-    {x19, x20},
-  }};
-
-  for (auto &RegPair : CalleeSaved) {
-    ldp(RegPair.first, RegPair.second, PairOffset);
-  }
-}
-
-void DispatchGenerator::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant) {
-  bool Is64Bit = Reg.IsX();
-  int Segments = Is64Bit ? 4 : 2;
-
-  movz(Reg, (Constant) & 0xFFFF, 0);
-  for (int i = 1; i < Segments; ++i) {
-    uint16_t Part = (Constant >> (i * 16)) & 0xFFFF;
-    if (Part) {
-      movk(Reg, Part, i * 16);
-    }
-  }
-}
-
-DispatchGenerator::DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
-  : vixl::aarch64::Assembler(MAX_DISPATCHER_CODE_SIZE, vixl::aarch64::PositionDependentCode)
-  , CTX {ctx}
-  , State {Thread} {
-
-  SetAllowAssembler(true);
-  auto Buffer = GetBuffer();
-
-  DispatchPtr = Buffer->GetOffsetAddress<CPUBackend::AsmDispatch>(GetCursorOffset());
-
-  // while (!Thread->State.RunningEvents.ShouldStop.load()) {
-  //    Ptr = FindBlock(RIP)
-  //    if (!Ptr)
-  //      Ptr = CTX->CompileBlock(RIP);
-  //
-  //    if (Ptr)
-  //      Ptr();
-  //    else
-  //    {
-  //      Ptr = FallbackCore->CompileBlock()
-  //      if (Ptr)
-  //        Ptr()
-  //      else {
-  //        ShouldStop = true;
-  //      }
-  //    }
-  // }
-
-  // Push all the register we need to save
-  PushCalleeSavedRegisters();
-
-  // Push our memory base to the correct register
-  // Move our thread pointer to the correct register
-  // This is passed in to parameter 0 (x0)
-  mov(STATE, x0);
-
-  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
-  // regardless of where we were in the stack
-  add(x0, sp, 0);
-  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)));
-
-  Label Exit;
-  Label LoopTop;
-  Label NoBlock;
-  Label ThreadPauseHandler;
-  bind(&LoopTop);
-  AbsoluteLoopTopAddress = GetLabelAddress<uint64_t>(&LoopTop);
-
-  // Load in our RIP
-  // Don't modify x2 since it contains our RIP once the block doesn't exist
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, State.rip)));
-  auto RipReg = x2;
-
-  // Mask the address by the virtual address size so we can check for aliases
-  LoadConstant(x3, Thread->LookupCache->GetVirtualMemorySize() - 1);
-  and_(x3, RipReg, x3);
-
-  {
-    // This is the block cache lookup routine
-    // It matches what is going on it LookupCache.h::FindBlock
-    LoadConstant(x0, Thread->LookupCache->GetPagePointer());
-
-    // Offset the address and add to our page pointer
-    lsr(x1, x3, 12);
-
-    // Load the pointer from the offset
-    ldr(x0, MemOperand(x0, x1, Shift::LSL, 3));
-
-    // If page pointer is zero then we have no block
-    cbz(x0, &NoBlock);
-
-    // Steal the page offset
-    and_(x1, x3, 0x0FFF);
-
-    // Shift the offset by the size of the block cache entry
-    add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry))));
-
-    // Load the guest address first to ensure it maps to the address we are currently at
-    // This fixes aliasing problems
-    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)));
-    cmp(x1, RipReg);
-    b(&NoBlock, Condition::ne);
-
-    // Now load the actual host block to execute if we can
-    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)));
-    cbz(x1, &NoBlock);
-
-    // If we've made it here then we have a real compiled block
-    {
-      mov(x0, STATE);
-      blr(x1);
-    }
-
-    if (CTX->GetGdbServerStatus()) {
-      // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
-      // This happens when single stepping
-
-      static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
-      ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, CTX)));
-      ldr(w0, MemOperand(x0, offsetof(FEXCore::Context::Context, Config.RunningMode)));
-      // If the value == 0 then branch to the top
-      cbz(x0, &LoopTop);
-      // Else we need to pause now
-      b(&ThreadPauseHandler);
-    }
-    else {
-      // Unconditionally loop to the top
-      // We will only stop on error when compiling a block or signal
-      b(&LoopTop);
-    }
-  }
-
-  {
-    bind(&Exit);
-    ThreadStopHandlerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-    PopCalleeSavedRegisters();
-
-    // Return from the function
-    // LR is set to the correct return location now
-    ret();
-  }
-
-  // Need to create the block
-  {
-    bind(&NoBlock);
-
-    ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, CTX)));
-    mov(x1, STATE);
-
-    using ClassPtrType = uintptr_t (FEXCore::Context::Context::*)(FEXCore::Core::InternalThreadState *, uint64_t);
-    union PtrCast {
-      ClassPtrType ClassPtr;
-      uintptr_t Data;
-    };
-
-    PtrCast Ptr;
-    Ptr.ClassPtr = &FEXCore::Context::Context::CompileBlock;
-    LoadConstant(x3, Ptr.Data);
-
-    // X2 contains our guest RIP
-    blr(x3); // { CTX, ThreadState, RIP}
-
-    b(&LoopTop);
-  }
-
-  {
-    bind(&ThreadPauseHandler);
-    ThreadPauseHandlerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-    // We are pausing, this means the frontend should be waiting for this thread to idle
-    // We will have faulted and jumped to this location at this point
-
-    // Call our sleep handler
-    LoadConstant(x0, reinterpret_cast<uintptr_t>(CTX));
-    mov(x1, STATE);
-    LoadConstant(x2, reinterpret_cast<uint64_t>(SleepThread));
-    blr(x2);
-
-    // XXX: Unsupported atm
-    //PauseReturnInstruction = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-    //// Fault to start running again
-    //hlt(0);
-  }
-
-  {
-    CallbackPtr = Buffer->GetOffsetAddress<CPUBackend::JITCallback>(GetCursorOffset());
-
-    // We expect the thunk to have previously pushed the registers it was using
-    PushCalleeSavedRegisters();
-
-    // First thing we need to move the thread state pointer back in to our register
-    mov(STATE, x0);
-
-    // Now push the callback return trampoline to the guest stack
-    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
-    LoadConstant(x0, CTX->X86CodeGen.CallbackReturn);
-
-    ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
-    sub(x2, x2, 16);
-    str(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
-
-    // Store the trampoline to the guest stack
-    // Guest stack is now correctly misaligned after a regular call instruction
-    str(x0, MemOperand(x2));
-
-    // Store RIP to the context state
-    str(x1, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.rip)));
-
-    // Now go back to the regular dispatcher loop
-    b(&LoopTop);
-  }
-
-  FinalizeCode();
-  uint64_t CodeEnd = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(reinterpret_cast<void*>(DispatchPtr), CodeEnd - reinterpret_cast<uint64_t>(DispatchPtr));
-  GetBuffer()->SetExecutable();
-}
-
-
-struct HostCTXHeader {
-  uint32_t Magic;
-  uint32_t Size;
-};
-
-constexpr uint32_t FPR_MAGIC = 0x46508001U;
-
-struct HostFPRState {
-  HostCTXHeader Head;
-  uint32_t FPSR;
-  uint32_t FPCR;
-  __uint128_t FPRs[32];
-};
-
-struct ContextBackup {
-  // Host State
-  uint64_t GPRs[31];
-  uint64_t PrevSP;
-  uint64_t PrevPC;
-  uint64_t PState;
-  uint32_t FPSR;
-  uint32_t FPCR;
-  __uint128_t FPRs[32];
-
-  // Guest state
-  int Signal;
-  FEXCore::Core::CPUState GuestState;
-};
-
-void DispatchGenerator::StoreThreadState(int Signal, void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  // We can end up getting a signal at any point in our host state
-  // Jump to a handler that saves all state so we can safely return
-  uint64_t OldSP = _mcontext->sp;
-  uintptr_t NewSP = OldSP;
-
-  size_t StackOffset = sizeof(ContextBackup);
-  NewSP -= StackOffset;
-  NewSP = AlignDown(NewSP, 16);
-
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-  memcpy(&Context->GPRs[0], &_mcontext->regs[0], 31 * sizeof(uint64_t));
-  Context->PrevSP = _mcontext->sp;
-  Context->PrevPC = _mcontext->pc;
-  Context->PState = _mcontext->pstate;
-
-  // Host FPR state starts at _mcontext->reserved[0];
-  HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
-  LogMan::Throw::A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
-  Context->FPSR = HostState->FPSR;
-  Context->FPCR = HostState->FPCR;
-  memcpy(&Context->FPRs[0], &HostState->FPRs[0], 32 * sizeof(__uint128_t));
-
-  // Retain the action pointer so we can see it when we return
-  Context->Signal = Signal;
-
-  // Save guest state
-  // We can't guarantee if registers are in context or host GPRs
-  // So we need to save everything
-  memcpy(&Context->GuestState, &State->State, sizeof(FEXCore::Core::CPUState));
-
-  // Set the new SP
-  _mcontext->sp = NewSP;
-}
-
-void DispatchGenerator::RestoreThreadState(void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  uint64_t OldSP = _mcontext->sp;
-  uintptr_t NewSP = OldSP;
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-
-  // First thing, reset the guest state
-  memcpy(&State->State, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
-
-  // Now restore host state
-  HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
-  LogMan::Throw::A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
-  memcpy(&HostState->FPRs[0], &Context->FPRs[0], 32 * sizeof(__uint128_t));
-  Context->FPCR = HostState->FPCR;
-  Context->FPSR = HostState->FPSR;
-
-  // Restore GPRs and other state
-  _mcontext->pstate = Context->PState;
-  _mcontext->pc = Context->PrevPC;
-  _mcontext->sp = Context->PrevSP;
-  memcpy(&_mcontext->regs[0], &Context->GPRs[0], 31 * sizeof(uint64_t));
-
-  // Restore the previous signal state
-  // This allows recursive signals to properly handle signal masking as we are walking back up the list of signals
-  CTX->SignalDelegation->SetCurrentSignal(Context->Signal);
-}
-
-bool DispatchGenerator::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  StoreThreadState(Signal, ucontext);
-
-  // Set the new PC
-  _mcontext->pc = AbsoluteLoopTopAddress;
-  // Set x28 (which is our state register) to point to our guest thread data
-  _mcontext->regs[28 /* STATE */] = reinterpret_cast<uint64_t>(State);
-
-  State->State.State.gregs[X86State::REG_RDI] = Signal;
-  uint64_t OldGuestSP = State->State.State.gregs[X86State::REG_RSP];
-  uint64_t NewGuestSP = OldGuestSP;
-
-  if (!(GuestStack->ss_flags & SS_DISABLE)) {
-    // If our guest is already inside of the alternative stack
-    // Then that means we are hitting recursive signals and we need to walk back the stack correctly
-    uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
-    uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
-    if (OldGuestSP >= AltStackBase &&
-        OldGuestSP <= AltStackEnd) {
-      // We are already in the alt stack, the rest of the code will handle adjusting this
-    }
-    else {
-      NewGuestSP = AltStackEnd;
-    }
-  }
-
-  // Back up past the redzone, which is 128bytes
-  // Don't need this offset if we aren't going to be putting siginfo in to it
-  NewGuestSP -= 128;
-
-  if (GuestAction->sa_flags & SA_SIGINFO) {
-    // XXX: siginfo_t(RSI), ucontext (RDX)
-    State->State.State.gregs[X86State::REG_RSI] = 0;
-    State->State.State.gregs[X86State::REG_RDX] = 0;
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
-  }
-  else {
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
-  }
-
-  // Set up the new SP for stack handling
-  NewGuestSP -= 8;
-  *(uint64_t*)NewGuestSP = CTX->X86CodeGen.SignalReturn;
-  State->State.State.gregs[X86State::REG_RSP] = NewGuestSP;
-
-  return true;
-}
-
-bool DispatchGenerator::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  FEXCore::Core::SignalEvent SignalReason = State->SignalReason.load();
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_PAUSE) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Store our thread state so we can come back to this
-    StoreThreadState(Signal, ucontext);
-
-    // Set the new PC
-    _mcontext->pc = ThreadPauseHandlerAddress;
-
-    // Set our state register to point to our guest thread data
-    _mcontext->regs[28 /* STATE */] = reinterpret_cast<uint64_t>(State);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_RETURN) {
-    RestoreThreadState(ucontext);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_STOP) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Our thread is stopping
-    // We don't care about anything at this point
-    // Set the stack to our starting location when we entered the JIT and get out safely
-    _mcontext->sp = State->State.ReturningStackLocation;
-
-    // Set the new PC
-    _mcontext->pc = ThreadStopHandlerAddress;
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  return false;
-}
-
-void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  Generator = new DispatchGenerator(ctx, Thread);
-  DispatchPtr = Generator->DispatchPtr;
-  CallbackPtr = Generator->CallbackPtr;
-
-  // TODO: Implement this. It is missing from the dispatcher
-  // TODO: It feels wrong to initialize this way
-  ctx->InterpreterCallbackReturn = nullptr;
-}
-
-bool InterpreterCore::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
-}
-
-bool InterpreterCore::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleSignalPause(Signal, info, ucontext);
-}
-
-void InterpreterCore::DeleteAsmDispatch() {
-  delete Generator;
-}
-
-}

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterClass.h

@@ -2,13 +2,15 @@
 
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/InternalThreadState.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
 
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 
 namespace FEXCore::CPU {
-class DispatchGenerator;
+class X86DispatchGenerator;
+class Arm64DispatchGenerator;
 
 #define DESTMAP_AS_MAP 0
 #if DESTMAP_AS_MAP
@@ -20,16 +22,14 @@ using DestMapType = std::vector<uint32_t>;
 class InterpreterCore final : public CPUBackend {
 public:
   explicit InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
-  ~InterpreterCore() override;
   std::string GetName() override { return "Interpreter"; }
-  void *CompileCode(FEXCore::IR::IRListView<true> const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
+  void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
 
   void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
 
   bool NeedsOpDispatch() override { return true; }
 
   void CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread);
-  void DeleteAsmDispatch();
 
   bool HandleSIGBUS(int Signal, void *info, void *ucontext);
 
@@ -38,8 +38,6 @@ private:
   FEXCore::Core::InternalThreadState *State;
 
   uint32_t AllocateTmpSpace(size_t Size);
-  bool HandleSignalPause(int Signal, void *info, void *ucontext);
-  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
 
   template<typename Res>
   Res GetDest(void* SSAData, IR::OrderedNodeWrapper Op);
@@ -47,7 +45,7 @@ private:
   template<typename Res>
   Res GetSrc(void* SSAData, IR::OrderedNodeWrapper Src);
 
-  DispatchGenerator *Generator{};
+  std::unique_ptr<Dispatcher> Dispatcher{};
 };
 
 }

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp

@@ -2,9 +2,8 @@
 #include "Common/SoftFloat.h"
 #include "Interface/Context/Context.h"
 
-#ifdef _M_ARM_64
 #include "Interface/Core/ArchHelpers/Arm64.h"
-#endif
+#include "Interface/Core/ArchHelpers/MContext.h"
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/DebugData.h"
 #include "Interface/Core/InternalThreadState.h"
@@ -22,57 +21,64 @@
 #include <cmath>
 #include <limits>
 #include <vector>
-#ifdef _M_X86_64
-#include <xmmintrin.h>
-#endif
 
 #include "InterpreterOps.h"
 
 namespace FEXCore::CPU {
 
-static void InterpreterExecution(FEXCore::Core::InternalThreadState *Thread) {
-  auto IR = Thread->IRLists.find(Thread->State.State.rip)->second.get();
-  
-  FEXCore::Core::DebugData *DebugData = nullptr;
-  
-  // DebugData is only used in debug builds
-  #ifndef NDEBUG
-  DebugData = Thread->DebugData.find(Thread->State.State.rip)->second.get();
-  #endif
+static void InterpreterExecution(FEXCore::Core::CpuStateFrame *Frame) {
+  auto Thread = Frame->Thread;
 
-  InterpreterOps::InterpretIR(Thread, IR, DebugData);
+  auto LocalEntry = Thread->LocalIRCache.find(Thread->CurrentFrame->State.rip);
+
+  InterpreterOps::InterpretIR(Thread, Thread->CurrentFrame->State.rip, LocalEntry->second.IR.get(), LocalEntry->second.DebugData.get());
 }
 
-
 bool InterpreterCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
 #ifdef _M_ARM_64
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-  uint32_t *PC = (uint32_t*)_mcontext->pc;
-  uint32_t Instr = PC[0];
-  if ((Instr & FEXCore::ArchHelpers::Arm64::CASPAL_MASK) == FEXCore::ArchHelpers::Arm64::CASPAL_INST) { // CASPAL
-    if (FEXCore::ArchHelpers::Arm64::HandleCASPAL(_mcontext, info, Instr)) {
-      // Skip this instruction now
-      _mcontext->pc += 4;
-      return true;
-    }
-    else {
-      LogMan::Msg::E("Unhandled JIT SIGBUS CASPAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
-      return false;
-    }
-  }
-  else if ((Instr & FEXCore::ArchHelpers::Arm64::CASAL_MASK) == FEXCore::ArchHelpers::Arm64::CASAL_INST) { // CASAL
-    if (FEXCore::ArchHelpers::Arm64::HandleCASAL(_mcontext, info, Instr)) {
-      // Skip this instruction now
-      _mcontext->pc += 4;
-      return true;
-    }
-    else {
-      LogMan::Msg::E("Unhandled JIT SIGBUS CASAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
-      return false;
-    }
-  }
+  constexpr bool is_arm64 = true;
+#else
+  constexpr bool is_arm64 = false;
 #endif
+
+  if constexpr (is_arm64) {
+    uint32_t *PC = reinterpret_cast<uint32_t*>(ArchHelpers::Context::GetPc(ucontext));
+    uint32_t Instr = PC[0];
+    if ((Instr & FEXCore::ArchHelpers::Arm64::CASPAL_MASK) == FEXCore::ArchHelpers::Arm64::CASPAL_INST) { // CASPAL
+      if (FEXCore::ArchHelpers::Arm64::HandleCASPAL(ucontext, info, Instr)) {
+        // Skip this instruction now
+        ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + 4);
+        return true;
+      }
+      else {
+        LogMan::Msg::E("Unhandled JIT SIGBUS CASPAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
+        return false;
+      }
+    }
+    else if ((Instr & FEXCore::ArchHelpers::Arm64::CASAL_MASK) == FEXCore::ArchHelpers::Arm64::CASAL_INST) { // CASAL
+      if (FEXCore::ArchHelpers::Arm64::HandleCASAL(ucontext, info, Instr)) {
+        // Skip this instruction now
+        ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + 4);
+        return true;
+      }
+      else {
+        LogMan::Msg::E("Unhandled JIT SIGBUS CASAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
+        return false;
+      }
+    }
+    else if ((Instr & FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_MASK) == FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_INST) { // Atomic memory op
+      if (FEXCore::ArchHelpers::Arm64::HandleAtomicMemOp(ucontext, info, Instr)) {
+        // Skip this instruction now
+        ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + 4);
+        return true;
+      }
+      else {
+        uint8_t Op = (PC[0] >> 12) & 0xF;
+        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x: PC: %p Instruction: 0x%08x\n", Op, PC, PC[0]);
+        return false;
+      }
+    }
+  }
   return false;
 }
 
@@ -86,7 +92,7 @@ InterpreterCore::InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::
     CreateAsmDispatch(ctx, Thread);
     CTX->SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
       InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
-      return Core->HandleSignalPause(Signal, info, ucontext);
+      return Core->Dispatcher->HandleSignalPause(Signal, info, ucontext);
     });
 
     CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
@@ -96,7 +102,7 @@ InterpreterCore::InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::
 
     auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
       InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
-      return Core->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
+      return Core->Dispatcher->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
     };
 
     for (uint32_t Signal = 0; Signal < SignalDelegator::MAX_SIGNALS; ++Signal) {
@@ -105,18 +111,12 @@ InterpreterCore::InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::
   }
 }
 
-
-InterpreterCore::~InterpreterCore() {
-  DeleteAsmDispatch();
-}
-
-
-void *InterpreterCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
+void *InterpreterCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
   return reinterpret_cast<void*>(InterpreterExecution);
 }
 
-FEXCore::CPU::CPUBackend *CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread) {
-  return new InterpreterCore(ctx, Thread, CompileThread);
+std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread) {
+  return std::make_unique<InterpreterCore>(ctx, Thread, CompileThread);
 }
 
 }

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.h

@@ -1,5 +1,7 @@
 #pragma once
 
+#include <memory>
+
 namespace FEXCore::Context {
 struct Context;
 }
@@ -11,6 +13,6 @@ namespace FEXCore::Core {
 namespace FEXCore::CPU {
 class CPUBackend;
 
-FEXCore::CPU::CPUBackend *CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
+std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
 
 }

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h

@@ -1,19 +1,42 @@
 namespace FEXCore::Core {
-    struct InternalThreadState;
+  struct InternalThreadState;
 }
 
 namespace FEXCore::IR {
-    template<bool copy>
     class IRListView;
 }
 
 namespace FEXCore::Core{
-    struct DebugData;
+  struct DebugData;
 }
 
 namespace FEXCore::CPU {
-    class InterpreterOps {
-        public:
-        static void InterpretIR(FEXCore::Core::InternalThreadState *Thread, FEXCore::IR::IRListView<true> *CurrentIR, FEXCore::Core::DebugData *DebugData);
-    };
+  enum FallbackABI {
+    FABI_UNKNOWN,
+    FABI_VOID_U16,
+    FABI_F80_F32,
+    FABI_F80_F64,
+    FABI_F80_I16,
+    FABI_F80_I32,
+    FABI_F32_F80,
+    FABI_F64_F80,
+    FABI_I16_F80,
+    FABI_I32_F80,
+    FABI_I64_F80,
+    FABI_I64_F80_F80,
+    FABI_F80_F80,
+    FABI_F80_F80_F80,
+  };
+
+  struct FallbackInfo {
+    FallbackABI ABI;
+    void *fn;
+  };
+  
+  class InterpreterOps {
+
+    public:
+      static void InterpretIR(FEXCore::Core::InternalThreadState *Thread, uint64_t Entry, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData);
+      static bool GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Info);
+  };
 };

External/FEXCore/Source/Interface/Core/Interpreter/x86_64Dispatcher.cpp

@@ -1,470 +0,0 @@
-#include "Common/MathUtils.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Context/Context.h"
-#include <FEXCore/Core/X86Enums.h>
-
-#include <cmath>
-#include <xbyak/xbyak.h>
-
-namespace FEXCore::CPU {
-static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
-#define STATE r14
-
-class DispatchGenerator : public Xbyak::CodeGenerator {
-  public:
-    DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread);
-    bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
-    bool HandleSignalPause(int Signal, void *info, void *ucontext);
-
-  CPUBackend::AsmDispatch DispatchPtr;
-  CPUBackend::JITCallback CallbackPtr;
-  FEXCore::Context::Context::IntCallbackReturn ReturnPtr;
-
-  uint64_t ThreadStopHandlerAddress;
-  uint64_t AbsoluteLoopTopAddress;
-  uint64_t ThreadPauseHandlerAddress;
-  FEXCore::Context::Context *CTX;
-  FEXCore::Core::InternalThreadState *State;
-  private:
-    void StoreThreadState(int Signal, void *ucontext);
-    void RestoreThreadState(void *ucontext);
-    std::stack<uint64_t> SignalFrames;
-};
-
-static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  --ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-
-  // Go to sleep
-  Thread->StartRunning.Wait();
-
-  Thread->State.RunningEvents.Running = true;
-  ++ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-}
-
-DispatchGenerator::DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
-  : Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE)
-  , CTX {ctx}
-  , State {Thread} {
-  using namespace Xbyak;
-  using namespace Xbyak::util;
-  DispatchPtr = getCurr<CPUBackend::AsmDispatch>();
-
-  // while (!Thread->State.RunningEvents.ShouldStop.load()) {
-  //    Ptr = FindBlock(RIP)
-  //    if (!Ptr)
-  //      Ptr = CTX->CompileBlock(RIP);
-  //
-  //    if (Ptr)
-  //      Ptr();
-  //    else
-  //    {
-  //      Ptr = FallbackCore->CompileBlock()
-  //      if (Ptr)
-  //        Ptr()
-  //      else {
-  //        ShouldStop = true;
-  //      }
-  //    }
-  // }
-  // Bunch of exit state stuff
-
-  // x86-64 ABI has the stack aligned when /call/ happens
-  // Which means the destination has a misaligned stack at that point
-  push(rbx);
-  push(rbp);
-  push(r12);
-  push(r13);
-  push(r14);
-  push(r15);
-  sub(rsp, 8);
-
-  mov(STATE, rdi);
-
-  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
-  // regardless of where we were in the stack
-  mov(qword [rdi + offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)], rsp);
-
-  Label LoopTop;
-  Label NoBlock;
-  Label ExitBlock;
-  Label ThreadPauseHandler;
-
-  L(LoopTop);
-  AbsoluteLoopTopAddress = getCurr<uint64_t>();
-
-  {
-    mov(r13, Thread->LookupCache->GetPagePointer());
-
-    // Load our RIP
-    mov(rdx, qword [STATE + offsetof(FEXCore::Core::CPUState, rip)]);
-
-    mov(rax, rdx);
-    mov(rbx, Thread->LookupCache->GetVirtualMemorySize() - 1);
-    and_(rax, rbx);
-    shr(rax, 12);
-
-    // Load page pointer
-    mov(rdi, qword [r13 + rax * 8]);
-
-    cmp(rdi, 0);
-    je(NoBlock);
-
-    mov (rax, rdx);
-    and_(rax, 0x0FFF);
-
-    shl(rax, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
-
-    // check for aliasing
-    mov(rcx, qword [rdi + rax + 8]);
-    cmp(rcx, rdx);
-    jne(NoBlock);
-    
-    // Load the block pointer
-    mov(rax, qword [rdi + rax]);
-
-    cmp(rax, 0);
-    je(NoBlock);
-
-    // Real block if we made it here
-    mov(rdi, STATE);
-    call(rax);
-
-    if (CTX->GetGdbServerStatus()) {
-      // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
-      // This happens when single stepping
-      static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
-      mov(rax, qword [STATE + (offsetof(FEXCore::Core::InternalThreadState, CTX))]);
-
-      // If the value == 0 then branch to the top
-      cmp(dword [rax + (offsetof(FEXCore::Context::Context, Config.RunningMode))], 0);
-      je(LoopTop);
-      // Else we need to pause now
-      jmp(ThreadPauseHandler);
-      ud2();
-    }
-    else {
-      jmp(LoopTop);
-    }
-  }
-
-  {
-    L(ExitBlock);
-    ThreadStopHandlerAddress = getCurr<uint64_t>();
-
-    add(rsp, 8);
-
-    pop(r15);
-    pop(r14);
-    pop(r13);
-    pop(r12);
-    pop(rbp);
-    pop(rbx);
-
-    ret();
-  }
-
-  // Block creation
-  {
-    L(NoBlock);
-
-    using ClassPtrType = uintptr_t (FEXCore::Context::Context::*)(FEXCore::Core::InternalThreadState *, uint64_t);
-    union PtrCast {
-      ClassPtrType ClassPtr;
-      uintptr_t Data;
-    };
-
-    PtrCast Ptr;
-    Ptr.ClassPtr = &FEXCore::Context::Context::CompileBlock;
-
-    // {rdi, rsi, rdx}
-    mov(rdi, reinterpret_cast<uint64_t>(CTX));
-    mov(rsi, STATE);
-    mov(rax, Ptr.Data);
-
-    call(rax);
-
-    // rdx already contains RIP here
-    jmp(LoopTop);
-  }
-
-  {
-    // Pause handler
-    ThreadPauseHandlerAddress = getCurr<uint64_t>();
-    L(ThreadPauseHandler);
-
-    mov(rdi, reinterpret_cast<uintptr_t>(CTX));
-    mov(rsi, STATE);
-    mov(rax, reinterpret_cast<uint64_t>(SleepThread));
-
-    call(rax);
-
-    // XXX: Unsupported atm
-    // uint64_t PauseReturnInstruction = getCurr<uint64_t>();
-    // ud2();
-  }
-
-  {
-    CallbackPtr = getCurr<CPUBackend::JITCallback>();
-
-    push(rbx);
-    push(rbp);
-    push(r12);
-    push(r13);
-    push(r14);
-    push(r15);
-    sub(rsp, 8);
-
-    // First thing we need to move the thread state pointer back in to our register
-    mov(STATE, rdi);
-    // XXX: XMM?
-
-    // Now push the callback return trampoline to the guest stack
-    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
-    mov(rax, CTX->X86CodeGen.CallbackReturn);
-
-    // Store the trampoline to the guest stack
-    // Guest stack is now correctly misaligned after a regular call instruction
-    sub(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])], 16);
-    mov(rbx, qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])]);
-    mov(qword [rbx], rax);
-
-    // Store RIP to the context state
-    mov(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.rip)], rsi);
-
-    // Back to the loop top now
-    jmp(LoopTop);
-  }
-
-
-  {
-    ReturnPtr = getCurr<FEXCore::Context::Context::IntCallbackReturn>();
-//  using CallbackReturn =  __attribute__((naked)) void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
-
-    // rdi = thread
-    // rsi = rsp
-
-    mov(rsp, rsi);
-
-    // Now jump back to the thunk
-    // XXX: XMM?
-    add(rsp, 8);
-
-    pop(r15);
-    pop(r14);
-    pop(r13);
-    pop(r12);
-    pop(rbp);
-    pop(rbx);
-
-    ret();
-  }
-  ready();
-}
-
-struct ContextBackup {
-  uint64_t StoredCookie;
-  // Host State
-  // RIP and RSP is stored in GPRs here
-  uint64_t GPRs[NGREG];
-  _libc_fpstate FPRState;
-
-  // Guest state
-  int Signal;
-  FEXCore::Core::CPUState GuestState;
-};
-
-void DispatchGenerator::StoreThreadState(int Signal, void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  // We can end up getting a signal at any point in our host state
-  // Jump to a handler that saves all state so we can safely return
-  uint64_t OldSP = _mcontext->gregs[REG_RSP];
-  uintptr_t NewSP = OldSP;
-
-  size_t StackOffset = sizeof(ContextBackup);
-
-  // We need to back up behind the host's red zone
-  // We do this on the guest side as well
-  NewSP -= 128;
-  NewSP -= StackOffset;
-  NewSP = AlignDown(NewSP, 16);
-
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-
-  Context->StoredCookie = 0x4142434445464748ULL;
-
-  // Copy the GPRs
-  memcpy(&Context->GPRs[0], &_mcontext->gregs[0], NGREG * sizeof(_mcontext->gregs[0]));
-  // Copy the FPRState
-  memcpy(&Context->FPRState, _mcontext->fpregs, sizeof(_libc_fpstate));
-
-  // XXX: Save 256bit and 512bit AVX register state
-
-  // Retain the action pointer so we can see it when we return
-  Context->Signal = Signal;
-
-  // Save guest state
-  // We can't guarantee if registers are in context or host GPRs
-  // So we need to save everything
-  memcpy(&Context->GuestState, &State->State, sizeof(FEXCore::Core::CPUState));
-
-  // Set the new SP
-  _mcontext->gregs[REG_RSP] = NewSP;
-
-  SignalFrames.push(NewSP);
-}
-
-void DispatchGenerator::RestoreThreadState(void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  uint64_t OldSP = SignalFrames.top();
-  SignalFrames.pop();
-  uintptr_t NewSP = OldSP;
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-
-  if (Context->StoredCookie != 0x4142434445464748ULL) {
-    LogMan::Msg::D("COOKIE WAS NOT CORRECT!\n");
-    exit(-1);
-  }
-
-  // First thing, reset the guest state
-  memcpy(&State->State, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
-
-  // Now restore host state
-
-  // Copy the GPRs
-  memcpy(&_mcontext->gregs[0], &Context->GPRs[0], NGREG * sizeof(_mcontext->gregs[0]));
-  // Copy the FPRState
-  memcpy(_mcontext->fpregs, &Context->FPRState, sizeof(_libc_fpstate));
-
-  // Restore the previous signal state
-  // This allows recursive signals to properly handle signal masking as we are walking back up the list of signals
-  CTX->SignalDelegation->SetCurrentSignal(Context->Signal);
-}
-
-bool DispatchGenerator::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  StoreThreadState(Signal, ucontext);
-
-  // Set the new PC
-  _mcontext->gregs[REG_RIP] = AbsoluteLoopTopAddress;
-  // Set our state register to point to our guest thread data
-  _mcontext->gregs[REG_R14] = reinterpret_cast<uint64_t>(State);
-
-  uint64_t OldGuestSP = State->State.State.gregs[X86State::REG_RSP];
-  uint64_t NewGuestSP = OldGuestSP;
-
-  if (!(GuestStack->ss_flags & SS_DISABLE)) {
-    // If our guest is already inside of the alternative stack
-    // Then that means we are hitting recursive signals and we need to walk back the stack correctly
-    uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
-    uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
-    if (OldGuestSP >= AltStackBase &&
-        OldGuestSP <= AltStackEnd) {
-      // We are already in the alt stack, the rest of the code will handle adjusting this
-    }
-    else {
-      NewGuestSP = AltStackEnd;
-    }
-  }
-
-  // Back up past the redzone, which is 128bytes
-  // Don't need this offset if we aren't going to be putting siginfo in to it
-  NewGuestSP -= 128;
-
-  State->State.State.gregs[X86State::REG_RDI] = Signal;
-
-  if (GuestAction->sa_flags & SA_SIGINFO) {
-    // XXX: siginfo_t(RSI), ucontext (RDX)
-    State->State.State.gregs[X86State::REG_RSI] = 0;
-    State->State.State.gregs[X86State::REG_RDX] = 0;
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
-  }
-  else {
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
-  }
-
-  // Set up the new SP for stack handling
-  NewGuestSP -= 8;
-  *(uint64_t*)NewGuestSP = CTX->X86CodeGen.SignalReturn;
-  State->State.State.gregs[X86State::REG_RSP] = NewGuestSP;
-
-  return true;
-}
-
-bool DispatchGenerator::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  FEXCore::Core::SignalEvent SignalReason = State->SignalReason.load();
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_PAUSE) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Store our thread state so we can come back to this
-    StoreThreadState(Signal, ucontext);
-
-    // Set the new PC
-    _mcontext->gregs[REG_RIP] = ThreadPauseHandlerAddress;
-
-    // Set our state register to point to our guest thread data
-    _mcontext->gregs[REG_R14] = reinterpret_cast<uint64_t>(State);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_STOP) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Our thread is stopping
-    // We don't care about anything at this point
-    // Set the stack to our starting location when we entered the core and get out safely
-    _mcontext->gregs[REG_RSP] = State->State.ReturningStackLocation;
-
-    // Set the new PC
-    _mcontext->gregs[REG_RIP] = ThreadStopHandlerAddress;
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_RETURN) {
-    RestoreThreadState(ucontext);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  return false;
-}
-
-void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  Generator = new DispatchGenerator(ctx, Thread);
-  DispatchPtr = Generator->DispatchPtr;
-  CallbackPtr = Generator->CallbackPtr;
-
-  // TODO: It feels wrong to initialize this way
-  ctx->InterpreterCallbackReturn = Generator->ReturnPtr;
-}
-
-bool InterpreterCore::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
-}
-
-bool InterpreterCore::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleSignalPause(Signal, info, ucontext);
-}
-
-void InterpreterCore::DeleteAsmDispatch() {
-  delete Generator;
-}
-
-}

External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp

@@ -1,3 +1,8 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
 
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
@@ -29,7 +34,7 @@ static int64_t LREM(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(TruncElementPair) {
   auto Op = IROp->C<IR::IROp_TruncElementPair>();
 
@@ -41,7 +46,7 @@ DEF_OP(TruncElementPair) {
       mov(Dst.second, Src.second);
       break;
     }
-    default: LogMan::Msg::A("Unhandled Truncation size: %d", Op->Size); break;
+    default: LOGMAN_MSG_A("Unhandled Truncation size: %d", Op->Size); break;
   }
 }
 
@@ -51,10 +56,22 @@ DEF_OP(Constant) {
   LoadConstant(Dst, Op->Constant);
 }
 
+DEF_OP(EntrypointOffset) {
+  auto Op = IROp->C<IR::IROp_EntrypointOffset>();
+
+  auto Constant = Entry + Op->Offset;
+  auto Dst = GetReg<RA_64>(Node);
+  LoadConstant(Dst, Constant);
+}
+
 DEF_OP(InlineConstant) {
   //nop
 }
 
+DEF_OP(InlineEntrypointOffset) {
+  //nop
+}
+
 DEF_OP(CycleCounter) {
 #ifdef DEBUG_CYCLES
   movz(GetReg<RA_64>(Node), 0);
@@ -78,7 +95,7 @@ DEF_OP(Add) {
       case 8:
         add(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), Const);
         break;
-      default: LogMan::Msg::A("Unsupported Add size: %d", OpSize);
+      default: LOGMAN_MSG_A("Unsupported Add size: %d", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -88,7 +105,7 @@ DEF_OP(Add) {
       case 8:
         add(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
         break;
-      default: LogMan::Msg::A("Unsupported Add size: %d", OpSize);
+      default: LOGMAN_MSG_A("Unsupported Add size: %d", OpSize);
     }
   }
 }
@@ -104,7 +121,7 @@ DEF_OP(Sub) {
       case 8:
         sub(GRS(Node), GRS(Op->Header.Args[0].ID()), Const);
         break;
-      default: LogMan::Msg::A("Unsupported Sub size: %d", OpSize);
+      default: LOGMAN_MSG_A("Unsupported Sub size: %d", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -114,7 +131,7 @@ DEF_OP(Sub) {
       case 8:
         sub(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
         break;
-      default: LogMan::Msg::A("Unsupported Sub size: %d", OpSize);
+      default: LOGMAN_MSG_A("Unsupported Sub size: %d", OpSize);
     }
   }
 
@@ -130,7 +147,7 @@ DEF_OP(Neg) {
     case 8:
       neg(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unsupported Not size: %d", OpSize);
+    default: LOGMAN_MSG_A("Unsupported Not size: %d", OpSize);
   }
 }
 
@@ -142,12 +159,11 @@ DEF_OP(Mul) {
   switch (OpSize) {
     case 4:
       mul(Dst.W(), GetReg<RA_32>(Op->Header.Args[0].ID()), GetReg<RA_32>(Op->Header.Args[1].ID()));
-      sxtw(Dst, Dst);
     break;
     case 8:
       mul(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
   }
 }
 
@@ -163,7 +179,7 @@ DEF_OP(UMul) {
     case 8:
       mul(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
   }
 }
 
@@ -200,7 +216,7 @@ DEF_OP(Div) {
       sdiv(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
     }
-    default: LogMan::Msg::A("Unknown DIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A("Unknown DIV Size: %d", Size); break;
   }
 }
 
@@ -227,7 +243,7 @@ DEF_OP(UDiv) {
       udiv(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
       break;
     }
-    default: LogMan::Msg::A("Unknown UDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A("Unknown UDIV Size: %d", Size); break;
   }
 }
 
@@ -274,7 +290,7 @@ DEF_OP(Rem) {
       msub(GetReg<RA_64>(Node), TMP1, Divisor, Dividend);
     break;
     }
-    default: LogMan::Msg::A("Unknown REM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown REM Size: %d", OpSize); break;
   }
 }
 
@@ -316,7 +332,7 @@ DEF_OP(URem) {
       msub(GetReg<RA_64>(Node), TMP1, Divisor, Dividend);
     break;
     }
-    default: LogMan::Msg::A("Unknown UREM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown UREM Size: %d", OpSize); break;
   }
 }
 
@@ -328,12 +344,12 @@ DEF_OP(MulH) {
       sxtw(TMP1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       sxtw(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
       mul(TMP1, TMP1, TMP2);
-      sbfx(GetReg<RA_64>(Node), TMP1, 32, 32);
+      ubfx(GetReg<RA_64>(Node), TMP1, 32, 32);
     break;
     case 8:
       smulh(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
   }
 }
 
@@ -350,7 +366,7 @@ DEF_OP(UMulH) {
     case 8:
       umulh(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
   }
 }
 
@@ -386,7 +402,6 @@ DEF_OP(Xor) {
 
 DEF_OP(Lshl) {
   auto Op = IROp->C<IR::IROp_Lshl>();
-  uint8_t OpSize = IROp->Size;
   uint64_t Const;
   if (IsInlineConstant(Op->Header.Args[1], &Const)) {
     lsl(GRS(Node), GRS(Op->Header.Args[0].ID()), (unsigned int)Const);
@@ -397,7 +412,6 @@ DEF_OP(Lshl) {
 
 DEF_OP(Lshr) {
   auto Op = IROp->C<IR::IROp_Lshr>();
-  uint8_t OpSize = IROp->Size;
   uint64_t Const;
   if (IsInlineConstant(Op->Header.Args[1], &Const)) {
     lsr(GRS(Node), GRS(Op->Header.Args[0].ID()), (unsigned int)Const);
@@ -448,7 +462,7 @@ DEF_OP(Ror) {
       break;
       }
 
-      default: LogMan::Msg::A("Unhandled ROR size: %d", OpSize);
+      default: LOGMAN_MSG_A("Unhandled ROR size: %d", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -461,7 +475,7 @@ DEF_OP(Ror) {
       break;
       }
 
-      default: LogMan::Msg::A("Unhandled ROR size: %d", OpSize);
+      default: LOGMAN_MSG_A("Unhandled ROR size: %d", OpSize);
     }
   }
 }
@@ -480,7 +494,7 @@ DEF_OP(Extr) {
     break;
     }
 
-    default: LogMan::Msg::A("Unhandled EXTR size: %d", OpSize);
+    default: LOGMAN_MSG_A("Unhandled EXTR size: %d", OpSize);
   }
 }
 
@@ -512,14 +526,10 @@ DEF_OP(LDiv) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LDIV);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LDIV));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
 
       // Result is now in x0
       // Fix the stack and any values that were stepped on
@@ -529,7 +539,7 @@ DEF_OP(LDiv) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A("Unknown LDIV Size: %d", Size); break;
   }
 }
 
@@ -559,14 +569,10 @@ DEF_OP(LUDiv) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LUDIV);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LUDIV));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
 
       // Result is now in x0
       // Fix the stack and any values that were stepped on
@@ -576,7 +582,7 @@ DEF_OP(LUDiv) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LUDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A("Unknown LUDIV Size: %d", Size); break;
   }
 }
 
@@ -616,14 +622,10 @@ DEF_OP(LRem) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LREM);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LREM));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
 
       // Result is now in x0
       // Fix the stack and any values that were stepped on
@@ -633,7 +635,7 @@ DEF_OP(LRem) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LREM Size: %d", Size); break;
+    default: LOGMAN_MSG_A("Unknown LREM Size: %d", Size); break;
   }
 }
 
@@ -670,14 +672,11 @@ DEF_OP(LURem) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LUREM);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LUREM));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
+
       // Fix the stack and any values that were stepped on
       PopDynamicRegsAndLR();
 
@@ -686,7 +685,7 @@ DEF_OP(LURem) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LUREM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown LUREM Size: %d", OpSize); break;
   }
 }
 
@@ -700,7 +699,7 @@ DEF_OP(Not) {
     case 8:
       mvn(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unsupported Not size: %d", OpSize);
+    default: LOGMAN_MSG_A("Unsupported Not size: %d", OpSize);
   }
 }
 
@@ -731,7 +730,7 @@ DEF_OP(Popcount) {
       // fmov has zero extended, unused bytes are zero
       addv(VTMP1.B(), VTMP1.V8B());
       break;
-    default: LogMan::Msg::A("Unsupported Popcount size: %d", OpSize);
+    default: LOGMAN_MSG_A("Unsupported Popcount size: %d", OpSize);
   }
 
   auto Dst = GetReg<RA_32>(Node);
@@ -780,7 +779,7 @@ DEF_OP(FindMSB) {
       clz(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()));
       sub(Dst, TMP1, Dst);
       break;
-    default: LogMan::Msg::A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown REV size: %d", OpSize); break;
   }
 }
 
@@ -801,7 +800,7 @@ DEF_OP(FindTrailingZeros) {
       rbit(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       clz(GetReg<RA_64>(Node), GetReg<RA_64>(Node));
       break;
-    default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
   }
 }
 
@@ -820,7 +819,7 @@ DEF_OP(CountLeadingZeroes) {
     case 8:
       clz(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
   }
 }
 
@@ -838,7 +837,7 @@ DEF_OP(Rev) {
     case 8:
       rev(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown REV size: %d", OpSize); break;
   }
 }
 
@@ -860,15 +859,15 @@ DEF_OP(Bfi) {
       bfi(TMP1, GetReg<RA_64>(Op->Header.Args[1].ID()), Op->lsb, Op->Width);
       mov(GetReg<RA_64>(Node), TMP1);
       break;
-    default: LogMan::Msg::A("Unknown BFI size: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown BFI size: %d", OpSize); break;
   }
 }
 
 DEF_OP(Bfe) {
   auto Op = IROp->C<IR::IROp_Bfe>();
   uint8_t OpSize = IROp->Size;
-  LogMan::Throw::A(OpSize <= 8, "OpSize is too large for BFE: %d", OpSize);
-  LogMan::Throw::A(Op->Width != 0, "Invalid BFE width of 0");
+  LOGMAN_THROW_A(OpSize <= 8, "OpSize is too large for BFE: %d", OpSize);
+  LOGMAN_THROW_A(Op->Width != 0, "Invalid BFE width of 0");
 
   auto Dst = GetReg<RA_64>(Node);
   ubfx(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), Op->lsb, Op->Width);
@@ -908,12 +907,12 @@ Condition MapSelectCC(IR::CondClassType Cond) {
   case FEXCore::IR::COND_FGT: return Condition::hi;
   case FEXCore::IR::COND_FU:  return Condition::vs;
   case FEXCore::IR::COND_FNU: return Condition::vc;
-  case FEXCore::IR::COND_VS:;
-  case FEXCore::IR::COND_VC:;
+  case FEXCore::IR::COND_VS:
+  case FEXCore::IR::COND_VC:
   case FEXCore::IR::COND_MI:
   case FEXCore::IR::COND_PL:
   default:
-  LogMan::Msg::A("Unsupported compare type");
+  LOGMAN_MSG_A("Unsupported compare type");
   return Condition::nv;
   }
 }
@@ -931,9 +930,9 @@ DEF_OP(Select) {
   } else if (IsFPR(Op->Cmp1.ID())) {
     fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
   } else {
-    LogMan::Msg::A("Select: Expected GPR or FPR");
+    LOGMAN_MSG_A("Select: Expected GPR or FPR");
   }
-  
+
   auto cc = MapSelectCC(Op->Cond);
 
   uint64_t const_true, const_false;
@@ -942,7 +941,7 @@ DEF_OP(Select) {
 
   if (is_const_true || is_const_false) {
     if (is_const_false != true || is_const_true != true || const_true != 1 || const_false != 0) {
-      LogMan::Msg::A("Select: Unsupported compare inline parameters");
+      LOGMAN_MSG_A("Select: Unsupported compare inline parameters");
     }
     cset(GRS(Node), cc);
   } else {
@@ -966,38 +965,53 @@ DEF_OP(VExtractToGPR) {
     case 8:
       umov(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->Idx);
     break;
-    default:  LogMan::Msg::A("Unhandled ExtractElementSize: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled ExtractElementSize: %d", OpSize);
   }
 }
 
-DEF_OP(Float_ToGPR_ZU) {
-  LogMan::Msg::D("Unimplemented");
-}
-
 DEF_OP(Float_ToGPR_ZS) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_ZS>();
-  if (Op->Header.ElementSize == 8) {
-    fcvtzs(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).D());
+  aarch64::Register Dst{};
+  aarch64::VRegister Src{};
+  if (Op->SrcElementSize == 8) {
+    Src = GetSrc(Op->Header.Args[0].ID()).D();
   }
   else {
-    fcvtzs(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).S());
+    Src = GetSrc(Op->Header.Args[0].ID()).S();
   }
-}
 
-DEF_OP(Float_ToGPR_U) {
-  LogMan::Msg::D("Unimplemented");
+  if (IROp->Size == 8) {
+    Dst = GetReg<RA_64>(Node);
+  }
+  else {
+    Dst = GetReg<RA_32>(Node);
+  }
+
+  fcvtzs(Dst, Src);
 }
 
 DEF_OP(Float_ToGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_S>();
-  if (Op->Header.ElementSize == 8) {
+
+  aarch64::Register Dst{};
+  aarch64::VRegister Src{};
+  if (Op->SrcElementSize == 8) {
     frinti(VTMP1.D(), GetSrc(Op->Header.Args[0].ID()).D());
-    fcvtzs(GetReg<RA_64>(Node), VTMP1.D());
+    Src = VTMP1.D();
   }
   else {
     frinti(VTMP1.S(), GetSrc(Op->Header.Args[0].ID()).S());
-    fcvtzs(GetReg<RA_32>(Node), VTMP1.S());
+    Src = VTMP1.S();
   }
+
+  if (IROp->Size == 8) {
+    Dst = GetReg<RA_64>(Node);
+  }
+  else {
+    Dst = GetReg<RA_32>(Node);
+  }
+
+  fcvtzs(Dst, Src);
 }
 
 DEF_OP(FCmp) {
@@ -1010,11 +1024,11 @@ DEF_OP(FCmp) {
     fcmp(GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
   }
   auto Dst = GetReg<RA_64>(Node);
-  
+
   bool set = false;
 
   if (Op->Flags & (1 << IR::FCMP_FLAG_EQ)) {
-    LogMan::Throw::A(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
+    LOGMAN_THROW_A(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
     // EQ or unordered
     cset(Dst, Condition::eq); // Z = 1
     csinc(Dst, Dst, xzr, Condition::vc); // IF !V ? Z : 1
@@ -1043,17 +1057,15 @@ DEF_OP(FCmp) {
   }
 }
 
-DEF_OP(F80Cmp) {
-  LogMan::Msg::D("Unimplemented");
-}
-
 #undef DEF_OP
 
-void JITCore::RegisterALUHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterALUHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(TRUNCELEMENTPAIR,  TruncElementPair);
   REGISTER_OP(CONSTANT,          Constant);
+  REGISTER_OP(ENTRYPOINTOFFSET,  EntrypointOffset);
   REGISTER_OP(INLINECONSTANT,    InlineConstant);
+  REGISTER_OP(INLINEENTRYPOINTOFFSET,  InlineEntrypointOffset);
   REGISTER_OP(CYCLECOUNTER,      CycleCounter);
   REGISTER_OP(ADD,               Add);
   REGISTER_OP(SUB,               Sub);
@@ -1090,12 +1102,9 @@ void JITCore::RegisterALUHandlers() {
   REGISTER_OP(SBFE,              Sbfe);
   REGISTER_OP(SELECT,            Select);
   REGISTER_OP(VEXTRACTTOGPR,     VExtractToGPR);
-  REGISTER_OP(FLOAT_TOGPR_ZU,    Float_ToGPR_ZU);
   REGISTER_OP(FLOAT_TOGPR_ZS,    Float_ToGPR_ZS);
-  REGISTER_OP(FLOAT_TOGPR_U,     Float_ToGPR_U);
   REGISTER_OP(FLOAT_TOGPR_S,     Float_ToGPR_S);
   REGISTER_OP(FCMP,              FCmp);
-  REGISTER_OP(F80CMP,            F80Cmp);
 
 #undef REGISTER_OP
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp

@@ -1,9 +1,15 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(CASPair) {
   auto Op = IROp->C<IR::IROp_CASPair>();
   uint8_t OpSize = IROp->Size;
@@ -28,7 +34,7 @@ DEF_OP(CASPair) {
       mov(Dst.first, TMP3);
       mov(Dst.second, TMP4);
       break;
-    default: LogMan::Msg::A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A("Unsupported: %d", OpSize);
     }
   }
   else {
@@ -83,7 +89,7 @@ DEF_OP(CASPair) {
         bind(&LoopExpected);
         break;
       }
-      default: LogMan::Msg::A("Unsupported: %d", OpSize);
+      default: LOGMAN_MSG_A("Unsupported: %d", OpSize);
     }
   }
 }
@@ -109,7 +115,7 @@ DEF_OP(CAS) {
     case 2: casalh(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
     case 4: casal(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
     case 8: casal(TMP2.X(), Desired.X(), MemOperand(MemSrc)); break;
-    default: LogMan::Msg::A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A("Unsupported: %d", OpSize);
     }
     mov(GetReg<RA_64>(Node), TMP2);
   }
@@ -200,7 +206,7 @@ DEF_OP(CAS) {
 
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", OpSize);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", OpSize);
     }
   }
 }
@@ -216,7 +222,7 @@ DEF_OP(AtomicAdd) {
     case 2: staddlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: staddl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: staddl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -258,7 +264,7 @@ DEF_OP(AtomicAdd) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
@@ -275,7 +281,7 @@ DEF_OP(AtomicSub) {
     case 2: staddlh(TMP2.W(), MemOperand(MemSrc)); break;
     case 4: staddl(TMP2.W(), MemOperand(MemSrc)); break;
     case 8: staddl(TMP2.X(), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -317,7 +323,7 @@ DEF_OP(AtomicSub) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
@@ -334,7 +340,7 @@ DEF_OP(AtomicAnd) {
     case 2: stclrlh(TMP2.W(), MemOperand(MemSrc)); break;
     case 4: stclrl(TMP2.W(), MemOperand(MemSrc)); break;
     case 8: stclrl(TMP2.X(), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -376,7 +382,7 @@ DEF_OP(AtomicAnd) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
@@ -392,7 +398,7 @@ DEF_OP(AtomicOr) {
     case 2: stsetlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: stsetl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: stsetl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -434,7 +440,7 @@ DEF_OP(AtomicOr) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
@@ -450,7 +456,7 @@ DEF_OP(AtomicXor) {
     case 2: steorlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: steorl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: steorl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -492,7 +498,7 @@ DEF_OP(AtomicXor) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
@@ -509,7 +515,7 @@ DEF_OP(AtomicSwap) {
     case 2: swplh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: swpl(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: swpl(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -552,7 +558,7 @@ DEF_OP(AtomicSwap) {
         mov(GetReg<RA_64>(Node), TMP2.X());
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
@@ -567,7 +573,7 @@ DEF_OP(AtomicFetchAdd) {
     case 2: ldaddalh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldaddal(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldaddal(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -613,7 +619,7 @@ DEF_OP(AtomicFetchAdd) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
@@ -629,7 +635,7 @@ DEF_OP(AtomicFetchSub) {
     case 2: ldaddalh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldaddal(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldaddal(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -675,7 +681,7 @@ DEF_OP(AtomicFetchSub) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
@@ -691,7 +697,7 @@ DEF_OP(AtomicFetchAnd) {
     case 2: ldclralh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldclral(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldclral(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -737,7 +743,7 @@ DEF_OP(AtomicFetchAnd) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
@@ -752,7 +758,7 @@ DEF_OP(AtomicFetchOr) {
     case 2: ldsetalh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldsetal(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldsetal(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -798,7 +804,7 @@ DEF_OP(AtomicFetchOr) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
@@ -813,7 +819,7 @@ DEF_OP(AtomicFetchXor) {
     case 2: ldeoralh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldeoral(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldeoral(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
   else {
@@ -859,14 +865,14 @@ DEF_OP(AtomicFetchXor) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
     }
   }
 }
 
 #undef DEF_OP
-void JITCore::RegisterAtomicHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterAtomicHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(CASPAIR,        CASPair);
   REGISTER_OP(CAS,            CAS);
   REGISTER_OP(ATOMICADD,      AtomicAdd);

External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp

@@ -1,13 +1,20 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/Core/InternalThreadState.h"
 
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/HLE/SyscallHandler.h>
+#include <Interface/HLE/Thunks/Thunks.h>
 
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(GuestCallDirect) {
   LogMan::Msg::D("Unimplemented");
 }
@@ -22,9 +29,7 @@ DEF_OP(GuestReturn) {
 
 DEF_OP(SignalReturn) {
   // First we must reset the stack
-  if (SpillSlots) {
-    add(sp, sp, SpillSlots * 16);
-  }
+  ResetStack();
 
   // Now branch to our signal return helper
   // This can't be a direct branch since the code needs to live at a constant location
@@ -36,11 +41,9 @@ DEF_OP(CallbackReturn) {
 
   // spill back to CTX
   SpillStaticRegs();
-  
+
   // First we must reset the stack
-  if (SpillSlots) {
-    add(sp, sp, SpillSlots * 16);
-  }
+  ResetStack();
 
   // We can now lower the ref counter again
   LoadConstant(x0, reinterpret_cast<uint64_t>(ThreadSharedData.SignalHandlerRefCounterPtr));
@@ -49,9 +52,9 @@ DEF_OP(CallbackReturn) {
   str(w2, MemOperand(x0));
 
   // We need to adjust an additional 8 bytes to get back to the original "misaligned" RSP state
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
+  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
   add(x2, x2, 8);
-  str(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
+  str(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
 
   PopCalleeSavedRegisters();
 
@@ -64,15 +67,13 @@ DEF_OP(ExitFunction) {
 
   Label FullLookup;
 
-  if (SpillSlots) {
-    add(sp, sp, SpillSlots * 16);
-  }
+  ResetStack();
 
   aarch64::Register RipReg;
   uint64_t NewRIP;
 
-  if (IsInlineConstant(Op->NewRIP, &NewRIP)) {
-    Literal l_BranchHost{ExitFunctionLinkerAddress};
+  if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
+    Literal l_BranchHost{ThreadSharedData.Dispatcher->ExitFunctionLinkerAddress};
     Literal l_BranchGuest{NewRIP};
 
     ldr(x0, &l_BranchHost);
@@ -82,9 +83,9 @@ DEF_OP(ExitFunction) {
     place(&l_BranchGuest);
   } else {
     RipReg = GetReg<RA_64>(Op->Header.Args[0].ID());
-    
+
     // L1 Cache
-    LoadConstant(x0, State->LookupCache->GetL1Pointer());
+    LoadConstant(x0, ThreadState->LookupCache->GetL1Pointer());
 
     and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
     add(x0, x0, Operand(x3, Shift::LSL, 4));
@@ -95,8 +96,8 @@ DEF_OP(ExitFunction) {
     br(x1);
 
     bind(&FullLookup);
-    LoadConstant(TMP1, AbsoluteLoopTopAddress);
-    str(RipReg, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, State.rip)));
+    LoadConstant(TMP1, ThreadSharedData.Dispatcher->AbsoluteLoopTopAddress);
+    str(RipReg, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
     br(TMP1);
   }
 }
@@ -136,12 +137,12 @@ Condition MapBranchCC(IR::CondClassType Cond) {
   case FEXCore::IR::COND_FGT: return Condition::hi;
   case FEXCore::IR::COND_FU:  return Condition::vs;
   case FEXCore::IR::COND_FNU: return Condition::vc;
-  case FEXCore::IR::COND_VS:;
-  case FEXCore::IR::COND_VC:;
+  case FEXCore::IR::COND_VS:
+  case FEXCore::IR::COND_VC:
   case FEXCore::IR::COND_MI:
   case FEXCore::IR::COND_PL:
   default:
-  LogMan::Msg::A("Unsupported compare type");
+  LOGMAN_MSG_A("Unsupported compare type");
   return Condition::nv;
   }
 }
@@ -168,10 +169,10 @@ DEF_OP(CondJump) {
   bool isConst = IsInlineConstant(Op->Cmp2, &Const);
 
   if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_EQ) {
-    LogMan::Throw::A(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
+    LOGMAN_THROW_A(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
     cbz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
   } else if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_NEQ) {
-    LogMan::Throw::A(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
+    LOGMAN_THROW_A(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
     cbnz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
   } else {
     if (IsGPR(Op->Cmp1.ID())) {
@@ -182,12 +183,12 @@ DEF_OP(CondJump) {
     } else if (IsFPR(Op->Cmp1.ID())) {
       fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
     } else {
-      LogMan::Msg::A("CondJump: Expected GPR or FPR");
+      LOGMAN_MSG_A("CondJump: Expected GPR or FPR");
     }
 
     b(TrueTargetLabel, MapBranchCC(Op->Cond));
   }
-  
+
   if (FalseIter == JumpTargets.end()) {
     FalseTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
   }
@@ -222,7 +223,7 @@ DEF_OP(Syscall) {
   blr(x3);
 
   add(sp, sp, SPOffset);
-  
+
   // Result is now in x0
   // Fix the stack and any values that were stepped on
   FillStaticRegs();
@@ -244,30 +245,35 @@ DEF_OP(Thunk) {
 
   mov(x0, GetReg<RA_64>(Op->Header.Args[0].ID()));
 
-#if _M_X86_64
-  ERROR_AND_DIE("JIT: OP_THUNK not supported with arm simulator")
-#else
-  LoadConstant(x2, Op->ThunkFnPtr);
+  auto thunkFn = ThreadState->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
+  LoadConstant(x2, (uintptr_t)thunkFn);
   blr(x2);
-#endif
 
   PopDynamicRegsAndLR();
-  
+
   FillStaticRegs(); // load from ctx after ra64 refill
 }
 
 
 DEF_OP(ValidateCode) {
   auto Op = IROp->C<IR::IROp_ValidateCode>();
-  uint8_t *NewCode = (uint8_t *)Op->CodePtr;
   uint8_t *OldCode = (uint8_t *)&Op->CodeOriginalLow;
   int len = Op->CodeLength;
   int idx = 0;
 
   LoadConstant(GetReg<RA_64>(Node), 0);
-  LoadConstant(x0, Op->CodePtr);
+  LoadConstant(x0, Entry + Op->Offset);
   LoadConstant(x1, 1);
 
+  while (len >= 8)
+  {
+    ldr(x2, MemOperand(x0, idx));
+    LoadConstant(x3, *(uint32_t *)(OldCode + idx));
+    cmp(x2, x3);
+    csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
+    len -= 8;
+    idx += 8;
+  }
   while (len >= 4)
   {
     ldr(w2, MemOperand(x0, idx));
@@ -298,17 +304,16 @@ DEF_OP(ValidateCode) {
 }
 
 DEF_OP(RemoveCodeEntry) {
-  auto Op = IROp->C<IR::IROp_RemoveCodeEntry>();
   // Arguments are passed as follows:
   // X0: Thread
   // X1: RIP
 
   PushDynamicRegsAndLR();
-  
+
   mov(x0, STATE);
-  LoadConstant(x1, Op->RIP);
- 
-  LoadConstant(x2, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntry));
+  LoadConstant(x1, Entry);
+
+  LoadConstant(x2, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit));
   SpillStaticRegs();
   blr(x2);
   FillStaticRegs();
@@ -319,15 +324,17 @@ DEF_OP(RemoveCodeEntry) {
 
 DEF_OP(CPUID) {
   auto Op = IROp->C<IR::IROp_CPUID>();
-  
+
   PushDynamicRegsAndLR();
 
   // x0 = CPUID Handler
   // x1 = CPUID Function
+  // x2 = CPUID Leaf
   LoadConstant(x0, reinterpret_cast<uint64_t>(&CTX->CPUID));
   mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
+  mov(x2, GetReg<RA_64>(Op->Header.Args[1].ID()));
 
-  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t);
+  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t, uint32_t);
   union PtrCast {
     ClassPtrType ClassPtr;
     uintptr_t Data;
@@ -350,8 +357,8 @@ DEF_OP(CPUID) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterBranchHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterBranchHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(GUESTCALLDIRECT,   GuestCallDirect);
   REGISTER_OP(GUESTCALLINDIRECT, GuestCallIndirect);
   REGISTER_OP(GUESTRETURN,       GuestReturn);

External/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp

@@ -1,10 +1,16 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(VInsGPR) {
   auto Op = IROp->C<IR::IROp_VInsGPR>();
   mov(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
@@ -25,7 +31,7 @@ DEF_OP(VInsGPR) {
       ins(GetDst(Node).V2D(), Op->Index, GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
     }
-    default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
   }
 }
 
@@ -46,14 +52,10 @@ DEF_OP(VCastFromGPR) {
     case 8:
       fmov(GetDst(Node).D(), GetReg<RA_64>(Op->Header.Args[0].ID()).X());
       break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Float_FromGPR_U) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Float_FromGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
   uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
@@ -89,20 +91,7 @@ DEF_OP(Float_FToF) {
       fcvt(GetDst(Node).S(), GetSrc(Op->Header.Args[0].ID()).D());
       break;
     }
-    default: LogMan::Msg::A("Unknown FCVT sizes: 0x%x", Conv);
-  }
-}
-
-DEF_OP(Vector_UToF) {
-  auto Op = IROp->C<IR::IROp_Vector_UToF>();
-  switch (Op->Header.ElementSize) {
-    case 4:
-      ucvtf(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
-    break;
-    case 8:
-      ucvtf(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
-    break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A("Unknown FCVT sizes: 0x%x", Conv);
   }
 }
 
@@ -115,20 +104,7 @@ DEF_OP(Vector_SToF) {
     case 8:
       scvtf(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
-  }
-}
-
-DEF_OP(Vector_FToZU) {
-  auto Op = IROp->C<IR::IROp_Vector_FToZU>();
-  switch (Op->Header.ElementSize) {
-    case 4:
-      fcvtzu(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
-    break;
-    case 8:
-      fcvtzu(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
-    break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
   }
 }
 
@@ -141,22 +117,7 @@ DEF_OP(Vector_FToZS) {
     case 8:
       fcvtzs(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
-  }
-}
-
-DEF_OP(Vector_FToU) {
-  auto Op = IROp->C<IR::IROp_Vector_FToU>();
-  switch (Op->Header.ElementSize) {
-    case 4:
-      frinti(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
-      fcvtzu(GetDst(Node).V4S(), GetDst(Node).V4S());
-    break;
-    case 8:
-      frinti(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
-      fcvtzu(GetDst(Node).V2D(), GetDst(Node).V2D());
-    break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
   }
 }
 
@@ -171,7 +132,7 @@ DEF_OP(Vector_FToS) {
       frinti(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
       fcvtzs(GetDst(Node).V2D(), GetDst(Node).V2D());
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
   }
 }
 
@@ -188,25 +149,78 @@ DEF_OP(Vector_FToF) {
       fcvtn(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2D());
       break;
     }
-    default: LogMan::Msg::A("Unknown Conversion Type : 0%04x", Conv); break;
+    default: LOGMAN_MSG_A("Unknown Conversion Type : 0%04x", Conv); break;
+  }
+}
+
+DEF_OP(Vector_FToI) {
+  auto Op = IROp->C<IR::IROp_Vector_FToI>();
+  switch (Op->Round) {
+    case FEXCore::IR::Round_Nearest.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintn(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintn(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Negative_Infinity.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintm(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintm(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Positive_Infinity.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintp(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintp(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Towards_Zero.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintz(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintz(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Host.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frinti(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frinti(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
   }
 }
 
 #undef DEF_OP
-void JITCore::RegisterConversionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterConversionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(VINSGPR,         VInsGPR);
   REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_U, Float_FromGPR_U);
   REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
   REGISTER_OP(FLOAT_FTOF,      Float_FToF);
-  REGISTER_OP(VECTOR_UTOF,     Vector_UToF);
   REGISTER_OP(VECTOR_STOF,     Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZU,    Vector_FToZU);
   REGISTER_OP(VECTOR_FTOZS,    Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOU,     Vector_FToU);
   REGISTER_OP(VECTOR_FTOS,     Vector_FToS);
   REGISTER_OP(VECTOR_FTOF,     Vector_FToF);
+  REGISTER_OP(VECTOR_FTOI,     Vector_FToI);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp

@@ -1,10 +1,16 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(AESImc) {
   auto Op = IROp->C<IR::IROp_VAESImc>();
@@ -83,8 +89,8 @@ DEF_OP(AESKeyGenAssist) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterEncryptionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterEncryptionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(VAESIMC,     AESImc);
   REGISTER_OP(VAESENC,     AESEnc);
   REGISTER_OP(VAESENCLAST, AESEncLast);

External/FEXCore/Source/Interface/Core/JIT/Arm64/FlagOps.cpp

@@ -1,18 +1,24 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(GetHostFlag) {
   auto Op = IROp->C<IR::IROp_GetHostFlag>();
   ubfx(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), Op->Flag, 1);
 }
 
 #undef DEF_OP
-void JITCore::RegisterFlagHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterFlagHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(GETHOSTFLAG, GetHostFlag);
 #undef REGISTER_OP
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h

@@ -1,9 +1,16 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #pragma once
 
 #include "Interface/Core/LookupCache.h"
+#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
 
 #include "aarch64/assembler-aarch64.h"
-#include "aarch64/cpu-aarch64.h"
 #include "aarch64/disasm-aarch64.h"
 #include "aarch64/assembler-aarch64.h"
 
@@ -29,56 +36,18 @@ namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
 
-// All but x29 are caller saved
-const std::array<aarch64::Register, 16> SRA64 = {
-  x4, x5, x6, x7, x8, x9, x10, x11,
-  x12, x18, x17, x16, x15, x14, x13, x29
-};
-
-// All are callee saved
-const std::array<aarch64::Register, 9> RA64 = {
-  x20, x21, x22, x23, x24, x25, x26, x27,
-  x19
-};
-
-const std::array<std::pair<aarch64::Register, aarch64::Register>, 4>  RA64Pair = {{
-  {x20, x21},
-  {x22, x23},
-  {x24, x25},
-  {x26, x27},
-}};
-
-const std::array<std::pair<aarch64::Register, aarch64::Register>, 4> RA32Pair = {{
-  {w20, w21},
-  {w22, w23},
-  {w24, w25},
-  {w26, w27},
-}};
-
-// All are caller saved
-const std::array<aarch64::VRegister, 16> SRAFPR = {
-  v16, v17, v18, v19, v20, v21, v22, v23,
-  v24, v25, v26, v27, v28, v29, v30, v31
-};
-
-//  v8..v15 = (lower 64bits) Callee saved
-const std::array<aarch64::VRegister, 12> RAFPR = {
-/*v0,  v1,  v2,  v3,*/v4,  v5,  v6,  v7,  // v0 ~ v3 are used as temps
-  v8,  v9,  v10, v11, v12, v13, v14, v15
-};
-
-class JITCore final : public CPUBackend, public vixl::aarch64::Assembler  {
+class Arm64JITCore final : public CPUBackend, public Arm64Emitter  {
 public:
   struct CodeBuffer {
     uint8_t *Ptr;
     size_t Size;
   };
 
-  explicit JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, CodeBuffer Buffer, bool CompileThread);
+  explicit Arm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
 
-  ~JITCore() override;
+  ~Arm64JITCore() override;
   std::string GetName() override { return "JIT"; }
-  void *CompileCode(FEXCore::IR::IRListView<true> const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
+  void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
 
   void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
 
@@ -86,21 +55,22 @@ public:
 
   void ClearCache() override;
 
-  bool HandleSIGILL(int Signal, void *info, void *ucontext);
   bool HandleSIGBUS(int Signal, void *info, void *ucontext);
-  bool HandleSignalPause(int Signal, void *info, void *ucontext);
-  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
 
   static constexpr size_t INITIAL_CODE_SIZE = 1024 * 1024 * 16;
-  static CodeBuffer AllocateNewCodeBuffer(size_t Size);
+  CodeBuffer AllocateNewCodeBuffer(size_t Size);
 
   void CopyNecessaryDataForCompileThread(CPUBackend *Original) override;
 
 private:
+  FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
+
+  std::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
   Label *PendingTargetLabel;
   FEXCore::Context::Context *CTX;
-  FEXCore::Core::InternalThreadState *State;
-  FEXCore::IR::IRListView<true> const *IR;
+  FEXCore::Core::InternalThreadState *ThreadState;
+  FEXCore::IR::IRListView const *IR;
+  uint64_t Entry;
 
   std::map<IR::OrderedNodeWrapper::NodeOffsetType, aarch64::Label> JumpTargets;
 
@@ -126,32 +96,35 @@ private:
   constexpr static uint8_t RA_FPR = 2;
 
   template<uint8_t RAType>
-  aarch64::Register GetReg(uint32_t Node);
+  aarch64::Register GetReg(uint32_t Node) const;
 
   template<>
-  aarch64::Register GetReg<RA_32>(uint32_t Node);
+  aarch64::Register GetReg<RA_32>(uint32_t Node) const;
   template<>
-  aarch64::Register GetReg<RA_64>(uint32_t Node);
+  aarch64::Register GetReg<RA_64>(uint32_t Node) const;
 
   template<uint8_t RAType>
-  std::pair<aarch64::Register, aarch64::Register> GetSrcPair(uint32_t Node);
+  std::pair<aarch64::Register, aarch64::Register> GetSrcPair(uint32_t Node) const;
 
   template<>
-  std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_32>(uint32_t Node);
+  std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_32>(uint32_t Node) const;
   template<>
-  std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_64>(uint32_t Node);
+  std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_64>(uint32_t Node) const;
 
-  aarch64::VRegister GetSrc(uint32_t Node);
-  aarch64::VRegister GetDst(uint32_t Node);
+  aarch64::VRegister GetSrc(uint32_t Node) const;
+  aarch64::VRegister GetDst(uint32_t Node) const;
 
-  FEXCore::IR::RegisterClassType GetRegClass(uint32_t Node);
+  FEXCore::IR::RegisterClassType GetRegClass(uint32_t Node) const;
 
-  bool IsFPR(uint32_t Node);
-  bool IsGPR(uint32_t Node);
+  IR::PhysicalRegister GetPhys(uint32_t Node) const;
+
+  bool IsFPR(uint32_t Node) const;
+  bool IsGPR(uint32_t Node) const;
 
   MemOperand GenerateMemOperand(uint8_t AccessSize, aarch64::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale);
 
-  bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr);
+  bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr) const;
+  bool IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value) const;
 
   struct LiveRange {
     uint32_t Begin;
@@ -161,9 +134,6 @@ private:
 #if DEBUG
   vixl::aarch64::Decoder Decoder;
 #endif
-  vixl::aarch64::CPU CPU;
-  bool SupportsAtomics{};
-  bool SupportsRCPC{};
 
   void EmplaceNewCodeBuffer(CodeBuffer Buffer) {
     CurrentCodeBuffer = &CodeBuffers.emplace_back(Buffer);
@@ -180,8 +150,6 @@ private:
   // For code safety we can't delete code buffers until outside of all signals
   std::vector<CodeBuffer> CodeBuffers{};
 
-  // This is the codebuffer that our dispatcher lives in
-  CodeBuffer DispatcherCodeBuffer{};
   // This is the current code buffer that we are tracking
   CodeBuffer *CurrentCodeBuffer{};
 
@@ -189,60 +157,24 @@ private:
   static constexpr size_t MAX_CODE_SIZE = 1024 * 1024 * 128;
   static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096 * 2;
 
-  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true);
-
 #if DEBUG
   vixl::aarch64::Disassembler Disasm;
 #endif
 
-  void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant);
-
-  void CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread);
-  void PushCalleeSavedRegisters();
-  void PopCalleeSavedRegisters();
-
-  static uint64_t ExitFunctionLink(JITCore *core, FEXCore::Core::InternalThreadState *Thread, uint64_t *record);
-
-  /**
-   * @name Dispatch Helper functions
-   * @{ */
-  uint64_t AbsoluteLoopTopAddressFillSRA{};
-  uint64_t AbsoluteLoopTopAddress{};
-  uint64_t ThreadPauseHandlerAddressSpillSRA{};
-  uint64_t ExitFunctionLinkerAddress{};
-  uint64_t ThreadPauseHandlerAddress{};
-
-  uint64_t ThreadStopHandlerAddressSpillSRA{};
-  uint64_t ThreadStopHandlerAddress{};
-  uint64_t PauseReturnInstruction{};
-
-  uint32_t SignalHandlerRefCounter{};
-
-  void StoreThreadState(int Signal, void *ucontext);
-  void RestoreThreadState(void *ucontext);
-  /**  @} */
+  static uint64_t ExitFunctionLink(Arm64JITCore *core, FEXCore::Core::CpuStateFrame *Frame, uint64_t *record);
 
   struct CompilerSharedData {
-    uint64_t InterpreterFallbackHelperAddress{};
-
     uint64_t SignalReturnInstruction{};
 
     uint32_t *SignalHandlerRefCounterPtr{};
+    FEXCore::CPU::Dispatcher *Dispatcher{};
   };
 
   CompilerSharedData ThreadSharedData;
   IR::RegisterAllocationPass *RAPass;
   IR::RegisterAllocationData *RAData;
 
-  uint32_t SpillSlots{};
-
-  void SpillStaticRegs();
-  void FillStaticRegs();
-
-  void PushDynamicRegsAndLR();
-  void PopDynamicRegsAndLR();
-
-  using OpHandler = void (JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
+  using OpHandler = void (Arm64JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
   std::array<OpHandler, FEXCore::IR::IROps::OP_LAST + 1> OpHandlers {};
   void RegisterALUHandlers();
   void RegisterAtomicHandlers();
@@ -265,7 +197,9 @@ private:
   ///< ALU Ops
   DEF_OP(TruncElementPair);
   DEF_OP(Constant);
+  DEF_OP(EntrypointOffset);
   DEF_OP(InlineConstant);
+  DEF_OP(InlineEntrypointOffset);
   DEF_OP(CycleCounter);
   DEF_OP(Add);
   DEF_OP(Sub);
@@ -306,10 +240,8 @@ private:
   DEF_OP(VExtractToGPR);
   DEF_OP(Float_ToGPR_ZU);
   DEF_OP(Float_ToGPR_ZS);
-  DEF_OP(Float_ToGPR_U);
   DEF_OP(Float_ToGPR_S);
   DEF_OP(FCmp);
-  DEF_OP(F80Cmp);
 
   ///< Atomic ops
   DEF_OP(CASPair);
@@ -344,16 +276,13 @@ private:
   ///< Conversion ops
   DEF_OP(VInsGPR);
   DEF_OP(VCastFromGPR);
-  DEF_OP(Float_FromGPR_U);
   DEF_OP(Float_FromGPR_S);
   DEF_OP(Float_FToF);
-  DEF_OP(Vector_UToF);
   DEF_OP(Vector_SToF);
-  DEF_OP(Vector_FToZU);
   DEF_OP(Vector_FToZS);
-  DEF_OP(Vector_FToU);
   DEF_OP(Vector_FToS);
   DEF_OP(Vector_FToF);
+  DEF_OP(Vector_FToI);
 
   ///< Flag ops
   DEF_OP(GetHostFlag);
@@ -373,8 +302,11 @@ private:
   DEF_OP(StoreMem);
   DEF_OP(LoadMemTSO);
   DEF_OP(StoreMemTSO);
+  DEF_OP(ParanoidLoadMemTSO);
+  DEF_OP(ParanoidStoreMemTSO);
   DEF_OP(VLoadMemElement);
   DEF_OP(VStoreMemElement);
+  DEF_OP(CacheLineClear);
 
   ///< Misc ops
   DEF_OP(EndBlock);
@@ -400,6 +332,7 @@ private:
   DEF_OP(SplatVector4);
   DEF_OP(VMov);
   DEF_OP(VAnd);
+  DEF_OP(VBic);
   DEF_OP(VOr);
   DEF_OP(VXor);
   DEF_OP(VAdd);
@@ -410,8 +343,10 @@ private:
   DEF_OP(VSQSub);
   DEF_OP(VAddP);
   DEF_OP(VAddV);
+  DEF_OP(VUMinV);
   DEF_OP(VURAvg);
   DEF_OP(VAbs);
+  DEF_OP(VPopcount);
   DEF_OP(VFAdd);
   DEF_OP(VFAddP);
   DEF_OP(VFSub);
@@ -431,6 +366,8 @@ private:
   DEF_OP(VSMax);
   DEF_OP(VZip);
   DEF_OP(VZip2);
+  DEF_OP(VUnZip);
+  DEF_OP(VUnZip2);
   DEF_OP(VBSL);
   DEF_OP(VCMPEQ);
   DEF_OP(VCMPEQZ);
@@ -453,6 +390,7 @@ private:
   DEF_OP(VInsElement);
   DEF_OP(VInsScalarElement);
   DEF_OP(VExtractElement);
+  DEF_OP(VDupElement);
   DEF_OP(VExtr);
   DEF_OP(VSLI);
   DEF_OP(VSRI);
@@ -475,6 +413,7 @@ private:
   DEF_OP(VSMull);
   DEF_OP(VUMull2);
   DEF_OP(VSMull2);
+  DEF_OP(VUABDL);
   DEF_OP(VTBL1);
 
   ///< Encryption ops

External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp

@@ -1,10 +1,17 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
+#include <FEXCore/Utils/CompilerDefs.h>
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(LoadContext) {
   auto Op = IROp->C<IR::IROp_LoadContext>();
@@ -23,7 +30,7 @@ DEF_OP(LoadContext) {
     case 8:
       ldr(GetReg<RA_64>(Node), MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled LoadContext size: %d", OpSize);
     }
   }
   else {
@@ -44,7 +51,7 @@ DEF_OP(LoadContext) {
     case 16:
       ldr(Dst, MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled LoadContext size: %d", OpSize);
     }
   }
 }
@@ -66,7 +73,7 @@ DEF_OP(StoreContext) {
     case 8:
       str(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled StoreContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled StoreContext size: %d", OpSize);
     }
   }
   else {
@@ -87,7 +94,7 @@ DEF_OP(StoreContext) {
     case 16:
       str(Src, MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled LoadContext size: %d", OpSize);
     }
   }
 }
@@ -95,61 +102,60 @@ DEF_OP(StoreContext) {
 
 DEF_OP(LoadRegister) {
   auto Op = IROp->C<IR::IROp_LoadRegister>();
-  uint8_t OpSize = IROp->Size;
 
   if (Op->Class == IR::GPRClass) {
-    auto regId = (Op->Offset - offsetof(FEXCore::Core::ThreadState, State.gregs[0])) / 8;
+    auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.gregs[0])) / 8;
     auto regOffs = Op->Offset & 7;
 
-    LogMan::Throw::A(regId < SRA64.size(), "out of range regId");
+    LOGMAN_THROW_A(regId < SRA64.size(), "out of range regId");
 
     auto reg = SRA64[regId];
-    
+
     switch(Op->Header.Size) {
       case 1:
-        LogMan::Throw::A(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0 || regOffs == 1, "unexpected regOffs");
         ubfx(GetReg<RA_64>(Node), reg, regOffs * 8, 8);
         break;
 
       case 2:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
         ubfx(GetReg<RA_64>(Node), reg, 0, 16);
         break;
 
       case 4:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Node).GetCode() != reg.GetCode())
           mov(GetReg<RA_32>(Node), reg.W());
         break;
 
       case 8:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Node).GetCode() != reg.GetCode())
           mov(GetReg<RA_64>(Node), reg);
         break;
     }
   } else if (Op->Class == IR::FPRClass) {
-    auto regId = (Op->Offset - offsetof(FEXCore::Core::ThreadState, State.xmm[0][0])) / 16;
+    auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0])) / 16;
     auto regOffs = Op->Offset & 15;
 
-    LogMan::Throw::A(regId < SRAFPR.size(), "out of range regId");
+    LOGMAN_THROW_A(regId < SRAFPR.size(), "out of range regId");
 
     auto guest = SRAFPR[regId];
     auto host = GetSrc(Node);
 
     switch(Op->Header.Size) {
       case 1:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
         mov(host.B(), guest.B());
         break;
 
       case 2:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
         fmov(host.H(), guest.H());
         break;
 
       case 4:
-        LogMan::Throw::A((regOffs & 3) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A((regOffs & 3) == 0, "unexpected regOffs");
         if (regOffs == 0) {
           if (host.GetCode() != guest.GetCode())
             fmov(host.S(), guest.S());
@@ -159,7 +165,7 @@ DEF_OP(LoadRegister) {
         break;
 
       case 8:
-        LogMan::Throw::A((regOffs & 7) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A((regOffs & 7) == 0, "unexpected regOffs");
         if (regOffs == 0) {
           if (host.GetCode() != guest.GetCode())
             mov(host.D(), guest.D());
@@ -169,56 +175,54 @@ DEF_OP(LoadRegister) {
         break;
 
       case 16:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
         if (host.GetCode() != guest.GetCode())
           mov(host.Q(), guest.Q());
         break;
     }
   } else {
-    LogMan::Throw::A(false, "Unhandled Op->Class %d", Op->Class);
+    LOGMAN_THROW_A(false, "Unhandled Op->Class %d", Op->Class);
   }
 }
 
 DEF_OP(StoreRegister) {
   auto Op = IROp->C<IR::IROp_StoreRegister>();
-  uint8_t OpSize = IROp->Size;
-
 
   if (Op->Class == IR::GPRClass) {
     auto regId = Op->Offset / 8 - 1;
     auto regOffs = Op->Offset & 7;
 
-    LogMan::Throw::A(regId < SRA64.size(), "out of range regId");
+    LOGMAN_THROW_A(regId < SRA64.size(), "out of range regId");
 
     auto reg = SRA64[regId];
-    
+
     switch(Op->Header.Size) {
       case 1:
-        LogMan::Throw::A(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0 || regOffs == 1, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), regOffs * 8, 8);
         break;
 
       case 2:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), 0, 16);
         break;
-        
+
       case 4:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), 0, 32);
         break;
 
       case 8:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Op->Value.ID()).GetCode() != reg.GetCode())
           mov(reg, GetReg<RA_64>(Op->Value.ID()));
         break;
     }
   } else if (Op->Class == IR::FPRClass) {
-    auto regId = (Op->Offset - offsetof(FEXCore::Core::ThreadState, State.xmm[0][0])) / 16;
+    auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0])) / 16;
     auto regOffs = Op->Offset & 15;
 
-    LogMan::Throw::A(regId < SRAFPR.size(), "regId out of range");
+    LOGMAN_THROW_A(regId < SRAFPR.size(), "regId out of range");
 
     auto guest = SRAFPR[regId];
     auto host = GetSrc(Op->Value.ID());
@@ -229,28 +233,28 @@ DEF_OP(StoreRegister) {
         break;
 
       case 2:
-        LogMan::Throw::A((regOffs & 1) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A((regOffs & 1) == 0, "unexpected regOffs");
         ins(guest.V8H(), regOffs/2, host.V8H(), 0);
         break;
 
       case 4:
-        LogMan::Throw::A((regOffs & 3) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A((regOffs & 3) == 0, "unexpected regOffs");
         ins(guest.V4S(), regOffs/4, host.V4S(), 0);
         break;
 
       case 8:
-        LogMan::Throw::A((regOffs & 7) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A((regOffs & 7) == 0, "unexpected regOffs");
         ins(guest.V2D(), regOffs / 8, host.V2D(), 0);
         break;
 
       case 16:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
         if (guest.GetCode() != host.GetCode())
           mov(guest.Q(), host.Q());
         break;
     }
   } else {
-    LogMan::Throw::A(false, "Unhandled Op->Class %d", Op->Class);
+    LOGMAN_THROW_A(false, "Unhandled Op->Class %d", Op->Class);
   }
 }
 
@@ -284,15 +288,15 @@ DEF_OP(LoadContextIndexed) {
         ldr(GetReg<RA_64>(Node), MemOperand(TMP1, Op->BaseOffset));
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
       }
       break;
     }
     case 16:
-      LogMan::Msg::A("Invalid Class load of size 16");
+      LOGMAN_MSG_A("Invalid Class load of size 16");
       break;
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
     }
   }
   else {
@@ -329,12 +333,12 @@ DEF_OP(LoadContextIndexed) {
         }
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
       }
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
     }
   }
 }
@@ -370,15 +374,15 @@ DEF_OP(StoreContextIndexed) {
         str(value, MemOperand(TMP1, Op->BaseOffset));
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
       }
       break;
     }
     case 16:
-      LogMan::Msg::A("Invalid Class load of size 16");
+      LOGMAN_MSG_A("Invalid Class load of size 16");
       break;
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
     }
   }
   else {
@@ -417,12 +421,12 @@ DEF_OP(StoreContextIndexed) {
         }
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
       }
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
     }
   }
 }
@@ -450,7 +454,7 @@ DEF_OP(SpillRegister) {
       str(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -466,10 +470,10 @@ DEF_OP(SpillRegister) {
       str(GetSrc(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
     }
   } else {
-    LogMan::Msg::A("Unhandled SpillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A("Unhandled SpillRegister class: %d", Op->Class.Val);
   }
 }
 
@@ -496,7 +500,7 @@ DEF_OP(FillRegister) {
       ldr(GetReg<RA_64>(Node), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -512,10 +516,10 @@ DEF_OP(FillRegister) {
       ldr(GetDst(Node), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
     }
   } else {
-    LogMan::Msg::A("Unhandled FillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A("Unhandled FillRegister class: %d", Op->Class.Val);
   }
 }
 
@@ -530,12 +534,12 @@ DEF_OP(StoreFlag) {
   strb(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag));
 }
 
-MemOperand JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) {
+MemOperand Arm64JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) {
   if (Offset.IsInvalid()) {
     return MemOperand(Base);
   } else {
     if (OffsetScale != 1 && OffsetScale != AccessSize) {
-        LogMan::Msg::A("Unhandled GenerateMemOperand OffsetScale: %d", OffsetScale);
+        LOGMAN_MSG_A("Unhandled GenerateMemOperand OffsetScale: %d", OffsetScale);
     }
     uint64_t Const;
     if (IsInlineConstant(Offset, &Const)) {
@@ -547,10 +551,12 @@ MemOperand JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Register Bas
         case IR::MEM_OFFSET_UXTW.Val: return MemOperand(Base, RegOffset.W(), Extend::UXTW, (int)std::log2(OffsetScale) );
         case IR::MEM_OFFSET_SXTW.Val: return MemOperand(Base, RegOffset.W(), Extend::SXTW, (int)std::log2(OffsetScale) );
 
-        default: LogMan::Msg::A("Unhandled GenerateMemOperand OffsetType: %d", OffsetType.Val); break;
+        default: LOGMAN_MSG_A("Unhandled GenerateMemOperand OffsetType: %d", OffsetType.Val); break;
       }
     }
   }
+
+  FEX_UNREACHABLE;
 }
 
 DEF_OP(LoadMem) {
@@ -574,7 +580,7 @@ DEF_OP(LoadMem) {
       case 8:
         ldr(Dst, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
     }
   }
   else {
@@ -595,7 +601,7 @@ DEF_OP(LoadMem) {
       case 16:
         ldr(Dst, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
     }
   }
 }
@@ -606,7 +612,7 @@ DEF_OP(LoadMemTSO) {
   auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
 
   if (!Op->Offset.IsInvalid()) {
-    LogMan::Msg::A("LoadMemTSO: No offset allowed");
+    LOGMAN_MSG_A("LoadMemTSO: No offset allowed");
   }
 
   if (SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
@@ -629,7 +635,7 @@ DEF_OP(LoadMemTSO) {
         case 8:
           ldapr(Dst, MemSrc);
           break;
-        default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
       }
       nop();
     }
@@ -654,7 +660,7 @@ DEF_OP(LoadMemTSO) {
         case 8:
           ldar(Dst, MemSrc);
           break;
-        default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
       }
       nop();
     }
@@ -675,7 +681,7 @@ DEF_OP(LoadMemTSO) {
       case 16:
         ldr(Dst, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
     }
     dmb(InnerShareable, BarrierAll);
   }
@@ -702,7 +708,7 @@ DEF_OP(StoreMem) {
       case 8:
         str(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
     }
   }
   else {
@@ -723,7 +729,7 @@ DEF_OP(StoreMem) {
       case 16:
         str(Src, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
     }
   }
 }
@@ -733,7 +739,7 @@ DEF_OP(StoreMemTSO) {
   auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
 
   if (!Op->Offset.IsInvalid()) {
-    LogMan::Msg::A("StoreMemTSO: No offset allowed");
+    LOGMAN_MSG_A("StoreMemTSO: No offset allowed");
   }
 
   if (Op->Class == FEXCore::IR::GPRClass) {
@@ -753,7 +759,7 @@ DEF_OP(StoreMemTSO) {
         case 8:
           stlr(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
           break;
-        default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
       }
       nop();
     }
@@ -777,23 +783,182 @@ DEF_OP(StoreMemTSO) {
       case 16:
         str(Src, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
     }
     dmb(InnerShareable, BarrierAll);
   }
 }
 
+DEF_OP(ParanoidLoadMemTSO) {
+  auto Op = IROp->C<IR::IROp_LoadMemTSO>();
+
+  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
+
+  if (!Op->Offset.IsInvalid()) {
+    LOGMAN_MSG_A("LoadMemTSO: No offset allowed");
+  }
+
+  if (Op->Class == FEXCore::IR::GPRClass) {
+    if (Op->Size == 1) {
+      // 8bit load is always aligned to natural alignment
+      auto Dst = GetReg<RA_64>(Node);
+      ldarb(Dst, MemSrc);
+    }
+    else {
+      auto Dst = GetReg<RA_64>(Node);
+      nop();
+      switch (Op->Size) {
+        case 2:
+          ldarh(Dst, MemSrc);
+          break;
+        case 4:
+          ldar(Dst.W(), MemSrc);
+          break;
+        case 8:
+          ldar(Dst, MemSrc);
+          break;
+        default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+      }
+      nop();
+    }
+  }
+  else {
+    auto Dst = GetDst(Node);
+    switch (Op->Size) {
+      case 2:
+        nop();
+        ldarh(TMP1, MemSrc);
+        nop();
+        fmov(Dst, TMP1);
+        break;
+      case 4:
+        nop();
+        ldar(TMP1.W(), MemSrc);
+        nop();
+        fmov(Dst, TMP1);
+        break;
+      case 8:
+        nop();
+        ldar(TMP1, MemSrc);
+        nop();
+        fmov(Dst, TMP1);
+        break;
+      case 16:
+        nop();
+        ldaxp(TMP1, TMP2, MemSrc);
+        clrex();
+        mov(Dst.V2D(), 0, TMP1);
+        mov(Dst.V2D(), 1, TMP2);
+        break;
+      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+    }
+  }
+}
+
+DEF_OP(ParanoidStoreMemTSO) {
+  auto Op = IROp->C<IR::IROp_StoreMemTSO>();
+  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
+
+  if (!Op->Offset.IsInvalid()) {
+    LOGMAN_MSG_A("StoreMemTSO: No offset allowed");
+  }
+
+  if (Op->Class == FEXCore::IR::GPRClass) {
+    if (Op->Size == 1) {
+      // 8bit load is always aligned to natural alignment
+      stlrb(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+    }
+    else {
+      nop();
+      switch (Op->Size) {
+        case 2:
+          stlrh(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+          break;
+        case 4:
+          stlr(GetReg<RA_32>(Op->Header.Args[1].ID()), MemSrc);
+          break;
+        case 8:
+          stlr(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+          break;
+        default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
+      }
+      nop();
+    }
+  }
+  else {
+    auto Src = GetSrc(Op->Header.Args[1].ID());
+    if (Op->Size == 1) {
+      // 8bit load is always aligned to natural alignment
+      mov(TMP1, Src.V4S(), 0);
+      stlrb(TMP1, MemSrc);
+    }
+    else {
+      switch (Op->Size) {
+        case 2:
+          mov(TMP1, Src.V4S(), 0);
+          nop();
+          stlrh(TMP1, MemSrc);
+          nop();
+          break;
+        case 4:
+          mov(TMP1, Src.V4S(), 0);
+          nop();
+          stlr(TMP1.W(), MemSrc);
+          nop();
+          break;
+        case 8:
+          mov(TMP1, Src.V2D(), 0);
+          nop();
+          stlr(TMP1, MemSrc);
+          nop();
+          break;
+        case 16: {
+          // Move vector to GPRs
+          mov(TMP1, Src.V2D(), 0);
+          mov(TMP2, Src.V2D(), 1);
+          Label B;
+          bind(&B);
+
+          nop(); // < Overwritten with DMB
+          // ldaxp must not have both the destination registers be the same
+          ldaxp(xzr, TMP3, MemSrc); // <- Can hit SIGBUS
+          nop(); // < Overwritten with DMB
+          stlxp(TMP3, TMP1, TMP2, MemSrc); // <- Can also hit SIGBUS
+          cbnz(TMP3, &B); // < Overwritten with DMB
+          break;
+        }
+        default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
+      }
+    }
+  }
+}
+
 DEF_OP(VLoadMemElement) {
-  LogMan::Msg::A("Unimplemented");
+  LOGMAN_MSG_A("Unimplemented");
 }
 
 DEF_OP(VStoreMemElement) {
-  LogMan::Msg::A("Unimplemented");
+  LOGMAN_MSG_A("Unimplemented");
+}
+
+DEF_OP(CacheLineClear) {
+  auto Op = IROp->C<IR::IROp_CacheLineClear>();
+
+  auto MemReg = GetReg<RA_64>(Op->Header.Args[0].ID());
+
+  // Clear dcache only
+  // icache doesn't matter here since the guest application shouldn't be calling clflush on JIT code.
+  mov(TMP1, MemReg);
+  for (size_t i = 0; i < std::max(1U, DCacheLineSize / 64U); ++i) {
+    dc(DataCacheOp::CVAU, TMP1);
+    add(TMP1, TMP1, DCacheLineSize);
+  }
+  dsb(InnerShareable, BarrierAll);
 }
 
 #undef DEF_OP
-void JITCore::RegisterMemoryHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterMemoryHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(LOADCONTEXT,         LoadContext);
   REGISTER_OP(STORECONTEXT,        StoreContext);
   REGISTER_OP(LOADREGISTER,        LoadRegister);
@@ -806,10 +971,17 @@ void JITCore::RegisterMemoryHandlers() {
   REGISTER_OP(STOREFLAG,           StoreFlag);
   REGISTER_OP(LOADMEM,             LoadMem);
   REGISTER_OP(STOREMEM,            StoreMem);
-  REGISTER_OP(LOADMEMTSO,          LoadMemTSO);
-  REGISTER_OP(STOREMEMTSO,         StoreMemTSO);
+  if (ParanoidTSO()) {
+    REGISTER_OP(LOADMEMTSO,          ParanoidLoadMemTSO);
+    REGISTER_OP(STOREMEMTSO,         ParanoidStoreMemTSO);
+  }
+  else {
+    REGISTER_OP(LOADMEMTSO,          LoadMemTSO);
+    REGISTER_OP(STOREMEMTSO,         StoreMemTSO);
+  }
   REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
   REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
+  REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp

@@ -1,10 +1,23 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
+static void PrintValue(uint64_t Value) {
+  LogMan::Msg::D("Value: 0x%lx", Value);
+}
+
+static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
+  LogMan::Msg::D("Value: 0x%016lx'%016lx", ValueUpper, Value);
+}
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(Fence) {
   auto Op = IROp->C<IR::IROp_Fence>();
@@ -18,7 +31,7 @@ DEF_OP(Fence) {
     case IR::Fence_Store.Val:
       dmb(FullSystem, BarrierWrites);
       break;
-    default: LogMan::Msg::A("Unknown Fence: %d", Op->Fence); break;
+    default: LOGMAN_MSG_A("Unknown Fence: %d", Op->Fence); break;
   }
 }
 
@@ -29,32 +42,38 @@ DEF_OP(Break) {
     case 5: // Guest ud2
       hlt(4);
       break;
+    case 1: // Int <imm8>
+      hlt(4);
+      break;
+    case 2: // overflow
+      hlt(4);
+      break;
+    case 3: // int 1
+      hlt(4);
+      break;
     case 4: { // HLT
       // Time to quit
       // Set our stack to the starting stack location
-      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)));
+      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)));
       add(sp, TMP1, 0);
 
       // Now we need to jump to the thread stop handler
-      LoadConstant(TMP1, ThreadStopHandlerAddressSpillSRA);
+      LoadConstant(TMP1, ThreadSharedData.Dispatcher->ThreadStopHandlerAddressSpillSRA);
       br(TMP1);
       break;
     }
     case 6: { // INT3
-      if (SpillSlots) {
-        add(sp, sp, SpillSlots * 16);
-      }
+      ResetStack();
 
-      LoadConstant(TMP1, ThreadPauseHandlerAddressSpillSRA);
+      LoadConstant(TMP1, ThreadSharedData.Dispatcher->ThreadPauseHandlerAddressSpillSRA);
       br(TMP1);
       break;
     }
-    default: LogMan::Msg::A("Unknown Break reason: %d", Op->Reason);
+    default: LOGMAN_MSG_A("Unknown Break reason: %d", Op->Reason);
   }
 }
 
 DEF_OP(GetRoundingMode) {
-  auto Op = IROp->C<IR::IROp_GetRoundingMode>();
   auto Dst = GetReg<RA_64>(Node);
   mrs(Dst, FPCR);
   lsr(Dst, Dst,  22);
@@ -112,9 +131,31 @@ DEF_OP(SetRoundingMode) {
   msr(FPCR, TMP1);
 }
 
+DEF_OP(Print) {
+  auto Op = IROp->C<IR::IROp_Print>();
+
+  PushDynamicRegsAndLR();
+
+  if (IsGPR(Op->Header.Args[0].ID())) {
+    mov(x0, GetReg<RA_64>(Op->Header.Args[0].ID()));
+    LoadConstant(x3, reinterpret_cast<uint64_t>(PrintValue));
+  }
+  else {
+    fmov(x0, GetSrc(Op->Header.Args[0].ID()).V1D());
+    // Bug in vixl that source vector needs to b V1D rather than V2D?
+    fmov(x1, GetSrc(Op->Header.Args[0].ID()).V1D(), 1);
+    LoadConstant(x3, reinterpret_cast<uint64_t>(PrintVectorValue));
+  }
+  SpillStaticRegs();
+  blr(x3);
+  FillStaticRegs();
+
+  PopDynamicRegsAndLR();
+}
+
 #undef DEF_OP
-void JITCore::RegisterMiscHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterMiscHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(DUMMY,      NoOp);
   REGISTER_OP(IRHEADER,   NoOp);
   REGISTER_OP(CODEBLOCK,  NoOp);
@@ -124,7 +165,7 @@ void JITCore::RegisterMiscHandlers() {
   REGISTER_OP(BREAK,      Break);
   REGISTER_OP(PHI,        NoOp);
   REGISTER_OP(PHIVALUE,   NoOp);
-  REGISTER_OP(PRINT,      Unhandled);
+  REGISTER_OP(PRINT,      Print);
   REGISTER_OP(GETROUNDINGMODE, GetRoundingMode);
   REGISTER_OP(SETROUNDINGMODE, SetRoundingMode);
   REGISTER_OP(INVALIDATEFLAGS,   NoOp);

External/FEXCore/Source/Interface/Core/JIT/Arm64/MoveOps.cpp

@@ -1,10 +1,16 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(ExtractElementPair) {
   auto Op = IROp->C<IR::IROp_ExtractElementPair>();
   switch (Op->Header.Size) {
@@ -20,7 +26,7 @@ DEF_OP(ExtractElementPair) {
       mov (GetReg<RA_64>(Node), Regs[Op->Element]);
       break;
     }
-    default: LogMan::Msg::A("Unknown Size"); break;
+    default: LOGMAN_MSG_A("Unknown Size"); break;
   }
 }
 
@@ -29,21 +35,24 @@ DEF_OP(CreateElementPair) {
   std::pair<aarch64::Register, aarch64::Register> Dst;
   aarch64::Register RegFirst;
   aarch64::Register RegSecond;
+  aarch64::Register RegTmp;
 
   switch (Op->Header.Size) {
     case 4: {
       Dst = GetSrcPair<RA_32>(Node);
       RegFirst = GetReg<RA_32>(Op->Header.Args[0].ID());
       RegSecond = GetReg<RA_32>(Op->Header.Args[1].ID());
+      RegTmp = w0;
       break;
     }
     case 8: {
       Dst = GetSrcPair<RA_64>(Node);
       RegFirst = GetReg<RA_64>(Op->Header.Args[0].ID());
       RegSecond = GetReg<RA_64>(Op->Header.Args[1].ID());
+      RegTmp = x0;
       break;
     }
-    default: LogMan::Msg::A("Unknown Size"); break;
+    default: LOGMAN_MSG_A("Unknown Size"); break;
   }
 
   if (Dst.first.GetCode() != RegSecond.GetCode()) {
@@ -53,7 +62,9 @@ DEF_OP(CreateElementPair) {
     mov(Dst.second, RegSecond);
     mov(Dst.first, RegFirst);
   } else {
-    LogMan::Msg::A("Unhandled CreateElementPair");
+    mov(RegTmp, RegFirst);
+    mov(Dst.second, RegSecond);
+    mov(Dst.first, RegTmp);
   }
 }
 
@@ -63,8 +74,8 @@ DEF_OP(Mov) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterMoveHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterMoveHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(EXTRACTELEMENTPAIR, ExtractElementPair);
   REGISTER_OP(CREATEELEMENTPAIR,  CreateElementPair);
   REGISTER_OP(MOV,                Mov);

External/FEXCore/Source/Interface/Core/JIT/JITCore.h

@@ -1,5 +1,7 @@
 #pragma once
 
+#include <memory>
+
 namespace FEXCore::Context {
 struct Context;
 }
@@ -11,5 +13,6 @@ struct InternalThreadState;
 namespace FEXCore::CPU {
 class CPUBackend;
 
-FEXCore::CPU::CPUBackend *CreateJITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
+std::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
+std::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp

@@ -1,8 +1,14 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(TruncElementPair) {
   auto Op = IROp->C<IR::IROp_TruncElementPair>();
 
@@ -14,7 +20,7 @@ DEF_OP(TruncElementPair) {
       mov(Dst.second, Src.second);
       break;
     }
-    default: LogMan::Msg::A("Unhandled Truncation size: %d", Op->Size); break;
+    default: LOGMAN_MSG_A("Unhandled Truncation size: %d", Op->Size); break;
   }
 }
 
@@ -23,17 +29,28 @@ DEF_OP(Constant) {
   mov(GetDst<RA_64>(Node), Op->Constant);
 }
 
+DEF_OP(EntrypointOffset) {
+  auto Op = IROp->C<IR::IROp_EntrypointOffset>();
+
+  auto Constant = Entry + Op->Offset;
+  mov(GetDst<RA_64>(Node), Constant);
+}
+
 DEF_OP(InlineConstant) {
   //nop
 }
 
+DEF_OP(InlineEntrypointOffset) {
+  //nop
+}
+
 DEF_OP(CycleCounter) {
 #ifdef DEBUG_CYCLES
   mov (GetDst<RA_64>(Node), 0);
 #else
   rdtsc();
   shl(rdx, 32);
-  or(rax, rdx);
+  or_(rax, rdx);
   mov (GetDst<RA_64>(Node), rax);
 #endif
 }
@@ -53,7 +70,7 @@ DEF_OP(Add) {
     case 8:
       add(rax, Const);
       break;
-    default:  LogMan::Msg::A("Unhandled Add size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled Add size: %d", OpSize);
       break;
     }
   } else {
@@ -64,7 +81,7 @@ DEF_OP(Add) {
     case 8:
       add(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled Add size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled Add size: %d", OpSize);
       break;
     }
   }
@@ -86,7 +103,7 @@ DEF_OP(Sub) {
     case 8:
       sub(rax, Const);
       break;
-    default:  LogMan::Msg::A("Unhandled Sub size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled Sub size: %d", OpSize);
       break;
     }
   } else {
@@ -97,7 +114,7 @@ DEF_OP(Sub) {
     case 8:
       sub(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled Sub size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled Sub size: %d", OpSize);
       break;
     }
   }
@@ -119,7 +136,7 @@ DEF_OP(Neg) {
     Src = GetSrc<RA_64>(Op->Header.Args[0].ID());
     Dst = GetDst<RA_64>(Node);
     break;
-  default:  LogMan::Msg::A("Unhandled Neg size: %d", OpSize);
+  default:  LOGMAN_MSG_A("Unhandled Neg size: %d", OpSize);
     break;
   }
   mov(Dst, Src);
@@ -143,7 +160,7 @@ DEF_OP(Mul) {
     imul(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(Dst, rax);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
   }
 }
 
@@ -162,7 +179,7 @@ DEF_OP(UMul) {
     mul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rax);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
   }
 }
 
@@ -201,7 +218,7 @@ DEF_OP(Div) {
     mov(GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV Size: %d", Size); break;
+  default: LOGMAN_MSG_A("Unknown UDIV Size: %d", Size); break;
   }
 }
 
@@ -244,7 +261,7 @@ DEF_OP(UDiv) {
     mov(GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV OpSize: %d", OpSize); break;
+  default: LOGMAN_MSG_A("Unknown UDIV OpSize: %d", OpSize); break;
   }
 }
 
@@ -281,7 +298,7 @@ DEF_OP(Rem) {
     mov(GetDst<RA_64>(Node), rdx);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV Size: %d", OpSize); break;
+  default: LOGMAN_MSG_A("Unknown UDIV Size: %d", OpSize); break;
   }
 }
 
@@ -324,7 +341,7 @@ DEF_OP(URem) {
     mov(GetDst<RA_64>(Node), rdx);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV OpSize: %d", OpSize); break;
+  default: LOGMAN_MSG_A("Unknown UDIV OpSize: %d", OpSize); break;
   }
 }
 
@@ -343,7 +360,7 @@ DEF_OP(MulH) {
     imul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rdx);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
   }
 }
 
@@ -362,7 +379,7 @@ DEF_OP(UMulH) {
     mul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rdx);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
   }
 }
 
@@ -373,9 +390,9 @@ DEF_OP(Or) {
 
   uint64_t Const;
   if (IsInlineConstant(Op->Header.Args[1], &Const)) {
-    or (rax, Const);
+    or_(rax, Const);
   } else {
-    or (rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
+    or_(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
   }
   mov(Dst, rax);
 }
@@ -386,9 +403,9 @@ DEF_OP(And) {
   mov(rax, GetSrc<RA_64>(Op->Header.Args[0].ID()));
   uint64_t Const;
   if (IsInlineConstant(Op->Header.Args[1], &Const)) {
-    and (rax, Const);
+    and_(rax, Const);
   } else {
-    and(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
+    and_(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
   }
   mov(Dst, rax);
 }
@@ -399,9 +416,9 @@ DEF_OP(Xor) {
   mov(rax, GetSrc<RA_64>(Op->Header.Args[0].ID()));
   uint64_t Const;
   if (IsInlineConstant(Op->Header.Args[1], &Const)) {
-    xor(rax, Const);
+    xor_(rax, Const);
   } else {
-    xor(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
+    xor_(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
   }
   mov(Dst, rax);
 }
@@ -424,11 +441,11 @@ DEF_OP(Lshl) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shl(GetDst<RA_64>(Node), Const);
         break;
-      default: LogMan::Msg::A("Unknown LSHL Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A("Unknown LSHL Size: %d\n", OpSize); break;
     };
   } else {
     mov(rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
-    and(rcx, Mask);
+    and_(rcx, Mask);
 
     switch (OpSize) {
       case 4:
@@ -439,7 +456,7 @@ DEF_OP(Lshl) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shl(GetDst<RA_64>(Node), cl);
         break;
-      default: LogMan::Msg::A("Unknown LSHL Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A("Unknown LSHL Size: %d\n", OpSize); break;
     };
   }
 }
@@ -471,12 +488,12 @@ DEF_OP(Lshr) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shr(GetDst<RA_64>(Node), Const);
         break;
-      default: LogMan::Msg::A("Unknown Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A("Unknown Size: %d\n", OpSize); break;
     };
 
   } else {
     mov (rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
-    and(rcx, Mask);
+    and_(rcx, Mask);
 
     switch (OpSize) {
       case 1:
@@ -495,7 +512,7 @@ DEF_OP(Lshr) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shr(GetDst<RA_64>(Node), cl);
         break;
-      default: LogMan::Msg::A("Unknown Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A("Unknown Size: %d\n", OpSize); break;
     };
   }
 }
@@ -529,12 +546,12 @@ DEF_OP(Ashr) {
       mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       sar(GetDst<RA_64>(Node), Const);
     break;
-    default: LogMan::Msg::A("Unknown ASHR Size: %d\n", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown ASHR Size: %d\n", OpSize); break;
     };
 
   } else {
     mov (rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
-    and(rcx, Mask);
+    and_(rcx, Mask);
     switch (OpSize) {
     case 1:
       movsx(rax, GetSrc<RA_8>(Op->Header.Args[0].ID()));
@@ -554,7 +571,7 @@ DEF_OP(Ashr) {
       mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       sar(GetDst<RA_64>(Node), cl);
     break;
-    default: LogMan::Msg::A("Unknown ASHR Size: %d\n", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown ASHR Size: %d\n", OpSize); break;
     };
   }
 }
@@ -579,11 +596,11 @@ DEF_OP(Ror) {
         ror(rax, Const);
       break;
       }
-      default: LogMan::Msg::A("Unknown ROR Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A("Unknown ROR Size: %d\n", OpSize); break;
     }
   } else {
     mov (rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
-    and(rcx, Mask);
+    and_(rcx, Mask);
     switch (OpSize) {
       case 4: {
         mov(eax, GetSrc<RA_32>(Op->Header.Args[0].ID()));
@@ -595,7 +612,7 @@ DEF_OP(Ror) {
         ror(rax, cl);
       break;
       }
-      default: LogMan::Msg::A("Unknown ROR Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A("Unknown ROR Size: %d\n", OpSize); break;
     }
   }
   mov(GetDst<RA_64>(Node), rax);
@@ -651,7 +668,7 @@ DEF_OP(LDiv) {
       mov(GetDst<RA_64>(Node), rax);
       break;
     }
-    default: LogMan::Msg::A("Unknown LDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown LDIV OpSize: %d", OpSize); break;
   }
 }
 
@@ -683,7 +700,7 @@ DEF_OP(LUDiv) {
       mov(GetDst<RA_64>(Node), rax);
       break;
     }
-    default: LogMan::Msg::A("Unknown LUDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown LUDIV OpSize: %d", OpSize); break;
   }
 }
 
@@ -715,7 +732,7 @@ DEF_OP(LRem) {
       mov(GetDst<RA_64>(Node), rdx);
       break;
     }
-    default: LogMan::Msg::A("Unknown LREM OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown LREM OpSize: %d", OpSize); break;
   }
 }
 
@@ -747,7 +764,7 @@ DEF_OP(LURem) {
       mov(GetDst<RA_64>(Node), rdx);
       break;
     }
-    default: LogMan::Msg::A("Unknown LUDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown LUDIV OpSize: %d", OpSize); break;
   }
 }
 
@@ -790,10 +807,10 @@ DEF_OP(FindLSB) {
   bsf(rcx, GetSrc<RA_64>(Op->Header.Args[0].ID()));
   mov(rax, 0x40);
   cmovz(rcx, rax);
-  xor(rax, rax);
+  xor_(rax, rax);
   cmp(GetSrc<RA_64>(Op->Header.Args[0].ID()), 1);
   sbb(rax, rax);
-  or(rax, rcx);
+  or_(rax, rcx);
   mov (GetDst<RA_64>(Node), rax);
 }
 
@@ -812,7 +829,7 @@ DEF_OP(FindMSB) {
     case 8:
       bsr(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unknown OpSize: %d", OpSize);
+    default: LOGMAN_MSG_A("Unknown OpSize: %d", OpSize);
   }
 }
 
@@ -836,7 +853,7 @@ DEF_OP(FindTrailingZeros) {
       mov(rax, 0x40);
       cmovz(GetDst<RA_64>(Node), rax);
       break;
-    default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
   }
 }
 
@@ -859,7 +876,7 @@ DEF_OP(CountLeadingZeroes) {
         lzcnt(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         break;
       }
-      default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+      default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
     }
   }
   else {
@@ -870,7 +887,7 @@ DEF_OP(CountLeadingZeroes) {
         Label Skip;
         je(Skip);
           bsr(ax, GetSrc<RA_16>(Op->Header.Args[0].ID()));
-          xor(ax, 0xF);
+          xor_(ax, 0xF);
           movzx(eax, ax);
         L(Skip);
         mov(GetDst<RA_32>(Node), eax);
@@ -882,7 +899,7 @@ DEF_OP(CountLeadingZeroes) {
         Label Skip;
         je(Skip);
           bsr(eax, GetSrc<RA_32>(Op->Header.Args[0].ID()));
-          xor(eax, 0x1F);
+          xor_(eax, 0x1F);
         L(Skip);
         mov(GetDst<RA_32>(Node), eax);
         break;
@@ -893,12 +910,12 @@ DEF_OP(CountLeadingZeroes) {
         Label Skip;
         je(Skip);
           bsr(rax, GetSrc<RA_64>(Op->Header.Args[0].ID()));
-          xor(rax, 0x3F);
+          xor_(rax, 0x3F);
         L(Skip);
         mov(GetDst<RA_64>(Node), rax);
         break;
       }
-      default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+      default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
     }
   }
 }
@@ -920,7 +937,7 @@ DEF_OP(Rev) {
       mov (GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       bswap(GetDst<RA_64>(Node).cvt64());
       break;
-    default: LogMan::Msg::A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A("Unknown REV size: %d", OpSize); break;
   }
 }
 
@@ -939,15 +956,15 @@ DEF_OP(Bfi) {
   mov(Dst, GetSrc<RA_64>(Op->Header.Args[0].ID()));
 
   mov(TMP2, DestMask);
-  and(Dst, TMP2);
+  and_(Dst, TMP2);
   mov(TMP2, SourceMask);
-  and(TMP1, TMP2);
+  and_(TMP1, TMP2);
   shl(TMP1, Op->lsb);
   or_(Dst, TMP1);
 
   if (OpSize != 8) {
     mov(rcx, uint64_t((1ULL << (OpSize * 8)) - 1));
-    and(Dst, rcx);
+    and_(Dst, rcx);
   }
 }
 
@@ -955,7 +972,7 @@ DEF_OP(Bfe) {
   auto Op = IROp->C<IR::IROp_Bfe>();
   uint8_t OpSize = IROp->Size;
 
-  LogMan::Throw::A(OpSize <= 8, "OpSize is too large for BFE: %d", OpSize);
+  LOGMAN_THROW_A(OpSize <= 8, "OpSize is too large for BFE: %d", OpSize);
 
   auto Dst = GetDst<RA_64>(Node);
 
@@ -987,7 +1004,7 @@ DEF_OP(Bfe) {
 
   if (Op->Width != 64) {
     mov(rcx, uint64_t((1ULL << Op->Width) - 1));
-    and(Dst, rcx);
+    and_(Dst, rcx);
   }
 }
 
@@ -1056,7 +1073,7 @@ DEF_OP(Select) {
 
   if (is_const_true || is_const_false) {
     if (is_const_false != true || is_const_true != true || const_true != 1 || const_false != 0) {
-      LogMan::Msg::A("Select: Unsupported compare inline parameters");
+      LOGMAN_MSG_A("Select: Unsupported compare inline parameters");
     }
     (this->*SetCC)(al);
     movzx(Dst, al);
@@ -1087,46 +1104,67 @@ DEF_OP(VExtractToGPR) {
       pextrq(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Idx);
     break;
     }
-    default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
   }
 }
 
-DEF_OP(Float_ToGPR_ZU) {
-  LogMan::Msg::D("Unimplemented");
-}
-
 DEF_OP(Float_ToGPR_ZS) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_ZS>();
-  if (Op->Header.ElementSize == 8) {
-    cvttsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
-  }
-  else {
-    cvttss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
-  }
-}
 
-DEF_OP(Float_ToGPR_U) {
-  LogMan::Msg::D("Unimplemented");
+  uint16_t Conv = (IROp->Size << 8) | Op->SrcElementSize;
+  switch (Conv) {
+    case 0x0804: // int64_t <- float
+      cvttss2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0808: // int64_t <- double
+      cvttsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0404: // int32_t <- float
+      cvttss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0408: // int32_t <- double
+      cvttsd2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+  }
 }
 
 DEF_OP(Float_ToGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_S>();
-  if (Op->Header.ElementSize == 8) {
-    cvtsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
-  }
-  else {
-    cvtss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+  uint16_t Conv = (IROp->Size << 8) | Op->SrcElementSize;
+  switch (Conv) {
+    case 0x0804: // int64_t <- float
+      cvtss2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0808: // int64_t <- double
+      cvtsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0404: // int32_t <- float
+      cvtss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0408: // int32_t <- double
+      cvtsd2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
   }
 }
 
 DEF_OP(FCmp) {
   auto Op = IROp->C<IR::IROp_FCmp>();
 
-  if (Op->ElementSize == 4) {
-    ucomiss(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+  if (Op->Flags & (1 << IR::FCMP_FLAG_UNORDERED)) {
+    if (Op->ElementSize == 4) {
+      ucomiss(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
+    else {
+      ucomisd(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
   }
   else {
-    ucomisd(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    if (Op->ElementSize == 4) {
+      comiss(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
+    else {
+      comisd(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
   }
   mov (rdx, 0);
 
@@ -1136,32 +1174,34 @@ DEF_OP(FCmp) {
     mov(rcx, 0);
     setb(cl);
     shl(rcx, IR::FCMP_FLAG_LT);
-    or(rdx, rcx);
+    or_(rdx, rcx);
   }
   if (Op->Flags & (1 << IR::FCMP_FLAG_UNORDERED)) {
     sahf();
     mov(rcx, 0);
     setp(cl);
     shl(rcx, IR::FCMP_FLAG_UNORDERED);
-    or(rdx, rcx);
+    or_(rdx, rcx);
   }
   if (Op->Flags & (1 << IR::FCMP_FLAG_EQ)) {
     sahf();
     mov(rcx, 0);
     setz(cl);
     shl(rcx, IR::FCMP_FLAG_EQ);
-    or(rdx, rcx);
+    or_(rdx, rcx);
   }
   mov (GetDst<RA_64>(Node), rdx);
 }
 
 #undef DEF_OP
 
-void JITCore::RegisterALUHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterALUHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(TRUNCELEMENTPAIR,  TruncElementPair);
   REGISTER_OP(CONSTANT,          Constant);
+  REGISTER_OP(ENTRYPOINTOFFSET,  EntrypointOffset);
   REGISTER_OP(INLINECONSTANT,    InlineConstant);
+  REGISTER_OP(INLINEENTRYPOINTOFFSET,  InlineEntrypointOffset);
   REGISTER_OP(CYCLECOUNTER,      CycleCounter);
   REGISTER_OP(ADD,               Add);
   REGISTER_OP(SUB,               Sub);
@@ -1198,9 +1238,7 @@ void JITCore::RegisterALUHandlers() {
   REGISTER_OP(SBFE,              Sbfe);
   REGISTER_OP(SELECT,            Select);
   REGISTER_OP(VEXTRACTTOGPR,     VExtractToGPR);
-  REGISTER_OP(FLOAT_TOGPR_ZU,    Float_ToGPR_ZU);
   REGISTER_OP(FLOAT_TOGPR_ZS,    Float_ToGPR_ZS);
-  REGISTER_OP(FLOAT_TOGPR_U,     Float_ToGPR_U);
   REGISTER_OP(FLOAT_TOGPR_S,     Float_ToGPR_S);
   REGISTER_OP(FCMP,              FCmp);
 #undef REGISTER_OP

External/FEXCore/Source/Interface/Core/JIT/x86_64/AtomicOps.cpp

@@ -1,8 +1,14 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(CASPair) {
   auto Op = IROp->C<IR::IROp_CAS>();
   uint8_t OpSize = IROp->Size;
@@ -49,7 +55,7 @@ DEF_OP(CASPair) {
       mov(Dst.second, rdx);
     break;
     }
-    default: LogMan::Msg::A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A("Unsupported: %d", OpSize);
   }
 }
 
@@ -68,7 +74,6 @@ DEF_OP(CAS) {
 
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[2].ID());
 
-  mov(rdx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
   mov(rax, GetSrc<RA_64>(Op->Header.Args[0].ID()));
 
   // RCX now contains pointer
@@ -76,31 +81,31 @@ DEF_OP(CAS) {
   // RDX contains our desired
 
   lock();
-
   switch (OpSize) {
   case 1: {
-    cmpxchg(byte [MemReg], dl);
-    movzx(rax, al);
+    cmpxchg(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+    movzx(GetDst<RA_64>(Node), al);
   break;
   }
   case 2: {
-    cmpxchg(word [MemReg], dx);
-    movzx(rax, ax);
+    cmpxchg(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+    movzx(GetDst<RA_64>(Node), ax);
   break;
   }
   case 4: {
-    cmpxchg(dword [MemReg], edx);
+    cmpxchg(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+    // RAX now contains the result
+    mov (GetDst<RA_64>(Node), eax);
   break;
   }
   case 8: {
-    cmpxchg(qword [MemReg], rdx);
+    cmpxchg(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+    // RAX now contains the result
+    mov (GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LogMan::Msg::A("Unsupported: %d", OpSize);
+  default: LOGMAN_MSG_A("Unsupported: %d", OpSize);
   }
-
-  // RAX now contains the result
-  mov (GetDst<RA_64>(Node), rax);
 }
 
 DEF_OP(AtomicAdd) {
@@ -122,7 +127,7 @@ DEF_OP(AtomicAdd) {
     case 8:
       add(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
   }
 }
 
@@ -144,7 +149,7 @@ DEF_OP(AtomicSub) {
     case 8:
       sub(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
   }
 }
 
@@ -155,18 +160,18 @@ DEF_OP(AtomicAnd) {
   lock();
   switch (Op->Size) {
     case 1:
-      and(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      and_(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
       break;
     case 2:
-      and(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      and_(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
       break;
     case 4:
-      and(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      and_(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
       break;
     case 8:
-      and(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      and_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
   }
 }
 
@@ -177,18 +182,18 @@ DEF_OP(AtomicOr) {
   lock();
   switch (Op->Size) {
     case 1:
-      or(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      or_(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
       break;
     case 2:
-      or(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      or_(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
       break;
     case 4:
-      or(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      or_(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
       break;
     case 8:
-      or(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      or_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
   }
 }
 
@@ -199,18 +204,18 @@ DEF_OP(AtomicXor) {
   lock();
   switch (Op->Size) {
     case 1:
-      xor(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      xor_(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
       break;
     case 2:
-      xor(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      xor_(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
       break;
     case 4:
-      xor(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      xor_(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
       break;
     case 8:
-      xor(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      xor_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
   }
 }
 
@@ -222,17 +227,17 @@ DEF_OP(AtomicSwap) {
 
   switch (Op->Size) {
     case 1:
-      mov(GetDst<RA_8>(Node), GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      movzx(GetDst<RA_64>(Node), GetSrc<RA_8>(Op->Header.Args[1].ID()));
       lock();
       xchg(byte [MemReg], GetDst<RA_8>(Node));
       break;
     case 2:
-      mov(GetDst<RA_16>(Node), GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      movzx(GetDst<RA_64>(Node), GetSrc<RA_16>(Op->Header.Args[1].ID()));
       lock();
       xchg(word [MemReg], GetDst<RA_16>(Node));
       break;
     case 4:
-      mov(GetDst<RA_32>(Node), GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      mov(GetDst<RA_64>(Node), GetSrc<RA_32>(Op->Header.Args[1].ID()));
       lock();
       xchg(dword [MemReg], GetDst<RA_32>(Node));
       break;
@@ -241,7 +246,7 @@ DEF_OP(AtomicSwap) {
       lock();
       xchg(qword [MemReg], GetDst<RA_64>(Node));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
   }
 }
 
@@ -251,13 +256,13 @@ DEF_OP(AtomicFetchAdd) {
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
   switch (Op->Size) {
     case 1:
-      mov(cl, GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      movzx(rcx, GetSrc<RA_8>(Op->Header.Args[1].ID()));
       lock();
       xadd(byte [MemReg], cl);
       movzx(GetDst<RA_32>(Node), cl);
       break;
     case 2:
-      mov(cx, GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      movzx(rcx, GetSrc<RA_16>(Op->Header.Args[1].ID()));
       lock();
       xadd(word [MemReg], cx);
       movzx(GetDst<RA_32>(Node), cx);
@@ -266,7 +271,7 @@ DEF_OP(AtomicFetchAdd) {
       mov(ecx, GetSrc<RA_32>(Op->Header.Args[1].ID()));
       lock();
       xadd(dword [MemReg], ecx);
-      mov(GetDst<RA_32>(Node), ecx);
+      mov(GetDst<RA_64>(Node), ecx);
       break;
     case 8:
       mov(rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
@@ -274,7 +279,7 @@ DEF_OP(AtomicFetchAdd) {
       xadd(qword [MemReg], rcx);
       mov(GetDst<RA_64>(Node), rcx);
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicFetchAdd size: %d", Op->Size);
   }
 }
 
@@ -311,7 +316,7 @@ DEF_OP(AtomicFetchSub) {
       xadd(qword [MemReg], rcx);
       mov(GetDst<RA_64>(Node), rcx);
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicFetchAdd size: %d", Op->Size);
   }
 }
 
@@ -329,7 +334,7 @@ DEF_OP(AtomicFetchAnd) {
       L(Loop);
       mov(TMP2.cvt8(), TMP1.cvt8());
       mov(TMP3.cvt8(), TMP1.cvt8());
-      and(TMP2.cvt8(), GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      and_(TMP2.cvt8(), GetSrc<RA_8>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
@@ -345,7 +350,7 @@ DEF_OP(AtomicFetchAnd) {
       L(Loop);
       mov(TMP2.cvt16(), TMP1.cvt16());
       mov(TMP3.cvt16(), TMP1.cvt16());
-      and(TMP2.cvt16(), GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      and_(TMP2.cvt16(), GetSrc<RA_16>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(word [MemReg], TMP2.cvt16());
@@ -362,7 +367,7 @@ DEF_OP(AtomicFetchAnd) {
       L(Loop);
       mov(TMP2.cvt32(), TMP1.cvt32());
       mov(TMP3.cvt32(), TMP1.cvt32());
-      and(TMP2.cvt32(), GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      and_(TMP2.cvt32(), GetSrc<RA_32>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
@@ -379,7 +384,7 @@ DEF_OP(AtomicFetchAnd) {
       L(Loop);
       mov(TMP2.cvt64(), TMP1.cvt64());
       mov(TMP3.cvt64(), TMP1.cvt64());
-      and(TMP2.cvt64(), GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      and_(TMP2.cvt64(), GetSrc<RA_64>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
@@ -389,7 +394,7 @@ DEF_OP(AtomicFetchAnd) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicFetchAdd size: %d", Op->Size);
   }
 }
 
@@ -406,7 +411,7 @@ DEF_OP(AtomicFetchOr) {
       L(Loop);
       mov(TMP2.cvt8(), TMP1.cvt8());
       mov(TMP3.cvt8(), TMP1.cvt8());
-      or(TMP2.cvt8(), GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      or_(TMP2.cvt8(), GetSrc<RA_8>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
@@ -422,7 +427,7 @@ DEF_OP(AtomicFetchOr) {
       L(Loop);
       mov(TMP2.cvt16(), TMP1.cvt16());
       mov(TMP3.cvt16(), TMP1.cvt16());
-      or(TMP2.cvt16(), GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      or_(TMP2.cvt16(), GetSrc<RA_16>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(word [MemReg], TMP2.cvt16());
@@ -439,7 +444,7 @@ DEF_OP(AtomicFetchOr) {
       L(Loop);
       mov(TMP2.cvt32(), TMP1.cvt32());
       mov(TMP3.cvt32(), TMP1.cvt32());
-      or(TMP2.cvt32(), GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      or_(TMP2.cvt32(), GetSrc<RA_32>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
@@ -456,7 +461,7 @@ DEF_OP(AtomicFetchOr) {
       L(Loop);
       mov(TMP2.cvt64(), TMP1.cvt64());
       mov(TMP3.cvt64(), TMP1.cvt64());
-      or(TMP2.cvt64(), GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      or_(TMP2.cvt64(), GetSrc<RA_64>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
@@ -466,7 +471,7 @@ DEF_OP(AtomicFetchOr) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicFetchAdd size: %d", Op->Size);
   }
 }
 
@@ -483,7 +488,7 @@ DEF_OP(AtomicFetchXor) {
       L(Loop);
       mov(TMP2.cvt8(), TMP1.cvt8());
       mov(TMP3.cvt8(), TMP1.cvt8());
-      xor(TMP2.cvt8(), GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      xor_(TMP2.cvt8(), GetSrc<RA_8>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
@@ -499,7 +504,7 @@ DEF_OP(AtomicFetchXor) {
       L(Loop);
       mov(TMP2.cvt16(), TMP1.cvt16());
       mov(TMP3.cvt16(), TMP1.cvt16());
-      xor(TMP2.cvt16(), GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      xor_(TMP2.cvt16(), GetSrc<RA_16>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(word [MemReg], TMP2.cvt16());
@@ -516,7 +521,7 @@ DEF_OP(AtomicFetchXor) {
       L(Loop);
       mov(TMP2.cvt32(), TMP1.cvt32());
       mov(TMP3.cvt32(), TMP1.cvt32());
-      xor(TMP2.cvt32(), GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      xor_(TMP2.cvt32(), GetSrc<RA_32>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
@@ -533,7 +538,7 @@ DEF_OP(AtomicFetchXor) {
       L(Loop);
       mov(TMP2.cvt64(), TMP1.cvt64());
       mov(TMP3.cvt64(), TMP1.cvt64());
-      xor(TMP2.cvt64(), GetSrc<RA_64>(Op->Header.Args[1].ID()));
+      xor_(TMP2.cvt64(), GetSrc<RA_64>(Op->Header.Args[1].ID()));
 
       // Updates RAX with the value from memory
       lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
@@ -543,13 +548,13 @@ DEF_OP(AtomicFetchXor) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled AtomicFetchAdd size: %d", Op->Size);
   }
 }
 
 #undef DEF_OP
-void JITCore::RegisterAtomicHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterAtomicHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(CASPAIR,        CASPair);
   REGISTER_OP(CAS,            CAS);
   REGISTER_OP(ATOMICADD,      AtomicAdd);

External/FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp

@@ -1,11 +1,18 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/HLE/SyscallHandler.h>
+#include <Interface/HLE/Thunks/Thunks.h>
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(GuestCallDirect) {
   LogMan::Msg::D("Unimplemented");
 }
@@ -39,7 +46,7 @@ DEF_OP(CallbackReturn) {
   sub(dword [rax], 1);
 
   // We need to adjust an additional 8 bytes to get back to the original "misaligned" RSP state
-  add(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])], 8);
+  add(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])], 8);
 
   // Now jump back to the thunk
   // XXX: XMM?
@@ -66,7 +73,7 @@ DEF_OP(ExitFunction) {
 
   uint64_t NewRIP;
 
-  if (IsInlineConstant(Op->NewRIP, &NewRIP)) {
+  if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
     Label l_BranchHost;
     Label l_BranchGuest;
 
@@ -74,12 +81,12 @@ DEF_OP(ExitFunction) {
     jmp(qword[rax]);
 
     L(l_BranchHost);
-    dq(ExitFunctionLinkerAddress);
+    dq(ThreadSharedData.Dispatcher->ExitFunctionLinkerAddress);
     L(l_BranchGuest);
     dq(NewRIP);
   } else {
     Xbyak::Reg RipReg = GetSrc<RA_64>(Op->NewRIP.ID());
-    
+
     // L1 Cache
     mov(rcx, ThreadState->LookupCache->GetL1Pointer());
     mov(rax, RipReg);
@@ -88,14 +95,14 @@ DEF_OP(ExitFunction) {
     shl(rax, 4);
 
     Xbyak::RegExp LookupBase = rcx + rax;
-  
+
     cmp(qword[LookupBase + 8], RipReg);
     jne(FullLookup);
     jmp(qword[LookupBase + 0]);
 
     L(FullLookup);
-    mov(rax, AbsoluteLoopTopAddress);
-    mov(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.rip)], RipReg);
+    mov(rax, ThreadSharedData.Dispatcher->AbsoluteLoopTopAddress);
+    mov(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.rip)], RipReg);
     jmp(rax);
   }
 
@@ -227,7 +234,9 @@ DEF_OP(Thunk) {
 
   mov(rdi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
 
-  mov(rax, reinterpret_cast<uintptr_t>(Op->ThunkFnPtr));
+  auto thunkFn = ThreadState->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
+
+  mov(rax, reinterpret_cast<uintptr_t>(thunkFn));
   call(rax);
 
   if (NumPush & 1)
@@ -244,7 +253,7 @@ DEF_OP(ValidateCode) {
   int idx = 0;
 
   xor_(GetDst<RA_64>(Node), GetDst<RA_64>(Node));
-  mov(rax, Op->CodePtr);
+  mov(rax, Entry + Op->Offset);
   mov(rbx, 1);
   while (len >= 4) {
     cmp(dword[rax + idx], *(uint32_t*)(OldCode + idx));
@@ -268,8 +277,6 @@ DEF_OP(ValidateCode) {
 }
 
 DEF_OP(RemoveCodeEntry) {
-  auto Op = IROp->C<IR::IROp_RemoveCodeEntry>();
-
   auto NumPush = RA64.size();
 
   for (auto &Reg : RA64)
@@ -279,11 +286,11 @@ DEF_OP(RemoveCodeEntry) {
     sub(rsp, 8); // Align
 
   mov(rdi, STATE);
-  mov(rax, Op->RIP); // imm64 move
+  mov(rax, Entry); // imm64 move
   mov(rsi, rax);
 
 
-  mov(rax, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntry));
+  mov(rax, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit));
   call(rax);
 
   if (NumPush & 1)
@@ -296,7 +303,7 @@ DEF_OP(RemoveCodeEntry) {
 DEF_OP(CPUID) {
   auto Op = IROp->C<IR::IROp_CPUID>();
 
-  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t Function);
+  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t Function, uint32_t Leaf);
   union {
     ClassPtrType ClassPtr;
     uint64_t Raw;
@@ -313,6 +320,7 @@ DEF_OP(CPUID) {
   // Result: RAX, RDX. 4xi32
 
   mov (rsi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  mov (rdx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
   mov (rdi, reinterpret_cast<uint64_t>(&CTX->CPUID));
 
   auto NumPush = RA64.size();
@@ -338,8 +346,8 @@ DEF_OP(CPUID) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterBranchHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterBranchHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(GUESTCALLDIRECT,   GuestCallDirect);
   REGISTER_OP(GUESTCALLINDIRECT, GuestCallIndirect);
   REGISTER_OP(GUESTRETURN,       GuestReturn);

External/FEXCore/Source/Interface/Core/JIT/x86_64/ConversionOps.cpp

@@ -1,9 +1,15 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(VInsGPR) {
   auto Op = IROp->C<IR::IROp_VInsGPR>();
   movapd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
@@ -25,7 +31,7 @@ DEF_OP(VInsGPR) {
       pinsrq(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[1].ID()), Op->Index);
       break;
     }
-    default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
   }
 }
 
@@ -46,14 +52,10 @@ DEF_OP(VCastFromGPR) {
     case 8:
       vmovq(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()).cvt64());
       break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Float_FromGPR_U) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Float_FromGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
   uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
@@ -89,14 +91,10 @@ DEF_OP(Float_FToF) {
       cvtsd2ss(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
     }
-    default: LogMan::Msg::A("Unknown FCVT sizes: 0x%x", Conv);
+    default: LOGMAN_MSG_A("Unknown FCVT sizes: 0x%x", Conv);
   }
 }
 
-DEF_OP(Vector_UToF) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Vector_SToF) {
   auto Op = IROp->C<IR::IROp_Vector_SToF>();
   switch (Op->Header.ElementSize) {
@@ -115,14 +113,10 @@ DEF_OP(Vector_SToF) {
       cvtsi2sd(xmm15, rax);
       movlhps(GetDst(Node), xmm15);
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Vector_FToZU) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Vector_FToZS) {
   auto Op = IROp->C<IR::IROp_Vector_FToZS>();
   switch (Op->Header.ElementSize) {
@@ -132,14 +126,10 @@ DEF_OP(Vector_FToZS) {
     case 8:
       cvttpd2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Vector_FToU) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Vector_FToS) {
   auto Op = IROp->C<IR::IROp_Vector_FToS>();
   switch (Op->Header.ElementSize) {
@@ -149,7 +139,7 @@ DEF_OP(Vector_FToS) {
     case 8:
       cvtpd2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
   }
 }
 
@@ -166,25 +156,54 @@ DEF_OP(Vector_FToF) {
       cvtpd2ps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
     }
-    default: LogMan::Msg::A("Unknown Conversion Type : 0%04x", Conv); break;
+    default: LOGMAN_MSG_A("Unknown Conversion Type : 0%04x", Conv); break;
+  }
+}
+
+DEF_OP(Vector_FToI) {
+  auto Op = IROp->C<IR::IROp_Vector_FToI>();
+  uint8_t RoundMode{};
+
+  switch (Op->Round) {
+    case FEXCore::IR::Round_Nearest.Val:
+      RoundMode = 0b0000'0'0'00;
+    break;
+    case FEXCore::IR::Round_Negative_Infinity.Val:
+      RoundMode = 0b0000'0'0'01;
+    break;
+    case FEXCore::IR::Round_Positive_Infinity.Val:
+      RoundMode = 0b0000'0'0'10;
+    break;
+    case FEXCore::IR::Round_Towards_Zero.Val:
+      RoundMode = 0b0000'0'0'11;
+    break;
+    case FEXCore::IR::Round_Host.Val:
+      RoundMode = 0b0000'0'1'00;
+    break;
+  }
+
+  switch (Op->Header.ElementSize) {
+    case 4:
+      roundps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), RoundMode);
+    break;
+    case 8:
+      roundpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), RoundMode);
+    break;
   }
 }
 
 #undef DEF_OP
-void JITCore::RegisterConversionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterConversionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(VINSGPR,         VInsGPR);
   REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_U, Float_FromGPR_U);
   REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
   REGISTER_OP(FLOAT_FTOF,      Float_FToF);
-  REGISTER_OP(VECTOR_UTOF,     Vector_UToF);
   REGISTER_OP(VECTOR_STOF,     Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZU,    Vector_FToZU);
   REGISTER_OP(VECTOR_FTOZS,    Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOU,     Vector_FToU);
   REGISTER_OP(VECTOR_FTOS,     Vector_FToS);
   REGISTER_OP(VECTOR_FTOF,     Vector_FToF);
+  REGISTER_OP(VECTOR_FTOI,     Vector_FToI);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/EncryptionOps.cpp

@@ -1,8 +1,14 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(AESImc) {
   auto Op = IROp->C<IR::IROp_VAESImc>();
@@ -35,8 +41,8 @@ DEF_OP(AESKeyGenAssist) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterEncryptionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterEncryptionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(VAESIMC,     AESImc);
   REGISTER_OP(VAESENC,     AESEnc);
   REGISTER_OP(VAESENCLAST, AESEncLast);

External/FEXCore/Source/Interface/Core/JIT/x86_64/FlagOps.cpp

@@ -1,21 +1,27 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(GetHostFlag) {
   auto Op = IROp->C<IR::IROp_GetHostFlag>();
 
   mov(rax, GetSrc<RA_64>(Op->Header.Args[0].ID()));
   shr(rax, Op->Flag);
-  and(rax, 1);
+  and_(rax, 1);
   mov(GetDst<RA_64>(Node), rax);
 }
 
 #undef DEF_OP
-void JITCore::RegisterFlagHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterFlagHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(GETHOSTFLAG, GetHostFlag);
 #undef REGISTER_OP
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.h

@@ -1 +0,0 @@
-

External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h

@@ -1,11 +1,18 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #pragma once
 
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/BlockSamplingData.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
 
-#include "Interface/Core/JIT/x86_64/JIT.h"
 #include "Common/MathUtils.h"
 
+#define XBYAK64
 #include <xbyak/xbyak.h>
 #include <xbyak/xbyak_util.h>
 
@@ -51,15 +58,15 @@ namespace FEXCore::CPU {
 using namespace Xbyak::util;
 const std::array<Xbyak::Reg, 9> RA64 = { rsi, r8, r9, r10, r11, rbp, r12, r13, r15 };
 const std::array<std::pair<Xbyak::Reg, Xbyak::Reg>, 4> RA64Pair = {{ {rsi, r8}, {r9, r10}, {r11, rbp}, {r12, r13} }};
-const std::array<Xbyak::Reg, 11> RAXMM = { xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10 };
-const std::array<Xbyak::Xmm, 11> RAXMM_x = { xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10 };
+const std::array<Xbyak::Reg, 11> RAXMM = { xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10, xmm11};
+const std::array<Xbyak::Xmm, 11> RAXMM_x = {  xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10, xmm11};
 
-class JITCore final : public CPUBackend, public Xbyak::CodeGenerator {
+class X86JITCore final : public CPUBackend, public Xbyak::CodeGenerator {
 public:
-  explicit JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, CodeBuffer Buffer, bool CompileThread);
-  ~JITCore() override;
+  explicit X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, CodeBuffer Buffer, bool CompileThread);
+  ~X86JITCore() override;
   std::string GetName() override { return "JIT"; }
-  void *CompileCode(FEXCore::IR::IRListView<true> const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
+  void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
 
   void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
 
@@ -69,17 +76,15 @@ public:
 
   static constexpr size_t INITIAL_CODE_SIZE = 1024 * 1024 * 16;
   static constexpr size_t MAX_CODE_SIZE = 1024 * 1024 * 256;
-
-  bool HandleSIGILL(int Signal, void *info, void *ucontext);
-  bool HandleSignalPause(int Signal, void *info, void *ucontext);
-  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
   void CopyNecessaryDataForCompileThread(CPUBackend *Original) override;
 
 private:
   Label* PendingTargetLabel{};
   FEXCore::Context::Context *CTX;
   FEXCore::Core::InternalThreadState *ThreadState;
-  FEXCore::IR::IRListView<true> const *IR;
+  FEXCore::IR::IRListView const *IR;
+  std::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
+  uint64_t Entry;
 
   std::unordered_map<IR::OrderedNodeWrapper::NodeOffsetType, Label> JumpTargets;
   Xbyak::util::Cpu Features{};
@@ -107,27 +112,27 @@ private:
   constexpr static uint8_t RA_64 = 3;
   constexpr static uint8_t RA_XMM = 4;
 
-  IR::PhysicalRegister GetPhys(uint32_t Node);
+  IR::PhysicalRegister GetPhys(uint32_t Node) const;
 
-  bool IsFPR(uint32_t Node);
-  bool IsGPR(uint32_t Node);
+  bool IsFPR(uint32_t Node) const;
+  bool IsGPR(uint32_t Node) const;
 
   template<uint8_t RAType>
-  Xbyak::Reg GetSrc(uint32_t Node);
+  Xbyak::Reg GetSrc(uint32_t Node) const;
   template<uint8_t RAType>
-  std::pair<Xbyak::Reg, Xbyak::Reg> GetSrcPair(uint32_t Node);
+  std::pair<Xbyak::Reg, Xbyak::Reg> GetSrcPair(uint32_t Node) const;
 
   template<uint8_t RAType>
-  Xbyak::Reg GetDst(uint32_t Node);
+  Xbyak::Reg GetDst(uint32_t Node) const;
 
-  Xbyak::Xmm GetSrc(uint32_t Node);
-  Xbyak::Xmm GetDst(uint32_t Node);
+  Xbyak::Xmm GetSrc(uint32_t Node) const;
+  Xbyak::Xmm GetDst(uint32_t Node) const;
 
-  Xbyak::RegExp GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale);
+  Xbyak::RegExp GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) const;
 
-  bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr);
+  bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr) const;
+  bool IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value) const;
 
-  void CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread);
   IR::RegisterAllocationPass *RAPass;
   FEXCore::IR::RegisterAllocationData *RAData;
 
@@ -135,13 +140,11 @@ private:
   bool GetSamplingData {true};
 #endif
 
-  static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096 * 1;
-
   void EmplaceNewCodeBuffer(CodeBuffer Buffer) {
     CurrentCodeBuffer = &CodeBuffers.emplace_back(Buffer);
   }
 
-  static uint64_t ExitFunctionLink(JITCore* code, FEXCore::Core::InternalThreadState *Thread, uint64_t *record);
+  static uint64_t ExitFunctionLink(X86JITCore* code, FEXCore::Core::CpuStateFrame *Frame, uint64_t *record);
 
   // This is the initial code buffer that we will fall back to
   // In a program without signals and code clearing, we will typically
@@ -152,41 +155,26 @@ private:
   // For code safety we can't delete code buffers until outside of all signals
   std::vector<CodeBuffer> CodeBuffers{};
 
-  // This is the codebuffer that our dispatcher lives in
-  CodeBuffer DispatcherCodeBuffer{};
   // This is the current code buffer that we are tracking
   CodeBuffer *CurrentCodeBuffer{};
 
-  uint64_t AbsoluteLoopTopAddress{};
-  uint64_t ExitFunctionLinkerAddress{};
-  uint64_t ThreadStopHandlerAddress{};
-  uint64_t ThreadPauseHandlerAddress{};
-
-  uint64_t PauseReturnInstruction{};
-
-  uint32_t SignalHandlerRefCounter{};
-
   struct CompilerSharedData {
-    void *InterpreterFallbackHelperAddress;
-
     uint64_t SignalHandlerReturnAddress{};
 
     uint32_t *SignalHandlerRefCounterPtr{};
+    FEXCore::CPU::Dispatcher *Dispatcher{};
   };
 
   CompilerSharedData ThreadSharedData;
 
-  void StoreThreadState(int Signal, void *ucontext);
-  void RestoreThreadState(void *ucontext);
-  std::stack<uint64_t> SignalFrames;
   uint32_t SpillSlots{};
-  using SetCC = void (JITCore::*)(const Operand& op);
-  using CMovCC = void (JITCore::*)(const Reg& reg, const Operand& op);
-  using JCC = void (JITCore::*)(const Label& label, LabelType type);
+  using SetCC = void (X86JITCore::*)(const Operand& op);
+  using CMovCC = void (X86JITCore::*)(const Reg& reg, const Operand& op);
+  using JCC = void (X86JITCore::*)(const Label& label, LabelType type);
 
   std::tuple<SetCC, CMovCC, JCC> GetCC(IR::CondClassType cond);
 
-  using OpHandler = void (JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
+  using OpHandler = void (X86JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
   std::array<OpHandler, FEXCore::IR::IROps::OP_LAST + 1> OpHandlers {};
   void RegisterALUHandlers();
   void RegisterAtomicHandlers();
@@ -198,6 +186,9 @@ private:
   void RegisterMoveHandlers();
   void RegisterVectorHandlers();
   void RegisterEncryptionHandlers();
+
+  void PushRegs();
+  void PopRegs();
 #define DEF_OP(x) void Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
   ///< Unhandled handler
@@ -209,7 +200,9 @@ private:
   ///< ALU Ops
   DEF_OP(TruncElementPair);
   DEF_OP(Constant);
+  DEF_OP(EntrypointOffset);
   DEF_OP(InlineConstant);
+  DEF_OP(InlineEntrypointOffset);
   DEF_OP(CycleCounter);
   DEF_OP(Add);
   DEF_OP(Sub);
@@ -248,9 +241,7 @@ private:
   DEF_OP(Sbfe);
   DEF_OP(Select);
   DEF_OP(VExtractToGPR);
-  DEF_OP(Float_ToGPR_ZU);
   DEF_OP(Float_ToGPR_ZS);
-  DEF_OP(Float_ToGPR_U);
   DEF_OP(Float_ToGPR_S);
   DEF_OP(FCmp);
   DEF_OP(F80Cmp);
@@ -288,16 +279,14 @@ private:
   ///< Conversion ops
   DEF_OP(VInsGPR);
   DEF_OP(VCastFromGPR);
-  DEF_OP(Float_FromGPR_U);
   DEF_OP(Float_FromGPR_S);
   DEF_OP(Float_FToF);
   DEF_OP(Vector_UToF);
   DEF_OP(Vector_SToF);
-  DEF_OP(Vector_FToZU);
   DEF_OP(Vector_FToZS);
-  DEF_OP(Vector_FToU);
   DEF_OP(Vector_FToS);
   DEF_OP(Vector_FToF);
+  DEF_OP(Vector_FToI);
 
   ///< Flag ops
   DEF_OP(GetHostFlag);
@@ -315,6 +304,7 @@ private:
   DEF_OP(StoreMem);
   DEF_OP(VLoadMemElement);
   DEF_OP(VStoreMemElement);
+  DEF_OP(CacheLineClear);
 
   ///< Misc ops
   DEF_OP(EndBlock);
@@ -339,6 +329,7 @@ private:
   DEF_OP(SplatVector);
   DEF_OP(VMov);
   DEF_OP(VAnd);
+  DEF_OP(VBic);
   DEF_OP(VOr);
   DEF_OP(VXor);
   DEF_OP(VAdd);
@@ -349,8 +340,10 @@ private:
   DEF_OP(VSQSub);
   DEF_OP(VAddP);
   DEF_OP(VAddV);
+  DEF_OP(VUMinV);
   DEF_OP(VURAvg);
   DEF_OP(VAbs);
+  DEF_OP(VPopcount);
   DEF_OP(VFAdd);
   DEF_OP(VFAddP);
   DEF_OP(VFSub);
@@ -370,6 +363,8 @@ private:
   DEF_OP(VSMax);
   DEF_OP(VZip);
   DEF_OP(VZip2);
+  DEF_OP(VUnZip);
+  DEF_OP(VUnZip2);
   DEF_OP(VBSL);
   DEF_OP(VCMPEQ);
   DEF_OP(VCMPEQZ);
@@ -392,6 +387,7 @@ private:
   DEF_OP(VInsElement);
   DEF_OP(VInsScalarElement);
   DEF_OP(VExtractElement);
+  DEF_OP(VDupElement);
   DEF_OP(VExtr);
   DEF_OP(VSLI);
   DEF_OP(VSRI);
@@ -414,6 +410,7 @@ private:
   DEF_OP(VSMull);
   DEF_OP(VUMull2);
   DEF_OP(VSMull2);
+  DEF_OP(VUABDL);
   DEF_OP(VTBL1);
 
   ///< Encryption ops

External/FEXCore/Source/Interface/Core/JIT/x86_64/MemoryOps.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
@@ -5,7 +11,7 @@
 
 namespace FEXCore::CPU {
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(LoadContext) {
   auto Op = IROp->C<IR::IROp_LoadContext>();
@@ -30,10 +36,10 @@ DEF_OP(LoadContext) {
     }
     break;
     case 16: {
-      LogMan::Msg::A("Invalid GPR load of size 16");
+      LOGMAN_MSG_A("Invalid GPR load of size 16");
     }
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled LoadContext size: %d", OpSize);
     }
   }
   else {
@@ -63,7 +69,7 @@ DEF_OP(LoadContext) {
         movups(GetDst(Node), xword [STATE + Op->Offset]);
     }
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled LoadContext size: %d", OpSize);
     }
   }
 }
@@ -94,7 +100,7 @@ DEF_OP(StoreContext) {
     case 16:
       LogMan::Msg::D("Invalid store size of 16");
     break;
-    default:  LogMan::Msg::A("Unhandled StoreContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled StoreContext size: %d", OpSize);
     }
   }
   else {
@@ -123,7 +129,7 @@ DEF_OP(StoreContext) {
         movups(xword [STATE + Op->Offset], GetSrc(Op->Header.Args[0].ID()));
     }
     break;
-    default:  LogMan::Msg::A("Unhandled StoreContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A("Unhandled StoreContext size: %d", OpSize);
     }
   }
 }
@@ -154,15 +160,15 @@ DEF_OP(LoadContextIndexed) {
         mov(GetDst<RA_64>(Node),  qword [rax + index * Op->Stride]);
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
       }
       break;
     }
     case 16:
-      LogMan::Msg::A("Invalid Class load of size 16");
+      LOGMAN_MSG_A("Invalid Class load of size 16");
       break;
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
     }
 
   }
@@ -189,7 +195,7 @@ DEF_OP(LoadContextIndexed) {
         vmovq(GetDst(Node),  qword [rax + index * Op->Stride]);
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
       }
       break;
     }
@@ -217,12 +223,12 @@ DEF_OP(LoadContextIndexed) {
           movups(GetDst(Node), xword [STATE + rax]);
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
       }
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
     }
   }
 }
@@ -242,13 +248,13 @@ DEF_OP(StoreContextIndexed) {
     case 4:
     case 8: {
       if (!(size == 1 || size == 2 || size == 4 || size == 8)) {
-        LogMan::Msg::A("Unhandled StoreContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A("Unhandled StoreContextIndexed size: %d", Op->Size);
       }
       mov(AddressFrame(Op->Size * 8) [rax + index * Op->Stride], value);
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled StoreContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A("Unhandled StoreContextIndexed stride: %d", Op->Stride);
     }
   }
   else {
@@ -273,7 +279,7 @@ DEF_OP(StoreContextIndexed) {
         vmovq(AddressFrame(Op->Size * 8) [rax + index * Op->Stride], value);
         break;
       default:
-        LogMan::Msg::A("Unhandled StoreContextIndexed size: %d", size);
+        LOGMAN_MSG_A("Unhandled StoreContextIndexed size: %d", size);
       }
       break;
     }
@@ -301,12 +307,12 @@ DEF_OP(StoreContextIndexed) {
           movups(xword [STATE + rax], value);
         break;
       default:
-        LogMan::Msg::A("Unhandled StoreContextIndexed size: %d", size);
+        LOGMAN_MSG_A("Unhandled StoreContextIndexed size: %d", size);
       }
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled StoreContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A("Unhandled StoreContextIndexed stride: %d", Op->Stride);
     }
   }
 }
@@ -334,7 +340,7 @@ DEF_OP(SpillRegister) {
         mov(qword [rsp + SlotOffset], GetSrc<RA_64>(Op->Header.Args[0].ID()));
         break;
       }
-      default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -350,10 +356,10 @@ DEF_OP(SpillRegister) {
         movaps(xword [rsp + SlotOffset], GetSrc(Op->Header.Args[0].ID()));
         break;
       }
-      default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
     }
   } else {
-    LogMan::Msg::A("Unhandled SpillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A("Unhandled SpillRegister class: %d", Op->Class.Val);
   }
 
 
@@ -382,7 +388,7 @@ DEF_OP(FillRegister) {
         mov(GetDst<RA_64>(Node), qword [rsp + SlotOffset]);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled FillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A("Unhandled FillRegister size: %d", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -398,10 +404,10 @@ DEF_OP(FillRegister) {
         movaps(GetDst(Node), xword [rsp + SlotOffset]);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled FillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A("Unhandled FillRegister size: %d", OpSize);
     }
   } else {
-    LogMan::Msg::A("Unhandled FillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A("Unhandled FillRegister class: %d", Op->Class.Val);
   }
 }
 
@@ -419,16 +425,16 @@ DEF_OP(StoreFlag) {
   mov(byte [STATE + (offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag)], al);
 }
 
-Xbyak::RegExp JITCore::GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) {
+Xbyak::RegExp X86JITCore::GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) const {
   if (Offset.IsInvalid()) {
     return Base;
   } else {
     if (OffsetScale != 1 && OffsetScale != 2 && OffsetScale != 4 && OffsetScale != 8) {
-      LogMan::Msg::A("Unhandled GenerateModRM OffsetScale: %d", OffsetScale);
+      LOGMAN_MSG_A("Unhandled GenerateModRM OffsetScale: %d", OffsetScale);
     }
 
     if (OffsetType != IR::MEM_OFFSET_SXTX) {
-      LogMan::Msg::A("Unhandled GenerateModRM OffsetType: %d", OffsetType.Val);
+      LOGMAN_MSG_A("Unhandled GenerateModRM OffsetType: %d", OffsetType.Val);
     }
 
     uint64_t Const;
@@ -469,7 +475,7 @@ DEF_OP(LoadMem) {
         mov(Dst, qword [MemPtr]);
       }
       break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
     }
   }
   else
@@ -505,7 +511,7 @@ DEF_OP(LoadMem) {
          }
        }
        break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
     }
   }
 }
@@ -531,7 +537,7 @@ DEF_OP(StoreMem) {
     case 8:
       mov(qword [MemPtr], GetSrc<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
     }
   }
   else {
@@ -554,22 +560,30 @@ DEF_OP(StoreMem) {
       else
         movups(xword [MemPtr], GetSrc(Op->Header.Args[1].ID()));
     break;
-    default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+    default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
     }
   }
 }
 
 DEF_OP(VLoadMemElement) {
-  LogMan::Msg::A("Unimplemented");
+  LOGMAN_MSG_A("Unimplemented");
 }
 
 DEF_OP(VStoreMemElement) {
-  LogMan::Msg::A("Unimplemented");
+  LOGMAN_MSG_A("Unimplemented");
+}
+
+DEF_OP(CacheLineClear) {
+  auto Op = IROp->C<IR::IROp_CacheLineClear>();
+
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
+
+  clflush(ptr [MemReg]);
 }
 
 #undef DEF_OP
-void JITCore::RegisterMemoryHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterMemoryHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(LOADCONTEXT,         LoadContext);
   REGISTER_OP(STORECONTEXT,        StoreContext);
   REGISTER_OP(LOADREGISTER,        Unhandled); // SRA specific, not supported on this backend
@@ -586,6 +600,7 @@ void JITCore::RegisterMemoryHandlers() {
   REGISTER_OP(STOREMEMTSO,         StoreMem);
   REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
   REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
+  REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/MiscOps.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
@@ -6,7 +12,11 @@ static void PrintValue(uint64_t Value) {
   LogMan::Msg::D("Value: 0x%lx", Value);
 }
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
+  LogMan::Msg::D("Value: 0x%016lx'%016lx", ValueUpper, Value);
+}
+
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(Fence) {
   auto Op = IROp->C<IR::IROp_Fence>();
@@ -20,7 +30,7 @@ DEF_OP(Fence) {
     case IR::Fence_Store.Val:
       sfence();
       break;
-    default: LogMan::Msg::A("Unknown Fence: %d", Op->Fence); break;
+    default: LOGMAN_MSG_A("Unknown Fence: %d", Op->Fence); break;
   }
 }
 
@@ -31,13 +41,22 @@ DEF_OP(Break) {
     case 5: // Guest ud2
       ud2();
     break;
+    case 1: // Int <imm8>
+      ud2();
+    break;
+    case 2: // overflow
+      ud2();
+      break;
+    case 3: // int 1
+      ud2();
+      break;
     case 4: { // HLT
       // Time to quit
       // Set our stack to the starting stack location
-      mov(rsp, qword [STATE + offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)]);
+      mov(rsp, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)]);
 
       // Now we need to jump to the thread stop handler
-      mov(TMP1, ThreadStopHandlerAddress);
+      mov(TMP1, ThreadSharedData.Dispatcher->ThreadStopHandlerAddress);
       jmp(TMP1);
       break;
     }
@@ -48,23 +67,23 @@ DEF_OP(Break) {
         if (SpillSlots) {
           add(rsp, SpillSlots * 16);
         }
-        
+
         // This jump target needs to be a constant offset here
-        mov(TMP1, ThreadPauseHandlerAddress);
+        mov(TMP1, ThreadSharedData.Dispatcher->ThreadPauseHandlerAddress);
         jmp(TMP1);
       }
       else {
         // If we don't have a gdb server attached then....crash?
         // Treat this case like HLT
-        mov(rsp, qword [STATE + offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)]);
+        mov(rsp, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)]);
 
         // Now we need to jump to the thread stop handler
-        mov(TMP1, ThreadStopHandlerAddress);
+        mov(TMP1, ThreadSharedData.Dispatcher->ThreadStopHandlerAddress);
         jmp(TMP1);
       }
     break;
     }
-    default: LogMan::Msg::A("Unknown Break reason: %d", Op->Reason);
+    default: LOGMAN_MSG_A("Unknown Break reason: %d", Op->Reason);
   }
 }
 
@@ -89,10 +108,10 @@ DEF_OP(SetRoundingMode) {
   mov(TMP1.cvt32(), dword [rsp]);
 
   // Insert the new rounding mode
-  and(TMP1.cvt32(), ~(0b111 << 13));
+  and_(TMP1.cvt32(), ~(0b111 << 13));
   mov(TMP2.cvt32(), Src);
   shl(TMP2.cvt32(), 13);
-  or(TMP1.cvt32(), TMP2.cvt32());
+  or_(TMP1.cvt32(), TMP2.cvt32());
 
   // Store it to mxcsr
   // Only loads from memory
@@ -104,29 +123,27 @@ DEF_OP(SetRoundingMode) {
 DEF_OP(Print) {
   auto Op = IROp->C<IR::IROp_Print>();
 
-  for (auto &Reg : RA64)
-    push(Reg);
+  PushRegs();
+  if (IsGPR(Op->Header.Args[0].ID())) {
+    mov (rdi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
 
-  auto NumPush = RA64.size();
-  if (NumPush & 1)
-    sub(rsp, 8); // Align
+    mov(rax, reinterpret_cast<uintptr_t>(PrintValue));
+  }
+  else {
+    pextrq(rdi, GetSrc(Op->Header.Args[0].ID()), 0);
+    pextrq(rsi, GetSrc(Op->Header.Args[0].ID()), 1);
 
-  mov (rdi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
-
-  mov(rax, reinterpret_cast<uintptr_t>(PrintValue));
+    mov(rax, reinterpret_cast<uintptr_t>(PrintVectorValue));
+  }
 
   call(rax);
 
-  if (NumPush & 1)
-    add(rsp, 8); // Align
-
-  for (uint32_t i = RA64.size(); i > 0; --i)
-    pop(RA64[i - 1]);
+  PopRegs();
 }
 
 #undef DEF_OP
-void JITCore::RegisterMiscHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterMiscHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(DUMMY,      NoOp);
   REGISTER_OP(IRHEADER,   NoOp);
   REGISTER_OP(CODEBLOCK,  NoOp);

External/FEXCore/Source/Interface/Core/JIT/x86_64/MoveOps.cpp

@@ -1,9 +1,15 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(ExtractElementPair) {
   auto Op = IROp->C<IR::IROp_ExtractElementPair>();
   switch (Op->Header.Size) {
@@ -19,7 +25,7 @@ DEF_OP(ExtractElementPair) {
       mov (GetDst<RA_64>(Node), Regs[Op->Element]);
       break;
     }
-    default: LogMan::Msg::A("Unknown Size"); break;
+    default: LOGMAN_MSG_A("Unknown Size"); break;
   }
 }
 
@@ -28,21 +34,24 @@ DEF_OP(CreateElementPair) {
   std::pair<Xbyak::Reg, Xbyak::Reg> Dst;
   Xbyak::Reg RegFirst;
   Xbyak::Reg RegSecond;
+  Xbyak::Reg RegTmp;
 
   switch (Op->Header.Size) {
     case 4: {
       Dst = GetSrcPair<RA_32>(Node);
       RegFirst = GetSrc<RA_32>(Op->Header.Args[0].ID());
       RegSecond = GetSrc<RA_32>(Op->Header.Args[1].ID());
+      RegTmp = eax;
       break;
     }
     case 8: {
       Dst = GetSrcPair<RA_64>(Node);
       RegFirst = GetSrc<RA_64>(Op->Header.Args[0].ID());
       RegSecond = GetSrc<RA_64>(Op->Header.Args[1].ID());
+      RegTmp = rax;
       break;
     }
-    default: LogMan::Msg::A("Unknown Size"); break;
+    default: LOGMAN_MSG_A("Unknown Size"); break;
   }
 
   if (Dst.first != RegSecond) {
@@ -52,7 +61,9 @@ DEF_OP(CreateElementPair) {
     mov(Dst.second, RegSecond);
     mov(Dst.first, RegFirst);
   } else {
-    LogMan::Msg::A("Unhandled CreateElementPair");
+    mov(RegTmp, RegFirst);
+    mov(Dst.second, RegSecond);
+    mov(Dst.first, RegTmp);
   }
 }
 
@@ -62,8 +73,8 @@ DEF_OP(Mov) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterMoveHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterMoveHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(EXTRACTELEMENTPAIR, ExtractElementPair);
   REGISTER_OP(CREATEELEMENTPAIR,  CreateElementPair);
   REGISTER_OP(MOV,                Mov);

External/FEXCore/Source/Interface/Core/LookupCache.cpp

@@ -1,6 +1,15 @@
+/*
+$info$
+tags: glue|block-database
+desc: Stores information about blocks, and provides C++ implementations to lookup the blocks
+$end_info$
+*/
+
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Core.h"
 #include "Interface/Core/LookupCache.h"
+#include <FEXCore/Utils/Allocator.h>
+
 #include <sys/mman.h>
 
 namespace FEXCore {
@@ -19,27 +28,27 @@ LookupCache::LookupCache(FEXCore::Context::Context *CTX)
   // Allocate a region of memory that we can use to back our block pointers
   // We need one pointer per page of virtual memory
   // At 64GB of virtual memory this will allocate 128MB of virtual memory space
-  PagePointer = reinterpret_cast<uintptr_t>(mmap(nullptr, ctx->Config.VirtualMemSize / 4096 * 8, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+  PagePointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, ctx->Config.VirtualMemSize / 4096 * 8, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
 
   // Allocate our memory backing our pages
   // We need 32KB per guest page (One pointer per byte)
   // XXX: We can drop down to 16KB if we store 4byte offsets from the code base
   // We currently limit to 128MB of real memory for caching for the total cache size.
   // Can end up being inefficient if we compile a small number of blocks per page
-  PageMemory = reinterpret_cast<uintptr_t>(mmap(nullptr, CODE_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
-  LogMan::Throw::A(PageMemory != -1ULL, "Failed to allocate page memory");
+  PageMemory = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, CODE_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+  LOGMAN_THROW_A(PageMemory != -1ULL, "Failed to allocate page memory");
 
   // L1 Cache
-  L1Pointer = reinterpret_cast<uintptr_t>(mmap(nullptr, L1_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
-  LogMan::Throw::A(L1Pointer != -1ULL, "Failed to allocate L1Pointer");
+  L1Pointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, L1_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+  LOGMAN_THROW_A(L1Pointer != -1ULL, "Failed to allocate L1Pointer");
 
   VirtualMemSize = ctx->Config.VirtualMemSize;
 }
 
 LookupCache::~LookupCache() {
-  munmap(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8);
-  munmap(reinterpret_cast<void*>(PageMemory), CODE_SIZE);
-  munmap(reinterpret_cast<void*>(L1Pointer), L1_SIZE);
+  FEXCore::Allocator::munmap(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8);
+  FEXCore::Allocator::munmap(reinterpret_cast<void*>(PageMemory), CODE_SIZE);
+  FEXCore::Allocator::munmap(reinterpret_cast<void*>(L1Pointer), L1_SIZE);
 }
 
 void LookupCache::HintUsedRange(uint64_t Address, uint64_t Size) {

External/FEXCore/Source/Interface/Core/LookupCache.h

@@ -35,11 +35,21 @@ public:
     }
   }
 
-  void AddBlockMapping(uint64_t Address, void *HostCode) { 
-    auto InsertPoint = BlockList.emplace(Address, (uintptr_t)HostCode);
-    LogMan::Throw::A(InsertPoint.second == true, "Dupplicate block mapping added");
+  std::map<uint64_t, std::vector<uint64_t>> CodePages;
 
-    // no need to update L1 or L2, they will get updated on first lookup
+  void AddBlockMapping(uint64_t Address, void *HostCode, uint64_t Start, uint64_t Length) { 
+    auto InsertPoint = BlockList.emplace(Address, (uintptr_t)HostCode);
+    LOGMAN_THROW_A(InsertPoint.second == true, "Dupplicate block mapping added");
+
+    for (auto CurrentPage = Start >> 12, EndPage = (Start + Length) >> 12; CurrentPage <= EndPage; CurrentPage++) {
+      CodePages[CurrentPage].push_back(Address);
+    }
+
+    // There is no need to update L1 or L2, they will get updated on first lookup
+    // However, adding to L1 here increases performance
+    auto &L1Entry = reinterpret_cast<LookupCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
+    L1Entry.GuestCode = Address;
+    L1Entry.HostCode = (uintptr_t)HostCode;
   }
 
   void Erase(uint64_t Address) {
@@ -88,8 +98,8 @@ public:
 
   void HintUsedRange(uint64_t Address, uint64_t Size);
 
-  uintptr_t GetL1Pointer() { return L1Pointer; }
-  uintptr_t GetPagePointer() { return PagePointer; }
+  uintptr_t GetL1Pointer() const { return L1Pointer; }
+  uintptr_t GetPagePointer() const { return PagePointer; }
   uintptr_t GetVirtualMemorySize() const { return VirtualMemSize; }
 
   constexpr static size_t L1_ENTRIES = 1 * 1024 * 1024; // Must be a power of 2
@@ -99,9 +109,8 @@ private:
   void CacheBlockMapping(uint64_t Address, uintptr_t HostCode) { 
     // Do L1
     auto &L1Entry = reinterpret_cast<LookupCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
-    if (L1Entry.GuestCode == Address) {
-      L1Entry.GuestCode = L1Entry.HostCode = 0;
-    }
+    L1Entry.GuestCode = Address;
+    L1Entry.HostCode = HostCode;
 
     // Do ful map
     auto FullAddress = Address;
@@ -197,6 +206,7 @@ private:
     }
   };
 
+
   std::map<BlockLinkTag, std::function<void()>> BlockLinks;
   std::map<uint64_t, uint64_t> BlockList;
 

External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -49,7 +49,7 @@ public:
 
   OrderedNode* GetNewJumpBlock(uint64_t RIP) {
     auto it = JumpTargets.find(RIP);
-    LogMan::Throw::A(it != JumpTargets.end(), "Couldn't find block generated for 0x%lx", RIP);
+    LOGMAN_THROW_A(it != JumpTargets.end(), "Couldn't find block generated for 0x%lx", RIP);
     return it->second.BlockEntry;
   }
 
@@ -59,7 +59,7 @@ public:
 
     it->second.HaveEmitted = true;
 
-    if (CurrentCodeBlock->Wrapped(ListData.Begin()).ID() == it->second.BlockEntry->Wrapped(ListData.Begin()).ID()) return;
+    if (CurrentCodeBlock->Wrapped(DualListData.ListBegin()).ID() == it->second.BlockEntry->Wrapped(DualListData.ListBegin()).ID()) return;
 
     // We have hit a RIP that is a jump target
     // Thus we need to end up in a new block
@@ -81,14 +81,15 @@ public:
     //  rdi, 0x8
     //  cmp qword [rdi-8], 0
     //  jne .label
-    if (!BlockSetRIP) {
+    if (LastOp && !BlockSetRIP) {
       auto it = JumpTargets.find(NextRIP);
-      if (it == JumpTargets.end() && LastOp) {
+      if (it == JumpTargets.end()) {
 
         uint8_t GPRSize = CTX->Config.Is64BitMode ? 8 : 4;
         // If we don't have a jump target to a new block then we have to leave
         // Set the RIP to the next instruction and leave
-        _ExitFunction(_Constant(GPRSize * 8, NextRIP));
+        auto RelocatedNextRIP = _EntrypointOffset(NextRIP - Entry, GPRSize);
+        _ExitFunction(RelocatedNextRIP);
       }
       else if (it != JumpTargets.end()) {
         _Jump(it->second.BlockEntry);
@@ -103,7 +104,8 @@ public:
   OpDispatchBuilder(FEXCore::Context::Context *ctx);
 
   void ResetWorkingList();
-  bool HadDecodeFailure() { return DecodeFailure; }
+  void ResetDecodeFailure() { DecodeFailure = false; }
+  bool HadDecodeFailure() const { return DecodeFailure; }
 
   void BeginFunction(uint64_t RIP, std::vector<FEXCore::Frontend::Decoder::DecodedBlocks> const *Blocks);
   void Finalize();
@@ -258,12 +260,6 @@ public:
   template<size_t ElementSize>
   void PSUBQOp(OpcodeArgs);
   template<size_t ElementSize>
-  void PMINUOp(OpcodeArgs);
-  template<size_t ElementSize>
-  void PMAXUOp(OpcodeArgs);
-  void PMINSWOp(OpcodeArgs);
-  void PMAXSWOp(OpcodeArgs);
-  template<size_t ElementSize>
   void MOVMSKOp(OpcodeArgs);
   void MOVMSKOpOne(OpcodeArgs);
   template<size_t ElementSize>
@@ -273,10 +269,6 @@ public:
   void PSHUFBOp(OpcodeArgs);
   template<size_t ElementSize, bool HalfSize, bool Low>
   void PSHUFDOp(OpcodeArgs);
-  template<size_t ElementSize>
-  void PCMPEQOp(OpcodeArgs);
-  template<size_t ElementSize>
-  void PCMPGTOp(OpcodeArgs);
   void MOVDOp(OpcodeArgs);
   template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
   void PSRLDOp(OpcodeArgs);
@@ -295,21 +287,21 @@ public:
   template<size_t ElementSize>
   void PAVGOp(OpcodeArgs);
   void MOVDDUPOp(OpcodeArgs);
-  template<size_t DstElementSize, bool Signed>
+  template<size_t DstElementSize>
   void CVTGPR_To_FPR(OpcodeArgs);
-  template<size_t SrcElementSize, bool Signed, bool HostRoundingMode>
+  template<size_t SrcElementSize, bool HostRoundingMode>
   void CVTFPR_To_GPR(OpcodeArgs);
-  template<size_t SrcElementSize, bool Signed, bool Widen>
+  template<size_t SrcElementSize, bool Widen>
   void Vector_CVT_Int_To_Float(OpcodeArgs);
   template<size_t DstElementSize, size_t SrcElementSize>
   void Scalar_CVT_Float_To_Float(OpcodeArgs);
   template<size_t DstElementSize, size_t SrcElementSize>
   void Vector_CVT_Float_To_Float(OpcodeArgs);
-  template<size_t SrcElementSize, bool Signed, bool Narrow, bool HostRoundingMode>
+  template<size_t SrcElementSize, bool Narrow, bool HostRoundingMode>
   void Vector_CVT_Float_To_Int(OpcodeArgs);
   template<size_t SrcElementSize, bool Signed, bool Widen>
   void MMX_To_XMM_Vector_CVT_Int_To_Float(OpcodeArgs);
-  template<size_t SrcElementSize, bool Signed, bool Narrow, bool HostRoundingMode>
+  template<size_t SrcElementSize, bool Narrow, bool HostRoundingMode>
   void XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs);
   void MASKMOVOp(OpcodeArgs);
   void MOVBetweenGPR_FPR(OpcodeArgs);
@@ -323,17 +315,13 @@ public:
   void ANDNOp(OpcodeArgs);
   template<size_t ElementSize>
   void PINSROp(OpcodeArgs);
+  void InsertPSOp(OpcodeArgs);
   template<size_t ElementSize>
   void PExtrOp(OpcodeArgs);
-  template<size_t ElementSize, bool Signed>
-  void PMULOp(OpcodeArgs);
 
   template<size_t ElementSize>
   void PSIGN(OpcodeArgs);
 
-  template<size_t ElementSize>
-  void PABS(OpcodeArgs);
-
   // X87 Ops
   template<size_t width>
   void FLD(OpcodeArgs);
@@ -349,6 +337,8 @@ public:
   void FST(OpcodeArgs);
 
   void FST(OpcodeArgs);
+
+  template<bool Truncate>
   void FIST(OpcodeArgs);
 
   enum class OpResult {
@@ -381,6 +371,7 @@ public:
   void X87TAN(OpcodeArgs);
   void X87ATAN(OpcodeArgs);
   void X87LDENV(OpcodeArgs);
+  void X87FLDCW(OpcodeArgs);
   void X87FNSTENV(OpcodeArgs);
   void X87FSTCW(OpcodeArgs);
   void X87LDSW(OpcodeArgs);
@@ -454,6 +445,8 @@ public:
   template<uint8_t FenceType>
   void FenceOp(OpcodeArgs);
 
+  void StoreFenceOrCLFlush(OpcodeArgs);
+
   void PSADBW(OpcodeArgs);
 
   void AESImcOp(OpcodeArgs);
@@ -463,6 +456,23 @@ public:
   void AESDecLastOp(OpcodeArgs);
   void AESKeyGenAssist(OpcodeArgs);
 
+  template<size_t ElementSize, size_t DstElementSize, bool Signed>
+  void ExtendVectorElements(OpcodeArgs);
+  template<size_t ElementSize, bool Scalar>
+  void VectorRound(OpcodeArgs);
+
+  template<size_t ElementSize>
+  void VectorBlend(OpcodeArgs);
+
+  template<size_t ElementSize>
+  void VectorVariableBlend(OpcodeArgs);
+  void PTestOp(OpcodeArgs);
+  void PHMINPOSUWOp(OpcodeArgs);
+  template<size_t ElementSize>
+  void DPPOp(OpcodeArgs);
+
+  void MPSADBWOp(OpcodeArgs);
+
   void UnimplementedOp(OpcodeArgs);
 
 #undef OpcodeArgs
@@ -471,22 +481,24 @@ public:
   OrderedNode *GetPackedRFLAG(bool Lower8);
 
   void SetMultiblock(bool _Multiblock) { Multiblock = _Multiblock; }
-  bool GetMultiblock() { return Multiblock; }
 
+  bool HandledLock = false;
 private:
   bool DecodeFailure{false};
   FEXCore::IR::IROp_IRHeader *Current_Header{};
+  OrderedNode *Current_HeaderNode{};
 
   OrderedNode *AppendSegmentOffset(OrderedNode *Value, uint32_t Flags, uint32_t DefaultPrefix = 0, bool Override = false);
 
+  OrderedNode *GetDynamicPC(FEXCore::X86Tables::DecodedOp const& Op, int64_t Offset = 0);
   OrderedNode *LoadSource(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp const& Op, FEXCore::X86Tables::DecodedOperand const& Operand, uint32_t Flags, int8_t Align, bool LoadData = true, bool ForceLoad = false);
   OrderedNode *LoadSource_WithOpSize(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp const& Op, FEXCore::X86Tables::DecodedOperand const& Operand, uint8_t OpSize, uint32_t Flags, int8_t Align, bool LoadData = true, bool ForceLoad = false);
   void StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp Op, FEXCore::X86Tables::DecodedOperand const& Operand, OrderedNode *const Src, uint8_t OpSize, int8_t Align);
   void StoreResult(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp Op, FEXCore::X86Tables::DecodedOperand const& Operand, OrderedNode *const Src, int8_t Align);
   void StoreResult(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp Op, OrderedNode *const Src, int8_t Align);
 
-  uint8_t GetDstSize(FEXCore::X86Tables::DecodedOp Op);
-  uint8_t GetSrcSize(FEXCore::X86Tables::DecodedOp Op);
+  uint8_t GetDstSize(FEXCore::X86Tables::DecodedOp Op) const;
+  uint8_t GetSrcSize(FEXCore::X86Tables::DecodedOp Op) const;
 
   template<unsigned BitOffset>
   void SetRFLAG(OrderedNode *Value);
@@ -516,12 +528,12 @@ private:
   OrderedNode * GetX87Top();
   void SetX87Top(OrderedNode *Value);
 
-  bool DestIsLockedMem(FEXCore::X86Tables::DecodedOp Op) {
-    return Op->Dest.TypeNone.Type !=FEXCore::X86Tables::DecodedOperand::TYPE_GPR && (Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_LOCK);
+  bool DestIsLockedMem(FEXCore::X86Tables::DecodedOp Op) const {
+    return DestIsMem(Op) && (Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_LOCK) != 0;
   }
 
-  bool DestIsMem(FEXCore::X86Tables::DecodedOp Op) {
-    return Op->Dest.TypeNone.Type !=FEXCore::X86Tables::DecodedOperand::TYPE_GPR;
+  bool DestIsMem(FEXCore::X86Tables::DecodedOp Op) const {
+    return !Op->Dest.IsGPR();
   }
 
   void CreateJumpBlocks(std::vector<FEXCore::Frontend::Decoder::DecodedBlocks> const *Blocks);

External/FEXCore/Source/Interface/Core/X86HelperGen.cpp

@@ -1,4 +1,12 @@
+/*
+$info$
+tags: glue|x86-guest-code
+desc: Guest-side assembly helpers used by the backends
+$end_info$
+*/
+
 #include "Interface/Core/X86HelperGen.h"
+#include <FEXCore/Utils/Allocator.h>
 
 #include <cstring>
 #include <stdlib.h>
@@ -24,15 +32,15 @@ X86GeneratedCode::X86GeneratedCode() {
 }
 
 X86GeneratedCode::~X86GeneratedCode() {
-  munmap(CodePtr, CODE_SIZE);
+  FEXCore::Allocator::munmap(CodePtr, CODE_SIZE);
 }
 
 void* X86GeneratedCode::AllocateGuestCodeSpace(size_t Size) {
-  FEXCore::Config::Value<bool> Is64BitMode{FEXCore::Config::CONFIG_IS64BIT_MODE, 0};
+  FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
 
   if (Is64BitMode()) {
     // 64bit mode can have its sigret handler anywhere
-    return mmap(nullptr, Size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+    return FEXCore::Allocator::mmap(nullptr, Size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
   }
 
   // First 64bit page
@@ -42,14 +50,14 @@ void* X86GeneratedCode::AllocateGuestCodeSpace(size_t Size) {
   // We need to have the sigret handler in the lower 32bits of memory space
   // Scan top down and try to allocate a location
   for (size_t Location = 0xFFFF'E000; Location != 0x0; Location -= 0x1000) {
-    void *Ptr = mmap(reinterpret_cast<void*>(Location), Size, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+    void *Ptr = FEXCore::Allocator::mmap(reinterpret_cast<void*>(Location), Size, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 
     if (Ptr != MAP_FAILED &&
         reinterpret_cast<uintptr_t>(Ptr) >= LOCATION_MAX) {
       // Failed to map in the lower 32bits
       // Try again
       // Can happen in the case that host kernel ignores MAP_FIXED_NOREPLACE
-      munmap(Ptr, Size);
+      FEXCore::Allocator::munmap(Ptr, Size);
       continue;
     }
 

External/FEXCore/Source/Interface/Core/X86HelperGen.h

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: glue|x86-guest-code
+$end_info$
+*/
+
 #pragma once
 #include <FEXCore/Config/Config.h>
 

External/FEXCore/Source/Interface/Core/X86Tables.cpp

@@ -1,3 +1,10 @@
+/*
+$info$
+meta: frontend|x86-tables ~ Metadata that drives the frontend x86/64 decoding
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include <FEXCore/Utils/LogManager.h>
 
 #include <FEXCore/Core/Context.h>

External/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 #include <FEXCore/Core/Context.h>
@@ -279,13 +285,13 @@ void InitializeBaseTables(Context::OperatingMode Mode) {
     {0xEA, 1, X86InstInfo{"JMPF",   TYPE_INST, FLAGS_NONE,                                                        0, nullptr}},
   };
 
-  GenerateTable(BaseOps, BaseOpTable, sizeof(BaseOpTable) / sizeof(BaseOpTable[0]));
+  GenerateTable(BaseOps, BaseOpTable, std::size(BaseOpTable));
 
   if (Mode == Context::MODE_64BIT) {
-    GenerateTable(BaseOps, BaseOpTable_64, sizeof(BaseOpTable_64) / sizeof(BaseOpTable_64[0]));
+    GenerateTable(BaseOps, BaseOpTable_64, std::size(BaseOpTable_64));
   }
   else {
-    GenerateTable(BaseOps, BaseOpTable_32, sizeof(BaseOpTable_32) / sizeof(BaseOpTable_32[0]));
+    GenerateTable(BaseOps, BaseOpTable_32, std::size(BaseOpTable_32));
   }
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/DDDTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -38,6 +44,6 @@ void InitializeDDDTables() {
     {0xB7, 1, X86InstInfo{"PMULHRW",  TYPE_3DNOW_INST, FLAGS_MODRM, 0, nullptr}},
   };
 
-  GenerateTable(DDDNowOps, DDDNowOpTable, sizeof(DDDNowOpTable) / sizeof(DDDNowOpTable[0]));
+  GenerateTable(DDDNowOps, DDDNowOpTable, std::size(DDDNowOpTable));
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/EVEXTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -20,6 +26,6 @@ void InitializeEVEXTables() {
     {0xE7, 1, X86InstInfo{"VMOVNTDQ",        TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
   };
 
-  GenerateTable(EVEXTableOps, EVEXTable, sizeof(EVEXTable) / sizeof(EVEXTable[0]));
+  GenerateTable(EVEXTableOps, EVEXTable, std::size(EVEXTable));
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/H0F38Tables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -35,10 +41,10 @@ void InitializeH0F38Tables() {
     {OPD(PF_38_NONE, 0x0B), 1, X86InstInfo{"PMULHRSW",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
     {OPD(PF_38_66,   0x0B), 1, X86InstInfo{"PMULHRSW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x10), 1, X86InstInfo{"PBLENDVB",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x14), 1, X86InstInfo{"BLENDVPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x15), 1, X86InstInfo{"BLENDVPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x17), 1, X86InstInfo{"PTEST",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(PF_38_66,   0x10), 1, X86InstInfo{"PBLENDVB",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x14), 1, X86InstInfo{"BLENDVPS",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x15), 1, X86InstInfo{"BLENDVPD",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x17), 1, X86InstInfo{"PTEST",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(PF_38_NONE, 0x1C), 1, X86InstInfo{"PABSB",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
     {OPD(PF_38_66,   0x1C), 1, X86InstInfo{"PABSB",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(PF_38_NONE, 0x1D), 1, X86InstInfo{"PABSW",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
@@ -46,34 +52,34 @@ void InitializeH0F38Tables() {
     {OPD(PF_38_NONE, 0x1E), 1, X86InstInfo{"PABSD",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
     {OPD(PF_38_66,   0x1E), 1, X86InstInfo{"PABSD",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x20), 1, X86InstInfo{"PMOVSXBW",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x21), 1, X86InstInfo{"PMOVSXBD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x22), 1, X86InstInfo{"PMOVSXBQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x23), 1, X86InstInfo{"PMOVSXWD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x24), 1, X86InstInfo{"PMOVSXWQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x25), 1, X86InstInfo{"PMOVSXDQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x28), 1, X86InstInfo{"PMULDQ",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x29), 1, X86InstInfo{"PCMPEQQ",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x2A), 1, X86InstInfo{"MOVNTDQA",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x2B), 1, X86InstInfo{"PACKUSDW",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(PF_38_66,   0x20), 1, X86InstInfo{"PMOVSXBW",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x21), 1, X86InstInfo{"PMOVSXBD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x22), 1, X86InstInfo{"PMOVSXBQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x23), 1, X86InstInfo{"PMOVSXWD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x24), 1, X86InstInfo{"PMOVSXWQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x25), 1, X86InstInfo{"PMOVSXDQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x28), 1, X86InstInfo{"PMULDQ",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x29), 1, X86InstInfo{"PCMPEQQ",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x2A), 1, X86InstInfo{"MOVNTDQA",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x2B), 1, X86InstInfo{"PACKUSDW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x30), 1, X86InstInfo{"PMOVZXBW",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x31), 1, X86InstInfo{"PMOVZXBD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x32), 1, X86InstInfo{"PMOVZXBQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x33), 1, X86InstInfo{"PMOVZXWD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x34), 1, X86InstInfo{"PMOVZXWQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x35), 1, X86InstInfo{"PMOVZXDQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x38), 1, X86InstInfo{"PMINSB",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x39), 1, X86InstInfo{"PMINSD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x3A), 1, X86InstInfo{"PMINUW",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x3B), 1, X86InstInfo{"PMINUD",     TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(PF_38_66,   0x3C), 1, X86InstInfo{"PMAXSB",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x3D), 1, X86InstInfo{"PMAXSD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x3E), 1, X86InstInfo{"PMAXUW",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x3F), 1, X86InstInfo{"PMAXUD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(PF_38_66,   0x30), 1, X86InstInfo{"PMOVZXBW",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x31), 1, X86InstInfo{"PMOVZXBD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x32), 1, X86InstInfo{"PMOVZXBQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x33), 1, X86InstInfo{"PMOVZXWD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x34), 1, X86InstInfo{"PMOVZXWQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x35), 1, X86InstInfo{"PMOVZXDQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x38), 1, X86InstInfo{"PMINSB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x39), 1, X86InstInfo{"PMINSD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3A), 1, X86InstInfo{"PMINUW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3B), 1, X86InstInfo{"PMINUD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3C), 1, X86InstInfo{"PMAXSB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3D), 1, X86InstInfo{"PMAXSD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3E), 1, X86InstInfo{"PMAXUW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3F), 1, X86InstInfo{"PMAXUD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x40), 1, X86InstInfo{"PMULLD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x41), 1, X86InstInfo{"PHMINPOSUW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(PF_38_66,   0x40), 1, X86InstInfo{"PMULLD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x41), 1, X86InstInfo{"PHMINPOSUW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
     {OPD(PF_38_66,   0xDB), 1, X86InstInfo{"AESIMC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(PF_38_66,   0xDC), 1, X86InstInfo{"AESENC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
@@ -92,6 +98,6 @@ void InitializeH0F38Tables() {
   };
 #undef OPD
 
-  GenerateTable(H0F38TableOps, H0F38Table, sizeof(H0F38Table) / sizeof(H0F38Table[0]));
+  GenerateTable(H0F38TableOps, H0F38Table, std::size(H0F38Table));
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/H0F3ATables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -10,26 +16,26 @@ void InitializeH0F3ATables(Context::OperatingMode Mode) {
 
   const U16U8InfoStruct H0F3ATable[] = {
     {OPD(0, PF_3A_NONE, 0x0F), 1, X86InstInfo{"PALIGNR",         TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
-    {OPD(0, PF_3A_66,   0x08), 1, X86InstInfo{"ROUNDPS",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x09), 1, X86InstInfo{"ROUNDPD",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x0A), 1, X86InstInfo{"ROUNDSS",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x0B), 1, X86InstInfo{"ROUNDSD",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x0C), 1, X86InstInfo{"BLENDPS",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x0D), 1, X86InstInfo{"BLENDPD",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x0E), 1, X86InstInfo{"PBLENDW",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(0, PF_3A_66,   0x08), 1, X86InstInfo{"ROUNDPS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x09), 1, X86InstInfo{"ROUNDPD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x0A), 1, X86InstInfo{"ROUNDSS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x0B), 1, X86InstInfo{"ROUNDSD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x0C), 1, X86InstInfo{"BLENDPS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
+    {OPD(0, PF_3A_66,   0x0D), 1, X86InstInfo{"BLENDPD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
+    {OPD(0, PF_3A_66,   0x0E), 1, X86InstInfo{"PBLENDW",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
     {OPD(0, PF_3A_66,   0x0F), 1, X86InstInfo{"PALIGNR",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
 
     {OPD(0, PF_3A_66,   0x14), 1, X86InstInfo{"PEXTRB",          TYPE_INST, GenFlagsSizes(SIZE_8BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
     {OPD(0, PF_3A_66,   0x15), 1, X86InstInfo{"PEXTRW",          TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
     {OPD(0, PF_3A_66,   0x16), 1, X86InstInfo{"PEXTRD",          TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
-    {OPD(0, PF_3A_66,   0x17), 1, X86InstInfo{"EXTRACTPS",       TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(0, PF_3A_66,   0x17), 1, X86InstInfo{"EXTRACTPS",       TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
 
-    {OPD(0, PF_3A_66,   0x20), 1, X86InstInfo{"PINSRB",          TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_8BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1, nullptr}},
-    {OPD(0, PF_3A_66,   0x21), 1, X86InstInfo{"INSERTPS",        TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(0, PF_3A_66,   0x20), 1, X86InstInfo{"PINSRB",          TYPE_INST, GenFlagsDstSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1, nullptr}},
+    {OPD(0, PF_3A_66,   0x21), 1, X86InstInfo{"INSERTPS",        TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
     {OPD(0, PF_3A_66,   0x22), 1, X86InstInfo{"PINSRD",          TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1, nullptr}},
-    {OPD(0, PF_3A_66,   0x40), 1, X86InstInfo{"DPPS",            TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x41), 1, X86InstInfo{"DPPD",            TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x42), 1, X86InstInfo{"MPSADBW",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(0, PF_3A_66,   0x40), 1, X86InstInfo{"DPPS",            TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x41), 1, X86InstInfo{"DPPD",            TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x42), 1, X86InstInfo{"MPSADBW",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
     {OPD(0, PF_3A_66,   0x44), 1, X86InstInfo{"PCLMULQDQ",       TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
 
     {OPD(0, PF_3A_66,   0x60), 1, X86InstInfo{"PCMPESTRM",       TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
@@ -48,10 +54,10 @@ void InitializeH0F3ATables(Context::OperatingMode Mode) {
 
 #undef OPD
 
-  GenerateTable(H0F3ATableOps, H0F3ATable, sizeof(H0F3ATable) / sizeof(H0F3ATable[0]));
+  GenerateTable(H0F3ATableOps, H0F3ATable, std::size(H0F3ATable));
 
   if (Mode == Context::MODE_64BIT) {
-    GenerateTable(H0F3ATableOps, H0F3ATable_64, sizeof(H0F3ATable_64) / sizeof(H0F3ATable_64[0]));
+    GenerateTable(H0F3ATableOps, H0F3ATable_64, std::size(H0F3ATable_64));
   }
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/PrimaryGroupTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -152,12 +158,12 @@ void InitializePrimaryGroupTables(Context::OperatingMode Mode) {
 
 #undef OPD
 
-  GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable, sizeof(PrimaryGroupOpTable) / sizeof(PrimaryGroupOpTable[0]));
+  GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable, std::size(PrimaryGroupOpTable));
   if (Mode == Context::MODE_64BIT) {
-    GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable_64, sizeof(PrimaryGroupOpTable_64) / sizeof(PrimaryGroupOpTable_64[0]));
+    GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable_64, std::size(PrimaryGroupOpTable_64));
   }
   else {
-    GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable_32, sizeof(PrimaryGroupOpTable_32) / sizeof(PrimaryGroupOpTable_32[0]));
+    GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable_32, std::size(PrimaryGroupOpTable_32));
   }
 
 }

External/FEXCore/Source/Interface/Core/X86Tables/SecondaryGroupTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -477,7 +483,7 @@ void InitializeSecondaryGroupTables() {
   };
 #undef OPD
 
-  GenerateTable(SecondInstGroupOps, SecondaryExtensionOpTable, sizeof(SecondaryExtensionOpTable) / sizeof(SecondaryExtensionOpTable[0]));
+  GenerateTable(SecondInstGroupOps, SecondaryExtensionOpTable, std::size(SecondaryExtensionOpTable));
 }
 
 }

External/FEXCore/Source/Interface/Core/X86Tables/SecondaryModRMTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -46,6 +52,6 @@ void InitializeSecondaryModRMTables() {
     {((3 << 3) | 7), 1, X86InstInfo{"",         TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
   };
 
-  GenerateTable(SecondModRMTableOps, SecondaryModRMExtensionOpTable, sizeof(SecondaryModRMExtensionOpTable) / sizeof(SecondaryModRMExtensionOpTable[0]));
+  GenerateTable(SecondModRMTableOps, SecondaryModRMExtensionOpTable, std::size(SecondaryModRMExtensionOpTable));
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/SecondaryTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
  #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -571,18 +577,18 @@ void InitializeSecondaryTables(Context::OperatingMode Mode) {
     {0xFF, 1, X86InstInfo{"",           TYPE_COPY_OTHER, FLAGS_NONE,                                                            0, nullptr}},
   };
 
-  GenerateTable(SecondBaseOps, TwoByteOpTable, sizeof(TwoByteOpTable) / sizeof(TwoByteOpTable[0]));
+  GenerateTable(SecondBaseOps, TwoByteOpTable, std::size(TwoByteOpTable));
 
 if (Mode == Context::MODE_64BIT) {
-    GenerateTable(SecondBaseOps, TwoByteOpTable_64, sizeof(TwoByteOpTable_64) / sizeof(TwoByteOpTable_64[0]));
+    GenerateTable(SecondBaseOps, TwoByteOpTable_64, std::size(TwoByteOpTable_64));
   }
   else {
-    GenerateTable(SecondBaseOps, TwoByteOpTable_32, sizeof(TwoByteOpTable_32) / sizeof(TwoByteOpTable_32[0]));
+    GenerateTable(SecondBaseOps, TwoByteOpTable_32, std::size(TwoByteOpTable_32));
   }
 
-  GenerateTableWithCopy(RepModOps, RepModOpTable, sizeof(RepModOpTable) / sizeof(RepModOpTable[0]), SecondBaseOps);
-  GenerateTableWithCopy(RepNEModOps, RepNEModOpTable,   sizeof(RepNEModOpTable) / sizeof(RepNEModOpTable[0]), SecondBaseOps);
-  GenerateTableWithCopy(OpSizeModOps, OpSizeModOpTable, sizeof(OpSizeModOpTable) / sizeof(OpSizeModOpTable[0]), SecondBaseOps);
+  GenerateTableWithCopy(RepModOps, RepModOpTable, std::size(RepModOpTable), SecondBaseOps);
+  GenerateTableWithCopy(RepNEModOps, RepNEModOpTable,   std::size(RepNEModOpTable), SecondBaseOps);
+  GenerateTableWithCopy(OpSizeModOps, OpSizeModOpTable, std::size(OpSizeModOpTable), SecondBaseOps);
 
 }
 

External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -500,7 +506,7 @@ void InitializeVEXTables() {
   };
 #undef OPD
 
-  GenerateTable(VEXTableOps, VEXTable, sizeof(VEXTable) / sizeof(VEXTable[0]));
-  GenerateTable(VEXTableGroupOps, VEXGroupTable, sizeof(VEXGroupTable) / sizeof(VEXGroupTable[0]));
+  GenerateTable(VEXTableOps, VEXTable, std::size(VEXTable));
+  GenerateTable(VEXTableGroupOps, VEXGroupTable, std::size(VEXGroupTable));
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #pragma once
 #include <FEXCore/Debug/X86Tables.h>
 
@@ -27,7 +33,7 @@ static inline void GenerateTable(X86InstInfo *FinalTable, U8U8InfoStruct const *
     auto OpNum = Op.first;
     X86InstInfo const &Info = Op.Info;
     for (uint32_t i = 0; i < Op.second; ++i) {
-      LogMan::Throw::A(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry %s->%s", FinalTable[OpNum + i].Name, Info.Name);
+      LOGMAN_THROW_A(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry %s->%s", FinalTable[OpNum + i].Name, Info.Name);
       FinalTable[OpNum + i] = Info;
 #ifndef NDEBUG
       ++Total;
@@ -44,7 +50,7 @@ static inline void GenerateTable(X86InstInfo *FinalTable, U16U8InfoStruct const
     auto OpNum = Op.first;
     X86InstInfo const &Info = Op.Info;
     for (uint32_t i = 0; i < Op.second; ++i) {
-      LogMan::Throw::A(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry %s->%s", FinalTable[OpNum + i].Name, Info.Name);
+      LOGMAN_THROW_A(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry %s->%s", FinalTable[OpNum + i].Name, Info.Name);
       FinalTable[OpNum + i] = Info;
 #ifndef NDEBUG
       ++Total;
@@ -61,7 +67,7 @@ static inline void GenerateTableWithCopy(X86InstInfo *FinalTable, U8U8InfoStruct
     auto OpNum = Op.first;
     X86InstInfo const &Info = Op.Info;
     for (uint32_t i = 0; i < Op.second; ++i) {
-      LogMan::Throw::A(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry %s->%s", FinalTable[OpNum + i].Name, Info.Name);
+      LOGMAN_THROW_A(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry %s->%s", FinalTable[OpNum + i].Name, Info.Name);
       if (Info.Type == TYPE_COPY_OTHER) {
         FinalTable[OpNum + i] = OtherLocal[OpNum + i];
       }
@@ -83,7 +89,7 @@ static inline void GenerateX87Table(X86InstInfo *FinalTable, U16U8InfoStruct con
     auto OpNum = Op.first;
     X86InstInfo const &Info = Op.Info;
     for (uint32_t i = 0; i < Op.second; ++i) {
-      LogMan::Throw::A(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry %s->%s", FinalTable[OpNum + i].Name, Info.Name);
+      LOGMAN_THROW_A(FinalTable[OpNum + i].Type == TYPE_UNKNOWN, "Duplicate Entry %s->%s", FinalTable[OpNum + i].Name, Info.Name);
       if ((OpNum & 0b11'000'000) == 0b11'000'000) {
         // If the mod field is 0b11 then it is a regular op
         FinalTable[OpNum + i] = Info;
@@ -91,7 +97,7 @@ static inline void GenerateX87Table(X86InstInfo *FinalTable, U16U8InfoStruct con
       else {
         // If the mod field is !0b11 then this instruction is duplicated through the whole mod [0b00, 0b10] range
         // and the modrm.rm space because that is used part of the instruction encoding
-        LogMan::Throw::A((OpNum & 0b11'000'000) == 0, "Only support mod field of zero in this path");
+        LOGMAN_THROW_A((OpNum & 0b11'000'000) == 0, "Only support mod field of zero in this path");
         for (uint16_t mod = 0b00'000'000; mod < 0b11'000'000; mod += 0b01'000'000) {
           for (uint16_t rm = 0b000; rm < 0b1'000; ++rm) {
             FinalTable[(OpNum | mod | rm) + i] = Info;

External/FEXCore/Source/Interface/Core/X86Tables/X87Tables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -254,6 +260,6 @@ void InitializeX87Tables() {
 #undef OPD
 #undef OPDReg
 
-  GenerateX87Table(X87Ops, X87OpTable, sizeof(X87OpTable) / sizeof(X87OpTable[0]));
+  GenerateX87Table(X87Ops, X87OpTable, std::size(X87OpTable));
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/XOPTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -119,7 +125,7 @@ void InitializeXOPTables() {
   };
 #undef OPD
 
-  GenerateTable(XOPTableOps, XOPTable, sizeof(XOPTable) / sizeof(XOPTable[0]));
-  GenerateTable(XOPTableGroupOps, XOPGroupTable, sizeof(XOPGroupTable) / sizeof(XOPGroupTable[0]));
+  GenerateTable(XOPTableOps, XOPTable, std::size(XOPTable));
+  GenerateTable(XOPTableGroupOps, XOPGroupTable, std::size(XOPGroupTable));
 }
 }

External/FEXCore/Source/Interface/HLE/Thunks/Thunks.cpp

@@ -1,3 +1,10 @@
+/*
+$info$
+meta: glue|thunks ~ FEXCore side of thunks: Registration, Lookup
+tags: glue|thunks
+$end_info$
+*/
+
 #include <FEXCore/Utils/LogManager.h>
 #include "Thunks.h"
 
@@ -7,6 +14,7 @@
 
 #include <string>
 #include <map>
+#include <array>
 #include <Interface/Context/Context.h>
 #include "Interface/Core/InternalThreadState.h"
 #include "FEXCore/Core/X86Enums.h"
@@ -22,23 +30,26 @@ static thread_local FEXCore::Core::InternalThreadState *Thread;
 
 
 namespace FEXCore {
-    
-    struct ExportEntry { const char* Name; ThunkedFunction* Fn; };
+
+    struct ExportEntry { uint8_t *sha256; ThunkedFunction* Fn; };
 
     class ThunkHandler_impl final: public ThunkHandler {
         std::shared_mutex ThunksMutex;
 
-        std::map<std::string, ThunkedFunction*> Thunks = {
-            { "fex:loadlib", &LoadLib}
+        std::map<IR::SHA256Sum, ThunkedFunction*> Thunks = {
+            {
+                // sha256(fex:loadlib)
+                { 0x27, 0x7e, 0xb7, 0x69, 0x5b, 0xe9, 0xab, 0x12, 0x6e, 0xf7, 0x85, 0x9d, 0x4b, 0xc9, 0xa2, 0x44, 0x46, 0xcf, 0xbd, 0xb5, 0x87, 0x43, 0xef, 0x28, 0xa2, 0x65, 0xba, 0xfc, 0x89, 0x0f, 0x77, 0x80},
+                &LoadLib
+            }
         };
 
         /*
             Set arg0/1 to arg regs, use CTX::HandleCallback to handle the callback
         */
         static void CallCallback(void *callback, void *arg0, void* arg1) {
-            
-            Thread->State.State.gregs[FEXCore::X86State::REG_RDI] = (uintptr_t)arg0;
-            Thread->State.State.gregs[FEXCore::X86State::REG_RSI] = (uintptr_t)arg1;
+            Thread->CurrentFrame->State.gregs[FEXCore::X86State::REG_RDI] = (uintptr_t)arg0;
+            Thread->CurrentFrame->State.gregs[FEXCore::X86State::REG_RSI] = (uintptr_t)arg1;
 
             Thread->CTX->HandleCallback((uintptr_t)callback);
         }
@@ -52,10 +63,10 @@ namespace FEXCore {
             auto Name = Args->Name;
             auto CallbackThunks = Args->CallbackThunks;
 
-            auto SOName = CTX->Config.ThunkLibsPath + "/" + (const char*)Name + "-host.so";
+            auto SOName = CTX->Config.ThunkHostLibsPath() + "/" + (const char*)Name + "-host.so";
 
             LogMan::Msg::D("Load lib: %s -> %s", Name, SOName.c_str());
-            
+
             auto Handle = dlopen(SOName.c_str(), RTLD_LOCAL | RTLD_NOW);
 
             if (!Handle) {
@@ -73,7 +84,7 @@ namespace FEXCore {
                 LogMan::Msg::E("Load lib: failed to find export %s", InitSym.c_str());
                 return;
             }
-            
+
             auto Exports = InitFN((void*)&CallCallback, CallbackThunks);
 
             auto That = reinterpret_cast<ThunkHandler_impl*>(CTX->ThunkHandler.get());
@@ -82,8 +93,8 @@ namespace FEXCore {
                 std::unique_lock lk(That->ThunksMutex);
 
                 int i;
-                for (i = 0; Exports[i].Name; i++) {
-                    That->Thunks[Exports[i].Name] = Exports[i].Fn;
+                for (i = 0; Exports[i].sha256; i++) {
+                    That->Thunks[*reinterpret_cast<IR::SHA256Sum*>(Exports[i].sha256)] = Exports[i].Fn;
                 }
 
                 LogMan::Msg::D("Loaded %d syms", i);
@@ -92,11 +103,11 @@ namespace FEXCore {
 
         public:
 
-        ThunkedFunction* LookupThunk(const char *Name) {
+        ThunkedFunction* LookupThunk(const IR::SHA256Sum &sha256) {
 
             std::shared_lock lk(ThunksMutex);
 
-            auto it = Thunks.find(Name);
+            auto it = Thunks.find(sha256);
 
             if (it != Thunks.end()) {
                 return it->second;

External/FEXCore/Source/Interface/HLE/Thunks/Thunks.h

@@ -1,4 +1,11 @@
+/*
+$info$
+tags: glue|thunks
+$end_info$
+*/
+
 #pragma once
+#include <FEXCore/IR/IR.h>
 
 namespace FEXCore::Core {
   struct InternalThreadState;
@@ -9,7 +16,7 @@ namespace FEXCore {
 
     class ThunkHandler {
     public:
-        virtual ThunkedFunction* LookupThunk(const char *name) = 0;
+        virtual ThunkedFunction* LookupThunk(const IR::SHA256Sum &sha256) = 0;
         virtual void RegisterTLSState(FEXCore::Core::InternalThreadState *Thread) = 0;
         virtual ~ThunkHandler() { }
 

External/FEXCore/Source/Interface/IR/IR.json

@@ -60,6 +60,12 @@
     "constexpr static uint8_t ROUND_MODE_TOWARDS_ZERO      = 3",
     "constexpr static uint8_t ROUND_MODE_FLUSH_TO_ZERO     = 1 << 2",
 
+    "static constexpr FEXCore::IR::RoundType Round_Nearest {ROUND_MODE_NEAREST}",
+    "static constexpr FEXCore::IR::RoundType Round_Negative_Infinity {ROUND_MODE_NEGATIVE_INFINITY}",
+    "static constexpr FEXCore::IR::RoundType Round_Positive_Infinity {ROUND_MODE_POSITIVE_INFINITY}",
+    "static constexpr FEXCore::IR::RoundType Round_Towards_Zero {ROUND_MODE_TOWARDS_ZERO} /* Truncate */",
+    "static constexpr FEXCore::IR::RoundType Round_Host {ROUND_MODE_TOWARDS_ZERO + 1}",
+
     "constexpr static FEXCore::IR::MemOffsetType MEM_OFFSET_SXTX {0};",
     "constexpr static FEXCore::IR::MemOffsetType MEM_OFFSET_UXTW {1};",
     "constexpr static FEXCore::IR::MemOffsetType MEM_OFFSET_SXTW {2};"
@@ -79,9 +85,7 @@
         "Blocks"
       ],
       "Args": [
-        "uint64_t", "Entry",
-        "uint32_t", "BlockCount",
-        "bool", "ShouldInterpret"
+        "uint32_t", "BlockCount"
       ]
     },
     "CodeBlock": {
@@ -133,17 +137,14 @@
       "Args": [
         "uint64_t", "CodeOriginalLow",
         "uint64_t", "CodeOriginalHigh",
-        "uint64_t", "CodePtr",
+        "int64_t", "Offset",
         "uint8_t", "CodeLength"
       ]
     },
 
     "RemoveCodeEntry": {
       "HasSideEffects": true,
-      "OpClass": "Misc",
-      "Args": [
-        "uint64_t", "RIP"
-      ]
+      "OpClass": "Misc"
     },
 
     "GuestCallDirect": {
@@ -284,6 +285,32 @@
       ]
     },
 
+    "EntrypointOffset": {
+      "Desc": ["Returns the <entrypoint> + Offset address"],
+      "OpClass": "ALU",
+      "HasDest": true,
+      "DestClass": "GPR",
+      "DestSize": "RegisterSize",
+      "Args": [
+        "int64_t", "Offset"
+      ],
+      "HelperArgs": [
+        "uint8_t", "RegisterSize"
+      ]
+    },
+
+    "InlineEntrypointOffset": {
+      "Desc": ["Returns the <entrypoint> + Offset address"],
+      "OpClass": "ALU",
+      "DestSize": "RegisterSize",
+      "Args": [
+        "int64_t", "Offset"
+      ],
+      "HelperArgs": [
+        "uint8_t", "RegisterSize"
+      ]
+    },
+
     "Constant": {
       "Desc": ["Generates a 64bit constant inside of a GPR",
                "Unsupported to create a constant in FPR"
@@ -644,8 +671,7 @@
         "ArgPtr"
       ],
       "Args":[
-        "const char*", "ThunkName",
-        "uintptr_t", "ThunkFnPtr"
+        "SHA256Sum", "ThunkNameHash"
       ]
     },
 
@@ -772,6 +798,17 @@
       ]
     },
 
+    "CacheLineClear": {
+      "Desc": ["Does a 64 byte cacheline clear at the address specified"
+              ],
+      "HasSideEffects": true,
+      "OpClass": "Memory",
+      "SSAArgs": "1",
+      "SSANames": [
+        "Addr"
+      ]
+    },
+
     "Add": {
       "Desc": [ "Integer Add",
                 "Will truncate to 64 or 32bits"
@@ -1117,7 +1154,11 @@
       "DestClass": "GPRPair",
       "FixedDestSize": "8",
       "NumElements": "2",
-      "SSAArgs": "1"
+      "SSAArgs": "2",
+      "SSANames": [
+        "Function",
+        "Leaf"
+      ]
     },
 
     "Bfi": {
@@ -1442,24 +1483,6 @@
       ]
     },
 
-    "Float_ToGPR_U": {
-      "Desc": ["Moves the scalar element to a GPR with conversion",
-               "Converts the 32bit or 64bit float to an unsigned integer",
-               "Rounding mode determined by host flag's rounding mode"
-              ],
-      "OpClass": "ALU",
-      "HasDest": true,
-      "DestClass": "GPR",
-      "DestSize": "ElementSize",
-      "SSAArgs": "1",
-      "SSANames": [
-        "Scalar"
-      ],
-      "Args": [
-        "uint8_t", "ElementSize"
-      ]
-    },
-
     "Float_ToGPR_S": {
       "Desc": ["Moves the scalar element to a GPR with conversion",
                "Converts the 32bit or 64bit float to an signed integer",
@@ -1468,30 +1491,16 @@
       "OpClass": "ALU",
       "HasDest": true,
       "DestClass": "GPR",
-      "DestSize": "ElementSize",
+      "DestSize": "DestElementSize",
       "SSAArgs": "1",
       "SSANames": [
         "Scalar"
       ],
-      "Args": [
-        "uint8_t", "ElementSize"
-      ]
-    },
-
-    "Float_ToGPR_ZU": {
-      "Desc": ["Moves the scalar element to a GPR with conversion",
-               "Converts the 32bit or 64bit float to an unsigned integer rounding towards zero (Truncating)"
-              ],
-      "OpClass": "ALU",
-      "HasDest": true,
-      "DestClass": "GPR",
-      "DestSize": "ElementSize",
-      "SSAArgs": "1",
-      "SSANames": [
-        "Scalar"
+      "HelperArgs": [
+        "uint8_t", "DestElementSize"
       ],
       "Args": [
-        "uint8_t", "ElementSize"
+        "uint8_t", "SrcElementSize"
       ]
     },
 
@@ -1502,13 +1511,16 @@
       "OpClass": "ALU",
       "HasDest": true,
       "DestClass": "GPR",
-      "DestSize": "ElementSize",
+      "DestSize": "DestElementSize",
       "SSAArgs": "1",
       "SSANames": [
         "Scalar"
       ],
+      "HelperArgs": [
+        "uint8_t", "DestElementSize"
+      ],
       "Args": [
-        "uint8_t", "ElementSize"
+        "uint8_t", "SrcElementSize"
       ]
     },
 
@@ -1538,7 +1550,6 @@
                "Depending on backend, may only support GPR printing"
               ],
       "OpClass": "Misc",
-      "DestSize": "GetOpSize(ssa0)",
       "SSAArgs": "1",
       "SSANames": [
         "Value"
@@ -1630,6 +1641,23 @@
       ]
     },
 
+    "VBic": {
+      "OpClass": "Vector",
+      "HasDest": true,
+      "DestClass": "FPR",
+      "DestSize": "RegisterSize",
+      "NumElements": "RegisterSize / ElementSize",
+      "SSAArgs": "2",
+      "SSANames": [
+        "Vector1",
+        "Vector2"
+      ],
+      "HelperArgs": [
+        "uint8_t", "RegisterSize",
+        "uint8_t", "ElementSize"
+      ]
+    },
+
     "VOr": {
       "OpClass": "Vector",
       "HasDest": true,
@@ -1775,8 +1803,8 @@
       "NumElements": "RegisterSize / ElementSize",
       "SSAArgs": "2",
       "SSANames": [
-        "Vector1",
-        "Vector2"
+        "VectorLower",
+        "VectorUpper"
       ],
       "HelperArgs": [
         "uint8_t", "RegisterSize",
@@ -1803,6 +1831,25 @@
       ]
     },
 
+    "VUMinV": {
+      "OpClass": "Vector",
+      "Desc": ["Does a horizontal vector unsigned minimum of elements across the source vector",
+               "Result is a zero extended scalar"
+              ],
+      "HasDest": true,
+      "DestClass": "FPR",
+      "DestSize": "RegisterSize",
+      "NumElements": "RegisterSize / ElementSize",
+      "SSAArgs": "1",
+      "SSANames": [
+        "Vector"
+      ],
+      "HelperArgs": [
+        "uint8_t", "RegisterSize",
+        "uint8_t", "ElementSize"
+      ]
+    },
+
     "VURAvg": {
       "OpClass": "Vector",
       "Desc": ["Does an unsigned rounded average", "dst_elem = (src1_elem + src2_elem + 1) >> 1"],
@@ -1839,6 +1886,24 @@
       ]
     },
 
+    "VPopcount": {
+      "OpClass": "Vector",
+      "Desc": ["Does a popcount for each element of the register"
+              ],
+      "HasDest": true,
+      "DestClass": "FPR",
+      "DestSize": "RegisterSize",
+      "NumElements": "RegisterSize / ElementSize",
+      "SSAArgs": "1",
+      "SSANames": [
+        "Vector"
+      ],
+      "HelperArgs": [
+        "uint8_t", "RegisterSize",
+        "uint8_t", "ElementSize"
+      ]
+    },
+
     "VFAdd": {
       "OpClass": "Vector",
       "HasDest": true,
@@ -1865,8 +1930,8 @@
       "NumElements": "RegisterSize / ElementSize",
       "SSAArgs": "2",
       "SSANames": [
-        "Vector1",
-        "Vector2"
+        "VectorLow",
+        "VectorHigh"
       ],
       "HelperArgs": [
         "uint8_t", "RegisterSize",
@@ -2158,6 +2223,40 @@
       ]
     },
 
+    "VUnZip": {
+      "OpClass": "Vector",
+      "HasDest": true,
+      "DestClass": "FPR",
+      "DestSize": "RegisterSize",
+      "NumElements": "RegisterSize / ElementSize",
+      "SSAArgs": "2",
+      "SSANames": [
+        "Lower",
+        "Upper"
+      ],
+      "HelperArgs": [
+        "uint8_t", "RegisterSize",
+        "uint8_t", "ElementSize"
+      ]
+    },
+
+    "VUnZip2": {
+      "OpClass": "Vector",
+      "HasDest": true,
+      "DestClass": "FPR",
+      "DestSize": "RegisterSize",
+      "NumElements": "RegisterSize / ElementSize",
+      "SSAArgs": "2",
+      "SSANames": [
+        "Lower",
+        "Upper"
+      ],
+      "HelperArgs": [
+        "uint8_t", "RegisterSize",
+        "uint8_t", "ElementSize"
+      ]
+    },
+
     "VBSL": {
       "Desc": ["Does a vector bitwise select.",
                "If the bit in the field is 1 then the corresponding bit is pulled from VectorTrue",
@@ -2549,6 +2648,26 @@
       ]
     },
 
+    "VDupElement": {
+      "Desc": ["Duplicates one element from the source register across the whole register"],
+      "OpClass": "Vector",
+      "HasDest": true,
+      "DestClass": "FPR",
+      "DestSize": "RegisterSize",
+      "NumElements": "RegisterSize / ElementSize",
+      "SSAArgs": "1",
+      "SSANames": [
+        "Vector"
+      ],
+      "HelperArgs": [
+        "uint8_t", "RegisterSize",
+        "uint8_t", "ElementSize"
+      ],
+      "Args": [
+        "uint8_t", "Index"
+      ]
+    },
+
     "VExtr": {
       "Desc": ["Concats two vector registers together and extracts a full width register from the element index",
                "Index is an element index. So it is offset by ElementSize argument",
@@ -2901,27 +3020,6 @@
       ]
     },
 
-    "Float_FromGPR_U": {
-      "OpClass": "Conv",
-      "Desc": ["Scalar op: Converts unsigned GPR to Scalar float",
-               "Zeroes the upper bits of the vector register"
-              ],
-      "HasDest": true,
-      "DestClass": "FPR",
-      "DestSize": "DstElementSize",
-      "NumElements": "1",
-      "SSAArgs": "1",
-      "SSANames": [
-        "GPR"
-      ],
-      "HelperArgs": [
-        "uint8_t", "DstElementSize"
-      ],
-      "Args": [
-        "uint8_t", "SrcElementSize"
-      ]
-    },
-
     "Float_FromGPR_S": {
       "OpClass": "Conv",
       "Desc": ["Scalar op: Converts signed GPR to Scalar float",
@@ -2998,25 +3096,6 @@
       ]
     },
 
-    "Vector_FToU": {
-      "OpClass": "Conv",
-      "Desc": ["Vector op: Converts float to unsigned integer",
-               "Rounding mode determined by host rounding mode"
-              ],
-      "HasDest": true,
-      "DestClass": "FPR",
-      "DestSize": "RegisterSize",
-      "NumElements": "RegisterSize / ElementSize",
-      "SSAArgs": "1",
-      "SSANames": [
-        "Vector"
-      ],
-      "HelperArgs": [
-        "uint8_t", "RegisterSize",
-        "uint8_t", "ElementSize"
-      ]
-    },
-
     "Vector_FToS": {
       "OpClass": "Conv",
       "Desc": ["Vector op: Converts float to signed integer, rounding towards zero",
@@ -3036,23 +3115,6 @@
       ]
     },
 
-    "Vector_FToZU": {
-      "OpClass": "Conv",
-      "Desc": "Vector op: Converts float to unsigned integer, rounding towards zero",
-      "HasDest": true,
-      "DestClass": "FPR",
-      "DestSize": "RegisterSize",
-      "NumElements": "RegisterSize / ElementSize",
-      "SSAArgs": "1",
-      "SSANames": [
-        "Vector"
-      ],
-      "HelperArgs": [
-        "uint8_t", "RegisterSize",
-        "uint8_t", "ElementSize"
-      ]
-    },
-
     "Vector_FToZS": {
       "OpClass": "Conv",
       "Desc": "Vector op: Converts float to signed integer, rounding towards zero",
@@ -3090,6 +3152,28 @@
       ]
     },
 
+    "Vector_FToI": {
+      "OpClass": "Conv",
+      "Desc": ["Vector op: Rounds float to integral",
+               "Rounding mode determined by argument"
+              ],
+      "HasDest": true,
+      "DestClass": "FPR",
+      "DestSize": "RegisterSize",
+      "NumElements": "RegisterSize / ElementSize",
+      "SSAArgs": "1",
+      "SSANames": [
+        "Vector"
+      ],
+      "HelperArgs": [
+        "uint8_t", "RegisterSize",
+        "uint8_t", "ElementSize"
+      ],
+      "Args":[
+        "FEXCore::IR::RoundType", "Round"
+      ]
+    },
+
     "VUMul": {
       "OpClass": "Vector",
       "HasDest": true,
@@ -3197,6 +3281,25 @@
       ]
     },
 
+    "VUABDL": {
+      "OpClass": "Vector",
+      "Desc": ["Unsigned Absolute Difference Long"
+              ],
+      "HasDest": true,
+      "DestClass": "FPR",
+      "DestSize": "RegisterSize",
+      "NumElements": "RegisterSize / (ElementSize << 1)",
+      "SSAArgs": "2",
+      "SSANames": [
+        "Vector1",
+        "Vector2"
+      ],
+      "HelperArgs": [
+        "uint8_t", "RegisterSize",
+        "uint8_t", "ElementSize"
+      ]
+    },
+
     "VTBL1": {
       "Desc": ["Does a vector table lookup from one register in to the destination",
                "Lookup is byte sized per byte element.",
@@ -3310,6 +3413,15 @@
       ]
     },
 
+    "F80LoadFCW": {
+      "OpClass": "Vector",
+      "HasSideEffects": true,
+      "SSAArgs": "1",
+      "SSANames": [
+        "X80FCW"
+      ]
+    },
+
     "F80Add": {
       "OpClass": "Vector",
       "HasDest": true,
@@ -3439,6 +3551,9 @@
       "SSANames": [
         "X80Src"
       ],
+      "Args": [
+        "bool", "Truncate"
+      ],
       "HelperArgs": [
         "uint8_t", "Size"
       ]

External/FEXCore/Source/Interface/IR/IRDumper.cpp

@@ -1,8 +1,17 @@
+/*
+$info$
+meta: ir|dumper ~ IR -> Text
+tags: ir|dumper
+$end_info$
+*/
+
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/LogManager.h>
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
+#include  <iomanip>
+
 namespace FEXCore::IR {
 #define IROP_GETNAME_IMPL
 #define IROP_GETRAARGS_IMPL
@@ -12,16 +21,23 @@ namespace FEXCore::IR {
 
 #include <FEXCore/IR/IRDefines.inc>
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView<false> const* IR, uint64_t Arg) {
+static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, const SHA256Sum &Arg) {
+  *out << "sha256:";
+  for(auto byte: Arg.data)
+    *out << std::hex << std::setfill('0') << std::setw(2) << (unsigned int)byte;
+}
+
+static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, uint64_t Arg) {
   *out << "#0x" << std::hex << Arg;
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView<false> const* IR, const char* Arg) {
+[[maybe_unused]]
+static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, const char* Arg) {
   *out <<  Arg;
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView<false> const* IR, CondClassType Arg) {
-  std::array<std::string, 22> CondNames = {
+static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, CondClassType Arg) {
+  static constexpr std::array<std::string_view, 22> CondNames = {
     "EQ",
     "NEQ",
     "UGE",
@@ -49,8 +65,8 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView<false>
   *out << CondNames[Arg];
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView<false> const* IR, MemOffsetType Arg) {
-  std::array<std::string, 3> Names = {
+static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, MemOffsetType Arg) {
+  static constexpr std::array<std::string_view, 3> Names = {
     "SXTX",
     "UXTW",
     "SXTW",
@@ -59,7 +75,7 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView<false>
   *out << Names[Arg];
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView<false> const* IR, RegisterClassType Arg) {
+static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, RegisterClassType Arg) {
   if (Arg == GPRClass.Val)
     *out << "GPR";
   else if (Arg == GPRFixedClass.Val)
@@ -74,7 +90,7 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView<false>
     *out << "Unknown Registerclass " << Arg;
 }
 
-static void PrintArg(std::stringstream *out, IRListView<false> const* IR, OrderedNodeWrapper Arg, IR::RegisterAllocationData *RAData) {
+static void PrintArg(std::stringstream *out, IRListView const* IR, OrderedNodeWrapper Arg, IR::RegisterAllocationData *RAData) {
   auto [CodeNode, IROp] = IR->at(Arg)();
 
   if (Arg.ID() == 0) {
@@ -83,7 +99,7 @@ static void PrintArg(std::stringstream *out, IRListView<false> const* IR, Ordere
     *out << "%ssa" << std::to_string(Arg.ID());
     if (RAData) {
       auto PhyReg = RAData->GetNodeRegister(Arg.ID());
-      
+
       switch (PhyReg.Class) {
         case FEXCore::IR::GPRClass.Val: *out << "(GPR"; break;
         case FEXCore::IR::GPRFixedClass.Val: *out << "(GPRFixed"; break;
@@ -123,7 +139,7 @@ static void PrintArg(std::stringstream *out, IRListView<false> const* IR, Ordere
   }
 }
 
-static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView<false> const* IR, FEXCore::IR::FenceType Arg) {
+static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::FenceType Arg) {
   if (Arg == IR::Fence_Load) {
     *out << "Loads";
   }
@@ -138,7 +154,18 @@ static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView<false>
   }
 }
 
-void Dump(std::stringstream *out, IRListView<false> const* IR, IR::RegisterAllocationData *RAData) {
+static void PrintArg(std::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::RoundType Arg) {
+  switch (Arg) {
+    case FEXCore::IR::Round_Nearest: *out << "Nearest"; break;
+    case FEXCore::IR::Round_Negative_Infinity: *out << "-Inf"; break;
+    case FEXCore::IR::Round_Positive_Infinity: *out << "+Inf"; break;
+    case FEXCore::IR::Round_Towards_Zero: *out << "Towards Zero"; break;
+    case FEXCore::IR::Round_Host: *out << "Host"; break;
+    default: *out << "<Unknown Round Type>"; break;
+  }
+}
+
+void Dump(std::stringstream *out, IRListView const* IR, IR::RegisterAllocationData *RAData) {
   auto HeaderOp = IR->GetHeader();
 
   int8_t CurrentIndent = 0;
@@ -151,7 +178,6 @@ void Dump(std::stringstream *out, IRListView<false> const* IR, IR::RegisterAlloc
   ++CurrentIndent;
   AddIndent();
   *out << "(%ssa0) " << "IRHeader ";
-  *out << "#0x" << std::hex << HeaderOp->Entry << ", ";
   *out << "%ssa" << HeaderOp->Blocks.ID() << ", ";
   *out << "#" << std::dec << HeaderOp->BlockCount << std::endl;
 

External/FEXCore/Source/Interface/IR/IREmitter.cpp

@@ -1,19 +1,25 @@
+/*
+$info$
+meta: ir|emitter ~ C++ Functions to generate IR. See IR.json for spec.
+tags: ir|emitter
+$end_info$
+*/
+
 #include <FEXCore/IR/IREmitter.h>
 
 namespace FEXCore::IR {
 void IREmitter::ResetWorkingList() {
-  Data.Reset();
-  ListData.Reset();
+  DualListData.Reset();
   CodeBlocks.clear();
   CurrentWriteCursor = nullptr;
   // This is necessary since we do "null" pointer checks
-  InvalidNode = reinterpret_cast<OrderedNode*>(ListData.Allocate(sizeof(OrderedNode)));
+  InvalidNode = reinterpret_cast<OrderedNode*>(DualListData.ListAllocate(sizeof(OrderedNode)));
   memset(InvalidNode, 0, sizeof(OrderedNode));
   CurrentCodeBlock = nullptr;
 }
 
 void IREmitter::ReplaceAllUsesWithRange(OrderedNode *Node, OrderedNode *NewNode, AllNodesIterator After, AllNodesIterator End) {
-  uintptr_t ListBegin = ListData.Begin();
+  uintptr_t ListBegin = DualListData.ListBegin();
   auto NodeId = Node->Wrapped(ListBegin).ID();
 
   while (After != End) {
@@ -38,8 +44,8 @@ void IREmitter::ReplaceAllUsesWithRange(OrderedNode *Node, OrderedNode *NewNode,
 }
 
 void IREmitter::ReplaceNodeArgument(OrderedNode *Node, uint8_t Arg, OrderedNode *NewArg) {
-  uintptr_t ListBegin = ListData.Begin();
-  uintptr_t DataBegin = Data.Begin();
+  uintptr_t ListBegin = DualListData.ListBegin();
+  uintptr_t DataBegin = DualListData.DataBegin();
 
   FEXCore::IR::IROp_Header *IROp = Node->Op(DataBegin);
   OrderedNodeWrapper OldArgWrapper = IROp->Args[Arg];
@@ -50,8 +56,8 @@ void IREmitter::ReplaceNodeArgument(OrderedNode *Node, uint8_t Arg, OrderedNode
 }
 
 void IREmitter::RemoveArgUses(OrderedNode *Node) {
-  uintptr_t ListBegin = ListData.Begin();
-  uintptr_t DataBegin = Data.Begin();
+  uintptr_t ListBegin = DualListData.ListBegin();
+  uintptr_t DataBegin = DualListData.DataBegin();
 
   FEXCore::IR::IROp_Header *IROp = Node->Op(DataBegin);
 
@@ -65,7 +71,7 @@ void IREmitter::RemoveArgUses(OrderedNode *Node) {
 void IREmitter::Remove(OrderedNode *Node) {
   RemoveArgUses(Node);
 
-  Node->Unlink(ListData.Begin());
+  Node->Unlink(DualListData.ListBegin());
 }
 
 IREmitter::IRPair<IROp_CodeBlock> IREmitter::CreateNewCodeBlockAfter(OrderedNode* insertAfter) {
@@ -76,14 +82,14 @@ IREmitter::IRPair<IROp_CodeBlock> IREmitter::CreateNewCodeBlockAfter(OrderedNode
   if (insertAfter) {
     LinkCodeBlocks(insertAfter, CodeNode);
   } else {
-    LogMan::Throw::A(CurrentCodeBlock != nullptr, "CurrentCodeBlock must not be null here");
-    
+    LOGMAN_THROW_A(CurrentCodeBlock != nullptr, "CurrentCodeBlock must not be null here");
+
     // Find last block
     auto LastBlock = CurrentCodeBlock;
 
-    while (LastBlock->Header.Next.GetNode(ListData.Begin()) != InvalidNode)
-      LastBlock = LastBlock->Header.Next.GetNode(ListData.Begin());
-    
+    while (LastBlock->Header.Next.GetNode(DualListData.ListBegin()) != InvalidNode)
+      LastBlock = LastBlock->Header.Next.GetNode(DualListData.ListBegin());
+
     // Append it after the last block
     LinkCodeBlocks(LastBlock, CodeNode);
   }
@@ -95,12 +101,12 @@ IREmitter::IRPair<IROp_CodeBlock> IREmitter::CreateNewCodeBlockAfter(OrderedNode
 
 void IREmitter::SetCurrentCodeBlock(OrderedNode *Node) {
   CurrentCodeBlock = Node;
-  LogMan::Throw::A(Node->Op(Data.Begin())->Op == OP_CODEBLOCK, "Node wasn't codeblock. It was '%s'", std::string(IR::GetName(Node->Op(Data.Begin())->Op)).c_str());
-  SetWriteCursor(Node->Op(Data.Begin())->CW<IROp_CodeBlock>()->Begin.GetNode(ListData.Begin()));
+  LOGMAN_THROW_A(Node->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Node wasn't codeblock. It was '%s'", std::string(IR::GetName(Node->Op(DualListData.DataBegin())->Op)).c_str());
+  SetWriteCursor(Node->Op(DualListData.DataBegin())->CW<IROp_CodeBlock>()->Begin.GetNode(DualListData.ListBegin()));
 }
 
 void IREmitter::ReplaceWithConstant(OrderedNode *Node, uint64_t Value) {
-    auto Header = Node->Op(Data.Begin());
+    auto Header = Node->Op(DualListData.DataBegin());
 
     if (IRSizes[Header->Op] >= sizeof(IROp_Constant)) {
       // Unlink any arguments the node currently has

External/FEXCore/Source/Interface/IR/IRParser.cpp

@@ -1,3 +1,10 @@
+/*
+$info$
+meta: ir|parser ~ Text -> IR
+tags: ir|parser
+$end_info$
+*/
+
 #include <string>
 #include <vector>
 #include <istream>
@@ -59,7 +66,8 @@ std::string DecodeErrorToString(DecodeFailure Failure) {
     case DecodeFailure::DECODE_INVALID_CONDFLAG: return "Invalid Conditional name";
     case DecodeFailure::DECODE_INVALID_MEMOFFSETTYPE: return "Invalid Memory Offset Type";
     case DecodeFailure::DECODE_INVALID_FENCETYPE: return "Invalid Fence Type";
-  };
+  }
+  return "Unknown Error";
 }
 
 std::unordered_map<std::string_view, FEXCore::IR::IROps> NameToOpMap;
@@ -67,22 +75,31 @@ std::unordered_map<std::string_view, FEXCore::IR::IROps> NameToOpMap;
 class IRParser: public FEXCore::IR::IREmitter {
   public:
   template<typename Type>
-  std::pair<DecodeFailure, Type> DecodeValue(std::string &Arg) {
+  std::pair<DecodeFailure, Type> DecodeValue(const std::string &Arg) {
     return {DecodeFailure::DECODE_UNKNOWN_TYPE, {}};
   }
 
 
   template<>
-  std::pair<DecodeFailure, uint8_t> DecodeValue(std::string &Arg) {
+  std::pair<DecodeFailure, uint8_t> DecodeValue(const std::string &Arg) {
     if (Arg.at(0) != '#') return {DecodeFailure::DECODE_INVALIDCHAR, 0};
 
     uint8_t Result = strtoul(&Arg.at(1), nullptr, 0);
     if (errno == ERANGE) return {DecodeFailure::DECODE_INVALIDRANGE, 0};
     return {DecodeFailure::DECODE_OKAY, Result};
-	}
+  }
 
   template<>
-  std::pair<DecodeFailure, uint16_t> DecodeValue(std::string &Arg) {
+  std::pair<DecodeFailure, bool> DecodeValue(const std::string &Arg) {
+    if (Arg.at(0) != '#') return {DecodeFailure::DECODE_INVALIDCHAR, 0};
+
+    uint8_t Result = strtoul(&Arg.at(1), nullptr, 0);
+    if (errno == ERANGE || Result > 1) return {DecodeFailure::DECODE_INVALIDRANGE, 0};
+    return {DecodeFailure::DECODE_OKAY, Result != 0};
+  }
+
+  template<>
+  std::pair<DecodeFailure, uint16_t> DecodeValue(const std::string &Arg) {
     if (Arg.at(0) != '#') return {DecodeFailure::DECODE_INVALIDCHAR, 0};
 
     uint16_t Result = strtoul(&Arg.at(1), nullptr, 0);
@@ -91,7 +108,7 @@ class IRParser: public FEXCore::IR::IREmitter {
   }
 
   template<>
-  std::pair<DecodeFailure, uint32_t> DecodeValue(std::string &Arg) {
+  std::pair<DecodeFailure, uint32_t> DecodeValue(const std::string &Arg) {
     if (Arg.at(0) != '#') return {DecodeFailure::DECODE_INVALIDCHAR, 0};
 
     uint32_t Result = strtoul(&Arg.at(1), nullptr, 0);
@@ -100,7 +117,7 @@ class IRParser: public FEXCore::IR::IREmitter {
   }
 
   template<>
-  std::pair<DecodeFailure, uint64_t> DecodeValue(std::string &Arg) {
+  std::pair<DecodeFailure, uint64_t> DecodeValue(const std::string &Arg) {
     if (Arg.at(0) != '#') return {DecodeFailure::DECODE_INVALIDCHAR, 0};
 
     uint64_t Result = strtoull(&Arg.at(1), nullptr, 0);
@@ -109,7 +126,47 @@ class IRParser: public FEXCore::IR::IREmitter {
   }
 
   template<>
-  std::pair<DecodeFailure, FEXCore::IR::RegisterClassType> DecodeValue(std::string &Arg) {
+  std::pair<DecodeFailure, int64_t> DecodeValue(const std::string &Arg) {
+    if (Arg.at(0) != '#') return {DecodeFailure::DECODE_INVALIDCHAR, 0};
+
+    int64_t Result = (int64_t)strtoull(&Arg.at(1), nullptr, 0);
+    if (errno == ERANGE) return {DecodeFailure::DECODE_INVALIDRANGE, 0};
+    return {DecodeFailure::DECODE_OKAY, Result};
+  }
+
+  template<>
+  std::pair<DecodeFailure, IR::SHA256Sum> DecodeValue(const std::string &Arg) {
+    IR::SHA256Sum Result;
+
+    if (Arg.at(0) != 's' || Arg.at(1) != 'h' || Arg.at(2) != 'a' || Arg.at(3) != '2' || Arg.at(4) != '5' || Arg.at(5) != '6' || Arg.at(6) != ':')
+      return {DecodeFailure::DECODE_INVALIDCHAR, Result};
+
+    auto GetDigit = [](const std::string &Arg, int pos, uint8_t *val) {
+      auto chr = Arg.at(pos);
+      if (chr >= '0' && chr <= '9') {
+        *val = chr - '0';
+        return true;
+      } else if (chr >= 'a' && chr <= 'f') {
+        *val = 10 + chr - 'a';
+        return true;
+      } else {
+        return false;
+      }
+    };
+
+    for (size_t i = 0; i < sizeof(Result.data); i++) {
+      uint8_t high, low;
+      if (!GetDigit(Arg, 7 + 2 * i + 0, &high) || !GetDigit(Arg, 7 + 2 * i + 1, &low)) {
+        return {DecodeFailure::DECODE_INVALIDRANGE, Result};
+      }
+      Result.data[i] = high * 16 + low;
+    }
+    
+    return {DecodeFailure::DECODE_OKAY, Result};
+  }
+
+  template<>
+  std::pair<DecodeFailure, FEXCore::IR::RegisterClassType> DecodeValue(const std::string &Arg) {
     if (Arg == "GPR") {
       return {DecodeFailure::DECODE_OKAY, FEXCore::IR::GPRClass};
     }
@@ -127,7 +184,7 @@ class IRParser: public FEXCore::IR::IREmitter {
   }
 
   template<>
-  std::pair<DecodeFailure, FEXCore::IR::TypeDefinition> DecodeValue(std::string &Arg) {
+  std::pair<DecodeFailure, FEXCore::IR::TypeDefinition> DecodeValue(const std::string &Arg) {
     uint8_t Size{}, Elements{1};
     int NumArgs = sscanf(Arg.c_str(), "i%hhdv%hhd", &Size, &Elements);
 
@@ -139,8 +196,8 @@ class IRParser: public FEXCore::IR::IREmitter {
   }
 
   template<>
-  std::pair<DecodeFailure, FEXCore::IR::CondClassType> DecodeValue(std::string &Arg) {
-    std::array<std::string, 22> CondNames = {
+  std::pair<DecodeFailure, FEXCore::IR::CondClassType> DecodeValue(const std::string &Arg) {
+    static constexpr std::array<std::string_view, 22> CondNames = {
       "EQ",
       "NEQ",
       "UGE",
@@ -174,8 +231,8 @@ class IRParser: public FEXCore::IR::IREmitter {
   }
 
   template<>
-  std::pair<DecodeFailure, FEXCore::IR::MemOffsetType> DecodeValue(std::string &Arg) {
-    std::array<std::string, 3> Names = {
+  std::pair<DecodeFailure, FEXCore::IR::MemOffsetType> DecodeValue(const std::string &Arg) {
+    static constexpr std::array<std::string_view, 3> Names = {
       "SXTX",
       "UXTW",
       "SXTW",
@@ -190,8 +247,8 @@ class IRParser: public FEXCore::IR::IREmitter {
   }
 
   template<>
-  std::pair<DecodeFailure, FEXCore::IR::FenceType> DecodeValue(std::string &Arg) {
-    std::array<std::string, 3> Names = {
+  std::pair<DecodeFailure, FEXCore::IR::FenceType> DecodeValue(const std::string &Arg) {
+    static constexpr std::array<std::string_view, 3> Names = {
       "Loads",
       "Stores",
       "LoadStores",
@@ -206,23 +263,22 @@ class IRParser: public FEXCore::IR::IREmitter {
   }
 
   template<>
-  std::pair<DecodeFailure, OrderedNode*> DecodeValue(std::string &Arg) {
+  std::pair<DecodeFailure, OrderedNode*> DecodeValue(const std::string &Arg) {
     if (Arg.at(0) != '%') return {DecodeFailure::DECODE_INVALIDCHAR, 0};
 
     // Strip off the type qualifier from the ssa value
-    size_t ArgEnd = std::string::npos;
     std::string SSAName = trim(Arg);
-    ArgEnd = SSAName.find_first_of(" ");
+    const size_t ArgEnd = SSAName.find_first_of(' ');
 
     if (ArgEnd != std::string::npos) {
-			SSAName = SSAName.substr(0, ArgEnd);
-		}
+      SSAName = SSAName.substr(0, ArgEnd);
+    }
 
-		// Forward declarations may make this not succed
+    // Forward declarations may make this not succed
     auto Op = SSANameMapper.find(SSAName);
-		if (Op == SSANameMapper.end()) {
+    if (Op == SSANameMapper.end()) {
       return {DecodeFailure::DECODE_UNKNOWN_SSA, nullptr};
-		}
+    }
 
     return {DecodeFailure::DECODE_OKAY, Op->second};
   }
@@ -246,21 +302,21 @@ class IRParser: public FEXCore::IR::IREmitter {
 
   IRParser(std::istream *text) {
     InitializeStaticTables();
-    
+
     std::string TmpLine;
     while (!text->eof()) {
       std::getline(*text, TmpLine);
-			if (text->eof()) {
-				break;
-			}
+      if (text->eof()) {
+        break;
+      }
       if (text->fail()) {
-        LogMan::Msg::E("Failed to getline on line: %ld", Lines.size());
+        LogMan::Msg::EFmt("Failed to getline on line: {}", Lines.size());
         return;
       }
       Lines.emplace_back(TmpLine);
     }
 
-		ResetWorkingList();
+    ResetWorkingList();
     Loaded = Parse();
   }
 
@@ -271,11 +327,11 @@ class IRParser: public FEXCore::IR::IREmitter {
 
 
   bool Parse() {
-    auto CheckPrintError = [&](LineDefinition &Def, DecodeFailure Failure) -> bool {
+    const auto CheckPrintError = [&](const LineDefinition &Def, DecodeFailure Failure) -> bool {
       if (Failure != DecodeFailure::DECODE_OKAY) {
-        LogMan::Msg::E("Error on Line: %d", Def.LineNumber);
-        LogMan::Msg::E("%s", Lines[Def.LineNumber].c_str());
-        LogMan::Msg::E("Value Couldn't be decoded due to %s", DecodeErrorToString(Failure).c_str());
+        LogMan::Msg::EFmt("Error on Line: {}", Def.LineNumber);
+        LogMan::Msg::EFmt("{}", Lines[Def.LineNumber]);
+        LogMan::Msg::EFmt("Value Couldn't be decoded due to {}", DecodeErrorToString(Failure));
         return false;
       }
 
@@ -283,13 +339,13 @@ class IRParser: public FEXCore::IR::IREmitter {
     };
 
     // String parse every line for our definitions
-		for (size_t i = 0; i < Lines.size(); ++i) {
-			std::string Line = Lines[i];
+    for (size_t i = 0; i < Lines.size(); ++i) {
+      std::string Line = Lines[i];
       LineDefinition Def{};
-			CurrentDef = &Def;
+      CurrentDef = &Def;
       Def.LineNumber = i;
 
-			Line = trim(Line);
+      Line = trim(Line);
 
       // Skip empty lines
       if (Line.empty()) {
@@ -303,35 +359,37 @@ class IRParser: public FEXCore::IR::IREmitter {
       }
 
       size_t CurrentPos{};
-			// Let's see if this node is assigning something first
-			if (Line[0] == '%') {
+      // Let's see if this node is assigning something first
+      if (Line[0] == '%') {
         size_t DefinitionEnd = std::string::npos;
-        if ((DefinitionEnd = Line.find_first_of("=", CurrentPos)) != std::string::npos) {
+        if ((DefinitionEnd = Line.find_first_of('=', CurrentPos)) != std::string::npos) {
           Def.Definition = Line.substr(0, DefinitionEnd);
           Def.Definition = trim(Def.Definition);
           Def.HasDefinition = true;
           CurrentPos = DefinitionEnd + 1; // +1 to ensure we go past then assignment
         }
         else {
-          LogMan::Msg::E("Error on Line: %d", i);
-          LogMan::Msg::E("%s", Lines[i].c_str());
-          LogMan::Msg::E("SSA declaration without assignment");
+          LogMan::Msg::EFmt("Error on Line: {}", i);
+          LogMan::Msg::EFmt("{}", Lines[i]);
+          LogMan::Msg::EFmt("SSA declaration without assignment");
           return false;
         }
-			}
+      }
 
       // Check if we are pulling in some IR from the IR Printer
       // Prints (%ssa%d) at the start of lines without a definition
       if (Line[0] == '(') {
         size_t DefinitionEnd = std::string::npos;
-        if ((DefinitionEnd = Line.find_first_of(")", CurrentPos)) != std::string::npos) {
+        if ((DefinitionEnd = Line.find_first_of(')', CurrentPos)) != std::string::npos) {
           size_t SSAEnd = std::string::npos;
-          if ((SSAEnd = Line.find_last_of(" ", DefinitionEnd)) != std::string::npos) {
+          if ((SSAEnd = Line.find_last_of(' ', DefinitionEnd)) != std::string::npos) {
             std::string Type = Line.substr(SSAEnd + 1, DefinitionEnd - SSAEnd - 1);
             Type = trim(Type);
 
             auto DefinitionSize = DecodeValue<FEXCore::IR::TypeDefinition>(Type);
-            if (!CheckPrintError(Def, DefinitionSize.first)) return false;
+            if (!CheckPrintError(Def, DefinitionSize.first)) {
+              return false;
+            }
             Def.Size = DefinitionSize.second;
           }
 
@@ -340,9 +398,9 @@ class IRParser: public FEXCore::IR::IREmitter {
           CurrentPos = DefinitionEnd + 1;
         }
         else {
-          LogMan::Msg::E("Error on Line: %d", i);
-          LogMan::Msg::E("%s", Lines[i].c_str());
-          LogMan::Msg::E("SSA value with numbered SSA provided but no closing parentheses");
+          LogMan::Msg::EFmt("Error on Line: {}", i);
+          LogMan::Msg::EFmt("{}", Lines[i]);
+          LogMan::Msg::EFmt("SSA value with numbered SSA provided but no closing parentheses");
           return false;
         }
       }
@@ -350,7 +408,7 @@ class IRParser: public FEXCore::IR::IREmitter {
       if (Def.HasDefinition) {
         // Let's check if we have a size declared with this variable
         size_t NameEnd = std::string::npos;
-        if ((NameEnd = Def.Definition.find_first_of(" ")) != std::string::npos) {
+        if ((NameEnd = Def.Definition.find_first_of(' ')) != std::string::npos) {
           std::string Type = Def.Definition.substr(NameEnd + 1);
           Type = trim(Type);
           Def.Definition = trim(Def.Definition.substr(0, NameEnd));
@@ -361,9 +419,9 @@ class IRParser: public FEXCore::IR::IREmitter {
         }
 
         if (Def.Definition == "%Invalid") {
-          LogMan::Msg::E("Error on Line: %d", i);
-          LogMan::Msg::E("%s", Lines[i].c_str());
-          LogMan::Msg::E("Definition tried to define reserved %Invalid ssa node");
+          LogMan::Msg::EFmt("Error on Line: {}", i);
+          LogMan::Msg::EFmt("{}", Lines[i]);
+          LogMan::Msg::EFmt("Definition tried to define reserved %Invalid ssa node");
           return false;
         }
       }
@@ -380,9 +438,9 @@ class IRParser: public FEXCore::IR::IREmitter {
       }
       else {
         if (RemainingLine.empty()) {
-          LogMan::Msg::E("Error on Line: %d", i);
-          LogMan::Msg::E("%s", Lines[i].c_str());
-          LogMan::Msg::E("Line without an IROp?");
+          LogMan::Msg::EFmt("Error on Line: {}", i);
+          LogMan::Msg::EFmt("{}", Lines[i]);
+          LogMan::Msg::EFmt("Line without an IROp?");
           return false;
         }
 
@@ -399,12 +457,10 @@ class IRParser: public FEXCore::IR::IREmitter {
         }
         else {
           while (!RemainingLine.empty()) {
-            size_t ArgEnd = std::string::npos;
-            ArgEnd = RemainingLine.find_first_of(",");
+            const size_t ArgEnd = RemainingLine.find(',');
+            std::string Arg = trim(RemainingLine.substr(0, ArgEnd));
 
-            std::string Arg = RemainingLine.substr(0, ArgEnd);
-            Arg = trim(Arg);
-            Def.Args.emplace_back(Arg);
+            Def.Args.emplace_back(std::move(Arg));
 
             RemainingLine.erase(0, ArgEnd+1); // +1 to ensure we go past the ','
             if (ArgEnd == std::string::npos)
@@ -413,17 +469,17 @@ class IRParser: public FEXCore::IR::IREmitter {
         }
       }
 
-      Defs.emplace_back(Def);
-		}
+      CurrentDef = &Defs.emplace_back(std::move(Def));
+    }
 
     // Ensure all of the ops are real ops
     for(size_t i = 0; i < Defs.size(); ++i) {
       auto &Def = Defs[i];
       auto Op = NameToOpMap.find(Def.IROp);
       if (Op == NameToOpMap.end()) {
-        LogMan::Msg::E("Error on Line: %d", Def.LineNumber);
-        LogMan::Msg::E("%s", Lines[Def.LineNumber].c_str());
-        LogMan::Msg::E("IROp '%s' doesn't exist", Def.IROp.c_str());
+        LogMan::Msg::EFmt("Error on Line: {}", Def.LineNumber);
+        LogMan::Msg::EFmt("{}", Lines[Def.LineNumber]);
+        LogMan::Msg::EFmt("IROp '{}' doesn't exist", Def.IROp);
         return false;
       }
       Def.OpEnum = Op->second;
@@ -433,40 +489,38 @@ class IRParser: public FEXCore::IR::IREmitter {
     IRPair<IROp_IRHeader> IRHeader;
     {
       auto &Def = Defs[0];
-			CurrentDef = &Def;
+      CurrentDef = &Def;
       if (Def.OpEnum != FEXCore::IR::IROps::OP_IRHEADER) {
-        LogMan::Msg::E("Error on Line: %d", Def.LineNumber);
-        LogMan::Msg::E("%s", Lines[Def.LineNumber].c_str());
-        LogMan::Msg::E("First op needs to be IRHeader. Was '%s'", Def.IROp.c_str());
+        LogMan::Msg::EFmt("Error on Line: {}", Def.LineNumber);
+        LogMan::Msg::EFmt("{}", Lines[Def.LineNumber]);
+        LogMan::Msg::EFmt("First op needs to be IRHeader. Was '{}'", Def.IROp);
         return false;
       }
 
-      auto Entry = DecodeValue<uint64_t>(Def.Args[0]);
-      auto CodeBlockCount = DecodeValue<uint64_t>(Def.Args[2]);
+      auto CodeBlockCount = DecodeValue<uint64_t>(Def.Args[1]);
 
-      if (!CheckPrintError(Def, Entry.first)) return false;
       if (!CheckPrintError(Def, CodeBlockCount.first)) return false;
 
-      IRHeader = _IRHeader(InvalidNode, Entry.second, CodeBlockCount.second, false);
+      IRHeader = _IRHeader(InvalidNode, CodeBlockCount.second);
     }
 
     SetWriteCursor(nullptr); // isolate the header from everything following
 
     // Initialize SSANameMapper with Invalid value
-    SSANameMapper["%Invalid"] = Invalid();
+    SSANameMapper.insert_or_assign("%Invalid", Invalid());
 
     // Spin through the blocks and generate basic block ops
     for(size_t i = 0; i < Defs.size(); ++i) {
       auto &Def = Defs[i];
       if (Def.OpEnum == FEXCore::IR::IROps::OP_CODEBLOCK) {
         auto CodeBlock = _CodeBlock(InvalidNode, InvalidNode);
-        SSANameMapper[Def.Definition] = CodeBlock.Node;
+        SSANameMapper.insert_or_assign(Def.Definition, CodeBlock.Node);
         Def.Node = CodeBlock.Node;
 
         if (i == 1) {
           // First code block is the entry block
           // Link the header to the first block
-          IRHeader.first->Blocks = CodeBlock.Node->Wrapped(ListData.Begin());
+          IRHeader.first->Blocks = CodeBlock.Node->Wrapped(DualListData.ListBegin());
         }
         CodeBlocks.emplace_back(CodeBlock.Node);
       }
@@ -478,63 +532,64 @@ class IRParser: public FEXCore::IR::IREmitter {
     FEXCore::IR::IROp_CodeBlock *CurrentBlockOp{};
     for(size_t i = 1; i < Defs.size(); ++i) {
       auto &Def = Defs[i];
-			CurrentDef = &Def;
-
+      CurrentDef = &Def;
 
       switch (Def.OpEnum) {
         // Special handled
         case FEXCore::IR::IROps::OP_IRHEADER:
-          LogMan::Msg::E("Error on Line: %d", Def.LineNumber);
-          LogMan::Msg::E("%s", Lines[Def.LineNumber].c_str());
-          LogMan::Msg::E("IRHEADER used in the middle of the block!");
+          LogMan::Msg::EFmt("Error on Line: {}", Def.LineNumber);
+          LogMan::Msg::EFmt("{}", Lines[Def.LineNumber]);
+          LogMan::Msg::EFmt("IRHEADER used in the middle of the block!");
           return false; // only one OP_IRHEADER allowed per block
 
         case FEXCore::IR::IROps::OP_CODEBLOCK: {
           SetWriteCursor(nullptr); // isolate from previous block
           if (CurrentBlock != nullptr) {
-            LogMan::Msg::E("Error on Line: %d", Def.LineNumber);
-            LogMan::Msg::E("%s", Lines[Def.LineNumber].c_str());
-            LogMan::Msg::E("CodeBlock being used inside of already existing codeblock!");
+            LogMan::Msg::EFmt("Error on Line: {}", Def.LineNumber);
+            LogMan::Msg::EFmt("{}", Lines[Def.LineNumber]);
+            LogMan::Msg::EFmt("CodeBlock being used inside of already existing codeblock!");
             return false;
           }
 
           CurrentBlock = Def.Node;
-          CurrentBlockOp = CurrentBlock->Op(Data.Begin())->CW<FEXCore::IR::IROp_CodeBlock>();
+          CurrentBlockOp = CurrentBlock->Op(DualListData.DataBegin())->CW<FEXCore::IR::IROp_CodeBlock>();
           break;
         }
 
 
         case FEXCore::IR::IROps::OP_BEGINBLOCK: {
           if (CurrentBlock == nullptr) {
-            LogMan::Msg::E("Error on Line: %d", Def.LineNumber);
-            LogMan::Msg::E("%s", Lines[Def.LineNumber].c_str());
-            LogMan::Msg::E("EndBlock being used outside of a block!");
+            LogMan::Msg::EFmt("Error on Line: {}", Def.LineNumber);
+            LogMan::Msg::EFmt("{}", Lines[Def.LineNumber]);
+            LogMan::Msg::EFmt("EndBlock being used outside of a block!");
             return false;
           }
 
           auto Adjust = DecodeValue<OrderedNode*>(Def.Args[0]);
-
-          if (!CheckPrintError(Def, Adjust.first)) return false;
+          if (!CheckPrintError(Def, Adjust.first)) {
+            return false;
+          }
 
           Def.Node = _BeginBlock(Adjust.second);
-          CurrentBlockOp->Begin = Def.Node->Wrapped(ListData.Begin());
+          CurrentBlockOp->Begin = Def.Node->Wrapped(DualListData.ListBegin());
           break;
         }
 
         case FEXCore::IR::IROps::OP_ENDBLOCK: {
           if (CurrentBlock == nullptr) {
-            LogMan::Msg::E("Error on Line: %d", Def.LineNumber);
-            LogMan::Msg::E("%s", Lines[Def.LineNumber].c_str());
-            LogMan::Msg::E("EndBlock being used outside of a block!");
+            LogMan::Msg::EFmt("Error on Line: {}", Def.LineNumber);
+            LogMan::Msg::EFmt("{}", Lines[Def.LineNumber]);
+            LogMan::Msg::EFmt("EndBlock being used outside of a block!");
             return false;
           }
 
           auto Adjust = DecodeValue<OrderedNode*>(Def.Args[0]);
-
-          if (!CheckPrintError(Def, Adjust.first)) return false;
+          if (!CheckPrintError(Def, Adjust.first)) {
+            return false;
+          }
 
           Def.Node = _EndBlock(Adjust.second);
-          CurrentBlockOp->Last = Def.Node->Wrapped(ListData.Begin());
+          CurrentBlockOp->Last = Def.Node->Wrapped(DualListData.ListBegin());
 
           CurrentBlock = nullptr;
           CurrentBlockOp = nullptr;
@@ -543,25 +598,23 @@ class IRParser: public FEXCore::IR::IREmitter {
         }
 
         case FEXCore::IR::IROps::OP_DUMMY: {
-          LogMan::Msg::E("Error on Line: %d", Def.LineNumber);
-          LogMan::Msg::E("%s", Lines[Def.LineNumber].c_str());
-          LogMan::Msg::E("Dummy op must not be used");
-
+          LogMan::Msg::EFmt("Error on Line: {}", Def.LineNumber);
+          LogMan::Msg::EFmt("{}", Lines[Def.LineNumber]);
+          LogMan::Msg::EFmt("Dummy op must not be used");
           break;
         }
 #define IROP_PARSER_SWITCH_HELPERS
 #include <FEXCore/IR/IRDefines.inc>
         default: {
-          LogMan::Msg::E("Error on Line: %d", Def.LineNumber);
-          LogMan::Msg::E("%s", Lines[Def.LineNumber].c_str());
-          LogMan::Msg::E("Unhandled Op enum '%s' in parser", Def.IROp.c_str());
+          LogMan::Msg::EFmt("Error on Line: {}", Def.LineNumber);
+          LogMan::Msg::EFmt("{}", Lines[Def.LineNumber]);
+          LogMan::Msg::EFmt("Unhandled Op enum '{}' in parser", Def.IROp);
           return false;
-          break;
         }
       }
 
       if (Def.HasDefinition) {
-        auto IROp = Def.Node->Op(Data.Begin());
+        auto IROp = Def.Node->Op(DualListData.DataBegin());
         if (Def.Size.Elements()) {
           IROp->Size = Def.Size.Bytes() * Def.Size.Elements();
           IROp->ElementSize = Def.Size.Bytes();
@@ -570,7 +623,7 @@ class IRParser: public FEXCore::IR::IREmitter {
           IROp->Size = Def.Size.Bytes();
           IROp->ElementSize = 0;
         }
-        SSANameMapper[Def.Definition] = Def.Node;
+        SSANameMapper.insert_or_assign(Def.Definition, Def.Node);
       }
     }
 
@@ -578,11 +631,11 @@ class IRParser: public FEXCore::IR::IREmitter {
 	}
 
   void InitializeStaticTables() {
-    if (NameToOpMap.size() == 0) {
+    if (NameToOpMap.empty()) {
       for (FEXCore::IR::IROps Op = FEXCore::IR::IROps::OP_DUMMY;
          Op <= FEXCore::IR::IROps::OP_LAST;
          Op = static_cast<FEXCore::IR::IROps>(static_cast<uint32_t>(Op) + 1)) {
-        NameToOpMap[FEXCore::IR::GetName(Op)] = Op;
+        NameToOpMap.insert_or_assign(FEXCore::IR::GetName(Op), Op);
       }
     }
   }
@@ -590,13 +643,12 @@ class IRParser: public FEXCore::IR::IREmitter {
 
 } // anon namespace
 
-IREmitter* Parse(std::istream *in) {
-    auto parser = new IRParser(in);
+std::unique_ptr<IREmitter> Parse(std::istream *in) {
+    auto parser = std::make_unique<IRParser>(in);
 
     if (parser->Loaded) {
       return parser;
     } else {
-      delete parser;
       return nullptr;
     }
 }