Implements BTC, BTR, BTS atomic unit tests

This just takes the regular non-atomic unit tests and changes them to
have lock prefixes.
These are all handled as byte sized atomics so there aren't any
alignment problems.

unittests/ASM/Secondary/08_XX_05_3_Atomic.asm

@@ -0,0 +1,37 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0x3"
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0x0000000100000000
+mov [rdx + 8 * 0], rax
+
+xor r15, r15 ; Will contain our results
+
+lock bts qword [rdx], 32
+cfmerge
+
+bt qword [rdx], 32
+cfmerge
+
+hlt

unittests/ASM/Secondary/08_XX_05_Atomic.asm

@@ -0,0 +1,61 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0x1F"
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0xFFFFFFFF80000000
+mov [rdx + 8 * 0], rax
+mov [rdx + 8 * 1], rax
+mov rax, 0x0
+mov [rdx + 8 * 2], rax
+mov rax, 0x01
+mov [rdx + 8 * 3], eax
+mov rax, 0x0
+mov [rdx + 8 * 3 + 4], eax
+
+xor r15, r15 ; Will contain our results
+
+; Test and set
+lock bts word [rdx], 1
+cfmerge
+
+; Ensure it is set
+bt word [rdx], 1
+cfmerge
+
+mov r13, 32
+lock bts dword [rdx], r13d
+cfmerge
+
+bt dword [rdx], r13d
+cfmerge
+
+lock bts qword [rdx], 64 * 2 + 63
+cfmerge
+
+bt qword [rdx], 64 * 2 + 63
+cfmerge
+
+hlt
+
+

unittests/ASM/Secondary/08_XX_06_3_Atomic.asm

@@ -0,0 +1,39 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0x2"
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0x0000000100000000
+mov [rdx + 8 * 0], rax
+
+xor r15, r15 ; Will contain our results
+
+lock btr qword [rdx], 32
+cfmerge
+
+bt qword [rdx], 32
+cfmerge
+
+hlt
+
+

unittests/ASM/Secondary/08_XX_06_Atomic.asm

@@ -0,0 +1,61 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0xA"
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0xFFFFFFFF80000000
+mov [rdx + 8 * 0], rax
+mov [rdx + 8 * 1], rax
+mov rax, 0x0
+mov [rdx + 8 * 2], rax
+mov rax, 0x01
+mov [rdx + 8 * 3], eax
+mov rax, 0x0
+mov [rdx + 8 * 3 + 4], eax
+
+xor r15, r15 ; Will contain our results
+
+; Test and set
+lock btr word [rdx], 1
+cfmerge
+
+; Ensure it is set
+bt word [rdx], 1
+cfmerge
+
+mov r13, 32
+lock btr dword [rdx], r13d
+cfmerge
+
+bt dword [rdx], r13d
+cfmerge
+
+lock btr qword [rdx], 64 * 2 + 63
+cfmerge
+
+bt qword [rdx], 64 * 2 + 63
+cfmerge
+
+hlt
+
+

unittests/ASM/Secondary/08_XX_07_3_Atomic.asm

@@ -0,0 +1,37 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0x2"
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0x0000000100000000
+mov [rdx + 8 * 0], rax
+
+xor r15, r15 ; Will contain our results
+
+lock btc qword [rdx], 32
+cfmerge
+
+bt qword [rdx], 32
+cfmerge
+
+hlt

unittests/ASM/Secondary/08_XX_07_Atomic.asm

@@ -0,0 +1,61 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0x1A"
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0xFFFFFFFF80000000
+mov [rdx + 8 * 0], rax
+mov [rdx + 8 * 1], rax
+mov rax, 0x0
+mov [rdx + 8 * 2], rax
+mov rax, 0x01
+mov [rdx + 8 * 3], eax
+mov rax, 0x0
+mov [rdx + 8 * 3 + 4], eax
+
+xor r15, r15 ; Will contain our results
+
+; Test and set
+lock btc word [rdx], 1
+cfmerge
+
+; Ensure it is set
+bt word [rdx], 1
+cfmerge
+
+mov r13, 32
+lock btc dword [rdx], r13d
+cfmerge
+
+bt dword [rdx], r13d
+cfmerge
+
+lock btc qword [rdx], 64 * 2 + 63
+cfmerge
+
+bt qword [rdx], 64 * 2 + 63
+cfmerge
+
+hlt
+
+

unittests/ASM/TwoByte/0F_AB_2_Atomic.asm

@@ -0,0 +1,61 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0x1F"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0xFFFFFFFF80000000
+mov [rdx + 8 * 0], rax
+mov [rdx + 8 * 1], rax
+mov [rdx + 8 * 2], rax
+mov rax, 0x01
+mov [rdx + 8 * 3], eax
+mov rax, 0x0
+mov [rdx + 8 * 3 + 4], eax
+
+lea rdx, [rdx + 8 * 3 + 4]
+
+xor r15, r15 ; Will contain our results
+
+; Test and set
+mov r13, -1
+lock bts word [rdx], r13w
+cfmerge
+
+; Ensure it is set
+mov r13, -1
+bt word [rdx], r13w
+cfmerge
+
+mov r13, -32
+lock bts dword [rdx], r13d
+cfmerge
+
+bt dword [rdx], r13d
+cfmerge
+
+mov r13, -64 * 3
+lock bts qword [rdx], r13
+cfmerge
+
+mov r13, -64 * 3
+bt qword [rdx], r13
+cfmerge
+
+hlt

unittests/ASM/TwoByte/0F_AB_Atomic.asm

@@ -0,0 +1,62 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0x1F"
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0xFFFFFFFF80000000
+mov [rdx + 8 * 0], rax
+mov [rdx + 8 * 1], rax
+mov [rdx + 8 * 2], rax
+mov rax, 0x01
+mov [rdx + 8 * 3], eax
+mov rax, 0x0
+mov [rdx + 8 * 3 + 4], eax
+
+xor r15, r15 ; Will contain our results
+
+; Test and set
+mov r13, 1
+lock bts word [rdx], r13w
+cfmerge
+
+; Ensure it is set
+mov r13, 1
+bt word [rdx], r13w
+cfmerge
+
+mov r13, 32
+lock bts dword [rdx], r13d
+cfmerge
+
+bt dword [rdx], r13d
+cfmerge
+
+mov r13, 64 * 3
+lock bts qword [rdx], r13
+cfmerge
+
+mov r13, 64 * 3
+bt qword [rdx], r13
+cfmerge
+
+hlt

unittests/ASM/TwoByte/0F_B3_2_Atomic.asm

@@ -0,0 +1,63 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0xA"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0xFFFFFFFF80000000
+mov [rdx + 8 * 0], rax
+mov [rdx + 8 * 1], rax
+mov [rdx + 8 * 2], rax
+mov rax, 0x01
+mov [rdx + 8 * 3], eax
+mov rax, 0x0
+mov [rdx + 8 * 3 + 4], eax
+
+lea rdx, [rdx + 8 * 3 + 4]
+
+xor r15, r15 ; Will contain our results
+
+; Test and set
+mov r13, -1
+lock btr word [rdx], r13w
+cfmerge
+
+; Ensure it is set
+mov r13, -1
+bt word [rdx], r13w
+cfmerge
+
+mov r13, -32
+lock btr dword [rdx], r13d
+cfmerge
+
+bt dword [rdx], r13d
+cfmerge
+
+mov r13, -64 * 3
+lock btr qword [rdx], r13
+cfmerge
+
+mov r13, -64 * 3
+bt qword [rdx], r13
+cfmerge
+
+hlt
+
+

unittests/ASM/TwoByte/0F_B3_Atomic.asm

@@ -0,0 +1,64 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0xA"
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0xFFFFFFFF80000000
+mov [rdx + 8 * 0], rax
+mov [rdx + 8 * 1], rax
+mov [rdx + 8 * 2], rax
+mov rax, 0x01
+mov [rdx + 8 * 3], eax
+mov rax, 0x0
+mov [rdx + 8 * 3 + 4], eax
+
+xor r15, r15 ; Will contain our results
+
+; Test and set
+mov r13, 1
+lock btr word [rdx], r13w
+cfmerge
+
+; Ensure it is set
+mov r13, 1
+bt word [rdx], r13w
+cfmerge
+
+mov r13, 32
+lock btr dword [rdx], r13d
+cfmerge
+
+bt dword [rdx], r13d
+cfmerge
+
+mov r13, 64 * 3
+lock btr qword [rdx], r13
+cfmerge
+
+mov r13, 64 * 3
+bt qword [rdx], r13
+cfmerge
+
+hlt
+
+

unittests/ASM/TwoByte/0F_BB_2_Atomic.asm

@@ -0,0 +1,61 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0x1A"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0xFFFFFFFF80000000
+mov [rdx + 8 * 0], rax
+mov [rdx + 8 * 1], rax
+mov [rdx + 8 * 2], rax
+mov rax, 0x01
+mov [rdx + 8 * 3], eax
+mov rax, 0x0
+mov [rdx + 8 * 3 + 4], eax
+
+lea rdx, [rdx + 8 * 3 + 4]
+
+xor r15, r15 ; Will contain our results
+
+; Test and set
+mov r13, -1
+lock btc word [rdx], r13w
+cfmerge
+
+; Ensure it is set
+mov r13, -1
+bt word [rdx], r13w
+cfmerge
+
+mov r13, -32
+lock btc dword [rdx], r13d
+cfmerge
+
+bt dword [rdx], r13d
+cfmerge
+
+mov r13, -64 * 3
+lock btc qword [rdx], r13
+cfmerge
+
+mov r13, -64 * 3
+bt qword [rdx], r13
+cfmerge
+
+hlt

unittests/ASM/TwoByte/0F_BB_Atomic.asm

@@ -0,0 +1,62 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "R15": "0x1A"
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+%macro cfmerge 0
+
+; Get CF
+sbb r14, r14
+and r14, 1
+
+; Merge in to results
+shl r15, 1
+or r15, r14
+
+%endmacro
+
+mov rdx, 0xe0000000
+
+mov rax, 0xFFFFFFFF80000000
+mov [rdx + 8 * 0], rax
+mov [rdx + 8 * 1], rax
+mov [rdx + 8 * 2], rax
+mov rax, 0x01
+mov [rdx + 8 * 3], eax
+mov rax, 0x0
+mov [rdx + 8 * 3 + 4], eax
+
+xor r15, r15 ; Will contain our results
+
+; Test and set
+mov r13, 1
+lock btc word [rdx], r13w
+cfmerge
+
+; Ensure it is set
+mov r13, 1
+bt word [rdx], r13w
+cfmerge
+
+mov r13, 32
+lock btc dword [rdx], r13d
+cfmerge
+
+bt dword [rdx], r13d
+cfmerge
+
+mov r13, 64 * 3
+lock btc qword [rdx], r13
+cfmerge
+
+mov r13, 64 * 3
+bt qword [rdx], r13
+cfmerge
+
+hlt