Merge pull request #792 from Sonicadvance1/implemented_unaligned_memory_ops

Implements unaligned atomic memory ops for ARMv8.1+

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64.h

@@ -9,6 +9,22 @@ namespace FEXCore::ArchHelpers::Arm64 {
   constexpr uint32_t CASAL_MASK = 0x3F'E0'FC'00;
   constexpr uint32_t CASAL_INST = 0x08'E0'FC'00;
 
+  constexpr uint32_t ATOMIC_MEM_MASK = 0x3B200C00;
+  constexpr uint32_t ATOMIC_MEM_INST = 0x38200000;
+
+  // Load ops are 4 bits
+  // Acquire and release bits are independent on the instruction
+  constexpr uint32_t ATOMIC_ADD_OP  = 0b0000;
+  constexpr uint32_t ATOMIC_CLR_OP  = 0b0001;
+  constexpr uint32_t ATOMIC_EOR_OP  = 0b0010;
+  constexpr uint32_t ATOMIC_SET_OP  = 0b0011;
+  constexpr uint32_t ATOMIC_SMAX_OP = 0b0100;
+  constexpr uint32_t ATOMIC_SMIN_OP = 0b0101;
+  constexpr uint32_t ATOMIC_UMAX_OP = 0b0110;
+  constexpr uint32_t ATOMIC_UMIN_OP = 0b0111;
+  constexpr uint32_t ATOMIC_SWAP_OP = 0b1000;
+
   bool HandleCASPAL(void *_mcontext, void *_info, uint32_t Instr);
   bool HandleCASAL(void *_mcontext, void *_info, uint32_t Instr);
+  bool HandleAtomicMemOp(void *_mcontext, void *_info, uint32_t Instr);
 }

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp

@@ -65,6 +65,18 @@ bool InterpreterCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
       return false;
     }
   }
+  else if ((Instr & FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_MASK) == FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_INST) { // Atomic memory op
+    if (FEXCore::ArchHelpers::Arm64::HandleAtomicMemOp(_mcontext, info, Instr)) {
+      // Skip this instruction now
+      _mcontext->pc += 4;
+      return true;
+    }
+    else {
+      uint8_t Op = (PC[0] >> 12) & 0xF;
+      LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x: PC: %p Instruction: 0x%08x\n", Op, PC, PC[0]);
+      return false;
+    }
+  }
 #endif
   return false;
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp

@@ -685,7 +685,18 @@ bool JITCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
       return false;
     }
   }
-
+  else if ((Instr & FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_MASK) == FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_INST) { // Atomic memory op
+    if (FEXCore::ArchHelpers::Arm64::HandleAtomicMemOp(_mcontext, info, Instr)) {
+      // Skip this instruction now
+      _mcontext->pc += 4;
+      return true;
+    }
+    else {
+      uint8_t Op = (PC[0] >> 12) & 0xF;
+      LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x: PC: %p Instruction: 0x%08x\n", Op, PC, PC[0]);
+      return false;
+    }
+  }
   else {
     LogMan::Msg::E("Unhandled JIT SIGBUS: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
     return false;

unittests/ASM/Disabled_Tests

@@ -34,3 +34,32 @@ Test_TwoByte/0F_B0_7.asm
 Test_Secondary/09_XX_01_7.asm
 Test_Secondary/09_XX_01_8.asm
 Test_Secondary/09_XX_01_9.asm
+
+# Doesn't support unaligned atomic memory ops on armv8.0
+Test_Primary/Primary_01_Atomic16.asm
+Test_Primary/Primary_01_Atomic32.asm
+Test_Primary/Primary_01_Atomic64.asm
+Test_Primary/Primary_09_Atomic16.asm
+Test_Primary/Primary_09_Atomic32.asm
+Test_Primary/Primary_09_Atomic64.asm
+Test_Primary/Primary_23_Atomic16.asm
+Test_Primary/Primary_23_Atomic32.asm
+Test_Primary/Primary_23_Atomic64.asm
+Test_Primary/Primary_29_Atomic16.asm
+Test_Primary/Primary_29_Atomic32.asm
+Test_Primary/Primary_29_Atomic64.asm
+Test_Primary/Primary_31_Atomic16.asm
+Test_Primary/Primary_31_Atomic32.asm
+Test_Primary/Primary_31_Atomic64.asm
+Test_Primary/Primary_87_Atomic16.asm
+Test_Primary/Primary_87_Atomic32.asm
+Test_Primary/Primary_87_Atomic64.asm
+Test_Primary/Primary_FF_0_Atomic16.asm
+Test_Primary/Primary_FF_0_Atomic32.asm
+Test_Primary/Primary_FF_0_Atomic64.asm
+Test_Primary/Primary_FF_1_Atomic16.asm
+Test_Primary/Primary_FF_1_Atomic32.asm
+Test_Primary/Primary_FF_1_Atomic64.asm
+Test_TwoByte/0F_C0_Atomic16.asm
+Test_TwoByte/0F_C0_Atomic32.asm
+Test_TwoByte/0F_C0_Atomic64.asm

unittests/ASM/Primary/Primary_01_Atomic16.asm

@@ -0,0 +1,52 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4242434446464848",
+    "RBX": "0x4242434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4242434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 1 byte offset within 4byte boundary
+lock add word [r15 + 8 * 0 + 1], ax
+
+; Test 3 byte offset across 4byte boundary
+lock add word [r15 + 8 * 0 + 3], ax
+
+; Test 7 byte offset across 8byte boundary
+lock add word [r15 + 8 * 0 + 7], ax
+
+; Test 15 byte offset across 16byte boundary
+lock add word [r15 + 8 * 0 + 15], ax
+
+; Test 63 byte offset across cacheline boundary
+lock add word [r15 + 8 * 0 + 63], ax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_01_Atomic32.asm

@@ -0,0 +1,49 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4242434446464748",
+    "RBX": "0x4242434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4242434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 3 byte offset across 4byte boundary
+lock add dword [r15 + 8 * 0 + 3], eax
+
+; Test 7 byte offset across 8byte boundary
+lock add dword [r15 + 8 * 0 + 7], eax
+
+; Test 15 byte offset across 16byte boundary
+lock add dword [r15 + 8 * 0 + 15], eax
+
+; Test 63 byte offset across cacheline boundary
+lock add dword [r15 + 8 * 0 + 63], eax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_01_Atomic64.asm

@@ -0,0 +1,46 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4242434445464748",
+    "RBX": "0x4242434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4242434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 7 byte offset across 8byte boundary
+lock add qword [r15 + 8 * 0 + 7], rax
+
+; Test 15 byte offset across 16byte boundary
+lock add qword [r15 + 8 * 0 + 15], rax
+
+; Test 63 byte offset across cacheline boundary
+lock add qword [r15 + 8 * 0 + 63], rax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_09_Atomic16.asm

@@ -0,0 +1,52 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4142434445464748",
+    "RBX": "0x4142434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4142434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 1 byte offset within 4byte boundary
+lock or word [r15 + 8 * 0 + 1], ax
+
+; Test 3 byte offset across 4byte boundary
+lock or word [r15 + 8 * 0 + 3], ax
+
+; Test 7 byte offset across 8byte boundary
+lock or word [r15 + 8 * 0 + 7], ax
+
+; Test 15 byte offset across 16byte boundary
+lock or word [r15 + 8 * 0 + 15], ax
+
+; Test 63 byte offset across cacheline boundary
+lock or word [r15 + 8 * 0 + 63], ax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_09_Atomic32.asm

@@ -0,0 +1,49 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4142434445464748",
+    "RBX": "0x4142434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4142434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 3 byte offset across 4byte boundary
+lock or dword [r15 + 8 * 0 + 3], eax
+
+; Test 7 byte offset across 8byte boundary
+lock or dword [r15 + 8 * 0 + 7], eax
+
+; Test 15 byte offset across 16byte boundary
+lock or dword [r15 + 8 * 0 + 15], eax
+
+; Test 63 byte offset across cacheline boundary
+lock or dword [r15 + 8 * 0 + 63], eax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_09_Atomic64.asm

@@ -0,0 +1,46 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4142434445464748",
+    "RBX": "0x4142434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4142434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 7 byte offset across 8byte boundary
+lock or qword [r15 + 8 * 0 + 7], rax
+
+; Test 15 byte offset across 16byte boundary
+lock or qword [r15 + 8 * 0 + 15], rax
+
+; Test 63 byte offset across cacheline boundary
+lock or qword [r15 + 8 * 0 + 63], rax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_23_Atomic16.asm

@@ -0,0 +1,52 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x0142430001000148",
+    "RBX": "0x0142434445464700",
+    "RCX": "0x4142434445464700",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x0142434445464748",
+    "RDI": "0x4142434445464700"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 1 byte offset within 4byte boundary
+lock and word [r15 + 8 * 0 + 1], ax
+
+; Test 3 byte offset across 4byte boundary
+lock and word [r15 + 8 * 0 + 3], ax
+
+; Test 7 byte offset across 8byte boundary
+lock and word [r15 + 8 * 0 + 7], ax
+
+; Test 15 byte offset across 16byte boundary
+lock and word [r15 + 8 * 0 + 15], ax
+
+; Test 63 byte offset across cacheline boundary
+lock and word [r15 + 8 * 0 + 63], ax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_23_Atomic32.asm

@@ -0,0 +1,49 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x0100000001464748",
+    "RBX": "0x0142434445000000",
+    "RCX": "0x4142434445000000",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x0142434445464748",
+    "RDI": "0x4142434445000000"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 3 byte offset across 4byte boundary
+lock and dword [r15 + 8 * 0 + 3], eax
+
+; Test 7 byte offset across 8byte boundary
+lock and dword [r15 + 8 * 0 + 7], eax
+
+; Test 15 byte offset across 16byte boundary
+lock and dword [r15 + 8 * 0 + 15], eax
+
+; Test 63 byte offset across cacheline boundary
+lock and dword [r15 + 8 * 0 + 63], eax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_23_Atomic64.asm

@@ -0,0 +1,46 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x0142434445464748",
+    "RBX": "0x0100000000000000",
+    "RCX": "0x4100000000000000",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x0142434445464748",
+    "RDI": "0x4100000000000000"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 7 byte offset across 8byte boundary
+lock and qword [r15 + 8 * 0 + 7], rax
+
+; Test 15 byte offset across 16byte boundary
+lock and qword [r15 + 8 * 0 + 15], rax
+
+; Test 63 byte offset across cacheline boundary
+lock and qword [r15 + 8 * 0 + 63], rax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_29_Atomic16.asm

@@ -0,0 +1,52 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4042434444464648",
+    "RBX": "0x4042434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4042434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 1 byte offset within 4byte boundary
+lock sub word [r15 + 8 * 0 + 1], ax
+
+; Test 3 byte offset across 4byte boundary
+lock sub word [r15 + 8 * 0 + 3], ax
+
+; Test 7 byte offset across 8byte boundary
+lock sub word [r15 + 8 * 0 + 7], ax
+
+; Test 15 byte offset across 16byte boundary
+lock sub word [r15 + 8 * 0 + 15], ax
+
+; Test 63 byte offset across cacheline boundary
+lock sub word [r15 + 8 * 0 + 63], ax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_29_Atomic32.asm

@@ -0,0 +1,49 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4042434444464748",
+    "RBX": "0x4042434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4042434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 3 byte offset across 4byte boundary
+lock sub dword [r15 + 8 * 0 + 3], eax
+
+; Test 7 byte offset across 8byte boundary
+lock sub dword [r15 + 8 * 0 + 7], eax
+
+; Test 15 byte offset across 16byte boundary
+lock sub dword [r15 + 8 * 0 + 15], eax
+
+; Test 63 byte offset across cacheline boundary
+lock sub dword [r15 + 8 * 0 + 63], eax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_29_Atomic64.asm

@@ -0,0 +1,46 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4042434445464748",
+    "RBX": "0x4042434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4042434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 7 byte offset across 8byte boundary
+lock sub qword [r15 + 8 * 0 + 7], rax
+
+; Test 15 byte offset across 16byte boundary
+lock sub qword [r15 + 8 * 0 + 15], rax
+
+; Test 63 byte offset across cacheline boundary
+lock sub qword [r15 + 8 * 0 + 63], rax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_31_Atomic16.asm

@@ -0,0 +1,52 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4042434444464648",
+    "RBX": "0x4042434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4042434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 1 byte offset within 4byte boundary
+lock xor word [r15 + 8 * 0 + 1], ax
+
+; Test 3 byte offset across 4byte boundary
+lock xor word [r15 + 8 * 0 + 3], ax
+
+; Test 7 byte offset across 8byte boundary
+lock xor word [r15 + 8 * 0 + 7], ax
+
+; Test 15 byte offset across 16byte boundary
+lock xor word [r15 + 8 * 0 + 15], ax
+
+; Test 63 byte offset across cacheline boundary
+lock xor word [r15 + 8 * 0 + 63], ax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_31_Atomic32.asm

@@ -0,0 +1,49 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4042434444464748",
+    "RBX": "0x4042434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4042434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 3 byte offset across 4byte boundary
+lock xor dword [r15 + 8 * 0 + 3], eax
+
+; Test 7 byte offset across 8byte boundary
+lock xor dword [r15 + 8 * 0 + 7], eax
+
+; Test 15 byte offset across 16byte boundary
+lock xor dword [r15 + 8 * 0 + 15], eax
+
+; Test 63 byte offset across cacheline boundary
+lock xor dword [r15 + 8 * 0 + 63], eax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_31_Atomic64.asm

@@ -0,0 +1,46 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4042434445464748",
+    "RBX": "0x4042434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4042434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 7 byte offset across 8byte boundary
+lock xor qword [r15 + 8 * 0 + 7], rax
+
+; Test 15 byte offset across 16byte boundary
+lock xor qword [r15 + 8 * 0 + 15], rax
+
+; Test 63 byte offset across cacheline boundary
+lock xor qword [r15 + 8 * 0 + 63], rax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_87_Atomic16.asm

@@ -0,0 +1,65 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x0142430001000148",
+    "RBX": "0x0142434445464700",
+    "RCX": "0x4142434445464700",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x0142434445464748",
+    "RDI": "0x4142434445464700",
+    "R14": "0x0000000000004647",
+    "R13": "0x0000000000004445",
+    "R12": "0x0000000000004841",
+    "R11": "0x0000000000004841",
+    "R10": "0x0000000000004841"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+; Test 1 byte offset within 4byte boundary
+mov rax, 1
+lock xchg word [r15 + 8 * 0 + 1], ax
+mov r14, rax
+
+; Test 3 byte offset across 4byte boundary
+mov rax, 1
+lock xchg word [r15 + 8 * 0 + 3], ax
+mov r13, rax
+
+; Test 7 byte offset across 8byte boundary
+mov rax, 1
+lock xchg word [r15 + 8 * 0 + 7], ax
+mov r12, rax
+
+; Test 15 byte offset across 16byte boundary
+mov rax, 1
+lock xchg word [r15 + 8 * 0 + 15], ax
+mov r11, rax
+
+; Test 63 byte offset across cacheline boundary
+mov rax, 1
+lock xchg word [r15 + 8 * 0 + 63], ax
+mov r10, rax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_87_Atomic32.asm

@@ -0,0 +1,59 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x0100000001464748",
+    "RBX": "0x0142434445000000",
+    "RCX": "0x4142434445000000",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x0142434445464748",
+    "RDI": "0x4142434445000000",
+    "R13": "0x0000000042434445",
+    "R12": "0x0000000046474841",
+    "R11": "0x0000000046474841",
+    "R10": "0x0000000046474841"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+; Test 3 byte offset across 4byte boundary
+mov rax, 1
+lock xchg dword [r15 + 8 * 0 + 3], eax
+mov r13, rax
+
+; Test 7 byte offset across 8byte boundary
+mov rax, 1
+lock xchg dword [r15 + 8 * 0 + 7], eax
+mov r12, rax
+
+; Test 15 byte offset across 16byte boundary
+mov rax, 1
+lock xchg dword [r15 + 8 * 0 + 15], eax
+mov r11, rax
+
+; Test 63 byte offset across cacheline boundary
+mov rax, 1
+lock xchg dword [r15 + 8 * 0 + 63], eax
+mov r10, rax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_87_Atomic64.asm

@@ -0,0 +1,53 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x0142434445464748",
+    "RBX": "0x0100000000000000",
+    "RCX": "0x4100000000000000",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x0142434445464748",
+    "RDI": "0x4100000000000000",
+    "R13": "0x4243444546474841",
+    "R12": "0x4243444546474841",
+    "R11": "0x4243444546474841"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+; Test 7 byte offset across 8byte boundary
+mov rax, 1
+lock xchg qword [r15 + 8 * 0 + 7], rax
+mov r13, rax
+
+; Test 15 byte offset across 16byte boundary
+mov rax, 1
+lock xchg qword [r15 + 8 * 0 + 15], rax
+mov r12, rax
+
+; Test 63 byte offset across cacheline boundary
+mov rax, 1
+lock xchg qword [r15 + 8 * 0 + 63], rax
+mov r11, rax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_FF_0_Atomic16.asm

@@ -0,0 +1,50 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4242434446464848",
+    "RBX": "0x4242434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4242434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+; Test 1 byte offset within 4byte boundary
+lock inc word [r15 + 8 * 0 + 1]
+
+; Test 3 byte offset across 4byte boundary
+lock inc word [r15 + 8 * 0 + 3]
+
+; Test 7 byte offset across 8byte boundary
+lock inc word [r15 + 8 * 0 + 7]
+
+; Test 15 byte offset across 16byte boundary
+lock inc word [r15 + 8 * 0 + 15]
+
+; Test 63 byte offset across cacheline boundary
+lock inc word [r15 + 8 * 0 + 63]
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_FF_0_Atomic32.asm

@@ -0,0 +1,49 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4242434446464748",
+    "RBX": "0x4242434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4242434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 3 byte offset across 4byte boundary
+lock inc dword [r15 + 8 * 0 + 3]
+
+; Test 7 byte offset across 8byte boundary
+lock inc dword [r15 + 8 * 0 + 7]
+
+; Test 15 byte offset across 16byte boundary
+lock inc dword [r15 + 8 * 0 + 15]
+
+; Test 63 byte offset across cacheline boundary
+lock inc dword [r15 + 8 * 0 + 63]
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_FF_0_Atomic64.asm

@@ -0,0 +1,46 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4242434445464748",
+    "RBX": "0x4242434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4242434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 7 byte offset across 8byte boundary
+lock inc qword [r15 + 8 * 0 + 7]
+
+; Test 15 byte offset across 16byte boundary
+lock inc qword [r15 + 8 * 0 + 15]
+
+; Test 63 byte offset across cacheline boundary
+lock inc qword [r15 + 8 * 0 + 63]
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_FF_1_Atomic16.asm

@@ -0,0 +1,52 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4042434444464648",
+    "RBX": "0x4042434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4042434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 1 byte offset within 4byte boundary
+lock dec word [r15 + 8 * 0 + 1]
+
+; Test 3 byte offset across 4byte boundary
+lock dec word [r15 + 8 * 0 + 3]
+
+; Test 7 byte offset across 8byte boundary
+lock dec word [r15 + 8 * 0 + 7]
+
+; Test 15 byte offset across 16byte boundary
+lock dec word [r15 + 8 * 0 + 15]
+
+; Test 63 byte offset across cacheline boundary
+lock dec word [r15 + 8 * 0 + 63]
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_FF_1_Atomic32.asm

@@ -0,0 +1,49 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4042434444464748",
+    "RBX": "0x4042434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4042434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 3 byte offset across 4byte boundary
+lock dec dword [r15 + 8 * 0 + 3]
+
+; Test 7 byte offset across 8byte boundary
+lock dec dword [r15 + 8 * 0 + 7]
+
+; Test 15 byte offset across 16byte boundary
+lock dec dword [r15 + 8 * 0 + 15]
+
+; Test 63 byte offset across cacheline boundary
+lock dec dword [r15 + 8 * 0 + 63]
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/Primary/Primary_FF_1_Atomic64.asm

@@ -0,0 +1,46 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4042434445464748",
+    "RBX": "0x4042434445464748",
+    "RCX": "0x4142434445464748",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x4042434445464748",
+    "RDI": "0x4142434445464748"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 7 byte offset across 8byte boundary
+lock dec qword [r15 + 8 * 0 + 7]
+
+; Test 15 byte offset across 16byte boundary
+lock dec qword [r15 + 8 * 0 + 15]
+
+; Test 63 byte offset across cacheline boundary
+lock dec qword [r15 + 8 * 0 + 63]
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/TwoByte/0F_C0_Atomic16.asm

@@ -0,0 +1,52 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x8642438a8c464848",
+    "RBX": "0x824243444546478c",
+    "RCX": "0x4142434445464790",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x8242434445464748",
+    "RDI": "0x4142434445464790"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 1 byte offset within 4byte boundary
+lock xadd word [r15 + 8 * 0 + 1], ax
+
+; Test 3 byte offset across 4byte boundary
+lock xadd word [r15 + 8 * 0 + 3], ax
+
+; Test 7 byte offset across 8byte boundary
+lock xadd word [r15 + 8 * 0 + 7], ax
+
+; Test 15 byte offset across 16byte boundary
+lock xadd word [r15 + 8 * 0 + 15], ax
+
+; Test 63 byte offset across cacheline boundary
+lock xadd word [r15 + 8 * 0 + 63], ax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/TwoByte/0F_C0_Atomic32.asm

@@ -0,0 +1,49 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x8642434446464748",
+    "RBX": "0x8242434445888a8c",
+    "RCX": "0x41424344458c8e90",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x8242434445464748",
+    "RDI": "0x41424344458c8e90"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 3 byte offset across 4byte boundary
+lock xadd dword [r15 + 8 * 0 + 3], eax
+
+; Test 7 byte offset across 8byte boundary
+lock xadd dword [r15 + 8 * 0 + 7], eax
+
+; Test 15 byte offset across 16byte boundary
+lock xadd dword [r15 + 8 * 0 + 15], eax
+
+; Test 63 byte offset across cacheline boundary
+lock xadd dword [r15 + 8 * 0 + 63], eax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt

unittests/ASM/TwoByte/0F_C0_Atomic64.asm

@@ -0,0 +1,46 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x4242434445464748",
+    "RBX": "0x8242434445464748",
+    "RCX": "0x418486888a8c8e90",
+    "RDX": "0x4142434445464748",
+    "RSI": "0x8242434445464748",
+    "RDI": "0x418486888a8c8e90"
+  }
+}
+%endif
+
+mov r15, 0xe0000000
+
+mov rax, 0x4142434445464748
+mov [r15 + 8 * 0], rax
+mov [r15 + 8 * 1], rax
+mov [r15 + 8 * 2], rax
+mov [r15 + 8 * 3], rax
+mov [r15 + 8 * 4], rax
+mov [r15 + 8 * 5], rax
+mov [r15 + 8 * 6], rax
+mov [r15 + 8 * 7], rax
+mov [r15 + 8 * 8], rax
+mov [r15 + 8 * 9], rax
+
+mov rax, 1
+
+; Test 7 byte offset across 8byte boundary
+lock xadd qword [r15 + 8 * 0 + 7], rax
+
+; Test 15 byte offset across 16byte boundary
+lock xadd qword [r15 + 8 * 0 + 15], rax
+
+; Test 63 byte offset across cacheline boundary
+lock xadd qword [r15 + 8 * 0 + 63], rax
+
+mov rax, qword [r15 + 8 * 0]
+mov rbx, qword [r15 + 8 * 1]
+mov rcx, qword [r15 + 8 * 2]
+mov rdx, qword [r15 + 8 * 3]
+mov rsi, qword [r15 + 8 * 7]
+mov rdi, qword [r15 + 8 * 8]
+
+hlt