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General: Make use of the <bit> header where applicable

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Since C++20, a bunch of bit manipulation functions finally have a common
interface, so lets make use of those
This commit is contained in:
Lioncash committed 2021-06-07 08:16:51 -04:00
1 parent 2b9029623e
commit 18e0f2636f
4 files changed
+21 -45
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External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp
Vendored
+2 -1
View File
@@ -5,6 +5,7 @@
#include "Interface/Context/Context.h"
#include <FEXCore/Core/X86Enums.h>
#include <bit>
#include <cmath>
#include "aarch64/assembler-aarch64.h"
@@ -103,7 +104,7 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::
ldr(x0, &l_PagePtr);
// Mask the address by the virtual address size so we can check for aliases
if (__builtin_popcountl(VirtualMemorySize) == 1) {
if (std::popcount(VirtualMemorySize) == 1) {
and_(x3, RipReg, Thread->LookupCache->GetVirtualMemorySize() - 1);
}
else {
External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp
Vendored
+15 -41
View File
@@ -1867,7 +1867,7 @@ void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, uin
case IR::OP_POPCOUNT: {
auto Op = IROp->C<IR::IROp_Popcount>();
uint64_t Src = *GetSrc<uint64_t*>(SSAData, Op->Header.Args[0]);
GD = __builtin_popcountl(Src);
GD = std::popcount(Src);
break;
}
case IR::OP_FINDLSB: {
@@ -1880,10 +1880,10 @@ void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, uin
case IR::OP_FINDMSB: {
auto Op = IROp->C<IR::IROp_FindMSB>();
switch (OpSize) {
case 1: GD = ((24 + OpSize * 8) - __builtin_clz(*GetSrc<uint8_t*>(SSAData, Op->Header.Args[0]))) - 1; break;
case 2: GD = ((16 + OpSize * 8) - __builtin_clz(*GetSrc<uint16_t*>(SSAData, Op->Header.Args[0]))) - 1; break;
case 4: GD = (OpSize * 8 - __builtin_clz(*GetSrc<uint32_t*>(SSAData, Op->Header.Args[0]))) - 1; break;
case 8: GD = (OpSize * 8 - __builtin_clzll(*GetSrc<uint64_t*>(SSAData, Op->Header.Args[0]))) - 1; break;
case 1: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint8_t*>(SSAData, Op->Header.Args[0]))) - 1; break;
case 2: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint16_t*>(SSAData, Op->Header.Args[0]))) - 1; break;
case 4: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint32_t*>(SSAData, Op->Header.Args[0]))) - 1; break;
case 8: GD = (OpSize * 8 - std::countl_zero(*GetSrc<uint64_t*>(SSAData, Op->Header.Args[0]))) - 1; break;
default: LOGMAN_MSG_A("Unknown REV size: %d", OpSize); break;
}
break;
@@ -1903,34 +1903,22 @@ void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, uin
switch (OpSize) {
case 1: {
auto Src = *GetSrc<uint8_t*>(SSAData, Op->Header.Args[0]);
if (Src)
GD = __builtin_ctz(Src);
else
GD = sizeof(Src) * 8;
GD = std::countr_zero(Src);
break;
}
case 2: {
auto Src = *GetSrc<uint16_t*>(SSAData, Op->Header.Args[0]);
if (Src)
GD = __builtin_ctz(Src);
else
GD = sizeof(Src) * 8;
GD = std::countr_zero(Src);
break;
}
case 4: {
auto Src = *GetSrc<uint32_t*>(SSAData, Op->Header.Args[0]);
if (Src)
GD = __builtin_ctz(Src);
else
GD = sizeof(Src) * 8;
GD = std::countr_zero(Src);
break;
}
case 8: {
auto Src = *GetSrc<uint64_t*>(SSAData, Op->Header.Args[0]);
if (Src)
GD = __builtin_ctzll(Src);
else
GD = sizeof(Src) * 8;
GD = std::countr_zero(Src);
break;
}
default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
@@ -1941,37 +1929,23 @@ void InterpreterOps::InterpretIR(FEXCore::Core::InternalThreadState *Thread, uin
auto Op = IROp->C<IR::IROp_CountLeadingZeroes>();
switch (OpSize) {
case 1: {
uint32_t Src = *GetSrc<uint8_t*>(SSAData, Op->Header.Args[0]);
Src <<= 24;
if (Src)
GD = __builtin_clz(Src);
else
GD = 8;
auto Src = *GetSrc<uint8_t*>(SSAData, Op->Header.Args[0]);
GD = std::countl_zero(Src);
break;
}
case 2: {
uint32_t Src = *GetSrc<uint16_t*>(SSAData, Op->Header.Args[0]);
Src <<= 16;
if (Src)
GD = __builtin_clz(Src);
else
GD = 16;
auto Src = *GetSrc<uint16_t*>(SSAData, Op->Header.Args[0]);
GD = std::countl_zero(Src);
break;
}
case 4: {
auto Src = *GetSrc<uint32_t*>(SSAData, Op->Header.Args[0]);
if (Src)
GD = __builtin_clz(Src);
else
GD = sizeof(Src) * 8;
GD = std::countl_zero(Src);
break;
}
case 8: {
auto Src = *GetSrc<uint64_t*>(SSAData, Op->Header.Args[0]);
if (Src)
GD = __builtin_clzll(Src);
else
GD = sizeof(Src) * 8;
GD = std::countl_zero(Src);
break;
}
default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Vendored
+2 -1
View File
@@ -10,6 +10,7 @@ $end_info$
#include "Interface/HLE/Thunks/Thunks.h"
#include <FEXCore/Core/CoreState.h>
#include <bit>
#include <climits>
#include <cstddef>
#include <cstdint>
@@ -4266,7 +4267,7 @@ void OpDispatchBuilder::SHUFOp(OpcodeArgs) {
// [63:0] = Src1[Selection]
// [127:64] = Src2[Selection]
uint8_t SelectionMask = NumElements - 1;
uint8_t ShiftAmount = __builtin_popcount(SelectionMask);
uint8_t ShiftAmount = std::popcount(SelectionMask);
for (uint8_t Element = 0; Element < NumElements; ++Element) {
Dest = _VInsElement(Size, ElementSize, Element, Shuffle & SelectionMask, Dest, Srcs[Element]);
Shuffle >>= ShiftAmount;
External/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp
Vendored
+2 -2
View File
@@ -735,9 +735,9 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
uint64_t NewConstant = (Constant1 * Constant2) & getMask(Op);
IREmit->ReplaceWithConstant(CodeNode, NewConstant);
Changed = true;
} else if (IREmit->IsValueConstant(Op->Header.Args[1], &Constant2) && __builtin_popcountl(Constant2) == 1) {
} else if (IREmit->IsValueConstant(Op->Header.Args[1], &Constant2) && std::popcount(Constant2) == 1) {
if (IROp->Size == 4 || IROp->Size == 8) {
uint64_t amt = __builtin_ctzl(Constant2);
uint64_t amt = std::countr_zero(Constant2);
IREmit->SetWriteCursor(CodeNode);
auto shift = IREmit->_Lshl(CurrentIR.GetNode(Op->Header.Args[0]), IREmit->_Constant(amt));
shift.first->Header.Size = IROp->Size; // force Lshl to be the same size as the original Mul