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Adds LDAXP and STLXP backpatch handlers
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849b83bd02
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@@ -12,6 +12,12 @@ namespace FEXCore::ArchHelpers::Arm64 {
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constexpr uint32_t ATOMIC_MEM_MASK = 0x3B200C00;
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constexpr uint32_t ATOMIC_MEM_INST = 0x38200000;
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constexpr uint32_t LDAXP_MASK = 0xBF'FF'80'00;
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constexpr uint32_t LDAXP_INST = 0x88'7F'80'00;
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constexpr uint32_t STLXP_MASK = 0xBF'E0'80'00;
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constexpr uint32_t STLXP_INST = 0x88'20'80'00;
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// Load ops are 4 bits
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// Acquire and release bits are independent on the instruction
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constexpr uint32_t ATOMIC_ADD_OP = 0b0000;
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@@ -359,6 +359,34 @@ bool Arm64JITCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
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// Back up one instruction and have another go
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ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) - 4);
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}
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else if ((Instr & FEXCore::ArchHelpers::Arm64::LDAXP_MASK) == FEXCore::ArchHelpers::Arm64::LDAXP_INST) { // LDAXP
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uint32_t DataReg2 = (Instr >> 10) & 0x1F;
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// Convert to LDP
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uint32_t LDP = 0b0010'1001'0100'0000'0000'0000'0000'0000;
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LDP |= Size << 31;
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LDP |= DataReg2 << 10;
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LDP |= AddrReg << 5;
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LDP |= DataReg;
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PC[-1] = DMB;
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PC[0] = LDP;
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PC[1] = DMB;
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// Back up one instruction and have another go
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ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) - 4);
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}
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else if ((Instr & FEXCore::ArchHelpers::Arm64::STLXP_MASK) == FEXCore::ArchHelpers::Arm64::STLXP_INST) { // STLXP
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uint32_t DataReg2 = (Instr >> 10) & 0x1F;
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// Convert to STP
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uint32_t STP = 0b0010'1001'0000'0000'0000'0000'0000'0000;
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STP |= Size << 31;
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STP |= DataReg2 << 10;
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STP |= AddrReg << 5;
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STP |= DataReg;
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PC[-1] = DMB;
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PC[0] = STP;
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PC[1] = DMB;
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// Back up one instruction and have another go
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ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) - 4);
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}
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else if ((Instr & FEXCore::ArchHelpers::Arm64::CASPAL_MASK) == FEXCore::ArchHelpers::Arm64::CASPAL_INST) { // CASPAL
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if (FEXCore::ArchHelpers::Arm64::HandleCASPAL(ucontext, info, Instr)) {
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// Skip this instruction now
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