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https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 21:00:17 +02:00
Remove old and unused HostCore
The thing we are actually using is Source/CommonCore/HostFactory.cpp
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Scott Mansell committed
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0bdddedfe6
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208fa0d1fc
2 files changed
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@@ -1,267 +0,0 @@
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#include "Common/MathUtils.h"
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#include "Core/CPU/CPUBackend.h"
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#include "Core/CPU/CPUCore.h"
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#include "Core/CPU/DebugData.h"
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#include "Core/CPU/IR.h"
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#include "Core/CPU/IntrusiveIRList.h"
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#include "Core/CPU/HostCore/HostCore.h"
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#include <FEXCore/Utils/LogManager.h>
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#include <ucontext.h>
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#include <cassert>
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#include <iostream>
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#include <sys/mman.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/wait.h>
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#include <sys/ptrace.h>
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#include <errno.h>
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#include <sys/user.h>
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#include <stdint.h>
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namespace FEX::CPU {
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class HostCore final : public CPUBackend {
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public:
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explicit HostCore(FEX::ThreadState *Thread);
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~HostCore() override = default;
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std::string GetName() override { return "Host Stepper"; }
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void* CompileCode(FEX::IR::IntrusiveIRList const *ir, FEX::CPU::DebugData *DebugData) override;
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void *MapRegion(void *HostPtr, uint64_t GuestPtr, uint64_t Size) override {
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// Map locally to unprotected
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printf("Mapping Guest Ptr: 0x%lx\n", GuestPtr);
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void *Mem = LocalMemoryMapper.MapRegionFlags(GuestPtr, Size, PROT_READ | PROT_WRITE | PROT_EXEC);
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memset(Mem, 0xCC, Size);
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return HostPtr;
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}
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void ExecuteCode(FEX::ThreadState *Thread);
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void SignalHandler(int sig, siginfo_t *info, void *RawContext);
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bool NeedsOpDispatch() override { return false; }
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private:
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void HandleSyscall();
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void ExecutionThreadFunction();
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void InstallSignalHandler();
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FEX::ThreadState *ThreadState;
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std::thread ExecutionThread;
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Memmap LocalMemoryMapper{};
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pid_t ChildPid;
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struct sigaction OldSigAction_SEGV;
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struct sigaction OldSigAction_TRAP;
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int PipeFDs[2];
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std::atomic_bool ShouldStart{false};
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};
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static HostCore *GlobalCore;
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static void SigAction_SEGV(int sig, siginfo_t* info, void* RawContext) {
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GlobalCore->SignalHandler(sig, info, RawContext);
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}
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HostCore::HostCore(FEX::ThreadState *Thread)
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: ThreadState {Thread} {
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GlobalCore = this;
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LocalMemoryMapper.AllocateSHMRegion(1ULL << 36);
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ExecutionThread = std::thread(&HostCore::ExecutionThreadFunction, this);
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}
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static void HostExecution(FEX::ThreadState *Thread) {
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HostCore *Core = reinterpret_cast<HostCore*>(Thread->CPUBackend.get());
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Core->ExecuteCode(Thread);
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}
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void HostCore::SignalHandler(int sig, siginfo_t *info, void *RawContext) {
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ucontext_t* Context = (ucontext_t*)RawContext;
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uint64_t HostToEmuRIP = (uint64_t)Context->uc_mcontext.gregs[REG_RIP] - LocalMemoryMapper.GetBaseOffset<uint64_t>(0);
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printf("We hecked up and faulted! %d Emu:0x%lx Host:0x%lx\n", sig, HostToEmuRIP, (uint64_t)Context->uc_mcontext.gregs[REG_RIP]);
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static uint64_t LastEMURip = ~0ULL;
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static uint64_t LastInstSize = 0;
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if (sig == SIGSEGV) {
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// RIP == Base instruction
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}
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else if (sig == SIGTRAP) {
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HostToEmuRIP -= 1; // 0xCC moves us ahead by one
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}
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uint8_t *LocalData = LocalMemoryMapper.GetPointer<uint8_t*>(HostToEmuRIP);
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uint8_t *ActualData = ThreadState->CPUCore->MemoryMapper->GetPointer<uint8_t*>(HostToEmuRIP);
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uint64_t TotalInstructionsLength {0};
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ThreadState->CPUCore->FrontendDecoder.DecodeInstructionsInBlock(ActualData, HostToEmuRIP);
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auto DecodedOps = ThreadState->CPUCore->FrontendDecoder.GetDecodedInsts();
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if (sig == SIGSEGV) {
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for (size_t i = 0; i < DecodedOps.second; ++i) {
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FEX::X86Tables::DecodedInst const* DecodedInfo {nullptr};
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DecodedInfo = &DecodedOps.first->at(i);
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auto CheckOp = [&](char const* Name, FEX::X86Tables::DecodedOperand const &Operand) {
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if (Operand.TypeNone.Type != FEX::X86Tables::DecodedOperand::TYPE_NONE &&
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Operand.TypeNone.Type != FEX::X86Tables::DecodedOperand::TYPE_LITERAL &&
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Operand.TypeNone.Type != FEX::X86Tables::DecodedOperand::TYPE_GPR) {
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printf("Operand type is %d\n", Operand.TypeNone.Type);
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const std::vector<unsigned> EmulatorToSystemContext = {
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offsetof(mcontext_t, gregs[REG_RAX]),
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offsetof(mcontext_t, gregs[REG_RBX]),
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offsetof(mcontext_t, gregs[REG_RCX]),
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offsetof(mcontext_t, gregs[REG_RDX]),
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offsetof(mcontext_t, gregs[REG_RSI]),
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offsetof(mcontext_t, gregs[REG_RDI]),
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offsetof(mcontext_t, gregs[REG_RBP]),
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offsetof(mcontext_t, gregs[REG_RSP]),
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offsetof(mcontext_t, gregs[REG_R8]),
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offsetof(mcontext_t, gregs[REG_R9]),
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offsetof(mcontext_t, gregs[REG_R10]),
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offsetof(mcontext_t, gregs[REG_R11]),
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offsetof(mcontext_t, gregs[REG_R12]),
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offsetof(mcontext_t, gregs[REG_R13]),
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offsetof(mcontext_t, gregs[REG_R14]),
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offsetof(mcontext_t, gregs[REG_R15]),
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};
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// Modify the registers to match the memory operands necessary.
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// This will propagate some addresses
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if (Operand.TypeNone.Type == FEX::X86Tables::DecodedOperand::TYPE_GPR_DIRECT) {
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uint64_t *GPR = (uint64_t*)((uintptr_t)&Context->uc_mcontext + EmulatorToSystemContext[Operand.TypeGPR.GPR]);
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uint64_t HostPointer = LocalMemoryMapper.GetPointer<uint64_t>(*GPR);
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printf("Changing host pointer from 0x%lx to %lx\n", *GPR, HostPointer);
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*GPR = HostPointer;
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}
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else {
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OldSigAction_SEGV.sa_sigaction(sig, info, RawContext);
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return;
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}
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}
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};
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printf("Insts: %ld\n", DecodedOps.second);
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CheckOp("Dest", DecodedInfo->Dest);
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CheckOp("Src1", DecodedInfo->Src1);
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CheckOp("Src2", DecodedInfo->Src2);
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// Reset RIP to the start of the instruction
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Context->uc_mcontext.gregs[REG_RIP] = (uint64_t)LocalData;
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return;
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}
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OldSigAction_SEGV.sa_sigaction(sig, info, RawContext);
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return;
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}
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else if (sig == SIGTRAP) {
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for (size_t i = 0; i < DecodedOps.second; ++i) {
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FEX::X86Tables::DecodedInst const* DecodedInfo {nullptr};
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DecodedInfo = &DecodedOps.first->at(i);
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TotalInstructionsLength += DecodedInfo->InstSize;
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}
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if (LastEMURip != ~0ULL) {
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uint8_t *PreviousLocalData = LocalMemoryMapper.GetPointer<uint8_t*>(LastEMURip);
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memset(PreviousLocalData, 0xCC, LastInstSize);
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}
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LastInstSize = TotalInstructionsLength;
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printf("\tHit an instruction of length %ld 0x%lx 0x%lx 0x%lx\n", TotalInstructionsLength, (uint64_t)Context->uc_mcontext.gregs[REG_RIP], (uint64_t)LocalData, (uint64_t)ActualData);
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memcpy(LocalData, ActualData, TotalInstructionsLength);
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printf("\tData Source:");
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for (uint64_t i = 0; i < TotalInstructionsLength; ++i) {
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printf("%02x ", ActualData[i]);
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}
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printf("\n");
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// Reset RIP to the start of the instruction
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Context->uc_mcontext.gregs[REG_RIP] = (uint64_t)LocalData;
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}
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}
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void HostCore::InstallSignalHandler() {
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struct sigaction sa;
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sa.sa_handler = nullptr;
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sa.sa_sigaction = &SigAction_SEGV;
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sa.sa_flags = SA_SIGINFO;
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sigemptyset(&sa.sa_mask);
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// We use sigsegv to capture invalid memory accesses
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// We then patch the GPR state of that instruction to point to the correct location
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sigaction(SIGSEGV, &sa, &OldSigAction_SEGV);
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// We use trapping to determine when we've stepped to a new instruction
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sigaction(SIGTRAP, &sa, &OldSigAction_TRAP);
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}
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void HostCore::ExecutionThreadFunction() {
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printf("Host Core created\n");
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if (pipe(PipeFDs) == -1) {
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LogMan::Msg::A("Couldn't pipe");
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return;
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}
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ChildPid = fork();
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if (ChildPid == 0) {
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// Child
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// Set that we want to be traced
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if (ptrace(PTRACE_TRACEME, 0, 0, 0)) {
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LogMan::Msg::A("Couldn't start trace");
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}
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raise(SIGSTOP);
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InstallSignalHandler();
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close(PipeFDs[1]);
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using Ptr = void (*)();
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read(PipeFDs[0], &ThreadState->CPUState, sizeof(FEX::X86State::State));
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printf("Child is running! 0x%lx\n", ThreadState->CPUState.rip);
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Ptr Loc = LocalMemoryMapper.GetPointer<Ptr>(ThreadState->CPUState.rip);
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Loc();
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printf("Oh Snap. We returned in the child\n");
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}
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else {
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// Parent
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// Parent will be the ptrace control thread
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int status;
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close(PipeFDs[0]);
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waitpid(ChildPid, &status, 0);
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if (WIFSTOPPED(status) && WSTOPSIG(status) == 19) {
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// Attach to child
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ptrace(PTRACE_ATTACH, ChildPid, 0, 0);
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ptrace(PTRACE_CONT, ChildPid, 0, 0);
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}
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while (!ShouldStart.load());
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printf("Telling child to go!\n");
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write(PipeFDs[1], &ThreadState->CPUState, sizeof(FEX::X86State::State));
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while (1) {
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ShouldStart.store(false);
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waitpid(ChildPid, &status, 0);
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if (WIFEXITED(status)) {
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return;
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}
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if (WIFSTOPPED(status) && WSTOPSIG(status) == 5) {
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ptrace(PTRACE_CONT, ChildPid, 0, 5);
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}
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if (WIFSTOPPED(status) && WSTOPSIG(status) == 11) {
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ptrace(PTRACE_DETACH, ChildPid, 0, 11);
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break;
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}
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}
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}
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}
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void* HostCore::CompileCode([[maybe_unused]] FEX::IR::IntrusiveIRList const* ir, FEX::CPU::DebugData *DebugData) {
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printf("Attempting to compile: 0x%lx\n", ThreadState->CPUState.rip);
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return reinterpret_cast<void*>(HostExecution);
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}
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void HostCore::ExecuteCode(FEX::ThreadState *Thread) {
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ShouldStart = true;
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while(1);
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}
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FEX::CPU::CPUBackend *CreateHostCore(FEX::ThreadState *Thread) {
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return new HostCore(Thread);
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}
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}
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@@ -1,10 +0,0 @@
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#pragma once
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namespace FEX {
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struct ThreadState;
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}
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namespace FEX::CPU {
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class CPUBackend;
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FEX::CPU::CPUBackend *CreateHostCore(FEX::ThreadState *Thread);
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}
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