Docs: Update for release FEX-2108

AArch64: Workaround static-pie crashing

.github/workflows/ccpp.yml

@@ -13,18 +13,22 @@ env:
   BUILD_TYPE: Release
   CC: clang
   CXX: clang++
+  FEX_FORCE32BITALLOCATOR: 1
 
 jobs:
   build:
     runs-on: ${{ matrix.arch }}
     strategy:
       matrix:
-        arch: [[self-hosted, x64], [self-hosted, ARMv8.0], [self-hosted, ARMv8.2]]
+        arch: [[self-hosted, x64], [self-hosted, ARMv8.0], [self-hosted, ARMv8.2], [self-hosted, ARMv8.4]]
       fail-fast: false
 
     steps:
     - uses: actions/checkout@v2
 
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
     - name : submodule checkout
       # Need to update submodules
       run: git submodule update --init --depth 1
@@ -45,7 +49,7 @@ jobs:
       # Note the current convention is to use the -S and -B options here to specify source
       # and build directories, but this is only available with CMake 3.13 and higher.
       # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
-      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True
 
     - name: Build
       working-directory: ${{runner.workspace}}/build
@@ -113,13 +117,36 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC64.log || true
 
+    - name: gcc target tests 32
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the gvisor tests
+      run: cmake --build . --config $BUILD_TYPE --target gcc_target_tests_32
+
+    - name: GCC32 Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC32.log || true
+
+    - name: Struct verifier tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target struct_verifier
+
+    - name: Struct verifier Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_StructVerifier.log || true
+
     - name: Truncate test results
       if: ${{ always() }}
       shell: bash
       working-directory: ${{runner.workspace}}/build
       # Cap out the log files at 20M in case something crash spins and dumps fault text
       # ASM tests get quite close to 10MB
-      run: truncate --size=20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
 
     - name: Set runner name
       if: ${{ always() }}

.gitmodules

@@ -30,3 +30,15 @@
         shallow = true
 	path = External/fex-gcc-target-tests-bins
 	url = https://github.com/FEX-Emu/fex-gcc-target-tests-bins.git
+[submodule "External/jemalloc"]
+	path = External/jemalloc
+	url = https://github.com/FEX-Emu/jemalloc.git
+[submodule "External/fmt"]
+	path = External/fmt
+	url = https://github.com/fmtlib/fmt.git
+[submodule "External/drm-headers"]
+	path = External/drm-headers
+	url = https://github.com/FEX-Emu/drm-headers.git
+[submodule "External/xxhash"]
+	path = External/xxhash
+	url = https://github.com/FEX-Emu/xxHash.git

CMakeLists.txt

@@ -12,6 +12,10 @@ option(ENABLE_ASAN "Enables Clang ASAN" FALSE)
 option(ENABLE_TSAN "Enables Clang TSAN" FALSE)
 option(ENABLE_ASSERTIONS "Enables assertions in build" FALSE)
 option(ENABLE_VISUAL_DEBUGGER "Enables the visual debugger for compiling" FALSE)
+option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
+option(ENABLE_WERROR "Enables -Werror" FALSE)
+option(ENABLE_STATIC_PIE "Enables static-pie build" FALSE)
+option(ENABLE_JEMALLOC "Enables jemalloc allocator" TRUE)
 
 set (X86_C_COMPILER "x86_64-linux-gnu-gcc" CACHE STRING "c compiler for compiling x86 guest libs")
 set (X86_CXX_COMPILER "x86_64-linux-gnu-g++" CACHE STRING "c++ compiler for compiling x86 guest libs")
@@ -27,14 +31,6 @@ if (ENABLE_ASSERTIONS)
   add_definitions(-DASSERTIONS_ENABLED=1)
 endif()
 
-if (ENABLE_IWYU)
-  find_program(IWYU_EXE "iwyu")
-  if (IWYU_EXE)
-    message(STATUS "IWYU enabled")
-    set(CMAKE_CXX_INCLUDE_WHAT_YOU_USE "${IWYU_EXE}")
-  endif()
-endif()
-
 set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/Bin)
@@ -50,6 +46,25 @@ else()
   set(CMAKE_INTERPROCEDURAL_OPTIMIZATION FALSE)
 endif()
 
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
+  option(ENABLE_X86_HOST_DEBUG "Enables compiling on x86_64 host" FALSE)
+  if (NOT ENABLE_X86_HOST_DEBUG)
+    message(FATAL_ERROR
+      " Be warned: FEX isn't optimized for x86_64 hosts!\n"
+      " Support for x86_64 hosts is only for debugging and convenience!\n"
+      " Don't expect amazing performance or optimal code generation!\n"
+      " Pass -DENABLE_X86_HOST_DEBUG=True to bypass this message!")
+  endif()
+  set(_M_X86_64 1)
+  add_definitions(-D_M_X86_64=1)
+  set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
+endif()
+
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
+  set(_M_ARM_64 1)
+  add_definitions(-D_M_ARM_64=1)
+endif()
+
 find_program(CCACHE_PROGRAM ccache)
 if(CCACHE_PROGRAM)
   message(STATUS "CCache enabled")
@@ -61,14 +76,140 @@ if (ENABLE_XRAY)
   link_libraries(-fxray-instrument)
 endif()
 
+set (PTHREAD_LIB pthread)
 if (ENABLE_LLD)
-  link_libraries(-fuse-ld=lld)
+  set (LD_OVERRIDE "-fuse-ld=lld")
+  link_libraries(${LD_OVERRIDE})
+endif()
+
+if (ENABLE_STATIC_PIE)
+  if (_M_ARM_64 AND ENABLE_LLD)
+    message (FATAL_ERROR "Static linking does not currently work with AArch64+LLD. Use GNU ld for now.")
+  endif()
+
+  file(WRITE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt.c
+    "int main(int argc, char* argv[])
+      {
+        return 0;
+      }")
+
+  # Compile the test application with our LD_OVERRIDE and static-pie options
+  try_compile(
+    COMPILE_RESULT
+    ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp
+    ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt.c
+    COMPILE_DEFINITIONS "-fPIE ${LD_OVERRIDE}"
+    LINK_LIBRARIES "-static-pie ${LD_OVERRIDE}"
+    COPY_FILE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt
+  )
+
+  if (${COMPILE_RESULT})
+    # Read the symbols from the elf
+    execute_process(COMMAND
+      readelf -s ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt
+      OUTPUT_FILE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/plt_out.txt
+      OUTPUT_VARIABLE PLT_SYMBOLS)
+
+    # Pull out the __rela_iplt_{start,end} symbols if they exist
+    execute_process(COMMAND
+      "grep" "__rela_iplt" ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/plt_out.txt
+      OUTPUT_VARIABLE PLT_SYMBOLS)
+
+    set (SYMBOLS_FINE TRUE)
+    set (HAS_IPLT -1)
+    # Check if we have any symbols in our grep output
+    # The symbols must either not exist at all OR the symbols are zero
+    if (PLT_SYMBOLS)
+      string(FIND ${PLT_SYMBOLS} "__rela_iplt_start" HAS_IPLT)
+    endif()
+
+    if (NOT HAS_IPLT EQUAL -1)
+      # We have some symbols from readelf. Let's parse the results to check if they are zero
+      # Format: '35: 0000000000000000     0 NOTYPE  LOCAL  HIDDEN   UND __rela_iplt_start'
+      string(REPLACE "\n" ";" SYMBOL_LIST ${PLT_SYMBOLS})
+      foreach (SYMBOL ${SYMBOL_LIST})
+        # strip any leading and trailing whitespace
+        string (STRIP ${SYMBOL} SYMBOL)
+        # Convert string to a list
+        string(REPLACE " " ";" SYMBOL_VALUES ${SYMBOL}})
+        # Pull out the address argument
+        list(GET SYMBOL_VALUES 1 OFFSET)
+
+        # Check against integer zero
+        if (NOT ${OFFSET} EQUAL 0)
+          # Symbol wasn't zero, this now fails
+          set (SYMBOLS_FINE FALSE)
+        endif()
+      endforeach()
+    endif()
+
+    if (SYMBOLS_FINE)
+      # We can now exnable static-pie
+      set (STATIC_PIE_OPTIONS "-static-pie")
+      # Pthreads has an issue with exposing symbols
+      # We need to make some concessions to the pthread gods
+      if (ENABLE_LLD)
+        set (PTHREAD_LIB
+          -Wl,--undefined-glob=pthread_*
+          -Wl,--undefined=__cxa_finalize
+          -Wl,--undefined=_pthread_cleanup_push_defer
+          -Wl,--undefined=_pthread_cleanup_pop_restore
+          -Wl,--undefined=__pthread_cleanup_upto
+          pthread)
+      else()
+        set (PTHREAD_LIB
+          -Wl,--undefined=pthread_join
+          -Wl,--undefined=pthread_attr_getdetachstate
+          -Wl,--undefined=pthread_sigmask
+          -Wl,--undefined=pthread_mutex_lock
+          -Wl,--undefined=pthread_cond_init
+          -Wl,--undefined=pthread_attr_init
+          -Wl,--undefined=pthread_mutex_unlock
+          -Wl,--undefined=pthread_mutexattr_destroy
+          -Wl,--undefined=pthread_detach
+          -Wl,--undefined=pthread_mutex_init
+          -Wl,--undefined=pthread_getattr_np
+          -Wl,--undefined=pthread_cond_timedwait
+          -Wl,--undefined=pthread_attr_destroy
+          -Wl,--undefined=pthread_mutexattr_settype
+          -Wl,--undefined=pthread_rwlock_unlock
+          -Wl,--undefined=pthread_rwlock_wrlock
+          -Wl,--undefined=pthread_setspecific
+          -Wl,--undefined=pthread_create
+          -Wl,--undefined=pthread_cond_clockwait
+          -Wl,--undefined=pthread_key_create
+          -Wl,--undefined=pthread_rwlock_rdlock
+          -Wl,--undefined=pthread_setname_np
+          -Wl,--undefined=pthread_cond_signal
+          -Wl,--undefined=pthread_mutexattr_init
+          -Wl,--undefined=pthread_attr_setstack
+          -Wl,--undefined=pthread_self
+          -Wl,--undefined=pthread_getaffinity_np
+          -Wl,--undefined=pthread_cond_wait
+          -Wl,--undefined=pthread_mutex_trylock
+          -Wl,--undefined=pthread_cond_broadcast
+          -Wl,--undefined=pthread_cond_destroy
+          -Wl,--undefined=pthread_getspecific
+          -Wl,--undefined=pthread_key_delete
+          -Wl,--undefined=pthread_once
+          -Wl,--undefined=__cxa_finalize
+          -Wl,--undefined=_pthread_cleanup_push_defer
+          -Wl,--undefined=_pthread_cleanup_pop_restore
+          -Wl,--undefined=__pthread_cleanup_upto
+          pthread)
+      endif()
+    else()
+      message (FATAL_ERROR "Application has __rela_iplt_{start,end} symbols. Which means static-pie can't be enabled")
+    endif()
+  else()
+    message (FATAL_ERROR "Couldn't compile static-pie test. Static-pie can't be enabled!")
+  endif()
 endif()
 
 if (ENABLE_ASAN)
   add_definitions(-DENABLE_ASAN=1)
-  add_compile_options(-fno-omit-frame-pointer -fsanitize=address)
-  link_libraries(-fno-omit-frame-pointer -fsanitize=address)
+  add_compile_options(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
+  link_libraries(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
 endif()
 
 if (ENABLE_TSAN)
@@ -76,41 +217,51 @@ if (ENABLE_TSAN)
   link_libraries(-fno-omit-frame-pointer -fsanitize=thread)
 endif()
 
+if (ENABLE_JEMALLOC)
+  add_definitions(-DENABLE_JEMALLOC=1)
+else()
+  message (STATUS
+    " jemalloc disabled!\n"
+    " This is not a recommended configuration!\n"
+    " This will very explicitly break 32-bit application execution!\n"
+    " Use at your own risk!")
+endif()
+
 set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
 set (CMAKE_LINKER_FLAGS_RELWITHDEBINFO "${CMAKE_LINKER_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
 
 set (CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -fomit-frame-pointer")
 set (CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-pointer")
 
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
-  set(_M_X86_64 1)
-  add_definitions(-D_M_X86_64=1)
-  set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
-endif()
-
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
-  set(_M_ARM_64 1)
-  add_definitions(-D_M_ARM_64=1)
-  add_subdirectory(External/vixl/)
-  include_directories(External/vixl/src/)
-  if(CMAKE_BUILD_TYPE MATCHES DEBUG)
-    add_definitions(-DVIXL_DEBUG=1)
-  endif()
-endif()
+add_subdirectory(External/vixl/)
+include_directories(External/vixl/src/)
 
 if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
   # This means we were attempted to get compiled with GCC
   message(FATAL_ERROR "FEX doesn't support getting compiled with GCC!")
 endif()
 
-find_package(Python 3.0 REQUIRED COMPONENTS Interpreter Development)
+find_package(PkgConfig REQUIRED)
+find_package(Python 3.0 REQUIRED COMPONENTS Interpreter)
+pkg_check_modules(XXHASH libxxhash>=0.8.0 QUIET)
+
+if (NOT XXHASH_FOUND)
+  message(STATUS "xxHash not found. Using Externals")
+  add_subdirectory(External/xxhash/)
+  include_directories(External/xxhash/)
+endif()
 
 add_definitions(-Wno-trigraphs)
 add_definitions(-DGLOBAL_DATA_DIRECTORY="${DATA_DIRECTORY}/")
 
+add_subdirectory(External/jemalloc/)
+include_directories(External/jemalloc/pregen/include/)
+
 add_subdirectory(External/cpp-optparse/)
 include_directories(External/cpp-optparse/)
 
+add_subdirectory(External/fmt/)
+
 add_subdirectory(External/imgui/)
 include_directories(External/imgui/)
 
@@ -149,32 +300,118 @@ if(COMPILER_SUPPORTS_MARCH_NATIVE)
   set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native")
 endif()
 
-if(_M_ARM_64)
-  # Due to an oversight in llvm, it declares any reasonably new Kryo CPU to only be ARMv8.0
-  # Manually detect newer CPU revisions until clang and llvm fixes their bug
-  # This script will either provide a supported CPU or 'native'
-  # Additionally -march doesn't work under AArch64+Clang, so you have to use -mcpu or -mtune
-  execute_process(COMMAND python3 "${PROJECT_SOURCE_DIR}/Scripts/aarch64_fit_native.py" "/proc/cpuinfo"
-    OUTPUT_VARIABLE AARCH64_CPU)
-
-  string(STRIP ${AARCH64_CPU} AARCH64_CPU)
-
-  check_cxx_compiler_flag("-mcpu=${AARCH64_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
-  if(COMPILER_SUPPORTS_CPU_TYPE)
-    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcpu=${AARCH64_CPU}")
+if(ENABLE_WERROR OR ENABLE_STRICT_WERROR)
+  add_compile_options(-Werror)
+  if (NOT ENABLE_STRICT_WERROR)
+    # Disable some Werror that can add frustration when developing
+    add_compile_options(-Wno-error=unused-variable)
   endif()
 endif()
 
+if(_M_ARM_64)
+  if (CMAKE_CXX_COMPILER_VERSION VERSION_GREATER_EQUAL 999999.0)
+    # Clang 12.0 fixed the -mcpu=native bug with mixed big.little implementers
+    # Clang can not currently check for native Apple M1 type in hypervisor. Currently disabled
+    check_cxx_compiler_flag("-mcpu=native" COMPILER_SUPPORTS_CPU_TYPE)
+    if(COMPILER_SUPPORTS_CPU_TYPE)
+      set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcpu=native")
+    endif()
+  else()
+    # Due to an oversight in llvm, it declares any reasonably new Kryo CPU to only be ARMv8.0
+    # Manually detect newer CPU revisions until clang and llvm fixes their bug
+    # This script will either provide a supported CPU or 'native'
+    # Additionally -march doesn't work under AArch64+Clang, so you have to use -mcpu or -mtune
+    execute_process(COMMAND python3 "${PROJECT_SOURCE_DIR}/Scripts/aarch64_fit_native.py" "/proc/cpuinfo" "${CMAKE_CXX_COMPILER_VERSION}"
+      OUTPUT_VARIABLE AARCH64_CPU)
+
+    string(STRIP ${AARCH64_CPU} AARCH64_CPU)
+
+    check_cxx_compiler_flag("-mcpu=${AARCH64_CPU}" COMPILER_SUPPORTS_CPU_TYPE)
+    if(COMPILER_SUPPORTS_CPU_TYPE)
+      set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcpu=${AARCH64_CPU}")
+    endif()
+  endif()
+endif()
+
+if (ENABLE_IWYU)
+  find_program(IWYU_EXE "iwyu")
+  if (IWYU_EXE)
+    message(STATUS "IWYU enabled")
+    set(CMAKE_CXX_INCLUDE_WHAT_YOU_USE "${IWYU_EXE}")
+  endif()
+endif()
+
+if (ENABLE_CLANG_FORMAT)
+  find_program(CLANG_TIDY_EXE "clang-tidy")
+  if (NOT CLANG_TIDY_EXE)
+    message(FATAL_ERROR "Couldn't find clang-tidy")
+  endif()
+
+  set(CLANG_TIDY_FLAGS
+    "-checks=*"
+    "-fuchsia*"
+    "-bugprone-macro-parentheses"
+    "-clang-analyzer-core.*"
+    "-cppcoreguidelines-pro-type-*"
+    "-cppcoreguidelines-pro-bounds-array-to-pointer-decay"
+    "-cppcoreguidelines-pro-bounds-pointer-arithmetic"
+    "-cppcoreguidelines-avoid-c-arrays"
+    "-cppcoreguidelines-avoid-magic-numbers"
+    "-cppcoreguidelines-pro-bounds-constant-array-index"
+    "-cppcoreguidelines-no-malloc"
+    "-cppcoreguidelines-special-member-functions"
+    "-cppcoreguidelines-owning-memory"
+    "-cppcoreguidelines-macro-usage"
+    "-cppcoreguidelines-avoid-goto"
+    "-google-readability-function-size"
+    "-google-readability-namespace-comments"
+    "-google-readability-braces-around-statements"
+    "-google-build-using-namespace"
+    "-hicpp-*"
+    "-llvm-namespace-comment"
+    "-llvm-include-order" # Messes up with case sensitivity
+    "-llvmlibc-*"
+    "-misc-unused-parameters"
+    "-modernize-loop-convert"
+    "-modernize-use-auto"
+    "-modernize-avoid-c-arrays"
+    "-modernize-use-nodiscard"
+    "readability-*"
+    "-readability-function-size"
+    "-readability-implicit-bool-conversion"
+    "-readability-braces-around-statements"
+    "-readability-else-after-return"
+    "-readability-magic-numbers"
+    "-readability-named-parameter"
+    "-readability-uppercase-literal-suffix"
+    "-cert-err34-c"
+    "-cert-err58-cpp"
+    "-bugprone-exception-escape"
+    )
+  string(REPLACE ";" "," CLANG_TIDY_FLAGS "${CLANG_TIDY_FLAGS}")
+  set(CMAKE_CXX_CLANG_TIDY ${CLANG_TIDY_EXE} "${CLANG_TIDY_FLAGS}")
+endif()
+
 add_compile_options(-Wall)
 
-add_subdirectory(External/FEXCore)
-
-add_subdirectory(Source/)
+configure_file(
+  ${CMAKE_CURRENT_SOURCE_DIR}/include/Config.h.in
+  ${CMAKE_BINARY_DIR}/generated/ConfigDefines.h)
 
 if (BUILD_TESTS)
   include(CTest)
   enable_testing()
   message(STATUS "Unit tests are enabled")
+endif()
+add_subdirectory(External/FEXCore)
+
+# Binfmt_misc files must be installed prior to Source/ installs
+add_subdirectory(Data/binfmts/)
+
+add_subdirectory(Source/)
+add_subdirectory(Data/AppConfig/)
+
+if (BUILD_TESTS)
   add_subdirectory(unittests/)
 endif()
 
@@ -185,16 +422,96 @@ if (BUILD_THUNKS)
     PREFIX host-libs
     SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/ThunkLibs/HostLibs"
     BINARY_DIR "Host"
+    CMAKE_ARGS "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
     INSTALL_COMMAND ""
     BUILD_ALWAYS ON
   )
 
+  install(
+    CODE "MESSAGE(\"-- Installing: host-libs\")"
+    CODE "
+    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target ThunkHostsInstall
+    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Host
+    )"
+    DEPENDS host-libs
+  )
+
   ExternalProject_Add(guest-libs
     PREFIX guest-libs
     SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/ThunkLibs/GuestLibs"
     BINARY_DIR "Guest"
-    CMAKE_ARGS "-DX86_C_COMPILER:STRING=${X86_C_COMPILER}" "-DX86_CXX_COMPILER:STRING=${X86_CXX_COMPILER}"
+    CMAKE_ARGS "-DX86_C_COMPILER:STRING=${X86_C_COMPILER}" "-DX86_CXX_COMPILER:STRING=${X86_CXX_COMPILER}" "-DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX}"
     INSTALL_COMMAND ""
     BUILD_ALWAYS ON
   )
+
+  install(
+    CODE "MESSAGE(\"-- Installing: guest-libs\")"
+    CODE "
+    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target ThunkGuestsInstall
+    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest
+    )"
+    DEPENDS guest-libs
+  )
 endif()
+
+set(FEX_VERSION_MAJOR "0")
+set(FEX_VERSION_MINOR "0")
+set(FEX_VERSION_PATCH "0")
+
+find_package(Git)
+if (GIT_FOUND)
+  execute_process(
+    COMMAND ${GIT_EXECUTABLE} describe --abbrev=0
+    WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
+    OUTPUT_VARIABLE GIT_DESCRIBE_STRING
+    RESULT_VARIABLE GIT_ERROR
+    ERROR_QUIET
+    OUTPUT_STRIP_TRAILING_WHITESPACE
+  )
+
+  if (NOT ${GIT_ERROR} EQUAL 0)
+    # Likely built in a way that doesn't have tags
+    # Setup a version tag that is unknown
+    set(GIT_DESCRIBE_STRING "FEX-0000")
+  endif()
+
+  # Change something like `FEX-2106.1-76-<hash>` in to a list
+  string(REPLACE "-" ";" DESCRIBE_LIST ${GIT_DESCRIBE_STRING})
+
+  # Extract the `2106.1` element
+  list(GET DESCRIBE_LIST 1 DESCRIBE_LIST)
+
+  # Change `2106.1` in to a list
+  string(REPLACE "." ";" DESCRIBE_LIST ${DESCRIBE_LIST})
+
+  # Calculate list size
+  list(LENGTH DESCRIBE_LIST LIST_SIZE)
+
+  # Pull out the major version
+  list(GET DESCRIBE_LIST 0 FEX_VERSION_MAJOR)
+
+  # Minor version only exists if there is a .1 at the end
+  # eg: 2106 versus 2106.1
+  if (LIST_SIZE GREATER 1)
+    list(GET DESCRIBE_LIST 1 FEX_VERSION_MINOR)
+  endif()
+endif()
+
+# Package creation
+set (CPACK_GENERATOR "DEB")
+set (CPACK_PACKAGE_NAME fex-emu)
+set (CPACK_PACKAGE_CONTACT "team@fex-emu.org")
+set (CPACK_PACKAGE_VERSION_MAJOR "${FEX_VERSION_MAJOR}")
+set (CPACK_PACKAGE_VERSION_MINOR "${FEX_VERSION_MINOR}")
+set (CPACK_PACKAGE_VERSION_PATCH "${FEX_VERSION_PATCH}")
+
+# Debian defines
+set (CPACK_DEBIAN_PACKAGE_DEPENDS "libstdc++6")
+set (CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA "${CMAKE_CURRENT_SOURCE_DIR}/CPack/postinst;${CMAKE_CURRENT_SOURCE_DIR}/CPack/prerm")
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
+  # binfmt_misc conflicts with qemu-user-static
+  # We also only install binfmt_misc on aarch64 hosts
+  set (CPACK_DEBIAN_PACKAGE_CONFLICTS "qemu-user-static")
+endif()
+include (CPack)

CPack/postinst

@@ -0,0 +1,18 @@
+#!/bin/sh
+set -e
+update_binfmt() {
+  # Check for update-binfmts
+  command -v update-binfmts >/dev/null || return 0
+
+  # Setup binfmt_misc
+  update-binfmts --import FEX-x86
+  update-binfmts --import FEX-x86_64
+}
+
+# Install FEXInterpreter hardlink
+# Needs to be done before setting up binfmt_misc
+ln -f /usr/bin/FEXLoader /usr/bin/FEXInterpreter
+
+if [ $(uname -m) = 'aarch64' ]; then
+  update_binfmt
+fi

CPack/prerm

@@ -0,0 +1,17 @@
+#!/bin/sh
+set -e
+update_binfmt() {
+  # Check for update-binfmts
+  command -v update-binfmts >/dev/null || return 0
+
+  # Uninstall
+  update-binfmts --unimport FEX-x86
+  update-binfmts --unimport FEX-x86_64
+}
+
+if [ $(uname -m) = 'aarch64' ]; then
+  update_binfmt
+fi
+
+# Remove FEXInterpreter hardlink
+unlink /usr/bin/FEXInterpreter

Data/AppConfig/CMakeLists.txt

@@ -0,0 +1,25 @@
+file(GLOB CONFIG_SOURCES CONFIGURE_DEPENDS *.json)
+file(GLOB GEN_CONFIG_SOURCES CONFIGURE_DEPENDS *.json.in)
+
+# Any application configuration json file gets installed
+foreach(CONFIG_SRC ${CONFIG_SOURCES})
+  install(FILES ${CONFIG_SRC}
+    DESTINATION ${DATA_DIRECTORY}/AppConfig/)
+endforeach()
+
+# Any configuration file json file that needs to be generated
+# First generate then install it
+foreach(GEN_CONFIG_SRC ${GEN_CONFIG_SOURCES})
+  # Get the filename only component
+  get_filename_component(CONFIG_NAME ${GEN_CONFIG_SRC} NAME_WE)
+
+  # Configure it
+  configure_file(
+    ${GEN_CONFIG_SRC}
+    ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}.json)
+
+  # Then install the configured json
+  install(
+    FILES ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}.json
+    DESTINATION ${DATA_DIRECTORY}/AppConfig/)
+endforeach()

Data/AppConfig/steam.json.in

@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "Env": "STEAM_GAME_LAUNCH_SHELL=@CMAKE_INSTALL_PREFIX@/bin/FEXBash"
+  }
+}

Data/AppConfig/steamwebhelper.json

@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "StallProcess": "1"
+  }
+}

Data/binfmts/CMakeLists.txt

@@ -0,0 +1,17 @@
+function(GenBinFmt Name)
+  # Get the filename only component
+  get_filename_component(FMT_NAME ${Name} NAME_WE)
+
+  # Configure it
+  configure_file(
+    ${Name}
+    ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME})
+
+  # Then install the configured binfmt
+  install(
+    FILES ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME}
+    DESTINATION ${CMAKE_INSTALL_PREFIX}/share/binfmts/)
+endfunction()
+
+GenBinFmt(FEX-x86.in)
+GenBinFmt(FEX-x86_64.in)

Data/binfmts/FEX-x86.in

@@ -0,0 +1,8 @@
+package fex
+interpreter @CMAKE_INSTALL_PREFIX@/bin/FEXInterpreter
+magic \x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00
+offset 0
+mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff
+credentials yes
+fix_binary yes
+preserve yes

Data/binfmts/FEX-x86_64.in

@@ -0,0 +1,8 @@
+package fex
+interpreter @CMAKE_INSTALL_PREFIX@/bin/FEXInterpreter
+magic \x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x3e\x00
+offset 0
+mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff
+credentials yes
+fix_binary yes
+preserve yes

Dockerfile

@@ -3,8 +3,9 @@ FROM ubuntu:20.04 as builder
 
 RUN DEBIAN_FRONTEND="noninteractive" apt-get update
 RUN DEBIAN_FRONTEND="noninteractive" apt install -y cmake \
-clang-10 llvm-10 nasm ninja-build libnuma-dev \
-libcap-dev libglfw3-dev libepoxy-dev
+clang-10 llvm-10 nasm ninja-build \
+libcap-dev libglfw3-dev libepoxy-dev python3-dev \
+python3 linux-headers-generic
 
 COPY . /opt/FEX
 
@@ -22,7 +23,7 @@ FROM ubuntu:20.04
 
 RUN DEBIAN_FRONTEND="noninteractive" apt-get update
 RUN DEBIAN_FRONTEND="noninteractive" apt install -y \
-libnuma-dev libcap-dev libglfw3-dev libepoxy-dev
+libcap-dev libglfw3-dev libepoxy-dev
 
 COPY --from=builder /opt/FEX/build/Bin/* /usr/bin/
 

External/FEXCore/CMakeLists.txt

@@ -4,6 +4,17 @@ project(${PROJECT_NAME}
   VERSION 0.01
   LANGUAGES CXX)
 
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
+  set(_M_X86_64 1)
+  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
+endif()
+
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
+  set(_M_ARM_64 1)
+endif()
+
+set(ENABLE_JIT_X86_64 ${_M_X86_64} CACHE BOOL "Enable the x86_64 JIT")
+set(ENABLE_JIT_ARM64 ${_M_ARM_64} CACHE BOOL "Enable the ARM64 JIT")
 option(ENABLE_CLANG_FORMAT "Run clang format over the source" FALSE)
 option(ENABLE_JITSYMBOLS "Enable visibility of JITSymbols in profiling tools" FALSE)
 
@@ -17,22 +28,11 @@ set(CMAKE_INCLUDE_CURRENT_DIR ON)
 include(CheckCXXCompilerFlag)
 include(CheckIncludeFileCXX)
 
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
-  set(_M_X86_64 1)
-  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
-  message(STATUS "Enabling x86-64 JIT")
-  set(ENABLE_JIT 1)
-endif()
 
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
-  message(STATUS "Enabling AArch64 JIT")
-  set(_M_ARM_64 1)
-  set(ENABLE_JIT 1)
-  if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
+if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
     # Useful to have for freestanding libFEXCore
     add_subdirectory(External/vixl/)
     include_directories(External/vixl/src/)
-  endif()
 endif()
 
 set(CMAKE_CXX_STANDARD 20)

External/FEXCore/Scripts/config_generator.py

@@ -0,0 +1,473 @@
+import datetime
+import json
+import sys
+
+def print_header():
+    header = '''#ifndef OPT_BASE
+#define OPT_BASE(type, group, enum, json, default)
+#endif
+#ifndef OPT_BOOL
+#define OPT_BOOL(group, enum, json, default) OPT_BASE(bool, group, enum, json, default)
+#endif
+#ifndef OPT_UINT8
+#define OPT_UINT8(group, enum, json, default) OPT_BASE(uint8_t, group, enum, json, default)
+#endif
+#ifndef OPT_INT32
+#define OPT_INT32(group, enum, json, default) OPT_BASE(int32_t, group, enum, json, default)
+#endif
+#ifndef OPT_UINT32
+#define OPT_UINT32(group, enum, json, default) OPT_BASE(uint32_t, group, enum, json, default)
+#endif
+#ifndef OPT_UINT64
+#define OPT_UINT64(group, enum, json, default) OPT_BASE(uint64_t, group, enum, json, default)
+#endif
+#ifndef OPT_STR
+#define OPT_STR(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#endif
+#ifndef OPT_STRARRAY
+#define OPT_STRARRAY(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#endif
+
+'''
+    output_file.write(header)
+
+def print_tail():
+    tail = '''#undef OPT_BASE
+#undef OPT_BOOL
+#undef OPT_UINT8
+#undef OPT_INT32
+#undef OPT_UINT32
+#undef OPT_UINT64
+#undef OPT_STR
+#undef OPT_STRARRAY
+'''
+    output_file.write(tail)
+
+def print_config(type, group_name, json_name, default_value):
+    output_file.write("OPT_{0} ({1}, {2}, {3}, {4})\n".format(type.upper(), group_name.upper(), json_name.upper(), json_name, default_value))
+
+def print_options(options):
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "\"" + default + "\""
+
+            print_config(
+                op_vals["Type"],
+                op_group,
+                op_key,
+                default)
+
+        output_file.write("\n")
+
+def print_unnamed_options(options):
+    output_file.write("// Unnamed configuration options\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "\"" + default + "\""
+
+            print_config(
+                op_vals["Type"],
+                op_group,
+                op_key.upper(), # KEY is the enum here, there is no json configuration for these
+                default)
+
+        output_file.write("\n")
+
+def print_man_option(short, long, desc, default):
+    if (short != None):
+        output_man.write(".It Fl {0} , ".format(short))
+    else:
+        output_man.write(".It ")
+
+    output_man.write("Fl Fl {0}=".format(long))
+
+    output_man.write("\n");
+
+    # Print description
+    for line in desc:
+        output_man.write(".Pp\n")
+        output_man.write("{0}\n".format(line))
+
+    output_man.write(".Pp\n")
+    output_man.write("\\fBdefault:\\fR {0}\n".format(default))
+    output_man.write(".Pp\n\n")
+
+def print_man_env_option(name, desc, default, no_json_key):
+    output_man.write("\\fBFEX_{0}\\fR\n".format(name.upper()))
+
+    # Print description
+    for line in desc:
+        output_man.write(".Pp\n")
+        output_man.write("{0}\n".format(line))
+
+    if (not no_json_key):
+        output_man.write(".Pp\n")
+        output_man.write("\\fBJSON key:\\fR '{0}'\n".format(name))
+        output_man.write(".Pp\n\n")
+
+    output_man.write(".Pp\n")
+    output_man.write("\\fBdefault:\\fR {0}\n".format(default))
+    output_man.write(".Pp\n\n")
+
+def print_man_options(options):
+    output_man.write(".Sh OPTIONS\n")
+    output_man.write(".Bl -tag -width -indent\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            short = None
+            long = op_key.lower()
+
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+
+            default = op_vals["Default"]
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = op_vals["TextDefault"]
+
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "'" + default + "'"
+            print_man_option(
+                short,
+                long,
+                op_vals["Desc"],
+                default
+            )
+
+    output_man.write(".El\n")
+
+def print_man_environment(options):
+    output_man.write(".Sh ENVIRONMENT\n")
+    output_man.write(".Bl -tag -width -indent\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = op_vals["TextDefault"]
+
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "'" + default + "'"
+            print_man_env_option(
+                op_key,
+                op_vals["Desc"],
+                default,
+                False
+            )
+
+    print_man_environment_tail()
+    output_man.write(".El\n")
+
+def print_man_environment_tail():
+
+    # Additional environment variables that live outside of the normal loop
+    print_man_env_option(
+    "FEX_APP_CONFIG_LOCATION",
+    [
+    "Allows the user to override where FEX looks for configuration files",
+    "By default FEX will look in {$HOME, $XDG_CONFIG_HOME}/.fex-emu/",
+    "This will override the full path",
+    ],
+    "''", True)
+
+    print_man_env_option(
+    "FEX_APP_CONFIG",
+    [
+    "Allows the user to override where FEX looks for only the application config file",
+    "By default FEX will look in {$HOME, $XDG_CONFIG_HOME}/.fex-emu/Config.json",
+    "This will override this file location",
+    "One must be careful with this option as it will override any applications that load with execve as well"
+    "If you need to support applications that execve then use FEX_APP_CONFIG_LOCATION instead"
+    ],
+    "''", True)
+
+    print_man_env_option(
+    "FEX_APP_DATA_LOCATION",
+    [
+    "Allows the user to override where FEX looks for data files",
+    "By default FEX will look in {$HOME, $XDG_DATA_HOME}/.fex-emu/",
+    "This will override the full path",
+    "This is the folder where FEX stores generated files like IR cache"
+    ],
+    "''", True)
+
+def print_man_header():
+    header ='''.Dd {0}
+.Dt FEX
+.Os Linux
+.Sh NAME
+.Nm FEXLoader
+.Nm FEXInterpreter
+.Nm FEXBash
+.Nd Fast x86-64 and x86 emulation.
+.Sh SYNOPSIS
+.Nm
+.Op options
+.Op Ar --
+.Ar Application
+<args> ...
+.Pp
+.Nm FEXInterpreter
+.Ar Application
+<args> ...
+.Pp
+.Nm FEXBash
+.Ar <args> ...
+.Sh DESCRIPTION
+FEX allows you to run x86 and x86-64 binaries on an AArch64 host, similar to qemu-user and box86.
+It has native support for a rootfs overlay, so you don't need to chroot, as well as some thunklibs so it can forward things like GL to the host.
+FEX presents a Linux 5.0 interface to the guest, and supports both AArch64 and x86-64 as hosts.
+FEX is very much work in progress, so expect things to change.
+'''
+    output_man.write(header.format(datetime.datetime.now().strftime("%d-%m-%Y")))
+
+def print_man_tail():
+    tail ='''.Sh FILES
+.Bl -tag -width "$prefix/share/fex-emu/GuestThunks" -compact
+.It Pa $XDG_HOME_DIR/.fex-emu
+Default FEX user configuration directory
+.It Pa $prefix/share/fex-emu/AppConfig
+System level application configuration files
+.It Pa $prefix/share/fex-emu/GuestThunks
+guest-side thunk data libraries
+.It Pa $prefix/lib/fex-emu/HostThunks
+host-side thunks for guest communication
+.El
+'''
+    output_man.write(tail)
+
+def print_config_option(type, group_name, json_name, default_value, short, choices, desc):
+    if (type == "bool"):
+        # Bool gets some special handling to add an inverted case
+        output_argloader.write("{0}Group".format(group_name))
+
+        options = ""
+        AddedArg = False
+        if (short != None):
+            AddedArg = True
+            options += "\"-{0}\"".format(short)
+
+        if (AddedArg):
+            options += ", "
+        options += "\"--{0}\"".format(json_name.lower())
+
+        output_argloader.write(".add_option({0})".format(options))
+
+        output_argloader.write("\n")
+
+        output_argloader.write("\t.action(\"store_true\")\n")
+
+        output_argloader.write("\t.dest(\"{0}\")\n".format(json_name));
+
+        # help
+        output_argloader.write("\t.help(\n")
+        desc_line_ender = ""
+        if (len(desc) > 1):
+            desc_line_ender = "\\n"
+
+        for line in desc:
+            output_argloader.write("\t\t\"{0}{1}\"\n".format(line, desc_line_ender))
+        output_argloader.write("\t)\n")
+
+        output_argloader.write("\t.set_default({0});\n\n".format(default_value));
+
+        output_argloader.write("{0}Group".format(group_name))
+        output_argloader.write(".add_option(\"--no-{0}\")\n".format(json_name.lower()))
+
+        # Inverted case sets the bool to false
+        output_argloader.write("\t.action(\"store_false\")\n")
+
+        output_argloader.write("\t.dest(\"{0}\");\n".format(json_name));
+    else:
+        output_argloader.write("{0}Group".format(group_name))
+        options = ""
+        AddedArg = False
+        if (short != None):
+            AddedArg = True
+            options += "\"-{0}\"".format(short)
+
+        if (AddedArg):
+            options += ", "
+        options += "\"--{0}\"".format(json_name.lower())
+
+        output_argloader.write(".add_option({0})".format(options))
+
+        output_argloader.write("\n")
+
+        output_argloader.write("\t.dest(\"{0}\")\n".format(json_name));
+
+        if (choices != None):
+            output_argloader.write("\t.choices({\n")
+            for choice in choices:
+                output_argloader.write("\t\t\"{0}\",\n".format(choice))
+            output_argloader.write("\t})\n")
+
+
+        # help
+        output_argloader.write("\t.help(\n")
+        desc_line_ender = ""
+        if (len(desc) > 1):
+            desc_line_ender = "\\n"
+
+        for line in desc:
+            output_argloader.write("\t\t\"{0}{1}\"\n".format(line, desc_line_ender))
+        output_argloader.write("\t)\n")
+
+        output_argloader.write("\t.set_default({0});\n".format(default_value));
+
+    output_argloader.write("\n");
+
+def print_argloader_options(options):
+    output_argloader.write("#ifdef BEFORE_PARSE\n")
+    output_argloader.write("#undef BEFORE_PARSE\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            default = op_vals["Default"]
+
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+                # Wrap the string argument in quotes
+                default = "\"" + default + "\""
+
+            # Textual default rather than enum based
+            if ("TextDefault" in op_vals):
+                default = "\"" + op_vals["TextDefault"] + "\""
+
+            short = None
+            choices = None
+
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+            if ("Choices" in op_vals):
+                choices = op_vals["Choices"]
+
+            print_config_option(
+                op_vals["Type"],
+                op_group,
+                op_key,
+                default,
+                short,
+                choices,
+                op_vals["Desc"])
+
+        output_argloader.write("\n")
+    output_argloader.write("#endif\n")
+
+def print_parse_argloader_options(options):
+    output_argloader.write("#ifdef AFTER_PARSE\n")
+    output_argloader.write("#undef AFTER_PARSE\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            output_argloader.write("if (Options.is_set_by_user(\"{0}\")) {{\n".format(op_key))
+
+            value_type = op_vals["Type"]
+            NeedsString = False
+            conversion_func = "std::to_string"
+            if ("ArgumentHandler" in op_vals):
+                NeedsString = True
+                conversion_func = "FEX::Handler::{0}".format(op_vals["ArgumentHandler"])
+            if (value_type == "str"):
+                NeedsString = True
+                conversion_func = ""
+
+            if (value_type == "strarray"):
+                # these need a bit more help
+                output_argloader.write("\tauto Array = Options.all(\"{0}\");\n".format(op_key))
+                output_argloader.write("\tfor (auto iter = Array.begin(); iter != Array.end(); ++iter) {\n")
+                output_argloader.write("\t\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, *iter);\n".format(op_key.upper()))
+                output_argloader.write("\t}\n")
+            else:
+                if (NeedsString):
+                    output_argloader.write("\tstd::string UserValue = Options[\"{0}\"];\n".format(op_key))
+                else:
+                    output_argloader.write("\t{0} UserValue = Options.get(\"{1}\");\n".format(value_type, op_key))
+
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, {1}(UserValue));\n".format(op_key.upper(), conversion_func))
+            output_argloader.write("}\n")
+
+    output_argloader.write("#endif\n")
+
+def check_for_duplicate_options(options):
+    short_map = []
+    long_map = []
+
+    # Spin through all the items and see if we have a duplicate option
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            short = None
+            long = op_key.lower()
+            long_invert = None
+            if ("ShortArg" in op_vals):
+                short = op_vals["ShortArg"]
+            if (op_vals["Type"] == "bool"):
+                long_invert = "no-" + long
+
+            # Check for short key duplication
+            if (short != None):
+                if (short in short_map):
+                    raise Exception("Short config '{0}' for option '{1}' has duplicate entry!".format(short, op_key))
+                else:
+                    short_map.append(short)
+
+            # Check for long key duplication
+            if (long in long_map):
+                raise Exception("Long config '{0}' has duplicate entry!".format(long))
+            else:
+                long_map.append(long)
+
+            # Check for long key duplication
+            if (long_invert != None):
+                if (long_invert in long_map):
+                    raise Exception("Long config '{0}' has duplicate entry!".format(long_invert))
+                else:
+                    long_map.append(long_invert)
+
+if (len(sys.argv) < 5):
+    sys.exit()
+
+output_filename = sys.argv[2]
+output_man_page = sys.argv[3]
+output_argumentloader_filename = sys.argv[4]
+
+json_file = open(sys.argv[1], "r")
+json_text = json_file.read()
+json_file.close()
+
+json_object = json.loads(json_text)
+
+options = json_object["Options"]
+unnamed_options = json_object["UnnamedOptions"]
+
+check_for_duplicate_options(options)
+
+# Generate config include file
+output_file = open(output_filename, "w")
+print_header()
+print_options(options)
+print_unnamed_options(unnamed_options)
+print_tail()
+output_file.close()
+
+# Generate man file
+output_man = open(output_man_page, "w")
+print_man_header()
+print_man_options(options)
+print_man_environment(options)
+print_man_tail()
+
+output_man.close()
+
+# Generate argument loader code
+output_argloader = open(output_argumentloader_filename, "w")
+print_argloader_options(options);
+print_parse_argloader_options(options);
+output_argloader.close()

External/FEXCore/Scripts/json_ir_generator.py

@@ -108,10 +108,10 @@ def print_ir_sizes(ops, defines):
 
     output_file.write("[[maybe_unused]] static size_t GetSize(IROps Op) { return IRSizes[Op]; }\n\n")
 
-    output_file.write("std::string_view const& GetName(IROps Op);\n")
-    output_file.write("uint8_t GetArgs(IROps Op);\n")
-    output_file.write("FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
-    output_file.write("bool HasSideEffects(IROps Op);\n")
+    output_file.write("__attribute__((const)) __attribute__((visibility(\"default\"))) std::string_view const& GetName(IROps Op);\n")
+    output_file.write("__attribute__((const)) __attribute__((visibility(\"default\"))) uint8_t GetArgs(IROps Op);\n")
+    output_file.write("__attribute__((const)) __attribute__((visibility(\"default\"))) FEXCore::IR::RegisterClassType GetRegClass(IROps Op);\n\n")
+    output_file.write("__attribute__((const)) __attribute__((visibility(\"default\"))) bool HasSideEffects(IROps Op);\n")
 
     output_file.write("#undef IROP_SIZES\n")
     output_file.write("#endif\n\n")
@@ -277,7 +277,7 @@ def print_ir_allocator_helpers(ops, defines):
     output_file.write("\tusing IRPair = Wrapper<T>;\n\n")
 
     output_file.write("\tIRPair<IROp_Header> AllocateRawOp(size_t HeaderSize) {\n")
-    output_file.write("\t\tauto Op = reinterpret_cast<IROp_Header*>(Data.Allocate(HeaderSize));\n")
+    output_file.write("\t\tauto Op = reinterpret_cast<IROp_Header*>(DualListData.DataAllocate(HeaderSize));\n")
     output_file.write("\t\tmemset(Op, 0, HeaderSize);\n")
     output_file.write("\t\tOp->Op = IROps::OP_DUMMY;\n")
     output_file.write("\t\treturn IRPair<IROp_Header>{Op, CreateNode(Op)};\n")
@@ -286,7 +286,7 @@ def print_ir_allocator_helpers(ops, defines):
     output_file.write("\ttemplate<class T, IROps T2>\n")
     output_file.write("\tT *AllocateOrphanOp() {\n")
     output_file.write("\t\tsize_t Size = FEXCore::IR::GetSize(T2);\n")
-    output_file.write("\t\tauto Op = reinterpret_cast<T*>(Data.Allocate(Size));\n")
+    output_file.write("\t\tauto Op = reinterpret_cast<T*>(DualListData.DataAllocate(Size));\n")
     output_file.write("\t\tmemset(Op, 0, Size);\n")
     output_file.write("\t\tOp->Header.Op = T2;\n")
     output_file.write("\t\treturn Op;\n")
@@ -295,25 +295,25 @@ def print_ir_allocator_helpers(ops, defines):
     output_file.write("\ttemplate<class T, IROps T2>\n")
     output_file.write("\tIRPair<T> AllocateOp() {\n")
     output_file.write("\t\tsize_t Size = FEXCore::IR::GetSize(T2);\n")
-    output_file.write("\t\tauto Op = reinterpret_cast<T*>(Data.Allocate(Size));\n")
+    output_file.write("\t\tauto Op = reinterpret_cast<T*>(DualListData.DataAllocate(Size));\n")
     output_file.write("\t\tmemset(Op, 0, Size);\n")
     output_file.write("\t\tOp->Header.Op = T2;\n")
     output_file.write("\t\treturn IRPair<T>{Op, CreateNode(&Op->Header)};\n")
     output_file.write("\t}\n\n")
 
     output_file.write("\tuint8_t GetOpSize(OrderedNode *Op) const {\n")
-    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(Data.Begin());\n")
+    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
     output_file.write("\t\treturn HeaderOp->Size;\n")
     output_file.write("\t}\n\n")
 
     output_file.write("\tuint8_t GetOpElements(OrderedNode *Op) const {\n")
-    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(Data.Begin());\n")
-    output_file.write("\t\tLogMan::Throw::A(HeaderOp->HasDest, \"Op %s has no dest\\n\", GetName(HeaderOp->Op));\n")
+    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
+    output_file.write("\t\tLOGMAN_THROW_A(HeaderOp->HasDest, \"Op %s has no dest\\n\", GetName(HeaderOp->Op));\n")
     output_file.write("\t\treturn HeaderOp->Size / HeaderOp->ElementSize;\n")
     output_file.write("\t}\n\n")
 
     output_file.write("\tbool OpHasDest(OrderedNode *Op) const {\n")
-    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(Data.Begin());\n")
+    output_file.write("\t\tauto HeaderOp = Op->Header.Value.GetNode(DualListData.DataBegin());\n")
     output_file.write("\t\treturn HeaderOp->HasDest;\n")
     output_file.write("\t}\n\n")
 
@@ -387,11 +387,14 @@ def print_ir_allocator_helpers(ops, defines):
             output_file.write(") {\n")
 
             output_file.write("\t\tauto Op = AllocateOp<IROp_%s, IROps::OP_%s>();\n" % (op_key, op_key.upper()))
-            output_file.write("\t\tOp.first->Header.NumArgs = %d;\n" % (SSAArgs))
+
+            if (SSAArgs != 0):
+                output_file.write("\t\tauto ListDataBegin = DualListData.ListBegin();\n")
+                for i in range(0, SSAArgs):
+                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(ListDataBegin);\n" % (i, i))
 
             if (SSAArgs != 0):
                 for i in range(0, SSAArgs):
-                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(ListData.Begin());\n" % (i, i))
                     output_file.write("\t\tssa%d->AddUse();\n" % (i))
 
             if (HasArgs):
@@ -399,11 +402,6 @@ def print_ir_allocator_helpers(ops, defines):
                     data_name = op_vals["Args"][i]
                     output_file.write("\t\tOp.first->%s = %s;\n" % (data_name, data_name))
 
-            if (HasFixedDestSize):
-                output_file.write("\t\tOp.first->Header.Size = %d;\n" % FixedDestSize)
-            if (HasDestSize):
-                output_file.write("\t\tOp.first->Header.Size = %s;\n" % DestSize)
-
             if (HasDest):
                 # We can only infer a size if we have arguments
                 if not (HasFixedDestSize or HasDestSize):
@@ -412,10 +410,18 @@ def print_ir_allocator_helpers(ops, defines):
                     if (SSAArgs != 0):
                         for i in range(0, SSAArgs):
                             output_file.write("\t\tuint8_t Size%d = GetOpSize(ssa%s);\n" % (i, i))
+                        for i in range(0, SSAArgs):
                             output_file.write("\t\tInferSize = std::max(InferSize, Size%d);\n" % (i))
 
                     output_file.write("\t\tOp.first->Header.Size = InferSize;\n")
 
+            output_file.write("\t\tOp.first->Header.NumArgs = %d;\n" % (SSAArgs))
+
+            if (HasFixedDestSize):
+                output_file.write("\t\tOp.first->Header.Size = %d;\n" % FixedDestSize)
+            if (HasDestSize):
+                output_file.write("\t\tOp.first->Header.Size = %s;\n" % DestSize)
+
             output_file.write("\t\tOp.first->Header.ElementSize = Op.first->Header.Size / (%s);\n" % NumElements)
 
             if (HasDest):
@@ -499,7 +505,7 @@ def print_ir_parser_allocator_helpers(ops, defines):
 
             if (SSAArgs != 0):
                 for i in range(0, SSAArgs):
-                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(ListData.Begin());\n" % (i, i))
+                    output_file.write("\t\tOp.first->Header.Args[%d] = ssa%d->Wrapped(DualListData.ListBegin());\n" % (i, i))
                     output_file.write("\t\tssa%d->AddUse();\n" % (i))
 
             if (HasArgs):

External/FEXCore/Source/CMakeLists.txt

@@ -1,49 +1,4 @@
-if (ENABLE_CLANG_FORMAT)
-  find_program(CLANG_TIDY_EXE "clang-tidy")
-  set(CLANG_TIDY_FLAGS
-    "-checks=*"
-    "-fuchsia*"
-    "-bugprone-macro-parentheses"
-    "-clang-analyzer-core.*"
-    "-cppcoreguidelines-pro-type-*"
-    "-cppcoreguidelines-pro-bounds-array-to-pointer-decay"
-    "-cppcoreguidelines-pro-bounds-pointer-arithmetic"
-    "-cppcoreguidelines-avoid-c-arrays"
-    "-cppcoreguidelines-avoid-magic-numbers"
-    "-cppcoreguidelines-pro-bounds-constant-array-index"
-    "-cppcoreguidelines-no-malloc"
-    "-cppcoreguidelines-special-member-functions"
-    "-cppcoreguidelines-owning-memory"
-    "-cppcoreguidelines-macro-usage"
-    "-cppcoreguidelines-avoid-goto"
-    "-google-readability-function-size"
-    "-google-readability-namespace-comments"
-    "-google-readability-braces-around-statements"
-    "-google-build-using-namespace"
-    "-hicpp-*"
-    "-llvm-namespace-comment"
-    "-llvm-include-order" # Messes up with case sensitivity
-    "-misc-unused-parameters"
-    "-modernize-loop-convert"
-    "-modernize-use-auto"
-    "-modernize-avoid-c-arrays"
-    "-modernize-use-nodiscard"
-    "readability-*"
-    "-readability-function-size"
-    "-readability-implicit-bool-conversion"
-    "-readability-braces-around-statements"
-    "-readability-else-after-return"
-    "-readability-magic-numbers"
-    "-readability-named-parameter"
-    "-readability-uppercase-literal-suffix"
-    "-cert-err34-c"
-    "-cert-err58-cpp"
-    "-bugprone-exception-escape"
-    )
-  string(REPLACE ";" "," CLANG_TIDY_FLAGS "${CLANG_TIDY_FLAGS}")
-
-  set(CMAKE_CXX_CLANG_TIDY ${CLANG_TIDY_EXE} "${CLANG_TIDY_FLAGS}")
-endif()
+set (MAN_DIR ${CMAKE_INSTALL_PREFIX}/share/man CACHE PATH "MAN_DIR")
 
 set (SRCS
   Common/Paths.cpp
@@ -126,10 +81,19 @@ set (SRCS
   Interface/Core/Frontend.cpp
   Interface/Core/GdbServer.cpp
   Interface/Core/HostFeatures.cpp
+  Interface/Core/OpcodeDispatcher/Crypto.cpp
+  Interface/Core/OpcodeDispatcher/Flags.cpp
+  Interface/Core/OpcodeDispatcher/Vector.cpp
+  Interface/Core/OpcodeDispatcher/X87.cpp
   Interface/Core/OpcodeDispatcher.cpp
   Interface/Core/X86Tables.cpp
   Interface/Core/X86DebugInfo.cpp
   Interface/Core/X86HelperGen.cpp
+  Interface/Core/ArchHelpers/Arm64_stubs.cpp
+  Interface/Core/ArchHelpers/Arm64Emitter.cpp
+  Interface/Core/Dispatcher/Dispatcher.cpp
+  Interface/Core/Dispatcher/X86Dispatcher.cpp
+  Interface/Core/Dispatcher/Arm64Dispatcher.cpp
   Interface/Core/Interpreter/InterpreterCore.cpp
   Interface/Core/Interpreter/InterpreterOps.cpp
   Interface/Core/X86Tables/BaseTables.cpp
@@ -154,6 +118,7 @@ set (SRCS
   Interface/IR/Passes/DeadContextStoreElimination.cpp
   Interface/IR/Passes/IRCompaction.cpp
   Interface/IR/Passes/IRValidation.cpp
+  Interface/IR/Passes/LongDivideRemovalPass.cpp
   Interface/IR/Passes/ValueDominanceValidation.cpp
   Interface/IR/Passes/PhiValidation.cpp
   Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
@@ -161,61 +126,61 @@ set (SRCS
   Interface/IR/Passes/StaticRegisterAllocationPass.cpp
   Interface/IR/Passes/RegisterAllocationPass.cpp
   Interface/IR/Passes/SyscallOptimization.cpp
-  Utils/ELFLoader.cpp
-  Utils/ELFSymbolDatabase.cpp
+  Utils/Allocator.cpp
+  Utils/Allocator/64BitAllocator.cpp
   Utils/LogManager.cpp
+  Utils/Threads.cpp
   )
 
-if (_M_X86_64)
-  list(APPEND SRCS Interface/Core/Interpreter/x86_64Dispatcher.cpp)
-endif()
 if(_M_ARM_64)
   list(APPEND SRCS
-    Interface/Core/ArchHelpers/Arm64.cpp
-    Interface/Core/Interpreter/Arm64Dispatcher.cpp)
+    Interface/Core/ArchHelpers/Arm64.cpp)
 endif()
 
-set (JIT_LIBS )
-if (ENABLE_JIT)
-  if (_M_X86_64)
-    add_definitions(-D_M_X86_64=1)
-    if (NOT FORCE_AARCH64)
-      list(APPEND SRCS
-        Interface/Core/JIT/x86_64/JIT.cpp
-        Interface/Core/JIT/x86_64/ALUOps.cpp
-        Interface/Core/JIT/x86_64/AtomicOps.cpp
-        Interface/Core/JIT/x86_64/BranchOps.cpp
-        Interface/Core/JIT/x86_64/ConversionOps.cpp
-        Interface/Core/JIT/x86_64/EncryptionOps.cpp
-        Interface/Core/JIT/x86_64/FlagOps.cpp
-        Interface/Core/JIT/x86_64/MemoryOps.cpp
-        Interface/Core/JIT/x86_64/MiscOps.cpp
-        Interface/Core/JIT/x86_64/MoveOps.cpp
-        Interface/Core/JIT/x86_64/VectorOps.cpp)
-    endif()
-  endif()
-  if(_M_ARM_64)
-    add_definitions(-D_M_ARM_64=1)
-    add_definitions(-DVIXL_INCLUDE_TARGET_AARCH64=1)
-    add_definitions(-DVIXL_CODE_BUFFER_MMAP=1)
-    list(APPEND SRCS
-      Interface/Core/JIT/Arm64/JIT.cpp
-      Interface/Core/JIT/Arm64/ALUOps.cpp
-      Interface/Core/JIT/Arm64/AtomicOps.cpp
-      Interface/Core/JIT/Arm64/BranchOps.cpp
-      Interface/Core/JIT/Arm64/ConversionOps.cpp
-      Interface/Core/JIT/Arm64/EncryptionOps.cpp
-      Interface/Core/JIT/Arm64/FlagOps.cpp
-      Interface/Core/JIT/Arm64/MemoryOps.cpp
-      Interface/Core/JIT/Arm64/MiscOps.cpp
-      Interface/Core/JIT/Arm64/MoveOps.cpp
-      Interface/Core/JIT/Arm64/VectorOps.cpp)
-    list(APPEND JIT_LIBS vixl)
-  endif()
+set(DEFINES -DTHREAD_LOCAL=_Thread_local)
+
+if (_M_X86_64)
+  list(APPEND DEFINES -D_M_X86_64=1)
+endif()
+
+if (_M_ARM_64)
+  list(APPEND DEFINES -D_M_ARM_64=1)
+endif()
+
+if (ENABLE_JIT_X86_64)
+  list(APPEND SRCS
+    Interface/Core/JIT/x86_64/JIT.cpp
+    Interface/Core/JIT/x86_64/ALUOps.cpp
+    Interface/Core/JIT/x86_64/AtomicOps.cpp
+    Interface/Core/JIT/x86_64/BranchOps.cpp
+    Interface/Core/JIT/x86_64/ConversionOps.cpp
+    Interface/Core/JIT/x86_64/EncryptionOps.cpp
+    Interface/Core/JIT/x86_64/FlagOps.cpp
+    Interface/Core/JIT/x86_64/MemoryOps.cpp
+    Interface/Core/JIT/x86_64/MiscOps.cpp
+    Interface/Core/JIT/x86_64/MoveOps.cpp
+    Interface/Core/JIT/x86_64/VectorOps.cpp)
+  list(APPEND DEFINES -DJIT_X86_64)
+endif()
+
+if (ENABLE_JIT_ARM64)
+  list(APPEND DEFINES -DJIT_ARM64)
+  list(APPEND SRCS
+    Interface/Core/JIT/Arm64/JIT.cpp
+    Interface/Core/JIT/Arm64/ALUOps.cpp
+    Interface/Core/JIT/Arm64/AtomicOps.cpp
+    Interface/Core/JIT/Arm64/BranchOps.cpp
+    Interface/Core/JIT/Arm64/ConversionOps.cpp
+    Interface/Core/JIT/Arm64/EncryptionOps.cpp
+    Interface/Core/JIT/Arm64/FlagOps.cpp
+    Interface/Core/JIT/Arm64/MemoryOps.cpp
+    Interface/Core/JIT/Arm64/MiscOps.cpp
+    Interface/Core/JIT/Arm64/MoveOps.cpp
+    Interface/Core/JIT/Arm64/VectorOps.cpp)
 endif()
 
 if (ENABLE_JITSYMBOLS)
-  add_definitions(-DENABLE_JITSYMBOLS=1)
+  list(APPEND DEFINES -DENABLE_JITSYMBOLS=1)
 endif()
 
 # Generate IR include file
@@ -251,21 +216,64 @@ add_custom_command(
 set_source_files_properties(${OUTPUT_IR_NAME} PROPERTIES
   GENERATED TRUE)
 
-# Create teh target
+# Create the target
 add_custom_target(IR_INC
   DEPENDS "${OUTPUT_NAME}"
   DEPENDS "${OUTPUT_IR_DOC}")
 
+# Generate the configuration include file
+set(OUTPUT_CONFIG_FOLDER "${CMAKE_BINARY_DIR}/include/FEXCore/Config")
+set(OUTPUT_CONFIG_NAME "${OUTPUT_CONFIG_FOLDER}/ConfigValues.inl")
+set(OUTPUT_CONFIG_OPTION_NAME "${OUTPUT_CONFIG_FOLDER}/ConfigOptions.inl")
+set(INPUT_CONFIG_NAME "${CMAKE_CURRENT_SOURCE_DIR}/Interface/Config/Config.json")
+set(OUTPUT_MAN_NAME "${CMAKE_BINARY_DIR}/generated/FEX.1")
+
+add_custom_target(CREATE_CONFIG_FOLDER ALL
+  COMMAND ${CMAKE_COMMAND} -E make_directory "${OUTPUT_CONFIG_FOLDER}")
+
+add_custom_command(
+  OUTPUT "${OUTPUT_CONFIG_NAME}"
+  OUTPUT "${OUTPUT_CONFIG_OPTION_NAME}"
+  OUTPUT "${OUTPUT_MAN_NAME}"
+  DEPENDS "${INPUT_CONFIG_NAME}"
+  DEPENDS CREATE_CONFIG_FOLDER
+  DEPENDS "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/config_generator.py"
+  COMMAND "python3" "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/config_generator.py" "${INPUT_CONFIG_NAME}" "${OUTPUT_CONFIG_NAME}" "${OUTPUT_MAN_NAME}"
+  "${OUTPUT_CONFIG_OPTION_NAME}"
+  )
+
+set_source_files_properties(${OUTPUT_CONFIG_NAME} PROPERTIES
+  GENERATED TRUE)
+set_source_files_properties(${OUTPUT_CONFIG_OPTION_NAME} PROPERTIES
+  GENERATED TRUE)
+
+set_source_files_properties(${OUTPUT_MAN_NAME} PROPERTIES
+  GENERATED TRUE)
+
+# Create the target
+add_custom_target(CONFIG_INC
+  DEPENDS "${OUTPUT_CONFIG_NAME}"
+  DEPENDS "${OUTPUT_CONFIG_OPTION_NAME}"
+  DEPENDS "${OUTPUT_MAN_NAME}")
+
+# Install the man page
+install(FILES ${OUTPUT_MAN_NAME} DESTINATION ${MAN_DIR}/man1)
+
 # Add in diagnostic colours if the option is available.
 # Ninja code generator will kill colours if this isn't here
 check_cxx_compiler_flag(-fdiagnostics-color=always GCC_COLOR)
 check_cxx_compiler_flag(-fcolor-diagnostics CLANG_COLOR)
 
-function(AddLibrary Name Type)
+function(AddObject Name Type)
   add_library(${Name} ${Type} ${SRCS})
   add_dependencies(${Name} IR_INC)
-  target_link_libraries(${Name} pthread rt ${JIT_LIBS} ${LINUX_LIBS} dl)
+  add_dependencies(${Name} CONFIG_INC)
+
+  target_link_libraries(${Name} vixl dl fmt::fmt xxhash)
   set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+  set_target_properties(${Name} PROPERTIES C_VISIBILITY_PRESET hidden)
+  set_target_properties(${Name} PROPERTIES CXX_VISIBILITY_PRESET hidden)
+  set_target_properties(${Name} PROPERTIES VISIBILITY_INLINES_HIDDEN TRUE)
 
   target_include_directories(${Name} PUBLIC "${CMAKE_CURRENT_BINARY_DIR}")
 
@@ -275,9 +283,18 @@ function(AddLibrary Name Type)
   target_include_directories(${Name} PUBLIC "${PROJECT_SOURCE_DIR}/include/")
   target_include_directories(${Name} PUBLIC "${CMAKE_BINARY_DIR}/include/")
 
+  target_compile_definitions(${Name} PRIVATE ${DEFINES})
+
   target_compile_options(${Name}
     PRIVATE
-    -Wno-trigraphs -Wall)
+    -Wall
+    -Werror=cast-qual
+    -Werror=ignored-qualifiers
+    -Werror=implicit-fallthrough
+
+    -Wno-trigraphs
+    -ffunction-sections
+  )
 
   if (GCC_COLOR)
     target_compile_options(${Name}
@@ -291,6 +308,29 @@ function(AddLibrary Name Type)
   endif()
 endfunction()
 
+function(AddLibrary Name Type)
+  add_library(${Name} ${Type} $<TARGET_OBJECTS:${PROJECT_NAME}_object>)
+  target_link_libraries(${Name} vixl dl fmt::fmt xxhash)
+  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+  set_target_properties(${Name} PROPERTIES C_VISIBILITY_PRESET hidden)
+  set_target_properties(${Name} PROPERTIES CXX_VISIBILITY_PRESET hidden)
+  set_target_properties(${Name} PROPERTIES VISIBILITY_INLINES_HIDDEN TRUE)
+
+  target_include_directories(${Name} PUBLIC "${CMAKE_CURRENT_BINARY_DIR}")
+  target_include_directories(${Name} PUBLIC "${PROJECT_SOURCE_DIR}/include/")
+  target_include_directories(${Name} PUBLIC "${CMAKE_BINARY_DIR}/include/")
+
+  if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
+    target_link_options(${Name}
+      PRIVATE
+      "LINKER:--gc-sections"
+      "LINKER:--strip-all"
+      "LINKER:--as-needed"
+    )
+  endif()
+endfunction()
+
+AddObject(${PROJECT_NAME}_object OBJECT)
 AddLibrary(${PROJECT_NAME} STATIC)
 AddLibrary(${PROJECT_NAME}_shared SHARED)
 

External/FEXCore/Source/Common/BitSet.h

@@ -1,5 +1,6 @@
 #pragma once
 #include "Common/MathUtils.h"
+#include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/LogManager.h>
 
 #include <cstring>
@@ -16,16 +17,16 @@ struct BitSet final {
   ElementType *Memory;
   void Allocate(size_t Elements) {
     size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
-    LogMan::Throw::A((AllocateSize * MinimumSize) >= Elements, "Fail");
-    Memory = static_cast<ElementType*>(malloc(AllocateSize));
+    LOGMAN_THROW_A((AllocateSize * MinimumSize) >= Elements, "Fail");
+    Memory = static_cast<ElementType*>(FEXCore::Allocator::malloc(AllocateSize));
   }
   void Realloc(size_t Elements) {
     size_t AllocateSize = AlignUp(Elements, MinimumSizeBits) / MinimumSize;
-    LogMan::Throw::A((AllocateSize * MinimumSize) >= Elements, "Fail");
-    Memory = static_cast<ElementType*>(realloc(Memory, AllocateSize));
+    LOGMAN_THROW_A((AllocateSize * MinimumSize) >= Elements, "Fail");
+    Memory = static_cast<ElementType*>(FEXCore::Allocator::realloc(Memory, AllocateSize));
   }
   void Free() {
-    free(Memory);
+    FEXCore::Allocator::free(Memory);
     Memory = nullptr;
   }
   bool Get(T Element) {
@@ -60,7 +61,7 @@ struct BitSetView final {
   ElementType *Memory;
 
   void GetView(BitSet<T> &Set, uint64_t ElementOffset) {
-    LogMan::Throw::A((ElementOffset % MinimumSize) == 0,
+    LOGMAN_THROW_A((ElementOffset % MinimumSize) == 0,
         "Bitset view offset needs to be aligned to size of backing element");
     Memory = &Set.Memory[ElementOffset / MinimumSizeBits];
   }

External/FEXCore/Source/Common/Paths.cpp

@@ -6,10 +6,13 @@
 #include <sys/stat.h>
 
 namespace FEXCore::Paths {
-  std::string CachePath;
-  std::string EntryCache;
+  std::unique_ptr<std::string> CachePath;
+  std::unique_ptr<std::string> EntryCache;
 
   void InitializePaths() {
+    CachePath = std::make_unique<std::string>();
+    EntryCache = std::make_unique<std::string>();
+
     char const *HomeDir = getenv("HOME");
 
     if (!HomeDir) {
@@ -22,29 +25,35 @@ namespace FEXCore::Paths {
 
     char *XDGDataDir = getenv("XDG_DATA_DIR");
     if (XDGDataDir) {
-      CachePath = XDGDataDir;
+      *CachePath = XDGDataDir;
     }
     else {
       if (HomeDir) {
-        CachePath = HomeDir;
+        *CachePath = HomeDir;
       }
     }
 
-    CachePath += "/.fex-emu/";
-    EntryCache = CachePath + "/EntryCache/";
+    *CachePath += "/.fex-emu/";
+    *EntryCache = *CachePath + "/EntryCache/";
 
+    std::error_code ec{};
     // Ensure the folder structure is created for our Data
-    if (!std::filesystem::exists(EntryCache) &&
-        !std::filesystem::create_directories(EntryCache)) {
-      LogMan::Msg::D("Couldn't create EntryCache directory: '%s'", EntryCache.c_str());
+    if (!std::filesystem::exists(*EntryCache, ec) &&
+        !std::filesystem::create_directories(*EntryCache, ec)) {
+      LogMan::Msg::D("Couldn't create EntryCache directory: '%s'", EntryCache->c_str());
     }
   }
 
+  void ShutdownPaths() {
+    CachePath.reset();
+    EntryCache.reset();
+  }
+
   std::string GetCachePath() {
-    return CachePath;
+    return *CachePath;
   }
 
   std::string GetEntryCachePath() {
-    return EntryCache;
+    return *EntryCache;
   }
 }

External/FEXCore/Source/Common/Paths.h

@@ -3,6 +3,7 @@
 
 namespace FEXCore::Paths {
   void InitializePaths();
+  void ShutdownPaths();
   std::string GetCachePath();
   std::string GetEntryCachePath();
 }

External/FEXCore/Source/Common/SoftFloat-3e/extF80_roundToInt.c

@@ -96,6 +96,7 @@ extFloat80_t
         switch ( roundingMode ) {
          case softfloat_round_near_even:
             if ( !(sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) break;
+            __attribute__((fallthrough));
          case softfloat_round_near_maxMag:
             if ( exp == 0x3FFE ) goto mag1;
             break;

External/FEXCore/Source/Common/SoftFloat.h

@@ -1,4 +1,6 @@
 #pragma once
+
+#include <FEXCore/Utils/BitUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 
 #include <cmath>
@@ -158,18 +160,18 @@ struct X80SoftFloat {
   }
 
   operator float() const {
-    float32_t Result = extF80_to_f32(*this);
-    return *(float*)&Result;
+    const float32_t Result = extF80_to_f32(*this);
+    return FEXCore::BitCast<float>(Result);
   }
 
   operator double() const {
-    float64_t Result = extF80_to_f64(*this);
-    return *(double*)&Result;
+    const float64_t Result = extF80_to_f64(*this);
+    return FEXCore::BitCast<double>(Result);
   }
 
   operator BIGFLOAT() const {
-    float128_t Result = extF80_to_f128(*this);
-    return *(BIGFLOAT*)&Result;
+    const float128_t Result = extF80_to_f128(*this);
+    return FEXCore::BitCast<BIGFLOAT>(Result);
   }
 
   operator int16_t() const {
@@ -196,11 +198,11 @@ struct X80SoftFloat {
   }
 
   void operator=(const float rhs) {
-    *this = f32_to_extF80(*(float32_t*)&rhs);
+    *this = f32_to_extF80(FEXCore::BitCast<float32_t>(rhs));
   }
 
   void operator=(const double rhs) {
-    *this = f64_to_extF80(*(float64_t*)&rhs);
+    *this = f64_to_extF80(FEXCore::BitCast<float64_t>(rhs));
   }
 
   void operator=(const int16_t rhs) {
@@ -226,15 +228,15 @@ struct X80SoftFloat {
   }
 
   X80SoftFloat(const float rhs) {
-    *this = f32_to_extF80(*(float32_t*)&rhs);
+    *this = f32_to_extF80(FEXCore::BitCast<float32_t>(rhs));
   }
 
   X80SoftFloat(const double rhs) {
-    *this = f64_to_extF80(*(float64_t*)&rhs);
+    *this = f64_to_extF80(FEXCore::BitCast<float64_t>(rhs));
   }
 
   X80SoftFloat(BIGFLOAT rhs) {
-    *this = f128_to_extF80(*(float128_t*)&rhs);
+    *this = f128_to_extF80(FEXCore::BitCast<float128_t>(rhs));
   }
 
   X80SoftFloat(const int16_t rhs) {

External/FEXCore/Source/Common/StringConv.h

@@ -38,4 +38,11 @@ namespace FEXCore::StrConv {
     *Result = Value;
     return true;
   }
+  template <typename T,
+    typename = std::enable_if<std::is_enum<T>::value, T>>
+  [[maybe_unused]] static bool Conv(std::string_view Value, T *Result) {
+    *Result = static_cast<T>(std::stoull(std::string(Value), nullptr, 0));
+    return true;
+  }
+
 }

External/FEXCore/Source/Interface/Config/Config.cpp

@@ -4,118 +4,135 @@
 #include "Interface/Context/Context.h"
 
 #include <FEXCore/Config/Config.h>
+#include <filesystem>
+#include <pwd.h>
 #include <map>
+#include <sys/sysinfo.h>
+#include <unistd.h>
 
 namespace FEXCore::Config {
-  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, uint64_t Config) {
-    switch (Option) {
-    case FEXCore::Config::CONFIG_MULTIBLOCK:
-      CTX->Config.Multiblock = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_MAXBLOCKINST:
-      CTX->Config.MaxInstPerBlock = Config;
-    break;
-    case FEXCore::Config::CONFIG_DEFAULTCORE:
-      CTX->Config.Core = static_cast<FEXCore::Config::ConfigCore>(Config);
-    break;
-    case FEXCore::Config::CONFIG_VIRTUALMEMSIZE:
-      CTX->Config.VirtualMemSize = Config;
-    break;
-    case FEXCore::Config::CONFIG_SINGLESTEP:
-      CTX->Config.RunningMode = Config != 0 ? FEXCore::Context::CoreRunningMode::MODE_SINGLESTEP : FEXCore::Context::CoreRunningMode::MODE_RUN;
-    break;
-    case FEXCore::Config::CONFIG_GDBSERVER:
-      Config != 0 ? CTX->StartGdbServer() : CTX->StopGdbServer();
-    break;
-    case FEXCore::Config::CONFIG_IS64BIT_MODE:
-      CTX->Config.Is64BitMode = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_TSO_ENABLED:
-      CTX->Config.TSOEnabled = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_SMC_CHECKS:
-      CTX->Config.SMCChecks = static_cast<FEXCore::Config::ConfigSMCChecks>(Config);
-    break;
-    case FEXCore::Config::CONFIG_ABI_LOCAL_FLAGS:
-      CTX->Config.ABILocalFlags = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_ABI_NO_PF:
-      CTX->Config.ABINoPF = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_VALIDATE_IR_PARSER:
-      CTX->Config.ValidateIRarser = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_AOTIR_GENERATE:
-      CTX->Config.AOTIRCapture = Config != 0;
-    break;
-    case FEXCore::Config::CONFIG_AOTIR_LOAD:
-      CTX->Config.AOTIRLoad = Config != 0;
-    break;
-    default: LogMan::Msg::A("Unknown configuration option");
+  char const* FindUserHomeThroughUID() {
+    auto passwd = getpwuid(geteuid());
+    if (passwd) {
+      return passwd->pw_dir;
     }
+    return nullptr;
+  }
+
+  const char *GetHomeDirectory() {
+    char const *HomeDir = getenv("HOME");
+
+    // Try to get home directory from uid
+    if (!HomeDir) {
+      HomeDir = FindUserHomeThroughUID();
+    }
+
+    // try the PWD
+    if (!HomeDir) {
+      HomeDir = getenv("PWD");
+    }
+
+    // Still doesn't exit? You get local
+    if (!HomeDir) {
+      HomeDir = ".";
+    }
+
+    return HomeDir;
+  }
+
+  std::string GetConfigDirectory(bool Global) {
+    std::string ConfigDir;
+    if (Global) {
+      ConfigDir = GLOBAL_DATA_DIRECTORY;
+    }
+    else {
+      char const *HomeDir = GetHomeDirectory();
+      char const *ConfigXDG = getenv("XDG_CONFIG_HOME");
+      char const *ConfigOverride = getenv("FEX_APP_CONFIG_LOCATION");
+      if (ConfigOverride) {
+        // Config override completely overrides the config directory
+        ConfigDir = ConfigOverride;
+      }
+      else {
+        ConfigDir = ConfigXDG ? ConfigXDG : HomeDir;
+        ConfigDir += "/.fex-emu/";
+      }
+
+      // Ensure the folder structure is created for our configuration
+      std::error_code ec{};
+      if (!std::filesystem::exists(ConfigDir, ec) &&
+          !std::filesystem::create_directories(ConfigDir, ec)) {
+        // Let's go local in this case
+        return "./";
+      }
+    }
+
+    return ConfigDir;
+  }
+
+  std::string GetConfigFileLocation() {
+    std::string ConfigFile{};
+    const char *AppConfig = getenv("FEX_APP_CONFIG");
+    if (AppConfig) {
+      // App config environment variable overwrites only the config file
+      ConfigFile = AppConfig;
+    }
+    else {
+      ConfigFile = GetConfigDirectory(false) + "Config.json";
+    }
+    return ConfigFile;
+  }
+
+  std::string GetApplicationConfig(const std::string &Filename, bool Global) {
+    std::string ConfigFile = GetConfigDirectory(Global);
+
+    std::error_code ec{};
+    if (!Global &&
+        !std::filesystem::exists(ConfigFile, ec) &&
+        !std::filesystem::create_directories(ConfigFile, ec)) {
+      LogMan::Msg::D("Couldn't create config directory: '%s'", ConfigFile.c_str());
+      // Let's go local in this case
+      return "./" + Filename + ".json";
+    }
+
+    ConfigFile += "AppConfig/";
+
+    // Attempt to create the local folder if it doesn't exist
+    if (!Global &&
+        !std::filesystem::exists(ConfigFile, ec) &&
+        !std::filesystem::create_directories(ConfigFile, ec)) {
+      // Let's go local in this case
+      return "./" + Filename + ".json";
+    }
+
+    ConfigFile += Filename + ".json";
+    return ConfigFile;
+  }
+
+  std::string GetDataDirectory() {
+    std::string DataDir{};
+
+    char const *HomeDir = GetHomeDirectory();
+    char const *DataXDG = getenv("XDG_DATA_HOME");
+    char const *DataOverride = getenv("FEX_APP_DATA_LOCATION");
+    if (DataOverride) {
+      // Data override will override the complete directory
+      DataDir = DataOverride;
+    }
+    else {
+      DataDir = DataXDG ?: HomeDir;
+      DataDir += "/.fex-emu/";
+    }
+    return DataDir;
+  }
+
+  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, uint64_t Config) {
   }
 
   void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, std::string const &Config) {
-    switch (Option) {
-    case CONFIG_ROOTFSPATH:
-      CTX->Config.RootFSPath = Config;
-      break;
-    case CONFIG_THUNKLIBSPATH:
-      CTX->Config.ThunkLibsPath = Config;
-      break;
-    case FEXCore::Config::CONFIG_DUMPIR:
-      CTX->Config.DumpIR = Config;
-      break;
-    default: LogMan::Msg::A("Unknown configuration option");
-    }
   }
 
   uint64_t GetConfig(FEXCore::Context::Context *CTX, ConfigOption Option) {
-    switch (Option) {
-    case FEXCore::Config::CONFIG_MULTIBLOCK:
-      return CTX->Config.Multiblock;
-    break;
-    case FEXCore::Config::CONFIG_MAXBLOCKINST:
-      return CTX->Config.MaxInstPerBlock;
-    break;
-    case FEXCore::Config::CONFIG_DEFAULTCORE:
-      return CTX->Config.Core;
-    break;
-    case FEXCore::Config::CONFIG_VIRTUALMEMSIZE:
-      return CTX->Config.VirtualMemSize;
-    break;
-    case FEXCore::Config::CONFIG_SINGLESTEP:
-      return CTX->Config.RunningMode == FEXCore::Context::CoreRunningMode::MODE_SINGLESTEP ? 1 : 0;
-    case FEXCore::Config::CONFIG_GDBSERVER:
-      return CTX->GetGdbServerStatus();
-    break;
-    case FEXCore::Config::CONFIG_IS64BIT_MODE:
-      return CTX->Config.Is64BitMode;
-    break;
-    case FEXCore::Config::CONFIG_TSO_ENABLED:
-      return CTX->Config.TSOEnabled;
-    break;
-    case FEXCore::Config::CONFIG_SMC_CHECKS:
-      return CTX->Config.SMCChecks;
-    break;
-    case FEXCore::Config::CONFIG_ABI_LOCAL_FLAGS:
-      return CTX->Config.ABILocalFlags;
-    break;
-    case FEXCore::Config::CONFIG_ABI_NO_PF:
-      return CTX->Config.ABINoPF;
-    break;
-    case FEXCore::Config::CONFIG_VALIDATE_IR_PARSER:
-      return CTX->Config.ValidateIRarser;
-    break;
-    case FEXCore::Config::CONFIG_AOTIR_GENERATE:
-      return CTX->Config.AOTIRCapture;
-    break;
-    case FEXCore::Config::CONFIG_AOTIR_LOAD:
-      return CTX->Config.AOTIRLoad;
-    break;
-    default: LogMan::Msg::A("Unknown configuration option");
-    }
-
     return 0;
   }
 
@@ -149,6 +166,7 @@ namespace FEXCore::Config {
 
   private:
     void MergeConfigMap(const LayerOptions &Options);
+    void MergeEnvironmentVariables(ConfigOption const &Option, LayerValue const &Value);
   };
 
   void MetaLayer::Load() {
@@ -163,10 +181,56 @@ namespace FEXCore::Config {
     }
   }
 
+
+  void MetaLayer::MergeEnvironmentVariables(ConfigOption const &Option, LayerValue const &Value) {
+    // Environment variables need a bit of additional work
+    // We want to merge the arrays rather than overwrite entirely
+    auto MetaEnvironment = OptionMap.find(Option);
+    if (MetaEnvironment == OptionMap.end()) {
+      // Doesn't exist, just insert
+      OptionMap.insert_or_assign(Option, Value);
+      return;
+    }
+
+    // If an environment variable exists in both current meta and in the incoming layer then the meta layer value is overwritten
+    std::unordered_map<std::string, std::string> LookupMap;
+    const auto AddToMap = [&LookupMap](FEXCore::Config::LayerValue const &Value) {
+      for (const auto &EnvVar : Value) {
+        const auto ItEq = EnvVar.find_first_of('=');
+        if (ItEq == std::string::npos) {
+          // Broken environment variable
+          // Skip
+          continue;
+        }
+        auto Key = std::string(EnvVar.begin(), EnvVar.begin() + ItEq);
+        auto Value = std::string(EnvVar.begin() + ItEq + 1, EnvVar.end());
+
+        // Add the key to the map, overwriting whatever previous value was there
+        LookupMap.insert_or_assign(std::move(Key), std::move(Value));
+      }
+    };
+
+    AddToMap(MetaEnvironment->second);
+    AddToMap(Value);
+
+    // Now with the two layers merged in the map
+    // Add all the values to the option
+    Erase(Option);
+    for (auto &Val : LookupMap) {
+      // Set will emplace multiple options in to its list
+      Set(Option, Val.first + "=" + Val.second);
+    }
+  }
+
   void MetaLayer::MergeConfigMap(const LayerOptions &Options) {
     // Insert this layer's options, overlaying previous options that exist here
     for (auto &it : Options) {
-      OptionMap.insert_or_assign(it.first, it.second);
+      if (it.first == FEXCore::Config::ConfigOption::CONFIG_ENV) {
+        MergeEnvironmentVariables(it.first, it.second);
+      }
+      else {
+        OptionMap.insert_or_assign(it.first, it.second);
+      }
     }
   }
 
@@ -189,8 +253,105 @@ namespace FEXCore::Config {
     }
   }
 
+  std::string ExpandPath(std::string PathName) {
+    if (PathName.empty()) {
+      return {};
+    }
+
+    std::filesystem::path Path{PathName};
+
+    // Expand home if it exists
+    if (Path.is_relative()) {
+      std::string Home = getenv("HOME") ?: "";
+      // Home expansion only works if it is the first character
+      // This matches bash behaviour
+      if (PathName.at(0) == '~') {
+        PathName.replace(0, 1, Home);
+        return PathName;
+      }
+
+      // Expand relative path to absolute
+      Path = std::filesystem::absolute(Path);
+
+      // Only return if it exists
+      std::error_code ec{};
+      if (std::filesystem::exists(Path, ec)) {
+        return Path;
+      }
+    }
+    return {};
+  }
+
   void ReloadMetaLayer() {
     Meta->Load();
+
+    // Do configuration option fix ups after everything is reloaded
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THREADS)) {
+      FEX_CONFIG_OPT(Cores, THREADS);
+      if (Cores == 0) {
+        // When the number of emulated CPU cores is zero then auto detect
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THREADS, std::to_string(get_nprocs_conf()));
+      }
+    }
+
+    auto ExpandPathIfExists = [](FEXCore::Config::ConfigOption Config, std::string PathName) {
+      auto NewPath = ExpandPath(PathName);
+      if (!NewPath.empty()) {
+        FEXCore::Config::EraseSet(Config, NewPath);
+      }
+    };
+
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_ROOTFS)) {
+      FEX_CONFIG_OPT(PathName, ROOTFS);
+      auto ExpandedString = ExpandPath(PathName());
+      if (!ExpandedString.empty()) {
+        // Adjust the path if it ended up being relative
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, ExpandedString);
+      }
+      else if (!PathName().empty()) {
+        // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
+        std::string NamedRootFS = GetDataDirectory() + "RootFS/" + PathName();
+        std::error_code ec{};
+        if (std::filesystem::exists(NamedRootFS, ec)) {
+          FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, NamedRootFS);
+        }
+      }
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKHOSTLIBS)) {
+      FEX_CONFIG_OPT(PathName, THUNKHOSTLIBS);
+      ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKHOSTLIBS, PathName());
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKGUESTLIBS)) {
+      FEX_CONFIG_OPT(PathName, THUNKGUESTLIBS);
+      ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKGUESTLIBS, PathName());
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKCONFIG)) {
+      FEX_CONFIG_OPT(PathName, THUNKCONFIG);
+      auto ExpandedString = ExpandPath(PathName());
+      if (!ExpandedString.empty()) {
+        // Adjust the path if it ended up being relative
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, ExpandedString);
+      }
+      else if (!PathName().empty()) {
+        // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
+        std::string NamedConfig = GetDataDirectory() + "ThunkConfigs/" + PathName();
+        std::error_code ec{};
+        if (std::filesystem::exists(NamedConfig, ec)) {
+          FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, NamedConfig);
+        }
+      }
+    }
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_OUTPUTLOG)) {
+      FEX_CONFIG_OPT(PathName, OUTPUTLOG);
+      if (PathName() != "stdout" && PathName() != "stderr") {
+        ExpandPathIfExists(FEXCore::Config::CONFIG_OUTPUTLOG, PathName());
+      }
+    }
+
+    if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_SINGLESTEP)) {
+      // Single stepping also enforces single instruction size blocks
+      Set(FEXCore::Config::ConfigOption::CONFIG_MAXINST, std::to_string(1u));
+    }
   }
 
   void AddLayer(std::unique_ptr<FEXCore::Config::Layer> _Layer) {
@@ -213,6 +374,10 @@ namespace FEXCore::Config {
     Meta->Set(Option, Data);
   }
 
+  void Erase(ConfigOption Option) {
+    Meta->Erase(Option);
+  }
+
   void EraseSet(ConfigOption Option, std::string Data) {
     Meta->EraseSet(Option, Data);
   }
@@ -252,8 +417,14 @@ namespace FEXCore::Config {
     }
   }
 
-  template bool Value<bool>::GetIfExists(FEXCore::Config::ConfigOption Option, bool Default);
-  template uint8_t Value<uint8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint8_t Default);
+  template bool     Value<bool>::GetIfExists(FEXCore::Config::ConfigOption Option, bool Default);
+  template int8_t   Value<int8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int8_t Default);
+  template uint8_t  Value<uint8_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint8_t Default);
+  template int16_t   Value<int16_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int16_t Default);
+  template uint16_t  Value<uint16_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint16_t Default);
+  template int32_t  Value<int32_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int32_t Default);
+  template uint32_t Value<uint32_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint32_t Default);
+  template int64_t  Value<int64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, int64_t Default);
   template uint64_t Value<uint64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint64_t Default);
 
   // Constructor
@@ -270,5 +441,6 @@ namespace FEXCore::Config {
       *List = **Value;
     }
   }
+  template void Value<std::string>::GetListIfExists(FEXCore::Config::ConfigOption Option, std::list<std::string> *List);
 }
 

External/FEXCore/Source/Interface/Config/Config.json

@@ -0,0 +1,274 @@
+{
+  "Options": {
+    "CPU": {
+      "Core": {
+        "Type": "uint32",
+        "Default": "FEXCore::Config::ConfigCore::CONFIG_IRJIT",
+        "TextDefault": "irjit",
+        "ShortArg": "c",
+        "Choices": [ "irint", "irjit", "host" ],
+        "ArgumentHandler": "CoreHandler",
+        "Desc": [
+          "Which CPU core to use",
+          "host only exists on x86_64",
+          "[irint, irjit, host]"
+        ]
+      },
+      "Multiblock": {
+        "Type": "bool",
+        "Default": "true",
+        "ShortArg": "m",
+        "Desc": [
+          "Controls multiblock code compilation"
+        ]
+      },
+      "MaxInst": {
+        "Type": "int32",
+        "Default": "5000",
+        "ShortArg": "n",
+        "Desc": [
+          "Maximum number of instruction to store in a block"
+        ]
+      },
+      "Threads": {
+        "Type": "uint32",
+        "Default": "1",
+        "ShortArg": "T",
+        "Desc": [
+          "Number of physical hardware threads to tell the process we have.",
+          "0 will auto detect."
+        ]
+      }
+    },
+    "Emulation": {
+      "RootFS": {
+        "Type": "str",
+        "Default": "",
+        "ShortArg": "R",
+        "Desc": [
+          "Which Root filesystem prefix to use",
+          "This can be a filesystem path",
+          "\teg: ~/RootFS/Debian_x86_64",
+          "Or this can be a name of a rootfs",
+          "If the named rootfs exists in the FEX data folder then it will use that one",
+          "\teg: $HOME/.fex-emu/RootFS/<RootFS name>/",
+          "Or if you have XDG_DATA_HOME the config will search in that directory",
+          "\teg: $XDG_DATA_HOME/.fex-emu/RootFS/<RootFS name>/"
+        ]
+      },
+      "ThunkHostLibs": {
+        "Type": "str",
+        "Default": "",
+        "ShortArg": "t",
+        "Desc": [
+          "Folder to find the host-side thunking libraries."
+        ]
+      },
+      "ThunkGuestLibs": {
+        "Type": "str",
+        "Default": "",
+        "ShortArg": "j",
+        "Desc": [
+          "Folder to find the guest-side thunking libraries."
+        ]
+      },
+      "ThunkConfig": {
+        "Type": "str",
+        "Default": "",
+        "ShortArg": "k",
+        "Desc": [
+          "A json file specifying where to overlay the thunks.",
+          "This can be a filesystem path",
+          "\teg: ~/MyThunkConfig.json",
+          "Or this can be a named of a Thunk config file",
+          "If the named config file exists in the FEX data folder folder the it will use that one",
+          "\teg: $HOME/.fex-emu/ThunkConfigs/<ThunkConfig name>",
+          "Or if you have XDG_DATA_HOME the config will search in that directory",
+          "\teg: $XDG_DATA_HOME/.fex-emu/ThunkConfigs/<ThunkConfig name>"
+        ]
+      },
+      "Env": {
+        "Type": "strarray",
+        "Default": "",
+        "ShortArg": "E",
+        "Desc": [
+          "Adds an environment variable to the emulated environment."
+        ]
+      }
+    },
+    "Debug": {
+      "SingleStep": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "S",
+        "Desc": [
+          "Single stepping configuration."
+        ]
+      },
+      "GdbServer": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "G",
+        "Desc": [
+          "Enables the GDB server."
+        ]
+      },
+      "DumpIR": {
+        "Type": "str",
+        "Default": "no",
+        "Desc": [
+          "Folder to dump the IR in to.",
+          "[no, stdout, stderr, <Folder>]"
+        ]
+      },
+      "DumpGPRs": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "g",
+        "Desc": [
+          "When the test harness ends, print the GPR state."
+        ]
+      },
+      "O0": {
+        "Type": "bool",
+        "Default": "false",
+        "ShortArg": "O0",
+        "Desc": [
+          "Disables optimizations passes for debugging."
+        ]
+      },
+      "Force32BitAllocator": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Forces use of the 32-bit allocator on 32-bit applications",
+          "Used to work around ulimit problems of CI runner",
+          "Potentially useful for debugging memory problems",
+          "32-bit allocator is always used if your host kernel is older than 4.17"
+        ]
+      }
+
+    },
+    "Logging": {
+      "SilentLog": {
+        "Type": "bool",
+        "Default": "true",
+        "ShortArg": "s",
+        "Desc": [
+          "Disables logging"
+        ]
+      },
+      "OutputLog": {
+        "Type": "str",
+        "Default": "stderr",
+        "ShortArg": "o",
+        "Desc": [
+          "File to write FEX output to.",
+          "[stdout, stderr, <Filename>]"
+        ]
+      }
+    },
+    "Hacks": {
+      "SMCChecks": {
+        "Type": "uint8",
+        "Default": "FEXCore::Config::CONFIG_SMC_MMAN",
+        "TextDefault": "mman",
+        "ArgumentHandler": "SMCCheckHandler",
+        "Desc": [
+          "Checks code for modification before execution.",
+          "\tnone: No checks",
+          "\tmman: Invalidate on mmap, mprotect, munmap",
+          "\tfull: Validate code before every run (slow)"
+        ]
+      },
+      "TSOEnabled": {
+        "Type": "bool",
+        "Default": "true",
+        "Desc": [
+          "Controls TSO IR ops.",
+          "Highly likely to break any multithreaded application if disabled."
+        ]
+      },
+      "ABILocalFlags": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "When enabled enables an optimization around flags.",
+          "Assumes flags are not used across cals.",
+          "Hand-written assembly can violate this assumption."
+        ]
+      },
+      "ABINoPF": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "When enabled enables an optimization around parity flag calculation.",
+          "Removes the calculation of the parity flag from GPR instructions.",
+          "Assuming no uses rely on it"
+        ]
+      },
+      "ParanoidTSO": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Makes TSO operations even more strict.",
+          "Forces vector loadstores to also become atomic."
+        ]
+      },
+      "StallProcess": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Forces a process to stall out on initialization",
+          "Useful for a process that keeps restarting and doesn't work"
+        ]
+      }
+    },
+    "Misc": {
+      "AOTIRCapture": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Captures IR and generates an AOT IR cache.",
+          "Captures both the loaded executable and libraries it loads."
+        ]
+      },
+      "AOTIRGenerate": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Scans file for executable code and generates an AOT IR cache.",
+          "Does not run the executable."
+        ]
+      },
+      "AOTIRLoad": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Loads an AOT IR cache for the loaded executable."
+        ]
+      }
+    }
+  },
+  "UnnamedOptions": {
+    "Misc": {
+      "IS_INTERPRETER": {
+        "Type": "bool",
+        "Default": "false"
+      },
+      "INTERPRETER_INSTALLED": {
+        "Type": "bool",
+        "Default": "false"
+      },
+      "APP_FILENAME": {
+        "Type": "str",
+        "Default": ""
+      },
+      "IS64BIT_MODE": {
+        "Type": "bool",
+        "Default": "false"
+      }
+    }
+  }
+}
+

External/FEXCore/Source/Interface/Context/Context.cpp

@@ -2,6 +2,7 @@
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Core.h"
 #include "Interface/Core/OpcodeDispatcher.h"
+#include "Interface/Core/X86Tables/X86Tables.h"
 
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CoreState.h>
@@ -14,6 +15,10 @@ namespace FEXCore::Context {
     IR::InstallOpcodeHandlers(Mode);
   }
 
+  void ShutdownStaticTables() {
+    FEXCore::Paths::ShutdownPaths();
+  }
+
   FEXCore::Context::Context *CreateNewContext() {
     return new FEXCore::Context::Context{};
   }
@@ -23,6 +28,9 @@ namespace FEXCore::Context {
   }
 
   void DestroyContext(FEXCore::Context::Context *CTX) {
+    if (CTX->ParentThread) {
+      CTX->DestroyThread(CTX->ParentThread);
+    }
     delete CTX;
   }
 
@@ -30,12 +38,11 @@ namespace FEXCore::Context {
     return CTX->InitCore(Loader);
   }
 
-  void SetExitHandler(FEXCore::Context::Context *CTX,
-      std::function<void(uint64_t ThreadId, FEXCore::Context::ExitReason)> handler) {
-    CTX->CustomExitHandler = handler;
+  void SetExitHandler(FEXCore::Context::Context *CTX, ExitHandler handler) {
+    CTX->CustomExitHandler = std::move(handler);
   }
 
-  std::function<void(uint64_t ThreadId, FEXCore::Context::ExitReason)> GetExitHandler(FEXCore::Context::Context *CTX) {
+  ExitHandler GetExitHandler(FEXCore::Context::Context *CTX) {
     return CTX->CustomExitHandler;
   }
 
@@ -47,6 +54,9 @@ namespace FEXCore::Context {
     CTX->Step();
   }
 
+  void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP) {
+    Thread->CTX->CompileBlock(Thread->CurrentFrame, GuestRIP);
+  }
 
   FEXCore::Context::ExitReason RunUntilExit(FEXCore::Context::Context *CTX) {
     return CTX->RunUntilExit();
@@ -65,11 +75,11 @@ namespace FEXCore::Context {
   }
 
   void GetCPUState(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
-    memcpy(State, &CTX->ParentThread->State.State, sizeof(FEXCore::Core::CPUState));
+    memcpy(State, CTX->ParentThread->CurrentFrame, sizeof(FEXCore::Core::CPUState));
   }
 
   void SetCPUState(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *State) {
-    memcpy(&CTX->ParentThread->State.State, State, sizeof(FEXCore::Core::CPUState));
+    memcpy(CTX->ParentThread->CurrentFrame, State, sizeof(FEXCore::Core::CPUState));
   }
 
   void Pause(FEXCore::Context::Context *CTX) {
@@ -84,10 +94,6 @@ namespace FEXCore::Context {
     CTX->CustomCPUFactory = std::move(Factory);
   }
 
-  void SetFallbackCPUBackendFactory(FEXCore::Context::Context *CTX, CustomCPUFactoryType Factory) {
-    CTX->FallbackCPUFactory = std::move(Factory);
-  }
-
   bool AddVirtualMemoryMapping([[maybe_unused]] FEXCore::Context::Context *CTX, [[maybe_unused]] uint64_t VirtualAddress, [[maybe_unused]] uint64_t PhysicalAddress, [[maybe_unused]] uint64_t Size) {
     return false;
   }
@@ -99,12 +105,12 @@ namespace FEXCore::Context {
     CTX->HandleCallback(RIP);
   }
 
-  void RegisterHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func) {
-      CTX->RegisterHostSignalHandler(Signal, Func);
+  void RegisterHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required) {
+      CTX->RegisterHostSignalHandler(Signal, Func, Required);
   }
 
-  void RegisterFrontendHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func) {
-    CTX->RegisterFrontendHostSignalHandler(Signal, Func);
+  void RegisterFrontendHostSignalHandler(FEXCore::Context::Context *CTX, int Signal, HostSignalDelegatorFunction Func, bool Required) {
+    CTX->RegisterFrontendHostSignalHandler(Signal, Func, Required);
   }
 
   FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Context::Context *CTX, FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID) {
@@ -123,20 +129,12 @@ namespace FEXCore::Context {
     CTX->StopThread(Thread);
   }
 
-  void DeleteForkedThreads(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
-    // This function is called after fork
-    // We need to cleanup some of the thread data that is dead
-    for (auto &DeadThread : CTX->Threads) {
-      if (DeadThread == Thread) {
-        continue;
-      }
+  void DestroyThread(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
+    CTX->DestroyThread(Thread);
+  }
 
-      // Setting running to false ensures that when they are shutdown we won't send signals to kill them
-      DeadThread->State.RunningEvents.Running = false;
-    }
-
-    // We now only have one thread
-    CTX->IdleWaitRefCount = 1;
+  void CleanupAfterFork(FEXCore::Context::Context *CTX, FEXCore::Core::InternalThreadState *Thread) {
+    CTX->CleanupAfterFork(Thread);
   }
 
   void SetSignalDelegator(FEXCore::Context::Context *CTX, FEXCore::SignalDelegator *SignalDelegation) {
@@ -147,16 +145,24 @@ namespace FEXCore::Context {
     CTX->SyscallHandler = Handler;
   }
 
-  FEXCore::CPUID::FunctionResults RunCPUIDFunction(FEXCore::Context::Context *CTX, uint32_t Function, [[maybe_unused]] uint32_t Leaf) {
-    return CTX->CPUID.RunFunction(Function);
+  FEXCore::CPUID::FunctionResults RunCPUIDFunction(FEXCore::Context::Context *CTX, uint32_t Function, uint32_t Leaf) {
+    return CTX->CPUID.RunFunction(Function, Leaf);
   }
 
-  void SetAOTIRLoader(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::istream>(const std::string&)> CacheReader) {
+  void SetAOTIRLoader(FEXCore::Context::Context *CTX, std::function<int(const std::string&)> CacheReader) {
     CTX->AOTIRLoader = CacheReader;
   }
 
-  bool WriteAOTIR(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::ostream>(const std::string&)> CacheWriter) {
-    return CTX->WriteAOTIRCache(CacheWriter);
+  void SetAOTIRWriter(FEXCore::Context::Context *CTX, std::function<std::unique_ptr<std::ostream>(const std::string&)> CacheWriter) {
+    CTX->AOTIRWriter = CacheWriter;
+  }
+
+  void FinalizeAOTIRCache(FEXCore::Context::Context *CTX) {
+    CTX->FinalizeAOTIRCache();
+  }
+
+  void WriteFilesWithCode(FEXCore::Context::Context *CTX, std::function<void(const std::string& fileid, const std::string& filename)> Writer) {
+    CTX->WriteFilesWithCode(Writer);
   }
 
   void AddNamedRegion(FEXCore::Context::Context *CTX, uintptr_t Base, uintptr_t Length, uintptr_t Offset, const std::string& Name) {
@@ -178,10 +184,6 @@ namespace Debug {
     return CTX->GetRuntimeStatsForThread(Thread);
   }
 
-  FEXCore::Core::CPUState GetCPUState(FEXCore::Context::Context *CTX) {
-    return CTX->GetCPUState();
-  }
-
   bool GetDebugDataForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::Core::DebugData *Data) {
     return CTX->GetDebugDataForRIP(RIP, Data);
   }
@@ -198,10 +200,6 @@ namespace Debug {
   // void SetIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList *const ir) {
   //   CTX->SetIRForRIP(RIP, ir);
   // }
-
-  FEXCore::Core::ThreadState *GetThreadState(FEXCore::Context::Context *CTX) {
-    return CTX->GetThreadState();
-  }
 }
 
 }

External/FEXCore/Source/Interface/Context/Context.h

@@ -1,4 +1,5 @@
 #pragma once
+
 #include "Common/JitSymbols.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/Frontend.h"
@@ -9,17 +10,21 @@
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/Event.h>
 #include <stdint.h>
 
-#include <memory>
-#include <map>
-#include <unordered_map>
-#include <set>
-#include <mutex>
-#include <istream>
-#include <ostream>
 #include <functional>
+#include <istream>
+#include <map>
+#include <memory>
+#include <mutex>
+#include <optional>
+#include <ostream>
+#include <set>
+#include <shared_mutex>
+#include <unordered_map>
+#include <queue>
 
 namespace FEXCore {
 class ThunkHandler;
@@ -28,7 +33,8 @@ class GdbServer;
 class SiganlDelegator;
 
 namespace CPU {
-  class JITCore;
+  class Arm64JITCore;
+  class X86JITCore;
 }
 namespace HLE {
 class SyscallHandler;
@@ -50,39 +56,75 @@ namespace FEXCore::Context {
     MODE_SINGLESTEP = 1,
   };
 
+  struct AOTIRInlineEntry {
+    uint64_t GuestHash;
+    uint64_t GuestLength;
+
+    /* RAData followed by IRData */
+    uint8_t InlineData[0];
+
+    IR::RegisterAllocationData *GetRAData();
+    IR::IRListView *GetIRData();
+  };
+
+  struct AOTIRInlineIndexEntry {
+    uint64_t GuestStart;
+    uint64_t DataOffset;
+  };
+
+  struct AOTIRInlineIndex {
+    uint64_t Count;
+    uint64_t DataBase;
+    AOTIRInlineIndexEntry Entries[0];
+
+    AOTIRInlineEntry *Find(uint64_t GuestStart);
+    AOTIRInlineEntry *GetInlineEntry(uint64_t DataOffset);
+  };
+
+  struct AOTIRCaptureCacheEntry {
+    std::unique_ptr<std::ostream> Stream;
+    std::map<uint64_t, uint64_t> Index;
+
+    void AppendAOTIRCaptureCache(uint64_t GuestRIP, uint64_t Start, uint64_t Length, uint64_t Hash, FEXCore::IR::IRListView *IRList, FEXCore::IR::RegisterAllocationData *RAData);
+  };
+
   struct Context {
     friend class FEXCore::HLE::SyscallHandler;
-    friend class FEXCore::CPU::JITCore;
+  #ifdef JIT_ARM64
+    friend class FEXCore::CPU::Arm64JITCore;
+  #endif
+  #ifdef JIT_X86_64
+    friend class FEXCore::CPU::X86JITCore;
+  #endif
+
     friend class FEXCore::IR::Validation::IRValidation;
 
     struct {
-      bool Multiblock {false};
-      bool BreakOnFrontendFailure {true};
-      int64_t MaxInstPerBlock {-1LL};
-      uint64_t VirtualMemSize {1ULL << 36};
       CoreRunningMode RunningMode {CoreRunningMode::MODE_RUN};
-      FEXCore::Config::ConfigCore Core {FEXCore::Config::CONFIG_INTERPRETER};
-      bool GdbServer {false};
-      std::string RootFSPath;
-      std::string ThunkLibsPath;
-
-      bool Is64BitMode {true};
-      bool TSOEnabled {true};
-      FEXCore::Config::ConfigSMCChecks SMCChecks {FEXCore::Config::CONFIG_SMC_MMAN};
-      bool ABILocalFlags {false};
-      bool ABINoPF {false};
-
-      bool AOTIRCapture {false};
-      bool AOTIRLoad {false};
-
-      std::string DumpIR;
+      uint64_t VirtualMemSize{1ULL << 36};
 
       // this is for internal use
       bool ValidateIRarser { false };
 
+      FEX_CONFIG_OPT(Multiblock, MULTIBLOCK);
+      FEX_CONFIG_OPT(SingleStepConfig, SINGLESTEP);
+      FEX_CONFIG_OPT(GdbServer, GDBSERVER);
+      FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
+      FEX_CONFIG_OPT(TSOEnabled, TSOENABLED);
+      FEX_CONFIG_OPT(ABILocalFlags, ABILOCALFLAGS);
+      FEX_CONFIG_OPT(ABINoPF, ABINOPF);
+      FEX_CONFIG_OPT(AOTIRCapture, AOTIRCAPTURE);
+      FEX_CONFIG_OPT(AOTIRGenerate, AOTIRGENERATE);
+      FEX_CONFIG_OPT(AOTIRLoad, AOTIRLOAD);
+      FEX_CONFIG_OPT(SMCChecks, SMCCHECKS);
+      FEX_CONFIG_OPT(Core, CORE);
+      FEX_CONFIG_OPT(MaxInstPerBlock, MAXINST);
+      FEX_CONFIG_OPT(RootFSPath, ROOTFS);
+      FEX_CONFIG_OPT(ThunkHostLibsPath, THUNKHOSTLIBS);
+      FEX_CONFIG_OPT(DumpIR, DUMPIR);
     } Config;
 
-    using IntCallbackReturn =  __attribute__((naked)) void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
+    using IntCallbackReturn =  FEX_NAKED void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
     IntCallbackReturn InterpreterCallbackReturn;
 
     FEXCore::HostFeatures HostFeatures;
@@ -105,30 +147,31 @@ namespace FEXCore::Context {
     std::unique_ptr<FEXCore::ThunkHandler> ThunkHandler;
 
     CustomCPUFactoryType CustomCPUFactory;
-    CustomCPUFactoryType FallbackCPUFactory;
-    std::function<void(uint64_t ThreadId, FEXCore::Context::ExitReason)> CustomExitHandler;
+    FEXCore::Context::ExitHandler CustomExitHandler;
 
     struct AOTIRCacheEntry {
-      uint64_t start;
-      uint64_t len;
-      uint64_t crc;
-      IR::IRListView *IR;
-      IR::RegisterAllocationData *RAData;
+      AOTIRInlineIndex *Array;
+      void *mapping;
+      size_t size;
     };
 
-    std::function<std::unique_ptr<std::istream>(const std::string&)> AOTIRLoader;
-    std::unordered_map<std::string, std::map<uint64_t, AOTIRCacheEntry>> AOTIRCache;
+    std::unordered_map<std::string, AOTIRCacheEntry> AOTIRCache;
+    std::function<int(const std::string&)> AOTIRLoader;
+    std::function<std::unique_ptr<std::ostream>(const std::string&)> AOTIRWriter;
+    std::unordered_map<std::string, AOTIRCaptureCacheEntry> AOTIRCaptureCache;
 
     struct AddrToFileEntry {
       uint64_t Start;
       uint64_t Len;
       uint64_t Offset;
       std::string fileid;
+      std::string filename;
       void *CachedFileEntry;
+      bool ContainsCode;
     };
 
     std::map<uint64_t, AddrToFileEntry> AddrToFile;
-
+    std::map<std::string, std::string> FilesWithCode;
 
 #ifdef BLOCKSTATS
     std::unique_ptr<FEXCore::BlockSamplingData> BlockData;
@@ -142,7 +185,7 @@ namespace FEXCore::Context {
 
     bool InitCore(FEXCore::CodeLoader *Loader);
     FEXCore::Context::ExitReason RunUntilExit();
-    int GetProgramStatus();
+    int GetProgramStatus() const;
     bool IsPaused() const { return !Running; }
     void Pause();
     void Run();
@@ -153,36 +196,58 @@ namespace FEXCore::Context {
     void StopThread(FEXCore::Core::InternalThreadState *Thread);
     void SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event);
 
-    bool GetGdbServerStatus() { return (bool)DebugServer; }
+    bool GetGdbServerStatus() const { return DebugServer != nullptr; }
     void StartGdbServer();
     void StopGdbServer();
     void HandleCallback(uint64_t RIP);
-    void RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func);
-    void RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func);
+    void RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required);
+    void RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required);
 
     static void RemoveCodeEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
 
+    // Wrapper which takes CpuStateFrame instead of InternalThreadState
+    static void RemoveCodeEntryFromJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP) {
+      RemoveCodeEntry(Frame->Thread, GuestRIP);
+    }
+
     // Debugger interface
     void CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
     uint64_t GetThreadCount() const;
     FEXCore::Core::RuntimeStats *GetRuntimeStatsForThread(uint64_t Thread);
-    FEXCore::Core::CPUState GetCPUState();
     bool GetDebugDataForRIP(uint64_t RIP, FEXCore::Core::DebugData *Data);
     bool FindHostCodeForRIP(uint64_t RIP, uint8_t **Code);
 
-    // XXX:
-    // bool FindIRForRIP(uint64_t RIP, FEXCore::IR::IntrusiveIRList **ir);
-    // void SetIRForRIP(uint64_t RIP, FEXCore::IR::IntrusiveIRList *const ir);
-    FEXCore::Core::ThreadState *GetThreadState();
-    void LoadEntryList();
+    struct GenerateIRResult {
+      FEXCore::IR::IRListView* IRList;
+      // User's responsibility to deallocate this.
+      FEXCore::IR::RegisterAllocationData* RAData;
+      uint64_t TotalInstructions;
+      uint64_t TotalInstructionsLength;
+      uint64_t StartAddr;
+      uint64_t Length;
+    };
+    [[nodiscard]] GenerateIRResult GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
 
-    std::tuple<FEXCore::IR::IRListView *, FEXCore::IR::RegisterAllocationData *, uint64_t, uint64_t, uint64_t, uint64_t> GenerateIR(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
+    struct CompileCodeResult {
+      void* CompiledCode;
+      FEXCore::IR::IRListView* IRData;
+      FEXCore::Core::DebugData* DebugData;
+      // User's responsibility to deallocate this.
+      FEXCore::IR::RegisterAllocationData* RAData;
+      bool GeneratedIR;
+      uint64_t StartAddr;
+      uint64_t Length;
+    };
+    [[nodiscard]] CompileCodeResult CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
+    uintptr_t CompileBlock(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);
+    
+    // same as CompileBlock, but aborts on failure
+    void CompileBlockJit(FEXCore::Core::CpuStateFrame *Frame, uint64_t GuestRIP);
 
-    std::tuple<void *, FEXCore::IR::IRListView *, FEXCore::Core::DebugData *, FEXCore::IR::RegisterAllocationData *, bool, uint64_t, uint64_t> CompileCode(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
-    uintptr_t CompileBlock(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestRIP);
-
-    bool LoadAOTIRCache(std::istream &stream);
-    bool WriteAOTIRCache(std::function<std::unique_ptr<std::ostream>(const std::string&)> CacheWriter);
+    bool LoadAOTIRCache(int streamfd);
+    void FinalizeAOTIRCache();
+    void WriteFilesWithCode(std::function<void(const std::string& fileid, const std::string& filename)> Writer);
+    
     // Used for thread creation from syscalls
     void InitializeCompiler(FEXCore::Core::InternalThreadState* State, bool CompileThread);
     FEXCore::Core::InternalThreadState* CreateThread(FEXCore::Core::CPUState *NewThreadState, uint64_t ParentTID);
@@ -191,7 +256,12 @@ namespace FEXCore::Context {
     void CopyMemoryMapping(FEXCore::Core::InternalThreadState *ParentThread, FEXCore::Core::InternalThreadState *ChildThread);
     void RunThread(FEXCore::Core::InternalThreadState *Thread);
 
-    std::vector<FEXCore::Core::InternalThreadState*> *const GetThreads() { return &Threads; }
+    void DestroyThread(FEXCore::Core::InternalThreadState *Thread);
+    void CleanupAfterFork(FEXCore::Core::InternalThreadState *ExceptForThread);
+
+    std::vector<FEXCore::Core::InternalThreadState*>* GetThreads() { return &Threads; }
+
+    uint8_t GetGPRSize() const { return Config.Is64BitMode ? 8 : 4; }
 
     void AddNamedRegion(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const std::string &filename);
     void RemoveNamedRegion(uintptr_t Base, uintptr_t Size);
@@ -200,32 +270,36 @@ namespace FEXCore::Context {
     FEXCore::JITSymbols Symbols;
 #endif
 
+    // Public for threading
+    void ExecutionThread(FEXCore::Core::InternalThreadState *Thread);
+
   protected:
     void ClearCodeCache(FEXCore::Core::InternalThreadState *Thread, bool AlsoClearIRCache);
 
   private:
     void WaitForIdleWithTimeout();
 
-    void ExecutionThread(FEXCore::Core::InternalThreadState *Thread);
     void NotifyPause();
 
     void AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr, uint64_t Start, uint64_t Length);
-
     FEXCore::CodeLoader *LocalLoader{};
 
     // Entry Cache
-    bool GetFilenameHash(std::string const &Filename, std::string &Hash);
-    void AddThreadRIPsToEntryList(FEXCore::Core::InternalThreadState *Thread);
-    void SaveEntryList();
-    std::set<uint64_t> EntryList;
-    std::vector<uint64_t> InitLocations;
     uint64_t StartingRIP;
     std::mutex ExitMutex;
     std::unique_ptr<GdbServer> DebugServer;
 
+    std::shared_mutex AOTIRCacheLock;
+    std::shared_mutex AOTIRCaptureCacheWriteoutLock;
+    std::atomic<bool> AOTIRCaptureCacheWriteoutFlusing;
+
+    std::queue<std::function<void()>> AOTIRCaptureCacheWriteoutQueue;
+    void AOTIRCaptureCacheWriteoutQueue_Flush();
+    void AOTIRCaptureCacheWriteoutQueue_Append(const std::function<void()> &fn);
+
     bool StartPaused = false;
-    FEXCore::Config::Value<std::string> AppFilename{FEXCore::Config::CONFIG_APP_FILENAME, ""};
+    FEX_CONFIG_OPT(AppFilename, APP_FILENAME);
   };
 
-  uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::InternalThreadState *Thread, FEXCore::HLE::SyscallArguments *Args);
+  uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::CpuStateFrame *Frame, FEXCore::HLE::SyscallArguments *Args);
 }

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64.h

@@ -12,6 +12,37 @@ namespace FEXCore::ArchHelpers::Arm64 {
   constexpr uint32_t ATOMIC_MEM_MASK = 0x3B200C00;
   constexpr uint32_t ATOMIC_MEM_INST = 0x38200000;
 
+  constexpr uint32_t LDAXP_MASK = 0xBF'FF'80'00;
+  constexpr uint32_t LDAXP_INST = 0x88'7F'80'00;
+
+  constexpr uint32_t STLXP_MASK = 0xBF'E0'80'00;
+  constexpr uint32_t STLXP_INST = 0x88'20'80'00;
+
+  constexpr uint32_t LDAXR_MASK = 0x3F'FF'FC'00;
+  constexpr uint32_t LDAXR_INST = 0x08'5F'FC'00;
+
+  constexpr uint32_t STLXR_MASK = 0x3F'E0'FC'00;
+  constexpr uint32_t STLXR_INST = 0x08'00'FC'00;
+
+  constexpr uint32_t CBNZ_MASK = 0x7F'00'00'00;
+  constexpr uint32_t CBNZ_INST = 0x35'00'00'00;
+
+  constexpr uint32_t ALU_OP_MASK = 0x7F'00'00'00;
+  constexpr uint32_t ADD_INST    = 0x0B'00'00'00;
+  constexpr uint32_t SUB_INST    = 0x4B'00'00'00;
+  constexpr uint32_t AND_INST    = 0x0A'00'00'00;
+  constexpr uint32_t OR_INST     = 0x2A'00'00'00;
+  constexpr uint32_t EOR_INST    = 0x4A'00'00'00;
+  enum ExclusiveAtomicPairType {
+    TYPE_SWAP,
+    TYPE_ADD,
+    TYPE_SUB,
+    TYPE_AND,
+    TYPE_OR,
+    TYPE_EOR,
+    TYPE_NEG, // This is just a sub with zero. Need to know the differences
+  };
+
   // Load ops are 4 bits
   // Acquire and release bits are independent on the instruction
   constexpr uint32_t ATOMIC_ADD_OP  = 0b0000;
@@ -24,7 +55,28 @@ namespace FEXCore::ArchHelpers::Arm64 {
   constexpr uint32_t ATOMIC_UMIN_OP = 0b0111;
   constexpr uint32_t ATOMIC_SWAP_OP = 0b1000;
 
-  bool HandleCASPAL(void *_mcontext, void *_info, uint32_t Instr);
-  bool HandleCASAL(void *_mcontext, void *_info, uint32_t Instr);
-  bool HandleAtomicMemOp(void *_mcontext, void *_info, uint32_t Instr);
+  constexpr uint32_t REGISTER_MASK = 0b11111;
+  constexpr uint32_t RD_OFFSET = 0;
+  constexpr uint32_t RN_OFFSET = 5;
+  constexpr uint32_t RM_OFFSET = 16;
+
+  inline uint32_t GetRdReg(uint32_t Instr) {
+    return (Instr >> RD_OFFSET) & REGISTER_MASK;
+  }
+
+  inline uint32_t GetRnReg(uint32_t Instr) {
+    return (Instr >> RN_OFFSET) & REGISTER_MASK;
+  }
+
+  inline uint32_t GetRmReg(uint32_t Instr) {
+    return (Instr >> RM_OFFSET) & REGISTER_MASK;
+  }
+
+  bool HandleAtomicLoad(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleAtomicStore(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleAtomicLoad128(void *_ucontext, void *_info, uint32_t Instr);
+  uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info);
+  bool HandleCASPAL(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleCASAL(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr);
 }

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp

@@ -0,0 +1,231 @@
+#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Core/CoreState.h>
+
+#include "aarch64/cpu-aarch64.h"
+
+namespace FEXCore::CPU {
+#define STATE x28
+
+// We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one.
+Arm64Emitter::Arm64Emitter(size_t size) : vixl::aarch64::Assembler(size, vixl::aarch64::PositionDependentCode) {
+  CPU.SetUp();
+
+  auto Features = vixl::CPUFeatures::InferFromOS();
+  SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
+  // RCPC is bugged on Snapdragon 865
+  // Causes glibc cond16 test to immediately throw assert
+  // __pthread_mutex_cond_lock: Assertion `mutex->__data.__owner == 0'
+  SupportsRCPC = false; //Features.Has(vixl::CPUFeatures::Feature::kRCpc);
+
+  if (SupportsAtomics) {
+    // Hypervisor can hide this on the c630?
+    Features.Combine(vixl::CPUFeatures::Feature::kLORegions);
+  }
+
+  SetCPUFeatures(Features);
+
+  if (!SupportsAtomics) {
+    WARN_ONCE("Host CPU doesn't support atomics. Expect bad performance");
+  }
+
+#ifdef _M_ARM_64
+  // We need to get the CPU's cache line size
+  // We expect sane targets that have correct cacheline sizes across clusters
+  uint64_t CTR;
+  __asm volatile ("mrs %[ctr], ctr_el0"
+    : [ctr] "=r"(CTR));
+
+  DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
+  ICacheLineSize = 4 << (CTR & 0xF);
+#endif
+}
+
+void Arm64Emitter::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant) {
+  bool Is64Bit = Reg.IsX();
+  int Segments = Is64Bit ? 4 : 2;
+
+  if (Is64Bit && ((~Constant)>> 16) == 0) {
+    movn(Reg, (~Constant) & 0xFFFF);
+    return;
+  }
+
+  movz(Reg, (Constant) & 0xFFFF, 0);
+  for (int i = 1; i < Segments; ++i) {
+    uint16_t Part = (Constant >> (i * 16)) & 0xFFFF;
+    if (Part) {
+      movk(Reg, Part, i * 16);
+    }
+  }
+}
+
+void Arm64Emitter::PushCalleeSavedRegisters() {
+  // We need to save pairs of registers
+  // We save r19-r30
+  MemOperand PairOffset(sp, -16, PreIndex);
+  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
+    {x19, x20},
+    {x21, x22},
+    {x23, x24},
+    {x25, x26},
+    {x27, x28},
+    {x29, x30},
+  }};
+
+  for (auto &RegPair : CalleeSaved) {
+    stp(RegPair.first, RegPair.second, PairOffset);
+  }
+
+  // Additionally we need to store the lower 64bits of v8-v15
+  // Here's a fun thing, we can use two ST4 instructions to store everything
+  // We just need a single sub to sp before that
+  const std::array<
+    std::tuple<vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister>, 2> FPRs = {{
+    {v8, v9, v10, v11},
+    {v12, v13, v14, v15},
+  }};
+
+  uint32_t VectorSaveSize = sizeof(uint64_t) * 8;
+  sub(sp, sp, VectorSaveSize);
+  // SP supporting move
+  // We just saved x19 so it is safe
+  add(x19, sp, 0);
+
+  MemOperand QuadOffset(x19, 32, PostIndex);
+  for (auto &RegQuad : FPRs) {
+    st4(std::get<0>(RegQuad).D(),
+        std::get<1>(RegQuad).D(),
+        std::get<2>(RegQuad).D(),
+        std::get<3>(RegQuad).D(),
+        0,
+        QuadOffset);
+  }
+}
+
+void Arm64Emitter::PopCalleeSavedRegisters() {
+  const std::array<
+    std::tuple<vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister,
+               vixl::aarch64::VRegister>, 2> FPRs = {{
+    {v12, v13, v14, v15},
+    {v8, v9, v10, v11},
+  }};
+
+  MemOperand QuadOffset(sp, 32, PostIndex);
+  for (auto &RegQuad : FPRs) {
+    ld4(std::get<0>(RegQuad).D(),
+        std::get<1>(RegQuad).D(),
+        std::get<2>(RegQuad).D(),
+        std::get<3>(RegQuad).D(),
+        0,
+        QuadOffset);
+  }
+
+  MemOperand PairOffset(sp, 16, PostIndex);
+  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
+    {x29, x30},
+    {x27, x28},
+    {x25, x26},
+    {x23, x24},
+    {x21, x22},
+    {x19, x20},
+  }};
+
+  for (auto &RegPair : CalleeSaved) {
+    ldp(RegPair.first, RegPair.second, PairOffset);
+  }
+}
+
+
+void Arm64Emitter::SpillStaticRegs() {
+  for (size_t i = 0; i < SRA64.size(); i+=2) {
+      stp(SRA64[i], SRA64[i+1], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+  }
+
+  for (size_t i = 0; i < SRAFPR.size(); i+=2) {
+    stp(SRAFPR[i].Q(), SRAFPR[i+1].Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+  }
+}
+
+void Arm64Emitter::FillStaticRegs() {
+  for (size_t i = 0; i < SRA64.size(); i+=2) {
+    ldp(SRA64[i], SRA64[i+1], MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i])));
+  }
+
+  for (size_t i = 0; i < SRAFPR.size(); i+=2) {
+    ldp(SRAFPR[i].Q(), SRAFPR[i+1].Q(), MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.xmm[i][0])));
+  }
+}
+
+void Arm64Emitter::PushDynamicRegsAndLR() {
+  uint64_t SPOffset = AlignUp((RA64.size() + 1) * 8 + RAFPR.size() * 16, 16);
+
+  sub(sp, sp, SPOffset);
+  int i = 0;
+
+  for (auto RA : RAFPR)
+  {
+    str(RA.Q(), MemOperand(sp, i * 8));
+    i+=2;
+  }
+
+#if 0 // All GPRs should be caller saved
+  for (auto RA : RA64)
+  {
+    str(RA, MemOperand(sp, i * 8));
+    i++;
+  }
+#endif
+
+  str(lr, MemOperand(sp, i * 8));
+}
+
+void Arm64Emitter::PopDynamicRegsAndLR() {
+  uint64_t SPOffset = AlignUp((RA64.size() + 1) * 8 + RAFPR.size() * 16, 16);
+  int i = 0;
+
+  for (auto RA : RAFPR)
+  {
+    ldr(RA.Q(), MemOperand(sp, i * 8));
+    i+=2;
+  }
+
+#if 0 // All GPRs should be caller saved
+  for (auto RA : RA64)
+  {
+    ldr(RA, MemOperand(sp, i * 8));
+    i++;
+  }
+#endif
+
+  ldr(lr, MemOperand(sp, i * 8));
+
+  add(sp, sp, SPOffset);
+}
+
+void Arm64Emitter::ResetStack() {
+  if (SpillSlots == 0)
+    return;
+
+  if (IsImmAddSub(SpillSlots * 16)) {
+    add(sp, sp, SpillSlots * 16);
+  } else {
+   // Too big to fit in a 12bit immediate
+   LoadConstant(x0, SpillSlots * 16);
+   add(sp, sp, x0);
+  }
+}
+
+void Arm64Emitter::Align16B() {
+  uint64_t CurrentOffset = GetBuffer()->GetOffsetAddress<uint64_t>(GetCursorOffset());
+  for (uint64_t i = (16 - (CurrentOffset & 0xF)); i != 0; i -= 4) {
+      nop();
+  }
+}
+
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h

@@ -0,0 +1,77 @@
+#pragma once
+
+#include "aarch64/assembler-aarch64.h"
+#include "aarch64/cpu-aarch64.h"
+
+namespace FEXCore::CPU {
+using namespace vixl;
+using namespace vixl::aarch64;
+
+// All but x29 are caller saved
+const std::array<aarch64::Register, 16> SRA64 = {
+  x4, x5, x6, x7, x8, x9, x10, x11,
+  x12, x18, x17, x16, x15, x14, x13, x29
+};
+
+// All are callee saved
+const std::array<aarch64::Register, 9> RA64 = {
+  x20, x21, x22, x23, x24, x25, x26, x27,
+  x19
+};
+
+const std::array<std::pair<aarch64::Register, aarch64::Register>, 4>  RA64Pair = {{
+  {x20, x21},
+  {x22, x23},
+  {x24, x25},
+  {x26, x27},
+}};
+
+const std::array<std::pair<aarch64::Register, aarch64::Register>, 4> RA32Pair = {{
+  {w20, w21},
+  {w22, w23},
+  {w24, w25},
+  {w26, w27},
+}};
+
+// All are caller saved
+const std::array<aarch64::VRegister, 16> SRAFPR = {
+  v16, v17, v18, v19, v20, v21, v22, v23,
+  v24, v25, v26, v27, v28, v29, v30, v31
+};
+
+//  v8..v15 = (lower 64bits) Callee saved
+const std::array<aarch64::VRegister, 12> RAFPR = {
+/*v0,  v1,  v2,  v3,*/v4,  v5,  v6,  v7,  // v0 ~ v3 are used as temps
+  v8,  v9,  v10, v11, v12, v13, v14, v15
+};
+
+// This class contains common emitter utility functions that can
+// be used by both Arm64 JIT and ARM64 Dispatcher
+class Arm64Emitter : public vixl::aarch64::Assembler {
+protected:
+  Arm64Emitter(size_t size);
+
+  vixl::aarch64::CPU CPU;
+  bool SupportsAtomics{};
+  bool SupportsRCPC{};
+
+  void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant);
+  void SpillStaticRegs();
+  void FillStaticRegs();
+
+  void PushDynamicRegsAndLR();
+  void PopDynamicRegsAndLR();
+
+  void PushCalleeSavedRegisters();
+  void PopCalleeSavedRegisters();
+
+  void ResetStack();
+  void Align16B();
+
+  uint32_t SpillSlots{};
+
+  uint32_t DCacheLineSize{};
+  uint32_t ICacheLineSize{};
+};
+
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64_stubs.cpp

@@ -0,0 +1,26 @@
+#include "Interface/Core/ArchHelpers/Arm64.h"
+
+#include <FEXCore/Utils/LogManager.h>
+
+namespace FEXCore::ArchHelpers::Arm64 {
+
+#ifndef _M_ARM_64
+// These are stub implementations that exist only to allow instantiating the arm64 jit
+// on non arm platforms.
+
+// Obvously such a configuration can't do the actual arm64-specific stuff
+
+bool HandleCASPAL(void *_ucontext, void *_info, uint32_t Instr) {
+    ERROR_AND_DIE("HandleCASPAL Not Implemented");
+}
+
+bool HandleCASAL(void *_ucontext, void *_info, uint32_t Instr) {
+    ERROR_AND_DIE("HandleCASAL Not Implemented");
+}
+
+bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr) {
+    ERROR_AND_DIE("HandleAtomicMemOp Not Implemented");
+}
+#endif
+
+}

External/FEXCore/Source/Interface/Core/ArchHelpers/MContext.h

@@ -0,0 +1,212 @@
+#pragma once
+
+#include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Core/CoreState.h>
+#include <FEXCore/Core/UContext.h>
+
+#include <signal.h>
+#include <string.h>
+#include <ucontext.h>
+#include <stdint.h>
+#include <type_traits>
+
+
+namespace FEXCore::ArchHelpers::Context {
+
+struct X86ContextBackup {
+  // Host State
+  // RIP and RSP is stored in GPRs here
+  uint64_t GPRs[23];
+  FEXCore::x86_64::_libc_fpstate FPRState;
+
+  // Guest state
+  int Signal;
+  FEXCore::Core::CPUState GuestState;
+
+  static constexpr int RedZoneSize = 128;
+};
+
+struct ArmContextBackup {
+  // Host State
+  uint64_t GPRs[31];
+  uint64_t PrevSP;
+  uint64_t PrevPC;
+  uint64_t PState;
+  uint32_t FPSR;
+  uint32_t FPCR;
+  __uint128_t FPRs[32];
+
+  // Guest state
+  int Signal;
+  FEXCore::Core::CPUState GuestState;
+
+  // Arm64 doesn't have a red zone
+  static constexpr int RedZoneSize = 0;
+};
+
+static inline mcontext_t* GetMContext(void* ucontext) {
+  ucontext_t* _context = (ucontext_t*)ucontext;
+  return &_context->uc_mcontext;
+}
+
+
+#ifdef _M_ARM_64
+
+static inline uint64_t GetSp(void* ucontext) {
+  return GetMContext(ucontext)->sp;
+}
+
+static inline uint64_t GetPc(void* ucontext) {
+  return GetMContext(ucontext)->pc;
+}
+
+static inline void SetSp(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->sp = val;
+}
+
+static inline void SetPc(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->pc = val;
+}
+
+static inline uint64_t GetState(void* ucontext) {
+  return GetMContext(ucontext)->regs[28];
+}
+
+static inline void SetState(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->regs[28] = val;
+}
+
+static inline uint64_t GetArmReg(void* ucontext, uint32_t id) {
+  return GetMContext(ucontext)->regs[id];
+}
+
+static inline void SetArmReg(void* ucontext, uint32_t id, uint64_t val) {
+  GetMContext(ucontext)->regs[id] = val;
+}
+
+constexpr uint32_t FPR_MAGIC = 0x46508001U;
+
+struct HostCTXHeader {
+  uint32_t Magic;
+  uint32_t Size;
+};
+
+struct HostFPRState {
+  HostCTXHeader Head;
+  uint32_t FPSR;
+  uint32_t FPCR;
+  __uint128_t FPRs[32];
+};
+
+using ContextBackup = ArmContextBackup;
+template <typename T>
+static inline void BackupContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, ArmContextBackup>::value) {
+    auto _mcontext = GetMContext(ucontext);
+
+    memcpy(&Backup->GPRs[0], &_mcontext->regs[0], 31 * sizeof(uint64_t));
+    Backup->PrevSP = ArchHelpers::Context::GetSp(ucontext);
+    Backup->PrevPC = ArchHelpers::Context::GetPc(ucontext);
+    Backup->PState = _mcontext->pstate;
+
+    // Host FPR state starts at _mcontext->reserved[0];
+    HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
+    LOGMAN_THROW_A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
+    Backup->FPSR = HostState->FPSR;
+    Backup->FPCR = HostState->FPCR;
+    memcpy(&Backup->FPRs[0], &HostState->FPRs[0], 32 * sizeof(__uint128_t));
+  } else {
+      ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+  }
+}
+
+template <typename T>
+static inline void RestoreContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, ArmContextBackup>::value) {
+   auto _mcontext = GetMContext(ucontext);
+
+    HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
+    LOGMAN_THROW_A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
+    memcpy(&HostState->FPRs[0], &Backup->FPRs[0], 32 * sizeof(__uint128_t));
+    HostState->FPCR = Backup->FPCR;
+    HostState->FPSR = Backup->FPSR;
+
+    // Restore GPRs and other state
+    _mcontext->pstate = Backup->PState;
+    ArchHelpers::Context::SetPc(ucontext, Backup->PrevPC);
+    ArchHelpers::Context::SetSp(ucontext, Backup->PrevSP);
+    memcpy(&_mcontext->regs[0], &Backup->GPRs[0], 31 * sizeof(uint64_t));
+  } else {
+      ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+  }
+}
+
+#endif
+
+#ifdef _M_X86_64
+
+static inline uint64_t GetSp(void* ucontext) {
+  return GetMContext(ucontext)->gregs[REG_RSP];
+}
+
+static inline uint64_t GetPc(void* ucontext) {
+  return GetMContext(ucontext)->gregs[REG_RIP];
+  }
+
+static inline void SetSp(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->gregs[REG_RSP] = val;
+}
+
+static inline void SetPc(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->gregs[REG_RIP] = val;
+}
+
+static inline uint64_t GetState(void* ucontext) {
+  return GetMContext(ucontext)->gregs[REG_R14];
+}
+
+static inline void SetState(void* ucontext, uint64_t val) {
+  GetMContext(ucontext)->gregs[REG_R14] = val;
+}
+
+static inline uint64_t GetArmReg(void* ucontext, uint32_t id) {
+  ERROR_AND_DIE("Not impelented for x86 host");
+}
+
+static inline void SetArmReg(void* ucontext, uint32_t id, uint64_t val) {
+  ERROR_AND_DIE("Not impelented for x86 host");
+}
+
+using ContextBackup = X86ContextBackup;
+template <typename T>
+static inline void BackupContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, X86ContextBackup>::value) {
+    auto _mcontext = GetMContext(ucontext);
+
+    // Copy the GPRs
+    memcpy(&Backup->GPRs[0], &_mcontext->gregs[0], sizeof(X86ContextBackup::GPRs));
+    // Copy the FPRState
+    memcpy(&Backup->FPRState, _mcontext->fpregs, sizeof(X86ContextBackup::FPRState));
+    // XXX: Save 256bit and 512bit AVX register state
+  } else {
+    ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+  }
+}
+
+template <typename T>
+static inline void RestoreContext(void* ucontext, T *Backup) {
+  if constexpr (std::is_same<T, X86ContextBackup>::value) {
+    auto _mcontext = GetMContext(ucontext);
+
+    // Copy the GPRs
+    memcpy(&_mcontext->gregs[0], &Backup->GPRs[0], sizeof(X86ContextBackup::GPRs));
+    // Copy the FPRState
+    memcpy(_mcontext->fpregs, &Backup->FPRState, sizeof(X86ContextBackup::FPRState));
+  } else {
+    ERROR_AND_DIE("Wrong context type"); // This must be a runtime error
+  }
+}
+
+#endif
+
+} // namespace FEXCore::ArchHelpers::Context

External/FEXCore/Source/Interface/Core/CPUID.cpp

@@ -1,13 +1,63 @@
+/*
+$info$
+tags: opcodes|cpuid
+desc: Handles presented capability bits for guest cpu
+$end_info$
+*/
+
 #include "Interface/Context/Context.h"
 #include "Interface/Core/CPUID.h"
 #include "git_version.h"
 
 #include <cstring>
+#ifdef _M_X86_64
+#include <cpuid.h>
+#endif
 
 namespace FEXCore {
-//#define CPUID_AMD
+constexpr uint32_t SUPPORTS_AVX = 0;
+// #define CPUID_AMD
+#ifdef CPUID_AMD
+constexpr uint32_t FAMILY_IDENTIFIER =
+  0 |          // Stepping
+  (0xA << 4) | // Model
+  (0xF << 8) | // Family ID
+  (0 << 12) |  // Processor type
+  (0 << 16) |  // Extended model ID
+  (1 << 20);   // Extended family ID
+#else
+constexpr uint32_t FAMILY_IDENTIFIER =
+  0 |          // Stepping
+  (0x7 << 4) |   // Model
+  (0x6 << 8) | // Family ID
+  (0 << 12) |  // Processor type
+  (1 << 16) |  // Extended model ID
+  (0x0 << 20);   // Extended family ID
+#endif
 
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0h() {
+#ifdef _M_ARM_64
+static uint32_t GetCycleCounterFrequency() {
+  uint64_t Result{};
+  __asm("mrs %[Res], CNTFRQ_EL0"
+      : [Res] "=r" (Result));
+  return Result;
+}
+#else
+static uint32_t GetCycleCounterFrequency() {
+  uint32_t eax, ebx, ecx, edx;
+  __cpuid(0, eax, ebx, ecx, edx);
+  if (eax >= 0x15) {
+    __cpuid(0x15, eax, ebx, ecx, edx);
+
+    if (eax && ebx && ecx) {
+      return ecx * ebx / eax;
+    }
+  }
+  return 0;
+}
+#endif
+
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
 
   // EBX, EDX, ECX become the manufacturer id string
@@ -26,29 +76,27 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0h() {
 }
 
 // Processor Info and Features bits
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h() {
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
+  uint32_t CoreCount = Cores();
+
+  Res.eax = FAMILY_IDENTIFIER;
 
-  Res.eax = 0 | // Stepping
-    (0 << 4) | // Model
-    (0xF << 8) | // Family ID
-    (0 << 12) | // Processor type
-    (0 << 16) | // Extended model ID
-    (0 << 20); // Extended family ID
   Res.ebx = 0 | // Brand index
     (8 << 8) | // Cache line size in bytes
-    (8 << 16) | // Number of addressable IDs for the logical cores in the physical CPU
+    (CoreCount << 16) | // Number of addressable IDs for the logical cores in the physical CPU
     (0 << 24); // Local APIC ID
+
   Res.ecx =
     (1 <<  0) | // SSE3
     (0 <<  1) | // PCLMULQDQ
     (1 <<  2) | // DS area supports 64bit layout
     (1 <<  3) | // MWait
-    (1 <<  4) | // DS-CPL
+    (0 <<  4) | // DS-CPL
     (0 <<  5) | // VMX
     (0 <<  6) | // SMX
     (0 <<  7) | // Intel SpeedStep
-    (0 <<  8) | // Thermal Monitor 2
+    (1 <<  8) | // Thermal Monitor 2
     (1 <<  9) | // SSSE3
     (0 << 10) | // L1 context ID
     (0 << 11) | // Silicon debug
@@ -58,8 +106,8 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h() {
     (0 << 15) | // Perfmon and debug capability
     (0 << 16) | // Reserved
     (0 << 17) | // Process-context identifiers
-    (1 << 18) | // Prefetching from memory mapped device
-    (0 << 19) | // SSE4.1
+    (0 << 18) | // Prefetching from memory mapped device
+    (1 << 19) | // SSE4.1
     (0 << 20) | // SSE4.2
     (0 << 21) | // X2APIC
     (1 << 22) | // MOVBE
@@ -68,7 +116,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h() {
     (CTX->HostFeatures.SupportsAES << 25) | // AES
     (0 << 26) | // XSAVE
     (0 << 27) | // OSXSAVE
-    (0 << 28) | // AVX
+    (SUPPORTS_AVX << 28) | // AVX
     (0 << 29) | // F16C
     (0 << 30) | // RDRAND
     (0 << 31);  // Hypervisor always returns zero
@@ -93,7 +141,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h() {
     (1 << 16) | // Page Attribute Table
     (1 << 17) | // 36bit page size extension
     (0 << 18) | // Processor serial number
-    (0 << 19) | // CLFLUSH
+    (1 << 19) | // CLFLUSH
     (0 << 20) | // Reserved
     (0 << 21) | // Debug store
     (0 << 22) | // Thermal monitor and software controled clock
@@ -101,16 +149,16 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h() {
     (1 << 24) | // FXSAVE/FXRSTOR
     (1 << 25) | // SSE
     (1 << 26) | // SSE2
-    (1 << 27) | // Self Snoop
+    (0 << 27) | // Self Snoop
     (1 << 28) | // Max APIC IDs reserved field is valid
     (1 << 29) | // Thermal monitor
     (0 << 30) | // Reserved
-    (1 << 31);  // Pending break enable
+    (0 << 31);  // Pending break enable
   return Res;
 }
 
 // 2: Cache and TLB information
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_02h() {
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_02h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
 
   // returns default values from i7 model 1Ah
@@ -134,125 +182,299 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_02h() {
   return Res;
 }
 
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_06h() {
+// 4: Deterministic cache parameters for each level
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_04h(uint32_t Leaf) {
+  FEXCore::CPUID::FunctionResults Res{};
+  constexpr uint32_t CacheType_Data = 1;
+  constexpr uint32_t CacheType_Instruction = 2;
+  constexpr uint32_t CacheType_Unified = 3;
+
+  if (Leaf == 0) {
+    // Report L1D
+    uint32_t CoreCount = Cores() - 1;
+
+    Res.eax = CacheType_Data | // Cache type
+      (0b001 << 5) |      // Cache level
+      (1 << 8)  |         // Self initializing cache level
+      (0 << 9)  |         // Fully associative
+      (0 << 14) |         // Maximum number of addressable IDs for logical processors sharing this cache (With SMT this would be 1)
+      (CoreCount << 26);  // Maximum number of addressable IDs for processor cores in the physical package
+
+    Res.ebx =
+      (63 << 0) | // Line Size - 1 : Claiming 64 byte
+      (0 << 12) | // Physical Line partitions
+      (7 << 22);  // Associativity - 1 : Claiming 8 way
+
+    // 32KB
+    Res.ecx = 63; // Number of sets - 1 : Claiming 64 sets
+
+    Res.edx =
+      (0 << 0) | // Write-back invalidate
+      (0 << 1) | // Cache inclusiveness - Includes lower caches
+      (0 << 2);  // Complex cache indexing - 0: Direct, 1: Complex
+  }
+  else if (Leaf == 1) {
+    // Report L1I
+    uint32_t CoreCount = Cores() - 1;
+
+    Res.eax = CacheType_Instruction | // Cache type
+      (0b001 << 5) |      // Cache level
+      (1 << 8)  |         // Self initializing cache level
+      (0 << 9)  |         // Fully associative
+      (0 << 14) |         // Maximum number of addressable IDs for logical processors sharing this cache (With SMT this would be 1)
+      (CoreCount << 26); // Maximum number of addressable IDs for processor cores in the physical package
+
+    Res.ebx =
+      (63 << 0) | // Line Size - 1 : Claiming 64 byte
+      (0 << 12) | // Physical Line partitions
+      (7 << 22);  // Associativity - 1 : Claiming 8 way
+
+    // 32KB
+    Res.ecx = 63; // Number of sets - 1 : Claiming 64 sets
+
+    Res.edx =
+      (0 << 0) | // Write-back invalidate
+      (0 << 1) | // Cache inclusiveness - Includes lower caches
+      (0 << 2);  // Complex cache indexing - 0: Direct, 1: Complex
+  }
+  else if (Leaf == 2) {
+    // Report L2
+    uint32_t CoreCount = Cores() - 1;
+
+    Res.eax = CacheType_Unified | // Cache type
+      (0b010 << 5) |      // Cache level
+      (1 << 8)  |         // Self initializing cache level
+      (0 << 9)  |         // Fully associative
+      (0 << 14) |         // Maximum number of addressable IDs for logical processors sharing this cache
+      (CoreCount << 26);  // Maximum number of addressable IDs for processor cores in the physical package
+
+    Res.ebx =
+      (63 << 0) | // Line Size - 1 : Claiming 64 byte
+      (0 << 12) | // Physical Line partitions
+      (7 << 22);  // Associativity - 1 : Claiming 8 way
+
+    // 512KB
+    Res.ecx = 0x3FF; // Number of sets - 1 : Claiming 1024 sets
+
+    Res.edx =
+      (0 << 0) | // Write-back invalidate
+      (0 << 1) | // Cache inclusiveness - Includes lower caches
+      (0 << 2);  // Complex cache indexing - 0: Direct, 1: Complex
+  }
+  else if (Leaf == 3) {
+    // Report L3
+    uint32_t CoreCount = Cores() - 1;
+
+    Res.eax = CacheType_Unified | // Cache type
+      (0b011 << 5) |      // Cache level
+      (1 << 8)  |         // Self initializing cache level
+      (0 << 9)  |         // Fully associative
+      (CoreCount << 14) | // Maximum number of addressable IDs for logical processors sharing this cache
+      (CoreCount << 26);  // Maximum number of addressable IDs for processor cores in the physical package
+
+    Res.ebx =
+      (63 << 0) | // Line Size - 1 : Claiming 64 byte
+      (0 << 12) | // Physical Line partitions
+      (7 << 22);  // Associativity - 1 : Claiming 8 way
+
+    // 8MB
+    Res.ecx = 0x4000; // Number of sets - 1 : Claiming 16384 sets
+
+    Res.edx =
+      (0 << 0) | // Write-back invalidate
+      (0 << 1) | // Cache inclusiveness - Includes lower caches
+      (1 << 2);  // Complex cache indexing - 0: Direct, 1: Complex
+  }
+
+  return Res;
+}
+
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_06h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
   Res.eax = (1 << 2); // Always running APIC
   Res.ecx = (0 << 3); // Intel performance energy bias preference (EPB)
   return Res;
 }
 
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h() {
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
+  if (Leaf == 0) {
+    // Number of subfunctions
+    Res.eax = 0x0;
+    Res.ebx =
+      (1 <<  0) | // FS/GS support
+      (0 <<  1) | // TSC adjust MSR
+      (0 <<  2) | // SGX
+      (0 <<  3) | // BMI1
+      (0 <<  4) | // Intel Hardware Lock Elison
+      (0 <<  5) | // AVX2 support
+      (1 <<  6) | // FPU data pointer updated only on exception
+      (1 <<  7) | // SMEP support
+      (0 <<  8) | // BMI2
+      (0 <<  9) | // Enhanced REP MOVSB/STOSB
+      (1 << 10) | // INVPCID for system software control of process-context
+      (0 << 11) | // Restricted transactional memory
+      (0 << 12) | // Intel resource directory technology Monitoring
+      (1 << 13) | // Deprecates FPU CS and DS
+      (0 << 14) | // Intel MPX
+      (0 << 15) | // Intel Resource Directory Technology Allocation
+      (0 << 16) | // Reserved
+      (0 << 17) | // Reserved
+      (0 << 18) | // RDSEED
+      (0 << 19) | // ADCX and ADOX instructions
+      (0 << 20) | // SMAP Supervisor mode access prevention and CLAC/STAC instructions
+      (0 << 21) | // Reserved
+      (0 << 22) | // Reserved
+      (0 << 23) | // CLFLUSHOPT instruction
+      (0 << 24) | // CLWB instruction
+      (0 << 25) | // Intel processor trace
+      (0 << 26) | // Reserved
+      (0 << 27) | // Reserved
+      (0 << 28) | // Reserved
+      (0 << 29) | // SHA instructions
+      (0 << 30) | // Reserved
+      (0 << 31);  // Reserved
 
-  // Number of subfunctions
-  Res.eax = 0x0;
-  Res.ebx =
-    (1 <<  0) | // FS/GS support
-    (0 <<  1) | // TSC adjust MSR
-    (0 <<  2) | // SGX
-    (0 <<  3) | // BMI1
-    (0 <<  4) | // Intel Hardware Lock Elison
-    (0 <<  5) | // AVX2 support
-    (1 <<  6) | // FPU data pointer updated only on exception
-    (1 <<  7) | // SMEP support
-    (0 <<  8) | // BMI2
-    (0 <<  9) | // Enhanced REP MOVSB/STOSB
-    (1 << 10) | // INVPCID for system software control of process-context
-    (0 << 11) | // Restricted transactional memory
-    (0 << 12) | // Intel resource directory technology Monitoring
-    (1 << 13) | // Deprecates FPU CS and DS
-    (0 << 14) | // Intel MPX
-    (0 << 15) | // Intel Resource Directory Technology Allocation
-    (0 << 16) | // Reserved
-    (0 << 17) | // Reserved
-    (0 << 18) | // RDSEED
-    (0 << 19) | // ADCX and ADOX instructions
-    (0 << 20) | // SMAP Supervisor mode access prevention and CLAC/STAC instructions
-    (0 << 21) | // Reserved
-    (0 << 22) | // Reserved
-    (0 << 23) | // CLFLUSHOPT instruction
-    (0 << 24) | // CLWB instruction
-    (0 << 25) | // Intel processor trace
-    (0 << 26) | // Reserved
-    (0 << 27) | // Reserved
-    (0 << 28) | // Reserved
-    (0 << 29) | // SHA instructions
-    (0 << 30) | // Reserved
-    (0 << 31);  // Reserved
+    Res.ecx =
+      (1 <<  0) | // PREFETCHWT1
+      (0 <<  1) | // AVX512VBMI
+      (0 <<  2) | // Usermode instruction prevention
+      (0 <<  3) | // Protection keys for user mode pages
+      (0 <<  4) | // OS protection keys
+      (0 <<  5) | // waitpkg
+      (0 <<  6) | // AVX512_VBMI2
+      (0 <<  7) | // CET shadow stack
+      (0 <<  8) | // GFNI
+      (0 <<  9) | // VAES
+      (0 << 10) | // VPCLMULQDQ
+      (0 << 11) | // AVX512_VNNI
+      (0 << 12) | // AVX512_BITALG
+      (0 << 13) | // Intel Total Memory Encryption
+      (0 << 14) | // AVX512_VPOPCNTDQ
+      (0 << 15) | // Reserved
+      (0 << 16) | // 5 Level page tables
+      (0 << 17) | // MPX MAWAU
+      (0 << 18) | // MPX MAWAU
+      (0 << 19) | // MPX MAWAU
+      (0 << 20) | // MPX MAWAU
+      (0 << 21) | // MPX MAWAU
+      (0 << 22) | // RDPID Read Processor ID
+      (0 << 23) | // Reserved
+      (0 << 24) | // Reserved
+      (0 << 25) | // CLDEMOTE
+      (0 << 26) | // Reserved
+      (0 << 27) | // MOVDIRI
+      (0 << 28) | // MOVDIR64B
+      (0 << 29) | // Reserved
+      (0 << 30) | // SGX Launch configuration
+      (0 << 31);  // Reserved
 
-  Res.ecx =
-    (1 <<  0) | // PREFETCHWT1
-    (0 <<  1) | // AVX512VBMI
-    (0 <<  2) | // Usermode instruction prevention
-    (0 <<  3) | // Protection keys for user mode pages
-    (1 <<  4) | // OS protection keys
-    (0 <<  5) | // waitpkg
-    (0 <<  6) | // AVX512_VBMI2
-    (0 <<  7) | // CET shadow stack
-    (0 <<  8) | // GFNI
-    (0 <<  9) | // VAES
-    (0 << 10) | // VPCLMULQDQ
-    (0 << 11) | // AVX512_VNNI
-    (0 << 12) | // AVX512_BITALG
-    (0 << 13) | // Intel Total Memory Encryption
-    (0 << 14) | // AVX512_VPOPCNTDQ
-    (0 << 15) | // Reserved
-    (0 << 16) | // 5 Level page tables
-    (0 << 17) | // MPX MAWAU
-    (0 << 18) | // MPX MAWAU
-    (0 << 19) | // MPX MAWAU
-    (0 << 20) | // MPX MAWAU
-    (0 << 21) | // MPX MAWAU
-    (0 << 22) | // RDPID Read Processor ID
-    (0 << 23) | // Reserved
-    (0 << 24) | // Reserved
-    (0 << 25) | // CLDEMOTE
-    (0 << 26) | // Reserved
-    (0 << 27) | // MOVDIRI
-    (0 << 28) | // MOVDIR64B
-    (0 << 29) | // Reserved
-    (0 << 30) | // SGX Launch configuration
-    (0 << 31);  // Reserved
-
-  Res.edx =
-    (0 <<  0) | // Reserved
-    (0 <<  1) | // Reserved
-    (0 <<  2) | // AVX512_4VNNIW
-    (0 <<  3) | // AVX512_4FMAPS
-    (0 <<  4) | // Fast Short Rep Mov
-    (0 <<  5) | // Reserved
-    (0 <<  6) | // Reserved
-    (0 <<  7) | // Reserved
-    (0 <<  8) | // AVX512_VP2INTERSECT
-    (0 <<  9) | // Reserved
-    (0 << 10) | // VERW clears CPU buffers
-    (0 << 11) | // Reserved
-    (0 << 12) | // Reserved
-    (0 << 13) | // Reserved
-    (0 << 14) | // SERIALIZE instruction
-    (0 << 15) | // Reserved
-    (0 << 16) | // Reserved
-    (0 << 17) | // Reserved
-    (0 << 18) | // Intel PCONFIG
-    (0 << 19) | // Intel Architectural LBR
-    (0 << 20) | // Intel CET
-    (0 << 21) | // Reserved
-    (0 << 22) | // Reserved
-    (0 << 23) | // Reserved
-    (0 << 24) | // Reserved
-    (0 << 25) | // Reserved
-    (0 << 26) | // Reserved
-    (0 << 27) | // Reserved
-    (0 << 28) | // L1D Flush
-    (0 << 29) | // Arch capabilities
-    (0 << 30) | // Reserved
-    (0 << 31);  // Reserved
+    Res.edx =
+      (0 <<  0) | // Reserved
+      (0 <<  1) | // Reserved
+      (0 <<  2) | // AVX512_4VNNIW
+      (0 <<  3) | // AVX512_4FMAPS
+      (0 <<  4) | // Fast Short Rep Mov
+      (0 <<  5) | // Reserved
+      (0 <<  6) | // Reserved
+      (0 <<  7) | // Reserved
+      (0 <<  8) | // AVX512_VP2INTERSECT
+      (0 <<  9) | // Reserved
+      (0 << 10) | // VERW clears CPU buffers
+      (0 << 11) | // Reserved
+      (0 << 12) | // Reserved
+      (0 << 13) | // Reserved
+      (0 << 14) | // SERIALIZE instruction
+      (0 << 15) | // Reserved
+      (0 << 16) | // Reserved
+      (0 << 17) | // Reserved
+      (0 << 18) | // Intel PCONFIG
+      (0 << 19) | // Intel Architectural LBR
+      (0 << 20) | // Intel CET
+      (0 << 21) | // Reserved
+      (0 << 22) | // Reserved
+      (0 << 23) | // Reserved
+      (0 << 24) | // Reserved
+      (0 << 25) | // Reserved
+      (0 << 26) | // Reserved
+      (0 << 27) | // Reserved
+      (0 << 28) | // L1D Flush
+      (0 << 29) | // Arch capabilities
+      (0 << 30) | // Reserved
+      (0 << 31);  // Reserved
+  }
 
   return Res;
 }
 
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0Dh(uint32_t Leaf) {
+  // Leaf 0
+  FEXCore::CPUID::FunctionResults Res{};
+
+  uint32_t XFeatureSupportedSizeMax = SUPPORTS_AVX ? 0x0000'0340 : 0x0000'0240; // XFeatureEnabledSizeMax: Legacy Header + FPU/SSE + AVX
+  if (Leaf == 0) {
+    // XFeatureSupportedMask[31:0]
+    Res.eax =
+      (1 << 0) |            // X87 support
+      (1 << 1) |            // 128-bit SSE support
+      (SUPPORTS_AVX << 2) | // 256-bit AVX support
+      (0b00 << 3) |         // MPX State
+      (0b000 << 5) |        // AVX-512 state
+      (0 << 8) |            // "Used for IA32_XSS" ... Used for what?
+      (0 << 9);             // PKRU state
+
+    // EBX and ECX doesn't need to match if a feature is supported but not enabled
+    Res.ebx = XFeatureSupportedSizeMax;
+    Res.ecx = XFeatureSupportedSizeMax; // XFeatureSupportedSizeMax: Size in bytes of XSAVE/XRSTOR area
+
+    // XFeatureSupportedMask[63:32]
+    Res.edx = 0; // Upper 32-bits of XFeatureSupportedMask
+  }
+  else if (Leaf == 1) {
+    Res.eax =
+      (0 << 0) | // XSAVEOPT
+      (0 << 1) | // XSAVEC (and XRSTOR)
+      (0 << 2) | // XGETBV - XGETBV with ECX=1 supported
+      (0 << 3);  // XSAVES - XSAVES, XRSTORS, and IA32_XSS supported
+
+    // Same information as Leaf 0 for ebx
+    Res.ebx = XFeatureSupportedSizeMax;
+
+    // Lower supported 32bits of IA32_XSS MSR. IA32_XSS[n] can only be set to 1 if ECX[n] is 1
+    Res.ecx =
+      (0b0000'0000 << 0) | // Used for XCR0
+      (0 << 8) |           // PT state
+      (0 << 9);            // Used for XCR0
+
+    // Upper supported 32bits of IA32_XSS MSR. IA32_XSS[n+32] can only be set to 1 if EDX[n] is 1
+    // Entirely reserved atm
+    Res.edx = 0;
+  }
+  else if (Leaf == 2) {
+    Res.eax = SUPPORTS_AVX ? 0x0000'0100 : 0; // YmmSaveStateSize
+    Res.ebx = SUPPORTS_AVX ? 0x0000'0240 : 0; // YmmSaveStateOffset
+
+    // Reserved
+    Res.ecx = 0;
+    Res.edx = 0;
+  }
+  return Res;
+}
+
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_15h(uint32_t Leaf) {
+  FEXCore::CPUID::FunctionResults Res{};
+  // TSC frequency = ECX * EBX / EAX
+  uint32_t FrequencyHz = GetCycleCounterFrequency();
+  if (FrequencyHz) {
+    Res.eax = 1;
+    Res.ebx = 1;
+    Res.ecx = FrequencyHz;
+  }
+  return Res;
+}
+
 // Highest extended function implemented
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0000h() {
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0000h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
   Res.eax = 0x8000001F;
 
@@ -271,15 +493,10 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0000h() {
 }
 
 // Extended processor and feature bits
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h() {
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
 
-  Res.eax = 0 | // Stepping
-    (0 << 4) | // Model
-    (0 << 8) | // Family ID
-    (0 << 12) | // Processor type
-    (0 << 16) | // Extended model ID
-    (0 << 20); // Extended family ID
+  Res.eax = FAMILY_IDENTIFIER;
 
   Res.ecx =
     (1 <<  0) | // LAHF/SAHF
@@ -304,13 +521,13 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h() {
     (0 << 19) | // Reserved
     (0 << 20) | // Reserved
     (0 << 21) | // Reserved
-    (1 << 22) | // Topology extensions support
-    (1 << 23) | // Core performance counter extensions
-    (1 << 24) | // NB performance counter extensions
+    (0 << 22) | // Topology extensions support
+    (0 << 23) | // Core performance counter extensions
+    (0 << 24) | // NB performance counter extensions
     (0 << 25) | // Reserved
     (0 << 26) | // Data breakpoints extensions
-    (1 << 27) | // Performance TSC
-    (1 << 28) | // L2 perf counter extensions
+    (0 << 27) | // Performance TSC
+    (0 << 28) | // L2 perf counter extensions
     (0 << 29) | // Reserved
     (0 << 30) | // Reserved
     (0 << 31);  // Reserved
@@ -342,7 +559,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h() {
     (1 << 23) | // MMX
     (1 << 24) | // FXSAVE/FXRSTOR
     (1 << 25) | // FXSAVE/FXRSTOR Optimizations
-    (1 << 26) | // 1 gigabit pages
+    (0 << 26) | // 1 gigabit pages
     (0 << 27) | // RDTSCP
     (0 << 28) | // Reserved
     (1 << 29) | // Long Mode
@@ -357,82 +574,312 @@ constexpr char ProcessorBrand[48] = {
 };
 
 //Processor brand string
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0002h() {
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0002h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
   memcpy(&Res, &ProcessorBrand[0], sizeof(FEXCore::CPUID::FunctionResults));
   return Res;
 }
 
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0003h() {
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0003h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
   memcpy(&Res, &ProcessorBrand[16], sizeof(FEXCore::CPUID::FunctionResults));
   return Res;
 }
 
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0004h() {
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0004h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
   memcpy(&Res, &ProcessorBrand[32], sizeof(FEXCore::CPUID::FunctionResults));
   return Res;
 }
 
-// Advanced power management
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0007h() {
+// L1 Cache and TLB identifiers
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0005h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
-  Res.eax = (1 << 2); // APIC timer not affected by p-state
+
+  // L1 TLB Information for 2MB and 4MB pages
+  Res.eax =
+    (64 << 0)  | // Number of TLB instruction entries
+    (255 << 8) | // instruction TLB associativity type (full)
+    (64 << 16) | // Number of TLB data entries
+    (255 << 24); // data TLB associativity type (full)
+
+  // L1 TLB Information for 4KB pages
+  Res.ebx =
+    (64 << 0)  | // Number of TLB instruction entries
+    (255 << 8) | // instruction TLB associativity type (full)
+    (64 << 16) | // Number of TLB data entries
+    (255 << 24); // data TLB associativity type (full)
+
+  // L1 data cache identifiers
+  Res.ecx =
+    (64 << 0) | // L1 data cache size line in bytes
+    (1 << 8)  | // L1 data cachelines per tag
+    (8 << 16) | // L1 data cache associativity
+    (32 << 24); // L1 data cache size in KB
+
+  // L1 instruction cache identifiers
+  Res.edx =
+    (64 << 0) | // L1 instruction cache line size in bytes
+    (1 << 8)  | // L1 instruction cachelines per tag
+    (4 << 16) | // L1 instruction cache associativity
+    (64 << 24); // L1 instruction cache size in KB
+
   return Res;
 }
 
-FEXCore::CPUID::FunctionResults CPUIDEmu::Function_Reserved() {
+// L2 Cache identifiers
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0006h(uint32_t Leaf) {
+  FEXCore::CPUID::FunctionResults Res{};
+
+  // L2 TLB Information for 2MB and 4MB pages
+  Res.eax =
+    (1024 << 0)  | // Number of TLB instruction entries
+    (6 << 12)    | // instruction TLB associativity type
+    (1536 << 16) | // Number of TLB data entries
+    (3 << 28);     // data TLB associativity type
+
+  // L2 TLB Information for 4KB pages
+  Res.ebx =
+    (1024 << 0)  | // Number of TLB instruction entries
+    (6 << 12)    | // instruction TLB associativity type
+    (1536 << 16) | // Number of TLB data entries
+    (5 << 28);     // data TLB associativity type
+
+  // L2 cache identifiers
+  Res.ecx =
+    (64 << 0) |  // cacheline size
+    (1 << 8)  |  // cachelines per tag
+    (6 << 12) |  // cache associativity
+    (512 << 16); // L2 cache size in KB
+
+  // L3 cache identifiers
+  Res.edx =
+    (64 << 0) | // cacheline size
+    (1 << 8)  | // cachelines per tag
+    (6 << 12) | // cache associativity
+    (16 << 18); // L2 cache size in KB
+  return Res;
+}
+
+// Advanced power management
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0007h(uint32_t Leaf) {
+  FEXCore::CPUID::FunctionResults Res{};
+  Res.eax = (1 << 2); // APIC timer not affected by p-state
+  Res.edx =
+    (1 << 8); // Invariant TSC
+  return Res;
+}
+
+// Virtual and physical address sizes
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0008h(uint32_t Leaf) {
+  FEXCore::CPUID::FunctionResults Res{};
+  Res.eax =
+    (48 << 0) | // PhysAddrSize = 48-bit
+    (48 << 8) | // LinAddrSize = 48-bit
+    (0 << 16); // GuestPhysAddrSize == PhysAddrSize
+
+  Res.ebx =
+    (0 << 2) | // XSaveErPtr: Saving and restoring error pointers
+    (0 << 1) | // IRPerf: Instructions retired count support
+    (0 << 0);  // CLZERO support
+
+  uint32_t CoreCount = Cores() - 1;
+  Res.ecx =
+    (0 << 16) |       // PerfTscSize: Performance timestamp count size
+    ((uint32_t)std::log2(CoreCount + 1) << 12) |       // ApicIdSize: Number of bits in ApicID
+    (CoreCount << 0); // Count count subtract one
+
+  return Res;
+}
+
+// TLB 1GB page identifiers
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0019h(uint32_t Leaf) {
+  FEXCore::CPUID::FunctionResults Res{};
+  Res.eax =
+    (0xF << 28) | // L1 DTLB associativity for 1GB pages
+    (64 << 16) |  // L1 DTLB entry count for 1GB pages
+    (0xF << 12) | // L1 ITLB associativity for 1GB pages
+    (64 << 0);    // L1 ITLB entry count for 1GB pages
+
+  Res.ebx =
+    (0 << 28) | // L2 DTLB associativity for 1GB pages
+    (0 << 16) | // L2 DTLB entry count for 1GB pages
+    (0 << 12) | // L2 ITLB associativity for 1GB pages
+    (0 << 0);   // L2 ITLB entry count for 1GB pages
+  return Res;
+}
+
+// Deterministic cache parameters for each level
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_001Dh(uint32_t Leaf) {
+  // This is nearly a copy of CPUID function 4h
+  // There are some minor changes though
+
+  FEXCore::CPUID::FunctionResults Res{};
+  constexpr uint32_t CacheType_Data = 1;
+  constexpr uint32_t CacheType_Instruction = 2;
+  constexpr uint32_t CacheType_Unified = 3;
+
+  if (Leaf == 0) {
+    // Report L1D
+    Res.eax = CacheType_Data | // Cache type
+      (0b001 << 5) |      // Cache level
+      (1 << 8)  |         // Self initializing cache level
+      (0 << 9)  |         // Fully associative
+      (0 << 14);          // Maximum number of addressable IDs for logical processors sharing this cache (With SMT this would be 1)
+
+    Res.ebx =
+      (63 << 0) | // Line Size - 1 : Claiming 64 byte
+      (0 << 12) | // Physical Line partitions
+      (7 << 22);  // Associativity - 1 : Claiming 8 way
+
+    // 32KB
+    Res.ecx = 63; // Number of sets - 1 : Claiming 64 sets
+
+    Res.edx =
+      (0 << 0) | // Write-back invalidate
+      (0 << 1);  // Cache inclusiveness - Includes lower caches
+  }
+  else if (Leaf == 1) {
+    // Report L1I
+    Res.eax = CacheType_Instruction | // Cache type
+      (0b001 << 5) |      // Cache level
+      (1 << 8)  |         // Self initializing cache level
+      (0 << 9)  |         // Fully associative
+      (0 << 14);          // Maximum number of addressable IDs for logical processors sharing this cache (With SMT this would be 1)
+
+    Res.ebx =
+      (63 << 0) | // Line Size - 1 : Claiming 64 byte
+      (0 << 12) | // Physical Line partitions
+      (7 << 22);  // Associativity - 1 : Claiming 8 way
+
+    // 32KB
+    Res.ecx = 63; // Number of sets - 1 : Claiming 64 sets
+
+    Res.edx =
+      (0 << 0) | // Write-back invalidate
+      (0 << 1);  // Cache inclusiveness - Includes lower caches
+  }
+  else if (Leaf == 2) {
+    // Report L2
+    Res.eax = CacheType_Unified | // Cache type
+      (0b010 << 5) |      // Cache level
+      (1 << 8)  |         // Self initializing cache level
+      (0 << 9)  |         // Fully associative
+      (0 << 14);          // Maximum number of addressable IDs for logical processors sharing this cache
+
+    Res.ebx =
+      (63 << 0) | // Line Size - 1 : Claiming 64 byte
+      (0 << 12) | // Physical Line partitions
+      (7 << 22);  // Associativity - 1 : Claiming 8 way
+
+    // 512KB
+    Res.ecx = 0x3FF; // Number of sets - 1 : Claiming 1024 sets
+
+    Res.edx =
+      (0 << 0) | // Write-back invalidate
+      (0 << 1);  // Cache inclusiveness - Includes lower caches
+  }
+  else if (Leaf == 3) {
+    // Report L3
+    uint32_t CoreCount = Cores() - 1;
+
+    Res.eax = CacheType_Unified | // Cache type
+      (0b011 << 5) |      // Cache level
+      (1 << 8)  |         // Self initializing cache level
+      (0 << 9)  |         // Fully associative
+      (CoreCount << 14);  // Maximum number of addressable IDs for logical processors sharing this cache
+
+    Res.ebx =
+      (63 << 0) | // Line Size - 1 : Claiming 64 byte
+      (0 << 12) | // Physical Line partitions
+      (7 << 22);  // Associativity - 1 : Claiming 8 way
+
+    // 8MB
+    Res.ecx = 0x4000; // Number of sets - 1 : Claiming 16384 sets
+
+    Res.edx =
+      (0 << 0) | // Write-back invalidate
+      (0 << 1);  // Cache inclusiveness - Includes lower caches
+  }
+
+  return Res;
+}
+
+FEXCore::CPUID::FunctionResults CPUIDEmu::Function_Reserved(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
   return Res;
 }
 
 void CPUIDEmu::Init(FEXCore::Context::Context *ctx) {
   CTX = ctx;
-  RegisterFunction(0, std::bind(&CPUIDEmu::Function_0h, this));
-  RegisterFunction(1, std::bind(&CPUIDEmu::Function_01h, this));
-  RegisterFunction(2, std::bind(&CPUIDEmu::Function_02h, this));
+  using namespace std::placeholders;
+  RegisterFunction(0, std::bind(&CPUIDEmu::Function_0h, this, _1));
+  RegisterFunction(1, std::bind(&CPUIDEmu::Function_01h, this, _1));
+  RegisterFunction(2, std::bind(&CPUIDEmu::Function_02h, this, _1));
   // 3: Serial Number(previously), now reserved
-  // 4: Deterministic cache parameters for each level
+#ifndef CPUID_AMD
+  // Deterministic cache parameters for each level
+  RegisterFunction(0x4, std::bind(&CPUIDEmu::Function_04h, this, _1));
+#endif
   // 5: Monitor/mwait
   // Thermal and power management
-  RegisterFunction(6, std::bind(&CPUIDEmu::Function_06h, this));
+  RegisterFunction(6, std::bind(&CPUIDEmu::Function_06h, this, _1));
   // Extended feature flags
-  RegisterFunction(7, std::bind(&CPUIDEmu::Function_07h, this));
+  RegisterFunction(7, std::bind(&CPUIDEmu::Function_07h, this, _1));
   // 9: Direct Cache Access information
   // 0x0A: Architectural performance monitoring
   // 0x0B: Extended topology enumeration
   // 0x0D: Processor extended state enumeration
+  RegisterFunction(0x0D, std::bind(&CPUIDEmu::Function_0Dh, this, _1));
   // 0x0F: Intel RDT monitoring
   // 0x10: Intel RDT allocation enumeration
   // 0x12: Intel SGX capability enumeration
   // 0x13: Reserved
   // 0x14: Intel Processor trace
-  // 0x15: Timestamp counter information
+#ifndef CPUID_AMD
+  // Timestamp counter information
+  // Doesn't exist on AMD hardware
+  RegisterFunction(0x15, std::bind(&CPUIDEmu::Function_15h, this, _1));
+#endif
   // 0x16: Processor frequency information
   // 0x17: SoC vendor attribute enumeration
 
   // Largest extended function number
-  RegisterFunction(0x8000'0000, std::bind(&CPUIDEmu::Function_8000_0000h, this));
+  RegisterFunction(0x8000'0000, std::bind(&CPUIDEmu::Function_8000_0000h, this, _1));
   // Processor vendor
-  RegisterFunction(0x8000'0001, std::bind(&CPUIDEmu::Function_8000_0001h, this));
+  RegisterFunction(0x8000'0001, std::bind(&CPUIDEmu::Function_8000_0001h, this, _1));
   // Processor brand string
-  RegisterFunction(0x8000'0002, std::bind(&CPUIDEmu::Function_8000_0002h, this));
+  RegisterFunction(0x8000'0002, std::bind(&CPUIDEmu::Function_8000_0002h, this, _1));
   // Processor brand string continued
-  RegisterFunction(0x8000'0003, std::bind(&CPUIDEmu::Function_8000_0003h, this));
+  RegisterFunction(0x8000'0003, std::bind(&CPUIDEmu::Function_8000_0003h, this, _1));
   // Processor brand string continued
-  RegisterFunction(0x8000'0004, std::bind(&CPUIDEmu::Function_8000_0004h, this));
+  RegisterFunction(0x8000'0004, std::bind(&CPUIDEmu::Function_8000_0004h, this, _1));
   // 0x8000'0005: L1 Cache and TLB identifiers
+#ifdef CPUID_AMD
+  RegisterFunction(0x8000'0005, std::bind(&CPUIDEmu::Function_8000_0005h, this, _1));
+#else
+  // This is full reserved on Intel platforms
+  RegisterFunction(0x8000'0005, std::bind(&CPUIDEmu::Function_Reserved, this, _1));
+#endif
   // 0x8000'0006: L2 Cache identifiers
+  RegisterFunction(0x8000'0006, std::bind(&CPUIDEmu::Function_8000_0006h, this, _1));
   // Advanced power management information
-  RegisterFunction(0x8000'0007, std::bind(&CPUIDEmu::Function_8000_0007h, this));
-  // 0x8000'0008: Virtual and physical address sizes
+  RegisterFunction(0x8000'0007, std::bind(&CPUIDEmu::Function_8000_0007h, this, _1));
+  // Virtual and physical address sizes
+  RegisterFunction(0x8000'0008, std::bind(&CPUIDEmu::Function_8000_0008h, this, _1));
+
   // 0x8000'000A: SVM Revision
-  // 0x8000'0019: TLB 1GB page identifiers
+  // TLB 1GB page identifiers
+  RegisterFunction(0x8000'0019, std::bind(&CPUIDEmu::Function_8000_0019h, this, _1));
+
   // 0x8000'001A: Performance optimization identifiers
   // 0x8000'001B: Instruction based sampling identifiers
   // 0x8000'001C: Lightweight profiling capabilities
   // 0x8000'001D: Cache properties
+#ifdef CPUID_AMD
+  // Deterministic cache parameters for each level
+  RegisterFunction(0x8000'001D, std::bind(&CPUIDEmu::Function_8000_001Dh, this, _1));
+#endif
   // 0x8000'001E: Extended APIC ID
   // 0x8000'001F: AMD Secure Encryption
 }

External/FEXCore/Source/Interface/Core/CPUID.h

@@ -3,6 +3,7 @@
 #include <unordered_map>
 
 #include <FEXCore/Core/CPUID.h>
+#include <FEXCore/Config/Config.h>
 #include <FEXCore/Utils/LogManager.h>
 
 namespace FEXCore {
@@ -23,22 +24,20 @@ private:
 public:
   void Init(FEXCore::Context::Context *ctx);
 
-  FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function) {
+  FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function, uint32_t Leaf) {
     auto Handler = FunctionHandlers.find(Function);
 
     if (Handler == FunctionHandlers.end()) {
-      #ifndef NDEBUG
-        LogMan::Msg::E("Unhandled CPU ID function, 0x%x", Function);
-      #endif
-      return Function_Reserved();
+      return Function_Reserved(Leaf);
     }
 
-    return Handler->second();
+    return Handler->second(Leaf);
   }
 private:
   FEXCore::Context::Context *CTX;
+  FEX_CONFIG_OPT(Cores, THREADS);
 
-  using FunctionHandler = std::function<FEXCore::CPUID::FunctionResults()>;
+  using FunctionHandler = std::function<FEXCore::CPUID::FunctionResults(uint32_t Leaf)>;
   void RegisterFunction(uint32_t Function, FunctionHandler Handler) {
     FunctionHandlers[Function] = Handler;
   }
@@ -46,18 +45,26 @@ private:
   std::unordered_map<uint32_t, FunctionHandler> FunctionHandlers;
 
   // Functions
-  FEXCore::CPUID::FunctionResults Function_0h();
-  FEXCore::CPUID::FunctionResults Function_01h();
-  FEXCore::CPUID::FunctionResults Function_02h();
-  FEXCore::CPUID::FunctionResults Function_06h();
-  FEXCore::CPUID::FunctionResults Function_07h();
-  FEXCore::CPUID::FunctionResults Function_8000_0000h();
-  FEXCore::CPUID::FunctionResults Function_8000_0001h();
-  FEXCore::CPUID::FunctionResults Function_8000_0002h();
-  FEXCore::CPUID::FunctionResults Function_8000_0003h();
-  FEXCore::CPUID::FunctionResults Function_8000_0004h();
-  FEXCore::CPUID::FunctionResults Function_8000_0007h();
-
-  FEXCore::CPUID::FunctionResults Function_Reserved();
+  FEXCore::CPUID::FunctionResults Function_0h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_01h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_02h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_04h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_06h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_07h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_0Dh(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_15h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0000h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0001h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0005h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0006h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0007h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0008h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0009h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_0019h(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_8000_001Dh(uint32_t Leaf);
+  FEXCore::CPUID::FunctionResults Function_Reserved(uint32_t Leaf);
 };
 }

External/FEXCore/Source/Interface/Core/CompileService.cpp

@@ -5,6 +5,12 @@
 #include "Interface/Core/OpcodeDispatcher.h"
 
 namespace FEXCore {
+  static void* ThreadHandler(void *Arg) {
+    FEXCore::CompileService *This = reinterpret_cast<FEXCore::CompileService*>(Arg);
+    This->ExecutionThread();
+    return nullptr;
+  }
+
   CompileService::CompileService(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
     : CTX {ctx}
     , ParentThread {Thread} {
@@ -16,9 +22,7 @@ namespace FEXCore {
     CTX->InitializeCompiler(CompileThreadData.get(), true);
     CompileThreadData->CPUBackend->CopyNecessaryDataForCompileThread(ParentThread->CPUBackend.get());
 
-    WorkerThread = std::thread([this]() {
-      ExecutionThread();
-    });
+    WorkerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
   }
 
   void CompileService::Initialize() {
@@ -30,7 +34,7 @@ namespace FEXCore {
     ShuttingDown = true;
     // Kick the working thread
     StartWork.NotifyAll();
-    WorkerThread.join();
+    WorkerThread->join(nullptr);
   }
 
   void CompileService::ClearCache(FEXCore::Core::InternalThreadState *Thread) {
@@ -57,7 +61,7 @@ namespace FEXCore {
         }
       }
 
-      LogMan::Throw::A(CompileThreadData->LocalIRCache.size() == 0, "Compile service must never have LocalIRCache");
+      LOGMAN_THROW_A(CompileThreadData->LocalIRCache.size() == 0, "Compile service must never have LocalIRCache");
 
       CompileMutex.unlock();
     }
@@ -92,7 +96,7 @@ namespace FEXCore {
 
     // Set our thread name so we can see its relation
     char ThreadName[16]{};
-    snprintf(ThreadName, 16, "%ld-CS", ParentThread->State.ThreadManager.TID.load());
+    snprintf(ThreadName, 16, "%ld-CS", ParentThread->ThreadManager.TID.load());
     pthread_setname_np(pthread_self(), ThreadName);
 
     while (true) {
@@ -120,15 +124,15 @@ namespace FEXCore {
         // If we had a work item then work on it
         if (Item) {
           // Make sure it's not in lookup cache by accident
-          LogMan::Throw::A(CompileThreadData->LookupCache->FindBlock(Item->RIP) == 0, "Compile Service must never have entries in the LookupCache");
-          
+          LOGMAN_THROW_A(CompileThreadData->LookupCache->FindBlock(Item->RIP) == 0, "Compile Service must never have entries in the LookupCache");
+
           // Code isn't in cache, compile now
           // Set our thread state's RIP
-          CompileThreadData->State.State.rip = Item->RIP;
+          CompileThreadData->CurrentFrame->State.rip = Item->RIP;
 
           auto [CodePtr, IRList, DebugData, RAData, Generated, StartAddr, Length] = CTX->CompileCode(CompileThreadData.get(), Item->RIP);
 
-          LogMan::Throw::A(Generated == true, "Compile Service doesn't have IR Cache");
+          LOGMAN_THROW_A(Generated == true, "Compile Service doesn't have IR Cache");
 
           if (!CodePtr) {
             // XXX: We currently have the expectation that compile service code will be significantly smaller than regular thread's code

External/FEXCore/Source/Interface/Core/CompileService.h

@@ -2,6 +2,7 @@
 
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Utils/Event.h>
+#include <FEXCore/Utils/Threads.h>
 
 #include <memory>
 #include <thread>
@@ -45,12 +46,14 @@ class CompileService final {
     WorkItem *CompileCode(uint64_t RIP);
     void ClearCache(FEXCore::Core::InternalThreadState *Thread);
 
+    // Public for threading
+    void ExecutionThread();
+
   private:
     FEXCore::Context::Context *CTX;
     FEXCore::Core::InternalThreadState *ParentThread;
 
-    void ExecutionThread();
-    std::thread WorkerThread;
+    std::unique_ptr<FEXCore::Threads::Thread> WorkerThread;
     std::unique_ptr<FEXCore::Core::InternalThreadState> CompileThreadData;
 
     std::mutex QueueMutex{};

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp

@@ -0,0 +1,367 @@
+#include "Interface/Core/LookupCache.h"
+
+#include "Interface/Core/ArchHelpers/MContext.h"
+#include "Interface/Core/Dispatcher/Arm64Dispatcher.h"
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Context/Context.h"
+
+#include <FEXCore/Core/X86Enums.h>
+#include <bit>
+#include <cmath>
+
+#include "aarch64/assembler-aarch64.h"
+#include "aarch64/cpu-aarch64.h"
+#include "aarch64/disasm-aarch64.h"
+
+namespace FEXCore::CPU {
+
+using namespace vixl;
+using namespace vixl::aarch64;
+
+static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
+#define STATE x28
+
+Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config)
+  : Dispatcher(ctx, Thread), Arm64Emitter(MAX_DISPATCHER_CODE_SIZE) {
+  SRAEnabled = config.StaticRegisterAssignment;
+  SetAllowAssembler(true);
+
+  auto Buffer = GetBuffer();
+  DispatchPtr = Buffer->GetOffsetAddress<CPUBackend::AsmDispatch>(GetCursorOffset());
+
+  // while (true) {
+  //    Ptr = FindBlock(RIP)
+  //    if (!Ptr)
+  //      Ptr = CTX->CompileBlock(RIP);
+  //
+  //    Ptr();
+  // }
+
+  uint64_t VirtualMemorySize = Thread->LookupCache->GetVirtualMemorySize();
+  Literal l_VirtualMemory {VirtualMemorySize};
+  Literal l_PagePtr {Thread->LookupCache->GetPagePointer()};
+  Literal l_L1Ptr {Thread->LookupCache->GetL1Pointer()};
+  Literal l_CTX {reinterpret_cast<uintptr_t>(CTX)};
+  Literal l_Sleep {reinterpret_cast<uint64_t>(SleepThread)};
+  Literal l_CompileBlock {GetCompileBlockPtr()};
+  Literal l_ExitFunctionLink {config.ExitFunctionLink};
+  Literal l_ExitFunctionLinkThis {config.ExitFunctionLinkThis};
+
+  // Push all the register we need to save
+  PushCalleeSavedRegisters();
+
+  // Push our memory base to the correct register
+  // Move our thread pointer to the correct register
+  // This is passed in to parameter 0 (x0)
+  mov(STATE, x0);
+
+  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
+  // regardless of where we were in the stack
+  add(x0, sp, 0);
+  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)));
+
+  AbsoluteLoopTopAddressFillSRA = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+
+  if (SRAEnabled) {
+    FillStaticRegs();
+  }
+
+  // We want to ensure that we are 16 byte aligned at the top of this loop
+  Align16B();
+  aarch64::Label FullLookup{};
+  aarch64::Label CallBlock{};
+  aarch64::Label LoopTop{};
+  aarch64::Label ExitSpillSRA{};
+  aarch64::Label ThreadPauseHandler{};
+
+  bind(&LoopTop);
+  AbsoluteLoopTopAddress = GetLabelAddress<uint64_t>(&LoopTop);
+
+  // Load in our RIP
+  // Don't modify x2 since it contains our RIP once the block doesn't exist
+  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
+  auto RipReg = x2;
+
+  // L1 Cache
+  ldr(x0, &l_L1Ptr);
+
+  and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
+  add(x0, x0, Operand(x3, Shift::LSL, 4));
+  ldp(x3, x0, MemOperand(x0));
+  cmp(x0, RipReg);
+  b(&FullLookup, Condition::ne);
+
+  if (!config.ExecuteBlocksWithCall) {
+    br(x3);
+  } else {
+    b(&CallBlock);
+  }
+
+  // L1C check failed, do a full lookup
+  bind(&FullLookup);
+
+  // This is the block cache lookup routine
+  // It matches what is going on it LookupCache.h::FindBlock
+  ldr(x0, &l_PagePtr);
+
+  // Mask the address by the virtual address size so we can check for aliases
+  if (std::popcount(VirtualMemorySize) == 1) {
+    and_(x3, RipReg, Thread->LookupCache->GetVirtualMemorySize() - 1);
+  }
+  else {
+    ldr(x3, &l_VirtualMemory);
+    and_(x3, RipReg, x3);
+  }
+
+  aarch64::Label NoBlock;
+  {
+    // Offset the address and add to our page pointer
+    lsr(x1, x3, 12);
+
+    // Load the pointer from the offset
+    ldr(x0, MemOperand(x0, x1, Shift::LSL, 3));
+
+    // If page pointer is zero then we have no block
+    cbz(x0, &NoBlock);
+
+    // Steal the page offset
+    and_(x1, x3, 0x0FFF);
+
+    // Shift the offset by the size of the block cache entry
+    add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry))));
+
+    // Load the guest address first to ensure it maps to the address we are currently at
+    // This fixes aliasing problems
+    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)));
+    cmp(x1, RipReg);
+    b(&NoBlock, Condition::ne);
+
+    // Now load the actual host block to execute if we can
+    ldr(x3, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)));
+    cbz(x3, &NoBlock);
+
+    // If we've made it here then we have a real compiled block
+    {
+      // update L1 cache
+      ldr(x0, &l_L1Ptr);
+
+      and_(x1, RipReg, LookupCache::L1_ENTRIES_MASK);
+      add(x0, x0, Operand(x1, Shift::LSL, 4));
+      stp(x3, x2, MemOperand(x0));
+
+      // Jump to the block
+      if (!config.ExecuteBlocksWithCall) {
+        br(x3);
+      } else {
+        bind(&CallBlock);
+        mov(x0, STATE);
+        blr(x3);
+
+        if (CTX->GetGdbServerStatus()) {
+          // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
+          // This happens when single stepping
+
+          static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
+          ldr(x0, &l_CTX);
+          ldr(w0, MemOperand(x0, offsetof(FEXCore::Context::Context, Config.RunningMode)));
+          // If the value == 0 then branch to the top
+          cbz(x0, &LoopTop);
+          // Else we need to pause now
+          b(&ThreadPauseHandler);
+        } else {
+          // Unconditionally loop to the top
+          // We will only stop on error when compiling a block or signal
+          b(&LoopTop);
+        }
+      }
+    }
+  }
+
+  {
+    bind(&ExitSpillSRA);
+    ThreadStopHandlerAddressSpillSRA = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    ThreadStopHandlerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+
+    PopCalleeSavedRegisters();
+
+    // Return from the function
+    // LR is set to the correct return location now
+    ret();
+  }
+
+  {
+    ExitFunctionLinkerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    ldr(x0, &l_ExitFunctionLinkThis);
+    mov(x1, STATE);
+    mov(x2, lr);
+
+    ldr(x3, &l_ExitFunctionLink);
+    blr(x3);
+
+    if (SRAEnabled)
+      FillStaticRegs();
+    br(x0);
+  }
+
+  // Need to create the block
+  {
+    bind(&NoBlock);
+
+    ldr(x0, &l_CTX);
+    mov(x1, STATE);
+    ldr(x3, &l_CompileBlock);
+
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    // X2 contains our guest RIP
+    blr(x3); // { CTX, Frame, RIP}
+
+    if (SRAEnabled)
+      FillStaticRegs();
+
+    b(&LoopTop);
+  }
+
+  {
+    SignalHandlerReturnAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+
+    // Now to get back to our old location we need to do a fault dance
+    // We can't use SIGTRAP here since gdb catches it and never gives it to the application!
+    hlt(0);
+  }
+
+  {
+    ThreadPauseHandlerAddressSpillSRA = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+    if (SRAEnabled)
+      SpillStaticRegs();
+
+    bind(&ThreadPauseHandler);
+    ThreadPauseHandlerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+    // We are pausing, this means the frontend should be waiting for this thread to idle
+    // We will have faulted and jumped to this location at this point
+
+    // Call our sleep handler
+    ldr(x0, &l_CTX);
+    mov(x1, STATE);
+    ldr(x2, &l_Sleep);
+    blr(x2);
+
+    PauseReturnInstruction = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+    // Fault to start running again
+    hlt(0);
+  }
+
+  {
+    // The expectation here is that a thunked function needs to call back in to the JIT in a reentrant safe way
+    // To do this safely we need to do some state tracking and register saving
+    //
+    // eg:
+    // JIT Call->
+    //  Thunk->
+    //    Thunk callback->
+    //
+    // The thunk callback needs to execute JIT code and when it returns, it needs to safely return to the thunk rather than JIT space
+    // This is handled by pushing a return address trampoline to the stack so when the guest address returns it hits our custom thunk return
+    //  - This will safely return us to the thunk
+    //
+    // On return to the thunk, the thunk can get whatever its return value is from the thread context depending on ABI handling on its end
+    // When the thunk itself returns, it'll do its regular return logic there
+    // void ReentrantCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP);
+    CallbackPtr = Buffer->GetOffsetAddress<CPUBackend::JITCallback>(GetCursorOffset());
+
+    // We expect the thunk to have previously pushed the registers it was using
+    PushCalleeSavedRegisters();
+
+    // First thing we need to move the thread state pointer back in to our register
+    mov(STATE, x0);
+
+    // Make sure to adjust the refcounter so we don't clear the cache now
+    LoadConstant(x0, reinterpret_cast<uint64_t>(&SignalHandlerRefCounter));
+    ldr(w2, MemOperand(x0));
+    add(w2, w2, 1);
+    str(w2, MemOperand(x0));
+
+    // Now push the callback return trampoline to the guest stack
+    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
+    LoadConstant(x0, CTX->X86CodeGen.CallbackReturn);
+
+    ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
+    sub(x2, x2, 16);
+    str(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
+
+    // Store the trampoline to the guest stack
+    // Guest stack is now correctly misaligned after a regular call instruction
+    str(x0, MemOperand(x2));
+
+    // Store RIP to the context state
+    str(x1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
+
+    // load static regs
+    if (SRAEnabled)
+      FillStaticRegs();
+
+    // Now go back to the regular dispatcher loop
+    b(&LoopTop);
+  }
+
+  place(&l_VirtualMemory);
+  place(&l_PagePtr);
+  place(&l_L1Ptr);
+  place(&l_CTX);
+  place(&l_Sleep);
+  place(&l_CompileBlock);
+  place(&l_ExitFunctionLink);
+  place(&l_ExitFunctionLinkThis);
+
+
+  FinalizeCode();
+  Start = reinterpret_cast<uint64_t>(DispatchPtr);
+  End = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
+  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
+  GetBuffer()->SetExecutable();
+
+#if ENABLE_JITSYMBOLS
+  std::string Name = "Dispatch_" + std::to_string(::gettid());
+  CTX->Symbols.Register(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr), Name);
+#endif
+}
+
+void Arm64Dispatcher::SpillSRA(void *ucontext) {
+  for(int i = 0; i < SRA64.size(); i++) {
+    ThreadState->CurrentFrame->State.gregs[i] = ArchHelpers::Context::GetArmReg(ucontext, SRA64[i].GetCode());
+  }
+  // TODO: Also recover FPRs, not sure where the neon context is
+  // This is usually not needed
+  /*
+  for(int i = 0; i < SRAFPR.size(); i++) {
+      State->State.State.xmm[i][0] = _mcontext.neon[SRAFPR[i].GetCode()];
+      State->State.State.xmm[i][0] = _mcontext.neon[SRAFPR[i].GetCode()];
+  }
+  */
+}
+
+#ifdef _M_ARM_64
+
+void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  DispatcherConfig config;
+  config.ExecuteBlocksWithCall = true;
+
+  Dispatcher = std::make_unique<Arm64Dispatcher>(ctx, Thread, config);
+  DispatchPtr = Dispatcher->DispatchPtr;
+  CallbackPtr = Dispatcher->CallbackPtr;
+
+  // TODO: It feels wrong to initialize this way
+  ctx->InterpreterCallbackReturn = Dispatcher->ReturnPtr;
+}
+
+#endif
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.h

@@ -0,0 +1,18 @@
+#pragma once
+
+#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+
+#include "aarch64/assembler-aarch64.h"
+
+namespace FEXCore::CPU {
+
+class Arm64Dispatcher final : public Dispatcher, public Arm64Emitter {
+  public:
+    Arm64Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config);
+
+  protected:
+    void SpillSRA(void *ucontext) override;
+};
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -0,0 +1,456 @@
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+
+#include "Common/MathUtils.h"
+#include "Interface/Core/ArchHelpers/MContext.h"
+#include <FEXCore/Core/X86Enums.h>
+
+namespace FEXCore::CPU {
+
+void Dispatcher::SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuStateFrame *Frame) {
+  auto Thread = Frame->Thread;
+
+  --ctx->IdleWaitRefCount;
+  ctx->IdleWaitCV.notify_all();
+
+  // Go to sleep
+  Thread->StartRunning.Wait();
+
+  Thread->RunningEvents.Running = true;
+  ++ctx->IdleWaitRefCount;
+  ctx->IdleWaitCV.notify_all();
+}
+
+void Dispatcher::StoreThreadState(int Signal, void *ucontext) {
+  // We can end up getting a signal at any point in our host state
+  // Jump to a handler that saves all state so we can safely return
+  uint64_t OldSP = ArchHelpers::Context::GetSp(ucontext);
+  uintptr_t NewSP = OldSP;
+
+  size_t StackOffset = sizeof(ArchHelpers::Context::ContextBackup);
+
+  // We need to back up behind the host's red zone
+  // We do this on the guest side as well
+  // (does nothing on arm hosts)
+  NewSP -= ArchHelpers::Context::ContextBackup::RedZoneSize;
+
+  NewSP -= StackOffset;
+  NewSP = AlignDown(NewSP, 16);
+
+  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
+  ArchHelpers::Context::BackupContext(ucontext, Context);
+
+  // Retain the action pointer so we can see it when we return
+  Context->Signal = Signal;
+
+  // Save guest state
+  // We can't guarantee if registers are in context or host GPRs
+  // So we need to save everything
+  memcpy(&Context->GuestState, ThreadState->CurrentFrame, sizeof(FEXCore::Core::CPUState));
+
+  // Set the new SP
+  ArchHelpers::Context::SetSp(ucontext, NewSP);
+
+  SignalFrames.push(NewSP);
+}
+
+void Dispatcher::RestoreThreadState(void *ucontext) {
+  LOGMAN_THROW_A(!SignalFrames.empty(), "Trying to restore a signal frame when we don't have any");
+  uint64_t OldSP = SignalFrames.top();
+  SignalFrames.pop();
+  uintptr_t NewSP = OldSP;
+  auto Context = reinterpret_cast<ArchHelpers::Context::ContextBackup*>(NewSP);
+
+  // First thing, reset the guest state
+  memcpy(ThreadState->CurrentFrame, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
+
+  // Now restore host state
+  ArchHelpers::Context::RestoreContext(ucontext, Context);
+
+  // Restore the previous signal state
+  // This allows recursive signals to properly handle signal masking as we are walking back up the list of signals
+  CTX->SignalDelegation->SetCurrentSignal(Context->Signal);
+}
+
+bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
+  StoreThreadState(Signal, ucontext);
+  auto Frame = ThreadState->CurrentFrame;
+
+  // Ref count our faults
+  // We use this to track if it is safe to clear cache
+  ++SignalHandlerRefCounter;
+
+  // Set the new PC
+  ArchHelpers::Context::SetPc(ucontext, AbsoluteLoopTopAddressFillSRA);
+  // Set our state register to point to our guest thread data
+  ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
+
+
+  uint64_t OldGuestSP = Frame->State.gregs[X86State::REG_RSP];
+  uint64_t NewGuestSP = OldGuestSP;
+
+  if (!(GuestStack->ss_flags & SS_DISABLE)) {
+    // If our guest is already inside of the alternative stack
+    // Then that means we are hitting recursive signals and we need to walk back the stack correctly
+    uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
+    uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
+    if (OldGuestSP >= AltStackBase &&
+        OldGuestSP <= AltStackEnd) {
+      // We are already in the alt stack, the rest of the code will handle adjusting this
+    }
+    else {
+      NewGuestSP = AltStackEnd;
+    }
+  }
+
+  // Back up past the redzone, which is 128bytes
+  // Don't need this offset if we aren't going to be putting siginfo in to it
+  NewGuestSP -= 128;
+
+  // siginfo_t
+  siginfo_t *HostSigInfo = reinterpret_cast<siginfo_t*>(info);
+
+  if (GuestAction->sa_flags & SA_SIGINFO &&
+      !(HostSigInfo->si_code == SI_QUEUE || // If the siginfo comes from sigqueue or user then we don't need to check
+        HostSigInfo->si_code == SI_USER)) {
+    if (SRAEnabled) {
+      if (!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), false)) {
+        LOGMAN_THROW_A(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true), "Signals in dispatcher have unsynchronized context");
+      } else {
+        // We are in jit, SRA must be spilled
+        SpillSRA(ucontext);
+      }
+    }
+
+    // Setup ucontext a bit
+    if (CTX->Config.Is64BitMode) {
+      NewGuestSP -= sizeof(FEXCore::x86_64::ucontext_t);
+      uint64_t UContextLocation = NewGuestSP;
+
+      NewGuestSP -= sizeof(siginfo_t);
+      uint64_t SigInfoLocation = NewGuestSP;
+
+      FEXCore::x86_64::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86_64::ucontext_t*>(UContextLocation);
+      siginfo_t *guest_siginfo = reinterpret_cast<siginfo_t*>(SigInfoLocation);
+
+      // We have extended float information
+      guest_uctx->uc_flags |= FEXCore::x86_64::UC_FP_XSTATE;
+
+      // Pointer to where the fpreg memory is
+      guest_uctx->uc_mcontext.fpregs = &guest_uctx->__fpregs_mem;
+
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] = Frame->State.rip;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CSGSFS] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = Signal;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_OLDMASK] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CR2] = 0;
+
+#define COPY_REG(x) \
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
+      COPY_REG(R8);
+      COPY_REG(R9);
+      COPY_REG(R10);
+      COPY_REG(R11);
+      COPY_REG(R12);
+      COPY_REG(R13);
+      COPY_REG(R14);
+      COPY_REG(R15);
+      COPY_REG(RDI);
+      COPY_REG(RSI);
+      COPY_REG(RBP);
+      COPY_REG(RBX);
+      COPY_REG(RDX);
+      COPY_REG(RAX);
+      COPY_REG(RCX);
+      COPY_REG(RSP);
+#undef COPY_REG
+
+      // Copy float registers
+      memcpy(guest_uctx->__fpregs_mem._st, Frame->State.mm, sizeof(Frame->State.mm));
+      memcpy(guest_uctx->__fpregs_mem._xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+
+      // FCW store default
+      guest_uctx->__fpregs_mem.fcw = Frame->State.FCW;
+      guest_uctx->__fpregs_mem.ftw = Frame->State.FTW;
+
+      // Reconstruct FSW
+      guest_uctx->__fpregs_mem.fsw =
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] << 11) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] << 8) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] << 9) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] << 10) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] << 14);
+
+      // Copy over signal stack information
+      guest_uctx->uc_stack.ss_flags = GuestStack->ss_flags;
+      guest_uctx->uc_stack.ss_sp = GuestStack->ss_sp;
+      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
+
+      // aarch64 and x86_64 siginfo_t matches. We can just copy this over
+      // SI_USER could also potentially have random data in it, needs to be bit perfect
+      // For guest faults we don't have a real way to reconstruct state to a real guest RIP
+      *guest_siginfo = *HostSigInfo;
+
+      Frame->State.gregs[X86State::REG_RSI] = SigInfoLocation;
+      Frame->State.gregs[X86State::REG_RDX] = UContextLocation;
+    }
+    else {
+      // XXX: 32bit Support
+      NewGuestSP -= sizeof(FEXCore::x86::ucontext_t);
+      uint64_t UContextLocation = NewGuestSP;
+      NewGuestSP -= sizeof(FEXCore::x86::siginfo_t);
+      uint64_t SigInfoLocation = NewGuestSP;
+
+      FEXCore::x86::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86::ucontext_t*>(UContextLocation);
+      FEXCore::x86::siginfo_t *guest_siginfo = reinterpret_cast<FEXCore::x86::siginfo_t*>(SigInfoLocation);
+
+      // We have extended float information
+      guest_uctx->uc_flags |= FEXCore::x86::UC_FP_XSTATE;
+
+      // Pointer to where the fpreg memory is
+      guest_uctx->uc_mcontext.fpregs = static_cast<uint32_t>(reinterpret_cast<uint64_t>(&guest_uctx->__fpregs_mem));
+
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS] = Frame->State.gs;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS] = Frame->State.fs;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ES] = Frame->State.es;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_DS] = Frame->State.ds;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = Signal;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] = Frame->State.rip;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS] = Frame->State.cs;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EFL] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_UESP] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS] = Frame->State.ss;
+
+#define COPY_REG(x) \
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
+      COPY_REG(RDI);
+      COPY_REG(RSI);
+      COPY_REG(RBP);
+      COPY_REG(RBX);
+      COPY_REG(RDX);
+      COPY_REG(RAX);
+      COPY_REG(RCX);
+      COPY_REG(RSP);
+#undef COPY_REG
+
+      // Copy float registers
+      memcpy(guest_uctx->__fpregs_mem._st, Frame->State.mm, sizeof(Frame->State.mm));
+      if (0) {
+        // XXX: Handle XMM
+        // memcpy(guest_uctx->__fpregs_mem._xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+        guest_uctx->__fpregs_mem.status = FEXCore::x86::fpstate_magic::MAGIC_XFPSTATE;
+      }
+      else {
+        guest_uctx->__fpregs_mem.status = FEXCore::x86::fpstate_magic::MAGIC_FPU;
+      }
+      // FCW store default
+      guest_uctx->__fpregs_mem.fcw = Frame->State.FCW;
+      guest_uctx->__fpregs_mem.ftw = Frame->State.FTW;
+      // Reconstruct FSW
+      guest_uctx->__fpregs_mem.fsw =
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] << 11) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] << 8) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] << 9) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] << 10) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] << 14);
+
+      // Copy over signal stack information
+      guest_uctx->uc_stack.ss_flags = GuestStack->ss_flags;
+      guest_uctx->uc_stack.ss_sp = static_cast<uint32_t>(reinterpret_cast<uint64_t>(GuestStack->ss_sp));
+      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
+
+      // These three elements are in every siginfo
+      guest_siginfo->si_signo = HostSigInfo->si_signo;
+      guest_siginfo->si_errno = HostSigInfo->si_errno;
+      guest_siginfo->si_code = HostSigInfo->si_code;
+
+      switch (Signal) {
+        case SIGSEGV:
+        case SIGBUS:
+          // Macro expansion to get the si_addr
+          // Can't really give a real result here. Pull from the context for now
+          guest_siginfo->_sifields._sigfault.addr = Frame->State.rip;
+          break;
+        case SIGCHLD:
+          guest_siginfo->_sifields._sigchld.pid = HostSigInfo->si_pid;
+          guest_siginfo->_sifields._sigchld.uid = HostSigInfo->si_uid;
+          guest_siginfo->_sifields._sigchld.status = HostSigInfo->si_status;
+          guest_siginfo->_sifields._sigchld.utime = HostSigInfo->si_utime;
+          guest_siginfo->_sifields._sigchld.stime = HostSigInfo->si_stime;
+          break;
+      default:
+        // Hope for the best, most things just copy over
+        memcpy(&guest_siginfo->_sifields, &HostSigInfo->_sifields, sizeof(siginfo_t));
+        break;
+      }
+
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = UContextLocation;
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = SigInfoLocation;
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = Signal;
+    }
+
+    Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
+  }
+  else {
+    if (!CTX->Config.Is64BitMode) {
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = Signal;
+    }
+
+    Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
+  }
+
+  if (CTX->Config.Is64BitMode) {
+    Frame->State.gregs[X86State::REG_RDI] = Signal;
+
+    // Set up the new SP for stack handling
+    NewGuestSP -= 8;
+    *(uint64_t*)NewGuestSP = CTX->X86CodeGen.SignalReturn;
+    Frame->State.gregs[X86State::REG_RSP] = NewGuestSP;
+  }
+  else {
+    NewGuestSP -= 4;
+    *(uint32_t*)NewGuestSP = CTX->X86CodeGen.SignalReturn;
+    LOGMAN_THROW_A(CTX->X86CodeGen.SignalReturn < 0x1'0000'0000ULL, "This needs to be below 4GB");
+    Frame->State.gregs[X86State::REG_RSP] = NewGuestSP;
+  }
+
+  return true;
+}
+
+bool Dispatcher::HandleSIGILL(int Signal, void *info, void *ucontext) {
+
+  if (ArchHelpers::Context::GetPc(ucontext) == SignalHandlerReturnAddress) {
+    RestoreThreadState(ucontext);
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    --SignalHandlerRefCounter;
+    return true;
+  }
+
+  if (ArchHelpers::Context::GetPc(ucontext) == PauseReturnInstruction) {
+    RestoreThreadState(ucontext);
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    --SignalHandlerRefCounter;
+    return true;
+  }
+
+  return false;
+}
+
+bool Dispatcher::HandleSignalPause(int Signal, void *info, void *ucontext) {
+  FEXCore::Core::SignalEvent SignalReason = ThreadState->SignalReason.load();
+  auto Frame = ThreadState->CurrentFrame;
+
+  if (SignalReason == FEXCore::Core::SignalEvent::Pause) {
+    // Store our thread state so we can come back to this
+    StoreThreadState(Signal, ucontext);
+
+    if (SRAEnabled && IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), false)) {
+      // We are in jit, SRA must be spilled
+      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddressSpillSRA);
+    } else {
+      if (SRAEnabled) {
+        // We are in non-jit, SRA is already spilled
+        LOGMAN_THROW_A(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true), "Signals in dispatcher have unsynchronized context");
+      }
+      ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddress);
+    }
+
+    // Set the new PC
+    ArchHelpers::Context::SetPc(ucontext, ThreadPauseHandlerAddress);
+
+    // Set our state register to point to our guest thread data
+    ArchHelpers::Context::SetState(ucontext, reinterpret_cast<uint64_t>(Frame));
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    ++SignalHandlerRefCounter;
+
+    ThreadState->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
+    return true;
+  }
+
+  if (SignalReason == FEXCore::Core::SignalEvent::Stop) {
+    // Our thread is stopping
+    // We don't care about anything at this point
+    // Set the stack to our starting location when we entered the core and get out safely
+    ArchHelpers::Context::SetSp(ucontext, Frame->ReturningStackLocation);
+
+    // Our ref counting doesn't matter anymore
+    SignalHandlerRefCounter = 0;
+
+    // Set the new PC
+    if (SRAEnabled && IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), false)) {
+      // We are in jit, SRA must be spilled
+      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddressSpillSRA);
+    } else {
+      if (SRAEnabled) {
+        // We are in non-jit, SRA is already spilled
+        LOGMAN_THROW_A(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true), "Signals in dispatcher have unsynchronized context");
+      }
+      ArchHelpers::Context::SetPc(ucontext, ThreadStopHandlerAddress);
+    }
+
+    ThreadState->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
+    return true;
+  }
+
+  if (SignalReason == FEXCore::Core::SignalEvent::Return) {
+    RestoreThreadState(ucontext);
+
+    // Ref count our faults
+    // We use this to track if it is safe to clear cache
+    --SignalHandlerRefCounter;
+
+    ThreadState->SignalReason.store(FEXCore::Core::SignalEvent::Nothing);
+    return true;
+  }
+
+  return false;
+}
+
+uint64_t Dispatcher::GetCompileBlockPtr() {
+  using ClassPtrType = void (FEXCore::Context::Context::*)(FEXCore::Core::CpuStateFrame *, uint64_t);
+  union PtrCast {
+    ClassPtrType ClassPtr;
+    uintptr_t Data;
+  };
+
+  PtrCast CompileBlockPtr;
+  CompileBlockPtr.ClassPtr = &FEXCore::Context::Context::CompileBlockJit;
+  return CompileBlockPtr.Data;
+}
+
+void Dispatcher::RemoveCodeBuffer(uint8_t* start_to_remove) {
+  for (auto iter = CodeBuffers.begin(); iter != CodeBuffers.end(); ++iter) {
+    auto [start, end] = *iter;
+    if (start == reinterpret_cast<uint64_t>(start_to_remove)) {
+      CodeBuffers.erase(iter);
+      return;
+    }
+  }
+}
+
+bool Dispatcher::IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher) const {
+  for (auto [start, end] : CodeBuffers) {
+    if (Address >= start && Address < end) {
+      return true;
+    }
+  }
+
+  if (IncludeDispatcher) {
+    return IsAddressInDispatcher(Address);
+  }
+  return false;
+}
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h

@@ -0,0 +1,85 @@
+#pragma once
+
+#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/Core/SignalDelegator.h>
+
+#include "Interface/Context/Context.h"
+
+#include <stack>
+
+namespace FEXCore::CPU {
+
+struct DispatcherConfig {
+  bool ExecuteBlocksWithCall = false;
+  uintptr_t ExitFunctionLink = 0;
+  uintptr_t ExitFunctionLinkThis = 0;
+  bool StaticRegisterAssignment = false;
+};
+
+class Dispatcher {
+public:
+  virtual ~Dispatcher() = default;
+  CPUBackend::AsmDispatch DispatchPtr;
+  CPUBackend::JITCallback CallbackPtr;
+  FEXCore::Context::Context::IntCallbackReturn ReturnPtr;
+
+  /**
+   * @name Dispatch Helper functions
+   * @{ */
+  uint64_t ThreadStopHandlerAddress{};
+  uint64_t ThreadStopHandlerAddressSpillSRA{};
+  uint64_t AbsoluteLoopTopAddress{};
+  uint64_t AbsoluteLoopTopAddressFillSRA{};
+  uint64_t ThreadPauseHandlerAddress{};
+  uint64_t ThreadPauseHandlerAddressSpillSRA{};
+  uint64_t ExitFunctionLinkerAddress{};
+  uint64_t SignalHandlerReturnAddress{};
+  uint64_t PauseReturnInstruction{};
+
+  /**  @} */
+
+  uint32_t SignalHandlerRefCounter{};
+
+  uint64_t Start{};
+  uint64_t End{};
+
+  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
+  bool HandleSIGILL(int Signal, void *info, void *ucontext);
+  bool HandleSignalPause(int Signal, void *info, void *ucontext);
+
+  void RegisterCodeBuffer(uint8_t* start, size_t size) {
+    CodeBuffers.emplace_back(reinterpret_cast<uint64_t>(start),
+        reinterpret_cast<uint64_t>(start + size));
+  }
+
+  void RemoveCodeBuffer(uint8_t* start);
+
+  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true) const;
+  bool IsAddressInDispatcher(uint64_t Address) const {
+    return Address >= Start && Address < End;
+  }
+
+protected:
+  Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
+    : CTX {ctx}
+    , ThreadState {Thread} {}
+
+  void StoreThreadState(int Signal, void *ucontext);
+  void RestoreThreadState(void *ucontext);
+  std::stack<uint64_t> SignalFrames;
+
+  bool SRAEnabled = false;
+  virtual void SpillSRA(void *ucontext) {}
+
+  FEXCore::Context::Context *CTX;
+  FEXCore::Core::InternalThreadState *ThreadState;
+
+  static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::CpuStateFrame *Frame);
+
+  static uint64_t GetCompileBlockPtr();
+
+private:
+  std::vector<std::tuple<uint64_t, uint64_t>> CodeBuffers; // Start, End
+};
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp

@@ -0,0 +1,324 @@
+#include "Interface/Core/LookupCache.h"
+
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
+
+#include "Interface/Core/Interpreter/InterpreterClass.h"
+#include "Interface/Context/Context.h"
+
+#include <FEXCore/Core/X86Enums.h>
+#include <cmath>
+
+namespace FEXCore::CPU {
+static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
+#define STATE r14
+
+X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config)
+  : Dispatcher(ctx, Thread)
+  , Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE,
+      FEXCore::Allocator::mmap(nullptr, MAX_DISPATCHER_CODE_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0),
+      nullptr) {
+
+  using namespace Xbyak;
+  using namespace Xbyak::util;
+  DispatchPtr = getCurr<CPUBackend::AsmDispatch>();
+
+  // Temp registers
+  // rax, rcx, rdx, rsi, r8, r9,
+  // r10, r11
+  //
+  // Callee Saved
+  // rbx, rbp, r12, r13, r14, r15
+  //
+  // 1St Argument: rdi <ThreadState>
+  // XMM:
+  // All temp
+
+  // while (true) {
+  //    Ptr = FindBlock(RIP)
+  //    if (!Ptr)
+  //      Ptr = CTX->CompileBlock(RIP);
+  //
+  //    if (Ptr)
+  //      Ptr();
+  //    else
+  //    {
+  //      Ptr = FallbackCore->CompileBlock()
+  //      if (Ptr)
+  //        Ptr()
+  //      else {
+  //        ShouldStop = true;
+  //      }
+  //    }
+  // }
+  // Bunch of exit state stuff
+
+  // x86-64 ABI has the stack aligned when /call/ happens
+  // Which means the destination has a misaligned stack at that point
+  push(rbx);
+  push(rbp);
+  push(r12);
+  push(r13);
+  push(r14);
+  push(r15);
+  sub(rsp, 8);
+
+  mov(STATE, rdi);
+
+  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
+  // regardless of where we were in the stack
+  mov(qword [rdi + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)], rsp);
+
+  Label LoopTop;
+  Label FullLookup;
+  Label CallBlock;
+  Label NoBlock;
+  Label ExitBlock;
+  Label ThreadPauseHandler;
+
+  L(LoopTop);
+  AbsoluteLoopTopAddressFillSRA = AbsoluteLoopTopAddress = getCurr<uint64_t>();
+
+  {
+    // Load our RIP
+    mov(rdx, qword [STATE + offsetof(FEXCore::Core::CPUState, rip)]);
+
+    // L1 Cache
+    mov(r13, Thread->LookupCache->GetL1Pointer());
+    mov(rax, rdx);
+
+    and_(rax, LookupCache::L1_ENTRIES_MASK);
+    shl(rax, 4);
+    cmp(qword[r13 + rax + 8], rdx);
+    jne(FullLookup);
+
+    if (!config.ExecuteBlocksWithCall) {
+      jmp(qword[r13 + rax + 0]);
+    } else {
+      mov(rax, qword[r13 + rax + 0]);
+      jmp(CallBlock);
+    }
+
+    L(FullLookup);
+    mov(r13, Thread->LookupCache->GetPagePointer());
+
+    // Full lookup
+    mov(rax, rdx);
+    mov(rbx, Thread->LookupCache->GetVirtualMemorySize() - 1);
+    and_(rax, rbx);
+    shr(rax, 12);
+
+    // Load page pointer
+    mov(rdi, qword [r13 + rax * 8]);
+
+    cmp(rdi, 0);
+    je(NoBlock);
+
+    mov (rax, rdx);
+    and_(rax, 0x0FFF);
+
+    shl(rax, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
+
+    // check for aliasing
+    mov(rcx, qword [rdi + rax + 8]);
+    cmp(rcx, rdx);
+    jne(NoBlock);
+
+    // Load the block pointer
+    mov(rax, qword [rdi + rax]);
+
+    cmp(rax, 0);
+    je(NoBlock);
+
+    // Update L1
+    
+    mov(r13, Thread->LookupCache->GetL1Pointer());
+    mov(rcx, rdx);
+    and_(rcx, LookupCache::L1_ENTRIES_MASK);
+    shl(rcx, 1);
+    mov(qword[r13 + rcx*8 + 8], rdx);
+    mov(qword[r13 + rcx*8 + 0], rax);
+
+    // Real block if we made it here
+    if (!config.ExecuteBlocksWithCall) {
+      jmp(rax);
+    } else {
+      L(CallBlock);
+      mov(rdi, STATE);
+      call(rax);
+
+      if (CTX->GetGdbServerStatus()) {
+        // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
+        // This happens when single stepping
+        static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
+        mov(rax, qword [STATE + (offsetof(FEXCore::Core::InternalThreadState, CTX))]);
+
+        // If the value == 0 then branch to the top
+        cmp(dword [rax + (offsetof(FEXCore::Context::Context, Config.RunningMode))], 0);
+        je(LoopTop);
+        // Else we need to pause now
+        jmp(ThreadPauseHandler);
+        ud2();
+      }
+      else {
+        jmp(LoopTop);
+      }
+    }
+  }
+
+  {
+    L(ExitBlock);
+    ThreadStopHandlerAddress = getCurr<uint64_t>();
+
+    add(rsp, 8);
+
+    pop(r15);
+    pop(r14);
+    pop(r13);
+    pop(r12);
+    pop(rbp);
+    pop(rbx);
+
+    ret();
+  }
+
+  // Block creation
+  {
+    L(NoBlock);
+
+    // {rdi, rsi, rdx}
+    mov(rdi, reinterpret_cast<uint64_t>(CTX));
+    mov(rsi, STATE);
+    mov(rax, GetCompileBlockPtr());
+
+    call(rax);
+
+    // rdx already contains RIP here
+    jmp(LoopTop);
+  }
+
+  {
+    ExitFunctionLinkerAddress = getCurr<uint64_t>();
+    // {rdi, rsi, rdx}
+    mov(rdi, config.ExitFunctionLinkThis);
+    mov(rsi, STATE);
+    mov(rdx, rax); // rax is set at the block end
+
+    mov(rax, config.ExitFunctionLink);
+    call(rax);
+    jmp(rax);
+  }
+
+  {
+    // Pause handler
+    ThreadPauseHandlerAddress = getCurr<uint64_t>();
+    L(ThreadPauseHandler);
+
+    mov(rdi, reinterpret_cast<uintptr_t>(CTX));
+    mov(rsi, STATE);
+    mov(rax, reinterpret_cast<uint64_t>(SleepThread));
+
+    call(rax);
+
+    // XXX: Unsupported atm
+    PauseReturnInstruction = getCurr<uint64_t>();
+    ud2();
+  }
+
+  {
+    CallbackPtr = getCurr<CPUBackend::JITCallback>();
+
+    push(rbx);
+    push(rbp);
+    push(r12);
+    push(r13);
+    push(r14);
+    push(r15);
+    sub(rsp, 8);
+
+    // First thing we need to move the thread state pointer back in to our register
+    mov(STATE, rdi);
+    // XXX: XMM?
+
+    // Make sure to adjust the refcounter so we don't clear the cache now
+    mov(rax, reinterpret_cast<uint64_t>(&SignalHandlerRefCounter));
+    add(dword [rax], 1);
+
+    // Now push the callback return trampoline to the guest stack
+    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
+    mov(rax, CTX->X86CodeGen.CallbackReturn);
+
+    // Store the trampoline to the guest stack
+    // Guest stack is now correctly misaligned after a regular call instruction
+    sub(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])], 16);
+    mov(rbx, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])]);
+    mov(qword [rbx], rax);
+
+    // Store RIP to the context state
+    mov(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.rip)], rsi);
+
+    // Back to the loop top now
+    jmp(LoopTop);
+  }
+
+  {
+    // Signal return handler
+    SignalHandlerReturnAddress = getCurr<uint64_t>();
+
+    ud2();
+  }
+
+
+  {
+    ReturnPtr = getCurr<FEXCore::Context::Context::IntCallbackReturn>();
+//  using CallbackReturn =  FEX_NAKED void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
+
+    // rdi = thread
+    // rsi = rsp
+
+    mov(rsp, rsi);
+
+    // Now jump back to the thunk
+    // XXX: XMM?
+    add(rsp, 8);
+
+    pop(r15);
+    pop(r14);
+    pop(r13);
+    pop(r12);
+    pop(rbp);
+    pop(rbx);
+
+    ret();
+  }
+  ready();
+
+  Start = reinterpret_cast<uint64_t>(getCode());
+  End = Start + getSize();
+
+  #if ENABLE_JITSYMBOLS
+    std::string Name = "Dispatch_" + std::to_string(::gettid());
+    CTX->Symbols.Register(reinterpret_cast<void*>(Start), End-Start, Name);
+  #endif
+}
+
+X86Dispatcher::~X86Dispatcher() {
+  FEXCore::Allocator::munmap(top_, MAX_DISPATCHER_CODE_SIZE);
+}
+
+#ifdef _M_X86_64
+
+void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  DispatcherConfig config;
+  config.ExecuteBlocksWithCall = true;
+
+  Dispatcher = std::make_unique<X86Dispatcher>(ctx, Thread, config);
+  DispatchPtr = Dispatcher->DispatchPtr;
+  CallbackPtr = Dispatcher->CallbackPtr;
+
+  // TODO: It feels wrong to initialize this way
+  ctx->InterpreterCallbackReturn = Dispatcher->ReturnPtr;
+}
+
+#endif
+
+}

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.h

@@ -0,0 +1,19 @@
+#pragma once
+
+#include "Interface/Core/Dispatcher/Dispatcher.h"
+
+#include <FEXCore/Utils/Allocator.h>
+
+#define XBYAK64
+#include <xbyak/xbyak.h>
+
+namespace FEXCore::CPU {
+
+class X86Dispatcher final : public Dispatcher, public Xbyak::CodeGenerator {
+  public:
+    X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config);
+
+    virtual ~X86Dispatcher() override;
+};
+
+}

External/FEXCore/Source/Interface/Core/Frontend.cpp

@@ -1,3 +1,10 @@
+/*
+$info$
+tags: frontend|x86-meta-blocks
+desc: Extracts instruction & block meta info, frontend multiblock logic
+$end_info$
+*/
+
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Frontend.h"
 #include "Interface/Core/InternalThreadState.h"
@@ -8,12 +15,18 @@
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <set>
+#include <sys/mman.h>
 
 namespace FEXCore::Frontend {
+#include "Interface/Core/VSyscall/VSyscall.inc"
+
 using namespace FEXCore::X86Tables;
 
 static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool HasREX, bool HasXMM, bool HasMM, uint8_t InvalidOffset = 16) {
-  constexpr std::array<uint64_t, 16> GPRIndexes = {
+  using GPRArray = std::array<uint32_t, 16>;
+
+  static constexpr GPRArray GPRIndexes = {
     // Classical ordering?
     FEXCore::X86State::REG_RAX,
     FEXCore::X86State::REG_RCX,
@@ -33,7 +46,7 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
     FEXCore::X86State::REG_R15,
   };
 
-  constexpr std::array<uint64_t, 16> GPR8BitHighIndexes = {
+  static constexpr GPRArray GPR8BitHighIndexes = {
     // Classical ordering?
     FEXCore::X86State::REG_RAX,
     FEXCore::X86State::REG_RCX,
@@ -53,7 +66,7 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
     FEXCore::X86State::REG_R15,
   };
 
-  constexpr std::array<uint64_t, 16> XMMIndexes = {
+  static constexpr GPRArray XMMIndexes = {
     FEXCore::X86State::REG_XMM_0,
     FEXCore::X86State::REG_XMM_1,
     FEXCore::X86State::REG_XMM_2,
@@ -72,7 +85,7 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
     FEXCore::X86State::REG_XMM_15,
   };
 
-  constexpr std::array<uint64_t, 16> MMIndexes = {
+  static constexpr GPRArray MMIndexes = {
     FEXCore::X86State::REG_MM_0,
     FEXCore::X86State::REG_MM_1,
     FEXCore::X86State::REG_MM_2,
@@ -91,7 +104,7 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
     FEXCore::X86State::REG_INVALID
   };
 
-  const std::array<uint64_t, 16> *GPRs = &GPRIndexes;
+  const GPRArray *GPRs = &GPRIndexes;
   if (HasXMM) {
     GPRs = &XMMIndexes;
   }
@@ -111,44 +124,45 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
 }
 
 Decoder::Decoder(FEXCore::Context::Context *ctx)
-  : CTX {ctx} {
-  DecodedBuffer.resize(DefaultDecodedBufferSize);
+  : CTX {ctx}
+  , OSABI { ctx->SyscallHandler ? ctx->SyscallHandler->GetOSABI() : FEXCore::HLE::SyscallOSABI::OS_UNKNOWN } {
+  // Using mmap is a start-up time optimization
+  // Take advantage of page faulting to reduce startup time for minimal runtime cost
+  DecodedBuffer =
+    reinterpret_cast<FEXCore::X86Tables::DecodedInst *>(
+      FEXCore::Allocator::mmap(0, sizeof(FEXCore::X86Tables::DecodedInst) * DefaultDecodedBufferSize,
+      PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+}
+
+Decoder::~Decoder() {
+  FEXCore::Allocator::munmap(DecodedBuffer, sizeof(FEXCore::X86Tables::DecodedInst) * DefaultDecodedBufferSize);
 }
 
 uint8_t Decoder::ReadByte() {
   uint8_t Byte = InstStream[InstructionSize];
-  LogMan::Throw::A(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
+  LOGMAN_THROW_A(InstructionSize < MAX_INST_SIZE, "Max instruction size exceeded!");
   Instruction[InstructionSize] = Byte;
   InstructionSize++;
   return Byte;
 }
 
-uint8_t Decoder::PeekByte(uint8_t Offset) {
+uint8_t Decoder::PeekByte(uint8_t Offset) const {
   uint8_t Byte = InstStream[InstructionSize + Offset];
   return Byte;
 }
 
 uint64_t Decoder::ReadData(uint8_t Size) {
-  uint64_t Res{};
-#define READ_DATA(x, y) \
-  case x: { \
-    y const *Data = reinterpret_cast<y const*>(&InstStream[InstructionSize]); \
-    Res = *Data; \
-  } \
-  break
-
-  switch (Size) {
-  case 0: return 0;
-  READ_DATA(1, uint8_t);
-  READ_DATA(2, uint16_t);
-  case 3: memcpy(&Res, &InstStream[InstructionSize], Size);
-  READ_DATA(4, uint32_t);
-  READ_DATA(8, uint64_t);
-  default:
-  LogMan::Msg::A("Unknown data size to read");
-  return 0;
+  if (Size == 0) {
+    return 0;
   }
-#undef READ_DATA
+
+  if (Size > sizeof(uint64_t)) {
+    LOGMAN_MSG_A("Unknown data size to read");
+    return 0;
+  }
+
+  uint64_t Res = 0;
+  std::memcpy(&Res, &InstStream[InstructionSize], Size);
 
 #ifndef NDEBUG
   for(size_t i = 0; i < Size; ++i) {
@@ -157,6 +171,7 @@ uint64_t Decoder::ReadData(uint8_t Size) {
 #else
   SkipBytes(Size);
 #endif
+
   return Res;
 }
 
@@ -197,9 +212,9 @@ void Decoder::DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     }
   }
 
-  Operand->TypeSIB.Type = DecodedOperand::TYPE_SIB;
-  Operand->TypeSIB.Scale = 1;
-  Operand->TypeSIB.Offset = Literal;
+  Operand->Type = DecodedOperand::OpType::SIB;
+  Operand->Data.SIB.Scale = 1;
+  Operand->Data.SIB.Offset = Literal;
 
   // Only called when ModRM.mod != 0b11
   struct Encodings {
@@ -212,34 +227,34 @@ void Decoder::DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
-    {FEXCore::X86State::REG_RSI, 255},
-    {FEXCore::X86State::REG_RDI, 255},
-    {255, 255},
-    {FEXCore::X86State::REG_RBX, 255},
+    {FEXCore::X86State::REG_RSI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RDI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_INVALID, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_INVALID},
     // Mod = 0b01
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
-    {FEXCore::X86State::REG_RSI, 255},
-    {FEXCore::X86State::REG_RDI, 255},
-    {FEXCore::X86State::REG_RBP, 255},
-    {FEXCore::X86State::REG_RBX, 255},
+    {FEXCore::X86State::REG_RSI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RDI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_INVALID},
     // Mod = 0b10
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
-    {FEXCore::X86State::REG_RSI, 255},
-    {FEXCore::X86State::REG_RDI, 255},
-    {FEXCore::X86State::REG_RBP, 255},
-    {FEXCore::X86State::REG_RBX, 255},
+    {FEXCore::X86State::REG_RSI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RDI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_INVALID},
   }};
 
   uint8_t LookupIndex = ModRM.mod << 3 | ModRM.rm;
   auto it = Lookup[LookupIndex];
-  Operand->TypeSIB.Base = it.Base;
-  Operand->TypeSIB.Index = it.Index;
+  Operand->Data.SIB.Base = it.Base;
+  Operand->Data.SIB.Index = it.Index;
 }
 
 void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM) {
@@ -277,21 +292,21 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     }
 
     // SIB
-    Operand->TypeSIB.Type = DecodedOperand::TYPE_SIB;
-    Operand->TypeSIB.Scale = 1 << SIB.scale;
+    Operand->Type = DecodedOperand::OpType::SIB;
+    Operand->Data.SIB.Scale = 1 << SIB.scale;
 
     // The invalid encoding types are described at Table 1-12. "promoted nsigned is always non-zero"
-    Operand->TypeSIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
-    Operand->TypeSIB.Base  = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
+    Operand->Data.SIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
+    Operand->Data.SIB.Base  = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
 
     uint64_t Literal {0};
-    LogMan::Throw::A(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
+    LOGMAN_THROW_A(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
 
     Literal = ReadData(Displacement);
     if (Displacement == 1) {
       Literal = static_cast<int8_t>(Literal);
     }
-    Operand->TypeSIB.Offset = Literal;
+    Operand->Data.SIB.Offset = Literal;
   }
   else if (ModRM.mod == 0) {
     // Explained in Table 1-14. "Operand Addressing Using ModRM and SIB Bytes"
@@ -300,13 +315,13 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
       uint32_t Literal;
       Literal = ReadData(4);
 
-      Operand->TypeRIPLiteral.Type = DecodedOperand::TYPE_RIP_RELATIVE;
-      Operand->TypeRIPLiteral.Literal.u = Literal;
+      Operand->Type = DecodedOperand::OpType::RIPRelative;
+      Operand->Data.RIPLiteral.Value.u = Literal;
     }
     else {
       // Register-direct addressing
-      Operand->TypeGPR.Type = DecodedOperand::TYPE_GPR_DIRECT;
-      Operand->TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
+      Operand->Type = DecodedOperand::OpType::GPRDirect;
+      Operand->Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
     }
   }
   else {
@@ -318,9 +333,9 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     }
     Displacement = DisplacementSize;
 
-    Operand->TypeGPRIndirect.Type = DecodedOperand::TYPE_GPR_INDIRECT;
-    Operand->TypeGPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
-    Operand->TypeGPRIndirect.Displacement = Literal;
+    Operand->Type = DecodedOperand::OpType::GPRIndirect;
+    Operand->Data.GPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
+    Operand->Data.GPRIndirect.Displacement = Literal;
   }
 }
 
@@ -344,7 +359,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
     return false;
   }
 
-  LogMan::Throw::A(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P),
+  LOGMAN_THROW_A(!(Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 && Info->Type <= FEXCore::X86Tables::TYPE_GROUP_P),
     "Group Ops should have been decoded before this!");
 
   uint8_t DestSize{};
@@ -460,22 +475,25 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ||
       HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RDX)) {
     // Some instructions hardcode their destination as RAX
-    CurrentDest->TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    CurrentDest->TypeGPR.HighBits = false;
-    CurrentDest->TypeGPR.GPR = HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ? FEXCore::X86State::REG_RAX : FEXCore::X86State::REG_RDX;
+    CurrentDest->Type = DecodedOperand::OpType::GPR;
+    CurrentDest->Data.GPR.HighBits = false;
+    CurrentDest->Data.GPR.GPR = HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ? FEXCore::X86State::REG_RAX : FEXCore::X86State::REG_RDX;
     CurrentDest = &DecodeInst->Src[0];
   }
 
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_REX_IN_BYTE)) {
-    LogMan::Throw::A(!HasMODRM, "This instruction shouldn't have ModRM!");
+    LOGMAN_THROW_A(!HasMODRM, "This instruction shouldn't have ModRM!");
 
     // If the REX is in the byte that means the lower nibble of the OP contains the destination GPR
     // This also means that the destination is always a GPR on these ones
     // ADDITIONALLY:
     // If there is a REX prefix then that allows extended GPR usage
-    CurrentDest->TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    DecodeInst->Dest.TypeGPR.HighBits = (Is8BitDest && !HasREX && (Op & 0b111) >= 0b100) || HasHighXMM;
-    CurrentDest->TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, Op & 0b111, Is8BitDest, HasREX, false, false);
+    CurrentDest->Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Dest.Data.GPR.HighBits = (Is8BitDest && !HasREX && (Op & 0b111) >= 0b100) || HasHighXMM;
+    CurrentDest->Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, Op & 0b111, Is8BitDest, HasREX, false, false);
+
+    if (CurrentDest->Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
+      return false;
   }
 
   uint8_t Bytes = Info->MoreBytes;
@@ -498,55 +516,63 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
     ModRM.Hex = DecodeInst->ModRM;
 
     // Decode the GPR source first
-    GPR.TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    GPR.TypeGPR.HighBits = (GPR8Bit && ModRM.reg >= 0b100 && !HasREX) || HasHighXMM;
-    GPR.TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_R ? 1 : 0, ModRM.reg, GPR8Bit, HasREX, HasXMMGPR, HasMMGPR);
+    GPR.Type = DecodedOperand::OpType::GPR;
+    GPR.Data.GPR.HighBits = (GPR8Bit && ModRM.reg >= 0b100 && !HasREX) || HasHighXMM;
+    GPR.Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_R ? 1 : 0, ModRM.reg, GPR8Bit, HasREX, HasXMMGPR, HasMMGPR);
+
+    if (GPR.Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
+      return false;
 
     // ModRM.mod == 0b11 == Register
     // ModRM.Mod != 0b11 == Register-direct addressing
     if (ModRM.mod == 0b11) {
-      NonGPR.TypeGPR.Type = DecodedOperand::TYPE_GPR;
-      NonGPR.TypeGPR.HighBits = (NonGPR8Bit && ModRM.rm >= 0b100 && !HasREX) || HasHighXMM;
-      NonGPR.TypeGPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, NonGPR8Bit, HasREX, HasXMMNonGPR, HasMMNonGPR);
+      NonGPR.Type = DecodedOperand::OpType::GPR;
+      NonGPR.Data.GPR.HighBits = (NonGPR8Bit && ModRM.rm >= 0b100 && !HasREX) || HasHighXMM;
+      NonGPR.Data.GPR.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, NonGPR8Bit, HasREX, HasXMMNonGPR, HasMMNonGPR);
+      if (NonGPR.Data.GPR.GPR == FEXCore::X86State::REG_INVALID)
+        return false;
     }
     else {
       auto Disp = DecodeModRMs_Disp[Has16BitAddressing];
       (this->*Disp)(&NonGPR, ModRM);
     }
+
+    return true;
   };
 
   size_t CurrentSrc = 0;
 
   if (Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM) {
     if (Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SF_MOD_DST) {
-      ModRMOperand(DecodeInst->Src[CurrentSrc], DecodeInst->Dest, HasXMMSrc, HasXMMDst, HasMMSrc, HasMMDst, Is8BitSrc, Is8BitDest);
+      if (!ModRMOperand(DecodeInst->Src[CurrentSrc], DecodeInst->Dest, HasXMMSrc, HasXMMDst, HasMMSrc, HasMMDst, Is8BitSrc, Is8BitDest))
+        return false;
     }
     else {
-      ModRMOperand(DecodeInst->Dest, DecodeInst->Src[CurrentSrc], HasXMMDst, HasXMMSrc, HasMMDst, HasMMSrc, Is8BitDest, Is8BitSrc);
+      if (!ModRMOperand(DecodeInst->Dest, DecodeInst->Src[CurrentSrc], HasXMMDst, HasXMMSrc, HasMMDst, HasMMSrc, Is8BitDest, Is8BitSrc))
+        return false;
     }
     ++CurrentSrc;
   }
 
   if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_RAX)) {
-    DecodeInst->Src[CurrentSrc].TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    DecodeInst->Src[CurrentSrc].TypeGPR.HighBits = false;
-    DecodeInst->Src[CurrentSrc].TypeGPR.GPR = FEXCore::X86State::REG_RAX;
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
+    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = FEXCore::X86State::REG_RAX;
     ++CurrentSrc;
   }
   else if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_RCX)) {
-    DecodeInst->Src[CurrentSrc].TypeGPR.Type = DecodedOperand::TYPE_GPR;
-    DecodeInst->Src[CurrentSrc].TypeGPR.HighBits = false;
-    DecodeInst->Src[CurrentSrc].TypeGPR.GPR = FEXCore::X86State::REG_RCX;
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
+    DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
+    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = FEXCore::X86State::REG_RCX;
     ++CurrentSrc;
   }
 
   if (Bytes != 0) {
-    LogMan::Throw::A(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
+    LOGMAN_THROW_A(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
 
-    DecodeInst->Src[CurrentSrc].TypeLiteral.Size = Bytes;
+    DecodeInst->Src[CurrentSrc].Data.Literal.Size = Bytes;
 
-    uint64_t Literal {0};
-    Literal = ReadData(Bytes);
+    uint64_t Literal = ReadData(Bytes);
 
     if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SRC_SEXT) ||
         (DecodeFlags::GetSizeDstFlags(DecodeInst->Flags) == DecodeFlags::SIZE_64BIT && Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SRC_SEXT64BIT)) {
@@ -559,15 +585,15 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
       else {
         Literal = static_cast<int32_t>(Literal);
       }
-      DecodeInst->Src[CurrentSrc].TypeLiteral.Size = DestSize;
+      DecodeInst->Src[CurrentSrc].Data.Literal.Size = DestSize;
     }
 
     Bytes = 0;
-    DecodeInst->Src[CurrentSrc].TypeLiteral.Type = DecodedOperand::TYPE_LITERAL;
-    DecodeInst->Src[CurrentSrc].TypeLiteral.Literal = Literal;
+    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::Literal;
+    DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal;
   }
 
-  LogMan::Throw::A(Bytes == 0, "Inst at 0x%lx: 0x%04x '%s' Had an instruction of size %d with %d remaining", DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name, InstructionSize, Bytes);
+  LOGMAN_THROW_A(Bytes == 0, "Inst at 0x%lx: 0x%04x '%s' Had an instruction of size %d with %d remaining", DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name, InstructionSize, Bytes);
   DecodeInst->InstSize = InstructionSize;
   return true;
 }
@@ -592,7 +618,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
     return false;
   }
 
-  LogMan::Throw::A(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX, "REX PREFIX should have been decoded before this!");
+  LOGMAN_THROW_A(Info->Type != FEXCore::X86Tables::TYPE_REX_PREFIX, "REX PREFIX should have been decoded before this!");
 
   if (Info->Type >= FEXCore::X86Tables::TYPE_GROUP_1 &&
       Info->Type <= FEXCore::X86Tables::TYPE_GROUP_11) {
@@ -648,7 +674,7 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
         3,
       };
       uint8_t Field = RegToField[ModRM.reg];
-      LogMan::Throw::A(Field != 255, "Invalid field selected!");
+      LOGMAN_THROW_A(Field != 255, "Invalid field selected!");
 
       LocalOp = (Field << 3) | ModRM.rm;
       return NormalOp(&SecondModRMTableOps[LocalOp], LocalOp);
@@ -682,7 +708,10 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
       uint8_t Byte2 = ReadByte();
       pp = Byte2 & 0b11;
       map_select = Byte1 & 0b11111;
-      LogMan::Throw::A(map_select >= 1 && map_select <= 3, "We don't understand a map_select of: %d", map_select);
+      if (!(map_select >= 1 && map_select <= 3)) {
+        LogMan::Msg::E("We don't understand a map_select of: %d", map_select);
+        return false;
+      }
     }
 
     uint16_t VEXOp = ReadByte();
@@ -730,6 +759,8 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
   DecodeInst->PC = PC;
 
   for(;;) {
+    if (InstructionSize >= MAX_INST_SIZE)
+      return false;
     uint8_t Op = ReadByte();
     switch (Op) {
     case 0x0F: {// Escape Op
@@ -880,7 +911,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
       auto Info = &FEXCore::X86Tables::BaseOps[Op];
 
       if (Info->Type == FEXCore::X86Tables::TYPE_REX_PREFIX) {
-        LogMan::Throw::A(CTX->Config.Is64BitMode, "Got REX prefix in 32bit mode");
+        LOGMAN_THROW_A(CTX->Config.Is64BitMode, "Got REX prefix in 32bit mode");
         DecodeInst->Flags |= DecodeFlags::FLAG_REX_PREFIX;
 
         // Widening displacement
@@ -910,6 +941,10 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
 
   }
 
+  if (DecodeInst->Dest.IsGPR()) {
+    assert(DecodeInst->Dest.Data.GPR.GPR != FEXCore::X86State::REG_INVALID);
+  }
+
   return true;
 }
 
@@ -919,6 +954,7 @@ void Decoder::BranchTargetInMultiblockRange() {
 
   // If the RIP setting is conditional AND within our symbol range then it can be considered for multiblock
   uint64_t TargetRIP = 0;
+  const uint8_t GPRSize = CTX->GetGPRSize();
   bool Conditional = true;
 
   switch (DecodeInst->OP) {
@@ -928,24 +964,33 @@ void Decoder::BranchTargetInMultiblockRange() {
       // auto RIPOffset = LoadSource(Op, Op->Src[0], Op->Flags);
       // auto RIPTargetConst = _Constant(Op->PC + Op->InstSize);
       // Target offset is PC + InstSize + Literal
-      LogMan::Throw::A(DecodeInst->Src[0].TypeNone.Type == DecodedOperand::TYPE_LITERAL, "Had wrong operand type");
-      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].TypeLiteral.Literal;
+      LOGMAN_THROW_A(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
+      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
     break;
     }
     case 0xE9:
     case 0xEB: // Both are unconditional JMP instructions
-      LogMan::Throw::A(DecodeInst->Src[0].TypeNone.Type == DecodedOperand::TYPE_LITERAL, "Had wrong operand type");
-      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].TypeLiteral.Literal;
+      LOGMAN_THROW_A(DecodeInst->Src[0].IsLiteral(), "Had wrong operand type");
+      TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].Data.Literal.Value;
       Conditional = false;
     break;
+    case 0xE8: // Call - Immediate target, We don't want to inline calls
+      if (ExternalBranches) {
+        ExternalBranches->insert(DecodeInst->PC + DecodeInst->InstSize);
+      }
+      [[fallthrough]];
     case 0xC2: // RET imm
     case 0xC3: // RET
-    case 0xE8: // Call - Immediate target, We don't want to inline calls
     default:
       return;
     break;
   }
 
+  if (GPRSize == 4) {
+    // If we are running a 32bit guest then wrap around addresses that go above 32bit
+    TargetRIP &= 0xFFFFFFFFU;
+  }
+
   // If the target RIP is within the symbol ranges then we are golden
   if (TargetRIP >= SymbolMinAddress && TargetRIP < SymbolMaxAddress) {
     // Update our conditional branch ranges before we return
@@ -965,9 +1010,32 @@ void Decoder::BranchTargetInMultiblockRange() {
         BlocksToDecode.find(TargetRIP) == BlocksToDecode.end()) {
       BlocksToDecode.emplace(TargetRIP);
     }
+  } else {
+    if (ExternalBranches) {
+      ExternalBranches->insert(TargetRIP);
+    }
   }
 }
 
+const uint8_t *Decoder::AdjustAddrForSpecialRegion(uint8_t const* _InstStream, uint64_t EntryPoint, uint64_t RIP) {
+  constexpr uint64_t VSyscall_Base = 0xFFFF'FFFF'FF60'0000ULL;
+  constexpr uint64_t VSyscall_End = VSyscall_Base + 0x1000;
+
+  if (OSABI == FEXCore::HLE::SyscallOSABI::OS_LINUX64 &&
+      RIP >= VSyscall_Base &&
+      RIP < VSyscall_End) {
+    // VSyscall
+    // This doesn't exist on AArch64 and on x86_64 hosts this is emulated with faults to a region mapped with --xp permissions
+    // Offset     0: vgettimeofday
+    // Offset 0x400: vtime
+    // Offset 0x800: vgetcpu
+    uint64_t Offset = RIP - VSyscall_Base;
+    return VSyscallData + Offset;
+  }
+
+  return _InstStream - EntryPoint + RIP;
+}
+
 bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC) {
   Blocks.clear();
   BlocksToDecode.clear();
@@ -988,7 +1056,7 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
   // If we don't have symbols available then we become a bit optimistic about multiblock ranges
   if (!SymbolAvailable) {
     // If we don't have a symbol available then assume all branches are valid for multiblock
-    SymbolMaxAddress = ~0ULL;
+    SymbolMaxAddress = SectionMaxAddress;
     SymbolMinAddress = EntryPoint;
   }
 
@@ -1011,14 +1079,17 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
     uint64_t BlockStartOffset = DecodedSize;
 
     // Do a bit of pointer math to figure out where we are in code
-    InstStream = _InstStream - EntryPoint + RIPToDecode;
+    InstStream = AdjustAddrForSpecialRegion(_InstStream, EntryPoint, RIPToDecode);
 
     while (1) {
       ErrorDuringDecoding = !DecodeInstruction(RIPToDecode + PCOffset);
 
       if (ErrorDuringDecoding) {
         LogMan::Msg::D("Couldn't Decode something at 0x%lx, Started at 0x%lx", PC + PCOffset, PC);
-        LogMan::Throw::A(Blocks.size() != 1, "Decode Error in entry block");
+        if (Blocks.size() == 1) {
+          return false;
+        }
+        LOGMAN_THROW_A(Blocks.size() != 1, "Decode Error in entry block");
 
         CurrentBlockDecoding.HasInvalidInstruction = true;
         if (ErrorDuringDecoding && Blocks.size() != 1) {
@@ -1052,7 +1123,7 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
       }
 
       if (DecodedSize >= CTX->Config.MaxInstPerBlock ||
-          DecodedSize >= DecodedBuffer.size()) {
+          DecodedSize >= DefaultDecodedBufferSize) {
         break;
       }
 
@@ -1069,7 +1140,7 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
 
     // Copy over only the number of instructions we decoded
     CurrentBlockDecoding.NumInstructions = BlockNumberOfInstructions;
-    CurrentBlockDecoding.DecodedInstructions = &DecodedBuffer.at(BlockStartOffset);
+    CurrentBlockDecoding.DecodedInstructions = &DecodedBuffer[BlockStartOffset];
   }
 
 

External/FEXCore/Source/Interface/Core/Frontend.h

@@ -1,6 +1,8 @@
 #pragma once
 
 #include <FEXCore/Debug/X86Tables.h>
+#include <FEXCore/HLE/SyscallHandler.h>
+
 #include <array>
 #include <cstdint>
 #include <utility>
@@ -24,31 +26,35 @@ public:
   };
 
   Decoder(FEXCore::Context::Context *ctx);
+  ~Decoder();
   bool DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC);
 
-  std::vector<DecodedBlocks> const *GetDecodedBlocks() {
+  std::vector<DecodedBlocks> const *GetDecodedBlocks() const {
     return &Blocks;
   }
 
   uint64_t DecodedMinAddress {};
   uint64_t DecodedMaxAddress {~0ULL};
   
+  void SetSectionMaxAddress(uint64_t v) { SectionMaxAddress = v; }
+  void SetExternalBranches(std::set<uint64_t> *v) { ExternalBranches = v; }
 private:
   FEXCore::Context::Context *CTX;
+  const FEXCore::HLE::SyscallOSABI OSABI{};
 
   bool DecodeInstruction(uint64_t PC);
 
   void BranchTargetInMultiblockRange();
 
   uint8_t ReadByte();
-  uint8_t PeekByte(uint8_t Offset);
+  uint8_t PeekByte(uint8_t Offset) const;
   uint64_t ReadData(uint8_t Size);
   void SkipBytes(uint8_t Size) { InstructionSize += Size; }
   bool NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op);
   bool NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op);
 
   static constexpr size_t DefaultDecodedBufferSize = 0x10000;
-  std::vector<FEXCore::X86Tables::DecodedInst> DecodedBuffer;
+  FEXCore::X86Tables::DecodedInst *DecodedBuffer{};
   size_t DecodedSize {};
 
   uint8_t const *InstStream;
@@ -65,10 +71,12 @@ private:
   uint64_t MaxCondBranchBackwards {~0ULL};
   uint64_t SymbolMaxAddress {};
   uint64_t SymbolMinAddress {~0ULL};
+  uint64_t SectionMaxAddress {~0ULL};
 
   std::vector<DecodedBlocks> Blocks;
   std::set<uint64_t> BlocksToDecode;
   std::set<uint64_t> HasBlocks;
+  std::set<uint64_t> *ExternalBranches {nullptr};
 
   // ModRM rm decoding
   using DecodeModRMPtr = void (FEXCore::Frontend::Decoder::*)(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);
@@ -79,5 +87,7 @@ private:
     &FEXCore::Frontend::Decoder::DecodeModRM_64,
     &FEXCore::Frontend::Decoder::DecodeModRM_16,
   };
+
+  const uint8_t *AdjustAddrForSpecialRegion(uint8_t const* _InstStream, uint64_t EntryPoint, uint64_t RIP);
 };
 }

External/FEXCore/Source/Interface/Core/GdbServer.cpp

@@ -1,3 +1,10 @@
+/*
+$info$
+tags: glue|gdbserver
+desc: Provides a gdb interface to the guest state
+$end_info$
+*/
+
 #include <cstdlib>
 #include <cstdio>
 #include <iomanip>
@@ -8,15 +15,19 @@
 #include <optional>
 #include "Common/NetStream.h"
 #include "Common/SoftFloat.h"
+
+#include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/LogManager.h>
 
-#include <sys/types.h>
-#include <sys/socket.h>
-#include <netdb.h>
-#include <string.h>
+#include <cstring>
 #include <fcntl.h>
-#include <unistd.h>
+#include <fmt/format.h>
 #include <fstream>
+#include <netdb.h>
+#include <sys/socket.h>
+#include <sys/types.h>
+#include <unistd.h>
+
 
 #include "GdbServer.h"
 #include <FEXCore/Core/CodeLoader.h>
@@ -27,20 +38,20 @@ namespace FEXCore
 
 void GdbServer::Break(int signal) {
     std::lock_guard lk(sendMutex);
+    if (!CommsStream) {
+      return;
+    }
 
-    std::ostringstream ss;
-    ss << "S" << std::setfill('0') << std::setw(2) << std::hex << signal;
-
-    if (CommsStream)
-        SendPacket(*CommsStream, ss.str());
+    const auto str = fmt::format("S{:02x}", signal);
+    SendPacket(*CommsStream, str);
 }
 
 GdbServer::GdbServer(FEXCore::Context::Context *ctx) : CTX(ctx) {
-    ctx->CustomExitHandler = [this](uint64_t ThreadId, FEXCore::Context::ExitReason ExitReason) {
+    Context::SetExitHandler(ctx, [this](uint64_t ThreadId, FEXCore::Context::ExitReason ExitReason) {
         if (ExitReason == FEXCore::Context::ExitReason::EXIT_DEBUG) {
             this->Break(SIGTRAP);
         }
-    };
+    });
 
     // This is a total hack as there is currently no way to resume once hitting a segfault
     // But it's semi-useful for debugging.
@@ -53,12 +64,12 @@ GdbServer::GdbServer(FEXCore::Context::Context *ctx) : CTX(ctx) {
           usleep(100000);
 
         return true;
-    });
+    }, true);
 
     StartThread();
 }
 
-static int calculateChecksum(std::string &packet) {
+static int calculateChecksum(const std::string &packet) {
     unsigned char checksum = 0;
     for (const char &c : packet) {
         checksum += c;
@@ -92,11 +103,9 @@ static std::string encodeHex(unsigned char *data, size_t length) {
 }
 
 static std::string getThreadName(uint32_t ThreadID) {
-  std::fstream fs;
-  std::ostringstream ThreadFile;
-  ThreadFile << "/proc/" << getpid() << "/task/" << ThreadID << "/comm";
+  const auto ThreadFile = fmt::format("/proc/{}/task/{}/comm", getpid(), ThreadID);
+  std::fstream fs(ThreadFile, std::fstream::in | std::fstream::binary);
 
-  fs.open(ThreadFile.str(), std::fstream::in | std::fstream::binary);
   if (fs.is_open()) {
     std::string ThreadName;
     fs >> ThreadName;
@@ -128,7 +137,7 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
         switch(c) {
         case '$': // start of packet
             if (packet.size() != 0)
-                LogMan::Msg::E("Dropping unexpected data: \"%s\"", packet.c_str());
+                LogMan::Msg::EFmt("Dropping unexpected data: \"{}\"", packet);
 
             // clear any existing data, must have been a mistake.
             packet = std::string();
@@ -149,7 +158,7 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
             if (calculateChecksum(packet) == expected_checksum) {
                 return packet;
             } else {
-                LogMan::Msg::E("Received Invalid Packet: $%s#%02x %c%c", packet.c_str(), expected_checksum);
+                LogMan::Msg::EFmt("Received Invalid Packet: ${}#{:02x}", packet, expected_checksum);
             }
             break;
         }
@@ -162,10 +171,10 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
     return "";
 }
 
-static std::string escapePacket(std::string packet) {
+static std::string escapePacket(const std::string& packet) {
     std::ostringstream ss;
 
-    for(auto &c : packet) {
+    for(const auto &c : packet) {
         switch (c) {
         case '$':
         case '#':
@@ -184,13 +193,11 @@ static std::string escapePacket(std::string packet) {
     return ss.str();
 }
 
-void GdbServer::SendPacket(std::ostream &stream, std::string packet) {
-  auto escaped = escapePacket(packet);
-  std::ostringstream ss;
+void GdbServer::SendPacket(std::ostream &stream, const std::string& packet) {
+  const auto escaped = escapePacket(packet);
+  const auto str = fmt::format("${}#{:02x}", escaped, calculateChecksum(escaped));
 
-  ss << '$' << escaped << '#';
-  ss << std::setfill('0') << std::setw(2) << std::hex << (int)calculateChecksum(escaped);
-  stream << ss.str() << std::flush;
+  stream << str << std::flush;
 }
 
 void GdbServer::SendACK(std::ostream &stream, bool NACK) {
@@ -211,7 +218,7 @@ void GdbServer::SendACK(std::ostream &stream, bool NACK) {
   }
 }
 
-struct __attribute__((packed)) GDBContextDefinition {
+struct FEX_PACKED GDBContextDefinition {
   uint64_t gregs[16];
   uint64_t rip;
   uint32_t eflags;
@@ -232,17 +239,17 @@ std::string GdbServer::readRegs() {
   bool Found = false;
 
   for (auto &Thread : *Threads) {
-    if (Thread->State.ThreadManager.GetTID() != CurrentDebuggingThread) {
+    if (Thread->ThreadManager.GetTID() != CurrentDebuggingThread) {
       continue;
     }
-    state = Thread->State.State;
+    memcpy(&state, Thread->CurrentFrame, sizeof(state));
     Found = true;
     break;
   }
 
   if (!Found) {
     // If set to an invalid thread then just get the parent thread ID
-    state = CTX->GetCPUState();
+    memcpy(&state, CTX->ParentThread->CurrentFrame, sizeof(state));
   }
 
   // Encode the GDB context definition
@@ -272,7 +279,7 @@ std::string GdbServer::readRegs() {
   return encodeHex((unsigned char *)&GDB, sizeof(GDBContextDefinition));
 }
 
-GdbServer::HandledPacketType GdbServer::readReg(std::string& packet) {
+GdbServer::HandledPacketType GdbServer::readReg(const std::string& packet) {
 	size_t addr;
 	auto ss = std::istringstream(packet);
 	ss.get(); // Drop first letter
@@ -284,17 +291,17 @@ GdbServer::HandledPacketType GdbServer::readReg(std::string& packet) {
   bool Found = false;
 
   for (auto &Thread : *Threads) {
-    if (Thread->State.ThreadManager.GetTID() != CurrentDebuggingThread) {
+    if (Thread->ThreadManager.GetTID() != CurrentDebuggingThread) {
       continue;
     }
-    state = Thread->State.State;
+    memcpy(&state, Thread->CurrentFrame, sizeof(state));
     Found = true;
     break;
   }
 
   if (!Found) {
     // If set to an invalid thread then just get the parent thread ID
-    state = CTX->GetCPUState();
+    memcpy(&state, CTX->ParentThread->CurrentFrame, sizeof(state));
   }
 
 
@@ -350,7 +357,7 @@ GdbServer::HandledPacketType GdbServer::readReg(std::string& packet) {
     return {encodeHex((unsigned char *)(&Empty), sizeof(uint32_t)), HandledPacketType::TYPE_ACK};
   }
 
-  LogMan::Msg::E("Unknown GDB register 0x%lx", addr);
+  LogMan::Msg::EFmt("Unknown GDB register 0x{:x}", addr);
   return {"E00", HandledPacketType::TYPE_ACK};
 }
 
@@ -455,7 +462,7 @@ std::string buildTargetXML() {
     return xml.str();
 }
 
-GdbServer::HandledPacketType GdbServer::handleXfer(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
     std::string object;
     std::string rw;
     std::string annex;
@@ -525,7 +532,7 @@ GdbServer::HandledPacketType GdbServer::handleXfer(std::string &packet) {
         ss << "<threads>\n";
         for (size_t i = 0; i < Threads->size(); ++i) {
           auto Thread = Threads->at(i);
-          ss << "\t<thread id=\"" << std::hex << Thread->State.ThreadManager.GetTID() << "\" core=\"" << i << "\" name=\"" <<  getThreadName(Thread->State.ThreadManager.GetTID()) << "\">\n";
+          ss << "\t<thread id=\"" << std::hex << Thread->ThreadManager.GetTID() << "\" core=\"" << i << "\" name=\"" <<  getThreadName(Thread->ThreadManager.GetTID()) << "\">\n";
           ss << "\t</thread>\n";
         }
 
@@ -541,10 +548,9 @@ GdbServer::HandledPacketType GdbServer::handleXfer(std::string &packet) {
 
 static size_t CheckMemMapping(uint64_t Address, size_t Size) {
   uint64_t AddressEnd = Address + Size;
-
-  std::fstream fs;
-  fs.open("/proc/self/maps", std::fstream::in | std::fstream::binary);
+  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
   std::string Line;
+
   while (std::getline(fs, Line)) {
     if (fs.eof()) break;
     uint64_t Begin, End;
@@ -561,32 +567,29 @@ static size_t CheckMemMapping(uint64_t Address, size_t Size) {
     }
   }
 
-  fs.close();
   return 0;
 }
 
 GdbServer::HandledPacketType GdbServer::handleProgramOffsets() {
-  std::fstream fs;
-  fs.open("/proc/self/maps", std::fstream::in | std::fstream::binary);
+  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
   std::string Line;
   std::string const &RuntimeExecutable = Filename();
+
   while (std::getline(fs, Line)) {
     uint64_t Begin, End;
     char Filename[255];
     if (sscanf(Line.c_str(), "%lx-%lx %*c%*c%*c%*c %*x %*x:%*x %*d%s", &Begin, &End, Filename) == 3) {
       if (RuntimeExecutable == Filename) {
-        std::ostringstream ss;
-        ss << "Text=" << std::hex << Begin << ";Data=" << std::hex << Begin << ";Bss=" << std::hex << Begin;
-        ss << std::flush;
-        return {ss.str(), HandledPacketType::TYPE_ACK};
+        auto str = fmt::format("Text={:x};Data={:x};Bss={:x}", Begin, Begin, Begin);
+        return {std::move(str), HandledPacketType::TYPE_ACK};
       }
     }
   }
-  fs.close();
+
   return {"Text=0;Data=0;Bss=0", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::handleMemory(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleMemory(const std::string &packet) {
     bool write;
     size_t addr;
     size_t length;
@@ -627,8 +630,8 @@ GdbServer::HandledPacketType GdbServer::handleMemory(std::string &packet) {
 }
 
 
-GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
-  auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
+GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
+  const auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
 
   if (match("qSupported")) {
     return {"PacketSize=5000;xmlRegisters=i386;qXfer:exec-file:read+;qXfer:features:read+;", HandledPacketType::TYPE_ACK};
@@ -653,7 +656,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
     ss << "m";
     for (size_t i = 0; i < Threads->size(); ++i) {
       auto Thread = Threads->at(i);
-      ss << std::hex << Thread->State.ThreadManager.TID << ",";
+      ss << std::hex << Thread->ThreadManager.TID << ",";
     }
     return {ss.str(), HandledPacketType::TYPE_ACK};
   }
@@ -672,7 +675,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
   if (match("qC")) {
     // Returns the current Thread ID
     std::ostringstream ss;
-    ss << "m" <<  std::hex << CTX->ParentThread->State.ThreadManager.TID;
+    ss << "m" <<  std::hex << CTX->ParentThread->ThreadManager.TID;
     return {ss.str(), HandledPacketType::TYPE_ACK};
   }
   if (match("QStartNoAckMode")) {
@@ -686,8 +689,8 @@ GdbServer::HandledPacketType GdbServer::handleQuery(std::string &packet) {
   return {"", HandledPacketType::TYPE_UNKNOWN};
 }
 
-GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
-    auto match = [&](std::string str) -> std::optional<std::istringstream> {
+GdbServer::HandledPacketType GdbServer::handleV(const std::string& packet) {
+    const auto match = [&](const std::string& str) -> std::optional<std::istringstream> {
         if (packet.rfind(str, 0) == 0) {
             auto ss = std::istringstream(packet);
             ss.seekg(str.size());
@@ -696,18 +699,11 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
         return std::nullopt;
     };
 
-    auto F = [](int result) {
-        std::ostringstream ss;
-        ss << "F" << std::hex << result;
-        return ss.str(); };
-    auto F_error = [&]() {
-        std::ostringstream ss;
-        ss << "F-1," << std::hex << errno;
-        return ss.str(); };
-    auto F_data = [&](int result, std::string data) {
-        std::ostringstream ss;
-        ss << "F" << std::hex << result << ";" << data;
-        return ss.str(); };
+    const auto F       = [](int result) { return fmt::format("F{:x}", result); };
+    const auto F_error = [] { return fmt::format("F-1,{:x}", errno); };
+    const auto F_data  = [](int result, const std::string& data) {
+        return fmt::format("F{:x};{}", result, data);
+    };
 
     std::optional<std::istringstream> ss;
     if((ss = match("vFile:open:"))) {
@@ -729,11 +725,11 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
         return {F(pid == 0 ? 0 : -1), HandledPacketType::TYPE_ACK}; // Only support the common filesystem
     }
     if((ss = match("vFile:close:"))) {
-			int fd;
-			*ss >> std::hex >> fd;
-			close(fd);
-			return {F(0), HandledPacketType::TYPE_ACK};
-		}
+      int fd;
+      *ss >> std::hex >> fd;
+      close(fd);
+      return {F(0), HandledPacketType::TYPE_ACK};
+    }
     if((ss = match("vFile:pread:"))) {
         int fd, count, offset;
 
@@ -770,7 +766,7 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
         }
 
         if (ss->fail()) {
- 						return {"E00", HandledPacketType::TYPE_ACK};
+            return {"E00", HandledPacketType::TYPE_ACK};
         }
 
         switch (action) {
@@ -780,27 +776,25 @@ GdbServer::HandledPacketType GdbServer::handleV(std::string& packet) {
           }
         case 's': {
             CTX->Step();
-						SendPacketPair({"OK", HandledPacketType::TYPE_ACK});
-            std::ostringstream ss;
-            ss << "T05thread:" << std::setfill('0') << std::setw(2) << std::hex << getpid() << ";core:2c;";
-
-            SendPacketPair({ss.str(), HandledPacketType::TYPE_ACK});
+            SendPacketPair({"OK", HandledPacketType::TYPE_ACK});
+            auto str = fmt::format("T05thread:{:02x};core:2c;", getpid());
+            SendPacketPair({std::move(str), HandledPacketType::TYPE_ACK});
             return {"OK", HandledPacketType::TYPE_ACK};
           }
         case 't':
             // This thread isn't part of the thread pool
             CTX->Stop(false /* Ignore current thread */);
- 						return {"OK", HandledPacketType::TYPE_ACK};
+            return {"OK", HandledPacketType::TYPE_ACK};
         default:
- 						return {"E00", HandledPacketType::TYPE_ACK};
+            return {"E00", HandledPacketType::TYPE_ACK};
         }
 
     }
-		return {"", HandledPacketType::TYPE_ACK};
+    return {"", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::handleThreadOp(std::string &packet) {
-  auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
+GdbServer::HandledPacketType GdbServer::handleThreadOp(const std::string &packet) {
+  const auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
 
   if (match("Hc")) {
     // Sets thread to this ID for stepping
@@ -816,7 +810,7 @@ GdbServer::HandledPacketType GdbServer::handleThreadOp(std::string &packet) {
   if (match("Hg")) {
     // Sets thread for "other" operations
     auto ss = std::istringstream(packet);
-    ss.seekg(std::string("Hg").size());
+    ss.seekg(std::string_view("Hg").size());
     ss >> std::hex >> CurrentDebuggingThread;
 
     // This must return quick otherwise IDA complains
@@ -827,7 +821,7 @@ GdbServer::HandledPacketType GdbServer::handleThreadOp(std::string &packet) {
   return {"", HandledPacketType::TYPE_UNKNOWN};
 }
 
-GdbServer::HandledPacketType GdbServer::handleBreakpoint(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleBreakpoint(const std::string &packet) {
   auto ss = std::istringstream(packet);
 
   bool Set{};
@@ -843,17 +837,15 @@ GdbServer::HandledPacketType GdbServer::handleBreakpoint(std::string &packet) {
   return {"OK", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::ProcessPacket(std::string &packet) {
+GdbServer::HandledPacketType GdbServer::ProcessPacket(const std::string &packet) {
   switch (packet[0]) {
     case '?': {
       // Indicates the reason that the thread has stopped
       // Behaviour changes if the target is in non-stop mode
       // Binja doesn't support S response here
       //return {"S00", HandledPacketType::TYPE_ACK};
-      std::ostringstream ss;
-      ss << "T00thread:" << std::setfill('0') << std::setw(2) << std::hex << getpid() << ";core:2c;";
-
-      return {ss.str(), HandledPacketType::TYPE_ACK};
+      auto str = fmt::format("T00thread:{:02x};core:2c;", getpid());
+      return {std::move(str), HandledPacketType::TYPE_ACK};
     }
     case 'g':
       return {readRegs(), HandledPacketType::TYPE_ACK};
@@ -883,14 +875,14 @@ GdbServer::HandledPacketType GdbServer::ProcessPacket(std::string &packet) {
   }
 }
 
-void GdbServer::SendPacketPair(HandledPacketType response) {
+void GdbServer::SendPacketPair(const HandledPacketType& response) {
   std::lock_guard lk(sendMutex);
   if (response.TypeResponse == HandledPacketType::TYPE_ACK ||
       response.TypeResponse == HandledPacketType::TYPE_ONLYACK) {
     SendACK(*CommsStream, false);
   }
   else if (response.TypeResponse == HandledPacketType::TYPE_NACK ||
-      response.TypeResponse == HandledPacketType::TYPE_ONLYNACK) {
+           response.TypeResponse == HandledPacketType::TYPE_ONLYNACK) {
     SendACK(*CommsStream, true);
   }
 
@@ -898,8 +890,8 @@ void GdbServer::SendPacketPair(HandledPacketType response) {
     SendPacket(*CommsStream, "");
   }
   else if (response.TypeResponse != HandledPacketType::TYPE_ONLYNACK &&
-      response.TypeResponse != HandledPacketType::TYPE_ONLYACK &&
-      response.TypeResponse != HandledPacketType::TYPE_NONE) {
+           response.TypeResponse != HandledPacketType::TYPE_ONLYACK &&
+           response.TypeResponse != HandledPacketType::TYPE_NONE) {
     SendPacket(*CommsStream, response.Response);
   }
 }
@@ -920,7 +912,7 @@ void GdbServer::GdbServerLoop() {
             response = ProcessPacket(packet);
             SendPacketPair(response);
             if (response.TypeResponse == HandledPacketType::TYPE_UNKNOWN) {
-              LogMan::Msg::D("Unknown packet %s", packet.c_str());
+              LogMan::Msg::DFmt("Unknown packet {}", packet);
             }
             break;
         }
@@ -936,25 +928,29 @@ void GdbServer::GdbServerLoop() {
             break;
         case '\x03': { // ASCII EOT
             CTX->Pause();
-            std::ostringstream ss;
-            ss << "T02thread:" << std::setfill('0') << std::setw(2) << std::hex << getpid() << ";core:2c;";
-            SendPacketPair({ss.str(), HandledPacketType::TYPE_ACK});
+            auto str = fmt::format("T02thread:{:02x};core:2c;", getpid());
+            SendPacketPair({std::move(str), HandledPacketType::TYPE_ACK});
             break;
           }
         default:
-            LogMan::Msg::D("GdbServer: Unexpected byte %c (%02x)", c, c);
+            LogMan::Msg::DFmt("GdbServer: Unexpected byte {} ({:02x})", static_cast<char>(c), c);
         }
     }
 
     {
         std::lock_guard lk(sendMutex);
-        CommsStream.release();
+        CommsStream.reset();
     }
   }
 }
+static void* ThreadHandler(void *Arg) {
+  FEXCore::GdbServer *This = reinterpret_cast<FEXCore::GdbServer*>(Arg);
+  This->GdbServerLoop();
+  return nullptr;
+}
 
 void GdbServer::StartThread() {
-    gdbServerThread = std::thread(&GdbServer::GdbServerLoop, this);
+    gdbServerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
 }
 
 std::unique_ptr<std::iostream> GdbServer::OpenSocket() {
@@ -991,7 +987,7 @@ std::unique_ptr<std::iostream> GdbServer::OpenSocket() {
 
     // Block until a connection arrives
 
-    LogMan::Msg::I("GdbServer, waiting for connection on localhost:8086");
+    LogMan::Msg::IFmt("GdbServer, waiting for connection on localhost:8086");
     listen(sockfd, 1);
 
     new_fd = accept(sockfd, (struct sockaddr *)&their_addr, &addr_size);

External/FEXCore/Source/Interface/Core/GdbServer.h

@@ -1,25 +1,36 @@
+/*
+$info$
+tags: glue|gdbserver
+$end_info$
+*/
+#pragma once
 
 #include <mutex>
 #include <thread>
 
 #include "Interface/Context/Context.h"
-
 #include "Common/NetStream.h"
 
+#include <FEXCore/Utils/Threads.h>
+
+#include <mutex>
+
 namespace FEXCore {
 
 class GdbServer {
 public:
     GdbServer(FEXCore::Context::Context *ctx);
 
+    // Public for threading
+    void GdbServerLoop();
+
 private:
     void Break(int signal);
 
     std::unique_ptr<std::iostream> OpenSocket();
     void StartThread();
-    void GdbServerLoop();
     std::string ReadPacket(std::iostream &stream);
-    void SendPacket(std::ostream &stream, std::string packet);
+    void SendPacket(std::ostream &stream, const std::string& packet);
 
     void SendACK(std::ostream &stream, bool NACK);
 
@@ -36,28 +47,28 @@ private:
       ResponseType TypeResponse{};
     };
 
-    void SendPacketPair(HandledPacketType packetPair);
-    HandledPacketType ProcessPacket(std::string &packet);
-    HandledPacketType handleQuery(std::string &packet);
-    HandledPacketType handleXfer(std::string &packet);
-    HandledPacketType handleMemory(std::string &packet);
-    HandledPacketType handleV(std::string& packet);
-    HandledPacketType handleThreadOp(std::string &packet);
-    HandledPacketType handleBreakpoint(std::string &packet);
+    void SendPacketPair(const HandledPacketType& packetPair);
+    HandledPacketType ProcessPacket(const std::string &packet);
+    HandledPacketType handleQuery(const std::string &packet);
+    HandledPacketType handleXfer(const std::string &packet);
+    HandledPacketType handleMemory(const std::string &packet);
+    HandledPacketType handleV(const std::string& packet);
+    HandledPacketType handleThreadOp(const std::string &packet);
+    HandledPacketType handleBreakpoint(const std::string &packet);
     HandledPacketType handleProgramOffsets();
 
     std::string readRegs();
-    HandledPacketType readReg(std::string& packet);
+    HandledPacketType readReg(const std::string& packet);
 
     FEXCore::Context::Context *CTX;
-    std::thread gdbServerThread;
+    std::unique_ptr<FEXCore::Threads::Thread> gdbServerThread;
     std::unique_ptr<std::iostream> CommsStream;
     std::mutex sendMutex;
     bool SettingNoAckMode{false};
     bool NoAckMode{false};
     std::string ThreadString{};
     uint32_t CurrentDebuggingThread{};
-    FEXCore::Config::Value<std::string> Filename{FEXCore::Config::CONFIG_APP_FILENAME, ""};
+    FEX_CONFIG_OPT(Filename, APP_FILENAME);
 };
 
 }

External/FEXCore/Source/Interface/Core/Interpreter/Arm64Dispatcher.cpp

@@ -1,563 +0,0 @@
-#include "Common/MathUtils.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include <FEXCore/Core/X86Enums.h>
-
-#include <cmath>
-
-#include "aarch64/assembler-aarch64.h"
-#include "aarch64/cpu-aarch64.h"
-#include "aarch64/disasm-aarch64.h"
-#include "aarch64/assembler-aarch64.h"
-
-namespace FEXCore::CPU {
-static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  --ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-
-  // Go to sleep
-  Thread->StartRunning.Wait();
-
-  Thread->State.RunningEvents.Running = true;
-  ++ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-}
-
-using namespace vixl;
-using namespace vixl::aarch64;
-
-#define STATE x28
-static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
-
-class DispatchGenerator : public vixl::aarch64::Assembler {
-  public:
-    DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread);
-    bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
-    bool HandleSignalPause(int Signal, void *info, void *ucontext);
-
-  CPUBackend::AsmDispatch DispatchPtr;
-  CPUBackend::JITCallback CallbackPtr;
-
-  uint64_t ThreadStopHandlerAddress;
-  uint64_t AbsoluteLoopTopAddress;
-  uint64_t ThreadPauseHandlerAddress;
-  FEXCore::Context::Context *CTX;
-  FEXCore::Core::InternalThreadState *State;
-  private:
-    void StoreThreadState(int Signal, void *ucontext);
-    void RestoreThreadState(void *ucontext);
-    void PushCalleeSavedRegisters();
-    void PopCalleeSavedRegisters();
-    void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant);
-    std::stack<uint64_t> SignalFrames;
-};
-
-void DispatchGenerator::PushCalleeSavedRegisters() {
-  // We need to save pairs of registers
-  // We save r19-r30
-  MemOperand PairOffset(sp, -16, PreIndex);
-  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
-    {x19, x20},
-    {x21, x22},
-    {x23, x24},
-    {x25, x26},
-    {x27, x28},
-    {x29, x30},
-  }};
-
-  for (auto &RegPair : CalleeSaved) {
-    stp(RegPair.first, RegPair.second, PairOffset);
-  }
-
-  // Additionally we need to store the lower 64bits of v8-v15
-  // Here's a fun thing, we can use two ST4 instructions to store everything
-  // We just need a single sub to sp before that
-  const std::array<
-    std::tuple<vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister>, 2> FPRs = {{
-    {v8, v9, v10, v11},
-    {v12, v13, v14, v15},
-  }};
-
-  uint32_t VectorSaveSize = sizeof(uint64_t) * 8;
-  sub(sp, sp, VectorSaveSize);
-  // SP supporting move
-  // We just saved x19 so it is safe
-  add(x19, sp, 0);
-
-  MemOperand QuadOffset(x19, 32, PostIndex);
-  for (auto &RegQuad : FPRs) {
-    st4(std::get<0>(RegQuad).D(),
-        std::get<1>(RegQuad).D(),
-        std::get<2>(RegQuad).D(),
-        std::get<3>(RegQuad).D(),
-        0,
-        QuadOffset);
-  }
-}
-
-void DispatchGenerator::PopCalleeSavedRegisters() {
-  const std::array<
-    std::tuple<vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister,
-               vixl::aarch64::VRegister>, 2> FPRs = {{
-    {v12, v13, v14, v15},
-    {v8, v9, v10, v11},
-  }};
-
-  MemOperand QuadOffset(sp, 32, PostIndex);
-  for (auto &RegQuad : FPRs) {
-    ld4(std::get<0>(RegQuad).D(),
-        std::get<1>(RegQuad).D(),
-        std::get<2>(RegQuad).D(),
-        std::get<3>(RegQuad).D(),
-        0,
-        QuadOffset);
-  }
-
-  MemOperand PairOffset(sp, 16, PostIndex);
-  const std::array<std::pair<vixl::aarch64::XRegister, vixl::aarch64::XRegister>, 6> CalleeSaved = {{
-    {x29, x30},
-    {x27, x28},
-    {x25, x26},
-    {x23, x24},
-    {x21, x22},
-    {x19, x20},
-  }};
-
-  for (auto &RegPair : CalleeSaved) {
-    ldp(RegPair.first, RegPair.second, PairOffset);
-  }
-}
-
-void DispatchGenerator::LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant) {
-  bool Is64Bit = Reg.IsX();
-  int Segments = Is64Bit ? 4 : 2;
-
-  movz(Reg, (Constant) & 0xFFFF, 0);
-  for (int i = 1; i < Segments; ++i) {
-    uint16_t Part = (Constant >> (i * 16)) & 0xFFFF;
-    if (Part) {
-      movk(Reg, Part, i * 16);
-    }
-  }
-}
-
-DispatchGenerator::DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
-  : vixl::aarch64::Assembler(MAX_DISPATCHER_CODE_SIZE, vixl::aarch64::PositionDependentCode)
-  , CTX {ctx}
-  , State {Thread} {
-
-  SetAllowAssembler(true);
-  auto Buffer = GetBuffer();
-
-  DispatchPtr = Buffer->GetOffsetAddress<CPUBackend::AsmDispatch>(GetCursorOffset());
-
-  // while (!Thread->State.RunningEvents.ShouldStop.load()) {
-  //    Ptr = FindBlock(RIP)
-  //    if (!Ptr)
-  //      Ptr = CTX->CompileBlock(RIP);
-  //
-  //    if (Ptr)
-  //      Ptr();
-  //    else
-  //    {
-  //      Ptr = FallbackCore->CompileBlock()
-  //      if (Ptr)
-  //        Ptr()
-  //      else {
-  //        ShouldStop = true;
-  //      }
-  //    }
-  // }
-
-  // Push all the register we need to save
-  PushCalleeSavedRegisters();
-
-  // Push our memory base to the correct register
-  // Move our thread pointer to the correct register
-  // This is passed in to parameter 0 (x0)
-  mov(STATE, x0);
-
-  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
-  // regardless of where we were in the stack
-  add(x0, sp, 0);
-  str(x0, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)));
-
-  Label Exit;
-  Label LoopTop;
-  Label NoBlock;
-  Label ThreadPauseHandler;
-  bind(&LoopTop);
-  AbsoluteLoopTopAddress = GetLabelAddress<uint64_t>(&LoopTop);
-
-  // Load in our RIP
-  // Don't modify x2 since it contains our RIP once the block doesn't exist
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, State.rip)));
-  auto RipReg = x2;
-
-  // Mask the address by the virtual address size so we can check for aliases
-  LoadConstant(x3, Thread->LookupCache->GetVirtualMemorySize() - 1);
-  and_(x3, RipReg, x3);
-
-  {
-    // This is the block cache lookup routine
-    // It matches what is going on it LookupCache.h::FindBlock
-    LoadConstant(x0, Thread->LookupCache->GetPagePointer());
-
-    // Offset the address and add to our page pointer
-    lsr(x1, x3, 12);
-
-    // Load the pointer from the offset
-    ldr(x0, MemOperand(x0, x1, Shift::LSL, 3));
-
-    // If page pointer is zero then we have no block
-    cbz(x0, &NoBlock);
-
-    // Steal the page offset
-    and_(x1, x3, 0x0FFF);
-
-    // Shift the offset by the size of the block cache entry
-    add(x0, x0, Operand(x1, Shift::LSL, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry))));
-
-    // Load the guest address first to ensure it maps to the address we are currently at
-    // This fixes aliasing problems
-    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, GuestCode)));
-    cmp(x1, RipReg);
-    b(&NoBlock, Condition::ne);
-
-    // Now load the actual host block to execute if we can
-    ldr(x1, MemOperand(x0, offsetof(FEXCore::LookupCache::LookupCacheEntry, HostCode)));
-    cbz(x1, &NoBlock);
-
-    // If we've made it here then we have a real compiled block
-    {
-      mov(x0, STATE);
-      blr(x1);
-    }
-
-    if (CTX->GetGdbServerStatus()) {
-      // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
-      // This happens when single stepping
-
-      static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
-      ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, CTX)));
-      ldr(w0, MemOperand(x0, offsetof(FEXCore::Context::Context, Config.RunningMode)));
-      // If the value == 0 then branch to the top
-      cbz(x0, &LoopTop);
-      // Else we need to pause now
-      b(&ThreadPauseHandler);
-    }
-    else {
-      // Unconditionally loop to the top
-      // We will only stop on error when compiling a block or signal
-      b(&LoopTop);
-    }
-  }
-
-  {
-    bind(&Exit);
-    ThreadStopHandlerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-    PopCalleeSavedRegisters();
-
-    // Return from the function
-    // LR is set to the correct return location now
-    ret();
-  }
-
-  // Need to create the block
-  {
-    bind(&NoBlock);
-
-    ldr(x0, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, CTX)));
-    mov(x1, STATE);
-
-    using ClassPtrType = uintptr_t (FEXCore::Context::Context::*)(FEXCore::Core::InternalThreadState *, uint64_t);
-    union PtrCast {
-      ClassPtrType ClassPtr;
-      uintptr_t Data;
-    };
-
-    PtrCast Ptr;
-    Ptr.ClassPtr = &FEXCore::Context::Context::CompileBlock;
-    LoadConstant(x3, Ptr.Data);
-
-    // X2 contains our guest RIP
-    blr(x3); // { CTX, ThreadState, RIP}
-
-    b(&LoopTop);
-  }
-
-  {
-    bind(&ThreadPauseHandler);
-    ThreadPauseHandlerAddress = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-    // We are pausing, this means the frontend should be waiting for this thread to idle
-    // We will have faulted and jumped to this location at this point
-
-    // Call our sleep handler
-    LoadConstant(x0, reinterpret_cast<uintptr_t>(CTX));
-    mov(x1, STATE);
-    LoadConstant(x2, reinterpret_cast<uint64_t>(SleepThread));
-    blr(x2);
-
-    // XXX: Unsupported atm
-    //PauseReturnInstruction = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-    //// Fault to start running again
-    //hlt(0);
-  }
-
-  {
-    CallbackPtr = Buffer->GetOffsetAddress<CPUBackend::JITCallback>(GetCursorOffset());
-
-    // We expect the thunk to have previously pushed the registers it was using
-    PushCalleeSavedRegisters();
-
-    // First thing we need to move the thread state pointer back in to our register
-    mov(STATE, x0);
-
-    // Now push the callback return trampoline to the guest stack
-    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
-    LoadConstant(x0, CTX->X86CodeGen.CallbackReturn);
-
-    ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
-    sub(x2, x2, 16);
-    str(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
-
-    // Store the trampoline to the guest stack
-    // Guest stack is now correctly misaligned after a regular call instruction
-    str(x0, MemOperand(x2));
-
-    // Store RIP to the context state
-    str(x1, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.rip)));
-
-    // Now go back to the regular dispatcher loop
-    b(&LoopTop);
-  }
-
-  FinalizeCode();
-  uint64_t CodeEnd = Buffer->GetOffsetAddress<uint64_t>(GetCursorOffset());
-  vixl::aarch64::CPU::EnsureIAndDCacheCoherency(reinterpret_cast<void*>(DispatchPtr), CodeEnd - reinterpret_cast<uint64_t>(DispatchPtr));
-  GetBuffer()->SetExecutable();
-}
-
-
-struct HostCTXHeader {
-  uint32_t Magic;
-  uint32_t Size;
-};
-
-constexpr uint32_t FPR_MAGIC = 0x46508001U;
-
-struct HostFPRState {
-  HostCTXHeader Head;
-  uint32_t FPSR;
-  uint32_t FPCR;
-  __uint128_t FPRs[32];
-};
-
-struct ContextBackup {
-  // Host State
-  uint64_t GPRs[31];
-  uint64_t PrevSP;
-  uint64_t PrevPC;
-  uint64_t PState;
-  uint32_t FPSR;
-  uint32_t FPCR;
-  __uint128_t FPRs[32];
-
-  // Guest state
-  int Signal;
-  FEXCore::Core::CPUState GuestState;
-};
-
-void DispatchGenerator::StoreThreadState(int Signal, void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  // We can end up getting a signal at any point in our host state
-  // Jump to a handler that saves all state so we can safely return
-  uint64_t OldSP = _mcontext->sp;
-  uintptr_t NewSP = OldSP;
-
-  size_t StackOffset = sizeof(ContextBackup);
-  NewSP -= StackOffset;
-  NewSP = AlignDown(NewSP, 16);
-
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-  memcpy(&Context->GPRs[0], &_mcontext->regs[0], 31 * sizeof(uint64_t));
-  Context->PrevSP = _mcontext->sp;
-  Context->PrevPC = _mcontext->pc;
-  Context->PState = _mcontext->pstate;
-
-  // Host FPR state starts at _mcontext->reserved[0];
-  HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
-  LogMan::Throw::A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
-  Context->FPSR = HostState->FPSR;
-  Context->FPCR = HostState->FPCR;
-  memcpy(&Context->FPRs[0], &HostState->FPRs[0], 32 * sizeof(__uint128_t));
-
-  // Retain the action pointer so we can see it when we return
-  Context->Signal = Signal;
-
-  // Save guest state
-  // We can't guarantee if registers are in context or host GPRs
-  // So we need to save everything
-  memcpy(&Context->GuestState, &State->State, sizeof(FEXCore::Core::CPUState));
-
-  // Set the new SP
-  _mcontext->sp = NewSP;
-}
-
-void DispatchGenerator::RestoreThreadState(void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  uint64_t OldSP = _mcontext->sp;
-  uintptr_t NewSP = OldSP;
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-
-  // First thing, reset the guest state
-  memcpy(&State->State, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
-
-  // Now restore host state
-  HostFPRState *HostState = reinterpret_cast<HostFPRState*>(&_mcontext->__reserved[0]);
-  LogMan::Throw::A(HostState->Head.Magic == FPR_MAGIC, "Wrong FPR Magic: 0x%08x", HostState->Head.Magic);
-  memcpy(&HostState->FPRs[0], &Context->FPRs[0], 32 * sizeof(__uint128_t));
-  Context->FPCR = HostState->FPCR;
-  Context->FPSR = HostState->FPSR;
-
-  // Restore GPRs and other state
-  _mcontext->pstate = Context->PState;
-  _mcontext->pc = Context->PrevPC;
-  _mcontext->sp = Context->PrevSP;
-  memcpy(&_mcontext->regs[0], &Context->GPRs[0], 31 * sizeof(uint64_t));
-
-  // Restore the previous signal state
-  // This allows recursive signals to properly handle signal masking as we are walking back up the list of signals
-  CTX->SignalDelegation->SetCurrentSignal(Context->Signal);
-}
-
-bool DispatchGenerator::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  StoreThreadState(Signal, ucontext);
-
-  // Set the new PC
-  _mcontext->pc = AbsoluteLoopTopAddress;
-  // Set x28 (which is our state register) to point to our guest thread data
-  _mcontext->regs[28 /* STATE */] = reinterpret_cast<uint64_t>(State);
-
-  State->State.State.gregs[X86State::REG_RDI] = Signal;
-  uint64_t OldGuestSP = State->State.State.gregs[X86State::REG_RSP];
-  uint64_t NewGuestSP = OldGuestSP;
-
-  if (!(GuestStack->ss_flags & SS_DISABLE)) {
-    // If our guest is already inside of the alternative stack
-    // Then that means we are hitting recursive signals and we need to walk back the stack correctly
-    uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
-    uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
-    if (OldGuestSP >= AltStackBase &&
-        OldGuestSP <= AltStackEnd) {
-      // We are already in the alt stack, the rest of the code will handle adjusting this
-    }
-    else {
-      NewGuestSP = AltStackEnd;
-    }
-  }
-
-  // Back up past the redzone, which is 128bytes
-  // Don't need this offset if we aren't going to be putting siginfo in to it
-  NewGuestSP -= 128;
-
-  if (GuestAction->sa_flags & SA_SIGINFO) {
-    // XXX: siginfo_t(RSI), ucontext (RDX)
-    State->State.State.gregs[X86State::REG_RSI] = 0;
-    State->State.State.gregs[X86State::REG_RDX] = 0;
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
-  }
-  else {
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
-  }
-
-  // Set up the new SP for stack handling
-  NewGuestSP -= 8;
-  *(uint64_t*)NewGuestSP = CTX->X86CodeGen.SignalReturn;
-  State->State.State.gregs[X86State::REG_RSP] = NewGuestSP;
-
-  return true;
-}
-
-bool DispatchGenerator::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  FEXCore::Core::SignalEvent SignalReason = State->SignalReason.load();
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_PAUSE) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Store our thread state so we can come back to this
-    StoreThreadState(Signal, ucontext);
-
-    // Set the new PC
-    _mcontext->pc = ThreadPauseHandlerAddress;
-
-    // Set our state register to point to our guest thread data
-    _mcontext->regs[28 /* STATE */] = reinterpret_cast<uint64_t>(State);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_RETURN) {
-    RestoreThreadState(ucontext);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_STOP) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Our thread is stopping
-    // We don't care about anything at this point
-    // Set the stack to our starting location when we entered the JIT and get out safely
-    _mcontext->sp = State->State.ReturningStackLocation;
-
-    // Set the new PC
-    _mcontext->pc = ThreadStopHandlerAddress;
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  return false;
-}
-
-void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  Generator = new DispatchGenerator(ctx, Thread);
-  DispatchPtr = Generator->DispatchPtr;
-  CallbackPtr = Generator->CallbackPtr;
-
-  // TODO: Implement this. It is missing from the dispatcher
-  // TODO: It feels wrong to initialize this way
-  ctx->InterpreterCallbackReturn = nullptr;
-}
-
-bool InterpreterCore::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
-}
-
-bool InterpreterCore::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleSignalPause(Signal, info, ucontext);
-}
-
-void InterpreterCore::DeleteAsmDispatch() {
-  delete Generator;
-}
-
-}

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterClass.h

@@ -1,14 +1,15 @@
 #pragma once
 
-#include "Interface/Core/LookupCache.h"
 #include "Interface/Core/InternalThreadState.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
 
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 
 namespace FEXCore::CPU {
-class DispatchGenerator;
+class X86DispatchGenerator;
+class Arm64DispatchGenerator;
 
 #define DESTMAP_AS_MAP 0
 #if DESTMAP_AS_MAP
@@ -20,16 +21,14 @@ using DestMapType = std::vector<uint32_t>;
 class InterpreterCore final : public CPUBackend {
 public:
   explicit InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
-  ~InterpreterCore() override;
   std::string GetName() override { return "Interpreter"; }
-  void *CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
+  void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
 
   void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
 
   bool NeedsOpDispatch() override { return true; }
 
   void CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread);
-  void DeleteAsmDispatch();
 
   bool HandleSIGBUS(int Signal, void *info, void *ucontext);
 
@@ -38,8 +37,6 @@ private:
   FEXCore::Core::InternalThreadState *State;
 
   uint32_t AllocateTmpSpace(size_t Size);
-  bool HandleSignalPause(int Signal, void *info, void *ucontext);
-  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
 
   template<typename Res>
   Res GetDest(void* SSAData, IR::OrderedNodeWrapper Op);
@@ -47,7 +44,7 @@ private:
   template<typename Res>
   Res GetSrc(void* SSAData, IR::OrderedNodeWrapper Src);
 
-  DispatchGenerator *Generator{};
+  std::unique_ptr<Dispatcher> Dispatcher{};
 };
 
 }

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp

@@ -2,9 +2,8 @@
 #include "Common/SoftFloat.h"
 #include "Interface/Context/Context.h"
 
-#ifdef _M_ARM_64
 #include "Interface/Core/ArchHelpers/Arm64.h"
-#endif
+#include "Interface/Core/ArchHelpers/MContext.h"
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/DebugData.h"
 #include "Interface/Core/InternalThreadState.h"
@@ -22,62 +21,76 @@
 #include <cmath>
 #include <limits>
 #include <vector>
-#ifdef _M_X86_64
-#include <xmmintrin.h>
-#endif
 
 #include "InterpreterOps.h"
 
 namespace FEXCore::CPU {
 
-static void InterpreterExecution(FEXCore::Core::InternalThreadState *Thread) {
-  auto LocalEntry = Thread->LocalIRCache.find(Thread->State.State.rip);
-  
-  InterpreterOps::InterpretIR(Thread, LocalEntry->second.IR.get(), LocalEntry->second.DebugData.get());
-}
+static void InterpreterExecution(FEXCore::Core::CpuStateFrame *Frame) {
+  auto Thread = Frame->Thread;
 
+  auto LocalEntry = Thread->LocalIRCache.find(Thread->CurrentFrame->State.rip);
+
+  InterpreterOps::InterpretIR(Thread, Thread->CurrentFrame->State.rip, LocalEntry->second.IR.get(), LocalEntry->second.DebugData.get());
+}
 
 bool InterpreterCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
 #ifdef _M_ARM_64
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-  uint32_t *PC = (uint32_t*)_mcontext->pc;
-  uint32_t Instr = PC[0];
-  if ((Instr & FEXCore::ArchHelpers::Arm64::CASPAL_MASK) == FEXCore::ArchHelpers::Arm64::CASPAL_INST) { // CASPAL
-    if (FEXCore::ArchHelpers::Arm64::HandleCASPAL(_mcontext, info, Instr)) {
-      // Skip this instruction now
-      _mcontext->pc += 4;
-      return true;
-    }
-    else {
-      LogMan::Msg::E("Unhandled JIT SIGBUS CASPAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
-      return false;
-    }
-  }
-  else if ((Instr & FEXCore::ArchHelpers::Arm64::CASAL_MASK) == FEXCore::ArchHelpers::Arm64::CASAL_INST) { // CASAL
-    if (FEXCore::ArchHelpers::Arm64::HandleCASAL(_mcontext, info, Instr)) {
-      // Skip this instruction now
-      _mcontext->pc += 4;
-      return true;
-    }
-    else {
-      LogMan::Msg::E("Unhandled JIT SIGBUS CASAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
-      return false;
-    }
-  }
-  else if ((Instr & FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_MASK) == FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_INST) { // Atomic memory op
-    if (FEXCore::ArchHelpers::Arm64::HandleAtomicMemOp(_mcontext, info, Instr)) {
-      // Skip this instruction now
-      _mcontext->pc += 4;
-      return true;
-    }
-    else {
-      uint8_t Op = (PC[0] >> 12) & 0xF;
-      LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x: PC: %p Instruction: 0x%08x\n", Op, PC, PC[0]);
-      return false;
-    }
-  }
+  constexpr bool is_arm64 = true;
+#else
+  constexpr bool is_arm64 = false;
 #endif
+
+  if constexpr (is_arm64) {
+    uint32_t *PC = reinterpret_cast<uint32_t*>(ArchHelpers::Context::GetPc(ucontext));
+    uint32_t Instr = PC[0];
+    if ((Instr & FEXCore::ArchHelpers::Arm64::CASPAL_MASK) == FEXCore::ArchHelpers::Arm64::CASPAL_INST) { // CASPAL
+      if (FEXCore::ArchHelpers::Arm64::HandleCASPAL(ucontext, info, Instr)) {
+        // Skip this instruction now
+        ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + 4);
+        return true;
+      }
+      else {
+        LogMan::Msg::E("Unhandled JIT SIGBUS CASPAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
+        return false;
+      }
+    }
+    else if ((Instr & FEXCore::ArchHelpers::Arm64::CASAL_MASK) == FEXCore::ArchHelpers::Arm64::CASAL_INST) { // CASAL
+      if (FEXCore::ArchHelpers::Arm64::HandleCASAL(ucontext, info, Instr)) {
+        // Skip this instruction now
+        ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + 4);
+        return true;
+      }
+      else {
+        LogMan::Msg::E("Unhandled JIT SIGBUS CASAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
+        return false;
+      }
+    }
+    else if ((Instr & FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_MASK) == FEXCore::ArchHelpers::Arm64::ATOMIC_MEM_INST) { // Atomic memory op
+      if (FEXCore::ArchHelpers::Arm64::HandleAtomicMemOp(ucontext, info, Instr)) {
+        // Skip this instruction now
+        ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + 4);
+        return true;
+      }
+      else {
+        uint8_t Op = (PC[0] >> 12) & 0xF;
+        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x: PC: %p Instruction: 0x%08x\n", Op, PC, PC[0]);
+        return false;
+      }
+    }
+    else if ((Instr & FEXCore::ArchHelpers::Arm64::LDAXR_MASK) == FEXCore::ArchHelpers::Arm64::LDAXR_INST) { // LDAXR*
+      uint64_t BytesToSkip = FEXCore::ArchHelpers::Arm64::HandleAtomicLoadstoreExclusive(ucontext, info);
+      if (BytesToSkip) {
+        // Skip this instruction now
+        ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + BytesToSkip);
+        return true;
+      }
+      else {
+        LogMan::Msg::E("Unhandled JIT SIGBUS LDAXR: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
+        return false;
+      }
+    }
+  }
   return false;
 }
 
@@ -91,17 +104,17 @@ InterpreterCore::InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::
     CreateAsmDispatch(ctx, Thread);
     CTX->SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
       InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
-      return Core->HandleSignalPause(Signal, info, ucontext);
-    });
+      return Core->Dispatcher->HandleSignalPause(Signal, info, ucontext);
+    }, true);
 
     CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
       InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
       return Core->HandleSIGBUS(Signal, info, ucontext);
-    });
+    }, true);
 
     auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
       InterpreterCore *Core = reinterpret_cast<InterpreterCore*>(Thread->CPUBackend.get());
-      return Core->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
+      return Core->Dispatcher->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
     };
 
     for (uint32_t Signal = 0; Signal < SignalDelegator::MAX_SIGNALS; ++Signal) {
@@ -110,18 +123,12 @@ InterpreterCore::InterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::
   }
 }
 
-
-InterpreterCore::~InterpreterCore() {
-  DeleteAsmDispatch();
-}
-
-
-void *InterpreterCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
+void *InterpreterCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) {
   return reinterpret_cast<void*>(InterpreterExecution);
 }
 
-FEXCore::CPU::CPUBackend *CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread) {
-  return new InterpreterCore(ctx, Thread, CompileThread);
+std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread) {
+  return std::make_unique<InterpreterCore>(ctx, Thread, CompileThread);
 }
 
 }

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.h

@@ -1,5 +1,7 @@
 #pragma once
 
+#include <memory>
+
 namespace FEXCore::Context {
 struct Context;
 }
@@ -11,6 +13,6 @@ namespace FEXCore::Core {
 namespace FEXCore::CPU {
 class CPUBackend;
 
-FEXCore::CPU::CPUBackend *CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
+std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
 
 }

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h

@@ -36,7 +36,7 @@ namespace FEXCore::CPU {
   class InterpreterOps {
 
     public:
-      static void InterpretIR(FEXCore::Core::InternalThreadState *Thread, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData);
+      static void InterpretIR(FEXCore::Core::InternalThreadState *Thread, uint64_t Entry, FEXCore::IR::IRListView *CurrentIR, FEXCore::Core::DebugData *DebugData);
       static bool GetFallbackHandler(IR::IROp_Header *IROp, FallbackInfo *Info);
   };
 };

External/FEXCore/Source/Interface/Core/Interpreter/x86_64Dispatcher.cpp

@@ -1,470 +0,0 @@
-#include "Common/MathUtils.h"
-#include "Interface/Core/Interpreter/InterpreterClass.h"
-#include "Interface/Context/Context.h"
-#include <FEXCore/Core/X86Enums.h>
-
-#include <cmath>
-#include <xbyak/xbyak.h>
-
-namespace FEXCore::CPU {
-static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
-#define STATE r14
-
-class DispatchGenerator : public Xbyak::CodeGenerator {
-  public:
-    DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread);
-    bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
-    bool HandleSignalPause(int Signal, void *info, void *ucontext);
-
-  CPUBackend::AsmDispatch DispatchPtr;
-  CPUBackend::JITCallback CallbackPtr;
-  FEXCore::Context::Context::IntCallbackReturn ReturnPtr;
-
-  uint64_t ThreadStopHandlerAddress;
-  uint64_t AbsoluteLoopTopAddress;
-  uint64_t ThreadPauseHandlerAddress;
-  FEXCore::Context::Context *CTX;
-  FEXCore::Core::InternalThreadState *State;
-  private:
-    void StoreThreadState(int Signal, void *ucontext);
-    void RestoreThreadState(void *ucontext);
-    std::stack<uint64_t> SignalFrames;
-};
-
-static void SleepThread(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  --ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-
-  // Go to sleep
-  Thread->StartRunning.Wait();
-
-  Thread->State.RunningEvents.Running = true;
-  ++ctx->IdleWaitRefCount;
-  ctx->IdleWaitCV.notify_all();
-}
-
-DispatchGenerator::DispatchGenerator(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread)
-  : Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE)
-  , CTX {ctx}
-  , State {Thread} {
-  using namespace Xbyak;
-  using namespace Xbyak::util;
-  DispatchPtr = getCurr<CPUBackend::AsmDispatch>();
-
-  // while (!Thread->State.RunningEvents.ShouldStop.load()) {
-  //    Ptr = FindBlock(RIP)
-  //    if (!Ptr)
-  //      Ptr = CTX->CompileBlock(RIP);
-  //
-  //    if (Ptr)
-  //      Ptr();
-  //    else
-  //    {
-  //      Ptr = FallbackCore->CompileBlock()
-  //      if (Ptr)
-  //        Ptr()
-  //      else {
-  //        ShouldStop = true;
-  //      }
-  //    }
-  // }
-  // Bunch of exit state stuff
-
-  // x86-64 ABI has the stack aligned when /call/ happens
-  // Which means the destination has a misaligned stack at that point
-  push(rbx);
-  push(rbp);
-  push(r12);
-  push(r13);
-  push(r14);
-  push(r15);
-  sub(rsp, 8);
-
-  mov(STATE, rdi);
-
-  // Save this stack pointer so we can cleanly shutdown the emulation with a long jump
-  // regardless of where we were in the stack
-  mov(qword [rdi + offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)], rsp);
-
-  Label LoopTop;
-  Label NoBlock;
-  Label ExitBlock;
-  Label ThreadPauseHandler;
-
-  L(LoopTop);
-  AbsoluteLoopTopAddress = getCurr<uint64_t>();
-
-  {
-    mov(r13, Thread->LookupCache->GetPagePointer());
-
-    // Load our RIP
-    mov(rdx, qword [STATE + offsetof(FEXCore::Core::CPUState, rip)]);
-
-    mov(rax, rdx);
-    mov(rbx, Thread->LookupCache->GetVirtualMemorySize() - 1);
-    and_(rax, rbx);
-    shr(rax, 12);
-
-    // Load page pointer
-    mov(rdi, qword [r13 + rax * 8]);
-
-    cmp(rdi, 0);
-    je(NoBlock);
-
-    mov (rax, rdx);
-    and_(rax, 0x0FFF);
-
-    shl(rax, (int)log2(sizeof(FEXCore::LookupCache::LookupCacheEntry)));
-
-    // check for aliasing
-    mov(rcx, qword [rdi + rax + 8]);
-    cmp(rcx, rdx);
-    jne(NoBlock);
-    
-    // Load the block pointer
-    mov(rax, qword [rdi + rax]);
-
-    cmp(rax, 0);
-    je(NoBlock);
-
-    // Real block if we made it here
-    mov(rdi, STATE);
-    call(rax);
-
-    if (CTX->GetGdbServerStatus()) {
-      // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
-      // This happens when single stepping
-      static_assert(sizeof(CTX->Config.RunningMode) == 4, "This is expected to be size of 4");
-      mov(rax, qword [STATE + (offsetof(FEXCore::Core::InternalThreadState, CTX))]);
-
-      // If the value == 0 then branch to the top
-      cmp(dword [rax + (offsetof(FEXCore::Context::Context, Config.RunningMode))], 0);
-      je(LoopTop);
-      // Else we need to pause now
-      jmp(ThreadPauseHandler);
-      ud2();
-    }
-    else {
-      jmp(LoopTop);
-    }
-  }
-
-  {
-    L(ExitBlock);
-    ThreadStopHandlerAddress = getCurr<uint64_t>();
-
-    add(rsp, 8);
-
-    pop(r15);
-    pop(r14);
-    pop(r13);
-    pop(r12);
-    pop(rbp);
-    pop(rbx);
-
-    ret();
-  }
-
-  // Block creation
-  {
-    L(NoBlock);
-
-    using ClassPtrType = uintptr_t (FEXCore::Context::Context::*)(FEXCore::Core::InternalThreadState *, uint64_t);
-    union PtrCast {
-      ClassPtrType ClassPtr;
-      uintptr_t Data;
-    };
-
-    PtrCast Ptr;
-    Ptr.ClassPtr = &FEXCore::Context::Context::CompileBlock;
-
-    // {rdi, rsi, rdx}
-    mov(rdi, reinterpret_cast<uint64_t>(CTX));
-    mov(rsi, STATE);
-    mov(rax, Ptr.Data);
-
-    call(rax);
-
-    // rdx already contains RIP here
-    jmp(LoopTop);
-  }
-
-  {
-    // Pause handler
-    ThreadPauseHandlerAddress = getCurr<uint64_t>();
-    L(ThreadPauseHandler);
-
-    mov(rdi, reinterpret_cast<uintptr_t>(CTX));
-    mov(rsi, STATE);
-    mov(rax, reinterpret_cast<uint64_t>(SleepThread));
-
-    call(rax);
-
-    // XXX: Unsupported atm
-    // uint64_t PauseReturnInstruction = getCurr<uint64_t>();
-    // ud2();
-  }
-
-  {
-    CallbackPtr = getCurr<CPUBackend::JITCallback>();
-
-    push(rbx);
-    push(rbp);
-    push(r12);
-    push(r13);
-    push(r14);
-    push(r15);
-    sub(rsp, 8);
-
-    // First thing we need to move the thread state pointer back in to our register
-    mov(STATE, rdi);
-    // XXX: XMM?
-
-    // Now push the callback return trampoline to the guest stack
-    // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
-    mov(rax, CTX->X86CodeGen.CallbackReturn);
-
-    // Store the trampoline to the guest stack
-    // Guest stack is now correctly misaligned after a regular call instruction
-    sub(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])], 16);
-    mov(rbx, qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])]);
-    mov(qword [rbx], rax);
-
-    // Store RIP to the context state
-    mov(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.rip)], rsi);
-
-    // Back to the loop top now
-    jmp(LoopTop);
-  }
-
-
-  {
-    ReturnPtr = getCurr<FEXCore::Context::Context::IntCallbackReturn>();
-//  using CallbackReturn =  __attribute__((naked)) void(*)(FEXCore::Core::InternalThreadState *Thread, volatile void *Host_RSP);
-
-    // rdi = thread
-    // rsi = rsp
-
-    mov(rsp, rsi);
-
-    // Now jump back to the thunk
-    // XXX: XMM?
-    add(rsp, 8);
-
-    pop(r15);
-    pop(r14);
-    pop(r13);
-    pop(r12);
-    pop(rbp);
-    pop(rbx);
-
-    ret();
-  }
-  ready();
-}
-
-struct ContextBackup {
-  uint64_t StoredCookie;
-  // Host State
-  // RIP and RSP is stored in GPRs here
-  uint64_t GPRs[NGREG];
-  _libc_fpstate FPRState;
-
-  // Guest state
-  int Signal;
-  FEXCore::Core::CPUState GuestState;
-};
-
-void DispatchGenerator::StoreThreadState(int Signal, void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  // We can end up getting a signal at any point in our host state
-  // Jump to a handler that saves all state so we can safely return
-  uint64_t OldSP = _mcontext->gregs[REG_RSP];
-  uintptr_t NewSP = OldSP;
-
-  size_t StackOffset = sizeof(ContextBackup);
-
-  // We need to back up behind the host's red zone
-  // We do this on the guest side as well
-  NewSP -= 128;
-  NewSP -= StackOffset;
-  NewSP = AlignDown(NewSP, 16);
-
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-
-  Context->StoredCookie = 0x4142434445464748ULL;
-
-  // Copy the GPRs
-  memcpy(&Context->GPRs[0], &_mcontext->gregs[0], NGREG * sizeof(_mcontext->gregs[0]));
-  // Copy the FPRState
-  memcpy(&Context->FPRState, _mcontext->fpregs, sizeof(_libc_fpstate));
-
-  // XXX: Save 256bit and 512bit AVX register state
-
-  // Retain the action pointer so we can see it when we return
-  Context->Signal = Signal;
-
-  // Save guest state
-  // We can't guarantee if registers are in context or host GPRs
-  // So we need to save everything
-  memcpy(&Context->GuestState, &State->State, sizeof(FEXCore::Core::CPUState));
-
-  // Set the new SP
-  _mcontext->gregs[REG_RSP] = NewSP;
-
-  SignalFrames.push(NewSP);
-}
-
-void DispatchGenerator::RestoreThreadState(void *ucontext) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  uint64_t OldSP = SignalFrames.top();
-  SignalFrames.pop();
-  uintptr_t NewSP = OldSP;
-  ContextBackup *Context = reinterpret_cast<ContextBackup*>(NewSP);
-
-  if (Context->StoredCookie != 0x4142434445464748ULL) {
-    LogMan::Msg::D("COOKIE WAS NOT CORRECT!\n");
-    exit(-1);
-  }
-
-  // First thing, reset the guest state
-  memcpy(&State->State, &Context->GuestState, sizeof(FEXCore::Core::CPUState));
-
-  // Now restore host state
-
-  // Copy the GPRs
-  memcpy(&_mcontext->gregs[0], &Context->GPRs[0], NGREG * sizeof(_mcontext->gregs[0]));
-  // Copy the FPRState
-  memcpy(_mcontext->fpregs, &Context->FPRState, sizeof(_libc_fpstate));
-
-  // Restore the previous signal state
-  // This allows recursive signals to properly handle signal masking as we are walking back up the list of signals
-  CTX->SignalDelegation->SetCurrentSignal(Context->Signal);
-}
-
-bool DispatchGenerator::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  ucontext_t* _context = (ucontext_t*)ucontext;
-  mcontext_t* _mcontext = &_context->uc_mcontext;
-
-  StoreThreadState(Signal, ucontext);
-
-  // Set the new PC
-  _mcontext->gregs[REG_RIP] = AbsoluteLoopTopAddress;
-  // Set our state register to point to our guest thread data
-  _mcontext->gregs[REG_R14] = reinterpret_cast<uint64_t>(State);
-
-  uint64_t OldGuestSP = State->State.State.gregs[X86State::REG_RSP];
-  uint64_t NewGuestSP = OldGuestSP;
-
-  if (!(GuestStack->ss_flags & SS_DISABLE)) {
-    // If our guest is already inside of the alternative stack
-    // Then that means we are hitting recursive signals and we need to walk back the stack correctly
-    uint64_t AltStackBase = reinterpret_cast<uint64_t>(GuestStack->ss_sp);
-    uint64_t AltStackEnd = AltStackBase + GuestStack->ss_size;
-    if (OldGuestSP >= AltStackBase &&
-        OldGuestSP <= AltStackEnd) {
-      // We are already in the alt stack, the rest of the code will handle adjusting this
-    }
-    else {
-      NewGuestSP = AltStackEnd;
-    }
-  }
-
-  // Back up past the redzone, which is 128bytes
-  // Don't need this offset if we aren't going to be putting siginfo in to it
-  NewGuestSP -= 128;
-
-  State->State.State.gregs[X86State::REG_RDI] = Signal;
-
-  if (GuestAction->sa_flags & SA_SIGINFO) {
-    // XXX: siginfo_t(RSI), ucontext (RDX)
-    State->State.State.gregs[X86State::REG_RSI] = 0;
-    State->State.State.gregs[X86State::REG_RDX] = 0;
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
-  }
-  else {
-    State->State.State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
-  }
-
-  // Set up the new SP for stack handling
-  NewGuestSP -= 8;
-  *(uint64_t*)NewGuestSP = CTX->X86CodeGen.SignalReturn;
-  State->State.State.gregs[X86State::REG_RSP] = NewGuestSP;
-
-  return true;
-}
-
-bool DispatchGenerator::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  FEXCore::Core::SignalEvent SignalReason = State->SignalReason.load();
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_PAUSE) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Store our thread state so we can come back to this
-    StoreThreadState(Signal, ucontext);
-
-    // Set the new PC
-    _mcontext->gregs[REG_RIP] = ThreadPauseHandlerAddress;
-
-    // Set our state register to point to our guest thread data
-    _mcontext->gregs[REG_R14] = reinterpret_cast<uint64_t>(State);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_STOP) {
-    ucontext_t* _context = (ucontext_t*)ucontext;
-    mcontext_t* _mcontext = &_context->uc_mcontext;
-
-    // Our thread is stopping
-    // We don't care about anything at this point
-    // Set the stack to our starting location when we entered the core and get out safely
-    _mcontext->gregs[REG_RSP] = State->State.ReturningStackLocation;
-
-    // Set the new PC
-    _mcontext->gregs[REG_RIP] = ThreadStopHandlerAddress;
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  if (SignalReason == FEXCore::Core::SignalEvent::SIGNALEVENT_RETURN) {
-    RestoreThreadState(ucontext);
-
-    State->SignalReason.store(FEXCore::Core::SIGNALEVENT_NONE);
-    return true;
-  }
-
-  return false;
-}
-
-void InterpreterCore::CreateAsmDispatch(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  Generator = new DispatchGenerator(ctx, Thread);
-  DispatchPtr = Generator->DispatchPtr;
-  CallbackPtr = Generator->CallbackPtr;
-
-  // TODO: It feels wrong to initialize this way
-  ctx->InterpreterCallbackReturn = Generator->ReturnPtr;
-}
-
-bool InterpreterCore::HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleGuestSignal(Signal, info, ucontext, GuestAction, GuestStack);
-}
-
-bool InterpreterCore::HandleSignalPause(int Signal, void *info, void *ucontext) {
-  DispatchGenerator *Gen = Generator;
-  return Gen->HandleSignalPause(Signal, info, ucontext);
-}
-
-void InterpreterCore::DeleteAsmDispatch() {
-  delete Generator;
-}
-
-}

External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp

@@ -1,3 +1,8 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
 
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
@@ -29,7 +34,7 @@ static int64_t LREM(int64_t SrcHigh, int64_t SrcLow, int64_t Divisor) {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(TruncElementPair) {
   auto Op = IROp->C<IR::IROp_TruncElementPair>();
 
@@ -41,7 +46,7 @@ DEF_OP(TruncElementPair) {
       mov(Dst.second, Src.second);
       break;
     }
-    default: LogMan::Msg::A("Unhandled Truncation size: %d", Op->Size); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", Op->Size); break;
   }
 }
 
@@ -54,7 +59,7 @@ DEF_OP(Constant) {
 DEF_OP(EntrypointOffset) {
   auto Op = IROp->C<IR::IROp_EntrypointOffset>();
 
-  auto Constant = IR->GetHeader()->Entry + Op->Offset;
+  auto Constant = Entry + Op->Offset;
   auto Dst = GetReg<RA_64>(Node);
   LoadConstant(Dst, Constant);
 }
@@ -90,7 +95,7 @@ DEF_OP(Add) {
       case 8:
         add(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), Const);
         break;
-      default: LogMan::Msg::A("Unsupported Add size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Add size: {}", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -100,7 +105,7 @@ DEF_OP(Add) {
       case 8:
         add(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
         break;
-      default: LogMan::Msg::A("Unsupported Add size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Add size: {}", OpSize);
     }
   }
 }
@@ -116,7 +121,7 @@ DEF_OP(Sub) {
       case 8:
         sub(GRS(Node), GRS(Op->Header.Args[0].ID()), Const);
         break;
-      default: LogMan::Msg::A("Unsupported Sub size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Sub size: {}", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -126,7 +131,7 @@ DEF_OP(Sub) {
       case 8:
         sub(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
         break;
-      default: LogMan::Msg::A("Unsupported Sub size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Sub size: {}", OpSize);
     }
   }
 
@@ -142,7 +147,7 @@ DEF_OP(Neg) {
     case 8:
       neg(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unsupported Not size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported Neg size: {}", OpSize);
   }
 }
 
@@ -154,12 +159,11 @@ DEF_OP(Mul) {
   switch (OpSize) {
     case 4:
       mul(Dst.W(), GetReg<RA_32>(Op->Header.Args[0].ID()), GetReg<RA_32>(Op->Header.Args[1].ID()));
-      sxtw(Dst, Dst);
     break;
     case 8:
       mul(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Mul size: %d", OpSize);
   }
 }
 
@@ -175,7 +179,7 @@ DEF_OP(UMul) {
     case 8:
       mul(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown UMul size: {}", OpSize);
   }
 }
 
@@ -212,7 +216,7 @@ DEF_OP(Div) {
       sdiv(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
     }
-    default: LogMan::Msg::A("Unknown DIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown DIV Size: {}", Size); break;
   }
 }
 
@@ -239,7 +243,7 @@ DEF_OP(UDiv) {
       udiv(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
       break;
     }
-    default: LogMan::Msg::A("Unknown UDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown UDIV Size: {}", Size); break;
   }
 }
 
@@ -286,7 +290,7 @@ DEF_OP(Rem) {
       msub(GetReg<RA_64>(Node), TMP1, Divisor, Dividend);
     break;
     }
-    default: LogMan::Msg::A("Unknown REM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown REM Size: {}", OpSize); break;
   }
 }
 
@@ -328,7 +332,7 @@ DEF_OP(URem) {
       msub(GetReg<RA_64>(Node), TMP1, Divisor, Dividend);
     break;
     }
-    default: LogMan::Msg::A("Unknown UREM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown UREM Size: {}", OpSize); break;
   }
 }
 
@@ -340,12 +344,12 @@ DEF_OP(MulH) {
       sxtw(TMP1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       sxtw(TMP2, GetReg<RA_64>(Op->Header.Args[1].ID()));
       mul(TMP1, TMP1, TMP2);
-      sbfx(GetReg<RA_64>(Node), TMP1, 32, 32);
+      ubfx(GetReg<RA_64>(Node), TMP1, 32, 32);
     break;
     case 8:
       smulh(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Sext size: {}", OpSize);
   }
 }
 
@@ -362,7 +366,7 @@ DEF_OP(UMulH) {
     case 8:
       umulh(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Sext size: {}", OpSize);
   }
 }
 
@@ -398,7 +402,6 @@ DEF_OP(Xor) {
 
 DEF_OP(Lshl) {
   auto Op = IROp->C<IR::IROp_Lshl>();
-  uint8_t OpSize = IROp->Size;
   uint64_t Const;
   if (IsInlineConstant(Op->Header.Args[1], &Const)) {
     lsl(GRS(Node), GRS(Op->Header.Args[0].ID()), (unsigned int)Const);
@@ -409,7 +412,6 @@ DEF_OP(Lshl) {
 
 DEF_OP(Lshr) {
   auto Op = IROp->C<IR::IROp_Lshr>();
-  uint8_t OpSize = IROp->Size;
   uint64_t Const;
   if (IsInlineConstant(Op->Header.Args[1], &Const)) {
     lsr(GRS(Node), GRS(Op->Header.Args[0].ID()), (unsigned int)Const);
@@ -460,7 +462,7 @@ DEF_OP(Ror) {
       break;
       }
 
-      default: LogMan::Msg::A("Unhandled ROR size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unhandled ROR size: {}", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -473,7 +475,7 @@ DEF_OP(Ror) {
       break;
       }
 
-      default: LogMan::Msg::A("Unhandled ROR size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unhandled ROR size: {}", OpSize);
     }
   }
 }
@@ -492,7 +494,7 @@ DEF_OP(Extr) {
     break;
     }
 
-    default: LogMan::Msg::A("Unhandled EXTR size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unhandled EXTR size: {}", OpSize);
   }
 }
 
@@ -524,14 +526,10 @@ DEF_OP(LDiv) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LDIV);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LDIV));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
 
       // Result is now in x0
       // Fix the stack and any values that were stepped on
@@ -541,7 +539,7 @@ DEF_OP(LDiv) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LDIV Size: {}", Size); break;
   }
 }
 
@@ -571,14 +569,10 @@ DEF_OP(LUDiv) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LUDIV);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LUDIV));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
 
       // Result is now in x0
       // Fix the stack and any values that were stepped on
@@ -588,7 +582,7 @@ DEF_OP(LUDiv) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LUDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUDIV Size: {}", Size); break;
   }
 }
 
@@ -628,14 +622,10 @@ DEF_OP(LRem) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LREM);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LREM));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
 
       // Result is now in x0
       // Fix the stack and any values that were stepped on
@@ -645,7 +635,7 @@ DEF_OP(LRem) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LREM Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LREM Size: {}", Size); break;
   }
 }
 
@@ -682,14 +672,11 @@ DEF_OP(LURem) {
       mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
       mov(x2, GetReg<RA_64>(Op->Header.Args[2].ID()));
 
-#if _M_X86_64
-      CallRuntime(LUREM);
-#else
       LoadConstant(x3, reinterpret_cast<uint64_t>(LUREM));
       SpillStaticRegs();
       blr(x3);
       FillStaticRegs();
-#endif
+
       // Fix the stack and any values that were stepped on
       PopDynamicRegsAndLR();
 
@@ -698,7 +685,7 @@ DEF_OP(LURem) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LogMan::Msg::A("Unknown LUREM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUREM Size: {}", OpSize); break;
   }
 }
 
@@ -712,7 +699,7 @@ DEF_OP(Not) {
     case 8:
       mvn(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unsupported Not size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported Not size: {}", OpSize);
   }
 }
 
@@ -743,7 +730,7 @@ DEF_OP(Popcount) {
       // fmov has zero extended, unused bytes are zero
       addv(VTMP1.B(), VTMP1.V8B());
       break;
-    default: LogMan::Msg::A("Unsupported Popcount size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported Popcount size: {}", OpSize);
   }
 
   auto Dst = GetReg<RA_32>(Node);
@@ -792,7 +779,7 @@ DEF_OP(FindMSB) {
       clz(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()));
       sub(Dst, TMP1, Dst);
       break;
-    default: LogMan::Msg::A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown FindMSB size: {}", OpSize); break;
   }
 }
 
@@ -813,7 +800,7 @@ DEF_OP(FindTrailingZeros) {
       rbit(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       clz(GetReg<RA_64>(Node), GetReg<RA_64>(Node));
       break;
-    default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown FindTrailingZeros size: {}", OpSize); break;
   }
 }
 
@@ -832,7 +819,7 @@ DEF_OP(CountLeadingZeroes) {
     case 8:
       clz(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown CountLeadingZeroes size: {}", OpSize); break;
   }
 }
 
@@ -850,7 +837,7 @@ DEF_OP(Rev) {
     case 8:
       rev(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown REV size: {}", OpSize); break;
   }
 }
 
@@ -872,15 +859,14 @@ DEF_OP(Bfi) {
       bfi(TMP1, GetReg<RA_64>(Op->Header.Args[1].ID()), Op->lsb, Op->Width);
       mov(GetReg<RA_64>(Node), TMP1);
       break;
-    default: LogMan::Msg::A("Unknown BFI size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown BFI size: {}", OpSize); break;
   }
 }
 
 DEF_OP(Bfe) {
   auto Op = IROp->C<IR::IROp_Bfe>();
-  uint8_t OpSize = IROp->Size;
-  LogMan::Throw::A(OpSize <= 8, "OpSize is too large for BFE: %d", OpSize);
-  LogMan::Throw::A(Op->Width != 0, "Invalid BFE width of 0");
+  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
+  LOGMAN_THROW_A_FMT(Op->Width != 0, "Invalid BFE width of 0");
 
   auto Dst = GetReg<RA_64>(Node);
   ubfx(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), Op->lsb, Op->Width);
@@ -894,7 +880,7 @@ DEF_OP(Sbfe) {
   if (OpSize == 8) {
     sbfx(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), Op->lsb, Op->Width);
   } else {
-    LogMan::Msg::D("Unimplemented Sbfe size");
+    LogMan::Msg::DFmt("Unimplemented Sbfe size");
   }
 }
 
@@ -920,12 +906,12 @@ Condition MapSelectCC(IR::CondClassType Cond) {
   case FEXCore::IR::COND_FGT: return Condition::hi;
   case FEXCore::IR::COND_FU:  return Condition::vs;
   case FEXCore::IR::COND_FNU: return Condition::vc;
-  case FEXCore::IR::COND_VS:;
-  case FEXCore::IR::COND_VC:;
+  case FEXCore::IR::COND_VS:
+  case FEXCore::IR::COND_VC:
   case FEXCore::IR::COND_MI:
   case FEXCore::IR::COND_PL:
   default:
-  LogMan::Msg::A("Unsupported compare type");
+  LOGMAN_MSG_A_FMT("Unsupported compare type");
   return Condition::nv;
   }
 }
@@ -943,9 +929,9 @@ DEF_OP(Select) {
   } else if (IsFPR(Op->Cmp1.ID())) {
     fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
   } else {
-    LogMan::Msg::A("Select: Expected GPR or FPR");
+    LOGMAN_MSG_A_FMT("Select: Expected GPR or FPR");
   }
-  
+
   auto cc = MapSelectCC(Op->Cond);
 
   uint64_t const_true, const_false;
@@ -954,7 +940,7 @@ DEF_OP(Select) {
 
   if (is_const_true || is_const_false) {
     if (is_const_false != true || is_const_true != true || const_true != 1 || const_false != 0) {
-      LogMan::Msg::A("Select: Unsupported compare inline parameters");
+      LOGMAN_MSG_A_FMT("Select: Unsupported compare inline parameters");
     }
     cset(GRS(Node), cc);
   } else {
@@ -978,38 +964,53 @@ DEF_OP(VExtractToGPR) {
     case 8:
       umov(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->Idx);
     break;
-    default:  LogMan::Msg::A("Unhandled ExtractElementSize: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled ExtractElementSize: {}", OpSize);
   }
 }
 
-DEF_OP(Float_ToGPR_ZU) {
-  LogMan::Msg::D("Unimplemented");
-}
-
 DEF_OP(Float_ToGPR_ZS) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_ZS>();
-  if (Op->Header.ElementSize == 8) {
-    fcvtzs(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).D());
+  aarch64::Register Dst{};
+  aarch64::VRegister Src{};
+  if (Op->SrcElementSize == 8) {
+    Src = GetSrc(Op->Header.Args[0].ID()).D();
   }
   else {
-    fcvtzs(GetReg<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()).S());
+    Src = GetSrc(Op->Header.Args[0].ID()).S();
   }
-}
 
-DEF_OP(Float_ToGPR_U) {
-  LogMan::Msg::D("Unimplemented");
+  if (IROp->Size == 8) {
+    Dst = GetReg<RA_64>(Node);
+  }
+  else {
+    Dst = GetReg<RA_32>(Node);
+  }
+
+  fcvtzs(Dst, Src);
 }
 
 DEF_OP(Float_ToGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_S>();
-  if (Op->Header.ElementSize == 8) {
+
+  aarch64::Register Dst{};
+  aarch64::VRegister Src{};
+  if (Op->SrcElementSize == 8) {
     frinti(VTMP1.D(), GetSrc(Op->Header.Args[0].ID()).D());
-    fcvtzs(GetReg<RA_64>(Node), VTMP1.D());
+    Src = VTMP1.D();
   }
   else {
     frinti(VTMP1.S(), GetSrc(Op->Header.Args[0].ID()).S());
-    fcvtzs(GetReg<RA_32>(Node), VTMP1.S());
+    Src = VTMP1.S();
   }
+
+  if (IROp->Size == 8) {
+    Dst = GetReg<RA_64>(Node);
+  }
+  else {
+    Dst = GetReg<RA_32>(Node);
+  }
+
+  fcvtzs(Dst, Src);
 }
 
 DEF_OP(FCmp) {
@@ -1022,11 +1023,11 @@ DEF_OP(FCmp) {
     fcmp(GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
   }
   auto Dst = GetReg<RA_64>(Node);
-  
+
   bool set = false;
 
   if (Op->Flags & (1 << IR::FCMP_FLAG_EQ)) {
-    LogMan::Throw::A(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
+    LOGMAN_THROW_A_FMT(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
     // EQ or unordered
     cset(Dst, Condition::eq); // Z = 1
     csinc(Dst, Dst, xzr, Condition::vc); // IF !V ? Z : 1
@@ -1057,8 +1058,8 @@ DEF_OP(FCmp) {
 
 #undef DEF_OP
 
-void JITCore::RegisterALUHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterALUHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(TRUNCELEMENTPAIR,  TruncElementPair);
   REGISTER_OP(CONSTANT,          Constant);
   REGISTER_OP(ENTRYPOINTOFFSET,  EntrypointOffset);
@@ -1100,9 +1101,7 @@ void JITCore::RegisterALUHandlers() {
   REGISTER_OP(SBFE,              Sbfe);
   REGISTER_OP(SELECT,            Select);
   REGISTER_OP(VEXTRACTTOGPR,     VExtractToGPR);
-  REGISTER_OP(FLOAT_TOGPR_ZU,    Float_ToGPR_ZU);
   REGISTER_OP(FLOAT_TOGPR_ZS,    Float_ToGPR_ZS);
-  REGISTER_OP(FLOAT_TOGPR_U,     Float_ToGPR_U);
   REGISTER_OP(FLOAT_TOGPR_S,     Float_ToGPR_S);
   REGISTER_OP(FCMP,              FCmp);
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp

@@ -1,9 +1,15 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(CASPair) {
   auto Op = IROp->C<IR::IROp_CASPair>();
   uint8_t OpSize = IROp->Size;
@@ -28,7 +34,7 @@ DEF_OP(CASPair) {
       mov(Dst.first, TMP3);
       mov(Dst.second, TMP4);
       break;
-    default: LogMan::Msg::A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
     }
   }
   else {
@@ -38,11 +44,15 @@ DEF_OP(CASPair) {
         aarch64::Label LoopNotExpected;
         aarch64::Label LoopExpected;
         bind(&LoopTop);
+        nop();
         ldaxp(TMP2.W(), TMP3.W(), MemOperand(MemSrc));
+        nop();
         cmp(TMP2.W(), Expected.first.W());
         ccmp(TMP3.W(), Expected.second.W(), NoFlag, Condition::eq);
         b(&LoopNotExpected, Condition::ne);
+        nop();
         stlxp(TMP2.W(), Desired.first.W(), Desired.second.W(), MemOperand(MemSrc));
+        nop();
         cbnz(TMP2.W(), &LoopTop);
         mov(Dst.first.W(), Expected.first.W());
         mov(Dst.second.W(), Expected.second.W());
@@ -63,11 +73,15 @@ DEF_OP(CASPair) {
         aarch64::Label LoopNotExpected;
         aarch64::Label LoopExpected;
         bind(&LoopTop);
+        nop();
         ldaxp(TMP2.X(), TMP3.X(), MemOperand(MemSrc));
+        nop();
         cmp(TMP2.X(), Expected.first.X());
         ccmp(TMP3.X(), Expected.second.X(), NoFlag, Condition::eq);
         b(&LoopNotExpected, Condition::ne);
+        nop();
         stlxp(TMP2.X(), Desired.first.X(), Desired.second.X(), MemOperand(MemSrc));
+        nop();
         cbnz(TMP2.X(), &LoopTop);
         mov(Dst.first.X(), Expected.first.X());
         mov(Dst.second.X(), Expected.second.X());
@@ -83,7 +97,7 @@ DEF_OP(CASPair) {
         bind(&LoopExpected);
         break;
       }
-      default: LogMan::Msg::A("Unsupported: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
     }
   }
 }
@@ -109,7 +123,7 @@ DEF_OP(CAS) {
     case 2: casalh(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
     case 4: casal(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
     case 8: casal(TMP2.X(), Desired.X(), MemOperand(MemSrc)); break;
-    default: LogMan::Msg::A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
     }
     mov(GetReg<RA_64>(Node), TMP2);
   }
@@ -200,7 +214,7 @@ DEF_OP(CAS) {
 
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", OpSize);
     }
   }
 }
@@ -216,7 +230,7 @@ DEF_OP(AtomicAdd) {
     case 2: staddlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: staddl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: staddl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -258,7 +272,7 @@ DEF_OP(AtomicAdd) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -275,7 +289,7 @@ DEF_OP(AtomicSub) {
     case 2: staddlh(TMP2.W(), MemOperand(MemSrc)); break;
     case 4: staddl(TMP2.W(), MemOperand(MemSrc)); break;
     case 8: staddl(TMP2.X(), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -317,7 +331,7 @@ DEF_OP(AtomicSub) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -334,7 +348,7 @@ DEF_OP(AtomicAnd) {
     case 2: stclrlh(TMP2.W(), MemOperand(MemSrc)); break;
     case 4: stclrl(TMP2.W(), MemOperand(MemSrc)); break;
     case 8: stclrl(TMP2.X(), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -376,7 +390,7 @@ DEF_OP(AtomicAnd) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -392,7 +406,7 @@ DEF_OP(AtomicOr) {
     case 2: stsetlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: stsetl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: stsetl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -434,7 +448,7 @@ DEF_OP(AtomicOr) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -450,7 +464,7 @@ DEF_OP(AtomicXor) {
     case 2: steorlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: steorl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: steorl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -492,7 +506,7 @@ DEF_OP(AtomicXor) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -509,36 +523,35 @@ DEF_OP(AtomicSwap) {
     case 2: swplh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: swpl(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: swpl(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
     // TMP2-TMP3
-    mov(TMP3, GetReg<RA_64>(Op->Header.Args[1].ID()));
     switch (Op->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+        stlxrb(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4.W(), &LoopTop);
-        uxtb(GetReg<RA_64>(Node), TMP2.W());
+        uxtb(GetReg<RA_32>(Node), TMP2.W());
         break;
       }
       case 2: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+        stlxrh(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4.W(), &LoopTop);
-        uxtw(GetReg<RA_64>(Node), TMP2.W());
+        uxtw(GetReg<RA_32>(Node), TMP2.W());
         break;
       }
       case 4: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxr(TMP2.W(), MemOperand(MemSrc));
-        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+        stlxr(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4.W(), &LoopTop);
         mov(GetReg<RA_32>(Node), TMP2.W());
         break;
@@ -547,12 +560,12 @@ DEF_OP(AtomicSwap) {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxr(TMP2, MemOperand(MemSrc));
-        stlxr(TMP4, TMP3.X(), MemOperand(MemSrc));
+        stlxr(TMP4, GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4, &LoopTop);
         mov(GetReg<RA_64>(Node), TMP2.X());
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -567,7 +580,7 @@ DEF_OP(AtomicFetchAdd) {
     case 2: ldaddalh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldaddal(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldaddal(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -613,7 +626,7 @@ DEF_OP(AtomicFetchAdd) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -629,7 +642,7 @@ DEF_OP(AtomicFetchSub) {
     case 2: ldaddalh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldaddal(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldaddal(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -675,7 +688,7 @@ DEF_OP(AtomicFetchSub) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -691,7 +704,7 @@ DEF_OP(AtomicFetchAnd) {
     case 2: ldclralh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldclral(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldclral(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -737,7 +750,7 @@ DEF_OP(AtomicFetchAnd) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -752,7 +765,7 @@ DEF_OP(AtomicFetchOr) {
     case 2: ldsetalh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldsetal(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldsetal(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -798,7 +811,7 @@ DEF_OP(AtomicFetchOr) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -813,7 +826,7 @@ DEF_OP(AtomicFetchXor) {
     case 2: ldeoralh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldeoral(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldeoral(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -859,14 +872,64 @@ DEF_OP(AtomicFetchXor) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
 
+DEF_OP(AtomicFetchNeg) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
+  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+
+  // TMP2-TMP3
+  switch (Op->Size) {
+    case 1: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxrb(TMP2.W(), MemOperand(MemSrc));
+      neg(TMP3.W(), TMP2.W());
+      stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+      cbnz(TMP4.W(), &LoopTop);
+      mov(GetReg<RA_32>(Node), TMP2.W());
+      break;
+    }
+    case 2: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxrh(TMP2.W(), MemOperand(MemSrc));
+      neg(TMP3.W(), TMP2.W());
+      stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+      cbnz(TMP4.W(), &LoopTop);
+      mov(GetReg<RA_32>(Node), TMP2.W());
+      break;
+    }
+    case 4: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxr(TMP2.W(), MemOperand(MemSrc));
+      neg(TMP3.W(), TMP2.W());
+      stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+      cbnz(TMP4.W(), &LoopTop);
+      mov(GetReg<RA_32>(Node), TMP2.W());
+      break;
+    }
+    case 8: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxr(TMP2, MemOperand(MemSrc));
+      neg(TMP3, TMP2);
+      stlxr(TMP4, TMP3, MemOperand(MemSrc));
+      cbnz(TMP4, &LoopTop);
+      mov(GetReg<RA_64>(Node), TMP2);
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
+  }
+}
+
 #undef DEF_OP
-void JITCore::RegisterAtomicHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterAtomicHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(CASPAIR,        CASPair);
   REGISTER_OP(CAS,            CAS);
   REGISTER_OP(ATOMICADD,      AtomicAdd);
@@ -880,6 +943,7 @@ void JITCore::RegisterAtomicHandlers() {
   REGISTER_OP(ATOMICFETCHAND, AtomicFetchAnd);
   REGISTER_OP(ATOMICFETCHOR,  AtomicFetchOr);
   REGISTER_OP(ATOMICFETCHXOR, AtomicFetchXor);
+  REGISTER_OP(ATOMICFETCHNEG, AtomicFetchNeg);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp

@@ -1,3 +1,11 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
+#include "Interface/Core/LookupCache.h"
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/Core/InternalThreadState.h"
 
@@ -8,17 +16,17 @@
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(GuestCallDirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestCallIndirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestReturn) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(SignalReturn) {
@@ -35,7 +43,7 @@ DEF_OP(CallbackReturn) {
 
   // spill back to CTX
   SpillStaticRegs();
-  
+
   // First we must reset the stack
   ResetStack();
 
@@ -46,9 +54,9 @@ DEF_OP(CallbackReturn) {
   str(w2, MemOperand(x0));
 
   // We need to adjust an additional 8 bytes to get back to the original "misaligned" RSP state
-  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
+  ldr(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
   add(x2, x2, 8);
-  str(x2, MemOperand(STATE, offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])));
+  str(x2, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])));
 
   PopCalleeSavedRegisters();
 
@@ -67,7 +75,7 @@ DEF_OP(ExitFunction) {
   uint64_t NewRIP;
 
   if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
-    Literal l_BranchHost{ExitFunctionLinkerAddress};
+    Literal l_BranchHost{ThreadSharedData.Dispatcher->ExitFunctionLinkerAddress};
     Literal l_BranchGuest{NewRIP};
 
     ldr(x0, &l_BranchHost);
@@ -77,9 +85,9 @@ DEF_OP(ExitFunction) {
     place(&l_BranchGuest);
   } else {
     RipReg = GetReg<RA_64>(Op->Header.Args[0].ID());
-    
+
     // L1 Cache
-    LoadConstant(x0, State->LookupCache->GetL1Pointer());
+    LoadConstant(x0, ThreadState->LookupCache->GetL1Pointer());
 
     and_(x3, RipReg, LookupCache::L1_ENTRIES_MASK);
     add(x0, x0, Operand(x3, Shift::LSL, 4));
@@ -90,8 +98,8 @@ DEF_OP(ExitFunction) {
     br(x1);
 
     bind(&FullLookup);
-    LoadConstant(TMP1, AbsoluteLoopTopAddress);
-    str(RipReg, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, State.rip)));
+    LoadConstant(TMP1, ThreadSharedData.Dispatcher->AbsoluteLoopTopAddress);
+    str(RipReg, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)));
     br(TMP1);
   }
 }
@@ -131,12 +139,12 @@ Condition MapBranchCC(IR::CondClassType Cond) {
   case FEXCore::IR::COND_FGT: return Condition::hi;
   case FEXCore::IR::COND_FU:  return Condition::vs;
   case FEXCore::IR::COND_FNU: return Condition::vc;
-  case FEXCore::IR::COND_VS:;
-  case FEXCore::IR::COND_VC:;
+  case FEXCore::IR::COND_VS:
+  case FEXCore::IR::COND_VC:
   case FEXCore::IR::COND_MI:
   case FEXCore::IR::COND_PL:
   default:
-  LogMan::Msg::A("Unsupported compare type");
+  LOGMAN_MSG_A_FMT("Unsupported compare type");
   return Condition::nv;
   }
 }
@@ -163,10 +171,10 @@ DEF_OP(CondJump) {
   bool isConst = IsInlineConstant(Op->Cmp2, &Const);
 
   if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_EQ) {
-    LogMan::Throw::A(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
+    LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
     cbz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
   } else if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_NEQ) {
-    LogMan::Throw::A(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
+    LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
     cbnz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
   } else {
     if (IsGPR(Op->Cmp1.ID())) {
@@ -177,12 +185,12 @@ DEF_OP(CondJump) {
     } else if (IsFPR(Op->Cmp1.ID())) {
       fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
     } else {
-      LogMan::Msg::A("CondJump: Expected GPR or FPR");
+      LOGMAN_MSG_A_FMT("CondJump: Expected GPR or FPR");
     }
 
     b(TrueTargetLabel, MapBranchCC(Op->Cond));
   }
-  
+
   if (FalseIter == JumpTargets.end()) {
     FalseTargetLabel = &JumpTargets.try_emplace(Op->FalseBlock.ID()).first->second;
   }
@@ -217,7 +225,7 @@ DEF_OP(Syscall) {
   blr(x3);
 
   add(sp, sp, SPOffset);
-  
+
   // Result is now in x0
   // Fix the stack and any values that were stepped on
   FillStaticRegs();
@@ -239,34 +247,30 @@ DEF_OP(Thunk) {
 
   mov(x0, GetReg<RA_64>(Op->Header.Args[0].ID()));
 
-#if _M_X86_64
-  ERROR_AND_DIE("JIT: OP_THUNK not supported with arm simulator")
-#else
-  auto thunkFn = State->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
+  auto thunkFn = ThreadState->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
   LoadConstant(x2, (uintptr_t)thunkFn);
   blr(x2);
-#endif
 
   PopDynamicRegsAndLR();
-  
+
   FillStaticRegs(); // load from ctx after ra64 refill
 }
 
 
 DEF_OP(ValidateCode) {
   auto Op = IROp->C<IR::IROp_ValidateCode>();
-  uint8_t *OldCode = (uint8_t *)&Op->CodeOriginalLow;
+  const auto *OldCode = (const uint8_t *)&Op->CodeOriginalLow;
   int len = Op->CodeLength;
   int idx = 0;
 
   LoadConstant(GetReg<RA_64>(Node), 0);
-  LoadConstant(x0, IR->GetHeader()->Entry + Op->Offset);
+  LoadConstant(x0, Entry + Op->Offset);
   LoadConstant(x1, 1);
-  
+
   while (len >= 8)
   {
     ldr(x2, MemOperand(x0, idx));
-    LoadConstant(x3, *(uint32_t *)(OldCode + idx));
+    LoadConstant(x3, *(const uint32_t *)(OldCode + idx));
     cmp(x2, x3);
     csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
     len -= 8;
@@ -275,7 +279,7 @@ DEF_OP(ValidateCode) {
   while (len >= 4)
   {
     ldr(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(uint32_t *)(OldCode + idx));
+    LoadConstant(w3, *(const uint32_t *)(OldCode + idx));
     cmp(w2, w3);
     csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
     len -= 4;
@@ -284,7 +288,7 @@ DEF_OP(ValidateCode) {
   while (len >= 2)
   {
     ldrh(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(uint16_t *)(OldCode + idx));
+    LoadConstant(w3, *(const uint16_t *)(OldCode + idx));
     cmp(w2, w3);
     csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
     len -= 2;
@@ -293,7 +297,7 @@ DEF_OP(ValidateCode) {
   while (len >= 1)
   {
     ldrb(w2, MemOperand(x0, idx));
-    LoadConstant(w3, *(uint8_t *)(OldCode + idx));
+    LoadConstant(w3, *(const uint8_t *)(OldCode + idx));
     cmp(w2, w3);
     csel(GetReg<RA_64>(Node), GetReg<RA_64>(Node), x1, Condition::eq);
     len -= 1;
@@ -302,17 +306,16 @@ DEF_OP(ValidateCode) {
 }
 
 DEF_OP(RemoveCodeEntry) {
-  auto Op = IROp->C<IR::IROp_RemoveCodeEntry>();
   // Arguments are passed as follows:
   // X0: Thread
   // X1: RIP
 
   PushDynamicRegsAndLR();
-  
+
   mov(x0, STATE);
-  LoadConstant(x1, IR->GetHeader()->Entry);
- 
-  LoadConstant(x2, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntry));
+  LoadConstant(x1, Entry);
+
+  LoadConstant(x2, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit));
   SpillStaticRegs();
   blr(x2);
   FillStaticRegs();
@@ -323,15 +326,17 @@ DEF_OP(RemoveCodeEntry) {
 
 DEF_OP(CPUID) {
   auto Op = IROp->C<IR::IROp_CPUID>();
-  
+
   PushDynamicRegsAndLR();
 
   // x0 = CPUID Handler
   // x1 = CPUID Function
+  // x2 = CPUID Leaf
   LoadConstant(x0, reinterpret_cast<uint64_t>(&CTX->CPUID));
   mov(x1, GetReg<RA_64>(Op->Header.Args[0].ID()));
+  mov(x2, GetReg<RA_64>(Op->Header.Args[1].ID()));
 
-  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t);
+  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t, uint32_t);
   union PtrCast {
     ClassPtrType ClassPtr;
     uintptr_t Data;
@@ -354,8 +359,8 @@ DEF_OP(CPUID) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterBranchHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterBranchHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(GUESTCALLDIRECT,   GuestCallDirect);
   REGISTER_OP(GUESTCALLINDIRECT, GuestCallIndirect);
   REGISTER_OP(GUESTRETURN,       GuestReturn);

External/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp

@@ -1,10 +1,16 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(VInsGPR) {
   auto Op = IROp->C<IR::IROp_VInsGPR>();
   mov(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
@@ -25,7 +31,7 @@ DEF_OP(VInsGPR) {
       ins(GetDst(Node).V2D(), Op->Index, GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
     }
-    default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -46,14 +52,10 @@ DEF_OP(VCastFromGPR) {
     case 8:
       fmov(GetDst(Node).D(), GetReg<RA_64>(Op->Header.Args[0].ID()).X());
       break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown castGPR element size: {}", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Float_FromGPR_U) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Float_FromGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
   uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
@@ -89,20 +91,7 @@ DEF_OP(Float_FToF) {
       fcvt(GetDst(Node).S(), GetSrc(Op->Header.Args[0].ID()).D());
       break;
     }
-    default: LogMan::Msg::A("Unknown FCVT sizes: 0x%x", Conv);
-  }
-}
-
-DEF_OP(Vector_UToF) {
-  auto Op = IROp->C<IR::IROp_Vector_UToF>();
-  switch (Op->Header.ElementSize) {
-    case 4:
-      ucvtf(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
-    break;
-    case 8:
-      ucvtf(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
-    break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown FCVT sizes: 0x{:x}", Conv);
   }
 }
 
@@ -115,20 +104,7 @@ DEF_OP(Vector_SToF) {
     case 8:
       scvtf(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
-  }
-}
-
-DEF_OP(Vector_FToZU) {
-  auto Op = IROp->C<IR::IROp_Vector_FToZU>();
-  switch (Op->Header.ElementSize) {
-    case 4:
-      fcvtzu(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
-    break;
-    case 8:
-      fcvtzu(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
-    break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -141,22 +117,7 @@ DEF_OP(Vector_FToZS) {
     case 8:
       fcvtzs(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
-  }
-}
-
-DEF_OP(Vector_FToU) {
-  auto Op = IROp->C<IR::IROp_Vector_FToU>();
-  switch (Op->Header.ElementSize) {
-    case 4:
-      frinti(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
-      fcvtzu(GetDst(Node).V4S(), GetDst(Node).V4S());
-    break;
-    case 8:
-      frinti(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
-      fcvtzu(GetDst(Node).V2D(), GetDst(Node).V2D());
-    break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -171,7 +132,7 @@ DEF_OP(Vector_FToS) {
       frinti(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
       fcvtzs(GetDst(Node).V2D(), GetDst(Node).V2D());
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -188,25 +149,78 @@ DEF_OP(Vector_FToF) {
       fcvtn(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2D());
       break;
     }
-    default: LogMan::Msg::A("Unknown Conversion Type : 0%04x", Conv); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToF Type : 0x{:04x}", Conv); break;
+  }
+}
+
+DEF_OP(Vector_FToI) {
+  auto Op = IROp->C<IR::IROp_Vector_FToI>();
+  switch (Op->Round) {
+    case FEXCore::IR::Round_Nearest.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintn(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintn(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Negative_Infinity.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintm(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintm(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Positive_Infinity.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintp(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintp(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Towards_Zero.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frintz(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frintz(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
+    case FEXCore::IR::Round_Host.Val:
+      switch (Op->Header.ElementSize) {
+        case 4:
+          frinti(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S());
+        break;
+        case 8:
+          frinti(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
+        break;
+      }
+    break;
   }
 }
 
 #undef DEF_OP
-void JITCore::RegisterConversionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterConversionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(VINSGPR,         VInsGPR);
   REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_U, Float_FromGPR_U);
   REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
   REGISTER_OP(FLOAT_FTOF,      Float_FToF);
-  REGISTER_OP(VECTOR_UTOF,     Vector_UToF);
   REGISTER_OP(VECTOR_STOF,     Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZU,    Vector_FToZU);
   REGISTER_OP(VECTOR_FTOZS,    Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOU,     Vector_FToU);
   REGISTER_OP(VECTOR_FTOS,     Vector_FToS);
   REGISTER_OP(VECTOR_FTOF,     Vector_FToF);
+  REGISTER_OP(VECTOR_FTOI,     Vector_FToI);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/EncryptionOps.cpp

@@ -1,10 +1,16 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(AESImc) {
   auto Op = IROp->C<IR::IROp_VAESImc>();
@@ -83,8 +89,8 @@ DEF_OP(AESKeyGenAssist) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterEncryptionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterEncryptionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(VAESIMC,     AESImc);
   REGISTER_OP(VAESENC,     AESEnc);
   REGISTER_OP(VAESENCLAST, AESEncLast);

External/FEXCore/Source/Interface/Core/JIT/Arm64/FlagOps.cpp

@@ -1,18 +1,24 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(GetHostFlag) {
   auto Op = IROp->C<IR::IROp_GetHostFlag>();
   ubfx(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), Op->Flag, 1);
 }
 
 #undef DEF_OP
-void JITCore::RegisterFlagHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterFlagHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(GETHOSTFLAG, GetHostFlag);
 #undef REGISTER_OP
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h

@@ -1,9 +1,15 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #pragma once
 
-#include "Interface/Core/LookupCache.h"
+#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
 
 #include "aarch64/assembler-aarch64.h"
-#include "aarch64/cpu-aarch64.h"
 #include "aarch64/disasm-aarch64.h"
 #include "aarch64/assembler-aarch64.h"
 
@@ -29,56 +35,18 @@ namespace FEXCore::CPU {
 using namespace vixl;
 using namespace vixl::aarch64;
 
-// All but x29 are caller saved
-const std::array<aarch64::Register, 16> SRA64 = {
-  x4, x5, x6, x7, x8, x9, x10, x11,
-  x12, x18, x17, x16, x15, x14, x13, x29
-};
-
-// All are callee saved
-const std::array<aarch64::Register, 9> RA64 = {
-  x20, x21, x22, x23, x24, x25, x26, x27,
-  x19
-};
-
-const std::array<std::pair<aarch64::Register, aarch64::Register>, 4>  RA64Pair = {{
-  {x20, x21},
-  {x22, x23},
-  {x24, x25},
-  {x26, x27},
-}};
-
-const std::array<std::pair<aarch64::Register, aarch64::Register>, 4> RA32Pair = {{
-  {w20, w21},
-  {w22, w23},
-  {w24, w25},
-  {w26, w27},
-}};
-
-// All are caller saved
-const std::array<aarch64::VRegister, 16> SRAFPR = {
-  v16, v17, v18, v19, v20, v21, v22, v23,
-  v24, v25, v26, v27, v28, v29, v30, v31
-};
-
-//  v8..v15 = (lower 64bits) Callee saved
-const std::array<aarch64::VRegister, 12> RAFPR = {
-/*v0,  v1,  v2,  v3,*/v4,  v5,  v6,  v7,  // v0 ~ v3 are used as temps
-  v8,  v9,  v10, v11, v12, v13, v14, v15
-};
-
-class JITCore final : public CPUBackend, public vixl::aarch64::Assembler  {
+class Arm64JITCore final : public CPUBackend, public Arm64Emitter  {
 public:
   struct CodeBuffer {
     uint8_t *Ptr;
     size_t Size;
   };
 
-  explicit JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, CodeBuffer Buffer, bool CompileThread);
+  explicit Arm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
 
-  ~JITCore() override;
+  ~Arm64JITCore() override;
   std::string GetName() override { return "JIT"; }
-  void *CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
+  void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
 
   void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
 
@@ -86,21 +54,22 @@ public:
 
   void ClearCache() override;
 
-  bool HandleSIGILL(int Signal, void *info, void *ucontext);
   bool HandleSIGBUS(int Signal, void *info, void *ucontext);
-  bool HandleSignalPause(int Signal, void *info, void *ucontext);
-  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
 
   static constexpr size_t INITIAL_CODE_SIZE = 1024 * 1024 * 16;
-  static CodeBuffer AllocateNewCodeBuffer(size_t Size);
+  CodeBuffer AllocateNewCodeBuffer(size_t Size);
 
   void CopyNecessaryDataForCompileThread(CPUBackend *Original) override;
 
 private:
+  FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
+
+  std::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
   Label *PendingTargetLabel;
   FEXCore::Context::Context *CTX;
-  FEXCore::Core::InternalThreadState *State;
+  FEXCore::Core::InternalThreadState *ThreadState;
   FEXCore::IR::IRListView const *IR;
+  uint64_t Entry;
 
   std::map<IR::OrderedNodeWrapper::NodeOffsetType, aarch64::Label> JumpTargets;
 
@@ -126,33 +95,35 @@ private:
   constexpr static uint8_t RA_FPR = 2;
 
   template<uint8_t RAType>
-  aarch64::Register GetReg(uint32_t Node);
+  aarch64::Register GetReg(uint32_t Node) const;
 
   template<>
-  aarch64::Register GetReg<RA_32>(uint32_t Node);
+  aarch64::Register GetReg<RA_32>(uint32_t Node) const;
   template<>
-  aarch64::Register GetReg<RA_64>(uint32_t Node);
+  aarch64::Register GetReg<RA_64>(uint32_t Node) const;
 
   template<uint8_t RAType>
-  std::pair<aarch64::Register, aarch64::Register> GetSrcPair(uint32_t Node);
+  std::pair<aarch64::Register, aarch64::Register> GetSrcPair(uint32_t Node) const;
 
   template<>
-  std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_32>(uint32_t Node);
+  std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_32>(uint32_t Node) const;
   template<>
-  std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_64>(uint32_t Node);
+  std::pair<aarch64::Register, aarch64::Register> GetSrcPair<RA_64>(uint32_t Node) const;
 
-  aarch64::VRegister GetSrc(uint32_t Node);
-  aarch64::VRegister GetDst(uint32_t Node);
+  aarch64::VRegister GetSrc(uint32_t Node) const;
+  aarch64::VRegister GetDst(uint32_t Node) const;
 
-  FEXCore::IR::RegisterClassType GetRegClass(uint32_t Node);
+  FEXCore::IR::RegisterClassType GetRegClass(uint32_t Node) const;
 
-  bool IsFPR(uint32_t Node);
-  bool IsGPR(uint32_t Node);
+  IR::PhysicalRegister GetPhys(uint32_t Node) const;
+
+  bool IsFPR(uint32_t Node) const;
+  bool IsGPR(uint32_t Node) const;
 
   MemOperand GenerateMemOperand(uint8_t AccessSize, aarch64::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale);
 
-  bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr);
-  bool IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value);
+  bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr) const;
+  bool IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value) const;
 
   struct LiveRange {
     uint32_t Begin;
@@ -162,9 +133,6 @@ private:
 #if DEBUG
   vixl::aarch64::Decoder Decoder;
 #endif
-  vixl::aarch64::CPU CPU;
-  bool SupportsAtomics{};
-  bool SupportsRCPC{};
 
   void EmplaceNewCodeBuffer(CodeBuffer Buffer) {
     CurrentCodeBuffer = &CodeBuffers.emplace_back(Buffer);
@@ -181,8 +149,6 @@ private:
   // For code safety we can't delete code buffers until outside of all signals
   std::vector<CodeBuffer> CodeBuffers{};
 
-  // This is the codebuffer that our dispatcher lives in
-  CodeBuffer DispatcherCodeBuffer{};
   // This is the current code buffer that we are tracking
   CodeBuffer *CurrentCodeBuffer{};
 
@@ -190,60 +156,24 @@ private:
   static constexpr size_t MAX_CODE_SIZE = 1024 * 1024 * 128;
   static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096 * 2;
 
-  bool IsAddressInJITCode(uint64_t Address, bool IncludeDispatcher = true);
-
 #if DEBUG
   vixl::aarch64::Disassembler Disasm;
 #endif
 
-  void LoadConstant(vixl::aarch64::Register Reg, uint64_t Constant);
-
-  void CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread);
-  void PushCalleeSavedRegisters();
-  void PopCalleeSavedRegisters();
-
-  static uint64_t ExitFunctionLink(JITCore *core, FEXCore::Core::InternalThreadState *Thread, uint64_t *record);
-
-  /**
-   * @name Dispatch Helper functions
-   * @{ */
-  uint64_t AbsoluteLoopTopAddressFillSRA{};
-  uint64_t AbsoluteLoopTopAddress{};
-  uint64_t ThreadPauseHandlerAddressSpillSRA{};
-  uint64_t ExitFunctionLinkerAddress{};
-  uint64_t ThreadPauseHandlerAddress{};
-
-  uint64_t ThreadStopHandlerAddressSpillSRA{};
-  uint64_t ThreadStopHandlerAddress{};
-  uint64_t PauseReturnInstruction{};
-
-  uint32_t SignalHandlerRefCounter{};
-
-  void StoreThreadState(int Signal, void *ucontext);
-  void RestoreThreadState(void *ucontext);
-  /**  @} */
+  static uint64_t ExitFunctionLink(Arm64JITCore *core, FEXCore::Core::CpuStateFrame *Frame, uint64_t *record);
 
   struct CompilerSharedData {
     uint64_t SignalReturnInstruction{};
 
     uint32_t *SignalHandlerRefCounterPtr{};
+    FEXCore::CPU::Dispatcher *Dispatcher{};
   };
 
   CompilerSharedData ThreadSharedData;
   IR::RegisterAllocationPass *RAPass;
   IR::RegisterAllocationData *RAData;
 
-  uint32_t SpillSlots{};
-
-  void SpillStaticRegs();
-  void FillStaticRegs();
-
-  void PushDynamicRegsAndLR();
-  void PopDynamicRegsAndLR();
-
-  void ResetStack();
-
-  using OpHandler = void (JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
+  using OpHandler = void (Arm64JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
   std::array<OpHandler, FEXCore::IR::IROps::OP_LAST + 1> OpHandlers {};
   void RegisterALUHandlers();
   void RegisterAtomicHandlers();
@@ -309,7 +239,6 @@ private:
   DEF_OP(VExtractToGPR);
   DEF_OP(Float_ToGPR_ZU);
   DEF_OP(Float_ToGPR_ZS);
-  DEF_OP(Float_ToGPR_U);
   DEF_OP(Float_ToGPR_S);
   DEF_OP(FCmp);
 
@@ -327,6 +256,7 @@ private:
   DEF_OP(AtomicFetchAnd);
   DEF_OP(AtomicFetchOr);
   DEF_OP(AtomicFetchXor);
+  DEF_OP(AtomicFetchNeg);
 
   ///< Branch ops
   DEF_OP(GuestCallDirect);
@@ -346,16 +276,13 @@ private:
   ///< Conversion ops
   DEF_OP(VInsGPR);
   DEF_OP(VCastFromGPR);
-  DEF_OP(Float_FromGPR_U);
   DEF_OP(Float_FromGPR_S);
   DEF_OP(Float_FToF);
-  DEF_OP(Vector_UToF);
   DEF_OP(Vector_SToF);
-  DEF_OP(Vector_FToZU);
   DEF_OP(Vector_FToZS);
-  DEF_OP(Vector_FToU);
   DEF_OP(Vector_FToS);
   DEF_OP(Vector_FToF);
+  DEF_OP(Vector_FToI);
 
   ///< Flag ops
   DEF_OP(GetHostFlag);
@@ -375,8 +302,11 @@ private:
   DEF_OP(StoreMem);
   DEF_OP(LoadMemTSO);
   DEF_OP(StoreMemTSO);
+  DEF_OP(ParanoidLoadMemTSO);
+  DEF_OP(ParanoidStoreMemTSO);
   DEF_OP(VLoadMemElement);
   DEF_OP(VStoreMemElement);
+  DEF_OP(CacheLineClear);
 
   ///< Misc ops
   DEF_OP(EndBlock);
@@ -402,6 +332,7 @@ private:
   DEF_OP(SplatVector4);
   DEF_OP(VMov);
   DEF_OP(VAnd);
+  DEF_OP(VBic);
   DEF_OP(VOr);
   DEF_OP(VXor);
   DEF_OP(VAdd);
@@ -412,8 +343,10 @@ private:
   DEF_OP(VSQSub);
   DEF_OP(VAddP);
   DEF_OP(VAddV);
+  DEF_OP(VUMinV);
   DEF_OP(VURAvg);
   DEF_OP(VAbs);
+  DEF_OP(VPopcount);
   DEF_OP(VFAdd);
   DEF_OP(VFAddP);
   DEF_OP(VFSub);
@@ -433,6 +366,8 @@ private:
   DEF_OP(VSMax);
   DEF_OP(VZip);
   DEF_OP(VZip2);
+  DEF_OP(VUnZip);
+  DEF_OP(VUnZip2);
   DEF_OP(VBSL);
   DEF_OP(VCMPEQ);
   DEF_OP(VCMPEQZ);
@@ -455,6 +390,7 @@ private:
   DEF_OP(VInsElement);
   DEF_OP(VInsScalarElement);
   DEF_OP(VExtractElement);
+  DEF_OP(VDupElement);
   DEF_OP(VExtr);
   DEF_OP(VSLI);
   DEF_OP(VSRI);
@@ -477,6 +413,7 @@ private:
   DEF_OP(VSMull);
   DEF_OP(VUMull2);
   DEF_OP(VSMull2);
+  DEF_OP(VUABDL);
   DEF_OP(VTBL1);
 
   ///< Encryption ops

External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp

@@ -1,10 +1,17 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
+#include <FEXCore/Utils/CompilerDefs.h>
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(LoadContext) {
   auto Op = IROp->C<IR::IROp_LoadContext>();
@@ -23,7 +30,7 @@ DEF_OP(LoadContext) {
     case 8:
       ldr(GetReg<RA_64>(Node), MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
     }
   }
   else {
@@ -44,7 +51,7 @@ DEF_OP(LoadContext) {
     case 16:
       ldr(Dst, MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
     }
   }
 }
@@ -66,7 +73,7 @@ DEF_OP(StoreContext) {
     case 8:
       str(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled StoreContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
     }
   }
   else {
@@ -87,7 +94,7 @@ DEF_OP(StoreContext) {
     case 16:
       str(Src, MemOperand(STATE, Op->Offset));
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
     }
   }
 }
@@ -95,61 +102,60 @@ DEF_OP(StoreContext) {
 
 DEF_OP(LoadRegister) {
   auto Op = IROp->C<IR::IROp_LoadRegister>();
-  uint8_t OpSize = IROp->Size;
 
   if (Op->Class == IR::GPRClass) {
-    auto regId = (Op->Offset - offsetof(FEXCore::Core::ThreadState, State.gregs[0])) / 8;
+    auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.gregs[0])) / 8;
     auto regOffs = Op->Offset & 7;
 
-    LogMan::Throw::A(regId < SRA64.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < SRA64.size(), "out of range regId");
 
     auto reg = SRA64[regId];
-    
+
     switch(Op->Header.Size) {
       case 1:
-        LogMan::Throw::A(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
         ubfx(GetReg<RA_64>(Node), reg, regOffs * 8, 8);
         break;
 
       case 2:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         ubfx(GetReg<RA_64>(Node), reg, 0, 16);
         break;
 
       case 4:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Node).GetCode() != reg.GetCode())
           mov(GetReg<RA_32>(Node), reg.W());
         break;
 
       case 8:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Node).GetCode() != reg.GetCode())
           mov(GetReg<RA_64>(Node), reg);
         break;
     }
   } else if (Op->Class == IR::FPRClass) {
-    auto regId = (Op->Offset - offsetof(FEXCore::Core::ThreadState, State.xmm[0][0])) / 16;
+    auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0])) / 16;
     auto regOffs = Op->Offset & 15;
 
-    LogMan::Throw::A(regId < SRAFPR.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < SRAFPR.size(), "out of range regId");
 
     auto guest = SRAFPR[regId];
     auto host = GetSrc(Node);
 
     switch(Op->Header.Size) {
       case 1:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         mov(host.B(), guest.B());
         break;
 
       case 2:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         fmov(host.H(), guest.H());
         break;
 
       case 4:
-        LogMan::Throw::A((regOffs & 3) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 3) == 0, "unexpected regOffs");
         if (regOffs == 0) {
           if (host.GetCode() != guest.GetCode())
             fmov(host.S(), guest.S());
@@ -159,7 +165,7 @@ DEF_OP(LoadRegister) {
         break;
 
       case 8:
-        LogMan::Throw::A((regOffs & 7) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 7) == 0, "unexpected regOffs");
         if (regOffs == 0) {
           if (host.GetCode() != guest.GetCode())
             mov(host.D(), guest.D());
@@ -169,56 +175,54 @@ DEF_OP(LoadRegister) {
         break;
 
       case 16:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (host.GetCode() != guest.GetCode())
           mov(host.Q(), guest.Q());
         break;
     }
   } else {
-    LogMan::Throw::A(false, "Unhandled Op->Class %d", Op->Class);
+    LOGMAN_THROW_A_FMT(false, "Unhandled Op->Class {}", Op->Class);
   }
 }
 
 DEF_OP(StoreRegister) {
   auto Op = IROp->C<IR::IROp_StoreRegister>();
-  uint8_t OpSize = IROp->Size;
-
 
   if (Op->Class == IR::GPRClass) {
     auto regId = Op->Offset / 8 - 1;
     auto regOffs = Op->Offset & 7;
 
-    LogMan::Throw::A(regId < SRA64.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < SRA64.size(), "out of range regId");
 
     auto reg = SRA64[regId];
-    
+
     switch(Op->Header.Size) {
       case 1:
-        LogMan::Throw::A(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), regOffs * 8, 8);
         break;
 
       case 2:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), 0, 16);
         break;
-        
+
       case 4:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), 0, 32);
         break;
 
       case 8:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Op->Value.ID()).GetCode() != reg.GetCode())
           mov(reg, GetReg<RA_64>(Op->Value.ID()));
         break;
     }
   } else if (Op->Class == IR::FPRClass) {
-    auto regId = (Op->Offset - offsetof(FEXCore::Core::ThreadState, State.xmm[0][0])) / 16;
+    auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0])) / 16;
     auto regOffs = Op->Offset & 15;
 
-    LogMan::Throw::A(regId < SRAFPR.size(), "regId out of range");
+    LOGMAN_THROW_A_FMT(regId < SRAFPR.size(), "regId out of range");
 
     auto guest = SRAFPR[regId];
     auto host = GetSrc(Op->Value.ID());
@@ -229,28 +233,28 @@ DEF_OP(StoreRegister) {
         break;
 
       case 2:
-        LogMan::Throw::A((regOffs & 1) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 1) == 0, "unexpected regOffs");
         ins(guest.V8H(), regOffs/2, host.V8H(), 0);
         break;
 
       case 4:
-        LogMan::Throw::A((regOffs & 3) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 3) == 0, "unexpected regOffs");
         ins(guest.V4S(), regOffs/4, host.V4S(), 0);
         break;
 
       case 8:
-        LogMan::Throw::A((regOffs & 7) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 7) == 0, "unexpected regOffs");
         ins(guest.V2D(), regOffs / 8, host.V2D(), 0);
         break;
 
       case 16:
-        LogMan::Throw::A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (guest.GetCode() != host.GetCode())
           mov(guest.Q(), host.Q());
         break;
     }
   } else {
-    LogMan::Throw::A(false, "Unhandled Op->Class %d", Op->Class);
+    LOGMAN_THROW_A_FMT(false, "Unhandled Op->Class {}", Op->Class);
   }
 }
 
@@ -284,15 +288,17 @@ DEF_OP(LoadContextIndexed) {
         ldr(GetReg<RA_64>(Node), MemOperand(TMP1, Op->BaseOffset));
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     case 16:
-      LogMan::Msg::A("Invalid Class load of size 16");
+      LOGMAN_MSG_A_FMT("Invalid Class load of size 16");
       break;
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
   else {
@@ -329,12 +335,14 @@ DEF_OP(LoadContextIndexed) {
         }
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
 }
@@ -370,15 +378,17 @@ DEF_OP(StoreContextIndexed) {
         str(value, MemOperand(TMP1, Op->BaseOffset));
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     case 16:
-      LogMan::Msg::A("Invalid Class load of size 16");
+      LOGMAN_MSG_A_FMT("Invalid Class store of size 16");
       break;
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
   else {
@@ -417,12 +427,14 @@ DEF_OP(StoreContextIndexed) {
         }
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
 }
@@ -430,7 +442,7 @@ DEF_OP(StoreContextIndexed) {
 DEF_OP(SpillRegister) {
   auto Op = IROp->C<IR::IROp_SpillRegister>();
   uint8_t OpSize = IROp->Size;
-  uint32_t SlotOffset = Op->Slot * 16 + 16;
+  uint32_t SlotOffset = Op->Slot * 16;
 
   if (Op->Class == FEXCore::IR::GPRClass) {
     switch (OpSize) {
@@ -450,7 +462,7 @@ DEF_OP(SpillRegister) {
       str(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -466,17 +478,17 @@ DEF_OP(SpillRegister) {
       str(GetSrc(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
     }
   } else {
-    LogMan::Msg::A("Unhandled SpillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A_FMT("Unhandled SpillRegister class: {}", Op->Class.Val);
   }
 }
 
 DEF_OP(FillRegister) {
   auto Op = IROp->C<IR::IROp_FillRegister>();
   uint8_t OpSize = IROp->Size;
-  uint32_t SlotOffset = Op->Slot * 16 + 16;
+  uint32_t SlotOffset = Op->Slot * 16;
 
   if (Op->Class == FEXCore::IR::GPRClass) {
     switch (OpSize) {
@@ -496,7 +508,7 @@ DEF_OP(FillRegister) {
       ldr(GetReg<RA_64>(Node), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled FillRegister size: {}", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -512,10 +524,10 @@ DEF_OP(FillRegister) {
       ldr(GetDst(Node), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled FillRegister size: {}", OpSize);
     }
   } else {
-    LogMan::Msg::A("Unhandled FillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A_FMT("Unhandled FillRegister class: {}", Op->Class.Val);
   }
 }
 
@@ -530,12 +542,12 @@ DEF_OP(StoreFlag) {
   strb(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag));
 }
 
-MemOperand JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) {
+MemOperand Arm64JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Register Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) {
   if (Offset.IsInvalid()) {
     return MemOperand(Base);
   } else {
     if (OffsetScale != 1 && OffsetScale != AccessSize) {
-        LogMan::Msg::A("Unhandled GenerateMemOperand OffsetScale: %d", OffsetScale);
+        LOGMAN_MSG_A_FMT("Unhandled GenerateMemOperand OffsetScale: {}", OffsetScale);
     }
     uint64_t Const;
     if (IsInlineConstant(Offset, &Const)) {
@@ -547,10 +559,12 @@ MemOperand JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Register Bas
         case IR::MEM_OFFSET_UXTW.Val: return MemOperand(Base, RegOffset.W(), Extend::UXTW, (int)std::log2(OffsetScale) );
         case IR::MEM_OFFSET_SXTW.Val: return MemOperand(Base, RegOffset.W(), Extend::SXTW, (int)std::log2(OffsetScale) );
 
-        default: LogMan::Msg::A("Unhandled GenerateMemOperand OffsetType: %d", OffsetType.Val); break;
+        default: LOGMAN_MSG_A_FMT("Unhandled GenerateMemOperand OffsetType: {}", OffsetType.Val); break;
       }
     }
   }
+
+  FEX_UNREACHABLE;
 }
 
 DEF_OP(LoadMem) {
@@ -574,7 +588,7 @@ DEF_OP(LoadMem) {
       case 8:
         ldr(Dst, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMem size: {}", Op->Size);
     }
   }
   else {
@@ -595,7 +609,7 @@ DEF_OP(LoadMem) {
       case 16:
         ldr(Dst, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMem size: {}", Op->Size);
     }
   }
 }
@@ -606,7 +620,7 @@ DEF_OP(LoadMemTSO) {
   auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
 
   if (!Op->Offset.IsInvalid()) {
-    LogMan::Msg::A("LoadMemTSO: No offset allowed");
+    LOGMAN_MSG_A_FMT("LoadMemTSO: No offset allowed");
   }
 
   if (SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
@@ -629,7 +643,7 @@ DEF_OP(LoadMemTSO) {
         case 8:
           ldapr(Dst, MemSrc);
           break;
-        default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", Op->Size);
       }
       nop();
     }
@@ -654,7 +668,7 @@ DEF_OP(LoadMemTSO) {
         case 8:
           ldar(Dst, MemSrc);
           break;
-        default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", Op->Size);
       }
       nop();
     }
@@ -675,7 +689,7 @@ DEF_OP(LoadMemTSO) {
       case 16:
         ldr(Dst, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", Op->Size);
     }
     dmb(InnerShareable, BarrierAll);
   }
@@ -702,7 +716,7 @@ DEF_OP(StoreMem) {
       case 8:
         str(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", Op->Size);
     }
   }
   else {
@@ -723,7 +737,7 @@ DEF_OP(StoreMem) {
       case 16:
         str(Src, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", Op->Size);
     }
   }
 }
@@ -733,7 +747,7 @@ DEF_OP(StoreMemTSO) {
   auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
 
   if (!Op->Offset.IsInvalid()) {
-    LogMan::Msg::A("StoreMemTSO: No offset allowed");
+    LOGMAN_MSG_A_FMT("StoreMemTSO: No offset allowed");
   }
 
   if (Op->Class == FEXCore::IR::GPRClass) {
@@ -753,7 +767,7 @@ DEF_OP(StoreMemTSO) {
         case 8:
           stlr(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
           break;
-        default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled StoreMemTSO size: {}", Op->Size);
       }
       nop();
     }
@@ -777,23 +791,166 @@ DEF_OP(StoreMemTSO) {
       case 16:
         str(Src, MemSrc);
         break;
-      default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled StoreMemTSO size: {}", Op->Size);
     }
     dmb(InnerShareable, BarrierAll);
   }
 }
 
+DEF_OP(ParanoidLoadMemTSO) {
+  auto Op = IROp->C<IR::IROp_LoadMemTSO>();
+
+  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
+
+  if (!Op->Offset.IsInvalid()) {
+    LOGMAN_MSG_A_FMT("ParanoidLoadMemTSO: No offset allowed");
+  }
+
+  if (Op->Class == FEXCore::IR::GPRClass) {
+    if (Op->Size == 1) {
+      // 8bit load is always aligned to natural alignment
+      auto Dst = GetReg<RA_64>(Node);
+      ldarb(Dst, MemSrc);
+    }
+    else {
+      auto Dst = GetReg<RA_64>(Node);
+      switch (Op->Size) {
+        case 2:
+          ldarh(Dst, MemSrc);
+          break;
+        case 4:
+          ldar(Dst.W(), MemSrc);
+          break;
+        case 8:
+          ldar(Dst, MemSrc);
+          break;
+        default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", Op->Size);
+      }
+    }
+  }
+  else {
+    auto Dst = GetDst(Node);
+    switch (Op->Size) {
+      case 2:
+        ldarh(TMP1.W(), MemSrc);
+        fmov(Dst.H(), TMP1.W());
+        break;
+      case 4:
+        ldar(TMP1.W(), MemSrc);
+        fmov(Dst.S(), TMP1.W());
+        break;
+      case 8:
+        ldar(TMP1, MemSrc);
+        fmov(Dst.D(), TMP1);
+        break;
+      case 16:
+        nop();
+        ldaxp(TMP1, TMP2, MemSrc);
+        clrex();
+        mov(Dst.V2D(), 0, TMP1);
+        mov(Dst.V2D(), 1, TMP2);
+        break;
+      default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", Op->Size);
+    }
+  }
+}
+
+DEF_OP(ParanoidStoreMemTSO) {
+  auto Op = IROp->C<IR::IROp_StoreMemTSO>();
+  auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
+
+  if (!Op->Offset.IsInvalid()) {
+    LOGMAN_MSG_A_FMT("ParanoidStoreMemTSO: No offset allowed");
+  }
+
+  if (Op->Class == FEXCore::IR::GPRClass) {
+    if (Op->Size == 1) {
+      // 8bit load is always aligned to natural alignment
+      stlrb(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+    }
+    else {
+      switch (Op->Size) {
+        case 2:
+          stlrh(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+          break;
+        case 4:
+          stlr(GetReg<RA_32>(Op->Header.Args[1].ID()), MemSrc);
+          break;
+        case 8:
+          stlr(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
+          break;
+        default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", Op->Size);
+      }
+    }
+  }
+  else {
+    auto Src = GetSrc(Op->Header.Args[1].ID());
+    if (Op->Size == 1) {
+      // 8bit load is always aligned to natural alignment
+      mov(TMP1.W(), Src.V16B(), 0);
+      stlrb(TMP1, MemSrc);
+    }
+    else {
+      switch (Op->Size) {
+        case 2:
+          mov(TMP1.W(), Src.V8H(), 0);
+          stlrh(TMP1, MemSrc);
+          break;
+        case 4:
+          mov(TMP1.W(), Src.V4S(), 0);
+          stlr(TMP1.W(), MemSrc);
+          break;
+        case 8:
+          mov(TMP1, Src.V2D(), 0);
+          stlr(TMP1, MemSrc);
+          break;
+        case 16: {
+          // Move vector to GPRs
+          mov(TMP1, Src.V2D(), 0);
+          mov(TMP2, Src.V2D(), 1);
+          Label B;
+          bind(&B);
+
+          nop(); // < Overwritten with DMB
+          // ldaxp must not have both the destination registers be the same
+          ldaxp(xzr, TMP3, MemSrc); // <- Can hit SIGBUS
+          nop(); // < Overwritten with DMB
+          stlxp(TMP3, TMP1, TMP2, MemSrc); // <- Can also hit SIGBUS
+          cbnz(TMP3, &B); // < Overwritten with DMB
+          break;
+        }
+        default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", Op->Size);
+      }
+    }
+  }
+}
+
 DEF_OP(VLoadMemElement) {
-  LogMan::Msg::A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VStoreMemElement) {
-  LogMan::Msg::A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
+}
+
+DEF_OP(CacheLineClear) {
+  auto Op = IROp->C<IR::IROp_CacheLineClear>();
+
+  auto MemReg = GetReg<RA_64>(Op->Header.Args[0].ID());
+
+  // Clear dcache only
+  // icache doesn't matter here since the guest application shouldn't be calling clflush on JIT code.
+  mov(TMP1, MemReg);
+  for (size_t i = 0; i < std::max(1U, DCacheLineSize / 64U); ++i) {
+    dc(DataCacheOp::CVAU, TMP1);
+    add(TMP1, TMP1, DCacheLineSize);
+  }
+  dsb(InnerShareable, BarrierAll);
 }
 
 #undef DEF_OP
-void JITCore::RegisterMemoryHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterMemoryHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(LOADCONTEXT,         LoadContext);
   REGISTER_OP(STORECONTEXT,        StoreContext);
   REGISTER_OP(LOADREGISTER,        LoadRegister);
@@ -806,10 +963,17 @@ void JITCore::RegisterMemoryHandlers() {
   REGISTER_OP(STOREFLAG,           StoreFlag);
   REGISTER_OP(LOADMEM,             LoadMem);
   REGISTER_OP(STOREMEM,            StoreMem);
-  REGISTER_OP(LOADMEMTSO,          LoadMemTSO);
-  REGISTER_OP(STOREMEMTSO,         StoreMemTSO);
+  if (ParanoidTSO()) {
+    REGISTER_OP(LOADMEMTSO,          ParanoidLoadMemTSO);
+    REGISTER_OP(STOREMEMTSO,         ParanoidStoreMemTSO);
+  }
+  else {
+    REGISTER_OP(LOADMEMTSO,          LoadMemTSO);
+    REGISTER_OP(STOREMEMTSO,         StoreMemTSO);
+  }
   REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
   REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
+  REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp

@@ -1,10 +1,23 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
+static void PrintValue(uint64_t Value) {
+  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
+}
+
+static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
+  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
+}
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(Fence) {
   auto Op = IROp->C<IR::IROp_Fence>();
@@ -18,7 +31,7 @@ DEF_OP(Fence) {
     case IR::Fence_Store.Val:
       dmb(FullSystem, BarrierWrites);
       break;
-    default: LogMan::Msg::A("Unknown Fence: %d", Op->Fence); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
   }
 }
 
@@ -29,30 +42,38 @@ DEF_OP(Break) {
     case 5: // Guest ud2
       hlt(4);
       break;
+    case 1: // Int <imm8>
+      hlt(4);
+      break;
+    case 2: // overflow
+      hlt(4);
+      break;
+    case 3: // int 1
+      hlt(4);
+      break;
     case 4: { // HLT
       // Time to quit
       // Set our stack to the starting stack location
-      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)));
+      ldr(TMP1, MemOperand(STATE, offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)));
       add(sp, TMP1, 0);
 
       // Now we need to jump to the thread stop handler
-      LoadConstant(TMP1, ThreadStopHandlerAddressSpillSRA);
+      LoadConstant(TMP1, ThreadSharedData.Dispatcher->ThreadStopHandlerAddressSpillSRA);
       br(TMP1);
       break;
     }
     case 6: { // INT3
       ResetStack();
 
-      LoadConstant(TMP1, ThreadPauseHandlerAddressSpillSRA);
+      LoadConstant(TMP1, ThreadSharedData.Dispatcher->ThreadPauseHandlerAddressSpillSRA);
       br(TMP1);
       break;
     }
-    default: LogMan::Msg::A("Unknown Break reason: %d", Op->Reason);
+    default: LOGMAN_MSG_A_FMT("Unknown Break reason: {}", Op->Reason);
   }
 }
 
 DEF_OP(GetRoundingMode) {
-  auto Op = IROp->C<IR::IROp_GetRoundingMode>();
   auto Dst = GetReg<RA_64>(Node);
   mrs(Dst, FPCR);
   lsr(Dst, Dst,  22);
@@ -110,9 +131,31 @@ DEF_OP(SetRoundingMode) {
   msr(FPCR, TMP1);
 }
 
+DEF_OP(Print) {
+  auto Op = IROp->C<IR::IROp_Print>();
+
+  PushDynamicRegsAndLR();
+
+  if (IsGPR(Op->Header.Args[0].ID())) {
+    mov(x0, GetReg<RA_64>(Op->Header.Args[0].ID()));
+    LoadConstant(x3, reinterpret_cast<uint64_t>(PrintValue));
+  }
+  else {
+    fmov(x0, GetSrc(Op->Header.Args[0].ID()).V1D());
+    // Bug in vixl that source vector needs to b V1D rather than V2D?
+    fmov(x1, GetSrc(Op->Header.Args[0].ID()).V1D(), 1);
+    LoadConstant(x3, reinterpret_cast<uint64_t>(PrintVectorValue));
+  }
+  SpillStaticRegs();
+  blr(x3);
+  FillStaticRegs();
+
+  PopDynamicRegsAndLR();
+}
+
 #undef DEF_OP
-void JITCore::RegisterMiscHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterMiscHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(DUMMY,      NoOp);
   REGISTER_OP(IRHEADER,   NoOp);
   REGISTER_OP(CODEBLOCK,  NoOp);
@@ -122,7 +165,7 @@ void JITCore::RegisterMiscHandlers() {
   REGISTER_OP(BREAK,      Break);
   REGISTER_OP(PHI,        NoOp);
   REGISTER_OP(PHIVALUE,   NoOp);
-  REGISTER_OP(PRINT,      Unhandled);
+  REGISTER_OP(PRINT,      Print);
   REGISTER_OP(GETROUNDINGMODE, GetRoundingMode);
   REGISTER_OP(SETROUNDINGMODE, SetRoundingMode);
   REGISTER_OP(INVALIDATEFLAGS,   NoOp);

External/FEXCore/Source/Interface/Core/JIT/Arm64/MoveOps.cpp

@@ -1,10 +1,16 @@
+/*
+$info$
+tags: backend|arm64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
 namespace FEXCore::CPU {
 
 using namespace vixl;
 using namespace vixl::aarch64;
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(ExtractElementPair) {
   auto Op = IROp->C<IR::IROp_ExtractElementPair>();
   switch (Op->Header.Size) {
@@ -20,7 +26,7 @@ DEF_OP(ExtractElementPair) {
       mov (GetReg<RA_64>(Node), Regs[Op->Element]);
       break;
     }
-    default: LogMan::Msg::A("Unknown Size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
   }
 }
 
@@ -46,7 +52,7 @@ DEF_OP(CreateElementPair) {
       RegTmp = x0;
       break;
     }
-    default: LogMan::Msg::A("Unknown Size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
   }
 
   if (Dst.first.GetCode() != RegSecond.GetCode()) {
@@ -68,8 +74,8 @@ DEF_OP(Mov) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterMoveHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void Arm64JITCore::RegisterMoveHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
   REGISTER_OP(EXTRACTELEMENTPAIR, ExtractElementPair);
   REGISTER_OP(CREATEELEMENTPAIR,  CreateElementPair);
   REGISTER_OP(MOV,                Mov);

External/FEXCore/Source/Interface/Core/JIT/JITCore.h

@@ -1,5 +1,7 @@
 #pragma once
 
+#include <memory>
+
 namespace FEXCore::Context {
 struct Context;
 }
@@ -11,5 +13,6 @@ struct InternalThreadState;
 namespace FEXCore::CPU {
 class CPUBackend;
 
-FEXCore::CPU::CPUBackend *CreateJITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
+std::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
+std::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, bool CompileThread);
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp

@@ -1,8 +1,14 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(TruncElementPair) {
   auto Op = IROp->C<IR::IROp_TruncElementPair>();
 
@@ -14,7 +20,7 @@ DEF_OP(TruncElementPair) {
       mov(Dst.second, Src.second);
       break;
     }
-    default: LogMan::Msg::A("Unhandled Truncation size: %d", Op->Size); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", Op->Size); break;
   }
 }
 
@@ -26,7 +32,7 @@ DEF_OP(Constant) {
 DEF_OP(EntrypointOffset) {
   auto Op = IROp->C<IR::IROp_EntrypointOffset>();
 
-  auto Constant = IR->GetHeader()->Entry + Op->Offset;
+  auto Constant = Entry + Op->Offset;
   mov(GetDst<RA_64>(Node), Constant);
 }
 
@@ -64,7 +70,7 @@ DEF_OP(Add) {
     case 8:
       add(rax, Const);
       break;
-    default:  LogMan::Msg::A("Unhandled Add size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Add size: {}", OpSize);
       break;
     }
   } else {
@@ -75,7 +81,7 @@ DEF_OP(Add) {
     case 8:
       add(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled Add size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Add size: {}", OpSize);
       break;
     }
   }
@@ -97,7 +103,7 @@ DEF_OP(Sub) {
     case 8:
       sub(rax, Const);
       break;
-    default:  LogMan::Msg::A("Unhandled Sub size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Sub size: {}", OpSize);
       break;
     }
   } else {
@@ -108,7 +114,7 @@ DEF_OP(Sub) {
     case 8:
       sub(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled Sub size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Sub size: {}", OpSize);
       break;
     }
   }
@@ -130,7 +136,7 @@ DEF_OP(Neg) {
     Src = GetSrc<RA_64>(Op->Header.Args[0].ID());
     Dst = GetDst<RA_64>(Node);
     break;
-  default:  LogMan::Msg::A("Unhandled Neg size: %d", OpSize);
+  default:  LOGMAN_MSG_A_FMT("Unhandled Neg size: {}", OpSize);
     break;
   }
   mov(Dst, Src);
@@ -154,7 +160,7 @@ DEF_OP(Mul) {
     imul(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(Dst, rax);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown Mul size: {}", OpSize);
   }
 }
 
@@ -173,7 +179,7 @@ DEF_OP(UMul) {
     mul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rax);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown UMul size: {}", OpSize);
   }
 }
 
@@ -212,7 +218,7 @@ DEF_OP(Div) {
     mov(GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV Size: %d", Size); break;
+  default: LOGMAN_MSG_A_FMT("Unknown DIV Size: {}", Size); break;
   }
 }
 
@@ -255,7 +261,7 @@ DEF_OP(UDiv) {
     mov(GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV OpSize: %d", OpSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown UDIV OpSize: {}", OpSize); break;
   }
 }
 
@@ -292,7 +298,7 @@ DEF_OP(Rem) {
     mov(GetDst<RA_64>(Node), rdx);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV Size: %d", OpSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown Rem Size: {}", OpSize); break;
   }
 }
 
@@ -335,7 +341,7 @@ DEF_OP(URem) {
     mov(GetDst<RA_64>(Node), rdx);
   break;
   }
-  default: LogMan::Msg::A("Unknown UDIV OpSize: %d", OpSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown URem OpSize: {}", OpSize); break;
   }
 }
 
@@ -354,7 +360,7 @@ DEF_OP(MulH) {
     imul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rdx);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown MulH size: {}", OpSize);
   }
 }
 
@@ -373,7 +379,7 @@ DEF_OP(UMulH) {
     mul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rdx);
   break;
-  default: LogMan::Msg::A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown UMulH size: {}", OpSize);
   }
 }
 
@@ -435,7 +441,7 @@ DEF_OP(Lshl) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shl(GetDst<RA_64>(Node), Const);
         break;
-      default: LogMan::Msg::A("Unknown LSHL Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown LSHL Size: {}\n", OpSize); break;
     };
   } else {
     mov(rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
@@ -450,7 +456,7 @@ DEF_OP(Lshl) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shl(GetDst<RA_64>(Node), cl);
         break;
-      default: LogMan::Msg::A("Unknown LSHL Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown LSHL Size: {}\n", OpSize); break;
     };
   }
 }
@@ -482,7 +488,7 @@ DEF_OP(Lshr) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shr(GetDst<RA_64>(Node), Const);
         break;
-      default: LogMan::Msg::A("Unknown Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Size: {}\n", OpSize); break;
     };
 
   } else {
@@ -506,7 +512,7 @@ DEF_OP(Lshr) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shr(GetDst<RA_64>(Node), cl);
         break;
-      default: LogMan::Msg::A("Unknown Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Size: {}\n", OpSize); break;
     };
   }
 }
@@ -540,7 +546,7 @@ DEF_OP(Ashr) {
       mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       sar(GetDst<RA_64>(Node), Const);
     break;
-    default: LogMan::Msg::A("Unknown ASHR Size: %d\n", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown ASHR Size: {}\n", OpSize); break;
     };
 
   } else {
@@ -565,7 +571,7 @@ DEF_OP(Ashr) {
       mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       sar(GetDst<RA_64>(Node), cl);
     break;
-    default: LogMan::Msg::A("Unknown ASHR Size: %d\n", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown ASHR Size: {}\n", OpSize); break;
     };
   }
 }
@@ -590,7 +596,7 @@ DEF_OP(Ror) {
         ror(rax, Const);
       break;
       }
-      default: LogMan::Msg::A("Unknown ROR Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown ROR Size: {}\n", OpSize); break;
     }
   } else {
     mov (rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
@@ -606,7 +612,7 @@ DEF_OP(Ror) {
         ror(rax, cl);
       break;
       }
-      default: LogMan::Msg::A("Unknown ROR Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown ROR Size: {}\n", OpSize); break;
     }
   }
   mov(GetDst<RA_64>(Node), rax);
@@ -662,7 +668,7 @@ DEF_OP(LDiv) {
       mov(GetDst<RA_64>(Node), rax);
       break;
     }
-    default: LogMan::Msg::A("Unknown LDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LDIV OpSize: {}", OpSize); break;
   }
 }
 
@@ -694,7 +700,7 @@ DEF_OP(LUDiv) {
       mov(GetDst<RA_64>(Node), rax);
       break;
     }
-    default: LogMan::Msg::A("Unknown LUDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUDIV OpSize: {}", OpSize); break;
   }
 }
 
@@ -726,7 +732,7 @@ DEF_OP(LRem) {
       mov(GetDst<RA_64>(Node), rdx);
       break;
     }
-    default: LogMan::Msg::A("Unknown LREM OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LREM OpSize: {}", OpSize); break;
   }
 }
 
@@ -758,7 +764,7 @@ DEF_OP(LURem) {
       mov(GetDst<RA_64>(Node), rdx);
       break;
     }
-    default: LogMan::Msg::A("Unknown LUDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUREM OpSize: {}", OpSize); break;
   }
 }
 
@@ -823,7 +829,7 @@ DEF_OP(FindMSB) {
     case 8:
       bsr(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LogMan::Msg::A("Unknown OpSize: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown FindMSB OpSize: {}", OpSize);
   }
 }
 
@@ -847,7 +853,7 @@ DEF_OP(FindTrailingZeros) {
       mov(rax, 0x40);
       cmovz(GetDst<RA_64>(Node), rax);
       break;
-    default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown FindTrailingZeros size: {}", OpSize); break;
   }
 }
 
@@ -870,7 +876,7 @@ DEF_OP(CountLeadingZeroes) {
         lzcnt(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         break;
       }
-      default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown CountLeadingZeros size: {}", OpSize); break;
     }
   }
   else {
@@ -909,7 +915,7 @@ DEF_OP(CountLeadingZeroes) {
         mov(GetDst<RA_64>(Node), rax);
         break;
       }
-      default: LogMan::Msg::A("Unknown size: %d", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown CountLeadingZeros size: {}", OpSize); break;
     }
   }
 }
@@ -931,7 +937,7 @@ DEF_OP(Rev) {
       mov (GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       bswap(GetDst<RA_64>(Node).cvt64());
       break;
-    default: LogMan::Msg::A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown REV size: {}", OpSize); break;
   }
 }
 
@@ -964,9 +970,7 @@ DEF_OP(Bfi) {
 
 DEF_OP(Bfe) {
   auto Op = IROp->C<IR::IROp_Bfe>();
-  uint8_t OpSize = IROp->Size;
-
-  LogMan::Throw::A(OpSize <= 8, "OpSize is too large for BFE: %d", OpSize);
+  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
 
   auto Dst = GetDst<RA_64>(Node);
 
@@ -1067,7 +1071,7 @@ DEF_OP(Select) {
 
   if (is_const_true || is_const_false) {
     if (is_const_false != true || is_const_true != true || const_true != 1 || const_false != 0) {
-      LogMan::Msg::A("Select: Unsupported compare inline parameters");
+      LOGMAN_MSG_A_FMT("Select: Unsupported compare inline parameters");
     }
     (this->*SetCC)(al);
     movzx(Dst, al);
@@ -1098,46 +1102,67 @@ DEF_OP(VExtractToGPR) {
       pextrq(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Idx);
     break;
     }
-    default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
-DEF_OP(Float_ToGPR_ZU) {
-  LogMan::Msg::D("Unimplemented");
-}
-
 DEF_OP(Float_ToGPR_ZS) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_ZS>();
-  if (Op->Header.ElementSize == 8) {
-    cvttsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
-  }
-  else {
-    cvttss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
-  }
-}
 
-DEF_OP(Float_ToGPR_U) {
-  LogMan::Msg::D("Unimplemented");
+  uint16_t Conv = (IROp->Size << 8) | Op->SrcElementSize;
+  switch (Conv) {
+    case 0x0804: // int64_t <- float
+      cvttss2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0808: // int64_t <- double
+      cvttsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0404: // int32_t <- float
+      cvttss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0408: // int32_t <- double
+      cvttsd2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+  }
 }
 
 DEF_OP(Float_ToGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_ToGPR_S>();
-  if (Op->Header.ElementSize == 8) {
-    cvtsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
-  }
-  else {
-    cvtss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+  uint16_t Conv = (IROp->Size << 8) | Op->SrcElementSize;
+  switch (Conv) {
+    case 0x0804: // int64_t <- float
+      cvtss2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0808: // int64_t <- double
+      cvtsd2si(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0404: // int32_t <- float
+      cvtss2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
+    case 0x0408: // int32_t <- double
+      cvtsd2si(GetDst<RA_32>(Node), GetSrc(Op->Header.Args[0].ID()));
+    break;
   }
 }
 
 DEF_OP(FCmp) {
   auto Op = IROp->C<IR::IROp_FCmp>();
 
-  if (Op->ElementSize == 4) {
-    ucomiss(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+  if (Op->Flags & (1 << IR::FCMP_FLAG_UNORDERED)) {
+    if (Op->ElementSize == 4) {
+      ucomiss(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
+    else {
+      ucomisd(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
   }
   else {
-    ucomisd(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    if (Op->ElementSize == 4) {
+      comiss(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
+    else {
+      comisd(GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
+    }
   }
   mov (rdx, 0);
 
@@ -1168,8 +1193,8 @@ DEF_OP(FCmp) {
 
 #undef DEF_OP
 
-void JITCore::RegisterALUHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterALUHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(TRUNCELEMENTPAIR,  TruncElementPair);
   REGISTER_OP(CONSTANT,          Constant);
   REGISTER_OP(ENTRYPOINTOFFSET,  EntrypointOffset);
@@ -1211,9 +1236,7 @@ void JITCore::RegisterALUHandlers() {
   REGISTER_OP(SBFE,              Sbfe);
   REGISTER_OP(SELECT,            Select);
   REGISTER_OP(VEXTRACTTOGPR,     VExtractToGPR);
-  REGISTER_OP(FLOAT_TOGPR_ZU,    Float_ToGPR_ZU);
   REGISTER_OP(FLOAT_TOGPR_ZS,    Float_ToGPR_ZS);
-  REGISTER_OP(FLOAT_TOGPR_U,     Float_ToGPR_U);
   REGISTER_OP(FLOAT_TOGPR_S,     Float_ToGPR_S);
   REGISTER_OP(FCMP,              FCmp);
 #undef REGISTER_OP

External/FEXCore/Source/Interface/Core/JIT/x86_64/AtomicOps.cpp

@@ -1,8 +1,14 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(CASPair) {
   auto Op = IROp->C<IR::IROp_CAS>();
   uint8_t OpSize = IROp->Size;
@@ -49,7 +55,7 @@ DEF_OP(CASPair) {
       mov(Dst.second, rdx);
     break;
     }
-    default: LogMan::Msg::A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
   }
 }
 
@@ -68,7 +74,6 @@ DEF_OP(CAS) {
 
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[2].ID());
 
-  mov(rdx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
   mov(rax, GetSrc<RA_64>(Op->Header.Args[0].ID()));
 
   // RCX now contains pointer
@@ -76,31 +81,31 @@ DEF_OP(CAS) {
   // RDX contains our desired
 
   lock();
-
   switch (OpSize) {
   case 1: {
-    cmpxchg(byte [MemReg], dl);
-    movzx(rax, al);
+    cmpxchg(byte [MemReg], GetSrc<RA_8>(Op->Header.Args[1].ID()));
+    movzx(GetDst<RA_64>(Node), al);
   break;
   }
   case 2: {
-    cmpxchg(word [MemReg], dx);
-    movzx(rax, ax);
+    cmpxchg(word [MemReg], GetSrc<RA_16>(Op->Header.Args[1].ID()));
+    movzx(GetDst<RA_64>(Node), ax);
   break;
   }
   case 4: {
-    cmpxchg(dword [MemReg], edx);
+    cmpxchg(dword [MemReg], GetSrc<RA_32>(Op->Header.Args[1].ID()));
+    // RAX now contains the result
+    mov (GetDst<RA_64>(Node), eax);
   break;
   }
   case 8: {
-    cmpxchg(qword [MemReg], rdx);
+    cmpxchg(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
+    // RAX now contains the result
+    mov (GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LogMan::Msg::A("Unsupported: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
   }
-
-  // RAX now contains the result
-  mov (GetDst<RA_64>(Node), rax);
 }
 
 DEF_OP(AtomicAdd) {
@@ -122,7 +127,7 @@ DEF_OP(AtomicAdd) {
     case 8:
       add(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", Op->Size);
   }
 }
 
@@ -144,7 +149,7 @@ DEF_OP(AtomicSub) {
     case 8:
       sub(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", Op->Size);
   }
 }
 
@@ -166,7 +171,7 @@ DEF_OP(AtomicAnd) {
     case 8:
       and_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", Op->Size);
   }
 }
 
@@ -188,7 +193,7 @@ DEF_OP(AtomicOr) {
     case 8:
       or_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", Op->Size);
   }
 }
 
@@ -210,7 +215,7 @@ DEF_OP(AtomicXor) {
     case 8:
       xor_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", Op->Size);
   }
 }
 
@@ -222,17 +227,17 @@ DEF_OP(AtomicSwap) {
 
   switch (Op->Size) {
     case 1:
-      mov(GetDst<RA_8>(Node), GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      movzx(GetDst<RA_64>(Node), GetSrc<RA_8>(Op->Header.Args[1].ID()));
       lock();
       xchg(byte [MemReg], GetDst<RA_8>(Node));
       break;
     case 2:
-      mov(GetDst<RA_16>(Node), GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      movzx(GetDst<RA_64>(Node), GetSrc<RA_16>(Op->Header.Args[1].ID()));
       lock();
       xchg(word [MemReg], GetDst<RA_16>(Node));
       break;
     case 4:
-      mov(GetDst<RA_32>(Node), GetSrc<RA_32>(Op->Header.Args[1].ID()));
+      mov(GetDst<RA_64>(Node), GetSrc<RA_32>(Op->Header.Args[1].ID()));
       lock();
       xchg(dword [MemReg], GetDst<RA_32>(Node));
       break;
@@ -241,7 +246,7 @@ DEF_OP(AtomicSwap) {
       lock();
       xchg(qword [MemReg], GetDst<RA_64>(Node));
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicSwap size: {}", Op->Size);
   }
 }
 
@@ -251,13 +256,13 @@ DEF_OP(AtomicFetchAdd) {
   Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
   switch (Op->Size) {
     case 1:
-      mov(cl, GetSrc<RA_8>(Op->Header.Args[1].ID()));
+      movzx(rcx, GetSrc<RA_8>(Op->Header.Args[1].ID()));
       lock();
       xadd(byte [MemReg], cl);
       movzx(GetDst<RA_32>(Node), cl);
       break;
     case 2:
-      mov(cx, GetSrc<RA_16>(Op->Header.Args[1].ID()));
+      movzx(rcx, GetSrc<RA_16>(Op->Header.Args[1].ID()));
       lock();
       xadd(word [MemReg], cx);
       movzx(GetDst<RA_32>(Node), cx);
@@ -266,7 +271,7 @@ DEF_OP(AtomicFetchAdd) {
       mov(ecx, GetSrc<RA_32>(Op->Header.Args[1].ID()));
       lock();
       xadd(dword [MemReg], ecx);
-      mov(GetDst<RA_32>(Node), ecx);
+      mov(GetDst<RA_64>(Node), ecx);
       break;
     case 8:
       mov(rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
@@ -274,7 +279,7 @@ DEF_OP(AtomicFetchAdd) {
       xadd(qword [MemReg], rcx);
       mov(GetDst<RA_64>(Node), rcx);
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchAdd size: {}", Op->Size);
   }
 }
 
@@ -311,7 +316,7 @@ DEF_OP(AtomicFetchSub) {
       xadd(qword [MemReg], rcx);
       mov(GetDst<RA_64>(Node), rcx);
       break;
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchSub size: {}", Op->Size);
   }
 }
 
@@ -389,7 +394,7 @@ DEF_OP(AtomicFetchAnd) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchAnd size: {}", Op->Size);
   }
 }
 
@@ -466,7 +471,7 @@ DEF_OP(AtomicFetchOr) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchOr size: {}", Op->Size);
   }
 }
 
@@ -543,13 +548,89 @@ DEF_OP(AtomicFetchXor) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LogMan::Msg::A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchXor size: {}", Op->Size);
+  }
+}
+
+DEF_OP(AtomicFetchNeg) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
+
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  switch (Op->Size) {
+    case 1: {
+      mov(TMP1.cvt8(), byte [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt8(), TMP1.cvt8());
+      mov(TMP3.cvt8(), TMP1.cvt8());
+      neg(TMP2.cvt8());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
+      jne(Loop);
+      // Result is the previous value from memory, which is currently in TMP3
+      movzx(GetDst<RA_64>(Node), TMP3.cvt8());
+      break;
+    }
+    case 2: {
+      mov(TMP1.cvt16(), word [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt16(), TMP1.cvt16());
+      mov(TMP3.cvt16(), TMP1.cvt16());
+      neg(TMP2.cvt16());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(word [MemReg], TMP2.cvt16());
+      jne(Loop);
+
+      // Result is the previous value from memory, which is currently in TMP3
+      movzx(GetDst<RA_64>(Node), TMP3.cvt16());
+      break;
+    }
+    case 4: {
+      mov(TMP1.cvt32(), dword [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt32(), TMP1.cvt32());
+      mov(TMP3.cvt32(), TMP1.cvt32());
+      neg(TMP2.cvt32());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
+      jne(Loop);
+
+      // Result is the previous value from memory, which is currently in TMP3
+      mov(GetDst<RA_32>(Node), TMP3.cvt32());
+      break;
+    }
+    case 8: {
+      mov(TMP1.cvt64(), qword [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt64(), TMP1.cvt64());
+      mov(TMP3.cvt64(), TMP1.cvt64());
+      neg(TMP2.cvt64());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
+      jne(Loop);
+
+      // Result is the previous value from memory, which is currently in TMP3
+      mov(GetDst<RA_64>(Node), TMP3.cvt64());
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchNeg size: {}", Op->Size);
   }
 }
 
 #undef DEF_OP
-void JITCore::RegisterAtomicHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterAtomicHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(CASPAIR,        CASPair);
   REGISTER_OP(CAS,            CAS);
   REGISTER_OP(ATOMICADD,      AtomicAdd);
@@ -563,6 +644,7 @@ void JITCore::RegisterAtomicHandlers() {
   REGISTER_OP(ATOMICFETCHAND, AtomicFetchAnd);
   REGISTER_OP(ATOMICFETCHOR,  AtomicFetchOr);
   REGISTER_OP(ATOMICFETCHXOR, AtomicFetchXor);
+  REGISTER_OP(ATOMICFETCHNEG, AtomicFetchNeg);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp

@@ -1,3 +1,11 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
+#include "Interface/Core/LookupCache.h"
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
@@ -6,17 +14,17 @@
 #include <Interface/HLE/Thunks/Thunks.h>
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(GuestCallDirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestCallIndirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestReturn) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(SignalReturn) {
@@ -40,7 +48,7 @@ DEF_OP(CallbackReturn) {
   sub(dword [rax], 1);
 
   // We need to adjust an additional 8 bytes to get back to the original "misaligned" RSP state
-  add(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.gregs[X86State::REG_RSP])], 8);
+  add(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.gregs[X86State::REG_RSP])], 8);
 
   // Now jump back to the thunk
   // XXX: XMM?
@@ -75,12 +83,12 @@ DEF_OP(ExitFunction) {
     jmp(qword[rax]);
 
     L(l_BranchHost);
-    dq(ExitFunctionLinkerAddress);
+    dq(ThreadSharedData.Dispatcher->ExitFunctionLinkerAddress);
     L(l_BranchGuest);
     dq(NewRIP);
   } else {
     Xbyak::Reg RipReg = GetSrc<RA_64>(Op->NewRIP.ID());
-    
+
     // L1 Cache
     mov(rcx, ThreadState->LookupCache->GetL1Pointer());
     mov(rax, RipReg);
@@ -89,14 +97,14 @@ DEF_OP(ExitFunction) {
     shl(rax, 4);
 
     Xbyak::RegExp LookupBase = rcx + rax;
-  
+
     cmp(qword[LookupBase + 8], RipReg);
     jne(FullLookup);
     jmp(qword[LookupBase + 0]);
 
     L(FullLookup);
-    mov(rax, AbsoluteLoopTopAddress);
-    mov(qword [STATE + offsetof(FEXCore::Core::InternalThreadState, State.State.rip)], RipReg);
+    mov(rax, ThreadSharedData.Dispatcher->AbsoluteLoopTopAddress);
+    mov(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, State.rip)], RipReg);
     jmp(rax);
   }
 
@@ -227,7 +235,7 @@ DEF_OP(Thunk) {
     sub(rsp, 8); // Align
 
   mov(rdi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
-  
+
   auto thunkFn = ThreadState->CTX->ThunkHandler->LookupThunk(Op->ThunkNameHash);
 
   mov(rax, reinterpret_cast<uintptr_t>(thunkFn));
@@ -242,28 +250,28 @@ DEF_OP(Thunk) {
 
 DEF_OP(ValidateCode) {
   auto Op = IROp->C<IR::IROp_ValidateCode>();
-  uint8_t* OldCode = (uint8_t*)&Op->CodeOriginalLow;
+  const auto* OldCode = (const uint8_t*)&Op->CodeOriginalLow;
   int len = Op->CodeLength;
   int idx = 0;
 
   xor_(GetDst<RA_64>(Node), GetDst<RA_64>(Node));
-  mov(rax, IR->GetHeader()->Entry + Op->Offset);
+  mov(rax, Entry + Op->Offset);
   mov(rbx, 1);
   while (len >= 4) {
-    cmp(dword[rax + idx], *(uint32_t*)(OldCode + idx));
+    cmp(dword[rax + idx], *(const uint32_t*)(OldCode + idx));
     cmovne(GetDst<RA_64>(Node), rbx);
     len-=4;
     idx+=4;
   }
   while (len >= 2) {
-    mov(rcx, *(uint16_t*)(OldCode + idx));
+    mov(rcx, *(const uint16_t*)(OldCode + idx));
     cmp(word[rax + idx], cx);
     cmovne(GetDst<RA_64>(Node), rbx);
     len-=2;
     idx+=2;
   }
   while (len >= 1) {
-    cmp(byte[rax + idx], *(uint8_t*)(OldCode + idx));
+    cmp(byte[rax + idx], *(const uint8_t*)(OldCode + idx));
     cmovne(GetDst<RA_64>(Node), rbx);
     len-=1;
     idx+=1;
@@ -271,8 +279,6 @@ DEF_OP(ValidateCode) {
 }
 
 DEF_OP(RemoveCodeEntry) {
-  auto Op = IROp->C<IR::IROp_RemoveCodeEntry>();
-
   auto NumPush = RA64.size();
 
   for (auto &Reg : RA64)
@@ -282,11 +288,11 @@ DEF_OP(RemoveCodeEntry) {
     sub(rsp, 8); // Align
 
   mov(rdi, STATE);
-  mov(rax, IR->GetHeader()->Entry); // imm64 move
+  mov(rax, Entry); // imm64 move
   mov(rsi, rax);
 
 
-  mov(rax, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntry));
+  mov(rax, reinterpret_cast<uintptr_t>(&Context::Context::RemoveCodeEntryFromJit));
   call(rax);
 
   if (NumPush & 1)
@@ -299,7 +305,7 @@ DEF_OP(RemoveCodeEntry) {
 DEF_OP(CPUID) {
   auto Op = IROp->C<IR::IROp_CPUID>();
 
-  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t Function);
+  using ClassPtrType = FEXCore::CPUID::FunctionResults (FEXCore::CPUIDEmu::*)(uint32_t Function, uint32_t Leaf);
   union {
     ClassPtrType ClassPtr;
     uint64_t Raw;
@@ -315,7 +321,9 @@ DEF_OP(CPUID) {
   //
   // Result: RAX, RDX. 4xi32
 
-  mov (rsi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
+  // rsi can be in the source registers, so copy argument to edx first
+  mov (edx, GetSrc<RA_32>(Op->Header.Args[1].ID()));
+  mov (esi, GetSrc<RA_32>(Op->Header.Args[0].ID()));
   mov (rdi, reinterpret_cast<uint64_t>(&CTX->CPUID));
 
   auto NumPush = RA64.size();
@@ -341,8 +349,8 @@ DEF_OP(CPUID) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterBranchHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterBranchHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(GUESTCALLDIRECT,   GuestCallDirect);
   REGISTER_OP(GUESTCALLINDIRECT, GuestCallIndirect);
   REGISTER_OP(GUESTRETURN,       GuestReturn);

External/FEXCore/Source/Interface/Core/JIT/x86_64/ConversionOps.cpp

@@ -1,9 +1,15 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(VInsGPR) {
   auto Op = IROp->C<IR::IROp_VInsGPR>();
   movapd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
@@ -25,7 +31,7 @@ DEF_OP(VInsGPR) {
       pinsrq(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[1].ID()), Op->Index);
       break;
     }
-    default: LogMan::Msg::A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -46,14 +52,10 @@ DEF_OP(VCastFromGPR) {
     case 8:
       vmovq(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()).cvt64());
       break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown VCastFromGPR element size: {}", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Float_FromGPR_U) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Float_FromGPR_S) {
   auto Op = IROp->C<IR::IROp_Float_FromGPR_S>();
   uint16_t Conv = (Op->Header.ElementSize << 8) | Op->SrcElementSize;
@@ -89,14 +91,10 @@ DEF_OP(Float_FToF) {
       cvtsd2ss(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
     }
-    default: LogMan::Msg::A("Unknown FCVT sizes: 0x%x", Conv);
+    default: LOGMAN_MSG_A_FMT("Unknown Float_FToF sizes: 0x{:x}", Conv);
   }
 }
 
-DEF_OP(Vector_UToF) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Vector_SToF) {
   auto Op = IROp->C<IR::IROp_Vector_SToF>();
   switch (Op->Header.ElementSize) {
@@ -115,14 +113,10 @@ DEF_OP(Vector_SToF) {
       cvtsi2sd(xmm15, rax);
       movlhps(GetDst(Node), xmm15);
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Vector_FToZU) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Vector_FToZS) {
   auto Op = IROp->C<IR::IROp_Vector_FToZS>();
   switch (Op->Header.ElementSize) {
@@ -132,14 +126,10 @@ DEF_OP(Vector_FToZS) {
     case 8:
       cvttpd2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", Op->Header.ElementSize);
   }
 }
 
-DEF_OP(Vector_FToU) {
-  LogMan::Msg::A("Unimplemented");
-}
-
 DEF_OP(Vector_FToS) {
   auto Op = IROp->C<IR::IROp_Vector_FToS>();
   switch (Op->Header.ElementSize) {
@@ -149,7 +139,7 @@ DEF_OP(Vector_FToS) {
     case 8:
       cvtpd2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LogMan::Msg::A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -166,25 +156,54 @@ DEF_OP(Vector_FToF) {
       cvtpd2ps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
     }
-    default: LogMan::Msg::A("Unknown Conversion Type : 0%04x", Conv); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToF conversion type : 0x{:04x}", Conv); break;
+  }
+}
+
+DEF_OP(Vector_FToI) {
+  auto Op = IROp->C<IR::IROp_Vector_FToI>();
+  uint8_t RoundMode{};
+
+  switch (Op->Round) {
+    case FEXCore::IR::Round_Nearest.Val:
+      RoundMode = 0b0000'0'0'00;
+    break;
+    case FEXCore::IR::Round_Negative_Infinity.Val:
+      RoundMode = 0b0000'0'0'01;
+    break;
+    case FEXCore::IR::Round_Positive_Infinity.Val:
+      RoundMode = 0b0000'0'0'10;
+    break;
+    case FEXCore::IR::Round_Towards_Zero.Val:
+      RoundMode = 0b0000'0'0'11;
+    break;
+    case FEXCore::IR::Round_Host.Val:
+      RoundMode = 0b0000'0'1'00;
+    break;
+  }
+
+  switch (Op->Header.ElementSize) {
+    case 4:
+      roundps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), RoundMode);
+    break;
+    case 8:
+      roundpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), RoundMode);
+    break;
   }
 }
 
 #undef DEF_OP
-void JITCore::RegisterConversionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterConversionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(VINSGPR,         VInsGPR);
   REGISTER_OP(VCASTFROMGPR,    VCastFromGPR);
-  REGISTER_OP(FLOAT_FROMGPR_U, Float_FromGPR_U);
   REGISTER_OP(FLOAT_FROMGPR_S, Float_FromGPR_S);
   REGISTER_OP(FLOAT_FTOF,      Float_FToF);
-  REGISTER_OP(VECTOR_UTOF,     Vector_UToF);
   REGISTER_OP(VECTOR_STOF,     Vector_SToF);
-  REGISTER_OP(VECTOR_FTOZU,    Vector_FToZU);
   REGISTER_OP(VECTOR_FTOZS,    Vector_FToZS);
-  REGISTER_OP(VECTOR_FTOU,     Vector_FToU);
   REGISTER_OP(VECTOR_FTOS,     Vector_FToS);
   REGISTER_OP(VECTOR_FTOF,     Vector_FToF);
+  REGISTER_OP(VECTOR_FTOI,     Vector_FToI);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/EncryptionOps.cpp

@@ -1,8 +1,14 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(AESImc) {
   auto Op = IROp->C<IR::IROp_VAESImc>();
@@ -35,8 +41,8 @@ DEF_OP(AESKeyGenAssist) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterEncryptionHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterEncryptionHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(VAESIMC,     AESImc);
   REGISTER_OP(VAESENC,     AESEnc);
   REGISTER_OP(VAESENCLAST, AESEncLast);

External/FEXCore/Source/Interface/Core/JIT/x86_64/FlagOps.cpp

@@ -1,9 +1,15 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(GetHostFlag) {
   auto Op = IROp->C<IR::IROp_GetHostFlag>();
 
@@ -14,8 +20,8 @@ DEF_OP(GetHostFlag) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterFlagHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterFlagHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(GETHOSTFLAG, GetHostFlag);
 #undef REGISTER_OP
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.h

@@ -1 +0,0 @@
-

External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h

@@ -1,11 +1,17 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #pragma once
 
-#include "Interface/Core/LookupCache.h"
 #include "Interface/Core/BlockSamplingData.h"
+#include "Interface/Core/Dispatcher/Dispatcher.h"
 
-#include "Interface/Core/JIT/x86_64/JIT.h"
 #include "Common/MathUtils.h"
 
+#define XBYAK64
 #include <xbyak/xbyak.h>
 #include <xbyak/xbyak_util.h>
 
@@ -54,12 +60,12 @@ const std::array<std::pair<Xbyak::Reg, Xbyak::Reg>, 4> RA64Pair = {{ {rsi, r8},
 const std::array<Xbyak::Reg, 11> RAXMM = { xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10, xmm11};
 const std::array<Xbyak::Xmm, 11> RAXMM_x = {  xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10, xmm11};
 
-class JITCore final : public CPUBackend, public Xbyak::CodeGenerator {
+class X86JITCore final : public CPUBackend, public Xbyak::CodeGenerator {
 public:
-  explicit JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, CodeBuffer Buffer, bool CompileThread);
-  ~JITCore() override;
+  explicit X86JITCore(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, CodeBuffer Buffer, bool CompileThread);
+  ~X86JITCore() override;
   std::string GetName() override { return "JIT"; }
-  void *CompileCode(FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
+  void *CompileCode(uint64_t Entry, FEXCore::IR::IRListView const *IR, FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData) override;
 
   void *MapRegion(void* HostPtr, uint64_t, uint64_t) override { return HostPtr; }
 
@@ -69,10 +75,6 @@ public:
 
   static constexpr size_t INITIAL_CODE_SIZE = 1024 * 1024 * 16;
   static constexpr size_t MAX_CODE_SIZE = 1024 * 1024 * 256;
-
-  bool HandleSIGILL(int Signal, void *info, void *ucontext);
-  bool HandleSignalPause(int Signal, void *info, void *ucontext);
-  bool HandleGuestSignal(int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
   void CopyNecessaryDataForCompileThread(CPUBackend *Original) override;
 
 private:
@@ -80,6 +82,8 @@ private:
   FEXCore::Context::Context *CTX;
   FEXCore::Core::InternalThreadState *ThreadState;
   FEXCore::IR::IRListView const *IR;
+  std::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
+  uint64_t Entry;
 
   std::unordered_map<IR::OrderedNodeWrapper::NodeOffsetType, Label> JumpTargets;
   Xbyak::util::Cpu Features{};
@@ -107,28 +111,27 @@ private:
   constexpr static uint8_t RA_64 = 3;
   constexpr static uint8_t RA_XMM = 4;
 
-  IR::PhysicalRegister GetPhys(uint32_t Node);
+  IR::PhysicalRegister GetPhys(uint32_t Node) const;
 
-  bool IsFPR(uint32_t Node);
-  bool IsGPR(uint32_t Node);
+  bool IsFPR(uint32_t Node) const;
+  bool IsGPR(uint32_t Node) const;
 
   template<uint8_t RAType>
-  Xbyak::Reg GetSrc(uint32_t Node);
+  Xbyak::Reg GetSrc(uint32_t Node) const;
   template<uint8_t RAType>
-  std::pair<Xbyak::Reg, Xbyak::Reg> GetSrcPair(uint32_t Node);
+  std::pair<Xbyak::Reg, Xbyak::Reg> GetSrcPair(uint32_t Node) const;
 
   template<uint8_t RAType>
-  Xbyak::Reg GetDst(uint32_t Node);
+  Xbyak::Reg GetDst(uint32_t Node) const;
 
-  Xbyak::Xmm GetSrc(uint32_t Node);
-  Xbyak::Xmm GetDst(uint32_t Node);
+  Xbyak::Xmm GetSrc(uint32_t Node) const;
+  Xbyak::Xmm GetDst(uint32_t Node) const;
 
-  Xbyak::RegExp GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale);
+  Xbyak::RegExp GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) const;
 
-  bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr);
-  bool IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value);
+  bool IsInlineConstant(const IR::OrderedNodeWrapper& Node, uint64_t* Value = nullptr) const;
+  bool IsInlineEntrypointOffset(const IR::OrderedNodeWrapper& WNode, uint64_t* Value) const;
 
-  void CreateCustomDispatch(FEXCore::Core::InternalThreadState *Thread);
   IR::RegisterAllocationPass *RAPass;
   FEXCore::IR::RegisterAllocationData *RAData;
 
@@ -136,13 +139,11 @@ private:
   bool GetSamplingData {true};
 #endif
 
-  static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096 * 1;
-
   void EmplaceNewCodeBuffer(CodeBuffer Buffer) {
     CurrentCodeBuffer = &CodeBuffers.emplace_back(Buffer);
   }
 
-  static uint64_t ExitFunctionLink(JITCore* code, FEXCore::Core::InternalThreadState *Thread, uint64_t *record);
+  static uint64_t ExitFunctionLink(X86JITCore* code, FEXCore::Core::CpuStateFrame *Frame, uint64_t *record);
 
   // This is the initial code buffer that we will fall back to
   // In a program without signals and code clearing, we will typically
@@ -153,39 +154,26 @@ private:
   // For code safety we can't delete code buffers until outside of all signals
   std::vector<CodeBuffer> CodeBuffers{};
 
-  // This is the codebuffer that our dispatcher lives in
-  CodeBuffer DispatcherCodeBuffer{};
   // This is the current code buffer that we are tracking
   CodeBuffer *CurrentCodeBuffer{};
 
-  uint64_t AbsoluteLoopTopAddress{};
-  uint64_t ExitFunctionLinkerAddress{};
-  uint64_t ThreadStopHandlerAddress{};
-  uint64_t ThreadPauseHandlerAddress{};
-
-  uint64_t PauseReturnInstruction{};
-
-  uint32_t SignalHandlerRefCounter{};
-
   struct CompilerSharedData {
     uint64_t SignalHandlerReturnAddress{};
 
     uint32_t *SignalHandlerRefCounterPtr{};
+    FEXCore::CPU::Dispatcher *Dispatcher{};
   };
 
   CompilerSharedData ThreadSharedData;
 
-  void StoreThreadState(int Signal, void *ucontext);
-  void RestoreThreadState(void *ucontext);
-  std::stack<uint64_t> SignalFrames;
   uint32_t SpillSlots{};
-  using SetCC = void (JITCore::*)(const Operand& op);
-  using CMovCC = void (JITCore::*)(const Reg& reg, const Operand& op);
-  using JCC = void (JITCore::*)(const Label& label, LabelType type);
+  using SetCC = void (X86JITCore::*)(const Operand& op);
+  using CMovCC = void (X86JITCore::*)(const Reg& reg, const Operand& op);
+  using JCC = void (X86JITCore::*)(const Label& label, LabelType type);
 
   std::tuple<SetCC, CMovCC, JCC> GetCC(IR::CondClassType cond);
 
-  using OpHandler = void (JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
+  using OpHandler = void (X86JITCore::*)(FEXCore::IR::IROp_Header *IROp, uint32_t Node);
   std::array<OpHandler, FEXCore::IR::IROps::OP_LAST + 1> OpHandlers {};
   void RegisterALUHandlers();
   void RegisterAtomicHandlers();
@@ -210,7 +198,7 @@ private:
 
   ///< ALU Ops
   DEF_OP(TruncElementPair);
-  DEF_OP(Constant); 
+  DEF_OP(Constant);
   DEF_OP(EntrypointOffset);
   DEF_OP(InlineConstant);
   DEF_OP(InlineEntrypointOffset);
@@ -252,9 +240,7 @@ private:
   DEF_OP(Sbfe);
   DEF_OP(Select);
   DEF_OP(VExtractToGPR);
-  DEF_OP(Float_ToGPR_ZU);
   DEF_OP(Float_ToGPR_ZS);
-  DEF_OP(Float_ToGPR_U);
   DEF_OP(Float_ToGPR_S);
   DEF_OP(FCmp);
   DEF_OP(F80Cmp);
@@ -273,6 +259,7 @@ private:
   DEF_OP(AtomicFetchAnd);
   DEF_OP(AtomicFetchOr);
   DEF_OP(AtomicFetchXor);
+  DEF_OP(AtomicFetchNeg);
 
   ///< Branch ops
   DEF_OP(GuestCallDirect);
@@ -292,16 +279,14 @@ private:
   ///< Conversion ops
   DEF_OP(VInsGPR);
   DEF_OP(VCastFromGPR);
-  DEF_OP(Float_FromGPR_U);
   DEF_OP(Float_FromGPR_S);
   DEF_OP(Float_FToF);
   DEF_OP(Vector_UToF);
   DEF_OP(Vector_SToF);
-  DEF_OP(Vector_FToZU);
   DEF_OP(Vector_FToZS);
-  DEF_OP(Vector_FToU);
   DEF_OP(Vector_FToS);
   DEF_OP(Vector_FToF);
+  DEF_OP(Vector_FToI);
 
   ///< Flag ops
   DEF_OP(GetHostFlag);
@@ -319,6 +304,7 @@ private:
   DEF_OP(StoreMem);
   DEF_OP(VLoadMemElement);
   DEF_OP(VStoreMemElement);
+  DEF_OP(CacheLineClear);
 
   ///< Misc ops
   DEF_OP(EndBlock);
@@ -343,6 +329,7 @@ private:
   DEF_OP(SplatVector);
   DEF_OP(VMov);
   DEF_OP(VAnd);
+  DEF_OP(VBic);
   DEF_OP(VOr);
   DEF_OP(VXor);
   DEF_OP(VAdd);
@@ -353,8 +340,10 @@ private:
   DEF_OP(VSQSub);
   DEF_OP(VAddP);
   DEF_OP(VAddV);
+  DEF_OP(VUMinV);
   DEF_OP(VURAvg);
   DEF_OP(VAbs);
+  DEF_OP(VPopcount);
   DEF_OP(VFAdd);
   DEF_OP(VFAddP);
   DEF_OP(VFSub);
@@ -374,6 +363,8 @@ private:
   DEF_OP(VSMax);
   DEF_OP(VZip);
   DEF_OP(VZip2);
+  DEF_OP(VUnZip);
+  DEF_OP(VUnZip2);
   DEF_OP(VBSL);
   DEF_OP(VCMPEQ);
   DEF_OP(VCMPEQZ);
@@ -396,6 +387,7 @@ private:
   DEF_OP(VInsElement);
   DEF_OP(VInsScalarElement);
   DEF_OP(VExtractElement);
+  DEF_OP(VDupElement);
   DEF_OP(VExtr);
   DEF_OP(VSLI);
   DEF_OP(VSRI);
@@ -418,6 +410,7 @@ private:
   DEF_OP(VSMull);
   DEF_OP(VUMull2);
   DEF_OP(VSMull2);
+  DEF_OP(VUABDL);
   DEF_OP(VTBL1);
 
   ///< Encryption ops

External/FEXCore/Source/Interface/Core/JIT/x86_64/MemoryOps.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
@@ -5,7 +11,7 @@
 
 namespace FEXCore::CPU {
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(LoadContext) {
   auto Op = IROp->C<IR::IROp_LoadContext>();
@@ -30,10 +36,10 @@ DEF_OP(LoadContext) {
     }
     break;
     case 16: {
-      LogMan::Msg::A("Invalid GPR load of size 16");
+      LOGMAN_MSG_A_FMT("Invalid GPR load of size 16");
     }
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
     }
   }
   else {
@@ -63,7 +69,7 @@ DEF_OP(LoadContext) {
         movups(GetDst(Node), xword [STATE + Op->Offset]);
     }
     break;
-    default:  LogMan::Msg::A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
     }
   }
 }
@@ -92,9 +98,9 @@ DEF_OP(StoreContext) {
     }
     break;
     case 16:
-      LogMan::Msg::D("Invalid store size of 16");
+      LogMan::Msg::DFmt("Invalid store size of 16");
     break;
-    default:  LogMan::Msg::A("Unhandled StoreContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
     }
   }
   else {
@@ -123,7 +129,7 @@ DEF_OP(StoreContext) {
         movups(xword [STATE + Op->Offset], GetSrc(Op->Header.Args[0].ID()));
     }
     break;
-    default:  LogMan::Msg::A("Unhandled StoreContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
     }
   }
 }
@@ -154,17 +160,18 @@ DEF_OP(LoadContextIndexed) {
         mov(GetDst<RA_64>(Node),  qword [rax + index * Op->Stride]);
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     case 16:
-      LogMan::Msg::A("Invalid Class load of size 16");
+      LOGMAN_MSG_A_FMT("Invalid Class load of size 16");
       break;
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed stride: {}", Op->Stride);
+      break;
     }
-
   }
   else {
     switch (Op->Stride) {
@@ -189,7 +196,8 @@ DEF_OP(LoadContextIndexed) {
         vmovq(GetDst(Node),  qword [rax + index * Op->Stride]);
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
@@ -217,12 +225,14 @@ DEF_OP(LoadContextIndexed) {
           movups(GetDst(Node), xword [STATE + rax]);
         break;
       default:
-        LogMan::Msg::A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
 }
@@ -242,13 +252,14 @@ DEF_OP(StoreContextIndexed) {
     case 4:
     case 8: {
       if (!(size == 1 || size == 2 || size == 4 || size == 8)) {
-        LogMan::Msg::A("Unhandled StoreContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", Op->Size);
       }
       mov(AddressFrame(Op->Size * 8) [rax + index * Op->Stride], value);
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled StoreContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
   else {
@@ -273,7 +284,8 @@ DEF_OP(StoreContextIndexed) {
         vmovq(AddressFrame(Op->Size * 8) [rax + index * Op->Stride], value);
         break;
       default:
-        LogMan::Msg::A("Unhandled StoreContextIndexed size: %d", size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", size);
+        break;
       }
       break;
     }
@@ -301,12 +313,14 @@ DEF_OP(StoreContextIndexed) {
           movups(xword [STATE + rax], value);
         break;
       default:
-        LogMan::Msg::A("Unhandled StoreContextIndexed size: %d", size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", size);
+        break;
       }
       break;
     }
     default:
-      LogMan::Msg::A("Unhandled StoreContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
 }
@@ -334,7 +348,7 @@ DEF_OP(SpillRegister) {
         mov(qword [rsp + SlotOffset], GetSrc<RA_64>(Op->Header.Args[0].ID()));
         break;
       }
-      default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -350,10 +364,10 @@ DEF_OP(SpillRegister) {
         movaps(xword [rsp + SlotOffset], GetSrc(Op->Header.Args[0].ID()));
         break;
       }
-      default:  LogMan::Msg::A("Unhandled SpillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
     }
   } else {
-    LogMan::Msg::A("Unhandled SpillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A_FMT("Unhandled SpillRegister class: {}", Op->Class.Val);
   }
 
 
@@ -382,7 +396,7 @@ DEF_OP(FillRegister) {
         mov(GetDst<RA_64>(Node), qword [rsp + SlotOffset]);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled FillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled FillRegister size: {}", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -398,10 +412,10 @@ DEF_OP(FillRegister) {
         movaps(GetDst(Node), xword [rsp + SlotOffset]);
         break;
       }
-      default:  LogMan::Msg::A("Unhandled FillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled FillRegister size: {}", OpSize);
     }
   } else {
-    LogMan::Msg::A("Unhandled FillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A_FMT("Unhandled FillRegister class: {}", Op->Class.Val);
   }
 }
 
@@ -419,16 +433,16 @@ DEF_OP(StoreFlag) {
   mov(byte [STATE + (offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag)], al);
 }
 
-Xbyak::RegExp JITCore::GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) {
+Xbyak::RegExp X86JITCore::GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) const {
   if (Offset.IsInvalid()) {
     return Base;
   } else {
     if (OffsetScale != 1 && OffsetScale != 2 && OffsetScale != 4 && OffsetScale != 8) {
-      LogMan::Msg::A("Unhandled GenerateModRM OffsetScale: %d", OffsetScale);
+      LOGMAN_MSG_A_FMT("Unhandled GenerateModRM OffsetScale: {}", OffsetScale);
     }
 
     if (OffsetType != IR::MEM_OFFSET_SXTX) {
-      LogMan::Msg::A("Unhandled GenerateModRM OffsetType: %d", OffsetType.Val);
+      LOGMAN_MSG_A_FMT("Unhandled GenerateModRM OffsetType: {}", OffsetType.Val);
     }
 
     uint64_t Const;
@@ -469,7 +483,7 @@ DEF_OP(LoadMem) {
         mov(Dst, qword [MemPtr]);
       }
       break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMem size: {}", Op->Size);
     }
   }
   else
@@ -505,7 +519,7 @@ DEF_OP(LoadMem) {
          }
        }
        break;
-      default:  LogMan::Msg::A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMem size: {}", Op->Size);
     }
   }
 }
@@ -531,7 +545,7 @@ DEF_OP(StoreMem) {
     case 8:
       mov(qword [MemPtr], GetSrc<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", Op->Size);
     }
   }
   else {
@@ -554,22 +568,30 @@ DEF_OP(StoreMem) {
       else
         movups(xword [MemPtr], GetSrc(Op->Header.Args[1].ID()));
     break;
-    default:  LogMan::Msg::A("Unhandled StoreMem size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", Op->Size);
     }
   }
 }
 
 DEF_OP(VLoadMemElement) {
-  LogMan::Msg::A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VStoreMemElement) {
-  LogMan::Msg::A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
+}
+
+DEF_OP(CacheLineClear) {
+  auto Op = IROp->C<IR::IROp_CacheLineClear>();
+
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
+
+  clflush(ptr [MemReg]);
 }
 
 #undef DEF_OP
-void JITCore::RegisterMemoryHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterMemoryHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(LOADCONTEXT,         LoadContext);
   REGISTER_OP(STORECONTEXT,        StoreContext);
   REGISTER_OP(LOADREGISTER,        Unhandled); // SRA specific, not supported on this backend
@@ -586,6 +608,7 @@ void JITCore::RegisterMemoryHandlers() {
   REGISTER_OP(STOREMEMTSO,         StoreMem);
   REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
   REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
+  REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/MiscOps.cpp

@@ -1,12 +1,22 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
 static void PrintValue(uint64_t Value) {
-  LogMan::Msg::D("Value: 0x%lx", Value);
+  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
 }
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
+  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
+}
+
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 
 DEF_OP(Fence) {
   auto Op = IROp->C<IR::IROp_Fence>();
@@ -20,7 +30,7 @@ DEF_OP(Fence) {
     case IR::Fence_Store.Val:
       sfence();
       break;
-    default: LogMan::Msg::A("Unknown Fence: %d", Op->Fence); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
   }
 }
 
@@ -31,13 +41,22 @@ DEF_OP(Break) {
     case 5: // Guest ud2
       ud2();
     break;
+    case 1: // Int <imm8>
+      ud2();
+    break;
+    case 2: // overflow
+      ud2();
+      break;
+    case 3: // int 1
+      ud2();
+      break;
     case 4: { // HLT
       // Time to quit
       // Set our stack to the starting stack location
-      mov(rsp, qword [STATE + offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)]);
+      mov(rsp, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)]);
 
       // Now we need to jump to the thread stop handler
-      mov(TMP1, ThreadStopHandlerAddress);
+      mov(TMP1, ThreadSharedData.Dispatcher->ThreadStopHandlerAddress);
       jmp(TMP1);
       break;
     }
@@ -50,21 +69,21 @@ DEF_OP(Break) {
         }
 
         // This jump target needs to be a constant offset here
-        mov(TMP1, ThreadPauseHandlerAddress);
+        mov(TMP1, ThreadSharedData.Dispatcher->ThreadPauseHandlerAddress);
         jmp(TMP1);
       }
       else {
         // If we don't have a gdb server attached then....crash?
         // Treat this case like HLT
-        mov(rsp, qword [STATE + offsetof(FEXCore::Core::ThreadState, ReturningStackLocation)]);
+        mov(rsp, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, ReturningStackLocation)]);
 
         // Now we need to jump to the thread stop handler
-        mov(TMP1, ThreadStopHandlerAddress);
+        mov(TMP1, ThreadSharedData.Dispatcher->ThreadStopHandlerAddress);
         jmp(TMP1);
       }
     break;
     }
-    default: LogMan::Msg::A("Unknown Break reason: %d", Op->Reason);
+    default: LOGMAN_MSG_A_FMT("Unknown Break reason: {}", Op->Reason);
   }
 }
 
@@ -104,29 +123,27 @@ DEF_OP(SetRoundingMode) {
 DEF_OP(Print) {
   auto Op = IROp->C<IR::IROp_Print>();
 
-  for (auto &Reg : RA64)
-    push(Reg);
+  PushRegs();
+  if (IsGPR(Op->Header.Args[0].ID())) {
+    mov (rdi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
 
-  auto NumPush = RA64.size();
-  if (NumPush & 1)
-    sub(rsp, 8); // Align
+    mov(rax, reinterpret_cast<uintptr_t>(PrintValue));
+  }
+  else {
+    pextrq(rdi, GetSrc(Op->Header.Args[0].ID()), 0);
+    pextrq(rsi, GetSrc(Op->Header.Args[0].ID()), 1);
 
-  mov (rdi, GetSrc<RA_64>(Op->Header.Args[0].ID()));
-
-  mov(rax, reinterpret_cast<uintptr_t>(PrintValue));
+    mov(rax, reinterpret_cast<uintptr_t>(PrintVectorValue));
+  }
 
   call(rax);
 
-  if (NumPush & 1)
-    add(rsp, 8); // Align
-
-  for (uint32_t i = RA64.size(); i > 0; --i)
-    pop(RA64[i - 1]);
+  PopRegs();
 }
 
 #undef DEF_OP
-void JITCore::RegisterMiscHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterMiscHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(DUMMY,      NoOp);
   REGISTER_OP(IRHEADER,   NoOp);
   REGISTER_OP(CODEBLOCK,  NoOp);

External/FEXCore/Source/Interface/Core/JIT/x86_64/MoveOps.cpp

@@ -1,9 +1,15 @@
+/*
+$info$
+tags: backend|x86-64
+$end_info$
+*/
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 namespace FEXCore::CPU {
 
-#define DEF_OP(x) void JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
+#define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(ExtractElementPair) {
   auto Op = IROp->C<IR::IROp_ExtractElementPair>();
   switch (Op->Header.Size) {
@@ -19,7 +25,7 @@ DEF_OP(ExtractElementPair) {
       mov (GetDst<RA_64>(Node), Regs[Op->Element]);
       break;
     }
-    default: LogMan::Msg::A("Unknown Size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
   }
 }
 
@@ -45,7 +51,7 @@ DEF_OP(CreateElementPair) {
       RegTmp = rax;
       break;
     }
-    default: LogMan::Msg::A("Unknown Size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
   }
 
   if (Dst.first != RegSecond) {
@@ -67,8 +73,8 @@ DEF_OP(Mov) {
 }
 
 #undef DEF_OP
-void JITCore::RegisterMoveHandlers() {
-#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &JITCore::Op_##x
+void X86JITCore::RegisterMoveHandlers() {
+#define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
   REGISTER_OP(EXTRACTELEMENTPAIR, ExtractElementPair);
   REGISTER_OP(CREATEELEMENTPAIR,  CreateElementPair);
   REGISTER_OP(MOV,                Mov);

External/FEXCore/Source/Interface/Core/LookupCache.cpp

@@ -1,6 +1,15 @@
+/*
+$info$
+tags: glue|block-database
+desc: Stores information about blocks, and provides C++ implementations to lookup the blocks
+$end_info$
+*/
+
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Core.h"
 #include "Interface/Core/LookupCache.h"
+#include <FEXCore/Utils/Allocator.h>
+
 #include <sys/mman.h>
 
 namespace FEXCore {
@@ -19,27 +28,27 @@ LookupCache::LookupCache(FEXCore::Context::Context *CTX)
   // Allocate a region of memory that we can use to back our block pointers
   // We need one pointer per page of virtual memory
   // At 64GB of virtual memory this will allocate 128MB of virtual memory space
-  PagePointer = reinterpret_cast<uintptr_t>(mmap(nullptr, ctx->Config.VirtualMemSize / 4096 * 8, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+  PagePointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, ctx->Config.VirtualMemSize / 4096 * 8, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
 
   // Allocate our memory backing our pages
   // We need 32KB per guest page (One pointer per byte)
   // XXX: We can drop down to 16KB if we store 4byte offsets from the code base
   // We currently limit to 128MB of real memory for caching for the total cache size.
   // Can end up being inefficient if we compile a small number of blocks per page
-  PageMemory = reinterpret_cast<uintptr_t>(mmap(nullptr, CODE_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
-  LogMan::Throw::A(PageMemory != -1ULL, "Failed to allocate page memory");
+  PageMemory = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, CODE_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+  LOGMAN_THROW_A(PageMemory != -1ULL, "Failed to allocate page memory");
 
   // L1 Cache
-  L1Pointer = reinterpret_cast<uintptr_t>(mmap(nullptr, L1_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
-  LogMan::Throw::A(L1Pointer != -1ULL, "Failed to allocate L1Pointer");
+  L1Pointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, L1_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+  LOGMAN_THROW_A(L1Pointer != -1ULL, "Failed to allocate L1Pointer");
 
   VirtualMemSize = ctx->Config.VirtualMemSize;
 }
 
 LookupCache::~LookupCache() {
-  munmap(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8);
-  munmap(reinterpret_cast<void*>(PageMemory), CODE_SIZE);
-  munmap(reinterpret_cast<void*>(L1Pointer), L1_SIZE);
+  FEXCore::Allocator::munmap(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8);
+  FEXCore::Allocator::munmap(reinterpret_cast<void*>(PageMemory), CODE_SIZE);
+  FEXCore::Allocator::munmap(reinterpret_cast<void*>(L1Pointer), L1_SIZE);
 }
 
 void LookupCache::HintUsedRange(uint64_t Address, uint64_t Size) {

External/FEXCore/Source/Interface/Core/LookupCache.h

@@ -38,14 +38,21 @@ public:
   std::map<uint64_t, std::vector<uint64_t>> CodePages;
 
   void AddBlockMapping(uint64_t Address, void *HostCode, uint64_t Start, uint64_t Length) { 
-    auto InsertPoint = BlockList.emplace(Address, (uintptr_t)HostCode);
-    LogMan::Throw::A(InsertPoint.second == true, "Dupplicate block mapping added");
+#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
+    auto InsertPoint =
+#endif
+    BlockList.emplace(Address, (uintptr_t)HostCode);
+    LOGMAN_THROW_A(InsertPoint.second == true, "Dupplicate block mapping added");
 
     for (auto CurrentPage = Start >> 12, EndPage = (Start + Length) >> 12; CurrentPage <= EndPage; CurrentPage++) {
       CodePages[CurrentPage].push_back(Address);
     }
 
-    // no need to update L1 or L2, they will get updated on first lookup
+    // There is no need to update L1 or L2, they will get updated on first lookup
+    // However, adding to L1 here increases performance
+    auto &L1Entry = reinterpret_cast<LookupCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
+    L1Entry.GuestCode = Address;
+    L1Entry.HostCode = (uintptr_t)HostCode;
   }
 
   void Erase(uint64_t Address) {
@@ -94,8 +101,8 @@ public:
 
   void HintUsedRange(uint64_t Address, uint64_t Size);
 
-  uintptr_t GetL1Pointer() { return L1Pointer; }
-  uintptr_t GetPagePointer() { return PagePointer; }
+  uintptr_t GetL1Pointer() const { return L1Pointer; }
+  uintptr_t GetPagePointer() const { return PagePointer; }
   uintptr_t GetVirtualMemorySize() const { return VirtualMemSize; }
 
   constexpr static size_t L1_ENTRIES = 1 * 1024 * 1024; // Must be a power of 2
@@ -105,9 +112,8 @@ private:
   void CacheBlockMapping(uint64_t Address, uintptr_t HostCode) { 
     // Do L1
     auto &L1Entry = reinterpret_cast<LookupCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
-    if (L1Entry.GuestCode == Address) {
-      L1Entry.GuestCode = L1Entry.HostCode = 0;
-    }
+    L1Entry.GuestCode = Address;
+    L1Entry.HostCode = HostCode;
 
     // Do ful map
     auto FullAddress = Address;

External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -49,7 +49,7 @@ public:
 
   OrderedNode* GetNewJumpBlock(uint64_t RIP) {
     auto it = JumpTargets.find(RIP);
-    LogMan::Throw::A(it != JumpTargets.end(), "Couldn't find block generated for 0x%lx", RIP);
+    LOGMAN_THROW_A(it != JumpTargets.end(), "Couldn't find block generated for 0x%lx", RIP);
     return it->second.BlockEntry;
   }
 
@@ -59,7 +59,7 @@ public:
 
     it->second.HaveEmitted = true;
 
-    if (CurrentCodeBlock->Wrapped(ListData.Begin()).ID() == it->second.BlockEntry->Wrapped(ListData.Begin()).ID()) return;
+    if (CurrentCodeBlock->Wrapped(DualListData.ListBegin()).ID() == it->second.BlockEntry->Wrapped(DualListData.ListBegin()).ID()) return;
 
     // We have hit a RIP that is a jump target
     // Thus we need to end up in a new block
@@ -81,14 +81,14 @@ public:
     //  rdi, 0x8
     //  cmp qword [rdi-8], 0
     //  jne .label
-    if (!BlockSetRIP) {
+    if (LastOp && !BlockSetRIP) {
       auto it = JumpTargets.find(NextRIP);
-      if (it == JumpTargets.end() && LastOp) {
+      if (it == JumpTargets.end()) {
 
-        uint8_t GPRSize = CTX->Config.Is64BitMode ? 8 : 4;
+        const uint8_t GPRSize = CTX->GetGPRSize();
         // If we don't have a jump target to a new block then we have to leave
         // Set the RIP to the next instruction and leave
-        auto RelocatedNextRIP = _EntrypointOffset(NextRIP - Current_Header->Entry, GPRSize);
+        auto RelocatedNextRIP = _EntrypointOffset(NextRIP - Entry, GPRSize);
         _ExitFunction(RelocatedNextRIP);
       }
       else if (it != JumpTargets.end()) {
@@ -104,7 +104,8 @@ public:
   OpDispatchBuilder(FEXCore::Context::Context *ctx);
 
   void ResetWorkingList();
-  bool HadDecodeFailure() { return DecodeFailure; }
+  void ResetDecodeFailure() { DecodeFailure = false; }
+  bool HadDecodeFailure() const { return DecodeFailure; }
 
   void BeginFunction(uint64_t RIP, std::vector<FEXCore::Frontend::Decoder::DecodedBlocks> const *Blocks);
   void Finalize();
@@ -259,12 +260,6 @@ public:
   template<size_t ElementSize>
   void PSUBQOp(OpcodeArgs);
   template<size_t ElementSize>
-  void PMINUOp(OpcodeArgs);
-  template<size_t ElementSize>
-  void PMAXUOp(OpcodeArgs);
-  void PMINSWOp(OpcodeArgs);
-  void PMAXSWOp(OpcodeArgs);
-  template<size_t ElementSize>
   void MOVMSKOp(OpcodeArgs);
   void MOVMSKOpOne(OpcodeArgs);
   template<size_t ElementSize>
@@ -274,20 +269,16 @@ public:
   void PSHUFBOp(OpcodeArgs);
   template<size_t ElementSize, bool HalfSize, bool Low>
   void PSHUFDOp(OpcodeArgs);
-  template<size_t ElementSize>
-  void PCMPEQOp(OpcodeArgs);
-  template<size_t ElementSize>
-  void PCMPGTOp(OpcodeArgs);
   void MOVDOp(OpcodeArgs);
-  template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
+  template<size_t ElementSize>
   void PSRLDOp(OpcodeArgs);
   template<size_t ElementSize>
   void PSRLI(OpcodeArgs);
   template<size_t ElementSize>
   void PSLLI(OpcodeArgs);
-  template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
+  template<size_t ElementSize>
   void PSLL(OpcodeArgs);
-  template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
+  template<size_t ElementSize>
   void PSRAOp(OpcodeArgs);
   void PSRLDQ(OpcodeArgs);
   void PSLLDQ(OpcodeArgs);
@@ -296,21 +287,21 @@ public:
   template<size_t ElementSize>
   void PAVGOp(OpcodeArgs);
   void MOVDDUPOp(OpcodeArgs);
-  template<size_t DstElementSize, bool Signed>
+  template<size_t DstElementSize>
   void CVTGPR_To_FPR(OpcodeArgs);
-  template<size_t SrcElementSize, bool Signed, bool HostRoundingMode>
+  template<size_t SrcElementSize, bool HostRoundingMode>
   void CVTFPR_To_GPR(OpcodeArgs);
-  template<size_t SrcElementSize, bool Signed, bool Widen>
+  template<size_t SrcElementSize, bool Widen>
   void Vector_CVT_Int_To_Float(OpcodeArgs);
   template<size_t DstElementSize, size_t SrcElementSize>
   void Scalar_CVT_Float_To_Float(OpcodeArgs);
   template<size_t DstElementSize, size_t SrcElementSize>
   void Vector_CVT_Float_To_Float(OpcodeArgs);
-  template<size_t SrcElementSize, bool Signed, bool Narrow, bool HostRoundingMode>
+  template<size_t SrcElementSize, bool Narrow, bool HostRoundingMode>
   void Vector_CVT_Float_To_Int(OpcodeArgs);
-  template<size_t SrcElementSize, bool Signed, bool Widen>
+  template<size_t SrcElementSize, bool Widen>
   void MMX_To_XMM_Vector_CVT_Int_To_Float(OpcodeArgs);
-  template<size_t SrcElementSize, bool Signed, bool Narrow, bool HostRoundingMode>
+  template<size_t SrcElementSize, bool HostRoundingMode>
   void XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs);
   void MASKMOVOp(OpcodeArgs);
   void MOVBetweenGPR_FPR(OpcodeArgs);
@@ -324,17 +315,13 @@ public:
   void ANDNOp(OpcodeArgs);
   template<size_t ElementSize>
   void PINSROp(OpcodeArgs);
+  void InsertPSOp(OpcodeArgs);
   template<size_t ElementSize>
   void PExtrOp(OpcodeArgs);
-  template<size_t ElementSize, bool Signed>
-  void PMULOp(OpcodeArgs);
 
   template<size_t ElementSize>
   void PSIGN(OpcodeArgs);
 
-  template<size_t ElementSize>
-  void PABS(OpcodeArgs);
-
   // X87 Ops
   template<size_t width>
   void FLD(OpcodeArgs);
@@ -393,6 +380,8 @@ public:
   void X87FRSTOR(OpcodeArgs);
   void X87FXAM(OpcodeArgs);
   void X87FCMOV(OpcodeArgs);
+  void X87EMMS(OpcodeArgs);
+  void X87FFREE(OpcodeArgs);
 
   void FXCH(OpcodeArgs);
 
@@ -458,6 +447,8 @@ public:
   template<uint8_t FenceType>
   void FenceOp(OpcodeArgs);
 
+  void StoreFenceOrCLFlush(OpcodeArgs);
+
   void PSADBW(OpcodeArgs);
 
   void AESImcOp(OpcodeArgs);
@@ -467,6 +458,23 @@ public:
   void AESDecLastOp(OpcodeArgs);
   void AESKeyGenAssist(OpcodeArgs);
 
+  template<size_t ElementSize, size_t DstElementSize, bool Signed>
+  void ExtendVectorElements(OpcodeArgs);
+  template<size_t ElementSize, bool Scalar>
+  void VectorRound(OpcodeArgs);
+
+  template<size_t ElementSize>
+  void VectorBlend(OpcodeArgs);
+
+  template<size_t ElementSize>
+  void VectorVariableBlend(OpcodeArgs);
+  void PTestOp(OpcodeArgs);
+  void PHMINPOSUWOp(OpcodeArgs);
+  template<size_t ElementSize>
+  void DPPOp(OpcodeArgs);
+
+  void MPSADBWOp(OpcodeArgs);
+
   void UnimplementedOp(OpcodeArgs);
 
 #undef OpcodeArgs
@@ -475,8 +483,8 @@ public:
   OrderedNode *GetPackedRFLAG(bool Lower8);
 
   void SetMultiblock(bool _Multiblock) { Multiblock = _Multiblock; }
-  bool GetMultiblock() { return Multiblock; }
 
+  bool HandledLock = false;
 private:
   bool DecodeFailure{false};
   FEXCore::IR::IROp_IRHeader *Current_Header{};
@@ -491,13 +499,23 @@ private:
   void StoreResult(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp Op, FEXCore::X86Tables::DecodedOperand const& Operand, OrderedNode *const Src, int8_t Align);
   void StoreResult(FEXCore::IR::RegisterClassType Class, FEXCore::X86Tables::DecodedOp Op, OrderedNode *const Src, int8_t Align);
 
-  uint8_t GetDstSize(FEXCore::X86Tables::DecodedOp Op);
-  uint8_t GetSrcSize(FEXCore::X86Tables::DecodedOp Op);
+  uint8_t GetDstSize(FEXCore::X86Tables::DecodedOp Op) const;
+  uint8_t GetSrcSize(FEXCore::X86Tables::DecodedOp Op) const;
 
   template<unsigned BitOffset>
-  void SetRFLAG(OrderedNode *Value);
-  void SetRFLAG(OrderedNode *Value, unsigned BitOffset);
-  OrderedNode *GetRFLAG(unsigned BitOffset);
+  void SetRFLAG(OrderedNode *Value) {
+    flagsOp = FLAGS_OP_NONE;
+    _StoreFlag(_Bfe(1, 0, Value), BitOffset);
+  }
+
+  void SetRFLAG(OrderedNode *Value, unsigned BitOffset) {
+    flagsOp = FLAGS_OP_NONE;
+    _StoreFlag(_Bfe(1, 0, Value), BitOffset);
+  }
+
+  OrderedNode *GetRFLAG(unsigned BitOffset) {
+    return _LoadFlag(BitOffset);
+  }
 
   OrderedNode *SelectCC(uint8_t OP, OrderedNode *TrueValue, OrderedNode *FalseValue);
 
@@ -520,14 +538,22 @@ private:
   void GenerateFlags_RotateLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
 
   OrderedNode * GetX87Top();
+  enum X87Tag {
+    TAG_VALID   = 0b00,
+    TAG_ZERO    = 0b01,
+    TAG_SPECIAL = 0b10,
+    TAG_EMPTY   = 0b11
+  };
+  void SetX87TopTag(OrderedNode *Value, uint32_t Tag);
+  OrderedNode *GetX87FTW(OrderedNode *Value);
   void SetX87Top(OrderedNode *Value);
 
-  bool DestIsLockedMem(FEXCore::X86Tables::DecodedOp Op) {
-    return Op->Dest.TypeNone.Type !=FEXCore::X86Tables::DecodedOperand::TYPE_GPR && (Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_LOCK);
+  bool DestIsLockedMem(FEXCore::X86Tables::DecodedOp Op) const {
+    return DestIsMem(Op) && (Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_LOCK) != 0;
   }
 
-  bool DestIsMem(FEXCore::X86Tables::DecodedOp Op) {
-    return Op->Dest.TypeNone.Type !=FEXCore::X86Tables::DecodedOperand::TYPE_GPR;
+  bool DestIsMem(FEXCore::X86Tables::DecodedOp Op) const {
+    return !Op->Dest.IsGPR();
   }
 
   void CreateJumpBlocks(std::vector<FEXCore::Frontend::Decoder::DecodedBlocks> const *Blocks);

External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp

@@ -0,0 +1,58 @@
+/*
+$info$
+tags: frontend|x86-to-ir, opcodes|dispatcher-implementations
+desc: Handles x86/64 Crypto instructions to IR
+$end_info$
+*/
+
+#include "Interface/Core/OpcodeDispatcher.h"
+
+#include <FEXCore/Core/X86Enums.h>
+
+namespace FEXCore::IR {
+#define OpcodeArgs [[maybe_unused]] FEXCore::X86Tables::DecodedOp Op
+
+void OpDispatchBuilder::AESImcOp(OpcodeArgs) {
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  auto Res = _VAESImc(Src);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+void OpDispatchBuilder::AESEncOp(OpcodeArgs) {
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  auto Res = _VAESEnc(Dest, Src);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+void OpDispatchBuilder::AESEncLastOp(OpcodeArgs) {
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  auto Res = _VAESEncLast(Dest, Src);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+void OpDispatchBuilder::AESDecOp(OpcodeArgs) {
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  auto Res = _VAESDec(Dest, Src);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+void OpDispatchBuilder::AESDecLastOp(OpcodeArgs) {
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  auto Res = _VAESDecLast(Dest, Src);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+void OpDispatchBuilder::AESKeyGenAssist(OpcodeArgs) {
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  uint64_t RCON = Op->Src[1].Data.Literal.Value;
+
+  auto Res = _VAESKeyGenAssist(Src, RCON);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+}

External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp

@@ -0,0 +1,810 @@
+/*
+$info$
+tags: frontend|x86-to-ir, opcodes|dispatcher-implementations
+desc: Handles x86/64 flag generation
+$end_info$
+*/
+
+#include "Interface/Core/OpcodeDispatcher.h"
+
+#include <FEXCore/Core/X86Enums.h>
+
+namespace FEXCore::IR {
+constexpr std::array<uint32_t, 17> FlagOffsets = {
+  FEXCore::X86State::RFLAG_CF_LOC,
+  FEXCore::X86State::RFLAG_PF_LOC,
+  FEXCore::X86State::RFLAG_AF_LOC,
+  FEXCore::X86State::RFLAG_ZF_LOC,
+  FEXCore::X86State::RFLAG_SF_LOC,
+  FEXCore::X86State::RFLAG_TF_LOC,
+  FEXCore::X86State::RFLAG_IF_LOC,
+  FEXCore::X86State::RFLAG_DF_LOC,
+  FEXCore::X86State::RFLAG_OF_LOC,
+  FEXCore::X86State::RFLAG_IOPL_LOC,
+  FEXCore::X86State::RFLAG_NT_LOC,
+  FEXCore::X86State::RFLAG_RF_LOC,
+  FEXCore::X86State::RFLAG_VM_LOC,
+  FEXCore::X86State::RFLAG_AC_LOC,
+  FEXCore::X86State::RFLAG_VIF_LOC,
+  FEXCore::X86State::RFLAG_VIP_LOC,
+  FEXCore::X86State::RFLAG_ID_LOC,
+};
+
+void OpDispatchBuilder::SetPackedRFLAG(bool Lower8, OrderedNode *Src) {
+  uint8_t NumFlags = FlagOffsets.size();
+  if (Lower8) {
+    NumFlags = 5;
+  }
+  auto OneConst = _Constant(1);
+  for (int i = 0; i < NumFlags; ++i) {
+    auto Tmp = _And(_Lshr(Src, _Constant(FlagOffsets[i])), OneConst);
+    SetRFLAG(Tmp, FlagOffsets[i]);
+  }
+}
+
+OrderedNode *OpDispatchBuilder::GetPackedRFLAG(bool Lower8) {
+  OrderedNode *Original = _Constant(2);
+  uint8_t NumFlags = FlagOffsets.size();
+  if (Lower8) {
+    NumFlags = 5;
+  }
+
+  for (int i = 0; i < NumFlags; ++i) {
+    OrderedNode *Flag = _LoadFlag(FlagOffsets[i]);
+    Flag = _Bfe(4, 32, 0, Flag);
+    Flag = _Lshl(Flag, _Constant(FlagOffsets[i]));
+    Original = _Or(Original, Flag);
+  }
+  return Original;
+}
+
+void OpDispatchBuilder::GenerateFlags_ADC(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
+  auto Size = GetSrcSize(Op) * 8;
+  // AF
+  {
+    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
+    AFRes = _Bfe(1, 4, AFRes);
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(AFRes);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto PopCountOp = _Popcount(_And(Res, _Constant(0xFF)));
+
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // CF
+  // Unsigned
+  {
+    auto SelectOpLT = _Select(FEXCore::IR::COND_ULT, Res, Src2, _Constant(1), _Constant(0));
+    auto SelectOpLE = _Select(FEXCore::IR::COND_ULE, Res, Src2, _Constant(1), _Constant(0));
+    auto SelectCF   = _Select(FEXCore::IR::COND_EQ, CF, _Constant(1), SelectOpLE, SelectOpLT);
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectCF);
+  }
+
+  // OF
+  // Signed
+  {
+    auto NegOne = _Constant(~0ULL);
+    auto XorOp1 = _Xor(_Xor(Src1, Src2), NegOne);
+    auto XorOp2 = _Xor(Res, Src1);
+    OrderedNode *AndOp1 = _And(XorOp1, XorOp2);
+
+    switch (Size) {
+    case 8:
+      AndOp1 = _Bfe(1, 7, AndOp1);
+    break;
+    case 16:
+      AndOp1 = _Bfe(1, 15, AndOp1);
+    break;
+    case 32:
+      AndOp1 = _Bfe(1, 31, AndOp1);
+    break;
+    case 64:
+      AndOp1 = _Bfe(1, 63, AndOp1);
+    break;
+    default: LOGMAN_MSG_A("Unknown BFESize: %d", Size); break;
+    }
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(AndOp1);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_SBB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
+  // AF
+  {
+    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
+    AFRes = _Bfe(1, 4, AFRes);
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(AFRes);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto PopCountOp = _Popcount(_And(Res, _Constant(0xFF)));
+
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // CF
+  // Unsigned
+  {
+    auto SelectOpLT = _Select(FEXCore::IR::COND_UGT, Res, Src1, _Constant(1), _Constant(0));
+    auto SelectOpLE = _Select(FEXCore::IR::COND_UGE, Res, Src1, _Constant(1), _Constant(0));
+    auto SelectCF   = _Select(FEXCore::IR::COND_EQ, CF, _Constant(1), SelectOpLE, SelectOpLT);
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectCF);
+  }
+
+  // OF
+  // Signed
+  {
+    auto XorOp1 = _Xor(Src1, Src2);
+    auto XorOp2 = _Xor(Res, Src1);
+    OrderedNode *AndOp1 = _And(XorOp1, XorOp2);
+
+    switch (GetSrcSize(Op)) {
+    case 1:
+      AndOp1 = _Bfe(1, 7, AndOp1);
+    break;
+    case 2:
+      AndOp1 = _Bfe(1, 15, AndOp1);
+    break;
+    case 4:
+      AndOp1 = _Bfe(1, 31, AndOp1);
+    break;
+    case 8:
+      AndOp1 = _Bfe(1, 63, AndOp1);
+    break;
+    default: LOGMAN_MSG_A("Unknown BFESize: %d", GetSrcSize(Op)); break;
+    }
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(AndOp1);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_SUB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
+  // AF
+  {
+    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
+    AFRes = _Bfe(1, 4, AFRes);
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(AFRes);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // ZF
+  {
+    auto ZeroConst = _Constant(0);
+    auto OneConst = _Constant(1);
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, ZeroConst, OneConst, ZeroConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // CF
+  if (UpdateCF) {
+    auto ZeroConst = _Constant(0);
+    auto OneConst = _Constant(1);
+
+    auto SelectOp = _Select(FEXCore::IR::COND_ULT,
+        Src1, Src2, OneConst, ZeroConst);
+
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectOp);
+  }
+  // OF
+  {
+    auto XorOp1 = _Xor(Src1, Src2);
+    auto XorOp2 = _Xor(Res, Src1);
+    OrderedNode *FinalAnd = _And(XorOp1, XorOp2);
+
+    FinalAnd = _Bfe(1, GetSrcSize(Op) * 8 - 1, FinalAnd);
+
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(FinalAnd);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_ADD(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
+  // AF
+  {
+    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
+    AFRes = _Bfe(1, 4, AFRes);
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(AFRes);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+  // CF
+  if (UpdateCF) {
+    auto SelectOp = _Select(FEXCore::IR::COND_ULT, Res, Src2, _Constant(1), _Constant(0));
+
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectOp);
+  }
+
+  // OF
+  {
+    auto NegOne = _Constant(~0ULL);
+    auto XorOp1 = _Xor(_Xor(Src1, Src2), NegOne);
+    auto XorOp2 = _Xor(Res, Src1);
+
+    OrderedNode *AndOp1 = _And(XorOp1, XorOp2);
+
+    switch (GetSrcSize(Op)) {
+    case 1:
+      AndOp1 = _Bfe(1, 7, AndOp1);
+    break;
+    case 2:
+      AndOp1 = _Bfe(1, 15, AndOp1);
+    break;
+    case 4:
+      AndOp1 = _Bfe(1, 31, AndOp1);
+    break;
+    case 8:
+      AndOp1 = _Bfe(1, 63, AndOp1);
+    break;
+    default: LOGMAN_MSG_A("Unknown BFESize: %d", GetSrcSize(Op)); break;
+    }
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(AndOp1);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_MUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *High) {
+  // PF/AF/ZF/SF
+  // Undefined
+  {
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(_Constant(0));
+  }
+
+  // CF/OF
+  {
+    // CF and OF are set if the result of the operation can't be fit in to the destination register
+    // If the value can fit then the top bits will be zero
+
+    auto SignBit = _Sbfe(1, GetSrcSize(Op) * 8 - 1, Res);
+
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ, High, SignBit, _Constant(0), _Constant(1));
+
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectOp);
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(SelectOp);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_UMUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *High) {
+  // AF/SF/PF/ZF
+  // Undefined
+  {
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(_Constant(0));
+  }
+
+  // CF/OF
+  {
+    // CF and OF are set if the result of the operation can't be fit in to the destination register
+    // The result register will be all zero if it can't fit due to how multiplication behaves
+
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ, High, _Constant(0), _Constant(0), _Constant(1));
+
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectOp);
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(SelectOp);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_Logical(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // CF/OF
+  {
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Constant(0));
+  }
+}
+
+#define COND_FLAG_SET(cond, flag, newflag) \
+auto oldflag = GetRFLAG(FEXCore::X86State::flag);\
+auto newval = _Select(FEXCore::IR::COND_EQ, cond, _Constant(0), oldflag, newflag);\
+SetRFLAG<FEXCore::X86State::flag>(newval);
+
+void OpDispatchBuilder::GenerateFlags_ShiftLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    auto Size = _Constant(GetSrcSize(Op) * 8);
+    auto ShiftAmt = _Sub(Size, Src2);
+    auto LastBit = _And(_Lshr(Src1, ShiftAmt), _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_CF_LOC, LastBit);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_PF_LOC, XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    COND_FLAG_SET(Src2, RFLAG_AF_LOC, _Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    COND_FLAG_SET(Src2, RFLAG_ZF_LOC, SelectOp);
+  }
+
+  // SF
+  {
+    auto val = _Bfe(1, GetSrcSize(Op) * 8 - 1, Res);
+    COND_FLAG_SET(Src2, RFLAG_SF_LOC, val);
+  }
+
+  // OF
+  {
+    // In the case of left shift. OF is only set from the result of <Top Source Bit> XOR <Top Result Bit>
+    // When Shift > 1 then OF is undefined
+    auto val = _Bfe(1, GetSrcSize(Op) * 8 - 1, _Xor(Src1, Res));
+    COND_FLAG_SET(Src2, RFLAG_OF_LOC, val);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_ShiftRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    auto ShiftAmt = _Sub(Src2, _Constant(1));
+    auto LastBit = _And(_Lshr(Src1, ShiftAmt), _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_CF_LOC, LastBit);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_PF_LOC, XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    COND_FLAG_SET(Src2, RFLAG_AF_LOC, _Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    COND_FLAG_SET(Src2, RFLAG_ZF_LOC, SelectOp);
+  }
+
+  // SF
+  {
+    auto val =_Bfe(1, GetSrcSize(Op) * 8 - 1, Res);
+    COND_FLAG_SET(Src2, RFLAG_SF_LOC, val);
+  }
+
+  // OF
+  {
+    // Only defined when Shift is 1 else undefined
+    // OF flag is set if a sign change occurred
+    auto val = _Bfe(1, GetSrcSize(Op) * 8 - 1, _Xor(Src1, Res));
+    COND_FLAG_SET(Src2, RFLAG_OF_LOC, val);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_SignShiftRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    auto ShiftAmt = _Sub(Src2, _Constant(1));
+    auto LastBit = _And(_Lshr(Src1, ShiftAmt), _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_CF_LOC, LastBit);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_PF_LOC, XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    COND_FLAG_SET(Src2, RFLAG_AF_LOC, _Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    COND_FLAG_SET(Src2, RFLAG_ZF_LOC, SelectOp);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    COND_FLAG_SET(Src2, RFLAG_SF_LOC, LshrOp);
+  }
+
+  // OF
+  {
+    COND_FLAG_SET(Src2, RFLAG_OF_LOC, _Constant(0));
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_ShiftLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+  // No flags changed if shift is zero
+  if (Shift == 0) return;
+
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(1, GetSrcSize(Op) * 8 - Shift, Src1));
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // SF
+  {
+    auto LshrOp = _Bfe(1, GetSrcSize(Op) * 8 - 1, Res);
+
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+
+    // OF
+    // In the case of left shift. OF is only set from the result of <Top Source Bit> XOR <Top Result Bit>
+    if (Shift == 1) {
+      auto SourceBit = _Bfe(1, GetSrcSize(Op) * 8 - 1, Src1);
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Xor(SourceBit, LshrOp));
+    }
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_SignShiftRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+  // No flags changed if shift is zero
+  if (Shift == 0) return;
+
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(1, Shift-1, Src1));
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+
+    // OF
+    // Only defined when Shift is 1 else undefined
+    // Only is set if the top bit was set to 1 when shifted
+    // So it is set to same value as SF
+    if (Shift == 1) {
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Constant(0));
+    }
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_ShiftRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+  // No flags changed if shift is zero
+  if (Shift == 0) return;
+
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(1, Shift-1, Src1));
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // OF
+  {
+    // Only defined when Shift is 1 else undefined
+    // Is set to the MSB of the original value
+    if (Shift == 1) {
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Bfe(1, GetSrcSize(Op) * 8 - 1, Src1));
+    }
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_RotateRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  auto OpSize = GetSrcSize(Op) * 8;
+
+  // Extract the last bit shifted in to CF
+  auto NewCF = _Bfe(1, OpSize - 1, Res);
+
+  // CF
+  {
+    auto OldCF = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC);
+    auto CF = _Select(FEXCore::IR::COND_EQ, Src2, _Constant(0), OldCF, NewCF);
+
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(CF);
+  }
+
+  // OF
+  {
+    auto OldOF = GetRFLAG(FEXCore::X86State::RFLAG_OF_LOC);
+
+    // OF is set to the XOR of the new CF bit and the most significant bit of the result
+    auto NewOF = _Xor(_Bfe(1, OpSize - 2, Res), NewCF);
+
+    // If shift == 0, don't update flags
+    auto OF = _Select(FEXCore::IR::COND_EQ, Src2, _Constant(0), OldOF, NewOF);
+
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(OF);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_RotateLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  auto OpSize = GetSrcSize(Op) * 8;
+
+  // Extract the last bit shifted in to CF
+  //auto Size = _Constant(GetSrcSize(Res) * 8);
+  //auto ShiftAmt = _Sub(Size, Src2);
+  auto NewCF = _Bfe(1, 0, Res);
+
+  // CF
+  {
+    auto OldCF = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC);
+    auto CF = _Select(FEXCore::IR::COND_EQ, Src2, _Constant(0), OldCF, NewCF);
+
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(CF);
+  }
+
+  // OF
+  {
+    auto OldOF = GetRFLAG(FEXCore::X86State::RFLAG_OF_LOC);
+    // OF is set to the XOR of the new CF bit and the most significant bit of the result
+    auto NewOF = _Xor(_Bfe(1, OpSize - 1, Res), NewCF);
+
+    auto OF = _Select(FEXCore::IR::COND_EQ, Src2, _Constant(0), OldOF, NewOF);
+
+    // If shift == 0, don't update flags
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(OF);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_RotateRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+  if (Shift == 0) return;
+
+  auto OpSize = GetSrcSize(Op) * 8;
+
+  auto NewCF = _Bfe(1, OpSize - Shift, Src1);
+
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(NewCF);
+  }
+
+  // OF
+  {
+    if (Shift == 1) {
+      // OF is set to the XOR of the new CF bit and the most significant bit of the result
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Xor(_Bfe(1, OpSize - 1, Res), NewCF));
+    }
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_RotateLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+  if (Shift == 0) return;
+
+  auto OpSize = GetSrcSize(Op) * 8;
+
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(1, Shift, Src1));
+  }
+
+  // OF
+  {
+    if (Shift == 1) {
+      // OF is the top two MSBs XOR'd together
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Xor(_Bfe(1, OpSize - 1, Src1), _Bfe(1, OpSize - 2, Src1)));
+    }
+  }
+}
+
+}

External/FEXCore/Source/Interface/Core/VSyscall/VSyscall.inc

@@ -0,0 +1,285 @@
+// This is the vsyscall page for x86_64 guest code
+// This was compiled with nasm with the following source then exported to binary
+
+//BITS 64;
+//
+//align 4096, db 0xcc
+//  ; __NR_gettimeofday
+//  mov rax, 96
+//  syscall
+//  ret
+//
+//align 1024, db 0xcc
+//  ; __NR_time
+//  mov rax, 201
+//  syscall
+//  ret
+//
+//align 1024, db 0xcc
+//  ; __NR_getcpu
+//  mov rax, 309
+//  syscall
+//  ret
+//
+//align 4096, db 0xcc
+
+// We only want one of these pages per FEX process
+// One page
+const static uint8_t VSyscallData[0x1000] = {
+	0xB8, 0x60, 0x00, 0x00, 0x00, 0x0F, 0x05, 0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xB8, 0xC9, 0x00, 0x00, 0x00, 0x0F, 0x05, 0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xB8, 0x35, 0x01, 0x00, 0x00, 0x0F, 0x05, 0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC
+};

External/FEXCore/Source/Interface/Core/X86DebugInfo.cpp

@@ -114,8 +114,6 @@ void InstallDebugInfo() {
   GenerateDebugTable(PrimaryInstGroupOps, PrimaryGroupOpTable);
 
   GenerateDebugTable(SecondInstGroupOps, SecondaryExtensionOpTable);
-
-  LogMan::Msg::D("Installing debug info");
 }
 }
 #endif

External/FEXCore/Source/Interface/Core/X86HelperGen.cpp

@@ -1,4 +1,12 @@
+/*
+$info$
+tags: glue|x86-guest-code
+desc: Guest-side assembly helpers used by the backends
+$end_info$
+*/
+
 #include "Interface/Core/X86HelperGen.h"
+#include <FEXCore/Utils/Allocator.h>
 
 #include <cstring>
 #include <stdlib.h>
@@ -24,15 +32,15 @@ X86GeneratedCode::X86GeneratedCode() {
 }
 
 X86GeneratedCode::~X86GeneratedCode() {
-  munmap(CodePtr, CODE_SIZE);
+  FEXCore::Allocator::munmap(CodePtr, CODE_SIZE);
 }
 
 void* X86GeneratedCode::AllocateGuestCodeSpace(size_t Size) {
-  FEXCore::Config::Value<bool> Is64BitMode{FEXCore::Config::CONFIG_IS64BIT_MODE, 0};
+  FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
 
   if (Is64BitMode()) {
     // 64bit mode can have its sigret handler anywhere
-    return mmap(nullptr, Size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+    return FEXCore::Allocator::mmap(nullptr, Size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
   }
 
   // First 64bit page
@@ -42,14 +50,14 @@ void* X86GeneratedCode::AllocateGuestCodeSpace(size_t Size) {
   // We need to have the sigret handler in the lower 32bits of memory space
   // Scan top down and try to allocate a location
   for (size_t Location = 0xFFFF'E000; Location != 0x0; Location -= 0x1000) {
-    void *Ptr = mmap(reinterpret_cast<void*>(Location), Size, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+    void *Ptr = ::mmap(reinterpret_cast<void*>(Location), Size, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 
     if (Ptr != MAP_FAILED &&
         reinterpret_cast<uintptr_t>(Ptr) >= LOCATION_MAX) {
       // Failed to map in the lower 32bits
       // Try again
       // Can happen in the case that host kernel ignores MAP_FIXED_NOREPLACE
-      munmap(Ptr, Size);
+      ::munmap(Ptr, Size);
       continue;
     }
 

External/FEXCore/Source/Interface/Core/X86HelperGen.h

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: glue|x86-guest-code
+$end_info$
+*/
+
 #pragma once
 #include <FEXCore/Config/Config.h>
 

External/FEXCore/Source/Interface/Core/X86Tables.cpp

@@ -1,3 +1,10 @@
+/*
+$info$
+meta: frontend|x86-tables ~ Metadata that drives the frontend x86/64 decoding
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include <FEXCore/Utils/LogManager.h>
 
 #include <FEXCore/Core/Context.h>
@@ -101,7 +108,6 @@ void InitializeInfoTables(Context::OperatingMode Mode) {
 
 #ifndef NDEBUG
   X86InstDebugInfo::InstallDebugInfo();
-  LogMan::Msg::D("X86Tables had %ld total insts, and %ld labeled as understood", Total, NumInsts);
 #endif
 }
 

External/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 #include <FEXCore/Core/Context.h>
@@ -279,13 +285,13 @@ void InitializeBaseTables(Context::OperatingMode Mode) {
     {0xEA, 1, X86InstInfo{"JMPF",   TYPE_INST, FLAGS_NONE,                                                        0, nullptr}},
   };
 
-  GenerateTable(BaseOps, BaseOpTable, sizeof(BaseOpTable) / sizeof(BaseOpTable[0]));
+  GenerateTable(BaseOps, BaseOpTable, std::size(BaseOpTable));
 
   if (Mode == Context::MODE_64BIT) {
-    GenerateTable(BaseOps, BaseOpTable_64, sizeof(BaseOpTable_64) / sizeof(BaseOpTable_64[0]));
+    GenerateTable(BaseOps, BaseOpTable_64, std::size(BaseOpTable_64));
   }
   else {
-    GenerateTable(BaseOps, BaseOpTable_32, sizeof(BaseOpTable_32) / sizeof(BaseOpTable_32[0]));
+    GenerateTable(BaseOps, BaseOpTable_32, std::size(BaseOpTable_32));
   }
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/DDDTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -38,6 +44,6 @@ void InitializeDDDTables() {
     {0xB7, 1, X86InstInfo{"PMULHRW",  TYPE_3DNOW_INST, FLAGS_MODRM, 0, nullptr}},
   };
 
-  GenerateTable(DDDNowOps, DDDNowOpTable, sizeof(DDDNowOpTable) / sizeof(DDDNowOpTable[0]));
+  GenerateTable(DDDNowOps, DDDNowOpTable, std::size(DDDNowOpTable));
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/EVEXTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -20,6 +26,6 @@ void InitializeEVEXTables() {
     {0xE7, 1, X86InstInfo{"VMOVNTDQ",        TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
   };
 
-  GenerateTable(EVEXTableOps, EVEXTable, sizeof(EVEXTable) / sizeof(EVEXTable[0]));
+  GenerateTable(EVEXTableOps, EVEXTable, std::size(EVEXTable));
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/H0F38Tables.cpp

@@ -1,3 +1,11 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
+#include <FEXCore/Core/Context.h>
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -35,10 +43,10 @@ void InitializeH0F38Tables() {
     {OPD(PF_38_NONE, 0x0B), 1, X86InstInfo{"PMULHRSW",   TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
     {OPD(PF_38_66,   0x0B), 1, X86InstInfo{"PMULHRSW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x10), 1, X86InstInfo{"PBLENDVB",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x14), 1, X86InstInfo{"BLENDVPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x15), 1, X86InstInfo{"BLENDVPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x17), 1, X86InstInfo{"PTEST",      TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(PF_38_66,   0x10), 1, X86InstInfo{"PBLENDVB",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x14), 1, X86InstInfo{"BLENDVPS",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x15), 1, X86InstInfo{"BLENDVPD",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x17), 1, X86InstInfo{"PTEST",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(PF_38_NONE, 0x1C), 1, X86InstInfo{"PABSB",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
     {OPD(PF_38_66,   0x1C), 1, X86InstInfo{"PABSB",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(PF_38_NONE, 0x1D), 1, X86InstInfo{"PABSW",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
@@ -46,34 +54,34 @@ void InitializeH0F38Tables() {
     {OPD(PF_38_NONE, 0x1E), 1, X86InstInfo{"PABSD",      TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 0, nullptr}},
     {OPD(PF_38_66,   0x1E), 1, X86InstInfo{"PABSD",      TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x20), 1, X86InstInfo{"PMOVSXBW",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x21), 1, X86InstInfo{"PMOVSXBD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x22), 1, X86InstInfo{"PMOVSXBQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x23), 1, X86InstInfo{"PMOVSXWD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x24), 1, X86InstInfo{"PMOVSXWQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x25), 1, X86InstInfo{"PMOVSXDQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x28), 1, X86InstInfo{"PMULDQ",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x29), 1, X86InstInfo{"PCMPEQQ",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x2A), 1, X86InstInfo{"MOVNTDQA",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x2B), 1, X86InstInfo{"PACKUSDW",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(PF_38_66,   0x20), 1, X86InstInfo{"PMOVSXBW",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x21), 1, X86InstInfo{"PMOVSXBD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x22), 1, X86InstInfo{"PMOVSXBQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x23), 1, X86InstInfo{"PMOVSXWD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x24), 1, X86InstInfo{"PMOVSXWQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x25), 1, X86InstInfo{"PMOVSXDQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x28), 1, X86InstInfo{"PMULDQ",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x29), 1, X86InstInfo{"PCMPEQQ",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x2A), 1, X86InstInfo{"MOVNTDQA",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x2B), 1, X86InstInfo{"PACKUSDW",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x30), 1, X86InstInfo{"PMOVZXBW",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x31), 1, X86InstInfo{"PMOVZXBD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x32), 1, X86InstInfo{"PMOVZXBQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x33), 1, X86InstInfo{"PMOVZXWD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x34), 1, X86InstInfo{"PMOVZXWQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x35), 1, X86InstInfo{"PMOVZXDQ",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x38), 1, X86InstInfo{"PMINSB",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x39), 1, X86InstInfo{"PMINSD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x3A), 1, X86InstInfo{"PMINUW",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x3B), 1, X86InstInfo{"PMINUD",     TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(PF_38_66,   0x3C), 1, X86InstInfo{"PMAXSB",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x3D), 1, X86InstInfo{"PMAXSD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x3E), 1, X86InstInfo{"PMAXUW",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x3F), 1, X86InstInfo{"PMAXUD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(PF_38_66,   0x30), 1, X86InstInfo{"PMOVZXBW",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x31), 1, X86InstInfo{"PMOVZXBD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x32), 1, X86InstInfo{"PMOVZXBQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_16BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x33), 1, X86InstInfo{"PMOVZXWD",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x34), 1, X86InstInfo{"PMOVZXWQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x35), 1, X86InstInfo{"PMOVZXDQ",   TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x38), 1, X86InstInfo{"PMINSB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x39), 1, X86InstInfo{"PMINSD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3A), 1, X86InstInfo{"PMINUW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3B), 1, X86InstInfo{"PMINUD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3C), 1, X86InstInfo{"PMAXSB",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3D), 1, X86InstInfo{"PMAXSD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3E), 1, X86InstInfo{"PMAXUW",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x3F), 1, X86InstInfo{"PMAXUD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(PF_38_66,   0x40), 1, X86InstInfo{"PMULLD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(PF_38_66,   0x41), 1, X86InstInfo{"PHMINPOSUW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(PF_38_66,   0x40), 1, X86InstInfo{"PMULLD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(PF_38_66,   0x41), 1, X86InstInfo{"PHMINPOSUW", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
     {OPD(PF_38_66,   0xDB), 1, X86InstInfo{"AESIMC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(PF_38_66,   0xDC), 1, X86InstInfo{"AESENC",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
@@ -92,6 +100,6 @@ void InitializeH0F38Tables() {
   };
 #undef OPD
 
-  GenerateTable(H0F38TableOps, H0F38Table, sizeof(H0F38Table) / sizeof(H0F38Table[0]));
+  GenerateTable(H0F38TableOps, H0F38Table, std::size(H0F38Table));
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/H0F3ATables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -10,26 +16,26 @@ void InitializeH0F3ATables(Context::OperatingMode Mode) {
 
   const U16U8InfoStruct H0F3ATable[] = {
     {OPD(0, PF_3A_NONE, 0x0F), 1, X86InstInfo{"PALIGNR",         TYPE_INST, GenFlagsSameSize(SIZE_64BIT)  | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_MMX, 1, nullptr}},
-    {OPD(0, PF_3A_66,   0x08), 1, X86InstInfo{"ROUNDPS",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x09), 1, X86InstInfo{"ROUNDPD",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x0A), 1, X86InstInfo{"ROUNDSS",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x0B), 1, X86InstInfo{"ROUNDSD",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x0C), 1, X86InstInfo{"BLENDPS",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x0D), 1, X86InstInfo{"BLENDPD",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x0E), 1, X86InstInfo{"PBLENDW",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(0, PF_3A_66,   0x08), 1, X86InstInfo{"ROUNDPS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x09), 1, X86InstInfo{"ROUNDPD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x0A), 1, X86InstInfo{"ROUNDSS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x0B), 1, X86InstInfo{"ROUNDSD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x0C), 1, X86InstInfo{"BLENDPS",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
+    {OPD(0, PF_3A_66,   0x0D), 1, X86InstInfo{"BLENDPD",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
+    {OPD(0, PF_3A_66,   0x0E), 1, X86InstInfo{"PBLENDW",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
     {OPD(0, PF_3A_66,   0x0F), 1, X86InstInfo{"PALIGNR",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
 
     {OPD(0, PF_3A_66,   0x14), 1, X86InstInfo{"PEXTRB",          TYPE_INST, GenFlagsSizes(SIZE_8BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
     {OPD(0, PF_3A_66,   0x15), 1, X86InstInfo{"PEXTRW",          TYPE_INST, GenFlagsSizes(SIZE_16BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
     {OPD(0, PF_3A_66,   0x16), 1, X86InstInfo{"PEXTRD",          TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
-    {OPD(0, PF_3A_66,   0x17), 1, X86InstInfo{"EXTRACTPS",       TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(0, PF_3A_66,   0x17), 1, X86InstInfo{"EXTRACTPS",       TYPE_INST, GenFlagsSizes(SIZE_32BIT, SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_DST_GPR | FLAGS_XMM_FLAGS, 1, nullptr}},
 
-    {OPD(0, PF_3A_66,   0x20), 1, X86InstInfo{"PINSRB",          TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_8BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1, nullptr}},
-    {OPD(0, PF_3A_66,   0x21), 1, X86InstInfo{"INSERTPS",        TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(0, PF_3A_66,   0x20), 1, X86InstInfo{"PINSRB",          TYPE_INST, GenFlagsDstSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1, nullptr}},
+    {OPD(0, PF_3A_66,   0x21), 1, X86InstInfo{"INSERTPS",        TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,           1, nullptr}},
     {OPD(0, PF_3A_66,   0x22), 1, X86InstInfo{"PINSRD",          TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR,           1, nullptr}},
-    {OPD(0, PF_3A_66,   0x40), 1, X86InstInfo{"DPPS",            TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x41), 1, X86InstInfo{"DPPD",            TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(0, PF_3A_66,   0x42), 1, X86InstInfo{"MPSADBW",         TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(0, PF_3A_66,   0x40), 1, X86InstInfo{"DPPS",            TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x41), 1, X86InstInfo{"DPPD",            TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
+    {OPD(0, PF_3A_66,   0x42), 1, X86InstInfo{"MPSADBW",         TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 1, nullptr}},
     {OPD(0, PF_3A_66,   0x44), 1, X86InstInfo{"PCLMULQDQ",       TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
 
     {OPD(0, PF_3A_66,   0x60), 1, X86InstInfo{"PCMPESTRM",       TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
@@ -48,10 +54,10 @@ void InitializeH0F3ATables(Context::OperatingMode Mode) {
 
 #undef OPD
 
-  GenerateTable(H0F3ATableOps, H0F3ATable, sizeof(H0F3ATable) / sizeof(H0F3ATable[0]));
+  GenerateTable(H0F3ATableOps, H0F3ATable, std::size(H0F3ATable));
 
   if (Mode == Context::MODE_64BIT) {
-    GenerateTable(H0F3ATableOps, H0F3ATable_64, sizeof(H0F3ATable_64) / sizeof(H0F3ATable_64[0]));
+    GenerateTable(H0F3ATableOps, H0F3ATable_64, std::size(H0F3ATable_64));
   }
 }
 }

External/FEXCore/Source/Interface/Core/X86Tables/PrimaryGroupTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -152,12 +158,12 @@ void InitializePrimaryGroupTables(Context::OperatingMode Mode) {
 
 #undef OPD
 
-  GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable, sizeof(PrimaryGroupOpTable) / sizeof(PrimaryGroupOpTable[0]));
+  GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable, std::size(PrimaryGroupOpTable));
   if (Mode == Context::MODE_64BIT) {
-    GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable_64, sizeof(PrimaryGroupOpTable_64) / sizeof(PrimaryGroupOpTable_64[0]));
+    GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable_64, std::size(PrimaryGroupOpTable_64));
   }
   else {
-    GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable_32, sizeof(PrimaryGroupOpTable_32) / sizeof(PrimaryGroupOpTable_32[0]));
+    GenerateTable(PrimaryInstGroupOps, PrimaryGroupOpTable_32, std::size(PrimaryGroupOpTable_32));
   }
 
 }

External/FEXCore/Source/Interface/Core/X86Tables/SecondaryGroupTables.cpp

@@ -1,3 +1,9 @@
+/*
+$info$
+tags: frontend|x86-tables
+$end_info$
+*/
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {
@@ -477,7 +483,7 @@ void InitializeSecondaryGroupTables() {
   };
 #undef OPD
 
-  GenerateTable(SecondInstGroupOps, SecondaryExtensionOpTable, sizeof(SecondaryExtensionOpTable) / sizeof(SecondaryExtensionOpTable[0]));
+  GenerateTable(SecondInstGroupOps, SecondaryExtensionOpTable, std::size(SecondaryExtensionOpTable));
 }
 
 }