Docs: Update for release FEX-2108

AArch64: Workaround static-pie crashing

.gitmodules

@@ -39,3 +39,6 @@
 [submodule "External/drm-headers"]
 	path = External/drm-headers
 	url = https://github.com/FEX-Emu/drm-headers.git
+[submodule "External/xxhash"]
+	path = External/xxhash
+	url = https://github.com/FEX-Emu/xxHash.git

CMakeLists.txt

@@ -14,6 +14,8 @@ option(ENABLE_ASSERTIONS "Enables assertions in build" FALSE)
 option(ENABLE_VISUAL_DEBUGGER "Enables the visual debugger for compiling" FALSE)
 option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
 option(ENABLE_WERROR "Enables -Werror" FALSE)
+option(ENABLE_STATIC_PIE "Enables static-pie build" FALSE)
+option(ENABLE_JEMALLOC "Enables jemalloc allocator" TRUE)
 
 set (X86_C_COMPILER "x86_64-linux-gnu-gcc" CACHE STRING "c compiler for compiling x86 guest libs")
 set (X86_CXX_COMPILER "x86_64-linux-gnu-g++" CACHE STRING "c++ compiler for compiling x86 guest libs")
@@ -44,38 +46,6 @@ else()
   set(CMAKE_INTERPROCEDURAL_OPTIMIZATION FALSE)
 endif()
 
-find_program(CCACHE_PROGRAM ccache)
-if(CCACHE_PROGRAM)
-  message(STATUS "CCache enabled")
-  set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE "${CCACHE_PROGRAM}")
-endif()
-
-if (ENABLE_XRAY)
-  add_compile_options(-fxray-instrument)
-  link_libraries(-fxray-instrument)
-endif()
-
-if (ENABLE_LLD)
-  link_libraries(-fuse-ld=lld)
-endif()
-
-if (ENABLE_ASAN)
-  add_definitions(-DENABLE_ASAN=1)
-  add_compile_options(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
-  link_libraries(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
-endif()
-
-if (ENABLE_TSAN)
-  add_compile_options(-fno-omit-frame-pointer -fsanitize=thread)
-  link_libraries(-fno-omit-frame-pointer -fsanitize=thread)
-endif()
-
-set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
-set (CMAKE_LINKER_FLAGS_RELWITHDEBINFO "${CMAKE_LINKER_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
-
-set (CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -fomit-frame-pointer")
-set (CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-pointer")
-
 if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
   option(ENABLE_X86_HOST_DEBUG "Enables compiling on x86_64 host" FALSE)
   if (NOT ENABLE_X86_HOST_DEBUG)
@@ -95,6 +65,174 @@ if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
   add_definitions(-D_M_ARM_64=1)
 endif()
 
+find_program(CCACHE_PROGRAM ccache)
+if(CCACHE_PROGRAM)
+  message(STATUS "CCache enabled")
+  set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE "${CCACHE_PROGRAM}")
+endif()
+
+if (ENABLE_XRAY)
+  add_compile_options(-fxray-instrument)
+  link_libraries(-fxray-instrument)
+endif()
+
+set (PTHREAD_LIB pthread)
+if (ENABLE_LLD)
+  set (LD_OVERRIDE "-fuse-ld=lld")
+  link_libraries(${LD_OVERRIDE})
+endif()
+
+if (ENABLE_STATIC_PIE)
+  if (_M_ARM_64 AND ENABLE_LLD)
+    message (FATAL_ERROR "Static linking does not currently work with AArch64+LLD. Use GNU ld for now.")
+  endif()
+
+  file(WRITE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt.c
+    "int main(int argc, char* argv[])
+      {
+        return 0;
+      }")
+
+  # Compile the test application with our LD_OVERRIDE and static-pie options
+  try_compile(
+    COMPILE_RESULT
+    ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp
+    ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt.c
+    COMPILE_DEFINITIONS "-fPIE ${LD_OVERRIDE}"
+    LINK_LIBRARIES "-static-pie ${LD_OVERRIDE}"
+    COPY_FILE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt
+  )
+
+  if (${COMPILE_RESULT})
+    # Read the symbols from the elf
+    execute_process(COMMAND
+      readelf -s ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/Determine_iplt
+      OUTPUT_FILE ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/plt_out.txt
+      OUTPUT_VARIABLE PLT_SYMBOLS)
+
+    # Pull out the __rela_iplt_{start,end} symbols if they exist
+    execute_process(COMMAND
+      "grep" "__rela_iplt" ${PROJECT_BINARY_DIR}/CMakeFiles/CMakeTmp/plt_out.txt
+      OUTPUT_VARIABLE PLT_SYMBOLS)
+
+    set (SYMBOLS_FINE TRUE)
+    set (HAS_IPLT -1)
+    # Check if we have any symbols in our grep output
+    # The symbols must either not exist at all OR the symbols are zero
+    if (PLT_SYMBOLS)
+      string(FIND ${PLT_SYMBOLS} "__rela_iplt_start" HAS_IPLT)
+    endif()
+
+    if (NOT HAS_IPLT EQUAL -1)
+      # We have some symbols from readelf. Let's parse the results to check if they are zero
+      # Format: '35: 0000000000000000     0 NOTYPE  LOCAL  HIDDEN   UND __rela_iplt_start'
+      string(REPLACE "\n" ";" SYMBOL_LIST ${PLT_SYMBOLS})
+      foreach (SYMBOL ${SYMBOL_LIST})
+        # strip any leading and trailing whitespace
+        string (STRIP ${SYMBOL} SYMBOL)
+        # Convert string to a list
+        string(REPLACE " " ";" SYMBOL_VALUES ${SYMBOL}})
+        # Pull out the address argument
+        list(GET SYMBOL_VALUES 1 OFFSET)
+
+        # Check against integer zero
+        if (NOT ${OFFSET} EQUAL 0)
+          # Symbol wasn't zero, this now fails
+          set (SYMBOLS_FINE FALSE)
+        endif()
+      endforeach()
+    endif()
+
+    if (SYMBOLS_FINE)
+      # We can now exnable static-pie
+      set (STATIC_PIE_OPTIONS "-static-pie")
+      # Pthreads has an issue with exposing symbols
+      # We need to make some concessions to the pthread gods
+      if (ENABLE_LLD)
+        set (PTHREAD_LIB
+          -Wl,--undefined-glob=pthread_*
+          -Wl,--undefined=__cxa_finalize
+          -Wl,--undefined=_pthread_cleanup_push_defer
+          -Wl,--undefined=_pthread_cleanup_pop_restore
+          -Wl,--undefined=__pthread_cleanup_upto
+          pthread)
+      else()
+        set (PTHREAD_LIB
+          -Wl,--undefined=pthread_join
+          -Wl,--undefined=pthread_attr_getdetachstate
+          -Wl,--undefined=pthread_sigmask
+          -Wl,--undefined=pthread_mutex_lock
+          -Wl,--undefined=pthread_cond_init
+          -Wl,--undefined=pthread_attr_init
+          -Wl,--undefined=pthread_mutex_unlock
+          -Wl,--undefined=pthread_mutexattr_destroy
+          -Wl,--undefined=pthread_detach
+          -Wl,--undefined=pthread_mutex_init
+          -Wl,--undefined=pthread_getattr_np
+          -Wl,--undefined=pthread_cond_timedwait
+          -Wl,--undefined=pthread_attr_destroy
+          -Wl,--undefined=pthread_mutexattr_settype
+          -Wl,--undefined=pthread_rwlock_unlock
+          -Wl,--undefined=pthread_rwlock_wrlock
+          -Wl,--undefined=pthread_setspecific
+          -Wl,--undefined=pthread_create
+          -Wl,--undefined=pthread_cond_clockwait
+          -Wl,--undefined=pthread_key_create
+          -Wl,--undefined=pthread_rwlock_rdlock
+          -Wl,--undefined=pthread_setname_np
+          -Wl,--undefined=pthread_cond_signal
+          -Wl,--undefined=pthread_mutexattr_init
+          -Wl,--undefined=pthread_attr_setstack
+          -Wl,--undefined=pthread_self
+          -Wl,--undefined=pthread_getaffinity_np
+          -Wl,--undefined=pthread_cond_wait
+          -Wl,--undefined=pthread_mutex_trylock
+          -Wl,--undefined=pthread_cond_broadcast
+          -Wl,--undefined=pthread_cond_destroy
+          -Wl,--undefined=pthread_getspecific
+          -Wl,--undefined=pthread_key_delete
+          -Wl,--undefined=pthread_once
+          -Wl,--undefined=__cxa_finalize
+          -Wl,--undefined=_pthread_cleanup_push_defer
+          -Wl,--undefined=_pthread_cleanup_pop_restore
+          -Wl,--undefined=__pthread_cleanup_upto
+          pthread)
+      endif()
+    else()
+      message (FATAL_ERROR "Application has __rela_iplt_{start,end} symbols. Which means static-pie can't be enabled")
+    endif()
+  else()
+    message (FATAL_ERROR "Couldn't compile static-pie test. Static-pie can't be enabled!")
+  endif()
+endif()
+
+if (ENABLE_ASAN)
+  add_definitions(-DENABLE_ASAN=1)
+  add_compile_options(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
+  link_libraries(-fno-omit-frame-pointer -fsanitize=address -fsanitize-address-use-after-scope)
+endif()
+
+if (ENABLE_TSAN)
+  add_compile_options(-fno-omit-frame-pointer -fsanitize=thread)
+  link_libraries(-fno-omit-frame-pointer -fsanitize=thread)
+endif()
+
+if (ENABLE_JEMALLOC)
+  add_definitions(-DENABLE_JEMALLOC=1)
+else()
+  message (STATUS
+    " jemalloc disabled!\n"
+    " This is not a recommended configuration!\n"
+    " This will very explicitly break 32-bit application execution!\n"
+    " Use at your own risk!")
+endif()
+
+set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
+set (CMAKE_LINKER_FLAGS_RELWITHDEBINFO "${CMAKE_LINKER_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
+
+set (CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -fomit-frame-pointer")
+set (CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-pointer")
+
 add_subdirectory(External/vixl/)
 include_directories(External/vixl/src/)
 
@@ -105,7 +243,13 @@ endif()
 
 find_package(PkgConfig REQUIRED)
 find_package(Python 3.0 REQUIRED COMPONENTS Interpreter)
-pkg_check_modules(XXHASH libxxhash REQUIRED)
+pkg_check_modules(XXHASH libxxhash>=0.8.0 QUIET)
+
+if (NOT XXHASH_FOUND)
+  message(STATUS "xxHash not found. Using Externals")
+  add_subdirectory(External/xxhash/)
+  include_directories(External/xxhash/)
+endif()
 
 add_definitions(-Wno-trigraphs)
 add_definitions(-DGLOBAL_DATA_DIRECTORY="${DATA_DIRECTORY}/")
@@ -356,6 +500,7 @@ endif()
 
 # Package creation
 set (CPACK_GENERATOR "DEB")
+set (CPACK_PACKAGE_NAME fex-emu)
 set (CPACK_PACKAGE_CONTACT "team@fex-emu.org")
 set (CPACK_PACKAGE_VERSION_MAJOR "${FEX_VERSION_MAJOR}")
 set (CPACK_PACKAGE_VERSION_MINOR "${FEX_VERSION_MINOR}")

Data/AppConfig/steamwebhelper.json

@@ -0,0 +1,5 @@
+{
+  "Config": {
+    "StallProcess": "1"
+  }
+}

Data/binfmts/CMakeLists.txt

@@ -1,4 +1,17 @@
-install(FILES FEX-x86
-  DESTINATION ${CMAKE_INSTALL_PREFIX}/share/binfmts/)
-install(FILES FEX-x86_64
-  DESTINATION ${CMAKE_INSTALL_PREFIX}/share/binfmts/)
+function(GenBinFmt Name)
+  # Get the filename only component
+  get_filename_component(FMT_NAME ${Name} NAME_WE)
+
+  # Configure it
+  configure_file(
+    ${Name}
+    ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME})
+
+  # Then install the configured binfmt
+  install(
+    FILES ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME}
+    DESTINATION ${CMAKE_INSTALL_PREFIX}/share/binfmts/)
+endfunction()
+
+GenBinFmt(FEX-x86.in)
+GenBinFmt(FEX-x86_64.in)

Data/binfmts/FEX-x86.in

@@ -1,9 +1,8 @@
 package fex
-interpreter /usr/bin/FEXInterpreter
+interpreter @CMAKE_INSTALL_PREFIX@/bin/FEXInterpreter
 magic \x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00
 offset 0
 mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff
 credentials yes
 fix_binary yes
-preserve no
-
+preserve yes

Data/binfmts/FEX-x86_64.in

@@ -1,8 +1,8 @@
 package fex
-interpreter /usr/bin/FEXInterpreter
+interpreter @CMAKE_INSTALL_PREFIX@/bin/FEXInterpreter
 magic \x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x3e\x00
 offset 0
 mask \xff\xff\xff\xff\xff\xfe\xfe\x00\x00\x00\x00\xff\xff\xff\xff\xff\xfe\xff\xff\xff
 credentials yes
 fix_binary yes
-preserve no
+preserve yes

External/FEXCore/Scripts/config_generator.py

@@ -98,14 +98,19 @@ def print_man_option(short, long, desc, default):
     output_man.write("\\fBdefault:\\fR {0}\n".format(default))
     output_man.write(".Pp\n\n")
 
-def print_man_env_option(name, desc, default):
-    output_man.write("\\fBFEX_{0}\\fR\n".format(name))
+def print_man_env_option(name, desc, default, no_json_key):
+    output_man.write("\\fBFEX_{0}\\fR\n".format(name.upper()))
 
     # Print description
     for line in desc:
         output_man.write(".Pp\n")
         output_man.write("{0}\n".format(line))
 
+    if (not no_json_key):
+        output_man.write(".Pp\n")
+        output_man.write("\\fBJSON key:\\fR '{0}'\n".format(name))
+        output_man.write(".Pp\n\n")
+
     output_man.write(".Pp\n")
     output_man.write("\\fBdefault:\\fR {0}\n".format(default))
     output_man.write(".Pp\n\n")
@@ -154,9 +159,10 @@ def print_man_environment(options):
                 # Wrap the string argument in quotes
                 default = "'" + default + "'"
             print_man_env_option(
-                op_key.upper(),
+                op_key,
                 op_vals["Desc"],
-                default
+                default,
+                False
             )
 
     print_man_environment_tail()
@@ -172,7 +178,7 @@ def print_man_environment_tail():
     "By default FEX will look in {$HOME, $XDG_CONFIG_HOME}/.fex-emu/",
     "This will override the full path",
     ],
-    "''")
+    "''", True)
 
     print_man_env_option(
     "FEX_APP_CONFIG",
@@ -183,7 +189,7 @@ def print_man_environment_tail():
     "One must be careful with this option as it will override any applications that load with execve as well"
     "If you need to support applications that execve then use FEX_APP_CONFIG_LOCATION instead"
     ],
-    "''")
+    "''", True)
 
     print_man_env_option(
     "FEX_APP_DATA_LOCATION",
@@ -193,7 +199,7 @@ def print_man_environment_tail():
     "This will override the full path",
     "This is the folder where FEX stores generated files like IR cache"
     ],
-    "''")
+    "''", True)
 
 def print_man_header():
     header ='''.Dd {0}

External/FEXCore/Source/CMakeLists.txt

@@ -81,6 +81,10 @@ set (SRCS
   Interface/Core/Frontend.cpp
   Interface/Core/GdbServer.cpp
   Interface/Core/HostFeatures.cpp
+  Interface/Core/OpcodeDispatcher/Crypto.cpp
+  Interface/Core/OpcodeDispatcher/Flags.cpp
+  Interface/Core/OpcodeDispatcher/Vector.cpp
+  Interface/Core/OpcodeDispatcher/X87.cpp
   Interface/Core/OpcodeDispatcher.cpp
   Interface/Core/X86Tables.cpp
   Interface/Core/X86DebugInfo.cpp
@@ -133,7 +137,7 @@ if(_M_ARM_64)
     Interface/Core/ArchHelpers/Arm64.cpp)
 endif()
 
-set(DEFINES )
+set(DEFINES -DTHREAD_LOCAL=_Thread_local)
 
 if (_M_X86_64)
   list(APPEND DEFINES -D_M_X86_64=1)
@@ -265,7 +269,7 @@ function(AddObject Name Type)
   add_dependencies(${Name} IR_INC)
   add_dependencies(${Name} CONFIG_INC)
 
-  target_link_libraries(${Name} pthread vixl dl fmt::fmt xxhash FEX_jemalloc)
+  target_link_libraries(${Name} vixl dl fmt::fmt xxhash)
   set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
   set_target_properties(${Name} PROPERTIES C_VISIBILITY_PRESET hidden)
   set_target_properties(${Name} PROPERTIES CXX_VISIBILITY_PRESET hidden)
@@ -306,7 +310,7 @@ endfunction()
 
 function(AddLibrary Name Type)
   add_library(${Name} ${Type} $<TARGET_OBJECTS:${PROJECT_NAME}_object>)
-  target_link_libraries(${Name} pthread vixl dl fmt::fmt xxhash FEX_jemalloc)
+  target_link_libraries(${Name} vixl dl fmt::fmt xxhash)
   set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
   set_target_properties(${Name} PROPERTIES C_VISIBILITY_PRESET hidden)
   set_target_properties(${Name} PROPERTIES CXX_VISIBILITY_PRESET hidden)

External/FEXCore/Source/Common/Paths.cpp

@@ -36,9 +36,10 @@ namespace FEXCore::Paths {
     *CachePath += "/.fex-emu/";
     *EntryCache = *CachePath + "/EntryCache/";
 
+    std::error_code ec{};
     // Ensure the folder structure is created for our Data
-    if (!std::filesystem::exists(*EntryCache) &&
-        !std::filesystem::create_directories(*EntryCache)) {
+    if (!std::filesystem::exists(*EntryCache, ec) &&
+        !std::filesystem::create_directories(*EntryCache, ec)) {
       LogMan::Msg::D("Couldn't create EntryCache directory: '%s'", EntryCache->c_str());
     }
   }

External/FEXCore/Source/Interface/Config/Config.cpp

@@ -59,9 +59,9 @@ namespace FEXCore::Config {
       }
 
       // Ensure the folder structure is created for our configuration
-      if (!std::filesystem::exists(ConfigDir) &&
-          !std::filesystem::create_directories(ConfigDir)) {
-        LogMan::Msg::D("Couldn't create config directory: '%s'", ConfigDir.c_str());
+      std::error_code ec{};
+      if (!std::filesystem::exists(ConfigDir, ec) &&
+          !std::filesystem::create_directories(ConfigDir, ec)) {
         // Let's go local in this case
         return "./";
       }
@@ -85,9 +85,11 @@ namespace FEXCore::Config {
 
   std::string GetApplicationConfig(const std::string &Filename, bool Global) {
     std::string ConfigFile = GetConfigDirectory(Global);
+
+    std::error_code ec{};
     if (!Global &&
-        !std::filesystem::exists(ConfigFile) &&
-        !std::filesystem::create_directories(ConfigFile)) {
+        !std::filesystem::exists(ConfigFile, ec) &&
+        !std::filesystem::create_directories(ConfigFile, ec)) {
       LogMan::Msg::D("Couldn't create config directory: '%s'", ConfigFile.c_str());
       // Let's go local in this case
       return "./" + Filename + ".json";
@@ -97,9 +99,8 @@ namespace FEXCore::Config {
 
     // Attempt to create the local folder if it doesn't exist
     if (!Global &&
-        !std::filesystem::exists(ConfigFile) &&
-        !std::filesystem::create_directories(ConfigFile)) {
-      LogMan::Msg::D("Couldn't create AppConfig directory: '%s'", ConfigFile.c_str());
+        !std::filesystem::exists(ConfigFile, ec) &&
+        !std::filesystem::create_directories(ConfigFile, ec)) {
       // Let's go local in this case
       return "./" + Filename + ".json";
     }
@@ -273,7 +274,8 @@ namespace FEXCore::Config {
       Path = std::filesystem::absolute(Path);
 
       // Only return if it exists
-      if (std::filesystem::exists(Path)) {
+      std::error_code ec{};
+      if (std::filesystem::exists(Path, ec)) {
         return Path;
       }
     }
@@ -309,7 +311,8 @@ namespace FEXCore::Config {
       else if (!PathName().empty()) {
         // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
         std::string NamedRootFS = GetDataDirectory() + "RootFS/" + PathName();
-        if (std::filesystem::exists(NamedRootFS)) {
+        std::error_code ec{};
+        if (std::filesystem::exists(NamedRootFS, ec)) {
           FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, NamedRootFS);
         }
       }
@@ -324,7 +327,19 @@ namespace FEXCore::Config {
     }
     if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_THUNKCONFIG)) {
       FEX_CONFIG_OPT(PathName, THUNKCONFIG);
-      ExpandPathIfExists(FEXCore::Config::CONFIG_THUNKCONFIG, PathName());
+      auto ExpandedString = ExpandPath(PathName());
+      if (!ExpandedString.empty()) {
+        // Adjust the path if it ended up being relative
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, ExpandedString);
+      }
+      else if (!PathName().empty()) {
+        // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
+        std::string NamedConfig = GetDataDirectory() + "ThunkConfigs/" + PathName();
+        std::error_code ec{};
+        if (std::filesystem::exists(NamedConfig, ec)) {
+          FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, NamedConfig);
+        }
+      }
     }
     if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_OUTPUTLOG)) {
       FEX_CONFIG_OPT(PathName, OUTPUTLOG);

External/FEXCore/Source/Interface/Config/Config.json

@@ -77,7 +77,14 @@
         "Default": "",
         "ShortArg": "k",
         "Desc": [
-          "A json file specifying where to overlay the thunks."
+          "A json file specifying where to overlay the thunks.",
+          "This can be a filesystem path",
+          "\teg: ~/MyThunkConfig.json",
+          "Or this can be a named of a Thunk config file",
+          "If the named config file exists in the FEX data folder folder the it will use that one",
+          "\teg: $HOME/.fex-emu/ThunkConfigs/<ThunkConfig name>",
+          "Or if you have XDG_DATA_HOME the config will search in that directory",
+          "\teg: $XDG_DATA_HOME/.fex-emu/ThunkConfigs/<ThunkConfig name>"
         ]
       },
       "Env": {
@@ -207,6 +214,14 @@
           "Makes TSO operations even more strict.",
           "Forces vector loadstores to also become atomic."
         ]
+      },
+      "StallProcess": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Forces a process to stall out on initialization",
+          "Useful for a process that keeps restarting and doesn't work"
+        ]
       }
     },
     "Misc": {

External/FEXCore/Source/Interface/Context/Context.cpp

@@ -2,6 +2,7 @@
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Core.h"
 #include "Interface/Core/OpcodeDispatcher.h"
+#include "Interface/Core/X86Tables/X86Tables.h"
 
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CoreState.h>

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64.cpp

@@ -1,4 +1,5 @@
 #include "Interface/Core/ArchHelpers/Arm64.h"
+#include "Interface/Core/ArchHelpers/MContext.h"
 
 #include <FEXCore/Utils/LogManager.h>
 
@@ -8,6 +9,27 @@
 #include <signal.h>
 
 namespace FEXCore::ArchHelpers::Arm64 {
+static __uint128_t LoadAcquire128(uint64_t Addr) {
+  __uint128_t Result{};
+  uint64_t Lower;
+  uint64_t Upper;
+  // This specifically avoids using std::atomic<__uint128_t>
+  // std::atomic helper does a ldaxp + stxp pair that crashes when the page is only mapped readable
+  __asm volatile(
+R"(
+  ldaxp %[ResultLower], %[ResultUpper], [%[Addr]];
+  clrex;
+)"
+  : [ResultLower] "=r" (Lower)
+  , [ResultUpper] "=r" (Upper)
+  : [Addr] "r" (Addr)
+  : "memory");
+  Result = Upper;
+  Result <<= 64;
+  Result |= Lower;
+  return Result;
+}
+
 static uint64_t LoadAcquire64(uint64_t Addr) {
   std::atomic<uint64_t> *Atom = reinterpret_cast<std::atomic<uint64_t>*>(Addr);
   return Atom->load(std::memory_order_acquire);
@@ -226,6 +248,175 @@ bool HandleCASPAL(void *_ucontext, void *_info, uint32_t Instr) {
   return false;
 }
 
+uint16_t DoLoad16(uint64_t Addr) {
+  uint64_t AlignmentMask = 0b1111;
+  if ((Addr & AlignmentMask) == 15) {
+    // Address crosses over 16byte or 64byte threshold
+    // Needs two loads
+    uint64_t AddrUpper = Addr + 1;
+    uint8_t ActualUpper{};
+    uint8_t ActualLower{};
+    // Careful ordering here
+    ActualUpper = LoadAcquire8(AddrUpper);
+    ActualLower = LoadAcquire8(Addr);
+
+    uint16_t Result = ActualUpper;
+    Result <<= 8;
+    Result |= ActualLower;
+    return Result;
+  }
+  else {
+    AlignmentMask = 0b111;
+    if ((Addr & AlignmentMask) == 7) {
+      // Crosses 8byte boundary
+      // Needs 128bit load
+      // Fits within a 16byte region
+      uint64_t Alignment = Addr & 0b1111;
+      Addr &= ~0b1111ULL;
+
+      __uint128_t TmpResult = LoadAcquire128(Addr);
+
+      // Zexts the result
+      uint16_t Result = TmpResult >> (Alignment * 8);
+      return Result;
+    }
+    else {
+      AlignmentMask = 0b11;
+      if ((Addr & AlignmentMask) == 3) {
+        // Crosses 4byte boundary
+        // Needs 64bit Load
+        uint64_t Alignment = Addr & AlignmentMask;
+        Addr &= ~AlignmentMask;
+
+        std::atomic<uint64_t> *Atomic = reinterpret_cast<std::atomic<uint64_t>*>(Addr);
+        uint64_t TmpResult = Atomic->load();
+
+        // Zexts the result
+        uint16_t Result = TmpResult >> (Alignment * 8);
+        return Result;
+      }
+      else {
+        // Fits within 4byte boundary
+        // Only needs 32bit Load
+        // Only alignment offset will be 1 here
+        uint64_t Alignment = Addr & AlignmentMask;
+        Addr &= ~AlignmentMask;
+
+        std::atomic<uint32_t> *Atomic = reinterpret_cast<std::atomic<uint32_t>*>(Addr);
+        uint32_t TmpResult = Atomic->load();
+
+        // Zexts the result
+        uint16_t Result = TmpResult >> (Alignment * 8);
+        return Result;
+      }
+    }
+  }
+}
+
+uint32_t DoLoad32(uint64_t Addr) {
+  uint64_t AlignmentMask = 0b1111;
+  if ((Addr & AlignmentMask) > 12) {
+    // Address crosses over 16byte threshold
+    // Needs dual 32bit load
+    uint64_t Alignment = Addr & 0b11;
+    Addr &= ~0b11ULL;
+
+    uint64_t AddrUpper = Addr + 4;
+
+    // Careful ordering here
+    uint32_t ActualUpper = LoadAcquire32(AddrUpper);
+    uint32_t ActualLower = LoadAcquire32(Addr);
+
+    uint64_t Result = ActualUpper;
+    Result <<= 32;
+    Result |= ActualLower;
+    return Result >> (Alignment * 8);
+  }
+  else {
+    AlignmentMask = 0b111;
+    if ((Addr & AlignmentMask) >= 5) {
+      // Crosses 8byte boundary
+      // Needs 128bit load
+      // Fits within a 16byte region
+      uint64_t Alignment = Addr & 0b1111;
+      Addr &= ~0b1111ULL;
+
+      __uint128_t TmpResult = LoadAcquire128(Addr);
+
+      return TmpResult >> (Alignment * 8);
+    }
+    else {
+      // Fits within 8byte boundary
+      // Only needs 64bit CAS
+      // Alignments can be [1,5)
+      uint64_t Alignment = Addr & AlignmentMask;
+      Addr &= ~AlignmentMask;
+
+      std::atomic<uint64_t> *Atomic = reinterpret_cast<std::atomic<uint64_t>*>(Addr);
+      uint64_t TmpResult = Atomic->load();
+
+      return TmpResult >> (Alignment * 8);
+    }
+  }
+}
+
+uint64_t DoLoad64(uint64_t Addr) {
+  uint64_t AlignmentMask = 0b1111;
+  if ((Addr & AlignmentMask) > 8) {
+    uint64_t Alignment = Addr & 0b111;
+    Addr &= ~0b111ULL;
+    uint64_t AddrUpper = Addr + 8;
+
+    // Crosses a 16byte boundary
+    // Needs two 8 byte loads
+    uint64_t ActualUpper{};
+    uint64_t ActualLower{};
+    // Careful ordering here
+    ActualUpper = LoadAcquire64(AddrUpper);
+    ActualLower = LoadAcquire64(Addr);
+
+    __uint128_t Result = ActualUpper;
+    Result <<= 64;
+    Result |= ActualLower;
+    return Result >> (Alignment * 8);
+  }
+  else {
+    // Fits within a 16byte region
+    uint64_t Alignment = Addr & AlignmentMask;
+    Addr &= ~AlignmentMask;
+    __uint128_t TmpResult = LoadAcquire128(Addr);
+    uint64_t Result = TmpResult >> (Alignment * 8);
+    return Result;
+  }
+}
+
+std::pair<uint64_t, uint64_t> DoLoad128(uint64_t Addr) {
+  // Any misalignment here means we cross a 16byte boundary
+  // So we need two 128bit loads
+  uint64_t Alignment = Addr & 0b1111;
+  Addr &= ~0b1111ULL;
+  uint64_t AddrUpper = Addr + 16;
+
+  union AlignedData {
+    struct {
+      __uint128_t Lower;
+      __uint128_t Upper;
+    } Large;
+    struct {
+      uint8_t Data[32];
+    } Bytes;
+  };
+
+  AlignedData *Data = reinterpret_cast<AlignedData*>(alloca(sizeof(AlignedData)));
+  Data->Large.Upper = LoadAcquire128(AddrUpper);
+  Data->Large.Lower = LoadAcquire128(Addr);
+
+  uint64_t ResultLower{}, ResultUpper{};
+  memcpy(&ResultLower, &Data->Bytes.Data[Alignment], sizeof(uint64_t));
+  memcpy(&ResultUpper, &Data->Bytes.Data[Alignment + sizeof(uint64_t)], sizeof(uint64_t));
+  return {ResultLower, ResultUpper};
+}
+
 template <typename T>
 using CASExpectedFn = T (*)(T Src, T Expected);
 template <typename T>
@@ -1202,4 +1393,499 @@ bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr) {
   return false;
 }
 
+bool HandleAtomicLoad(void *_ucontext, void *_info, uint32_t Instr) {
+  mcontext_t* mcontext = &reinterpret_cast<ucontext_t*>(_ucontext)->uc_mcontext;
+  siginfo_t* info = reinterpret_cast<siginfo_t*>(_info);
+
+  if (info->si_code != BUS_ADRALN) {
+    // This only handles alignment problems
+    return false;
+  }
+  uint32_t Size = 1 << (Instr >> 30);
+
+  uint32_t ResultReg = Instr & 0b11111;
+  uint32_t AddressReg = (Instr >> 5) & 0b11111;
+
+  uint64_t Addr = mcontext->regs[AddressReg];
+
+  if (Size == 2) {
+    auto Res = DoLoad16(Addr);
+    // We set the result register if it isn't a zero register
+    if (ResultReg != 31) {
+      mcontext->regs[ResultReg] = Res;
+    }
+    return true;
+  }
+  else if (Size == 4) {
+    auto Res = DoLoad32(Addr);
+    // We set the result register if it isn't a zero register
+    if (ResultReg != 31) {
+      mcontext->regs[ResultReg] = Res;
+    }
+    return true;
+  }
+  else if (Size == 8) {
+    auto Res = DoLoad64(Addr);
+    // We set the result register if it isn't a zero register
+    if (ResultReg != 31) {
+      mcontext->regs[ResultReg] = Res;
+    }
+    return true;
+  }
+
+  return false;
+}
+
+bool HandleAtomicStore(void *_ucontext, void *_info, uint32_t Instr) {
+  mcontext_t* mcontext = &reinterpret_cast<ucontext_t*>(_ucontext)->uc_mcontext;
+  siginfo_t* info = reinterpret_cast<siginfo_t*>(_info);
+
+  if (info->si_code != BUS_ADRALN) {
+    // This only handles alignment problems
+    return false;
+  }
+  uint32_t Size = 1 << (Instr >> 30);
+
+  uint32_t DataReg = Instr & 0x1F;
+  uint32_t AddressReg = (Instr >> 5) & 0b11111;
+
+  uint64_t Addr = mcontext->regs[AddressReg];
+
+  constexpr bool DoRetry = false;
+  if (Size == 2) {
+    DoCAS16<DoRetry>(
+      mcontext->regs[DataReg],
+      0, // Unused
+      Addr,
+      [](uint16_t SrcVal, uint16_t) -> uint16_t {
+        // Expected is just src
+        return SrcVal;
+      },
+      [](uint16_t, uint16_t Desired) -> uint16_t {
+        // Desired is just Desired
+        return Desired;
+      });
+    return true;
+  }
+  else if (Size == 4) {
+    DoCAS32<DoRetry>(
+      mcontext->regs[DataReg],
+      0, // Unused
+      Addr,
+      [](uint32_t SrcVal, uint32_t) -> uint32_t {
+        // Expected is just src
+        return SrcVal;
+      },
+      [](uint32_t, uint32_t Desired) -> uint32_t {
+        // Desired is just Desired
+        return Desired;
+      });
+    return true;
+  }
+  else if (Size == 8) {
+    DoCAS64<DoRetry>(
+      mcontext->regs[DataReg],
+      0, // Unused
+      Addr,
+      [](uint64_t SrcVal, uint64_t) -> uint64_t {
+        // Expected is just src
+        return SrcVal;
+      },
+      [](uint64_t, uint64_t Desired) -> uint64_t {
+        // Desired is just Desired
+        return Desired;
+      });
+    return true;
+  }
+
+  return false;
+}
+
+bool HandleAtomicLoad128(void *_ucontext, void *_info, uint32_t Instr) {
+  mcontext_t* mcontext = &reinterpret_cast<ucontext_t*>(_ucontext)->uc_mcontext;
+  siginfo_t* info = reinterpret_cast<siginfo_t*>(_info);
+
+  if (info->si_code != BUS_ADRALN) {
+    // This only handles alignment problems
+    return false;
+  }
+  uint32_t ResultReg = Instr & 0b11111;
+  uint32_t ResultReg2 = (Instr >> 10) & 0x1F;
+  uint32_t AddressReg = (Instr >> 5) & 0b11111;
+
+  uint64_t Addr = mcontext->regs[AddressReg];
+
+  auto Res = DoLoad128(Addr);
+  // We set the result register if it isn't a zero register
+  if (ResultReg != 31) {
+    mcontext->regs[ResultReg] = std::get<0>(Res);
+  }
+  if (ResultReg2 != 31) {
+    mcontext->regs[ResultReg2] = std::get<1>(Res);
+  }
+
+  return true;
+}
+
+uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
+  mcontext_t* mcontext = &reinterpret_cast<ucontext_t*>(_ucontext)->uc_mcontext;
+  siginfo_t* info = reinterpret_cast<siginfo_t*>(_info);
+
+  if (info->si_code != BUS_ADRALN) {
+    // This only handles alignment problems
+    return 0;
+  }
+
+  uint32_t *PC = (uint32_t*)ArchHelpers::Context::GetPc(_ucontext);
+  uint32_t Instr = PC[0];
+
+  // Atomic Add
+  // [1] ldaxrb(TMP2.W(), MemOperand(MemSrc));
+  // [2] add(TMP2.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+  // [3] stlxrb(TMP2.W(), TMP2.W(), MemOperand(MemSrc));
+  // [4] cbnz(TMP2.W(), &LoopTop);
+  //
+  // Atomic Fetch Add
+  // [1] ldaxrb(TMP2.W(), MemOperand(MemSrc));
+  // [2] add(TMP3.W(), TMP2.W(), GetReg<RA_32>(Op->Header.Args[1].ID()));
+  // [3] stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+  // [4] cbnz(TMP4.W(), &LoopTop);
+  // [5] mov(GetReg<RA_32>(Node), TMP2.W());
+  //
+  // Atomic Swap
+  //
+  // [1] ldaxrb(TMP2.W(), MemOperand(MemSrc));
+  // [2] stlxrb(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
+  // [3] cbnz(TMP4.W(), &LoopTop);
+  // [4] uxtb(GetReg<RA_64>(Node), TMP2.W());
+  //
+  // ASSUMPTIONS:
+  // - Both cases:
+  //   - The [2]ALU op: (Non NEG case)
+  //     - First source is from [1]ldaxr
+  //     - Second source is incoming value
+  //   - The [2]ALU op: (NEG case)
+  //     - First source is zero register
+  //     - The second source is the from [1]ldaxr
+  //   - No ALU op: (SWAP case)
+  //     - No DataSourceRegister
+  //
+  // - In Atomic case (non-fetch)
+  //   - The [3]stlxr instruction status + memory register are the SAME register
+  //
+  // - In Atomic FETCH case
+  //   - The [3]stlxr instruction's status + memory register are never the same register
+  //   - The [5]mov instruction source is always the destination register from [1] ldaxr*
+  uint32_t ResultReg = GetRdReg(Instr);
+  uint32_t AddressReg = GetRnReg(Instr);
+  uint64_t Addr = mcontext->regs[AddressReg];
+
+  size_t NumInstructionsToSkip = 0;
+
+  // Are we an Atomic op or AtomicFetch?
+  bool AtomicFetch = false;
+
+  // This is the register that is the incoming source to the ALU operation
+  // <DataResultReg> = <Load Exclusive Value> <Op> <DataSourceReg>
+  // NEG case is special
+  // <DataResultReg> = Zero <Sub> <Load Exclusive Value>
+  // DataSourceRegister must always be the Rm register
+  uint32_t DataSourceReg {};
+  ExclusiveAtomicPairType AtomicOp {ExclusiveAtomicPairType::TYPE_SWAP};
+
+  // Scan forward at most five instructions to find our instructions
+  for (size_t i = 1; i < 6; ++i) {
+    uint32_t NextInstr = PC[i];
+    if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::ADD_INST) {
+      AtomicOp = ExclusiveAtomicPairType::TYPE_ADD;
+      DataSourceReg = GetRmReg(NextInstr);
+    }
+    else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::SUB_INST) {
+      uint32_t RnReg = GetRnReg(NextInstr);
+      if (RnReg == REGISTER_MASK) {
+        // Zero reg means neg
+        AtomicOp = ExclusiveAtomicPairType::TYPE_NEG;
+      }
+      else {
+        AtomicOp = ExclusiveAtomicPairType::TYPE_SUB;
+      }
+      DataSourceReg = GetRmReg(NextInstr);
+    }
+    else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::AND_INST) {
+      AtomicOp = ExclusiveAtomicPairType::TYPE_AND;
+      DataSourceReg = GetRmReg(NextInstr);
+    }
+    else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::OR_INST) {
+      AtomicOp = ExclusiveAtomicPairType::TYPE_OR;
+      DataSourceReg = GetRmReg(NextInstr);
+    }
+    else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::EOR_INST) {
+      AtomicOp = ExclusiveAtomicPairType::TYPE_EOR;
+      DataSourceReg = GetRmReg(NextInstr);
+    }
+    else if ((NextInstr & FEXCore::ArchHelpers::Arm64::STLXR_MASK) == FEXCore::ArchHelpers::Arm64::STLXR_INST) {
+#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
+      // Just double check that the memory destination matches
+      uint32_t StoreAddressReg = GetRnReg(NextInstr);
+      LOGMAN_THROW_A(StoreAddressReg == AddressReg, "StoreExclusive memory register didn't match the store exclusive register");
+#endif
+      uint32_t StatusReg = GetRmReg(NextInstr);
+      uint32_t StoreResultReg = GetRdReg(NextInstr);
+      // We are an atomic fetch instruction if the data register isn't the status register
+      AtomicFetch = !(StatusReg == StoreResultReg);
+      if (AtomicOp == ExclusiveAtomicPairType::TYPE_SWAP) {
+        // In the case of swap we don't have an ALU op inbetween
+        // Source is directly in STLXR
+        DataSourceReg = StoreResultReg;
+      }
+    }
+    else if ((NextInstr & FEXCore::ArchHelpers::Arm64::CBNZ_MASK) == FEXCore::ArchHelpers::Arm64::CBNZ_INST) {
+      // Found the CBNZ, we want to skip to just after this instruction when done
+      NumInstructionsToSkip = i + 1;
+      // This is the last instruction we care about. Leave now
+      break;
+    }
+    else {
+      LogMan::Msg::A("Unknown instruction 0x%08x", NextInstr);
+    }
+  }
+
+  uint32_t Size = 1 << (Instr >> 30);
+
+  constexpr bool DoRetry = true;
+  if (Size == 2) {
+    using AtomicType = uint16_t;
+    auto NOPExpected = [](AtomicType SrcVal, AtomicType) -> AtomicType {
+      return SrcVal;
+    };
+
+    auto ADDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal + Desired;
+    };
+
+    auto SUBDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal - Desired;
+    };
+
+    auto ANDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal & Desired;
+    };
+
+    auto ORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal | Desired;
+    };
+
+    auto EORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal ^ Desired;
+    };
+
+    auto NEGDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return -SrcVal;
+    };
+
+    auto SWAPDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return Desired;
+    };
+
+    CASDesiredFn<AtomicType> DesiredFunction{};
+
+    switch (AtomicOp) {
+      case ExclusiveAtomicPairType::TYPE_SWAP:
+        DesiredFunction = SWAPDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_ADD:
+        DesiredFunction = ADDDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_SUB:
+        DesiredFunction = SUBDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_AND:
+        DesiredFunction = ANDDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_OR:
+        DesiredFunction = ORDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_EOR:
+        DesiredFunction = EORDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_NEG:
+        DesiredFunction = NEGDesired;
+        break;
+      default:
+        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x", AtomicOp);
+        return false;
+        break;
+    }
+
+    auto Res = DoCAS16<DoRetry>(
+      mcontext->regs[DataSourceReg],
+      0, // Unused
+      Addr,
+      NOPExpected,
+      DesiredFunction);
+
+    if (AtomicFetch && ResultReg != 31) {
+      // On atomic fetch then we store the resulting value back in to the loadacquire destination register
+      // We want the memory value BEFORE the ALU op
+      mcontext->regs[ResultReg] = Res;
+    }
+  }
+  else if (Size == 4) {
+    using AtomicType = uint32_t;
+    auto NOPExpected = [](AtomicType SrcVal, AtomicType) -> AtomicType {
+      return SrcVal;
+    };
+
+    auto ADDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal + Desired;
+    };
+
+    auto SUBDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal - Desired;
+    };
+
+    auto ANDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal & Desired;
+    };
+
+    auto ORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal | Desired;
+    };
+
+    auto EORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal ^ Desired;
+    };
+
+    auto NEGDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return -SrcVal;
+    };
+
+    auto SWAPDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return Desired;
+    };
+
+    CASDesiredFn<AtomicType> DesiredFunction{};
+
+    switch (AtomicOp) {
+      case ExclusiveAtomicPairType::TYPE_SWAP:
+        DesiredFunction = SWAPDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_ADD:
+        DesiredFunction = ADDDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_SUB:
+        DesiredFunction = SUBDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_AND:
+        DesiredFunction = ANDDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_OR:
+        DesiredFunction = ORDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_EOR:
+        DesiredFunction = EORDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_NEG:
+        DesiredFunction = NEGDesired;
+        break;
+      default:
+        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x", AtomicOp);
+        return false;
+        break;
+    }
+
+    auto Res = DoCAS32<DoRetry>(
+      mcontext->regs[DataSourceReg],
+      0, // Unused
+      Addr,
+      NOPExpected,
+      DesiredFunction);
+
+    if (AtomicFetch && ResultReg != 31) {
+      // On atomic fetch then we store the resulting value back in to the loadacquire destination register
+      // We want the memory value BEFORE the ALU op
+      mcontext->regs[ResultReg] = Res;
+    }
+  }
+  else if (Size == 8) {
+    using AtomicType = uint64_t;
+    auto NOPExpected = [](AtomicType SrcVal, AtomicType) -> AtomicType {
+      return SrcVal;
+    };
+
+    auto ADDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal + Desired;
+    };
+
+    auto SUBDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal - Desired;
+    };
+
+    auto ANDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal & Desired;
+    };
+
+    auto ORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal | Desired;
+    };
+
+    auto EORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return SrcVal ^ Desired;
+    };
+
+    auto NEGDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return -SrcVal;
+    };
+
+    auto SWAPDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
+      return Desired;
+    };
+
+    CASDesiredFn<AtomicType> DesiredFunction{};
+
+    switch (AtomicOp) {
+      case ExclusiveAtomicPairType::TYPE_SWAP:
+        DesiredFunction = SWAPDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_ADD:
+        DesiredFunction = ADDDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_SUB:
+        DesiredFunction = SUBDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_AND:
+        DesiredFunction = ANDDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_OR:
+        DesiredFunction = ORDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_EOR:
+        DesiredFunction = EORDesired;
+        break;
+      case ExclusiveAtomicPairType::TYPE_NEG:
+        DesiredFunction = NEGDesired;
+        break;
+      default:
+        LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x", AtomicOp);
+        return false;
+        break;
+    }
+
+    auto Res = DoCAS64<DoRetry>(
+      mcontext->regs[DataSourceReg],
+      0, // Unused
+      Addr,
+      NOPExpected,
+      DesiredFunction);
+    if (AtomicFetch && ResultReg != 31) {
+      // On atomic fetch then we store the resulting value back in to the loadacquire destination register
+      // We want the memory value BEFORE the ALU op
+      mcontext->regs[ResultReg] = Res;
+    }
+  }
+
+  // Multiply by 4 for number of bytes to skip
+  return NumInstructionsToSkip * 4;
+}
+
 }

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64.h

@@ -18,6 +18,31 @@ namespace FEXCore::ArchHelpers::Arm64 {
   constexpr uint32_t STLXP_MASK = 0xBF'E0'80'00;
   constexpr uint32_t STLXP_INST = 0x88'20'80'00;
 
+  constexpr uint32_t LDAXR_MASK = 0x3F'FF'FC'00;
+  constexpr uint32_t LDAXR_INST = 0x08'5F'FC'00;
+
+  constexpr uint32_t STLXR_MASK = 0x3F'E0'FC'00;
+  constexpr uint32_t STLXR_INST = 0x08'00'FC'00;
+
+  constexpr uint32_t CBNZ_MASK = 0x7F'00'00'00;
+  constexpr uint32_t CBNZ_INST = 0x35'00'00'00;
+
+  constexpr uint32_t ALU_OP_MASK = 0x7F'00'00'00;
+  constexpr uint32_t ADD_INST    = 0x0B'00'00'00;
+  constexpr uint32_t SUB_INST    = 0x4B'00'00'00;
+  constexpr uint32_t AND_INST    = 0x0A'00'00'00;
+  constexpr uint32_t OR_INST     = 0x2A'00'00'00;
+  constexpr uint32_t EOR_INST    = 0x4A'00'00'00;
+  enum ExclusiveAtomicPairType {
+    TYPE_SWAP,
+    TYPE_ADD,
+    TYPE_SUB,
+    TYPE_AND,
+    TYPE_OR,
+    TYPE_EOR,
+    TYPE_NEG, // This is just a sub with zero. Need to know the differences
+  };
+
   // Load ops are 4 bits
   // Acquire and release bits are independent on the instruction
   constexpr uint32_t ATOMIC_ADD_OP  = 0b0000;
@@ -30,6 +55,27 @@ namespace FEXCore::ArchHelpers::Arm64 {
   constexpr uint32_t ATOMIC_UMIN_OP = 0b0111;
   constexpr uint32_t ATOMIC_SWAP_OP = 0b1000;
 
+  constexpr uint32_t REGISTER_MASK = 0b11111;
+  constexpr uint32_t RD_OFFSET = 0;
+  constexpr uint32_t RN_OFFSET = 5;
+  constexpr uint32_t RM_OFFSET = 16;
+
+  inline uint32_t GetRdReg(uint32_t Instr) {
+    return (Instr >> RD_OFFSET) & REGISTER_MASK;
+  }
+
+  inline uint32_t GetRnReg(uint32_t Instr) {
+    return (Instr >> RN_OFFSET) & REGISTER_MASK;
+  }
+
+  inline uint32_t GetRmReg(uint32_t Instr) {
+    return (Instr >> RM_OFFSET) & REGISTER_MASK;
+  }
+
+  bool HandleAtomicLoad(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleAtomicStore(void *_ucontext, void *_info, uint32_t Instr);
+  bool HandleAtomicLoad128(void *_ucontext, void *_info, uint32_t Instr);
+  uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info);
   bool HandleCASPAL(void *_ucontext, void *_info, uint32_t Instr);
   bool HandleCASAL(void *_ucontext, void *_info, uint32_t Instr);
   bool HandleAtomicMemOp(void *_ucontext, void *_info, uint32_t Instr);

External/FEXCore/Source/Interface/Core/CPUID.cpp

@@ -96,7 +96,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
     (0 <<  5) | // VMX
     (0 <<  6) | // SMX
     (0 <<  7) | // Intel SpeedStep
-    (0 <<  8) | // Thermal Monitor 2
+    (1 <<  8) | // Thermal Monitor 2
     (1 <<  9) | // SSSE3
     (0 << 10) | // L1 context ID
     (0 << 11) | // Silicon debug
@@ -151,7 +151,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
     (1 << 26) | // SSE2
     (0 << 27) | // Self Snoop
     (1 << 28) | // Max APIC IDs reserved field is valid
-    (0 << 29) | // Thermal monitor
+    (1 << 29) | // Thermal monitor
     (0 << 30) | // Reserved
     (0 << 31);  // Pending break enable
   return Res;

External/FEXCore/Source/Interface/Core/CPUID.h

@@ -28,9 +28,6 @@ public:
     auto Handler = FunctionHandlers.find(Function);
 
     if (Handler == FunctionHandlers.end()) {
-      #ifndef NDEBUG
-        LogMan::Msg::E("Unhandled CPU ID function, 0x%x-0x%x", Function, Leaf);
-      #endif
       return Function_Reserved(Leaf);
     }
 

External/FEXCore/Source/Interface/Core/Core.cpp

@@ -33,7 +33,7 @@ $end_info$
 #include "Interface/HLE/Thunks/Thunks.h"
 #include "FEXCore/Utils/Allocator.h"
 
-#include <xxh3.h>
+#include <xxhash.h>
 #include <fstream>
 #include <unistd.h>
 #include <filesystem>
@@ -216,6 +216,7 @@ namespace FEXCore::Context {
     NewThreadState.flags[1] = 1;
     NewThreadState.flags[9] = 1;
     NewThreadState.FCW = 0x37F;
+    NewThreadState.FTW = 0xFFFF;
 
     FEXCore::Core::InternalThreadState *Thread = CreateThread(&NewThreadState, 0);
 
@@ -586,6 +587,12 @@ namespace FEXCore::Context {
 
     // Clean up dead stacks
     FEXCore::Threads::Thread::CleanupAfterFork();
+
+    if (LiveThread->CompileService) {
+      // If this live thread had a compile service then it no longer exists
+      // Erase the shared_ptr
+      LiveThread->CompileService.reset();
+    }
   }
 
   void Context::AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr, uint64_t Start, uint64_t Length) {

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp

@@ -1,3 +1,5 @@
+#include "Interface/Core/LookupCache.h"
+
 #include "Interface/Core/ArchHelpers/MContext.h"
 #include "Interface/Core/Dispatcher/Arm64Dispatcher.h"
 

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -54,6 +54,7 @@ void Dispatcher::StoreThreadState(int Signal, void *ucontext) {
 }
 
 void Dispatcher::RestoreThreadState(void *ucontext) {
+  LOGMAN_THROW_A(!SignalFrames.empty(), "Trying to restore a signal frame when we don't have any");
   uint64_t OldSP = SignalFrames.top();
   SignalFrames.pop();
   uintptr_t NewSP = OldSP;
@@ -105,7 +106,12 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
   // Don't need this offset if we aren't going to be putting siginfo in to it
   NewGuestSP -= 128;
 
-  if (GuestAction->sa_flags & SA_SIGINFO) {
+  // siginfo_t
+  siginfo_t *HostSigInfo = reinterpret_cast<siginfo_t*>(info);
+
+  if (GuestAction->sa_flags & SA_SIGINFO &&
+      !(HostSigInfo->si_code == SI_QUEUE || // If the siginfo comes from sigqueue or user then we don't need to check
+        HostSigInfo->si_code == SI_USER)) {
     if (SRAEnabled) {
       if (!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), false)) {
         LOGMAN_THROW_A(!IsAddressInJITCode(ArchHelpers::Context::GetPc(ucontext), true), "Signals in dispatcher have unsynchronized context");
@@ -117,7 +123,6 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
 
     // Setup ucontext a bit
     if (CTX->Config.Is64BitMode) {
-
       NewGuestSP -= sizeof(FEXCore::x86_64::ucontext_t);
       uint64_t UContextLocation = NewGuestSP;
 
@@ -133,6 +138,14 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
       // Pointer to where the fpreg memory is
       guest_uctx->uc_mcontext.fpregs = &guest_uctx->__fpregs_mem;
 
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_RIP] = Frame->State.rip;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_EFL] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CSGSFS] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_ERR] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_TRAPNO] = Signal;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_OLDMASK] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_CR2] = 0;
+
 #define COPY_REG(x) \
       guest_uctx->uc_mcontext.gregs[FEXCore::x86_64::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
       COPY_REG(R8);
@@ -159,6 +172,7 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
 
       // FCW store default
       guest_uctx->__fpregs_mem.fcw = Frame->State.FCW;
+      guest_uctx->__fpregs_mem.ftw = Frame->State.FTW;
 
       // Reconstruct FSW
       guest_uctx->__fpregs_mem.fsw =
@@ -173,8 +187,6 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
       guest_uctx->uc_stack.ss_sp = GuestStack->ss_sp;
       guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
 
-      // siginfo_t
-      siginfo_t *HostSigInfo = reinterpret_cast<siginfo_t*>(info);
       // aarch64 and x86_64 siginfo_t matches. We can just copy this over
       // SI_USER could also potentially have random data in it, needs to be bit perfect
       // For guest faults we don't have a real way to reconstruct state to a real guest RIP
@@ -186,12 +198,68 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
     else {
       // XXX: 32bit Support
       NewGuestSP -= sizeof(FEXCore::x86::ucontext_t);
-      uint64_t UContextLocation = 0; // NewGuestSP;
+      uint64_t UContextLocation = NewGuestSP;
       NewGuestSP -= sizeof(FEXCore::x86::siginfo_t);
       uint64_t SigInfoLocation = NewGuestSP;
 
+      FEXCore::x86::ucontext_t *guest_uctx = reinterpret_cast<FEXCore::x86::ucontext_t*>(UContextLocation);
       FEXCore::x86::siginfo_t *guest_siginfo = reinterpret_cast<FEXCore::x86::siginfo_t*>(SigInfoLocation);
-      siginfo_t *HostSigInfo = reinterpret_cast<siginfo_t*>(info);
+
+      // We have extended float information
+      guest_uctx->uc_flags |= FEXCore::x86::UC_FP_XSTATE;
+
+      // Pointer to where the fpreg memory is
+      guest_uctx->uc_mcontext.fpregs = static_cast<uint32_t>(reinterpret_cast<uint64_t>(&guest_uctx->__fpregs_mem));
+
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS] = Frame->State.gs;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_FS] = Frame->State.fs;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ES] = Frame->State.es;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_DS] = Frame->State.ds;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_TRAPNO] = Signal;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_ERR] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EIP] = Frame->State.rip;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_CS] = Frame->State.cs;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_EFL] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_UESP] = 0;
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS] = Frame->State.ss;
+
+#define COPY_REG(x) \
+      guest_uctx->uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x] = Frame->State.gregs[X86State::REG_##x];
+      COPY_REG(RDI);
+      COPY_REG(RSI);
+      COPY_REG(RBP);
+      COPY_REG(RBX);
+      COPY_REG(RDX);
+      COPY_REG(RAX);
+      COPY_REG(RCX);
+      COPY_REG(RSP);
+#undef COPY_REG
+
+      // Copy float registers
+      memcpy(guest_uctx->__fpregs_mem._st, Frame->State.mm, sizeof(Frame->State.mm));
+      if (0) {
+        // XXX: Handle XMM
+        // memcpy(guest_uctx->__fpregs_mem._xmm, Frame->State.xmm, sizeof(Frame->State.xmm));
+        guest_uctx->__fpregs_mem.status = FEXCore::x86::fpstate_magic::MAGIC_XFPSTATE;
+      }
+      else {
+        guest_uctx->__fpregs_mem.status = FEXCore::x86::fpstate_magic::MAGIC_FPU;
+      }
+      // FCW store default
+      guest_uctx->__fpregs_mem.fcw = Frame->State.FCW;
+      guest_uctx->__fpregs_mem.ftw = Frame->State.FTW;
+      // Reconstruct FSW
+      guest_uctx->__fpregs_mem.fsw =
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_TOP_LOC] << 11) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C0_LOC] << 8) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C1_LOC] << 9) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C2_LOC] << 10) |
+        (Frame->State.flags[FEXCore::X86State::X87FLAG_C3_LOC] << 14);
+
+      // Copy over signal stack information
+      guest_uctx->uc_stack.ss_flags = GuestStack->ss_flags;
+      guest_uctx->uc_stack.ss_sp = static_cast<uint32_t>(reinterpret_cast<uint64_t>(GuestStack->ss_sp));
+      guest_uctx->uc_stack.ss_size = GuestStack->ss_size;
 
       // These three elements are in every siginfo
       guest_siginfo->si_signo = HostSigInfo->si_signo;
@@ -213,9 +281,8 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
           guest_siginfo->_sifields._sigchld.stime = HostSigInfo->si_stime;
           break;
       default:
-        LogMan::Msg::D("Unhandled siginfo_t signal: %d", Signal);
         // Hope for the best, most things just copy over
-        memcpy(guest_siginfo, info, sizeof(siginfo_t));
+        memcpy(&guest_siginfo->_sifields, &HostSigInfo->_sifields, sizeof(siginfo_t));
         break;
       }
 
@@ -223,11 +290,18 @@ bool Dispatcher::HandleGuestSignal(int Signal, void *info, void *ucontext, Guest
       *(uint32_t*)NewGuestSP = UContextLocation;
       NewGuestSP -= 4;
       *(uint32_t*)NewGuestSP = SigInfoLocation;
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = Signal;
     }
 
     Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.sigaction);
   }
   else {
+    if (!CTX->Config.Is64BitMode) {
+      NewGuestSP -= 4;
+      *(uint32_t*)NewGuestSP = Signal;
+    }
+
     Frame->State.rip = reinterpret_cast<uint64_t>(GuestAction->sigaction_handler.handler);
   }
 

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp

@@ -1,3 +1,5 @@
+#include "Interface/Core/LookupCache.h"
+
 #include "Interface/Core/Dispatcher/X86Dispatcher.h"
 
 #include "Interface/Core/Interpreter/InterpreterClass.h"
@@ -12,7 +14,9 @@ static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
 
 X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config)
   : Dispatcher(ctx, Thread)
-  , Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE, nullptr, this) {
+  , Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE,
+      FEXCore::Allocator::mmap(nullptr, MAX_DISPATCHER_CODE_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0),
+      nullptr) {
 
   using namespace Xbyak;
   using namespace Xbyak::util;
@@ -298,7 +302,7 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::Inte
 }
 
 X86Dispatcher::~X86Dispatcher() {
-
+  FEXCore::Allocator::munmap(top_, MAX_DISPATCHER_CODE_SIZE);
 }
 
 #ifdef _M_X86_64

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.h

@@ -9,19 +9,11 @@
 
 namespace FEXCore::CPU {
 
-class X86Dispatcher final : public Dispatcher, public Xbyak::CodeGenerator, public Xbyak::Allocator {
+class X86Dispatcher final : public Dispatcher, public Xbyak::CodeGenerator {
   public:
     X86Dispatcher(FEXCore::Context::Context *ctx, FEXCore::Core::InternalThreadState *Thread, DispatcherConfig &config);
 
     virtual ~X86Dispatcher() override;
-
-    // Xbyak::Allocator
-    Xbyak::uint8 *alloc(size_t size) override { Size = size; return reinterpret_cast<uint8_t*>(FEXCore::Allocator::mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0)); }
-    void free(Xbyak::uint8 *p) override { FEXCore::Allocator::munmap(p, Size); }
-    bool useProtect() const override { return false; }
-
-  private:
-    size_t Size{};
 };
 
 }

External/FEXCore/Source/Interface/Core/Frontend.cpp

@@ -16,8 +16,11 @@ $end_info$
 #include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <set>
+#include <sys/mman.h>
 
 namespace FEXCore::Frontend {
+#include "Interface/Core/VSyscall/VSyscall.inc"
+
 using namespace FEXCore::X86Tables;
 
 static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool HasREX, bool HasXMM, bool HasMM, uint8_t InvalidOffset = 16) {
@@ -121,8 +124,18 @@ static uint32_t MapModRMToReg(uint8_t REX, uint8_t bits, bool HighBits, bool Has
 }
 
 Decoder::Decoder(FEXCore::Context::Context *ctx)
-  : CTX {ctx} {
-  DecodedBuffer.resize(DefaultDecodedBufferSize);
+  : CTX {ctx}
+  , OSABI { ctx->SyscallHandler ? ctx->SyscallHandler->GetOSABI() : FEXCore::HLE::SyscallOSABI::OS_UNKNOWN } {
+  // Using mmap is a start-up time optimization
+  // Take advantage of page faulting to reduce startup time for minimal runtime cost
+  DecodedBuffer =
+    reinterpret_cast<FEXCore::X86Tables::DecodedInst *>(
+      FEXCore::Allocator::mmap(0, sizeof(FEXCore::X86Tables::DecodedInst) * DefaultDecodedBufferSize,
+      PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+}
+
+Decoder::~Decoder() {
+  FEXCore::Allocator::munmap(DecodedBuffer, sizeof(FEXCore::X86Tables::DecodedInst) * DefaultDecodedBufferSize);
 }
 
 uint8_t Decoder::ReadByte() {
@@ -214,28 +227,28 @@ void Decoder::DecodeModRM_16(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
-    {FEXCore::X86State::REG_RSI, 255},
-    {FEXCore::X86State::REG_RDI, 255},
-    {255, 255},
-    {FEXCore::X86State::REG_RBX, 255},
+    {FEXCore::X86State::REG_RSI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RDI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_INVALID, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_INVALID},
     // Mod = 0b01
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
-    {FEXCore::X86State::REG_RSI, 255},
-    {FEXCore::X86State::REG_RDI, 255},
-    {FEXCore::X86State::REG_RBP, 255},
-    {FEXCore::X86State::REG_RBX, 255},
+    {FEXCore::X86State::REG_RSI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RDI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_INVALID},
     // Mod = 0b10
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_RDI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RSI},
     {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_RDI},
-    {FEXCore::X86State::REG_RSI, 255},
-    {FEXCore::X86State::REG_RDI, 255},
-    {FEXCore::X86State::REG_RBP, 255},
-    {FEXCore::X86State::REG_RBX, 255},
+    {FEXCore::X86State::REG_RSI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RDI, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBP, FEXCore::X86State::REG_INVALID},
+    {FEXCore::X86State::REG_RBX, FEXCore::X86State::REG_INVALID},
   }};
 
   uint8_t LookupIndex = ModRM.mod << 3 | ModRM.rm;
@@ -929,7 +942,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
   }
 
   if (DecodeInst->Dest.IsGPR()) {
-    assert(DecodeInst->Dest.Data.GPR.GPR != 255);
+    assert(DecodeInst->Dest.Data.GPR.GPR != FEXCore::X86State::REG_INVALID);
   }
 
   return true;
@@ -1004,6 +1017,25 @@ void Decoder::BranchTargetInMultiblockRange() {
   }
 }
 
+const uint8_t *Decoder::AdjustAddrForSpecialRegion(uint8_t const* _InstStream, uint64_t EntryPoint, uint64_t RIP) {
+  constexpr uint64_t VSyscall_Base = 0xFFFF'FFFF'FF60'0000ULL;
+  constexpr uint64_t VSyscall_End = VSyscall_Base + 0x1000;
+
+  if (OSABI == FEXCore::HLE::SyscallOSABI::OS_LINUX64 &&
+      RIP >= VSyscall_Base &&
+      RIP < VSyscall_End) {
+    // VSyscall
+    // This doesn't exist on AArch64 and on x86_64 hosts this is emulated with faults to a region mapped with --xp permissions
+    // Offset     0: vgettimeofday
+    // Offset 0x400: vtime
+    // Offset 0x800: vgetcpu
+    uint64_t Offset = RIP - VSyscall_Base;
+    return VSyscallData + Offset;
+  }
+
+  return _InstStream - EntryPoint + RIP;
+}
+
 bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC) {
   Blocks.clear();
   BlocksToDecode.clear();
@@ -1047,7 +1079,7 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
     uint64_t BlockStartOffset = DecodedSize;
 
     // Do a bit of pointer math to figure out where we are in code
-    InstStream = _InstStream - EntryPoint + RIPToDecode;
+    InstStream = AdjustAddrForSpecialRegion(_InstStream, EntryPoint, RIPToDecode);
 
     while (1) {
       ErrorDuringDecoding = !DecodeInstruction(RIPToDecode + PCOffset);
@@ -1091,7 +1123,7 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
       }
 
       if (DecodedSize >= CTX->Config.MaxInstPerBlock ||
-          DecodedSize >= DecodedBuffer.size()) {
+          DecodedSize >= DefaultDecodedBufferSize) {
         break;
       }
 
@@ -1108,7 +1140,7 @@ bool Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC)
 
     // Copy over only the number of instructions we decoded
     CurrentBlockDecoding.NumInstructions = BlockNumberOfInstructions;
-    CurrentBlockDecoding.DecodedInstructions = &DecodedBuffer.at(BlockStartOffset);
+    CurrentBlockDecoding.DecodedInstructions = &DecodedBuffer[BlockStartOffset];
   }
 
 

External/FEXCore/Source/Interface/Core/Frontend.h

@@ -1,6 +1,8 @@
 #pragma once
 
 #include <FEXCore/Debug/X86Tables.h>
+#include <FEXCore/HLE/SyscallHandler.h>
+
 #include <array>
 #include <cstdint>
 #include <utility>
@@ -24,6 +26,7 @@ public:
   };
 
   Decoder(FEXCore::Context::Context *ctx);
+  ~Decoder();
   bool DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC);
 
   std::vector<DecodedBlocks> const *GetDecodedBlocks() const {
@@ -37,6 +40,7 @@ public:
   void SetExternalBranches(std::set<uint64_t> *v) { ExternalBranches = v; }
 private:
   FEXCore::Context::Context *CTX;
+  const FEXCore::HLE::SyscallOSABI OSABI{};
 
   bool DecodeInstruction(uint64_t PC);
 
@@ -50,7 +54,7 @@ private:
   bool NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op);
 
   static constexpr size_t DefaultDecodedBufferSize = 0x10000;
-  std::vector<FEXCore::X86Tables::DecodedInst> DecodedBuffer;
+  FEXCore::X86Tables::DecodedInst *DecodedBuffer{};
   size_t DecodedSize {};
 
   uint8_t const *InstStream;
@@ -83,5 +87,7 @@ private:
     &FEXCore::Frontend::Decoder::DecodeModRM_64,
     &FEXCore::Frontend::Decoder::DecodeModRM_16,
   };
+
+  const uint8_t *AdjustAddrForSpecialRegion(uint8_t const* _InstStream, uint64_t EntryPoint, uint64_t RIP);
 };
 }

External/FEXCore/Source/Interface/Core/GdbServer.cpp

@@ -939,7 +939,7 @@ void GdbServer::GdbServerLoop() {
 
     {
         std::lock_guard lk(sendMutex);
-        CommsStream.release();
+        CommsStream.reset();
     }
   }
 }

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterClass.h

@@ -1,6 +1,5 @@
 #pragma once
 
-#include "Interface/Core/LookupCache.h"
 #include "Interface/Core/InternalThreadState.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp

@@ -78,6 +78,18 @@ bool InterpreterCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
         return false;
       }
     }
+    else if ((Instr & FEXCore::ArchHelpers::Arm64::LDAXR_MASK) == FEXCore::ArchHelpers::Arm64::LDAXR_INST) { // LDAXR*
+      uint64_t BytesToSkip = FEXCore::ArchHelpers::Arm64::HandleAtomicLoadstoreExclusive(ucontext, info);
+      if (BytesToSkip) {
+        // Skip this instruction now
+        ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + BytesToSkip);
+        return true;
+      }
+      else {
+        LogMan::Msg::E("Unhandled JIT SIGBUS LDAXR: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
+        return false;
+      }
+    }
   }
   return false;
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp

@@ -46,7 +46,7 @@ DEF_OP(TruncElementPair) {
       mov(Dst.second, Src.second);
       break;
     }
-    default: LOGMAN_MSG_A("Unhandled Truncation size: %d", Op->Size); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", Op->Size); break;
   }
 }
 
@@ -95,7 +95,7 @@ DEF_OP(Add) {
       case 8:
         add(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), Const);
         break;
-      default: LOGMAN_MSG_A("Unsupported Add size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Add size: {}", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -105,7 +105,7 @@ DEF_OP(Add) {
       case 8:
         add(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
         break;
-      default: LOGMAN_MSG_A("Unsupported Add size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Add size: {}", OpSize);
     }
   }
 }
@@ -121,7 +121,7 @@ DEF_OP(Sub) {
       case 8:
         sub(GRS(Node), GRS(Op->Header.Args[0].ID()), Const);
         break;
-      default: LOGMAN_MSG_A("Unsupported Sub size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Sub size: {}", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -131,7 +131,7 @@ DEF_OP(Sub) {
       case 8:
         sub(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
         break;
-      default: LOGMAN_MSG_A("Unsupported Sub size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported Sub size: {}", OpSize);
     }
   }
 
@@ -147,7 +147,7 @@ DEF_OP(Neg) {
     case 8:
       neg(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LOGMAN_MSG_A("Unsupported Not size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported Neg size: {}", OpSize);
   }
 }
 
@@ -163,7 +163,7 @@ DEF_OP(Mul) {
     case 8:
       mul(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Mul size: %d", OpSize);
   }
 }
 
@@ -179,7 +179,7 @@ DEF_OP(UMul) {
     case 8:
       mul(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown UMul size: {}", OpSize);
   }
 }
 
@@ -216,7 +216,7 @@ DEF_OP(Div) {
       sdiv(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
     }
-    default: LOGMAN_MSG_A("Unknown DIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown DIV Size: {}", Size); break;
   }
 }
 
@@ -243,7 +243,7 @@ DEF_OP(UDiv) {
       udiv(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown UDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown UDIV Size: {}", Size); break;
   }
 }
 
@@ -290,7 +290,7 @@ DEF_OP(Rem) {
       msub(GetReg<RA_64>(Node), TMP1, Divisor, Dividend);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown REM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown REM Size: {}", OpSize); break;
   }
 }
 
@@ -332,7 +332,7 @@ DEF_OP(URem) {
       msub(GetReg<RA_64>(Node), TMP1, Divisor, Dividend);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown UREM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown UREM Size: {}", OpSize); break;
   }
 }
 
@@ -349,7 +349,7 @@ DEF_OP(MulH) {
     case 8:
       smulh(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Sext size: {}", OpSize);
   }
 }
 
@@ -366,7 +366,7 @@ DEF_OP(UMulH) {
     case 8:
       umulh(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()), GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Sext size: {}", OpSize);
   }
 }
 
@@ -462,7 +462,7 @@ DEF_OP(Ror) {
       break;
       }
 
-      default: LOGMAN_MSG_A("Unhandled ROR size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unhandled ROR size: {}", OpSize);
     }
   } else {
     switch (OpSize) {
@@ -475,7 +475,7 @@ DEF_OP(Ror) {
       break;
       }
 
-      default: LOGMAN_MSG_A("Unhandled ROR size: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unhandled ROR size: {}", OpSize);
     }
   }
 }
@@ -494,7 +494,7 @@ DEF_OP(Extr) {
     break;
     }
 
-    default: LOGMAN_MSG_A("Unhandled EXTR size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unhandled EXTR size: {}", OpSize);
   }
 }
 
@@ -539,7 +539,7 @@ DEF_OP(LDiv) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown LDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LDIV Size: {}", Size); break;
   }
 }
 
@@ -582,7 +582,7 @@ DEF_OP(LUDiv) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown LUDIV Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUDIV Size: {}", Size); break;
   }
 }
 
@@ -635,7 +635,7 @@ DEF_OP(LRem) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown LREM Size: %d", Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LREM Size: {}", Size); break;
   }
 }
 
@@ -685,7 +685,7 @@ DEF_OP(LURem) {
       mov(GetReg<RA_64>(Node), x0);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown LUREM Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUREM Size: {}", OpSize); break;
   }
 }
 
@@ -699,7 +699,7 @@ DEF_OP(Not) {
     case 8:
       mvn(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LOGMAN_MSG_A("Unsupported Not size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported Not size: {}", OpSize);
   }
 }
 
@@ -730,7 +730,7 @@ DEF_OP(Popcount) {
       // fmov has zero extended, unused bytes are zero
       addv(VTMP1.B(), VTMP1.V8B());
       break;
-    default: LOGMAN_MSG_A("Unsupported Popcount size: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported Popcount size: {}", OpSize);
   }
 
   auto Dst = GetReg<RA_32>(Node);
@@ -779,7 +779,7 @@ DEF_OP(FindMSB) {
       clz(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()));
       sub(Dst, TMP1, Dst);
       break;
-    default: LOGMAN_MSG_A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown FindMSB size: {}", OpSize); break;
   }
 }
 
@@ -800,7 +800,7 @@ DEF_OP(FindTrailingZeros) {
       rbit(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       clz(GetReg<RA_64>(Node), GetReg<RA_64>(Node));
       break;
-    default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown FindTrailingZeros size: {}", OpSize); break;
   }
 }
 
@@ -819,7 +819,7 @@ DEF_OP(CountLeadingZeroes) {
     case 8:
       clz(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown CountLeadingZeroes size: {}", OpSize); break;
   }
 }
 
@@ -837,7 +837,7 @@ DEF_OP(Rev) {
     case 8:
       rev(GetReg<RA_64>(Node), GetReg<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LOGMAN_MSG_A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown REV size: {}", OpSize); break;
   }
 }
 
@@ -859,14 +859,14 @@ DEF_OP(Bfi) {
       bfi(TMP1, GetReg<RA_64>(Op->Header.Args[1].ID()), Op->lsb, Op->Width);
       mov(GetReg<RA_64>(Node), TMP1);
       break;
-    default: LOGMAN_MSG_A("Unknown BFI size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown BFI size: {}", OpSize); break;
   }
 }
 
 DEF_OP(Bfe) {
   auto Op = IROp->C<IR::IROp_Bfe>();
-  LOGMAN_THROW_A(IROp->Size <= 8, "OpSize is too large for BFE: %d", IROp->Size);
-  LOGMAN_THROW_A(Op->Width != 0, "Invalid BFE width of 0");
+  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
+  LOGMAN_THROW_A_FMT(Op->Width != 0, "Invalid BFE width of 0");
 
   auto Dst = GetReg<RA_64>(Node);
   ubfx(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), Op->lsb, Op->Width);
@@ -880,7 +880,7 @@ DEF_OP(Sbfe) {
   if (OpSize == 8) {
     sbfx(Dst, GetReg<RA_64>(Op->Header.Args[0].ID()), Op->lsb, Op->Width);
   } else {
-    LogMan::Msg::D("Unimplemented Sbfe size");
+    LogMan::Msg::DFmt("Unimplemented Sbfe size");
   }
 }
 
@@ -911,7 +911,7 @@ Condition MapSelectCC(IR::CondClassType Cond) {
   case FEXCore::IR::COND_MI:
   case FEXCore::IR::COND_PL:
   default:
-  LOGMAN_MSG_A("Unsupported compare type");
+  LOGMAN_MSG_A_FMT("Unsupported compare type");
   return Condition::nv;
   }
 }
@@ -929,7 +929,7 @@ DEF_OP(Select) {
   } else if (IsFPR(Op->Cmp1.ID())) {
     fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
   } else {
-    LOGMAN_MSG_A("Select: Expected GPR or FPR");
+    LOGMAN_MSG_A_FMT("Select: Expected GPR or FPR");
   }
 
   auto cc = MapSelectCC(Op->Cond);
@@ -940,7 +940,7 @@ DEF_OP(Select) {
 
   if (is_const_true || is_const_false) {
     if (is_const_false != true || is_const_true != true || const_true != 1 || const_false != 0) {
-      LOGMAN_MSG_A("Select: Unsupported compare inline parameters");
+      LOGMAN_MSG_A_FMT("Select: Unsupported compare inline parameters");
     }
     cset(GRS(Node), cc);
   } else {
@@ -964,7 +964,7 @@ DEF_OP(VExtractToGPR) {
     case 8:
       umov(GetReg<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->Idx);
     break;
-    default:  LOGMAN_MSG_A("Unhandled ExtractElementSize: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled ExtractElementSize: {}", OpSize);
   }
 }
 
@@ -1027,7 +1027,7 @@ DEF_OP(FCmp) {
   bool set = false;
 
   if (Op->Flags & (1 << IR::FCMP_FLAG_EQ)) {
-    LOGMAN_THROW_A(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
+    LOGMAN_THROW_A_FMT(IR::FCMP_FLAG_EQ == 0, "IR::FCMP_FLAG_EQ must equal 0");
     // EQ or unordered
     cset(Dst, Condition::eq); // Z = 1
     csinc(Dst, Dst, xzr, Condition::vc); // IF !V ? Z : 1

External/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp

@@ -34,7 +34,7 @@ DEF_OP(CASPair) {
       mov(Dst.first, TMP3);
       mov(Dst.second, TMP4);
       break;
-    default: LOGMAN_MSG_A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
     }
   }
   else {
@@ -44,11 +44,15 @@ DEF_OP(CASPair) {
         aarch64::Label LoopNotExpected;
         aarch64::Label LoopExpected;
         bind(&LoopTop);
+        nop();
         ldaxp(TMP2.W(), TMP3.W(), MemOperand(MemSrc));
+        nop();
         cmp(TMP2.W(), Expected.first.W());
         ccmp(TMP3.W(), Expected.second.W(), NoFlag, Condition::eq);
         b(&LoopNotExpected, Condition::ne);
+        nop();
         stlxp(TMP2.W(), Desired.first.W(), Desired.second.W(), MemOperand(MemSrc));
+        nop();
         cbnz(TMP2.W(), &LoopTop);
         mov(Dst.first.W(), Expected.first.W());
         mov(Dst.second.W(), Expected.second.W());
@@ -69,11 +73,15 @@ DEF_OP(CASPair) {
         aarch64::Label LoopNotExpected;
         aarch64::Label LoopExpected;
         bind(&LoopTop);
+        nop();
         ldaxp(TMP2.X(), TMP3.X(), MemOperand(MemSrc));
+        nop();
         cmp(TMP2.X(), Expected.first.X());
         ccmp(TMP3.X(), Expected.second.X(), NoFlag, Condition::eq);
         b(&LoopNotExpected, Condition::ne);
+        nop();
         stlxp(TMP2.X(), Desired.first.X(), Desired.second.X(), MemOperand(MemSrc));
+        nop();
         cbnz(TMP2.X(), &LoopTop);
         mov(Dst.first.X(), Expected.first.X());
         mov(Dst.second.X(), Expected.second.X());
@@ -89,7 +97,7 @@ DEF_OP(CASPair) {
         bind(&LoopExpected);
         break;
       }
-      default: LOGMAN_MSG_A("Unsupported: %d", OpSize);
+      default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
     }
   }
 }
@@ -115,7 +123,7 @@ DEF_OP(CAS) {
     case 2: casalh(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
     case 4: casal(TMP2.W(), Desired.W(), MemOperand(MemSrc)); break;
     case 8: casal(TMP2.X(), Desired.X(), MemOperand(MemSrc)); break;
-    default: LOGMAN_MSG_A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
     }
     mov(GetReg<RA_64>(Node), TMP2);
   }
@@ -206,7 +214,7 @@ DEF_OP(CAS) {
 
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", OpSize);
     }
   }
 }
@@ -222,7 +230,7 @@ DEF_OP(AtomicAdd) {
     case 2: staddlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: staddl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: staddl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -264,7 +272,7 @@ DEF_OP(AtomicAdd) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -281,7 +289,7 @@ DEF_OP(AtomicSub) {
     case 2: staddlh(TMP2.W(), MemOperand(MemSrc)); break;
     case 4: staddl(TMP2.W(), MemOperand(MemSrc)); break;
     case 8: staddl(TMP2.X(), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -323,7 +331,7 @@ DEF_OP(AtomicSub) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -340,7 +348,7 @@ DEF_OP(AtomicAnd) {
     case 2: stclrlh(TMP2.W(), MemOperand(MemSrc)); break;
     case 4: stclrl(TMP2.W(), MemOperand(MemSrc)); break;
     case 8: stclrl(TMP2.X(), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -382,7 +390,7 @@ DEF_OP(AtomicAnd) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -398,7 +406,7 @@ DEF_OP(AtomicOr) {
     case 2: stsetlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: stsetl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: stsetl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -440,7 +448,7 @@ DEF_OP(AtomicOr) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -456,7 +464,7 @@ DEF_OP(AtomicXor) {
     case 2: steorlh(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 4: steorl(GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
     case 8: steorl(GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -498,7 +506,7 @@ DEF_OP(AtomicXor) {
         cbnz(TMP2, &LoopTop);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -515,36 +523,35 @@ DEF_OP(AtomicSwap) {
     case 2: swplh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: swpl(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: swpl(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
     // TMP2-TMP3
-    mov(TMP3, GetReg<RA_64>(Op->Header.Args[1].ID()));
     switch (Op->Size) {
       case 1: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxrb(TMP2.W(), MemOperand(MemSrc));
-        stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+        stlxrb(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4.W(), &LoopTop);
-        uxtb(GetReg<RA_64>(Node), TMP2.W());
+        uxtb(GetReg<RA_32>(Node), TMP2.W());
         break;
       }
       case 2: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxrh(TMP2.W(), MemOperand(MemSrc));
-        stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+        stlxrh(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4.W(), &LoopTop);
-        uxtw(GetReg<RA_64>(Node), TMP2.W());
+        uxtw(GetReg<RA_32>(Node), TMP2.W());
         break;
       }
       case 4: {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxr(TMP2.W(), MemOperand(MemSrc));
-        stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+        stlxr(TMP4.W(), GetReg<RA_32>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4.W(), &LoopTop);
         mov(GetReg<RA_32>(Node), TMP2.W());
         break;
@@ -553,12 +560,12 @@ DEF_OP(AtomicSwap) {
         aarch64::Label LoopTop;
         bind(&LoopTop);
         ldaxr(TMP2, MemOperand(MemSrc));
-        stlxr(TMP4, TMP3.X(), MemOperand(MemSrc));
+        stlxr(TMP4, GetReg<RA_64>(Op->Header.Args[1].ID()), MemOperand(MemSrc));
         cbnz(TMP4, &LoopTop);
         mov(GetReg<RA_64>(Node), TMP2.X());
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -573,7 +580,7 @@ DEF_OP(AtomicFetchAdd) {
     case 2: ldaddalh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldaddal(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldaddal(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -619,7 +626,7 @@ DEF_OP(AtomicFetchAdd) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -635,7 +642,7 @@ DEF_OP(AtomicFetchSub) {
     case 2: ldaddalh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldaddal(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldaddal(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -681,7 +688,7 @@ DEF_OP(AtomicFetchSub) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -697,7 +704,7 @@ DEF_OP(AtomicFetchAnd) {
     case 2: ldclralh(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldclral(TMP2.W(), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldclral(TMP2.X(), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -743,7 +750,7 @@ DEF_OP(AtomicFetchAnd) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -758,7 +765,7 @@ DEF_OP(AtomicFetchOr) {
     case 2: ldsetalh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldsetal(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldsetal(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -804,7 +811,7 @@ DEF_OP(AtomicFetchOr) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
@@ -819,7 +826,7 @@ DEF_OP(AtomicFetchXor) {
     case 2: ldeoralh(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 4: ldeoral(GetReg<RA_32>(Op->Header.Args[1].ID()), GetReg<RA_32>(Node), MemOperand(MemSrc)); break;
     case 8: ldeoral(GetReg<RA_64>(Op->Header.Args[1].ID()), GetReg<RA_64>(Node), MemOperand(MemSrc)); break;
-    default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
   else {
@@ -865,11 +872,61 @@ DEF_OP(AtomicFetchXor) {
         mov(GetReg<RA_64>(Node), TMP2);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled Atomic size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
     }
   }
 }
 
+DEF_OP(AtomicFetchNeg) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
+  auto MemSrc = GetReg<RA_64>(Op->Header.Args[0].ID());
+
+  // TMP2-TMP3
+  switch (Op->Size) {
+    case 1: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxrb(TMP2.W(), MemOperand(MemSrc));
+      neg(TMP3.W(), TMP2.W());
+      stlxrb(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+      cbnz(TMP4.W(), &LoopTop);
+      mov(GetReg<RA_32>(Node), TMP2.W());
+      break;
+    }
+    case 2: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxrh(TMP2.W(), MemOperand(MemSrc));
+      neg(TMP3.W(), TMP2.W());
+      stlxrh(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+      cbnz(TMP4.W(), &LoopTop);
+      mov(GetReg<RA_32>(Node), TMP2.W());
+      break;
+    }
+    case 4: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxr(TMP2.W(), MemOperand(MemSrc));
+      neg(TMP3.W(), TMP2.W());
+      stlxr(TMP4.W(), TMP3.W(), MemOperand(MemSrc));
+      cbnz(TMP4.W(), &LoopTop);
+      mov(GetReg<RA_32>(Node), TMP2.W());
+      break;
+    }
+    case 8: {
+      aarch64::Label LoopTop;
+      bind(&LoopTop);
+      ldaxr(TMP2, MemOperand(MemSrc));
+      neg(TMP3, TMP2);
+      stlxr(TMP4, TMP3, MemOperand(MemSrc));
+      cbnz(TMP4, &LoopTop);
+      mov(GetReg<RA_64>(Node), TMP2);
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled Atomic size: {}", Op->Size);
+  }
+}
+
 #undef DEF_OP
 void Arm64JITCore::RegisterAtomicHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &Arm64JITCore::Op_##x
@@ -886,6 +943,7 @@ void Arm64JITCore::RegisterAtomicHandlers() {
   REGISTER_OP(ATOMICFETCHAND, AtomicFetchAnd);
   REGISTER_OP(ATOMICFETCHOR,  AtomicFetchOr);
   REGISTER_OP(ATOMICFETCHXOR, AtomicFetchXor);
+  REGISTER_OP(ATOMICFETCHNEG, AtomicFetchNeg);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp

@@ -4,6 +4,8 @@ tags: backend|arm64
 $end_info$
 */
 
+#include "Interface/Core/LookupCache.h"
+
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/Core/InternalThreadState.h"
 
@@ -16,15 +18,15 @@ using namespace vixl;
 using namespace vixl::aarch64;
 #define DEF_OP(x) void Arm64JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(GuestCallDirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestCallIndirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestReturn) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(SignalReturn) {
@@ -142,7 +144,7 @@ Condition MapBranchCC(IR::CondClassType Cond) {
   case FEXCore::IR::COND_MI:
   case FEXCore::IR::COND_PL:
   default:
-  LOGMAN_MSG_A("Unsupported compare type");
+  LOGMAN_MSG_A_FMT("Unsupported compare type");
   return Condition::nv;
   }
 }
@@ -169,10 +171,10 @@ DEF_OP(CondJump) {
   bool isConst = IsInlineConstant(Op->Cmp2, &Const);
 
   if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_EQ) {
-    LOGMAN_THROW_A(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
+    LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
     cbz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
   } else if (isConst && Const == 0 && Op->Cond.Val == FEXCore::IR::COND_NEQ) {
-    LOGMAN_THROW_A(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
+    LOGMAN_THROW_A_FMT(IsGPR(Op->Cmp1.ID()), "CondJump: Expected GPR");
     cbnz(GRCMP(Op->Cmp1.ID()), TrueTargetLabel);
   } else {
     if (IsGPR(Op->Cmp1.ID())) {
@@ -183,7 +185,7 @@ DEF_OP(CondJump) {
     } else if (IsFPR(Op->Cmp1.ID())) {
       fcmp(GRFCMP(Op->Cmp1.ID()), GRFCMP(Op->Cmp2.ID()));
     } else {
-      LOGMAN_MSG_A("CondJump: Expected GPR or FPR");
+      LOGMAN_MSG_A_FMT("CondJump: Expected GPR or FPR");
     }
 
     b(TrueTargetLabel, MapBranchCC(Op->Cond));

External/FEXCore/Source/Interface/Core/JIT/Arm64/ConversionOps.cpp

@@ -31,7 +31,7 @@ DEF_OP(VInsGPR) {
       ins(GetDst(Node).V2D(), Op->Index, GetReg<RA_64>(Op->Header.Args[1].ID()));
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -52,7 +52,7 @@ DEF_OP(VCastFromGPR) {
     case 8:
       fmov(GetDst(Node).D(), GetReg<RA_64>(Op->Header.Args[0].ID()).X());
       break;
-    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown castGPR element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -91,7 +91,7 @@ DEF_OP(Float_FToF) {
       fcvt(GetDst(Node).S(), GetSrc(Op->Header.Args[0].ID()).D());
       break;
     }
-    default: LOGMAN_MSG_A("Unknown FCVT sizes: 0x%x", Conv);
+    default: LOGMAN_MSG_A_FMT("Unknown FCVT sizes: 0x{:x}", Conv);
   }
 }
 
@@ -104,7 +104,7 @@ DEF_OP(Vector_SToF) {
     case 8:
       scvtf(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -117,7 +117,7 @@ DEF_OP(Vector_FToZS) {
     case 8:
       fcvtzs(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -132,7 +132,7 @@ DEF_OP(Vector_FToS) {
       frinti(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
       fcvtzs(GetDst(Node).V2D(), GetDst(Node).V2D());
     break;
-    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -149,7 +149,7 @@ DEF_OP(Vector_FToF) {
       fcvtn(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2D());
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Conversion Type : 0%04x", Conv); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToF Type : 0x{:04x}", Conv); break;
   }
 }
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp

@@ -11,6 +11,7 @@ $end_info$
 */
 
 #include "Interface/Context/Context.h"
+#include "Interface/Core/LookupCache.h"
 
 #include "Interface/Core/ArchHelpers/Arm64.h"
 #include "Interface/Core/ArchHelpers/MContext.h"
@@ -45,8 +46,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
   FallbackInfo Info;
   if (!InterpreterOps::GetFallbackHandler(IROp, &Info)) {
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-    auto Name = FEXCore::IR::GetName(IROp->Op);
-    LOGMAN_MSG_A("Unhandled IR Op: %s", std::string(Name).c_str());
+    LOGMAN_MSG_A_FMT("Unhandled IR Op: {}", FEXCore::IR::GetName(IROp->Op));
 #endif
   } else {
     switch(Info.ABI) {
@@ -295,8 +295,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
       case FABI_UNKNOWN:
       default:
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-        auto Name = FEXCore::IR::GetName(IROp->Op);
-        LOGMAN_MSG_A("Unhandled IR Fallback abi: %s %d", std::string(Name).c_str(), Info.ABI);
+        LOGMAN_MSG_A_FMT("Unhandled IR Fallback ABI: {} {}", FEXCore::IR::GetName(IROp->Op), Info.ABI);
 #endif
       break;
     }
@@ -315,7 +314,7 @@ Arm64JITCore::CodeBuffer Arm64JITCore::AllocateNewCodeBuffer(size_t Size) {
                     PROT_READ | PROT_WRITE | PROT_EXEC,
                     MAP_PRIVATE | MAP_ANONYMOUS,
                     -1, 0));
-  LOGMAN_THROW_A(!!Buffer.Ptr, "Couldn't allocate code buffer");
+  LOGMAN_THROW_A_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer");
   Dispatcher->RegisterCodeBuffer(Buffer.Ptr, Buffer.Size);
   return Buffer;
 }
@@ -345,26 +344,52 @@ bool Arm64JITCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
     0b1011'0000'0000; // Inner shareable all
   if ((Instr & 0x3F'FF'FC'00) == 0x08'DF'FC'00 || // LDAR*
       (Instr & 0x3F'FF'FC'00) == 0x38'BF'C0'00) { // LDAPR*
-    uint32_t LDR = 0b0011'1000'0111'1111'0110'1000'0000'0000;
-    LDR |= Size << 30;
-    LDR |= AddrReg << 5;
-    LDR |= DataReg;
-    PC[-1] = DMB;
-    PC[0] = LDR;
-    PC[1] = DMB;
-    // Back up one instruction and have another go
-    ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) - 4);
+    if (ParanoidTSO()) {
+      if (FEXCore::ArchHelpers::Arm64::HandleAtomicLoad(ucontext, info, Instr)) {
+        // Skip this instruction now
+        ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + 4);
+        return true;
+      }
+      else {
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDAR*: PC: {} Instruction: 0x{:08x}\n", fmt::ptr(PC), PC[0]);
+        return false;
+      }
+    }
+    else {
+      uint32_t LDR = 0b0011'1000'0111'1111'0110'1000'0000'0000;
+      LDR |= Size << 30;
+      LDR |= AddrReg << 5;
+      LDR |= DataReg;
+      PC[-1] = DMB;
+      PC[0] = LDR;
+      PC[1] = DMB;
+      // Back up one instruction and have another go
+      ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) - 4);
+    }
   }
   else if ( (Instr & 0x3F'FF'FC'00) == 0x08'9F'FC'00) { // STLR*
-    uint32_t STR = 0b0011'1000'0011'1111'0110'1000'0000'0000;
-    STR |= Size << 30;
-    STR |= AddrReg << 5;
-    STR |= DataReg;
-    PC[-1] = DMB;
-    PC[0] = STR;
-    PC[1] = DMB;
-    // Back up one instruction and have another go
-    ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) - 4);
+    if (ParanoidTSO()) {
+      if (FEXCore::ArchHelpers::Arm64::HandleAtomicStore(ucontext, info, Instr)) {
+        // Skip this instruction now
+        ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + 4);
+        return true;
+      }
+      else {
+        LogMan::Msg::EFmt("Unhandled JIT SIGBUS STLR*: PC: {} Instruction: 0x{:08x}\n", fmt::ptr(PC), PC[0]);
+        return false;
+      }
+    }
+    else {
+      uint32_t STR = 0b0011'1000'0011'1111'0110'1000'0000'0000;
+      STR |= Size << 30;
+      STR |= AddrReg << 5;
+      STR |= DataReg;
+      PC[-1] = DMB;
+      PC[0] = STR;
+      PC[1] = DMB;
+      // Back up one instruction and have another go
+      ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) - 4);
+    }
   }
   else if ((Instr & FEXCore::ArchHelpers::Arm64::LDAXP_MASK) == FEXCore::ArchHelpers::Arm64::LDAXP_INST) { // LDAXP
     uint32_t DataReg2 = (Instr >> 10) & 0x1F;
@@ -401,7 +426,7 @@ bool Arm64JITCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
       return true;
     }
     else {
-      LogMan::Msg::E("Unhandled JIT SIGBUS CASPAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
+      LogMan::Msg::EFmt("Unhandled JIT SIGBUS CASPAL: PC: {} Instruction: 0x{:08x}\n", fmt::ptr(PC), PC[0]);
       return false;
     }
   }
@@ -412,7 +437,7 @@ bool Arm64JITCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
       return true;
     }
     else {
-      LogMan::Msg::E("Unhandled JIT SIGBUS CASAL: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
+      LogMan::Msg::EFmt("Unhandled JIT SIGBUS CASAL: PC: {} Instruction: 0x{:08x}\n", fmt::ptr(PC), PC[0]);
       return false;
     }
   }
@@ -424,12 +449,24 @@ bool Arm64JITCore::HandleSIGBUS(int Signal, void *info, void *ucontext) {
     }
     else {
       uint8_t Op = (PC[0] >> 12) & 0xF;
-      LogMan::Msg::E("Unhandled JIT SIGBUS Atomic mem op 0x%02x: PC: %p Instruction: 0x%08x\n", Op, PC, PC[0]);
+      LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}: PC: {} Instruction: 0x{:08x}\n", Op, fmt::ptr(PC), PC[0]);
+      return false;
+    }
+  }
+  else if ((Instr & FEXCore::ArchHelpers::Arm64::LDAXR_MASK) == FEXCore::ArchHelpers::Arm64::LDAXR_INST) { // LDAXR*
+    uint64_t BytesToSkip = FEXCore::ArchHelpers::Arm64::HandleAtomicLoadstoreExclusive(ucontext, info);
+    if (BytesToSkip) {
+      // Skip this instruction now
+      ArchHelpers::Context::SetPc(ucontext, ArchHelpers::Context::GetPc(ucontext) + BytesToSkip);
+      return true;
+    }
+    else {
+      LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDAXR: PC: {} Instruction: 0x{:08x}\n", fmt::ptr(PC), PC[0]);
       return false;
     }
   }
   else {
-    LogMan::Msg::E("Unhandled JIT SIGBUS: PC: %p Instruction: 0x%08x\n", PC, PC[0]);
+    LogMan::Msg::EFmt("Unhandled JIT SIGBUS: PC: {} Instruction: 0x{:08x}\n", fmt::ptr(PC), PC[0]);
     return false;
   }
 
@@ -584,7 +621,7 @@ Arm64JITCore::~Arm64JITCore() {
 IR::PhysicalRegister Arm64JITCore::GetPhys(uint32_t Node) const {
   auto PhyReg = RAData->GetNodeRegister(Node);
 
-  LOGMAN_THROW_A(!PhyReg.IsInvalid(), "Couldn't Allocate register for node: ssa%d. Class: %d", Node, PhyReg.Class);
+  LOGMAN_THROW_A_FMT(!PhyReg.IsInvalid(), "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class);
 
   return PhyReg;
 }
@@ -598,7 +635,7 @@ aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_32>(uint32_t Node) const
   } else if (Reg.Class == IR::GPRClass.Val) {
     return RA64[Reg.Reg].W();
   } else {
-    LOGMAN_THROW_A(false, "Unexpected Class: %d", Reg.Class);
+    LOGMAN_THROW_A_FMT(false, "Unexpected Class: {}", Reg.Class);
   }
 
   FEX_UNREACHABLE;
@@ -613,7 +650,7 @@ aarch64::Register Arm64JITCore::GetReg<Arm64JITCore::RA_64>(uint32_t Node) const
   } else if (Reg.Class == IR::GPRClass.Val) {
     return RA64[Reg.Reg];
   } else {
-    LOGMAN_THROW_A(false, "Unexpected Class: %d", Reg.Class);
+    LOGMAN_THROW_A_FMT(false, "Unexpected Class: {}", Reg.Class);
   }
 
   FEX_UNREACHABLE;
@@ -639,7 +676,7 @@ aarch64::VRegister Arm64JITCore::GetSrc(uint32_t Node) const {
   } else if (Reg.Class == IR::FPRClass.Val) {
     return RAFPR[Reg.Reg];
   } else {
-    LOGMAN_THROW_A(false, "Unexpected Class: %d", Reg.Class);
+    LOGMAN_THROW_A_FMT(false, "Unexpected Class: {}", Reg.Class);
   }
 
   FEX_UNREACHABLE;
@@ -653,7 +690,7 @@ aarch64::VRegister Arm64JITCore::GetDst(uint32_t Node) const {
   } else if (Reg.Class == IR::FPRClass.Val) {
     return RAFPR[Reg.Reg];
   } else {
-    LOGMAN_THROW_A(false, "Unexpected Class: %d", Reg.Class);
+    LOGMAN_THROW_A_FMT(false, "Unexpected Class: {}", Reg.Class);
   }
 
   FEX_UNREACHABLE;
@@ -791,7 +828,7 @@ void *Arm64JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IR
     using namespace FEXCore::IR;
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
     auto BlockIROp = BlockHeader->CW<FEXCore::IR::IROp_CodeBlock>();
-    LOGMAN_THROW_A(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
+    LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
 #endif
 
     {
@@ -856,7 +893,7 @@ uint64_t Arm64JITCore::ExitFunctionLink(Arm64JITCore *core, FEXCore::Core::CpuSt
   auto HostCode = Thread->LookupCache->FindBlock(GuestRip);
 
   if (!HostCode) {
-    //printf("ExitFunctionLink: Aborting, %lX not in cache\n", GuestRip);
+    //fmt::print("ExitFunctionLink: Aborting, {:X} not in cache\n", GuestRip);
     Frame->State.rip = GuestRip;
     return core->ThreadSharedData.Dispatcher->AbsoluteLoopTopAddress;
   }

External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h

@@ -6,7 +6,6 @@ $end_info$
 
 #pragma once
 
-#include "Interface/Core/LookupCache.h"
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 
@@ -257,6 +256,7 @@ private:
   DEF_OP(AtomicFetchAnd);
   DEF_OP(AtomicFetchOr);
   DEF_OP(AtomicFetchXor);
+  DEF_OP(AtomicFetchNeg);
 
   ///< Branch ops
   DEF_OP(GuestCallDirect);

External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp

@@ -30,7 +30,7 @@ DEF_OP(LoadContext) {
     case 8:
       ldr(GetReg<RA_64>(Node), MemOperand(STATE, Op->Offset));
     break;
-    default:  LOGMAN_MSG_A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
     }
   }
   else {
@@ -51,7 +51,7 @@ DEF_OP(LoadContext) {
     case 16:
       ldr(Dst, MemOperand(STATE, Op->Offset));
     break;
-    default:  LOGMAN_MSG_A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
     }
   }
 }
@@ -73,7 +73,7 @@ DEF_OP(StoreContext) {
     case 8:
       str(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(STATE, Op->Offset));
     break;
-    default:  LOGMAN_MSG_A("Unhandled StoreContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
     }
   }
   else {
@@ -94,7 +94,7 @@ DEF_OP(StoreContext) {
     case 16:
       str(Src, MemOperand(STATE, Op->Offset));
     break;
-    default:  LOGMAN_MSG_A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
     }
   }
 }
@@ -107,29 +107,29 @@ DEF_OP(LoadRegister) {
     auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.gregs[0])) / 8;
     auto regOffs = Op->Offset & 7;
 
-    LOGMAN_THROW_A(regId < SRA64.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < SRA64.size(), "out of range regId");
 
     auto reg = SRA64[regId];
 
     switch(Op->Header.Size) {
       case 1:
-        LOGMAN_THROW_A(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
         ubfx(GetReg<RA_64>(Node), reg, regOffs * 8, 8);
         break;
 
       case 2:
-        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         ubfx(GetReg<RA_64>(Node), reg, 0, 16);
         break;
 
       case 4:
-        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Node).GetCode() != reg.GetCode())
           mov(GetReg<RA_32>(Node), reg.W());
         break;
 
       case 8:
-        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Node).GetCode() != reg.GetCode())
           mov(GetReg<RA_64>(Node), reg);
         break;
@@ -138,24 +138,24 @@ DEF_OP(LoadRegister) {
     auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0])) / 16;
     auto regOffs = Op->Offset & 15;
 
-    LOGMAN_THROW_A(regId < SRAFPR.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < SRAFPR.size(), "out of range regId");
 
     auto guest = SRAFPR[regId];
     auto host = GetSrc(Node);
 
     switch(Op->Header.Size) {
       case 1:
-        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         mov(host.B(), guest.B());
         break;
 
       case 2:
-        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         fmov(host.H(), guest.H());
         break;
 
       case 4:
-        LOGMAN_THROW_A((regOffs & 3) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 3) == 0, "unexpected regOffs");
         if (regOffs == 0) {
           if (host.GetCode() != guest.GetCode())
             fmov(host.S(), guest.S());
@@ -165,7 +165,7 @@ DEF_OP(LoadRegister) {
         break;
 
       case 8:
-        LOGMAN_THROW_A((regOffs & 7) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 7) == 0, "unexpected regOffs");
         if (regOffs == 0) {
           if (host.GetCode() != guest.GetCode())
             mov(host.D(), guest.D());
@@ -175,13 +175,13 @@ DEF_OP(LoadRegister) {
         break;
 
       case 16:
-        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (host.GetCode() != guest.GetCode())
           mov(host.Q(), guest.Q());
         break;
     }
   } else {
-    LOGMAN_THROW_A(false, "Unhandled Op->Class %d", Op->Class);
+    LOGMAN_THROW_A_FMT(false, "Unhandled Op->Class {}", Op->Class);
   }
 }
 
@@ -192,28 +192,28 @@ DEF_OP(StoreRegister) {
     auto regId = Op->Offset / 8 - 1;
     auto regOffs = Op->Offset & 7;
 
-    LOGMAN_THROW_A(regId < SRA64.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < SRA64.size(), "out of range regId");
 
     auto reg = SRA64[regId];
 
     switch(Op->Header.Size) {
       case 1:
-        LOGMAN_THROW_A(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), regOffs * 8, 8);
         break;
 
       case 2:
-        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), 0, 16);
         break;
 
       case 4:
-        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         bfi(reg, GetReg<RA_64>(Op->Value.ID()), 0, 32);
         break;
 
       case 8:
-        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (GetReg<RA_64>(Op->Value.ID()).GetCode() != reg.GetCode())
           mov(reg, GetReg<RA_64>(Op->Value.ID()));
         break;
@@ -222,7 +222,7 @@ DEF_OP(StoreRegister) {
     auto regId = (Op->Offset - offsetof(FEXCore::Core::CpuStateFrame, State.xmm[0][0])) / 16;
     auto regOffs = Op->Offset & 15;
 
-    LOGMAN_THROW_A(regId < SRAFPR.size(), "regId out of range");
+    LOGMAN_THROW_A_FMT(regId < SRAFPR.size(), "regId out of range");
 
     auto guest = SRAFPR[regId];
     auto host = GetSrc(Op->Value.ID());
@@ -233,28 +233,28 @@ DEF_OP(StoreRegister) {
         break;
 
       case 2:
-        LOGMAN_THROW_A((regOffs & 1) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 1) == 0, "unexpected regOffs");
         ins(guest.V8H(), regOffs/2, host.V8H(), 0);
         break;
 
       case 4:
-        LOGMAN_THROW_A((regOffs & 3) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 3) == 0, "unexpected regOffs");
         ins(guest.V4S(), regOffs/4, host.V4S(), 0);
         break;
 
       case 8:
-        LOGMAN_THROW_A((regOffs & 7) == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT((regOffs & 7) == 0, "unexpected regOffs");
         ins(guest.V2D(), regOffs / 8, host.V2D(), 0);
         break;
 
       case 16:
-        LOGMAN_THROW_A(regOffs == 0, "unexpected regOffs");
+        LOGMAN_THROW_A_FMT(regOffs == 0, "unexpected regOffs");
         if (guest.GetCode() != host.GetCode())
           mov(guest.Q(), host.Q());
         break;
     }
   } else {
-    LOGMAN_THROW_A(false, "Unhandled Op->Class %d", Op->Class);
+    LOGMAN_THROW_A_FMT(false, "Unhandled Op->Class {}", Op->Class);
   }
 }
 
@@ -288,15 +288,17 @@ DEF_OP(LoadContextIndexed) {
         ldr(GetReg<RA_64>(Node), MemOperand(TMP1, Op->BaseOffset));
         break;
       default:
-        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     case 16:
-      LOGMAN_MSG_A("Invalid Class load of size 16");
+      LOGMAN_MSG_A_FMT("Invalid Class load of size 16");
       break;
     default:
-      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
   else {
@@ -333,12 +335,14 @@ DEF_OP(LoadContextIndexed) {
         }
         break;
       default:
-        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     default:
-      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
 }
@@ -374,15 +378,17 @@ DEF_OP(StoreContextIndexed) {
         str(value, MemOperand(TMP1, Op->BaseOffset));
         break;
       default:
-        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     case 16:
-      LOGMAN_MSG_A("Invalid Class load of size 16");
+      LOGMAN_MSG_A_FMT("Invalid Class store of size 16");
       break;
     default:
-      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
   else {
@@ -421,12 +427,14 @@ DEF_OP(StoreContextIndexed) {
         }
         break;
       default:
-        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     default:
-      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
 }
@@ -434,7 +442,7 @@ DEF_OP(StoreContextIndexed) {
 DEF_OP(SpillRegister) {
   auto Op = IROp->C<IR::IROp_SpillRegister>();
   uint8_t OpSize = IROp->Size;
-  uint32_t SlotOffset = Op->Slot * 16 + 16;
+  uint32_t SlotOffset = Op->Slot * 16;
 
   if (Op->Class == FEXCore::IR::GPRClass) {
     switch (OpSize) {
@@ -454,7 +462,7 @@ DEF_OP(SpillRegister) {
       str(GetReg<RA_64>(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -470,17 +478,17 @@ DEF_OP(SpillRegister) {
       str(GetSrc(Op->Header.Args[0].ID()), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
     }
   } else {
-    LOGMAN_MSG_A("Unhandled SpillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A_FMT("Unhandled SpillRegister class: {}", Op->Class.Val);
   }
 }
 
 DEF_OP(FillRegister) {
   auto Op = IROp->C<IR::IROp_FillRegister>();
   uint8_t OpSize = IROp->Size;
-  uint32_t SlotOffset = Op->Slot * 16 + 16;
+  uint32_t SlotOffset = Op->Slot * 16;
 
   if (Op->Class == FEXCore::IR::GPRClass) {
     switch (OpSize) {
@@ -500,7 +508,7 @@ DEF_OP(FillRegister) {
       ldr(GetReg<RA_64>(Node), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled FillRegister size: {}", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -516,10 +524,10 @@ DEF_OP(FillRegister) {
       ldr(GetDst(Node), MemOperand(sp, SlotOffset));
       break;
     }
-    default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled FillRegister size: {}", OpSize);
     }
   } else {
-    LOGMAN_MSG_A("Unhandled FillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A_FMT("Unhandled FillRegister class: {}", Op->Class.Val);
   }
 }
 
@@ -539,7 +547,7 @@ MemOperand Arm64JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Registe
     return MemOperand(Base);
   } else {
     if (OffsetScale != 1 && OffsetScale != AccessSize) {
-        LOGMAN_MSG_A("Unhandled GenerateMemOperand OffsetScale: %d", OffsetScale);
+        LOGMAN_MSG_A_FMT("Unhandled GenerateMemOperand OffsetScale: {}", OffsetScale);
     }
     uint64_t Const;
     if (IsInlineConstant(Offset, &Const)) {
@@ -551,7 +559,7 @@ MemOperand Arm64JITCore::GenerateMemOperand(uint8_t AccessSize, aarch64::Registe
         case IR::MEM_OFFSET_UXTW.Val: return MemOperand(Base, RegOffset.W(), Extend::UXTW, (int)std::log2(OffsetScale) );
         case IR::MEM_OFFSET_SXTW.Val: return MemOperand(Base, RegOffset.W(), Extend::SXTW, (int)std::log2(OffsetScale) );
 
-        default: LOGMAN_MSG_A("Unhandled GenerateMemOperand OffsetType: %d", OffsetType.Val); break;
+        default: LOGMAN_MSG_A_FMT("Unhandled GenerateMemOperand OffsetType: {}", OffsetType.Val); break;
       }
     }
   }
@@ -580,7 +588,7 @@ DEF_OP(LoadMem) {
       case 8:
         ldr(Dst, MemSrc);
         break;
-      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMem size: {}", Op->Size);
     }
   }
   else {
@@ -601,7 +609,7 @@ DEF_OP(LoadMem) {
       case 16:
         ldr(Dst, MemSrc);
         break;
-      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMem size: {}", Op->Size);
     }
   }
 }
@@ -612,7 +620,7 @@ DEF_OP(LoadMemTSO) {
   auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
 
   if (!Op->Offset.IsInvalid()) {
-    LOGMAN_MSG_A("LoadMemTSO: No offset allowed");
+    LOGMAN_MSG_A_FMT("LoadMemTSO: No offset allowed");
   }
 
   if (SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
@@ -635,7 +643,7 @@ DEF_OP(LoadMemTSO) {
         case 8:
           ldapr(Dst, MemSrc);
           break;
-        default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", Op->Size);
       }
       nop();
     }
@@ -660,7 +668,7 @@ DEF_OP(LoadMemTSO) {
         case 8:
           ldar(Dst, MemSrc);
           break;
-        default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", Op->Size);
       }
       nop();
     }
@@ -681,7 +689,7 @@ DEF_OP(LoadMemTSO) {
       case 16:
         ldr(Dst, MemSrc);
         break;
-      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", Op->Size);
     }
     dmb(InnerShareable, BarrierAll);
   }
@@ -708,7 +716,7 @@ DEF_OP(StoreMem) {
       case 8:
         str(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
         break;
-      default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", Op->Size);
     }
   }
   else {
@@ -729,7 +737,7 @@ DEF_OP(StoreMem) {
       case 16:
         str(Src, MemSrc);
         break;
-      default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", Op->Size);
     }
   }
 }
@@ -739,7 +747,7 @@ DEF_OP(StoreMemTSO) {
   auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
 
   if (!Op->Offset.IsInvalid()) {
-    LOGMAN_MSG_A("StoreMemTSO: No offset allowed");
+    LOGMAN_MSG_A_FMT("StoreMemTSO: No offset allowed");
   }
 
   if (Op->Class == FEXCore::IR::GPRClass) {
@@ -759,7 +767,7 @@ DEF_OP(StoreMemTSO) {
         case 8:
           stlr(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
           break;
-        default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled StoreMemTSO size: {}", Op->Size);
       }
       nop();
     }
@@ -783,7 +791,7 @@ DEF_OP(StoreMemTSO) {
       case 16:
         str(Src, MemSrc);
         break;
-      default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled StoreMemTSO size: {}", Op->Size);
     }
     dmb(InnerShareable, BarrierAll);
   }
@@ -795,7 +803,7 @@ DEF_OP(ParanoidLoadMemTSO) {
   auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
 
   if (!Op->Offset.IsInvalid()) {
-    LOGMAN_MSG_A("LoadMemTSO: No offset allowed");
+    LOGMAN_MSG_A_FMT("ParanoidLoadMemTSO: No offset allowed");
   }
 
   if (Op->Class == FEXCore::IR::GPRClass) {
@@ -806,7 +814,6 @@ DEF_OP(ParanoidLoadMemTSO) {
     }
     else {
       auto Dst = GetReg<RA_64>(Node);
-      nop();
       switch (Op->Size) {
         case 2:
           ldarh(Dst, MemSrc);
@@ -817,31 +824,24 @@ DEF_OP(ParanoidLoadMemTSO) {
         case 8:
           ldar(Dst, MemSrc);
           break;
-        default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", Op->Size);
       }
-      nop();
     }
   }
   else {
     auto Dst = GetDst(Node);
     switch (Op->Size) {
       case 2:
-        nop();
-        ldarh(TMP1, MemSrc);
-        nop();
-        fmov(Dst, TMP1);
+        ldarh(TMP1.W(), MemSrc);
+        fmov(Dst.H(), TMP1.W());
         break;
       case 4:
-        nop();
         ldar(TMP1.W(), MemSrc);
-        nop();
-        fmov(Dst, TMP1);
+        fmov(Dst.S(), TMP1.W());
         break;
       case 8:
-        nop();
         ldar(TMP1, MemSrc);
-        nop();
-        fmov(Dst, TMP1);
+        fmov(Dst.D(), TMP1);
         break;
       case 16:
         nop();
@@ -850,7 +850,7 @@ DEF_OP(ParanoidLoadMemTSO) {
         mov(Dst.V2D(), 0, TMP1);
         mov(Dst.V2D(), 1, TMP2);
         break;
-      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", Op->Size);
     }
   }
 }
@@ -860,7 +860,7 @@ DEF_OP(ParanoidStoreMemTSO) {
   auto MemSrc = MemOperand(GetReg<RA_64>(Op->Header.Args[0].ID()));
 
   if (!Op->Offset.IsInvalid()) {
-    LOGMAN_MSG_A("StoreMemTSO: No offset allowed");
+    LOGMAN_MSG_A_FMT("ParanoidStoreMemTSO: No offset allowed");
   }
 
   if (Op->Class == FEXCore::IR::GPRClass) {
@@ -869,7 +869,6 @@ DEF_OP(ParanoidStoreMemTSO) {
       stlrb(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
     }
     else {
-      nop();
       switch (Op->Size) {
         case 2:
           stlrh(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
@@ -880,37 +879,30 @@ DEF_OP(ParanoidStoreMemTSO) {
         case 8:
           stlr(GetReg<RA_64>(Op->Header.Args[1].ID()), MemSrc);
           break;
-        default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", Op->Size);
       }
-      nop();
     }
   }
   else {
     auto Src = GetSrc(Op->Header.Args[1].ID());
     if (Op->Size == 1) {
       // 8bit load is always aligned to natural alignment
-      mov(TMP1, Src.V4S(), 0);
+      mov(TMP1.W(), Src.V16B(), 0);
       stlrb(TMP1, MemSrc);
     }
     else {
       switch (Op->Size) {
         case 2:
-          mov(TMP1, Src.V4S(), 0);
-          nop();
+          mov(TMP1.W(), Src.V8H(), 0);
           stlrh(TMP1, MemSrc);
-          nop();
           break;
         case 4:
-          mov(TMP1, Src.V4S(), 0);
-          nop();
+          mov(TMP1.W(), Src.V4S(), 0);
           stlr(TMP1.W(), MemSrc);
-          nop();
           break;
         case 8:
           mov(TMP1, Src.V2D(), 0);
-          nop();
           stlr(TMP1, MemSrc);
-          nop();
           break;
         case 16: {
           // Move vector to GPRs
@@ -927,18 +919,18 @@ DEF_OP(ParanoidStoreMemTSO) {
           cbnz(TMP3, &B); // < Overwritten with DMB
           break;
         }
-        default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
+        default:  LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", Op->Size);
       }
     }
   }
 }
 
 DEF_OP(VLoadMemElement) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VStoreMemElement) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(CacheLineClear) {

External/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp

@@ -8,11 +8,11 @@ $end_info$
 
 namespace FEXCore::CPU {
 static void PrintValue(uint64_t Value) {
-  LogMan::Msg::D("Value: 0x%lx", Value);
+  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
 }
 
 static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
-  LogMan::Msg::D("Value: 0x%016lx'%016lx", ValueUpper, Value);
+  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
 }
 
 using namespace vixl;
@@ -31,7 +31,7 @@ DEF_OP(Fence) {
     case IR::Fence_Store.Val:
       dmb(FullSystem, BarrierWrites);
       break;
-    default: LOGMAN_MSG_A("Unknown Fence: %d", Op->Fence); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
   }
 }
 
@@ -69,7 +69,7 @@ DEF_OP(Break) {
       br(TMP1);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Break reason: %d", Op->Reason);
+    default: LOGMAN_MSG_A_FMT("Unknown Break reason: {}", Op->Reason);
   }
 }
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/MoveOps.cpp

@@ -26,7 +26,7 @@ DEF_OP(ExtractElementPair) {
       mov (GetReg<RA_64>(Node), Regs[Op->Element]);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
   }
 }
 
@@ -52,7 +52,7 @@ DEF_OP(CreateElementPair) {
       RegTmp = x0;
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
   }
 
   if (Dst.first.GetCode() != RegSecond.GetCode()) {

External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp

@@ -22,7 +22,7 @@ DEF_OP(VectorZero) {
        eor(GetDst(Node).V16B(), GetDst(Node).V16B(), GetDst(Node).V16B());
        break;
      }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", OpSize); break;
   }
 }
 
@@ -43,47 +43,47 @@ DEF_OP(VectorImm) {
 }
 
 DEF_OP(CreateVector2) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(CreateVector4) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(SplatVector2) {
-	auto Op = IROp->C<IR::IROp_SplatVector2>();
+  auto Op = IROp->C<IR::IROp_SplatVector2>();
   uint8_t OpSize = IROp->Size;
-	LOGMAN_THROW_A(OpSize <= 16, "Can't handle a vector of size: %d", OpSize);
+  LOGMAN_THROW_A_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize);
 
-	uint8_t ElementSize = OpSize / 2;
+  uint8_t ElementSize = OpSize / 2;
 
-	switch (ElementSize) {
-		case 4:
-			dup(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S(), 0);
-		break;
-		case 8:
-			dup(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), 0);
-		break;
-		default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.Size); break;
-	}
+  switch (ElementSize) {
+    case 4:
+      dup(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S(), 0);
+    break;
+    case 8:
+      dup(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), 0);
+    break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.Size); break;
+  }
 }
 
 DEF_OP(SplatVector4) {
-	auto Op = IROp->C<IR::IROp_SplatVector4>();
+  auto Op = IROp->C<IR::IROp_SplatVector4>();
   uint8_t OpSize = IROp->Size;
-	LOGMAN_THROW_A(OpSize <= 16, "Can't handle a vector of size: %d", OpSize);
+  LOGMAN_THROW_A_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize);
 
-	uint8_t ElementSize = OpSize / 4;
+  uint8_t ElementSize = OpSize / 4;
 
-	switch (ElementSize) {
-		case 4:
-			dup(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S(), 0);
-		break;
-		case 8:
-			dup(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), 0);
-		break;
-		default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.Size); break;
-	}
+  switch (ElementSize) {
+    case 4:
+      dup(GetDst(Node).V4S(), GetSrc(Op->Header.Args[0].ID()).V4S(), 0);
+    break;
+    case 8:
+      dup(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), 0);
+    break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.Size); break;
+  }
 }
 
 DEF_OP(VMov) {
@@ -118,7 +118,7 @@ DEF_OP(VMov) {
 			  mov(GetDst(Node).V16B(), GetSrc(Op->Header.Args[0].ID()).V16B());
 			break;
 		}
-		default: LOGMAN_MSG_A("Unknown Element Size: %d", OpSize); break;
+		default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", OpSize); break;
 	}
 }
 
@@ -161,7 +161,7 @@ DEF_OP(VAdd) {
       add(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -184,7 +184,7 @@ DEF_OP(VSub) {
       sub(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -207,7 +207,7 @@ DEF_OP(VUQAdd) {
       uqadd(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -230,7 +230,7 @@ DEF_OP(VUQSub) {
       uqsub(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -253,7 +253,7 @@ DEF_OP(VSQAdd) {
       sqadd(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -276,7 +276,7 @@ DEF_OP(VSQSub) {
       sqsub(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -298,7 +298,7 @@ DEF_OP(VAddP) {
         addp(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2S(), GetSrc(Op->Header.Args[1].ID()).V2S());
         break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -319,7 +319,7 @@ DEF_OP(VAddP) {
         addp(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
         break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -338,7 +338,7 @@ DEF_OP(VAddV) {
     case 8:
       addp(GetDst(Node).VCast(OpSize * 8, 1), GetSrc(Op->Header.Args[0].ID()).VCast(OpSize * 8, Elements));
       break;
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -353,7 +353,7 @@ DEF_OP(VUMinV) {
     case 4:
       uminv(GetDst(Node).VCast(Op->Header.ElementSize * 8, 1), GetSrc(Op->Header.Args[0].ID()).VCast(OpSize * 8, Elements));
       break;
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -368,7 +368,7 @@ DEF_OP(VURAvg) {
       urhadd(GetDst(Node).V8H(), GetSrc(Op->Header.Args[0].ID()).V8H(), GetSrc(Op->Header.Args[1].ID()).V8H());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -383,7 +383,7 @@ DEF_OP(VAbs) {
         abs(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -395,7 +395,7 @@ DEF_OP(VAbs) {
       case 8:
         abs(GetDst(Node).VCast(OpSize * 8, Elements), GetSrc(Op->Header.Args[0].ID()).VCast(OpSize * 8, Elements));
         break;
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -410,7 +410,7 @@ DEF_OP(VPopcount) {
         cnt(GetDst(Node).V8B(), GetSrc(Op->Header.Args[0].ID()).V8B());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -419,7 +419,7 @@ DEF_OP(VPopcount) {
       case 1:
         cnt(GetDst(Node).V16B(), GetSrc(Op->Header.Args[0].ID()).V16B());
         break;
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -438,7 +438,7 @@ DEF_OP(VFAdd) {
         fadd(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -452,7 +452,7 @@ DEF_OP(VFAdd) {
         fadd(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -468,7 +468,7 @@ DEF_OP(VFAddP) {
       faddp(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -486,7 +486,7 @@ DEF_OP(VFSub) {
         fsub(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -500,7 +500,7 @@ DEF_OP(VFSub) {
         fsub(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -519,7 +519,7 @@ DEF_OP(VFMul) {
         fmul(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -533,7 +533,7 @@ DEF_OP(VFMul) {
         fmul(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -552,7 +552,7 @@ DEF_OP(VFDiv) {
         fdiv(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -566,7 +566,7 @@ DEF_OP(VFDiv) {
         fdiv(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -587,7 +587,7 @@ DEF_OP(VFMin) {
         fcsel(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D(), Condition::mi);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -607,7 +607,7 @@ DEF_OP(VFMin) {
         mov(GetDst(Node).V2D(), VTMP2.V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -628,7 +628,7 @@ DEF_OP(VFMax) {
         fcsel(GetDst(Node).D(), GetSrc(Op->Header.Args[1].ID()).D(), GetSrc(Op->Header.Args[0].ID()).D(), Condition::mi);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -648,7 +648,7 @@ DEF_OP(VFMax) {
         mov(GetDst(Node).V2D(), VTMP2.V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -669,7 +669,7 @@ DEF_OP(VFRecp) {
         fdiv(GetDst(Node).D(), VTMP1.D(), GetSrc(Op->Header.Args[0].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -685,7 +685,7 @@ DEF_OP(VFRecp) {
         fdiv(GetDst(Node).V2D(), VTMP1.V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -704,7 +704,7 @@ DEF_OP(VFSqrt) {
         fsqrt(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -718,7 +718,7 @@ DEF_OP(VFSqrt) {
         fsqrt(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -741,7 +741,7 @@ DEF_OP(VFRSqrt) {
         fdiv(GetDst(Node).D(), VTMP1.D(), VTMP2.D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -759,7 +759,7 @@ DEF_OP(VFRSqrt) {
         fdiv(GetDst(Node).V2D(), VTMP1.V2D(), VTMP2.V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -779,7 +779,7 @@ DEF_OP(VNeg) {
   case 8:
     neg(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-  default: LOGMAN_MSG_A("Unsupported Not size: %d", IROp->Size);
+  default: LOGMAN_MSG_A_FMT("Unsupported VNeg size: {}", IROp->Size);
   }
 }
 
@@ -792,7 +792,7 @@ DEF_OP(VFNeg) {
   case 8:
     fneg(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-  default: LOGMAN_MSG_A("Unsupported Not size: %d", IROp->Size);
+  default: LOGMAN_MSG_A_FMT("Unsupported VFNeg size: {}", IROp->Size);
   }
 }
 
@@ -823,7 +823,7 @@ DEF_OP(VUMin) {
       mov(GetDst(Node).V2D(), VTMP2.V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -849,7 +849,7 @@ DEF_OP(VSMin) {
       mov(GetDst(Node).V2D(), VTMP2.V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -875,7 +875,7 @@ DEF_OP(VUMax) {
       mov(GetDst(Node).V2D(), VTMP2.V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -901,7 +901,7 @@ DEF_OP(VSMax) {
       mov(GetDst(Node).V2D(), VTMP2.V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -922,7 +922,7 @@ DEF_OP(VZip) {
         zip1(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2S(), GetSrc(Op->Header.Args[1].ID()).V2S());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -943,7 +943,7 @@ DEF_OP(VZip) {
         zip1(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -965,7 +965,7 @@ DEF_OP(VZip2) {
       zip2(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2S(), GetSrc(Op->Header.Args[1].ID()).V2S());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -986,7 +986,7 @@ DEF_OP(VZip2) {
       zip2(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1008,7 +1008,7 @@ DEF_OP(VUnZip) {
         uzp1(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2S(), GetSrc(Op->Header.Args[1].ID()).V2S());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1029,7 +1029,7 @@ DEF_OP(VUnZip) {
         uzp1(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1051,7 +1051,7 @@ DEF_OP(VUnZip2) {
       uzp2(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2S(), GetSrc(Op->Header.Args[1].ID()).V2S());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1072,7 +1072,7 @@ DEF_OP(VUnZip2) {
       uzp2(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1105,7 +1105,7 @@ DEF_OP(VCMPEQ) {
         cmeq(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1127,7 +1127,7 @@ DEF_OP(VCMPEQ) {
         cmeq(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1146,7 +1146,7 @@ DEF_OP(VCMPEQZ) {
         cmeq(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), 0);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1168,7 +1168,7 @@ DEF_OP(VCMPEQZ) {
         cmeq(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), 0);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1187,7 +1187,7 @@ DEF_OP(VCMPGT) {
         cmgt(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1209,7 +1209,7 @@ DEF_OP(VCMPGT) {
         cmgt(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1228,7 +1228,7 @@ DEF_OP(VCMPGTZ) {
         cmgt(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), 0);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1250,7 +1250,7 @@ DEF_OP(VCMPGTZ) {
         cmgt(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), 0);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1269,7 +1269,7 @@ DEF_OP(VCMPLTZ) {
         cmlt(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), 0);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1291,7 +1291,7 @@ DEF_OP(VCMPLTZ) {
         cmlt(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), 0);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1310,7 +1310,7 @@ DEF_OP(VFCMPEQ) {
         fcmeq(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1328,7 +1328,7 @@ DEF_OP(VFCMPEQ) {
         fcmeq(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1347,7 +1347,7 @@ DEF_OP(VFCMPNEQ) {
         fcmeq(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
     mvn(GetDst(Node).V8B(), GetDst(Node).V8B());
   }
@@ -1366,7 +1366,7 @@ DEF_OP(VFCMPNEQ) {
         fcmeq(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
     mvn(GetDst(Node).V16B(), GetDst(Node).V16B());
   }
@@ -1386,7 +1386,7 @@ DEF_OP(VFCMPLT) {
         fcmgt(GetDst(Node).D(), GetSrc(Op->Header.Args[1].ID()).D(), GetSrc(Op->Header.Args[0].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1404,7 +1404,7 @@ DEF_OP(VFCMPLT) {
         fcmgt(GetDst(Node).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1423,7 +1423,7 @@ DEF_OP(VFCMPGT) {
         fcmgt(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).D(), GetSrc(Op->Header.Args[1].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1441,7 +1441,7 @@ DEF_OP(VFCMPGT) {
         fcmgt(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1460,7 +1460,7 @@ DEF_OP(VFCMPLE) {
         fcmge(GetDst(Node).D(), GetSrc(Op->Header.Args[1].ID()).D(), GetSrc(Op->Header.Args[0].ID()).D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1478,7 +1478,7 @@ DEF_OP(VFCMPLE) {
         fcmge(GetDst(Node).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1501,7 +1501,7 @@ DEF_OP(VFCMPORD) {
         orr(GetDst(Node).V8B(), VTMP1.V8B(), VTMP2.V8B());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1525,7 +1525,7 @@ DEF_OP(VFCMPORD) {
         orr(GetDst(Node).V16B(), VTMP1.V16B(), VTMP2.V16B());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1550,7 +1550,7 @@ DEF_OP(VFCMPUNO) {
         mvn(GetDst(Node).V8B(), GetDst(Node).V8B());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -1577,21 +1577,21 @@ DEF_OP(VFCMPUNO) {
         mvn(GetDst(Node).V16B(), GetDst(Node).V16B());
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
 
 DEF_OP(VUShl) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VUShr) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VSShr) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VUShlS) {
@@ -1618,7 +1618,7 @@ DEF_OP(VUShlS) {
       ushl(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), VTMP1.V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1650,7 +1650,7 @@ DEF_OP(VUShrS) {
       ushl(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), VTMP1.V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1682,7 +1682,7 @@ DEF_OP(VSShrS) {
       sshl(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), VTMP1.V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1713,7 +1713,7 @@ DEF_OP(VInsElement) {
       mov(reg.V2D(), Op->DestIdx, GetSrc(Op->Header.Args[1].ID()).V2D(), Op->SrcIdx);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 
   if (GetDst(Node).GetCode() != reg.GetCode()) {
@@ -1748,7 +1748,7 @@ DEF_OP(VInsScalarElement) {
       mov(reg.V2D(), Op->DestIdx, GetSrc(Op->Header.Args[1].ID()).V2D(), 0);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 
   if (GetDst(Node).GetCode() != reg.GetCode()) {
@@ -1772,7 +1772,7 @@ DEF_OP(VExtractElement) {
     case 8:
       mov(GetDst(Node).D(), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->Index);
     break;
-    default:  LOGMAN_MSG_A("Unhandled ExtractElementSize: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled VExtractElement element size: {}", OpSize);
   }
 }
 
@@ -1791,7 +1791,7 @@ DEF_OP(VDupElement) {
     case 8:
       dup(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->Index);
     break;
-    default:  LOGMAN_MSG_A("Unhandled DupElementSize: %d", Op->Header.ElementSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled VDupElement element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -1906,7 +1906,7 @@ DEF_OP(VUShrI) {
         ushr(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->BitShift);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1931,7 +1931,7 @@ DEF_OP(VSShrI) {
       sshr(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), std::min((uint8_t)(Op->Header.ElementSize * 8 - 1), Op->BitShift));
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1959,7 +1959,7 @@ DEF_OP(VShlI) {
         shl(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->BitShift);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1980,7 +1980,7 @@ DEF_OP(VUShrNI) {
       shrn(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2D(), Op->BitShift);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -2000,7 +2000,7 @@ DEF_OP(VUShrNI2) {
       shrn2(VTMP1.V4S(), GetSrc(Op->Header.Args[1].ID()).V2D(), Op->BitShift);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 
   mov(GetDst(Node), VTMP1);
@@ -2023,7 +2023,7 @@ DEF_OP(VSXTL) {
     case 8:
       sxtl(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2S());
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -2039,7 +2039,7 @@ DEF_OP(VSXTL2) {
     case 8:
       sxtl2(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V4S());
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -2055,7 +2055,7 @@ DEF_OP(VUXTL) {
     case 8:
       uxtl(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2S());
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -2071,7 +2071,7 @@ DEF_OP(VUXTL2) {
     case 8:
       uxtl2(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V4S());
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -2087,7 +2087,7 @@ DEF_OP(VSQXTN) {
     case 4:
       sqxtn(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -2109,7 +2109,7 @@ DEF_OP(VSQXTN2) {
         sqxtn(VTMP2.V2S(), GetSrc(Op->Header.Args[1].ID()).V2D());
         ins(VTMP1.V4S(), 1, VTMP2.V4S(), 0);
       break;
-      default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
     }
   }
   else {
@@ -2123,7 +2123,7 @@ DEF_OP(VSQXTN2) {
       case 4:
         sqxtn2(VTMP1.V4S(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
-      default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
     }
   }
   mov(GetDst(Node), VTMP1);
@@ -2141,7 +2141,7 @@ DEF_OP(VSQXTUN) {
     case 4:
       sqxtun(GetDst(Node).V2S(), GetSrc(Op->Header.Args[0].ID()).V2D());
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -2163,7 +2163,7 @@ DEF_OP(VSQXTUN2) {
         sqxtun(VTMP2.V2S(), GetSrc(Op->Header.Args[1].ID()).V2D());
         ins(VTMP1.V4S(), 1, VTMP2.V4S(), 0);
       break;
-      default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
     }
   }
   else {
@@ -2177,7 +2177,7 @@ DEF_OP(VSQXTUN2) {
       case 4:
         sqxtun2(VTMP1.V4S(), GetSrc(Op->Header.Args[1].ID()).V2D());
       break;
-      default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
     }
   }
   mov(GetDst(Node), VTMP1);
@@ -2202,7 +2202,7 @@ DEF_OP(VMul) {
       mul(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2D(), GetSrc(Op->Header.Args[1].ID()).V2D());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -2221,7 +2221,7 @@ DEF_OP(VUMull) {
       umull(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2S(), GetSrc(Op->Header.Args[1].ID()).V2S());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize >> 1); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize >> 1); break;
   }
 }
 
@@ -2240,7 +2240,7 @@ DEF_OP(VSMull) {
       smull(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2S(), GetSrc(Op->Header.Args[1].ID()).V2S());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize >> 1); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize >> 1); break;
   }
 }
 
@@ -2259,7 +2259,7 @@ DEF_OP(VUMull2) {
       umull2(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V4S(), GetSrc(Op->Header.Args[1].ID()).V4S());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize >> 1); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize >> 1); break;
   }
 }
 
@@ -2278,7 +2278,7 @@ DEF_OP(VSMull2) {
       smull2(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V4S(), GetSrc(Op->Header.Args[1].ID()).V4S());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize >> 1); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize >> 1); break;
   }
 }
 
@@ -2297,7 +2297,7 @@ DEF_OP(VUABDL) {
       uabdl(GetDst(Node).V2D(), GetSrc(Op->Header.Args[0].ID()).V2S(), GetSrc(Op->Header.Args[1].ID()).V2S());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize >> 1); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize >> 1); break;
   }
 }
 
@@ -2314,7 +2314,7 @@ DEF_OP(VTBL1) {
       tbl(GetDst(Node).V16B(), GetSrc(Op->Header.Args[0].ID()).V16B(), GetSrc(Op->Header.Args[1].ID()).V16B());
     break;
     }
-    default: LOGMAN_MSG_A("Unknown OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown OpSize: {}", OpSize); break;
   }
 }
 

External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp

@@ -20,7 +20,7 @@ DEF_OP(TruncElementPair) {
       mov(Dst.second, Src.second);
       break;
     }
-    default: LOGMAN_MSG_A("Unhandled Truncation size: %d", Op->Size); break;
+    default: LOGMAN_MSG_A_FMT("Unhandled Truncation size: {}", Op->Size); break;
   }
 }
 
@@ -70,7 +70,7 @@ DEF_OP(Add) {
     case 8:
       add(rax, Const);
       break;
-    default:  LOGMAN_MSG_A("Unhandled Add size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Add size: {}", OpSize);
       break;
     }
   } else {
@@ -81,7 +81,7 @@ DEF_OP(Add) {
     case 8:
       add(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LOGMAN_MSG_A("Unhandled Add size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Add size: {}", OpSize);
       break;
     }
   }
@@ -103,7 +103,7 @@ DEF_OP(Sub) {
     case 8:
       sub(rax, Const);
       break;
-    default:  LOGMAN_MSG_A("Unhandled Sub size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Sub size: {}", OpSize);
       break;
     }
   } else {
@@ -114,7 +114,7 @@ DEF_OP(Sub) {
     case 8:
       sub(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LOGMAN_MSG_A("Unhandled Sub size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled Sub size: {}", OpSize);
       break;
     }
   }
@@ -136,7 +136,7 @@ DEF_OP(Neg) {
     Src = GetSrc<RA_64>(Op->Header.Args[0].ID());
     Dst = GetDst<RA_64>(Node);
     break;
-  default:  LOGMAN_MSG_A("Unhandled Neg size: %d", OpSize);
+  default:  LOGMAN_MSG_A_FMT("Unhandled Neg size: {}", OpSize);
     break;
   }
   mov(Dst, Src);
@@ -160,7 +160,7 @@ DEF_OP(Mul) {
     imul(rax, GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(Dst, rax);
   break;
-  default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown Mul size: {}", OpSize);
   }
 }
 
@@ -179,7 +179,7 @@ DEF_OP(UMul) {
     mul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rax);
   break;
-  default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown UMul size: {}", OpSize);
   }
 }
 
@@ -218,7 +218,7 @@ DEF_OP(Div) {
     mov(GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LOGMAN_MSG_A("Unknown UDIV Size: %d", Size); break;
+  default: LOGMAN_MSG_A_FMT("Unknown DIV Size: {}", Size); break;
   }
 }
 
@@ -261,7 +261,7 @@ DEF_OP(UDiv) {
     mov(GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LOGMAN_MSG_A("Unknown UDIV OpSize: %d", OpSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown UDIV OpSize: {}", OpSize); break;
   }
 }
 
@@ -298,7 +298,7 @@ DEF_OP(Rem) {
     mov(GetDst<RA_64>(Node), rdx);
   break;
   }
-  default: LOGMAN_MSG_A("Unknown UDIV Size: %d", OpSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown Rem Size: {}", OpSize); break;
   }
 }
 
@@ -341,7 +341,7 @@ DEF_OP(URem) {
     mov(GetDst<RA_64>(Node), rdx);
   break;
   }
-  default: LOGMAN_MSG_A("Unknown UDIV OpSize: %d", OpSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown URem OpSize: {}", OpSize); break;
   }
 }
 
@@ -360,7 +360,7 @@ DEF_OP(MulH) {
     imul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rdx);
   break;
-  default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown MulH size: {}", OpSize);
   }
 }
 
@@ -379,7 +379,7 @@ DEF_OP(UMulH) {
     mul(GetSrc<RA_64>(Op->Header.Args[1].ID()));
     mov(GetDst<RA_64>(Node), rdx);
   break;
-  default: LOGMAN_MSG_A("Unknown Sext size: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unknown UMulH size: {}", OpSize);
   }
 }
 
@@ -441,7 +441,7 @@ DEF_OP(Lshl) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shl(GetDst<RA_64>(Node), Const);
         break;
-      default: LOGMAN_MSG_A("Unknown LSHL Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown LSHL Size: {}\n", OpSize); break;
     };
   } else {
     mov(rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
@@ -456,7 +456,7 @@ DEF_OP(Lshl) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shl(GetDst<RA_64>(Node), cl);
         break;
-      default: LOGMAN_MSG_A("Unknown LSHL Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown LSHL Size: {}\n", OpSize); break;
     };
   }
 }
@@ -488,7 +488,7 @@ DEF_OP(Lshr) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shr(GetDst<RA_64>(Node), Const);
         break;
-      default: LOGMAN_MSG_A("Unknown Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Size: {}\n", OpSize); break;
     };
 
   } else {
@@ -512,7 +512,7 @@ DEF_OP(Lshr) {
         mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         shr(GetDst<RA_64>(Node), cl);
         break;
-      default: LOGMAN_MSG_A("Unknown Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Size: {}\n", OpSize); break;
     };
   }
 }
@@ -546,7 +546,7 @@ DEF_OP(Ashr) {
       mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       sar(GetDst<RA_64>(Node), Const);
     break;
-    default: LOGMAN_MSG_A("Unknown ASHR Size: %d\n", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown ASHR Size: {}\n", OpSize); break;
     };
 
   } else {
@@ -571,7 +571,7 @@ DEF_OP(Ashr) {
       mov(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       sar(GetDst<RA_64>(Node), cl);
     break;
-    default: LOGMAN_MSG_A("Unknown ASHR Size: %d\n", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown ASHR Size: {}\n", OpSize); break;
     };
   }
 }
@@ -596,7 +596,7 @@ DEF_OP(Ror) {
         ror(rax, Const);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown ROR Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown ROR Size: {}\n", OpSize); break;
     }
   } else {
     mov (rcx, GetSrc<RA_64>(Op->Header.Args[1].ID()));
@@ -612,7 +612,7 @@ DEF_OP(Ror) {
         ror(rax, cl);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown ROR Size: %d\n", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown ROR Size: {}\n", OpSize); break;
     }
   }
   mov(GetDst<RA_64>(Node), rax);
@@ -668,7 +668,7 @@ DEF_OP(LDiv) {
       mov(GetDst<RA_64>(Node), rax);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown LDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LDIV OpSize: {}", OpSize); break;
   }
 }
 
@@ -700,7 +700,7 @@ DEF_OP(LUDiv) {
       mov(GetDst<RA_64>(Node), rax);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown LUDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUDIV OpSize: {}", OpSize); break;
   }
 }
 
@@ -732,7 +732,7 @@ DEF_OP(LRem) {
       mov(GetDst<RA_64>(Node), rdx);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown LREM OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LREM OpSize: {}", OpSize); break;
   }
 }
 
@@ -764,7 +764,7 @@ DEF_OP(LURem) {
       mov(GetDst<RA_64>(Node), rdx);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown LUDIV OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown LUREM OpSize: {}", OpSize); break;
   }
 }
 
@@ -829,7 +829,7 @@ DEF_OP(FindMSB) {
     case 8:
       bsr(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       break;
-    default: LOGMAN_MSG_A("Unknown OpSize: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unknown FindMSB OpSize: {}", OpSize);
   }
 }
 
@@ -853,7 +853,7 @@ DEF_OP(FindTrailingZeros) {
       mov(rax, 0x40);
       cmovz(GetDst<RA_64>(Node), rax);
       break;
-    default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown FindTrailingZeros size: {}", OpSize); break;
   }
 }
 
@@ -876,7 +876,7 @@ DEF_OP(CountLeadingZeroes) {
         lzcnt(GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
         break;
       }
-      default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown CountLeadingZeros size: {}", OpSize); break;
     }
   }
   else {
@@ -915,7 +915,7 @@ DEF_OP(CountLeadingZeroes) {
         mov(GetDst<RA_64>(Node), rax);
         break;
       }
-      default: LOGMAN_MSG_A("Unknown size: %d", OpSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown CountLeadingZeros size: {}", OpSize); break;
     }
   }
 }
@@ -937,7 +937,7 @@ DEF_OP(Rev) {
       mov (GetDst<RA_64>(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()));
       bswap(GetDst<RA_64>(Node).cvt64());
       break;
-    default: LOGMAN_MSG_A("Unknown REV size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown REV size: {}", OpSize); break;
   }
 }
 
@@ -970,7 +970,7 @@ DEF_OP(Bfi) {
 
 DEF_OP(Bfe) {
   auto Op = IROp->C<IR::IROp_Bfe>();
-  LOGMAN_THROW_A(IROp->Size <= 8, "OpSize is too large for BFE: %d", IROp->Size);
+  LOGMAN_THROW_A_FMT(IROp->Size <= 8, "OpSize is too large for BFE: {}", IROp->Size);
 
   auto Dst = GetDst<RA_64>(Node);
 
@@ -1071,7 +1071,7 @@ DEF_OP(Select) {
 
   if (is_const_true || is_const_false) {
     if (is_const_false != true || is_const_true != true || const_true != 1 || const_false != 0) {
-      LOGMAN_MSG_A("Select: Unsupported compare inline parameters");
+      LOGMAN_MSG_A_FMT("Select: Unsupported compare inline parameters");
     }
     (this->*SetCC)(al);
     movzx(Dst, al);
@@ -1102,7 +1102,7 @@ DEF_OP(VExtractToGPR) {
       pextrq(GetDst<RA_64>(Node), GetSrc(Op->Header.Args[0].ID()), Op->Idx);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 

External/FEXCore/Source/Interface/Core/JIT/x86_64/AtomicOps.cpp

@@ -55,7 +55,7 @@ DEF_OP(CASPair) {
       mov(Dst.second, rdx);
     break;
     }
-    default: LOGMAN_MSG_A("Unsupported: %d", OpSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
   }
 }
 
@@ -104,7 +104,7 @@ DEF_OP(CAS) {
     mov (GetDst<RA_64>(Node), rax);
   break;
   }
-  default: LOGMAN_MSG_A("Unsupported: %d", OpSize);
+  default: LOGMAN_MSG_A_FMT("Unsupported: {}", OpSize);
   }
 }
 
@@ -127,7 +127,7 @@ DEF_OP(AtomicAdd) {
     case 8:
       add(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", Op->Size);
   }
 }
 
@@ -149,7 +149,7 @@ DEF_OP(AtomicSub) {
     case 8:
       sub(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", Op->Size);
   }
 }
 
@@ -171,7 +171,7 @@ DEF_OP(AtomicAnd) {
     case 8:
       and_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", Op->Size);
   }
 }
 
@@ -193,7 +193,7 @@ DEF_OP(AtomicOr) {
     case 8:
       or_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", Op->Size);
   }
 }
 
@@ -215,7 +215,7 @@ DEF_OP(AtomicXor) {
     case 8:
       xor_(qword [MemReg], GetSrc<RA_64>(Op->Header.Args[1].ID()));
       break;
-    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicAdd size: {}", Op->Size);
   }
 }
 
@@ -246,7 +246,7 @@ DEF_OP(AtomicSwap) {
       lock();
       xchg(qword [MemReg], GetDst<RA_64>(Node));
       break;
-    default:  LOGMAN_MSG_A("Unhandled AtomicAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicSwap size: {}", Op->Size);
   }
 }
 
@@ -279,7 +279,7 @@ DEF_OP(AtomicFetchAdd) {
       xadd(qword [MemReg], rcx);
       mov(GetDst<RA_64>(Node), rcx);
       break;
-    default:  LOGMAN_MSG_A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchAdd size: {}", Op->Size);
   }
 }
 
@@ -316,7 +316,7 @@ DEF_OP(AtomicFetchSub) {
       xadd(qword [MemReg], rcx);
       mov(GetDst<RA_64>(Node), rcx);
       break;
-    default:  LOGMAN_MSG_A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchSub size: {}", Op->Size);
   }
 }
 
@@ -394,7 +394,7 @@ DEF_OP(AtomicFetchAnd) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LOGMAN_MSG_A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchAnd size: {}", Op->Size);
   }
 }
 
@@ -471,7 +471,7 @@ DEF_OP(AtomicFetchOr) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LOGMAN_MSG_A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchOr size: {}", Op->Size);
   }
 }
 
@@ -548,7 +548,83 @@ DEF_OP(AtomicFetchXor) {
       mov(GetDst<RA_64>(Node), TMP3.cvt64());
       break;
     }
-    default:  LOGMAN_MSG_A("Unhandled AtomicFetchAdd size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchXor size: {}", Op->Size);
+  }
+}
+
+DEF_OP(AtomicFetchNeg) {
+  auto Op = IROp->C<IR::IROp_AtomicFetchNeg>();
+
+  Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Header.Args[0].ID());
+  switch (Op->Size) {
+    case 1: {
+      mov(TMP1.cvt8(), byte [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt8(), TMP1.cvt8());
+      mov(TMP3.cvt8(), TMP1.cvt8());
+      neg(TMP2.cvt8());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(byte [MemReg], TMP2.cvt8());
+      jne(Loop);
+      // Result is the previous value from memory, which is currently in TMP3
+      movzx(GetDst<RA_64>(Node), TMP3.cvt8());
+      break;
+    }
+    case 2: {
+      mov(TMP1.cvt16(), word [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt16(), TMP1.cvt16());
+      mov(TMP3.cvt16(), TMP1.cvt16());
+      neg(TMP2.cvt16());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(word [MemReg], TMP2.cvt16());
+      jne(Loop);
+
+      // Result is the previous value from memory, which is currently in TMP3
+      movzx(GetDst<RA_64>(Node), TMP3.cvt16());
+      break;
+    }
+    case 4: {
+      mov(TMP1.cvt32(), dword [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt32(), TMP1.cvt32());
+      mov(TMP3.cvt32(), TMP1.cvt32());
+      neg(TMP2.cvt32());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(dword [MemReg], TMP2.cvt32());
+      jne(Loop);
+
+      // Result is the previous value from memory, which is currently in TMP3
+      mov(GetDst<RA_32>(Node), TMP3.cvt32());
+      break;
+    }
+    case 8: {
+      mov(TMP1.cvt64(), qword [MemReg]);
+
+      Label Loop;
+      L(Loop);
+      mov(TMP2.cvt64(), TMP1.cvt64());
+      mov(TMP3.cvt64(), TMP1.cvt64());
+      neg(TMP2.cvt64());
+
+      // Updates RAX with the value from memory
+      lock(); cmpxchg(qword [MemReg], TMP2.cvt64());
+      jne(Loop);
+
+      // Result is the previous value from memory, which is currently in TMP3
+      mov(GetDst<RA_64>(Node), TMP3.cvt64());
+      break;
+    }
+    default:  LOGMAN_MSG_A_FMT("Unhandled AtomicFetchNeg size: {}", Op->Size);
   }
 }
 
@@ -568,6 +644,7 @@ void X86JITCore::RegisterAtomicHandlers() {
   REGISTER_OP(ATOMICFETCHAND, AtomicFetchAnd);
   REGISTER_OP(ATOMICFETCHOR,  AtomicFetchOr);
   REGISTER_OP(ATOMICFETCHXOR, AtomicFetchXor);
+  REGISTER_OP(ATOMICFETCHNEG, AtomicFetchNeg);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp

@@ -4,6 +4,8 @@ tags: backend|x86-64
 $end_info$
 */
 
+#include "Interface/Core/LookupCache.h"
+
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
@@ -14,15 +16,15 @@ $end_info$
 namespace FEXCore::CPU {
 #define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
 DEF_OP(GuestCallDirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestCallIndirect) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(GuestReturn) {
-  LogMan::Msg::D("Unimplemented");
+  LogMan::Msg::DFmt("Unimplemented");
 }
 
 DEF_OP(SignalReturn) {

External/FEXCore/Source/Interface/Core/JIT/x86_64/ConversionOps.cpp

@@ -31,7 +31,7 @@ DEF_OP(VInsGPR) {
       pinsrq(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[1].ID()), Op->Index);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -52,7 +52,7 @@ DEF_OP(VCastFromGPR) {
     case 8:
       vmovq(GetDst(Node), GetSrc<RA_64>(Op->Header.Args[0].ID()).cvt64());
       break;
-    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown VCastFromGPR element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -91,7 +91,7 @@ DEF_OP(Float_FToF) {
       cvtsd2ss(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown FCVT sizes: 0x%x", Conv);
+    default: LOGMAN_MSG_A_FMT("Unknown Float_FToF sizes: 0x{:x}", Conv);
   }
 }
 
@@ -113,7 +113,7 @@ DEF_OP(Vector_SToF) {
       cvtsi2sd(xmm15, rax);
       movlhps(GetDst(Node), xmm15);
     break;
-    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_SToF element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -126,7 +126,7 @@ DEF_OP(Vector_FToZS) {
     case 8:
       cvttpd2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToZS element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -139,7 +139,7 @@ DEF_OP(Vector_FToS) {
     case 8:
       cvtpd2dq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown castGPR element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToS element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -156,7 +156,7 @@ DEF_OP(Vector_FToF) {
       cvtpd2ps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Conversion Type : 0%04x", Conv); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Vector_FToF conversion type : 0x{:04x}", Conv); break;
   }
 }
 

External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp

@@ -6,6 +6,7 @@ $end_info$
 */
 
 #include "Interface/Context/Context.h"
+#include "Interface/Core/LookupCache.h"
 
 #include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include "Interface/Core/JIT/x86_64/JITClass.h"
@@ -36,7 +37,7 @@ CodeBuffer AllocateNewCodeBuffer(size_t Size) {
                     PROT_READ | PROT_WRITE | PROT_EXEC,
                     MAP_PRIVATE | MAP_ANONYMOUS,
                     -1, 0));
-  LOGMAN_THROW_A(Buffer.Ptr != reinterpret_cast<uint8_t*>(~0ULL), "Couldn't allocate code buffer");
+  LOGMAN_THROW_A_FMT(Buffer.Ptr != reinterpret_cast<uint8_t*>(~0ULL), "Couldn't allocate code buffer");
   return Buffer;
 }
 
@@ -54,9 +55,9 @@ void X86JITCore::CopyNecessaryDataForCompileThread(CPUBackend *Original) {
 }
 
 void X86JITCore::PushRegs() {
-  for (auto &Xmm : RAXMM_x) {
-    sub(rsp, 16);
-    movaps(ptr[rsp], Xmm);
+  sub(rsp, 16 * RAXMM_x.size());
+  for (size_t i = 0; i < RAXMM_x.size(); ++i) {
+    movaps(ptr[rsp + i * 16], RAXMM_x[i]);
   }
 
   for (auto &Reg : RA64)
@@ -75,18 +76,18 @@ void X86JITCore::PopRegs() {
   for (uint32_t i = RA64.size(); i > 0; --i)
     pop(RA64[i - 1]);
 
-  for (uint32_t i = RAXMM_x.size(); i > 0; --i) {
-    movaps(RAXMM_x[i - 1], ptr[rsp]);
-    add(rsp, 16);
+  for (size_t i = 0; i < RAXMM_x.size(); ++i) {
+    movaps(RAXMM_x[i], ptr[rsp + i * 16]);
   }
+
+  add(rsp, 16 * RAXMM_x.size());
 }
 
 void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
   FallbackInfo Info;
   if (!InterpreterOps::GetFallbackHandler(IROp, &Info)) {
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-    auto Name = FEXCore::IR::GetName(IROp->Op);
-    LOGMAN_MSG_A("Unhandled IR Op: %s", std::string(Name).c_str());
+    LOGMAN_MSG_A_FMT("Unhandled IR Op: {}", FEXCore::IR::GetName(IROp->Op));
 #endif
   } else {
     switch(Info.ABI) {
@@ -285,8 +286,7 @@ void X86JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
       case FABI_UNKNOWN:
       default:
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
-      auto Name = FEXCore::IR::GetName(IROp->Op);
-        LOGMAN_MSG_A("Unhandled IR Fallback abi: %s %d", std::string(Name).c_str(), Info.ABI);
+        LOGMAN_MSG_A_FMT("Unhandled IR Fallback ABI: {} {}", FEXCore::IR::GetName(IROp->Op), Info.ABI);
 #endif
         break;
     }
@@ -419,7 +419,7 @@ void X86JITCore::ClearCache() {
 IR::PhysicalRegister X86JITCore::GetPhys(uint32_t Node) const {
   auto PhyReg = RAData->GetNodeRegister(Node);
 
-  LOGMAN_THROW_A(PhyReg.Raw != 255, "Couldn't Allocate register for node: ssa%d. Class: %d", Node, PhyReg.Class);
+  LOGMAN_THROW_A_FMT(PhyReg.Raw != 255, "Couldn't Allocate register for node: ssa{}. Class: {}", Node, PhyReg.Class);
 
   return PhyReg;
 }
@@ -568,7 +568,7 @@ std::tuple<X86JITCore::SetCC, X86JITCore::CMovCC, X86JITCore::JCC> X86JITCore::G
     case FEXCore::IR::COND_VS:
     case FEXCore::IR::COND_VC:
     default:
-      LOGMAN_MSG_A("Unsupported compare type");
+      LOGMAN_MSG_A_FMT("Unsupported compare type");
       break;
   }
 
@@ -611,7 +611,7 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
     L(RunBlock);
   }
 
-  LOGMAN_THROW_A(RAData != nullptr, "Needs RA");
+  LOGMAN_THROW_A_FMT(RAData != nullptr, "Needs RA");
 
   SpillSlots = RAData->SpillSlots();
 
@@ -669,7 +669,7 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
     {
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
       auto BlockIROp = BlockHeader->CW<IROp_CodeBlock>();
-      LOGMAN_THROW_A(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
+      LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == IR::OP_CODEBLOCK, "IR type failed to be a code block");
 #endif
 
       uint32_t Node = IR->GetID(BlockNode);
@@ -721,7 +721,7 @@ void *X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRLi
             Inst << "Reg" << GetPhys(ArgNode) << (i + 1 == NumArgs ? "" : ", ");
         }
 
-        LogMan::Msg::D("%s", Inst.str().c_str());
+        LogMan::Msg::DFmt("{}", Inst.str());
       }
       #endif
       uint32_t ID = IR->GetID(CodeNode);

External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h

@@ -6,7 +6,6 @@ $end_info$
 
 #pragma once
 
-#include "Interface/Core/LookupCache.h"
 #include "Interface/Core/BlockSamplingData.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 
@@ -260,6 +259,7 @@ private:
   DEF_OP(AtomicFetchAnd);
   DEF_OP(AtomicFetchOr);
   DEF_OP(AtomicFetchXor);
+  DEF_OP(AtomicFetchNeg);
 
   ///< Branch ops
   DEF_OP(GuestCallDirect);

External/FEXCore/Source/Interface/Core/JIT/x86_64/MemoryOps.cpp

@@ -36,10 +36,10 @@ DEF_OP(LoadContext) {
     }
     break;
     case 16: {
-      LOGMAN_MSG_A("Invalid GPR load of size 16");
+      LOGMAN_MSG_A_FMT("Invalid GPR load of size 16");
     }
     break;
-    default:  LOGMAN_MSG_A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
     }
   }
   else {
@@ -69,7 +69,7 @@ DEF_OP(LoadContext) {
         movups(GetDst(Node), xword [STATE + Op->Offset]);
     }
     break;
-    default:  LOGMAN_MSG_A("Unhandled LoadContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize);
     }
   }
 }
@@ -98,9 +98,9 @@ DEF_OP(StoreContext) {
     }
     break;
     case 16:
-      LogMan::Msg::D("Invalid store size of 16");
+      LogMan::Msg::DFmt("Invalid store size of 16");
     break;
-    default:  LOGMAN_MSG_A("Unhandled StoreContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
     }
   }
   else {
@@ -129,7 +129,7 @@ DEF_OP(StoreContext) {
         movups(xword [STATE + Op->Offset], GetSrc(Op->Header.Args[0].ID()));
     }
     break;
-    default:  LOGMAN_MSG_A("Unhandled StoreContext size: %d", OpSize);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreContext size: {}", OpSize);
     }
   }
 }
@@ -160,17 +160,18 @@ DEF_OP(LoadContextIndexed) {
         mov(GetDst<RA_64>(Node),  qword [rax + index * Op->Stride]);
         break;
       default:
-        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     case 16:
-      LOGMAN_MSG_A("Invalid Class load of size 16");
+      LOGMAN_MSG_A_FMT("Invalid Class load of size 16");
       break;
     default:
-      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed stride: {}", Op->Stride);
+      break;
     }
-
   }
   else {
     switch (Op->Stride) {
@@ -195,7 +196,8 @@ DEF_OP(LoadContextIndexed) {
         vmovq(GetDst(Node),  qword [rax + index * Op->Stride]);
         break;
       default:
-        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
@@ -223,12 +225,14 @@ DEF_OP(LoadContextIndexed) {
           movups(GetDst(Node), xword [STATE + rax]);
         break;
       default:
-        LOGMAN_MSG_A("Unhandled LoadContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed size: {}", Op->Size);
+        break;
       }
       break;
     }
     default:
-      LOGMAN_MSG_A("Unhandled LoadContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled LoadContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
 }
@@ -248,13 +252,14 @@ DEF_OP(StoreContextIndexed) {
     case 4:
     case 8: {
       if (!(size == 1 || size == 2 || size == 4 || size == 8)) {
-        LOGMAN_MSG_A("Unhandled StoreContextIndexed size: %d", Op->Size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", Op->Size);
       }
       mov(AddressFrame(Op->Size * 8) [rax + index * Op->Stride], value);
       break;
     }
     default:
-      LOGMAN_MSG_A("Unhandled StoreContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
   else {
@@ -279,7 +284,8 @@ DEF_OP(StoreContextIndexed) {
         vmovq(AddressFrame(Op->Size * 8) [rax + index * Op->Stride], value);
         break;
       default:
-        LOGMAN_MSG_A("Unhandled StoreContextIndexed size: %d", size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", size);
+        break;
       }
       break;
     }
@@ -307,12 +313,14 @@ DEF_OP(StoreContextIndexed) {
           movups(xword [STATE + rax], value);
         break;
       default:
-        LOGMAN_MSG_A("Unhandled StoreContextIndexed size: %d", size);
+        LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed size: {}", size);
+        break;
       }
       break;
     }
     default:
-      LOGMAN_MSG_A("Unhandled StoreContextIndexed stride: %d", Op->Stride);
+      LOGMAN_MSG_A_FMT("Unhandled StoreContextIndexed stride: {}", Op->Stride);
+      break;
     }
   }
 }
@@ -340,7 +348,7 @@ DEF_OP(SpillRegister) {
         mov(qword [rsp + SlotOffset], GetSrc<RA_64>(Op->Header.Args[0].ID()));
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -356,10 +364,10 @@ DEF_OP(SpillRegister) {
         movaps(xword [rsp + SlotOffset], GetSrc(Op->Header.Args[0].ID()));
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled SpillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled SpillRegister size: {}", OpSize);
     }
   } else {
-    LOGMAN_MSG_A("Unhandled SpillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A_FMT("Unhandled SpillRegister class: {}", Op->Class.Val);
   }
 
 
@@ -388,7 +396,7 @@ DEF_OP(FillRegister) {
         mov(GetDst<RA_64>(Node), qword [rsp + SlotOffset]);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled FillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled FillRegister size: {}", OpSize);
     }
   } else if (Op->Class == FEXCore::IR::FPRClass) {
     switch (OpSize) {
@@ -404,10 +412,10 @@ DEF_OP(FillRegister) {
         movaps(GetDst(Node), xword [rsp + SlotOffset]);
         break;
       }
-      default:  LOGMAN_MSG_A("Unhandled FillRegister size: %d", OpSize);
+      default:  LOGMAN_MSG_A_FMT("Unhandled FillRegister size: {}", OpSize);
     }
   } else {
-    LOGMAN_MSG_A("Unhandled FillRegister class: %d", Op->Class.Val);
+    LOGMAN_MSG_A_FMT("Unhandled FillRegister class: {}", Op->Class.Val);
   }
 }
 
@@ -430,11 +438,11 @@ Xbyak::RegExp X86JITCore::GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper
     return Base;
   } else {
     if (OffsetScale != 1 && OffsetScale != 2 && OffsetScale != 4 && OffsetScale != 8) {
-      LOGMAN_MSG_A("Unhandled GenerateModRM OffsetScale: %d", OffsetScale);
+      LOGMAN_MSG_A_FMT("Unhandled GenerateModRM OffsetScale: {}", OffsetScale);
     }
 
     if (OffsetType != IR::MEM_OFFSET_SXTX) {
-      LOGMAN_MSG_A("Unhandled GenerateModRM OffsetType: %d", OffsetType.Val);
+      LOGMAN_MSG_A_FMT("Unhandled GenerateModRM OffsetType: {}", OffsetType.Val);
     }
 
     uint64_t Const;
@@ -475,7 +483,7 @@ DEF_OP(LoadMem) {
         mov(Dst, qword [MemPtr]);
       }
       break;
-      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMem size: {}", Op->Size);
     }
   }
   else
@@ -511,7 +519,7 @@ DEF_OP(LoadMem) {
          }
        }
        break;
-      default:  LOGMAN_MSG_A("Unhandled LoadMem size: %d", Op->Size);
+      default:  LOGMAN_MSG_A_FMT("Unhandled LoadMem size: {}", Op->Size);
     }
   }
 }
@@ -537,7 +545,7 @@ DEF_OP(StoreMem) {
     case 8:
       mov(qword [MemPtr], GetSrc<RA_64>(Op->Header.Args[1].ID()));
     break;
-    default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", Op->Size);
     }
   }
   else {
@@ -560,17 +568,17 @@ DEF_OP(StoreMem) {
       else
         movups(xword [MemPtr], GetSrc(Op->Header.Args[1].ID()));
     break;
-    default:  LOGMAN_MSG_A("Unhandled StoreMem size: %d", Op->Size);
+    default:  LOGMAN_MSG_A_FMT("Unhandled StoreMem size: {}", Op->Size);
     }
   }
 }
 
 DEF_OP(VLoadMemElement) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VStoreMemElement) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(CacheLineClear) {

External/FEXCore/Source/Interface/Core/JIT/x86_64/MiscOps.cpp

@@ -9,11 +9,11 @@ $end_info$
 
 namespace FEXCore::CPU {
 static void PrintValue(uint64_t Value) {
-  LogMan::Msg::D("Value: 0x%lx", Value);
+  LogMan::Msg::DFmt("Value: 0x{:x}", Value);
 }
 
 static void PrintVectorValue(uint64_t Value, uint64_t ValueUpper) {
-  LogMan::Msg::D("Value: 0x%016lx'%016lx", ValueUpper, Value);
+  LogMan::Msg::DFmt("Value: 0x{:016x}'{:016x}", ValueUpper, Value);
 }
 
 #define DEF_OP(x) void X86JITCore::Op_##x(FEXCore::IR::IROp_Header *IROp, uint32_t Node)
@@ -30,7 +30,7 @@ DEF_OP(Fence) {
     case IR::Fence_Store.Val:
       sfence();
       break;
-    default: LOGMAN_MSG_A("Unknown Fence: %d", Op->Fence); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Fence: {}", Op->Fence); break;
   }
 }
 
@@ -83,7 +83,7 @@ DEF_OP(Break) {
       }
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Break reason: %d", Op->Reason);
+    default: LOGMAN_MSG_A_FMT("Unknown Break reason: {}", Op->Reason);
   }
 }
 

External/FEXCore/Source/Interface/Core/JIT/x86_64/MoveOps.cpp

@@ -25,7 +25,7 @@ DEF_OP(ExtractElementPair) {
       mov (GetDst<RA_64>(Node), Regs[Op->Element]);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
   }
 }
 
@@ -51,7 +51,7 @@ DEF_OP(CreateElementPair) {
       RegTmp = rax;
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Size"); break;
   }
 
   if (Dst.first != RegSecond) {

External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp

@@ -62,24 +62,24 @@ DEF_OP(VectorImm) {
 }
 
 DEF_OP(CreateVector2) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(CreateVector4) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(SplatVector) {
   auto Op = IROp->C<IR::IROp_SplatVector2>();
   uint8_t OpSize = IROp->Size;
 
-  LOGMAN_THROW_A(OpSize <= 16, "Can't handle a vector of size: %d", OpSize);
+  LOGMAN_THROW_A_FMT(OpSize <= 16, "Can't handle a vector of size: {}", OpSize);
   uint8_t Elements = 0;
 
   switch (Op->Header.Op) {
     case IR::OP_SPLATVECTOR4: Elements = 4; break;
     case IR::OP_SPLATVECTOR2: Elements = 2; break;
-    default: LOGMAN_MSG_A("Uknown Splat size"); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Splat size"); break;
   }
 
   uint8_t ElementSize = OpSize / Elements;
@@ -92,7 +92,7 @@ DEF_OP(SplatVector) {
     case 8:
       movddup(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.Size); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.Size); break;
   }
 }
 
@@ -130,7 +130,7 @@ DEF_OP(VMov) {
       movaps(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", OpSize); break;
   }
 }
 
@@ -176,7 +176,7 @@ DEF_OP(VAdd) {
       vpaddq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -199,7 +199,7 @@ DEF_OP(VSub) {
       vpsubq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -214,7 +214,7 @@ DEF_OP(VUQAdd) {
       vpaddusw(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -229,7 +229,7 @@ DEF_OP(VUQSub) {
       vpsubusw(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -244,7 +244,7 @@ DEF_OP(VSQAdd) {
       vpaddsw(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -259,7 +259,7 @@ DEF_OP(VSQSub) {
       vpsubsw(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -296,7 +296,7 @@ DEF_OP(VAddP) {
       case 4:
         vphaddd(GetDst(Node), xmm15, xmm14);
         break;
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -325,7 +325,7 @@ DEF_OP(VAddP) {
       case 4:
         vphaddd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
         break;
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -357,7 +357,7 @@ DEF_OP(VAddV) {
       pinsrd(xmm15, eax, 0);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 
   movaps(Dest, xmm15);
@@ -376,7 +376,7 @@ DEF_OP(VUMinV) {
       pinsrw(Dest, eax, 1);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -391,7 +391,7 @@ DEF_OP(VURAvg) {
       vpavgw(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -414,7 +414,7 @@ DEF_OP(VAbs) {
       vpabsq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -438,7 +438,7 @@ DEF_OP(VPopcount) {
       }
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 
   movaps(Dest, xmm15);
@@ -459,7 +459,7 @@ DEF_OP(VFAdd) {
         vaddsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -473,7 +473,7 @@ DEF_OP(VFAdd) {
         vaddpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -487,7 +487,7 @@ DEF_OP(VFAddP) {
     case 8:
       vhaddpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -506,7 +506,7 @@ DEF_OP(VFSub) {
         vsubsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -520,7 +520,7 @@ DEF_OP(VFSub) {
         vsubpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -540,7 +540,7 @@ DEF_OP(VFMul) {
         vmulsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -554,7 +554,7 @@ DEF_OP(VFMul) {
         vmulpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -574,7 +574,7 @@ DEF_OP(VFDiv) {
         vdivsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -588,7 +588,7 @@ DEF_OP(VFDiv) {
         vdivpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -608,7 +608,7 @@ DEF_OP(VFMin) {
         vminsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -622,7 +622,7 @@ DEF_OP(VFMin) {
         vminpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -642,7 +642,7 @@ DEF_OP(VFMax) {
         vmaxsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -656,7 +656,7 @@ DEF_OP(VFMax) {
         vmaxpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -674,7 +674,7 @@ DEF_OP(VFRecp) {
         vdivss(GetDst(Node), xmm15, GetSrc(Op->Header.Args[0].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -687,7 +687,7 @@ DEF_OP(VFRecp) {
         vdivps(GetDst(Node), xmm15, GetSrc(Op->Header.Args[0].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -707,7 +707,7 @@ DEF_OP(VFSqrt) {
         vsqrtsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[0].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -721,7 +721,7 @@ DEF_OP(VFSqrt) {
         vsqrtpd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -747,7 +747,7 @@ DEF_OP(VFRSqrt) {
         divsd(GetDst(Node), xmm15);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -761,7 +761,7 @@ DEF_OP(VFRSqrt) {
         divps(GetDst(Node), xmm15);
       break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -786,7 +786,7 @@ DEF_OP(VNeg) {
       vpsubq(GetDst(Node), xmm15, GetSrc(Op->Header.Args[0].ID()));
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -807,7 +807,7 @@ DEF_OP(VFNeg) {
       vxorpd(GetDst(Node), xmm15, GetSrc(Op->Header.Args[0].ID()));
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -830,7 +830,7 @@ DEF_OP(VUMin) {
         pinsrq(GetDst(Node), TMP2, 0);
         break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -847,7 +847,7 @@ DEF_OP(VUMin) {
         vpminud(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
         break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -867,7 +867,7 @@ DEF_OP(VSMin) {
       vpminsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -886,7 +886,7 @@ DEF_OP(VUMax) {
       vpmaxud(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -905,7 +905,7 @@ DEF_OP(VSMax) {
       vpmaxsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -930,7 +930,7 @@ DEF_OP(VZip) {
       punpcklqdq(xmm15, GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
   movapd(GetDst(Node), xmm15);
 }
@@ -957,7 +957,7 @@ DEF_OP(VZip2) {
       vpunpckhdq(GetDst(Node), xmm15, xmm14);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
   else {
@@ -978,7 +978,7 @@ DEF_OP(VZip2) {
       punpckhqdq(xmm15, GetSrc(Op->Header.Args[1].ID()));
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
     movapd(GetDst(Node), xmm15);
   }
@@ -989,7 +989,7 @@ DEF_OP(VUnZip) {
   uint8_t OpSize = IROp->Size;
 
   if (OpSize == 8) {
-    LOGMAN_MSG_A("Unsupported registersize on VunZip");
+    LOGMAN_MSG_A_FMT("Unsupported register size on VUnZip");
   }
   else {
     switch (Op->Header.ElementSize) {
@@ -1031,7 +1031,7 @@ DEF_OP(VUnZip) {
           0b0'0);
         break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1042,7 +1042,7 @@ DEF_OP(VUnZip2) {
 
 
   if (OpSize == 8) {
-    LOGMAN_MSG_A("Unsupported registersize on VunZip");
+    LOGMAN_MSG_A_FMT("Unsupported register size on VUnZip2");
   }
   else {
     switch (Op->Header.ElementSize) {
@@ -1084,7 +1084,7 @@ DEF_OP(VUnZip2) {
           0b1'1);
         break;
       }
-      default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+      default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
     }
   }
 }
@@ -1113,7 +1113,7 @@ DEF_OP(VCMPEQ) {
     case 8:
       vpcmpeqq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -1134,7 +1134,7 @@ DEF_OP(VCMPEQZ) {
     case 8:
       vpcmpeqq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), xmm15);
       break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -1154,7 +1154,7 @@ DEF_OP(VCMPGT) {
     case 8:
       vpcmpgtq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -1175,7 +1175,7 @@ DEF_OP(VCMPGTZ) {
     case 8:
       vpcmpgtq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), xmm15);
       break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -1196,7 +1196,7 @@ DEF_OP(VCMPLTZ) {
     case 8:
       vpcmpgtq(GetDst(Node), xmm15, GetSrc(Op->Header.Args[0].ID()));
       break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -1212,7 +1212,7 @@ DEF_OP(VFCMPEQ) {
     case 8:
       vcmpsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 0);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
   else {
@@ -1223,7 +1223,7 @@ DEF_OP(VFCMPEQ) {
     case 8:
       vcmppd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 0);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
 }
@@ -1240,7 +1240,7 @@ DEF_OP(VFCMPNEQ) {
     case 8:
       vcmpsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 4);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
 
   }
@@ -1252,7 +1252,7 @@ DEF_OP(VFCMPNEQ) {
     case 8:
       vcmppd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 4);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
 }
@@ -1269,7 +1269,7 @@ DEF_OP(VFCMPLT) {
     case 8:
       vcmpsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 1);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
   else {
@@ -1280,7 +1280,7 @@ DEF_OP(VFCMPLT) {
     case 8:
       vcmppd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 1);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
 }
@@ -1297,7 +1297,7 @@ DEF_OP(VFCMPGT) {
     case 8:
       vcmpsd(GetDst(Node), GetSrc(Op->Header.Args[1].ID()), GetSrc(Op->Header.Args[0].ID()), 1);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
   else {
@@ -1308,7 +1308,7 @@ DEF_OP(VFCMPGT) {
     case 8:
       vcmppd(GetDst(Node), GetSrc(Op->Header.Args[1].ID()), GetSrc(Op->Header.Args[0].ID()), 1);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
 }
@@ -1325,7 +1325,7 @@ DEF_OP(VFCMPLE) {
     case 8:
       vcmpsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 2);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
   else {
@@ -1336,7 +1336,7 @@ DEF_OP(VFCMPLE) {
     case 8:
       vcmppd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 2);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
 }
@@ -1353,7 +1353,7 @@ DEF_OP(VFCMPORD) {
     case 8:
       vcmpsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 7);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
   else {
@@ -1364,7 +1364,7 @@ DEF_OP(VFCMPORD) {
     case 8:
       vcmppd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 7);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
 }
@@ -1381,7 +1381,7 @@ DEF_OP(VFCMPUNO) {
     case 8:
       vcmpsd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 3);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
   else {
@@ -1392,21 +1392,21 @@ DEF_OP(VFCMPUNO) {
     case 8:
       vcmppd(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()), 3);
     break;
-    default: LOGMAN_MSG_A("Unsupported elementSize: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unsupported element size: {}", Op->Header.ElementSize);
     }
   }
 }
 
 DEF_OP(VUShl) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VUShr) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VSShr) {
-  LOGMAN_MSG_A("Unimplemented");
+  LOGMAN_MSG_A_FMT("Unimplemented");
 }
 
 DEF_OP(VUShlS) {
@@ -1425,7 +1425,7 @@ DEF_OP(VUShlS) {
       vpsllq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1445,7 +1445,7 @@ DEF_OP(VUShrS) {
       vpsrlq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1462,7 +1462,7 @@ DEF_OP(VSShrS) {
       break;
     }
     case 8: // Doesn't exist on x86
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1495,7 +1495,7 @@ DEF_OP(VInsElement) {
     pinsrq(xmm15, rax, Op->DestIdx);
   break;
   }
-  default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 
   movapd(GetDst(Node), xmm15);
@@ -1530,7 +1530,7 @@ DEF_OP(VInsScalarElement) {
     pinsrq(xmm15, rax, Op->DestIdx);
   break;
   }
-  default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+  default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 
   movapd(GetDst(Node), xmm15);
@@ -1560,7 +1560,7 @@ DEF_OP(VExtractElement) {
       pinsrq(GetDst(Node), rax, 0);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1613,7 +1613,7 @@ DEF_OP(VDupElement) {
         (Op->Index << 1));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1666,7 +1666,7 @@ DEF_OP(VUShrI) {
       psrlq(GetDst(Node), Op->BitShift);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1704,7 +1704,7 @@ DEF_OP(VSShrI) {
       }
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1724,7 +1724,7 @@ DEF_OP(VShlI) {
       psllq(GetDst(Node), Op->BitShift);
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1754,7 +1754,7 @@ DEF_OP(VUShrNI) {
       mov(rcx, 0x80'80'80'80'80'80'80'80); // Upper
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 
   vmovq(xmm15, rax);
@@ -1790,7 +1790,7 @@ DEF_OP(VUShrNI2) {
       mov(rcx, 0x0B'0A'09'08'03'02'01'00); // Upper
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 
   vmovq(xmm15, rax);
@@ -1817,7 +1817,7 @@ DEF_OP(VSXTL) {
     case 8:
       pmovsxdq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -1836,7 +1836,7 @@ DEF_OP(VSXTL2) {
     case 8:
       pmovsxdq(GetDst(Node), GetDst(Node));
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -1852,7 +1852,7 @@ DEF_OP(VUXTL) {
     case 8:
       pmovzxdq(GetDst(Node), GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -1871,7 +1871,7 @@ DEF_OP(VUXTL2) {
     case 8:
       pmovzxdq(GetDst(Node), GetDst(Node));
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 }
 
@@ -1884,7 +1884,7 @@ DEF_OP(VSQXTN) {
     case 2:
       packssdw(xmm15, GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
   psrldq(xmm15, 8);
   movaps(GetDst(Node), xmm15);
@@ -1903,7 +1903,7 @@ DEF_OP(VSQXTN2) {
     case 2:
       packssdw(xmm15, GetSrc(Op->Header.Args[1].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
 
   if (OpSize == 8) {
@@ -1921,7 +1921,7 @@ DEF_OP(VSQXTUN) {
     case 2:
       packusdw(xmm15, GetSrc(Op->Header.Args[0].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
   psrldq(xmm15, 8);
   movaps(GetDst(Node), xmm15);
@@ -1940,7 +1940,7 @@ DEF_OP(VSQXTUN2) {
     case 2:
       packusdw(xmm15, GetSrc(Op->Header.Args[1].ID()));
     break;
-    default: LOGMAN_MSG_A("Unknown element size: %d", Op->Header.ElementSize);
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize);
   }
   if (OpSize == 8) {
     psrldq(xmm15, OpSize / 2);
@@ -1960,7 +1960,7 @@ DEF_OP(VMul) {
       vpmulld(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -1991,7 +1991,7 @@ DEF_OP(VUMull) {
       vpmuludq(GetDst(Node), xmm14, xmm15);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -2026,7 +2026,7 @@ DEF_OP(VSMull) {
       vpmuldq(GetDst(Node), xmm14, xmm15);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -2062,7 +2062,7 @@ DEF_OP(VUMull2) {
       vpmuludq(GetDst(Node), xmm14, xmm15);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -2102,7 +2102,7 @@ DEF_OP(VSMull2) {
       vpmuldq(GetDst(Node), xmm14, xmm15);
     break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -2123,7 +2123,7 @@ DEF_OP(VUABDL) {
       vpabsd(GetDst(Node), GetDst(Node));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown Element Size: %d", Op->Header.ElementSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown Element Size: {}", Op->Header.ElementSize); break;
   }
 }
 
@@ -2141,7 +2141,7 @@ DEF_OP(VTBL1) {
       vpshufb(GetDst(Node), GetSrc(Op->Header.Args[0].ID()), GetSrc(Op->Header.Args[1].ID()));
       break;
     }
-    default: LOGMAN_MSG_A("Unknown OpSize: %d", OpSize); break;
+    default: LOGMAN_MSG_A_FMT("Unknown OpSize: {}", OpSize); break;
   }
 }
 

External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -270,15 +270,15 @@ public:
   template<size_t ElementSize, bool HalfSize, bool Low>
   void PSHUFDOp(OpcodeArgs);
   void MOVDOp(OpcodeArgs);
-  template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
+  template<size_t ElementSize>
   void PSRLDOp(OpcodeArgs);
   template<size_t ElementSize>
   void PSRLI(OpcodeArgs);
   template<size_t ElementSize>
   void PSLLI(OpcodeArgs);
-  template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
+  template<size_t ElementSize>
   void PSLL(OpcodeArgs);
-  template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
+  template<size_t ElementSize>
   void PSRAOp(OpcodeArgs);
   void PSRLDQ(OpcodeArgs);
   void PSLLDQ(OpcodeArgs);
@@ -299,9 +299,9 @@ public:
   void Vector_CVT_Float_To_Float(OpcodeArgs);
   template<size_t SrcElementSize, bool Narrow, bool HostRoundingMode>
   void Vector_CVT_Float_To_Int(OpcodeArgs);
-  template<size_t SrcElementSize, bool Signed, bool Widen>
+  template<size_t SrcElementSize, bool Widen>
   void MMX_To_XMM_Vector_CVT_Int_To_Float(OpcodeArgs);
-  template<size_t SrcElementSize, bool Narrow, bool HostRoundingMode>
+  template<size_t SrcElementSize, bool HostRoundingMode>
   void XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs);
   void MASKMOVOp(OpcodeArgs);
   void MOVBetweenGPR_FPR(OpcodeArgs);
@@ -380,6 +380,8 @@ public:
   void X87FRSTOR(OpcodeArgs);
   void X87FXAM(OpcodeArgs);
   void X87FCMOV(OpcodeArgs);
+  void X87EMMS(OpcodeArgs);
+  void X87FFREE(OpcodeArgs);
 
   void FXCH(OpcodeArgs);
 
@@ -501,9 +503,19 @@ private:
   uint8_t GetSrcSize(FEXCore::X86Tables::DecodedOp Op) const;
 
   template<unsigned BitOffset>
-  void SetRFLAG(OrderedNode *Value);
-  void SetRFLAG(OrderedNode *Value, unsigned BitOffset);
-  OrderedNode *GetRFLAG(unsigned BitOffset);
+  void SetRFLAG(OrderedNode *Value) {
+    flagsOp = FLAGS_OP_NONE;
+    _StoreFlag(_Bfe(1, 0, Value), BitOffset);
+  }
+
+  void SetRFLAG(OrderedNode *Value, unsigned BitOffset) {
+    flagsOp = FLAGS_OP_NONE;
+    _StoreFlag(_Bfe(1, 0, Value), BitOffset);
+  }
+
+  OrderedNode *GetRFLAG(unsigned BitOffset) {
+    return _LoadFlag(BitOffset);
+  }
 
   OrderedNode *SelectCC(uint8_t OP, OrderedNode *TrueValue, OrderedNode *FalseValue);
 
@@ -526,6 +538,14 @@ private:
   void GenerateFlags_RotateLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
 
   OrderedNode * GetX87Top();
+  enum X87Tag {
+    TAG_VALID   = 0b00,
+    TAG_ZERO    = 0b01,
+    TAG_SPECIAL = 0b10,
+    TAG_EMPTY   = 0b11
+  };
+  void SetX87TopTag(OrderedNode *Value, uint32_t Tag);
+  OrderedNode *GetX87FTW(OrderedNode *Value);
   void SetX87Top(OrderedNode *Value);
 
   bool DestIsLockedMem(FEXCore::X86Tables::DecodedOp Op) const {

External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp

@@ -0,0 +1,58 @@
+/*
+$info$
+tags: frontend|x86-to-ir, opcodes|dispatcher-implementations
+desc: Handles x86/64 Crypto instructions to IR
+$end_info$
+*/
+
+#include "Interface/Core/OpcodeDispatcher.h"
+
+#include <FEXCore/Core/X86Enums.h>
+
+namespace FEXCore::IR {
+#define OpcodeArgs [[maybe_unused]] FEXCore::X86Tables::DecodedOp Op
+
+void OpDispatchBuilder::AESImcOp(OpcodeArgs) {
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  auto Res = _VAESImc(Src);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+void OpDispatchBuilder::AESEncOp(OpcodeArgs) {
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  auto Res = _VAESEnc(Dest, Src);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+void OpDispatchBuilder::AESEncLastOp(OpcodeArgs) {
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  auto Res = _VAESEncLast(Dest, Src);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+void OpDispatchBuilder::AESDecOp(OpcodeArgs) {
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  auto Res = _VAESDec(Dest, Src);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+void OpDispatchBuilder::AESDecLastOp(OpcodeArgs) {
+  OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  auto Res = _VAESDecLast(Dest, Src);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+void OpDispatchBuilder::AESKeyGenAssist(OpcodeArgs) {
+  OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
+  LOGMAN_THROW_A(Op->Src[1].IsLiteral(), "Src1 needs to be literal here");
+  uint64_t RCON = Op->Src[1].Data.Literal.Value;
+
+  auto Res = _VAESKeyGenAssist(Src, RCON);
+  StoreResult(FPRClass, Op, Res, -1);
+}
+
+}

External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp

@@ -0,0 +1,810 @@
+/*
+$info$
+tags: frontend|x86-to-ir, opcodes|dispatcher-implementations
+desc: Handles x86/64 flag generation
+$end_info$
+*/
+
+#include "Interface/Core/OpcodeDispatcher.h"
+
+#include <FEXCore/Core/X86Enums.h>
+
+namespace FEXCore::IR {
+constexpr std::array<uint32_t, 17> FlagOffsets = {
+  FEXCore::X86State::RFLAG_CF_LOC,
+  FEXCore::X86State::RFLAG_PF_LOC,
+  FEXCore::X86State::RFLAG_AF_LOC,
+  FEXCore::X86State::RFLAG_ZF_LOC,
+  FEXCore::X86State::RFLAG_SF_LOC,
+  FEXCore::X86State::RFLAG_TF_LOC,
+  FEXCore::X86State::RFLAG_IF_LOC,
+  FEXCore::X86State::RFLAG_DF_LOC,
+  FEXCore::X86State::RFLAG_OF_LOC,
+  FEXCore::X86State::RFLAG_IOPL_LOC,
+  FEXCore::X86State::RFLAG_NT_LOC,
+  FEXCore::X86State::RFLAG_RF_LOC,
+  FEXCore::X86State::RFLAG_VM_LOC,
+  FEXCore::X86State::RFLAG_AC_LOC,
+  FEXCore::X86State::RFLAG_VIF_LOC,
+  FEXCore::X86State::RFLAG_VIP_LOC,
+  FEXCore::X86State::RFLAG_ID_LOC,
+};
+
+void OpDispatchBuilder::SetPackedRFLAG(bool Lower8, OrderedNode *Src) {
+  uint8_t NumFlags = FlagOffsets.size();
+  if (Lower8) {
+    NumFlags = 5;
+  }
+  auto OneConst = _Constant(1);
+  for (int i = 0; i < NumFlags; ++i) {
+    auto Tmp = _And(_Lshr(Src, _Constant(FlagOffsets[i])), OneConst);
+    SetRFLAG(Tmp, FlagOffsets[i]);
+  }
+}
+
+OrderedNode *OpDispatchBuilder::GetPackedRFLAG(bool Lower8) {
+  OrderedNode *Original = _Constant(2);
+  uint8_t NumFlags = FlagOffsets.size();
+  if (Lower8) {
+    NumFlags = 5;
+  }
+
+  for (int i = 0; i < NumFlags; ++i) {
+    OrderedNode *Flag = _LoadFlag(FlagOffsets[i]);
+    Flag = _Bfe(4, 32, 0, Flag);
+    Flag = _Lshl(Flag, _Constant(FlagOffsets[i]));
+    Original = _Or(Original, Flag);
+  }
+  return Original;
+}
+
+void OpDispatchBuilder::GenerateFlags_ADC(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
+  auto Size = GetSrcSize(Op) * 8;
+  // AF
+  {
+    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
+    AFRes = _Bfe(1, 4, AFRes);
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(AFRes);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto PopCountOp = _Popcount(_And(Res, _Constant(0xFF)));
+
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // CF
+  // Unsigned
+  {
+    auto SelectOpLT = _Select(FEXCore::IR::COND_ULT, Res, Src2, _Constant(1), _Constant(0));
+    auto SelectOpLE = _Select(FEXCore::IR::COND_ULE, Res, Src2, _Constant(1), _Constant(0));
+    auto SelectCF   = _Select(FEXCore::IR::COND_EQ, CF, _Constant(1), SelectOpLE, SelectOpLT);
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectCF);
+  }
+
+  // OF
+  // Signed
+  {
+    auto NegOne = _Constant(~0ULL);
+    auto XorOp1 = _Xor(_Xor(Src1, Src2), NegOne);
+    auto XorOp2 = _Xor(Res, Src1);
+    OrderedNode *AndOp1 = _And(XorOp1, XorOp2);
+
+    switch (Size) {
+    case 8:
+      AndOp1 = _Bfe(1, 7, AndOp1);
+    break;
+    case 16:
+      AndOp1 = _Bfe(1, 15, AndOp1);
+    break;
+    case 32:
+      AndOp1 = _Bfe(1, 31, AndOp1);
+    break;
+    case 64:
+      AndOp1 = _Bfe(1, 63, AndOp1);
+    break;
+    default: LOGMAN_MSG_A("Unknown BFESize: %d", Size); break;
+    }
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(AndOp1);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_SBB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF) {
+  // AF
+  {
+    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
+    AFRes = _Bfe(1, 4, AFRes);
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(AFRes);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto PopCountOp = _Popcount(_And(Res, _Constant(0xFF)));
+
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // CF
+  // Unsigned
+  {
+    auto SelectOpLT = _Select(FEXCore::IR::COND_UGT, Res, Src1, _Constant(1), _Constant(0));
+    auto SelectOpLE = _Select(FEXCore::IR::COND_UGE, Res, Src1, _Constant(1), _Constant(0));
+    auto SelectCF   = _Select(FEXCore::IR::COND_EQ, CF, _Constant(1), SelectOpLE, SelectOpLT);
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectCF);
+  }
+
+  // OF
+  // Signed
+  {
+    auto XorOp1 = _Xor(Src1, Src2);
+    auto XorOp2 = _Xor(Res, Src1);
+    OrderedNode *AndOp1 = _And(XorOp1, XorOp2);
+
+    switch (GetSrcSize(Op)) {
+    case 1:
+      AndOp1 = _Bfe(1, 7, AndOp1);
+    break;
+    case 2:
+      AndOp1 = _Bfe(1, 15, AndOp1);
+    break;
+    case 4:
+      AndOp1 = _Bfe(1, 31, AndOp1);
+    break;
+    case 8:
+      AndOp1 = _Bfe(1, 63, AndOp1);
+    break;
+    default: LOGMAN_MSG_A("Unknown BFESize: %d", GetSrcSize(Op)); break;
+    }
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(AndOp1);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_SUB(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
+  // AF
+  {
+    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
+    AFRes = _Bfe(1, 4, AFRes);
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(AFRes);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // ZF
+  {
+    auto ZeroConst = _Constant(0);
+    auto OneConst = _Constant(1);
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, ZeroConst, OneConst, ZeroConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // CF
+  if (UpdateCF) {
+    auto ZeroConst = _Constant(0);
+    auto OneConst = _Constant(1);
+
+    auto SelectOp = _Select(FEXCore::IR::COND_ULT,
+        Src1, Src2, OneConst, ZeroConst);
+
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectOp);
+  }
+  // OF
+  {
+    auto XorOp1 = _Xor(Src1, Src2);
+    auto XorOp2 = _Xor(Res, Src1);
+    OrderedNode *FinalAnd = _And(XorOp1, XorOp2);
+
+    FinalAnd = _Bfe(1, GetSrcSize(Op) * 8 - 1, FinalAnd);
+
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(FinalAnd);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_ADD(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF) {
+  // AF
+  {
+    OrderedNode *AFRes = _Xor(_Xor(Src1, Src2), Res);
+    AFRes = _Bfe(1, 4, AFRes);
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(AFRes);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+  // CF
+  if (UpdateCF) {
+    auto SelectOp = _Select(FEXCore::IR::COND_ULT, Res, Src2, _Constant(1), _Constant(0));
+
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectOp);
+  }
+
+  // OF
+  {
+    auto NegOne = _Constant(~0ULL);
+    auto XorOp1 = _Xor(_Xor(Src1, Src2), NegOne);
+    auto XorOp2 = _Xor(Res, Src1);
+
+    OrderedNode *AndOp1 = _And(XorOp1, XorOp2);
+
+    switch (GetSrcSize(Op)) {
+    case 1:
+      AndOp1 = _Bfe(1, 7, AndOp1);
+    break;
+    case 2:
+      AndOp1 = _Bfe(1, 15, AndOp1);
+    break;
+    case 4:
+      AndOp1 = _Bfe(1, 31, AndOp1);
+    break;
+    case 8:
+      AndOp1 = _Bfe(1, 63, AndOp1);
+    break;
+    default: LOGMAN_MSG_A("Unknown BFESize: %d", GetSrcSize(Op)); break;
+    }
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(AndOp1);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_MUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *High) {
+  // PF/AF/ZF/SF
+  // Undefined
+  {
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(_Constant(0));
+  }
+
+  // CF/OF
+  {
+    // CF and OF are set if the result of the operation can't be fit in to the destination register
+    // If the value can fit then the top bits will be zero
+
+    auto SignBit = _Sbfe(1, GetSrcSize(Op) * 8 - 1, Res);
+
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ, High, SignBit, _Constant(0), _Constant(1));
+
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectOp);
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(SelectOp);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_UMUL(FEXCore::X86Tables::DecodedOp Op, OrderedNode *High) {
+  // AF/SF/PF/ZF
+  // Undefined
+  {
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(_Constant(0));
+  }
+
+  // CF/OF
+  {
+    // CF and OF are set if the result of the operation can't be fit in to the destination register
+    // The result register will be all zero if it can't fit due to how multiplication behaves
+
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ, High, _Constant(0), _Constant(0), _Constant(1));
+
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(SelectOp);
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(SelectOp);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_Logical(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // CF/OF
+  {
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Constant(0));
+  }
+}
+
+#define COND_FLAG_SET(cond, flag, newflag) \
+auto oldflag = GetRFLAG(FEXCore::X86State::flag);\
+auto newval = _Select(FEXCore::IR::COND_EQ, cond, _Constant(0), oldflag, newflag);\
+SetRFLAG<FEXCore::X86State::flag>(newval);
+
+void OpDispatchBuilder::GenerateFlags_ShiftLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    auto Size = _Constant(GetSrcSize(Op) * 8);
+    auto ShiftAmt = _Sub(Size, Src2);
+    auto LastBit = _And(_Lshr(Src1, ShiftAmt), _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_CF_LOC, LastBit);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_PF_LOC, XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    COND_FLAG_SET(Src2, RFLAG_AF_LOC, _Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    COND_FLAG_SET(Src2, RFLAG_ZF_LOC, SelectOp);
+  }
+
+  // SF
+  {
+    auto val = _Bfe(1, GetSrcSize(Op) * 8 - 1, Res);
+    COND_FLAG_SET(Src2, RFLAG_SF_LOC, val);
+  }
+
+  // OF
+  {
+    // In the case of left shift. OF is only set from the result of <Top Source Bit> XOR <Top Result Bit>
+    // When Shift > 1 then OF is undefined
+    auto val = _Bfe(1, GetSrcSize(Op) * 8 - 1, _Xor(Src1, Res));
+    COND_FLAG_SET(Src2, RFLAG_OF_LOC, val);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_ShiftRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    auto ShiftAmt = _Sub(Src2, _Constant(1));
+    auto LastBit = _And(_Lshr(Src1, ShiftAmt), _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_CF_LOC, LastBit);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_PF_LOC, XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    COND_FLAG_SET(Src2, RFLAG_AF_LOC, _Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    COND_FLAG_SET(Src2, RFLAG_ZF_LOC, SelectOp);
+  }
+
+  // SF
+  {
+    auto val =_Bfe(1, GetSrcSize(Op) * 8 - 1, Res);
+    COND_FLAG_SET(Src2, RFLAG_SF_LOC, val);
+  }
+
+  // OF
+  {
+    // Only defined when Shift is 1 else undefined
+    // OF flag is set if a sign change occurred
+    auto val = _Bfe(1, GetSrcSize(Op) * 8 - 1, _Xor(Src1, Res));
+    COND_FLAG_SET(Src2, RFLAG_OF_LOC, val);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_SignShiftRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    auto ShiftAmt = _Sub(Src2, _Constant(1));
+    auto LastBit = _And(_Lshr(Src1, ShiftAmt), _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_CF_LOC, LastBit);
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    COND_FLAG_SET(Src2, RFLAG_PF_LOC, XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    COND_FLAG_SET(Src2, RFLAG_AF_LOC, _Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    COND_FLAG_SET(Src2, RFLAG_ZF_LOC, SelectOp);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    COND_FLAG_SET(Src2, RFLAG_SF_LOC, LshrOp);
+  }
+
+  // OF
+  {
+    COND_FLAG_SET(Src2, RFLAG_OF_LOC, _Constant(0));
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_ShiftLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+  // No flags changed if shift is zero
+  if (Shift == 0) return;
+
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(1, GetSrcSize(Op) * 8 - Shift, Src1));
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // SF
+  {
+    auto LshrOp = _Bfe(1, GetSrcSize(Op) * 8 - 1, Res);
+
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+
+    // OF
+    // In the case of left shift. OF is only set from the result of <Top Source Bit> XOR <Top Result Bit>
+    if (Shift == 1) {
+      auto SourceBit = _Bfe(1, GetSrcSize(Op) * 8 - 1, Src1);
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Xor(SourceBit, LshrOp));
+    }
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_SignShiftRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+  // No flags changed if shift is zero
+  if (Shift == 0) return;
+
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(1, Shift-1, Src1));
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+
+    // OF
+    // Only defined when Shift is 1 else undefined
+    // Only is set if the top bit was set to 1 when shifted
+    // So it is set to same value as SF
+    if (Shift == 1) {
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Constant(0));
+    }
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_ShiftRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+  // No flags changed if shift is zero
+  if (Shift == 0) return;
+
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(1, Shift-1, Src1));
+  }
+
+  // PF
+  if (!CTX->Config.ABINoPF) {
+    auto EightBitMask = _Constant(0xFF);
+    auto PopCountOp = _Popcount(_And(Res, EightBitMask));
+    auto XorOp = _Xor(PopCountOp, _Constant(1));
+    SetRFLAG<FEXCore::X86State::RFLAG_PF_LOC>(XorOp);
+  } else {
+    _InvalidateFlags(1UL << FEXCore::X86State::RFLAG_PF_LOC);
+  }
+
+  // AF
+  {
+    // Undefined
+    // Set to zero anyway
+    SetRFLAG<FEXCore::X86State::RFLAG_AF_LOC>(_Constant(0));
+  }
+
+  // ZF
+  {
+    auto SelectOp = _Select(FEXCore::IR::COND_EQ,
+        Res, _Constant(0), _Constant(1), _Constant(0));
+    SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+  }
+
+  // SF
+  {
+    auto SignBitConst = _Constant(GetSrcSize(Op) * 8 - 1);
+
+    auto LshrOp = _Lshr(Res, SignBitConst);
+    SetRFLAG<FEXCore::X86State::RFLAG_SF_LOC>(LshrOp);
+  }
+
+  // OF
+  {
+    // Only defined when Shift is 1 else undefined
+    // Is set to the MSB of the original value
+    if (Shift == 1) {
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Bfe(1, GetSrcSize(Op) * 8 - 1, Src1));
+    }
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_RotateRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  auto OpSize = GetSrcSize(Op) * 8;
+
+  // Extract the last bit shifted in to CF
+  auto NewCF = _Bfe(1, OpSize - 1, Res);
+
+  // CF
+  {
+    auto OldCF = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC);
+    auto CF = _Select(FEXCore::IR::COND_EQ, Src2, _Constant(0), OldCF, NewCF);
+
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(CF);
+  }
+
+  // OF
+  {
+    auto OldOF = GetRFLAG(FEXCore::X86State::RFLAG_OF_LOC);
+
+    // OF is set to the XOR of the new CF bit and the most significant bit of the result
+    auto NewOF = _Xor(_Bfe(1, OpSize - 2, Res), NewCF);
+
+    // If shift == 0, don't update flags
+    auto OF = _Select(FEXCore::IR::COND_EQ, Src2, _Constant(0), OldOF, NewOF);
+
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(OF);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_RotateLeft(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
+  auto OpSize = GetSrcSize(Op) * 8;
+
+  // Extract the last bit shifted in to CF
+  //auto Size = _Constant(GetSrcSize(Res) * 8);
+  //auto ShiftAmt = _Sub(Size, Src2);
+  auto NewCF = _Bfe(1, 0, Res);
+
+  // CF
+  {
+    auto OldCF = GetRFLAG(FEXCore::X86State::RFLAG_CF_LOC);
+    auto CF = _Select(FEXCore::IR::COND_EQ, Src2, _Constant(0), OldCF, NewCF);
+
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(CF);
+  }
+
+  // OF
+  {
+    auto OldOF = GetRFLAG(FEXCore::X86State::RFLAG_OF_LOC);
+    // OF is set to the XOR of the new CF bit and the most significant bit of the result
+    auto NewOF = _Xor(_Bfe(1, OpSize - 1, Res), NewCF);
+
+    auto OF = _Select(FEXCore::IR::COND_EQ, Src2, _Constant(0), OldOF, NewOF);
+
+    // If shift == 0, don't update flags
+    SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(OF);
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_RotateRightImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+  if (Shift == 0) return;
+
+  auto OpSize = GetSrcSize(Op) * 8;
+
+  auto NewCF = _Bfe(1, OpSize - Shift, Src1);
+
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(NewCF);
+  }
+
+  // OF
+  {
+    if (Shift == 1) {
+      // OF is set to the XOR of the new CF bit and the most significant bit of the result
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Xor(_Bfe(1, OpSize - 1, Res), NewCF));
+    }
+  }
+}
+
+void OpDispatchBuilder::GenerateFlags_RotateLeftImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+  if (Shift == 0) return;
+
+  auto OpSize = GetSrcSize(Op) * 8;
+
+  // CF
+  {
+    // Extract the last bit shifted in to CF
+    SetRFLAG<FEXCore::X86State::RFLAG_CF_LOC>(_Bfe(1, Shift, Src1));
+  }
+
+  // OF
+  {
+    if (Shift == 1) {
+      // OF is the top two MSBs XOR'd together
+      SetRFLAG<FEXCore::X86State::RFLAG_OF_LOC>(_Xor(_Bfe(1, OpSize - 1, Src1), _Bfe(1, OpSize - 2, Src1)));
+    }
+  }
+}
+
+}

External/FEXCore/Source/Interface/Core/VSyscall/VSyscall.inc

@@ -0,0 +1,285 @@
+// This is the vsyscall page for x86_64 guest code
+// This was compiled with nasm with the following source then exported to binary
+
+//BITS 64;
+//
+//align 4096, db 0xcc
+//  ; __NR_gettimeofday
+//  mov rax, 96
+//  syscall
+//  ret
+//
+//align 1024, db 0xcc
+//  ; __NR_time
+//  mov rax, 201
+//  syscall
+//  ret
+//
+//align 1024, db 0xcc
+//  ; __NR_getcpu
+//  mov rax, 309
+//  syscall
+//  ret
+//
+//align 4096, db 0xcc
+
+// We only want one of these pages per FEX process
+// One page
+const static uint8_t VSyscallData[0x1000] = {
+	0xB8, 0x60, 0x00, 0x00, 0x00, 0x0F, 0x05, 0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xB8, 0xC9, 0x00, 0x00, 0x00, 0x0F, 0x05, 0xC3, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
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+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+	0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC
+};

External/FEXCore/Source/Interface/Core/X86DebugInfo.cpp

@@ -114,8 +114,6 @@ void InstallDebugInfo() {
   GenerateDebugTable(PrimaryInstGroupOps, PrimaryGroupOpTable);
 
   GenerateDebugTable(SecondInstGroupOps, SecondaryExtensionOpTable);
-
-  LogMan::Msg::D("Installing debug info");
 }
 }
 #endif

External/FEXCore/Source/Interface/Core/X86HelperGen.cpp

@@ -50,14 +50,14 @@ void* X86GeneratedCode::AllocateGuestCodeSpace(size_t Size) {
   // We need to have the sigret handler in the lower 32bits of memory space
   // Scan top down and try to allocate a location
   for (size_t Location = 0xFFFF'E000; Location != 0x0; Location -= 0x1000) {
-    void *Ptr = FEXCore::Allocator::mmap(reinterpret_cast<void*>(Location), Size, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+    void *Ptr = ::mmap(reinterpret_cast<void*>(Location), Size, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 
     if (Ptr != MAP_FAILED &&
         reinterpret_cast<uintptr_t>(Ptr) >= LOCATION_MAX) {
       // Failed to map in the lower 32bits
       // Try again
       // Can happen in the case that host kernel ignores MAP_FIXED_NOREPLACE
-      FEXCore::Allocator::munmap(Ptr, Size);
+      ::munmap(Ptr, Size);
       continue;
     }
 

External/FEXCore/Source/Interface/Core/X86Tables.cpp

@@ -108,7 +108,6 @@ void InitializeInfoTables(Context::OperatingMode Mode) {
 
 #ifndef NDEBUG
   X86InstDebugInfo::InstallDebugInfo();
-  LogMan::Msg::D("X86Tables had %ld total insts, and %ld labeled as understood", Total, NumInsts);
 #endif
 }
 

External/FEXCore/Source/Interface/Core/X86Tables/H0F38Tables.cpp

@@ -4,6 +4,8 @@ tags: frontend|x86-tables
 $end_info$
 */
 
+#include <FEXCore/Core/Context.h>
+
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 namespace FEXCore::X86Tables {

External/FEXCore/Source/Interface/Core/X86Tables/SecondaryTables.cpp

@@ -27,7 +27,7 @@ void InitializeSecondaryTables(Context::OperatingMode Mode) {
     {0x0B, 1, X86InstInfo{"UD2",        TYPE_INST, FLAGS_DEBUG | FLAGS_BLOCK_END | FLAGS_NO_OVERLAY,                                                    0, nullptr}},
     {0x0C, 1, X86InstInfo{"",           TYPE_INVALID, FLAGS_NO_OVERLAY,                                                                                 0, nullptr}},
     {0x0D, 1, X86InstInfo{"",           TYPE_GROUP_P, FLAGS_MODRM | FLAGS_NO_OVERLAY,                                                                                 0, nullptr}},
-    {0x0E, 1, X86InstInfo{"FEMMS",      TYPE_INST, FLAGS_BLOCK_END | FLAGS_NO_OVERLAY,                                                            0, nullptr}},
+    {0x0E, 1, X86InstInfo{"FEMMS",      TYPE_INST, FLAGS_NO_OVERLAY,                                                            0, nullptr}},
     {0x0F, 1, X86InstInfo{"",           TYPE_3DNOW_TABLE, FLAGS_NO_OVERLAY,                                                                             0, nullptr}},
 
     {0x10, 1, X86InstInfo{"MOVUPS",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS,                                                 0, nullptr}},

External/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h

@@ -6,6 +6,7 @@ $end_info$
 
 #pragma once
 #include <FEXCore/Debug/X86Tables.h>
+#include <FEXCore/Core/Context.h>
 
 #include <FEXCore/Utils/LogManager.h>
 
@@ -113,5 +114,7 @@ static inline void GenerateX87Table(X86InstInfo *FinalTable, U16U8InfoStruct con
   }
 };
 
+void InitializeInfoTables(Context::OperatingMode Mode);
+
 }
 

External/FEXCore/Source/Interface/IR/IR.json

@@ -1462,6 +1462,24 @@
       ]
     },
 
+    "AtomicFetchNeg": {
+      "HasSideEffects": true,
+      "Desc": ["Atomic integer fetch and two's complement negate",
+               "Dest is the value prior to operating on the value in memory"
+              ],
+      "OpClass": "Atomic",
+      "HasDest": true,
+      "DestClass": "GPR",
+      "DestSize": "Size",
+      "SSAArgs": "1",
+      "SSANames": [
+        "Addr"
+      ],
+      "Args": [
+        "uint8_t", "Size"
+      ]
+    },
+
     "VExtractToGPR": {
       "Desc": ["Extracts an element from a vector and places it in a GPR",
                "The element that is extracted from the vector is zero extended to the GPR size"

External/FEXCore/Source/Interface/IR/IREmitter.cpp

@@ -82,7 +82,7 @@ IREmitter::IRPair<IROp_CodeBlock> IREmitter::CreateNewCodeBlockAfter(OrderedNode
   if (insertAfter) {
     LinkCodeBlocks(insertAfter, CodeNode);
   } else {
-    LOGMAN_THROW_A(CurrentCodeBlock != nullptr, "CurrentCodeBlock must not be null here");
+    LOGMAN_THROW_A_FMT(CurrentCodeBlock != nullptr, "CurrentCodeBlock must not be null here");
 
     // Find last block
     auto LastBlock = CurrentCodeBlock;
@@ -101,7 +101,7 @@ IREmitter::IRPair<IROp_CodeBlock> IREmitter::CreateNewCodeBlockAfter(OrderedNode
 
 void IREmitter::SetCurrentCodeBlock(OrderedNode *Node) {
   CurrentCodeBlock = Node;
-  LOGMAN_THROW_A(Node->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Node wasn't codeblock. It was '%s'", std::string(IR::GetName(Node->Op(DualListData.DataBegin())->Op)).c_str());
+  LOGMAN_THROW_A_FMT(Node->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK, "Node wasn't codeblock. It was '{}'", IR::GetName(Node->Op(DualListData.DataBegin())->Op));
   SetWriteCursor(Node->Op(DualListData.DataBegin())->CW<IROp_CodeBlock>()->Begin.GetNode(DualListData.ListBegin()));
 }
 

External/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp

@@ -448,8 +448,10 @@ bool ConstProp::ZextAndMaskingElimination(IREmitter *IREmit, const IRListView& C
         IREmit->ReplaceAllUsesWith(CodeNode, CurrentIR.GetNode(source));
       } else if (IROp->Size == sourceHeader->Size) {
         // VMOV of same size
+        // XXX: This is unsafe of an optimization since in some cases we can't see through garbage data in the upper bits of a vector
+        // RCLSE generates VMOV instructions which are being used as a zero extension
         //printf("printf vmov of same size?!\n");
-        IREmit->ReplaceAllUsesWith(CodeNode, CurrentIR.GetNode(source));
+        //IREmit->ReplaceAllUsesWith(CodeNode, CurrentIR.GetNode(source));
       }
       break;
     }
@@ -489,7 +491,7 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
 
       if (IREmit->IsValueConstant(IROp->Args[0], &Constant1) &&
           IREmit->IsValueConstant(IROp->Args[1], &Constant2)) {
-        LOGMAN_MSG_A("Could const prop op: %s", std::string(IR::GetName(IROp->Op)).c_str());
+        LOGMAN_MSG_A_FMT("Could const prop op: {}", IR::GetName(IROp->Op));
       }
     break;
     }
@@ -505,7 +507,7 @@ bool ConstProp::ConstantPropagation(IREmitter *IREmit, const IRListView& Current
       uint64_t Constant1;
 
       if (IREmit->IsValueConstant(IROp->Args[0], &Constant1)) {
-        LOGMAN_MSG_A("Could const prop op: %s", std::string(IR::GetName(IROp->Op)).c_str());
+        LOGMAN_MSG_A_FMT("Could const prop op: {}", IR::GetName(IROp->Op));
       }
     break;
     }

External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp

@@ -17,14 +17,36 @@ namespace {
   };
 
   enum LastAccessType {
-    ACCESS_NONE,          ///< Was never previously accessed
-    ACCESS_WRITE,         ///< Was fully overwritten
-    ACCESS_READ,          ///< Was fully read
-    ACCESS_PARTIAL_WRITE, ///< Was partially written
-    ACCESS_PARTIAL_READ,  ///< Was partially read
-    ACCESS_INVALID,       ///< Accessing this is invalid
+    ACCESS_NONE      = (0b000 << 0), ///< Was never previously accessed
+    ACCESS_WRITE     = (0b001 << 0), ///< Was fully overwritten
+    ACCESS_READ      = (0b010 << 0), ///< Was fully read
+    ACCESS_INVALID   = (0b011 << 0), ///< Accessing this is invalid
+    ACCESS_TYPE_MASK = (0b011 << 0),
+    ACCESS_PARTIAL   = (0b100 << 0),
+    ACCESS_PARTIAL_WRITE = (ACCESS_PARTIAL | ACCESS_WRITE), ///< Was partially written
+    ACCESS_PARTIAL_READ  = (ACCESS_PARTIAL | ACCESS_READ),  ///< Was partially read
   };
 
+  static bool IsWriteAccess(LastAccessType Type) {
+    return (Type & ACCESS_TYPE_MASK) == ACCESS_WRITE;
+  }
+
+  static bool IsReadAccess(LastAccessType Type) {
+    return (Type & ACCESS_TYPE_MASK) == ACCESS_READ;
+  }
+
+  static bool IsInvalidAccess(LastAccessType Type) {
+    return (Type & ACCESS_TYPE_MASK) == ACCESS_INVALID;
+  }
+
+  static bool IsPartialAccess(LastAccessType Type) {
+    return (Type & ACCESS_PARTIAL) == ACCESS_PARTIAL;
+  }
+
+  static bool IsFullAccess(LastAccessType Type) {
+    return (Type & ACCESS_PARTIAL) == 0;
+  }
+
   struct ContextMemberInfo {
     ContextMemberClassification Class;
     LastAccessType Accessed;
@@ -40,7 +62,7 @@ namespace {
     std::vector<ContextMemberInfo> ClassificationInfo;
   };
 
-  constexpr static std::array<LastAccessType, 15> DefaultAccess = {
+  constexpr static std::array<LastAccessType, 16> DefaultAccess = {
     ACCESS_NONE,
     ACCESS_NONE,
     ACCESS_INVALID, // PAD
@@ -56,6 +78,7 @@ namespace {
     ACCESS_NONE,
     ACCESS_NONE,
     ACCESS_NONE,
+    ACCESS_NONE,
   };
 
   static void ClassifyContextStruct(ContextInfo *ContextClassificationInfo) {
@@ -145,7 +168,7 @@ namespace {
       DefaultAccess[4],
       FEXCore::IR::InvalidClass,
     });
-    
+
     ContextClassification->emplace_back(ContextMemberInfo{
       ContextMemberClassification {
         offsetof(FEXCore::Core::CPUState, fs),
@@ -208,6 +231,17 @@ namespace {
       FEXCore::IR::InvalidClass,
     });
 
+    // FTW
+    ContextClassification->emplace_back(ContextMemberInfo {
+      ContextMemberClassification {
+        offsetof(FEXCore::Core::CPUState, FTW),
+        sizeof(FEXCore::Core::CPUState::FTW),
+      },
+      DefaultAccess[15],
+      FEXCore::IR::InvalidClass,
+    });
+
+
     size_t ClassifiedStructSize{};
     ContextClassificationInfo->Lookup.reserve(sizeof(FEXCore::Core::CPUState));
     for (auto &it : *ContextClassification) {
@@ -270,6 +304,7 @@ namespace {
     }
 
     SetAccess(Offset++, DefaultAccess[14]);
+    SetAccess(Offset++, DefaultAccess[15]);
   }
 
   struct BlockInfo {
@@ -431,6 +466,8 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
   ContextInfo &LocalInfo = ClassifiedStruct;
 
   for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
+    auto BlockOp = BlockHeader->CW<FEXCore::IR::IROp_CodeBlock>();
+    auto BlockEnd = IREmit->GetIterator(BlockOp->Last);
 
     ResetClassificationAccesses(&LocalInfo);
 
@@ -443,9 +480,9 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
         uint8_t LastSize = Info->AccessSize;
         LastAccessType LastAccess = Info->Accessed;
         OrderedNode *LastStoreNode = Info->StoreNode;
-        RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_WRITE, CurrentIR.GetNode(Op->Header.Args[0]), CodeNode);
+        RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_WRITE, CurrentIR.GetNode(Op->Value), CodeNode);
 
-        if ((LastAccess == ACCESS_WRITE || LastAccess == ACCESS_PARTIAL_WRITE) &&
+        if (IsWriteAccess(LastAccess) &&
             LastClass == Op->Class &&
             LastOffset == Op->Offset &&
             LastSize <= IROp->Size) {
@@ -470,7 +507,7 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
         OrderedNode *LastStoreNode = Info->StoreNode;
         RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_READ, CodeNode);
 
-        if ((LastAccess == ACCESS_WRITE || LastAccess == ACCESS_PARTIAL_WRITE) &&
+        if (IsWriteAccess(LastAccess) &&
             LastClass == Op->Class &&
             LastOffset == Op->Offset &&
             IROp->Size <= LastSize) {
@@ -491,46 +528,52 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
 
             if (TruncateSize != IREmit->GetOpSize(LastNode)) {
               // We need to insert an explict truncation
-              if (LastClass == FPRClass) {
-                LastNode = IREmit->_VMov(LastNode, TruncateSize); // Vmov truncates and zexts when register width is smaller than source
-              }
-              else if (LastClass == GPRPairClass) {
-                LastNode = IREmit->_TruncElementPair(LastNode, TruncateSize);
-              }
-              else if (LastClass == GPRClass) {
-                LastNode = IREmit->_Bfe(Info->AccessSize, TruncateSize * 8, 0, LastNode);
-              } else {
-                LOGMAN_MSG_A("Unhandled Register class");
-              }
+              LastNode = IREmit->_Bfe(Info->AccessSize, TruncateSize * 8, 0, LastNode);
             }
 
-            IREmit->ReplaceAllUsesWith(CodeNode, LastNode);
+            IREmit->ReplaceAllUsesWithRange(CodeNode, LastNode, IREmit->GetIterator(IREmit->WrapNode(CodeNode)), BlockEnd);
             RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_READ, LastNode);
             Changed = true;
-          } else {
-            if (LastClass == FPRClass && LastSize == IROp->Size && LastSize == IREmit->GetOpSize(LastNode)) {
-              // LoadCtx matches StoreCtx and Node Size
-              IREmit->ReplaceAllUsesWith(CodeNode, LastNode);
-              RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_READ, LastNode);
-              Changed = true;
-            } else if (LastClass == FPRClass && LastSize >= IROp->Size && IROp->Size == IREmit->GetOpSize(LastNode)) {
+          } else if (LastClass == FPRClass) {
+            if (LastSize == IROp->Size && LastSize == IREmit->GetOpSize(LastNode)) {
+              if (IsFullAccess(Info->Accessed)) {
+                // LoadCtx matches StoreCtx and Node Size
+                IREmit->ReplaceAllUsesWithRange(CodeNode, LastNode, IREmit->GetIterator(IREmit->WrapNode(CodeNode)), BlockEnd);
+                RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_READ, LastNode);
+                Changed = true;
+              }
+              else {
+                // If this load size is a partial load then it may be expecting a zext of
+                // the vector element
+                IREmit->SetWriteCursor(CodeNode);
+                // zext to size
+                LastNode = IREmit->_VMov(LastNode, IROp->Size);
+
+                IREmit->ReplaceAllUsesWithRange(CodeNode, LastNode, IREmit->GetIterator(IREmit->WrapNode(CodeNode)), BlockEnd);
+                RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_READ, LastNode);
+                Changed = true;
+              }
+            } else if (LastSize >= IROp->Size &&
+                       IROp->Size == IREmit->GetOpSize(LastNode)) {
               // LoadCtx is <= StoreCtx and Node is LoadCtx
-              IREmit->ReplaceAllUsesWith(CodeNode, LastNode);
+              IREmit->ReplaceAllUsesWithRange(CodeNode, LastNode, IREmit->GetIterator(IREmit->WrapNode(CodeNode)), BlockEnd);
               RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_READ, LastNode);
               Changed = true;
-            } else if (LastClass == FPRClass && LastSize >= IROp->Size && IROp->Size < IREmit->GetOpSize(LastNode)) {
+            } else if (LastSize >= IROp->Size &&
+                       IROp->Size < IREmit->GetOpSize(LastNode)) {
               IREmit->SetWriteCursor(CodeNode);
               // trucate to size
               LastNode = IREmit->_VMov(LastNode, IROp->Size);
-              IREmit->ReplaceAllUsesWith(CodeNode, LastNode);
+              IREmit->ReplaceAllUsesWithRange(CodeNode, LastNode, IREmit->GetIterator(IREmit->WrapNode(CodeNode)), BlockEnd);
               RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_READ, LastNode);
               Changed = true;
-            } else if (LastClass == FPRClass && LastSize >= IROp->Size && IROp->Size > IREmit->GetOpSize(LastNode)) {
+            } else if (LastSize >= IROp->Size &&
+                       IROp->Size > IREmit->GetOpSize(LastNode)) {
               IREmit->SetWriteCursor(CodeNode);
               // zext to size
               LastNode = IREmit->_VMov(LastNode, IROp->Size);
 
-              IREmit->ReplaceAllUsesWith(CodeNode, LastNode);
+              IREmit->ReplaceAllUsesWithRange(CodeNode, LastNode, IREmit->GetIterator(IREmit->WrapNode(CodeNode)), BlockEnd);
               RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_READ, LastNode);
               Changed = true;
             } else {
@@ -538,13 +581,13 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
             }
           }
         }
-        else if ((LastAccess == ACCESS_READ || LastAccess == ACCESS_PARTIAL_READ) &&
+        else if (IsReadAccess(LastAccess) &&
+                 IsReadAccess(Info->Accessed) &&
                  LastClass == Op->Class &&
                  LastOffset == Op->Offset &&
-                 LastSize == IROp->Size &&
-                 (Info->Accessed == ACCESS_READ || Info->Accessed == ACCESS_PARTIAL_READ)) {
+                 LastSize == IROp->Size) {
           // Did we read and then read again?
-          IREmit->ReplaceAllUsesWith(CodeNode, LastNode);
+          IREmit->ReplaceAllUsesWithRange(CodeNode, LastNode, IREmit->GetIterator(IREmit->WrapNode(CodeNode)), BlockEnd);
           RecordAccess(Info, Op->Class, Op->Offset, IROp->Size, ACCESS_READ, LastNode);
           Changed = true;
         }
@@ -591,21 +634,21 @@ bool RCLSE::RedundantStoreLoadElimination(FEXCore::IR::IREmitter *IREmit) {
         LastAccessType LastAccess = Info->Accessed;
         OrderedNode *LastNode = Info->Node;
 
-        if (LastAccess == ACCESS_WRITE) { // 1 byte so always a full write
+        if (IsWriteAccess(LastAccess)) { // 1 byte so always a full write
           // If the last store matches this load value then we can replace the loaded value with the previous valid one
           IREmit->SetWriteCursor(CodeNode);
           IREmit->ReplaceAllUsesWith(CodeNode, LastNode);
           RecordAccess(Info, FEXCore::IR::GPRClass, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag, 1, ACCESS_READ, LastNode);
           Changed = true;
         }
-        else if (LastAccess == ACCESS_READ) {
+        else if (IsReadAccess(LastAccess)) {
           IREmit->ReplaceAllUsesWith(CodeNode, LastNode);
           RecordAccess(Info, FEXCore::IR::GPRClass, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag, 1, ACCESS_READ, LastNode);
           Changed = true;
         }
       }
       else if (IROp->Op == OP_STORECONTEXTINDEXED ||
-               IROp->Op == OP_LOADCONTEXTINDEXED || 
+               IROp->Op == OP_LOADCONTEXTINDEXED ||
                IROp->Op == OP_SYSCALL) {
         // We can't track through these
         ResetClassificationAccesses(&LocalInfo);
@@ -622,7 +665,7 @@ bool RCLSE::Run(FEXCore::IR::IREmitter *IREmit) {
   // XXX: We don't do cross-block optimizations yet
   //CalculateControlFlowInfo(IREmit);
   bool Changed = false;
-  
+
   // Run up to 5 times
   for( int i = 0; i < 5 && RedundantStoreLoadElimination(IREmit); i++) {
     Changed = true;

External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp

@@ -56,7 +56,7 @@ bool IRValidation::Run(IREmitter *IREmit) {
 
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
   auto HeaderOp = CurrentIR.GetHeader();
-  LOGMAN_THROW_A(HeaderOp->Header.Op == OP_IRHEADER, "First op wasn't IRHeader");
+  LOGMAN_THROW_A_FMT(HeaderOp->Header.Op == OP_IRHEADER, "First op wasn't IRHeader");
 #endif
 
   IR::RegisterAllocationData * RAData{};
@@ -68,7 +68,7 @@ bool IRValidation::Run(IREmitter *IREmit) {
 
   for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
     auto BlockIROp = BlockHeader->CW<FEXCore::IR::IROp_CodeBlock>();
-    LOGMAN_THROW_A(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block");
+    LOGMAN_THROW_A_FMT(BlockIROp->Header.Op == OP_CODEBLOCK, "IR type failed to be a code block");
 
     uint32_t BlockID = CurrentIR.GetID(BlockNode);
 
@@ -211,7 +211,7 @@ bool IRValidation::Run(IREmitter *IREmit) {
           break;
         }
         default:
-          // LOGMAN_MSG_A("Unknown IR Op: %d(%s)", IROp->Op, FEXCore::IR::GetName(IROp->Op).data());
+          // LOGMAN_MSG_A_FMT("Unknown IR Op: {}({})", IROp->Op, FEXCore::IR::GetName(IROp->Op));
         break;
       }
     }
@@ -267,10 +267,9 @@ bool IRValidation::Run(IREmitter *IREmit) {
     }
   }
 
-  std::stringstream Out;
-
   HadWarning = false;
   if (HadError || HadWarning) {
+    std::stringstream Out;
     FEXCore::IR::Dump(&Out, &CurrentIR, RAData);
 
     if (HadError) {

External/FEXCore/Source/Interface/IR/Passes/PhiValidation.cpp

@@ -52,17 +52,13 @@ bool PhiValidation::Run(IREmitter *IREmit) {
     }
   }
 
-  std::stringstream Out;
-
   if (HadError) {
+    std::stringstream Out;
     FEXCore::IR::Dump(&Out, &CurrentIR, nullptr);
-
     Out << "Errors:" << std::endl << Errors.str() << std::endl;
-
     LogMan::Msg::EFmt("{}", Out.str());
   }
 
-
   return false;
 }
 

External/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp

@@ -12,6 +12,7 @@ $end_info$
 
 #include <iterator>
 #include <unordered_set>
+#include <sys/mman.h>
 
 #define SRA_DEBUG(...) // printf(__VA_ARGS__)
 
@@ -177,6 +178,7 @@ namespace {
   };
 
   static_assert(sizeof(RegisterNode) == 128 * 4);
+  constexpr size_t REGISTER_NODES_PER_PAGE = FEXCore::Core::PAGE_SIZE / sizeof(RegisterNode);
 
   struct RegisterSet {
     std::vector<RegisterClass> Classes;
@@ -204,8 +206,8 @@ namespace {
   struct RegisterGraph {
     std::unique_ptr<FEXCore::IR::RegisterAllocationData, FEXCore::IR::RegisterAllocationDataDeleter> AllocData;
     RegisterSet Set;
-    std::vector<RegisterNode> Nodes;
-    uint32_t NodeCount;
+    std::vector<RegisterNode> Nodes{};
+    uint32_t NodeCount{};
     std::vector<SpillStackUnit> SpillStack;
     std::unordered_map<uint32_t, std::unordered_set<uint32_t>> BlockPredecessors;
     std::unordered_map<uint32_t, std::unordered_set<uint32_t>> VisitedNodePredecessors;
@@ -258,11 +260,14 @@ namespace {
   }
 
   void ResetRegisterGraph(RegisterGraph *Graph, uint64_t NodeCount) {
-    NodeCount = AlignUp(NodeCount, sizeof(uint64_t));
+    NodeCount = AlignUp(NodeCount, REGISTER_NODES_PER_PAGE);
+
+    // Clear to free the Bucketlists which have unique_ptrs
+    // Resize to our correct size
     Graph->Nodes.clear();
     Graph->Nodes.resize(NodeCount);
+
     Graph->VisitedNodePredecessors.clear();
-    Graph->AllocData.reset();
     Graph->AllocData.reset((FEXCore::IR::RegisterAllocationData*)FEXCore::Allocator::malloc(FEXCore::IR::RegisterAllocationData::Size(NodeCount)));
     memset(&Graph->AllocData->Map[0], INVALID_REGCLASS.Raw, NodeCount);
     Graph->AllocData->MapCount = NodeCount;

External/FEXCore/Source/Interface/IR/Passes/ValueDominanceValidation.cpp

@@ -28,12 +28,9 @@ public:
 
 bool ValueDominanceValidation::Run(IREmitter *IREmit) {
   bool HadError = false;
-  bool HadWarning = false;
   auto CurrentIR = IREmit->ViewIR();
 
   std::ostringstream Errors;
-  std::ostringstream Warnings;
-
   std::unordered_map<IR::OrderedNodeWrapper::NodeOffsetType, BlockInfo> OffsetToBlockMap;
 
   for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
@@ -193,19 +190,10 @@ bool ValueDominanceValidation::Run(IREmitter *IREmit) {
     }
   }
 
-  std::stringstream Out;
-
-  if (HadError || HadWarning) {
+  if (HadError) {
+    std::stringstream Out;
     FEXCore::IR::Dump(&Out, &CurrentIR, nullptr);
-
-    if (HadError) {
-      Out << "Errors:" << std::endl << Errors.str() << std::endl;
-    }
-
-    if (HadWarning) {
-      Out << "Warnings:" << std::endl << Warnings.str() << std::endl;
-    }
-
+    Out << "Errors:" << std::endl << Errors.str() << std::endl;
     LogMan::Msg::EFmt("{}", Out.str());
   }
 

External/FEXCore/Source/Utils/Allocator.cpp

@@ -1,39 +1,36 @@
 #include "Utils/Allocator/HostAllocator.h"
 #include <FEXCore/Utils/Allocator.h>
 #include <sys/mman.h>
+#ifdef ENABLE_JEMALLOC
 #include <jemalloc/jemalloc.h>
+#endif
 #include <memory>
 #include <malloc.h>
 
 extern "C" {
-  extern void *__libc_malloc(size_t size);
-  extern void *__libc_realloc(void *ptr, size_t size);
-  extern void __libc_free(void *ptr);
-
   typedef void* (*mmap_hook_type)(
             void *addr, size_t length, int prot, int flags,
             int fd, off_t offset);
   typedef int (*munmap_hook_type)(void *addr, size_t length);
 
+#ifdef ENABLE_JEMALLOC
   extern mmap_hook_type __mmap_hook;
   extern munmap_hook_type __munmap_hook;
-
-  static FEXCore::Allocator::MALLOC_Hook global_malloc {::__libc_malloc};
-  static FEXCore::Allocator::REALLOC_Hook global_realloc {::__libc_realloc};
-  static FEXCore::Allocator::FREE_Hook global_free {::__libc_free};
-
-  // Override the global functions
-  FEX_DEFAULT_VISIBILITY void *malloc(size_t size) { return global_malloc(size); }
-  FEX_DEFAULT_VISIBILITY void *realloc(void *ptr, size_t size) { return global_realloc(ptr, size); }
-  FEX_DEFAULT_VISIBILITY void free(void *ptr) { return global_free(ptr); }
+#endif
 }
 
 namespace FEXCore::Allocator {
   MMAP_Hook mmap {::mmap};
   MUNMAP_Hook munmap {::munmap};
-  MALLOC_Hook malloc {::__libc_malloc};
-  REALLOC_Hook realloc {::__libc_realloc};
-  FREE_Hook free {::__libc_free};
+#ifdef ENABLE_JEMALLOC
+  MALLOC_Hook malloc {::je_malloc};
+  REALLOC_Hook realloc {::je_realloc};
+  FREE_Hook free {::je_free};
+#else
+  MALLOC_Hook malloc {::malloc};
+  REALLOC_Hook realloc {::realloc};
+  FREE_Hook free {::free};
+#endif
 
   using GLIBC_MALLOC_Hook = void*(*)(size_t, const void *caller);
   using GLIBC_REALLOC_Hook = void*(*)(void*, size_t, const void *caller);
@@ -59,60 +56,26 @@ namespace FEXCore::Allocator {
     return Result;
   }
 
-  void *FEX_malloc_hook(size_t size, const void *caller) {
-    return ::je_malloc(size);
-  }
-
-  void *FEX_realloc_hook(void *ptr, size_t size, const void *caller) {
-    return ::je_realloc(ptr, size);
-  }
-
-  void FEX_free_hook(void *ptr, const void *caller) {
-    return ::je_free(ptr);
-  }
-
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wdeprecated-declarations"
   void SetupHooks() {
     Alloc64 = Alloc::OSAllocator::Create64BitAllocator();
+#ifdef ENABLE_JEMALLOC
     __mmap_hook   = FEX_mmap;
     __munmap_hook = FEX_munmap;
+#endif
     FEXCore::Allocator::mmap = FEX_mmap;
     FEXCore::Allocator::munmap = FEX_munmap;
-    FEXCore::Allocator::malloc = ::je_malloc;
-    FEXCore::Allocator::realloc = ::je_realloc;
-    FEXCore::Allocator::free = ::je_free;
-
-    global_malloc = ::je_malloc;
-    global_realloc = ::je_realloc;
-    global_free = ::je_free;
-
-    __malloc_hook = FEXCore::Allocator::FEX_malloc_hook;
-    __realloc_hook = FEXCore::Allocator::FEX_realloc_hook;
-    __free_hook = FEXCore::Allocator::FEX_free_hook;
   }
 
   void ClearHooks() {
+#ifdef ENABLE_JEMALLOC
     __mmap_hook   = ::mmap;
     __munmap_hook = ::munmap;
+#endif
     FEXCore::Allocator::mmap = ::mmap;
     FEXCore::Allocator::munmap = ::munmap;
-    FEXCore::Allocator::malloc = ::__libc_malloc;
-    FEXCore::Allocator::realloc = ::__libc_realloc;
-    FEXCore::Allocator::free = ::__libc_free;
-
-    global_malloc = ::__libc_malloc;
-    global_realloc = ::__libc_realloc;
-    global_free = ::__libc_free;
-
-    // Reset's glibc hooks
-    __malloc_hook = 0;
-    __realloc_hook = 0;
-    __free_hook = 0;
   }
 #pragma GCC diagnostic pop
 
 }
-
-extern "C" {
-}

External/FEXCore/Source/Utils/Allocator/64BitAllocator.cpp

@@ -122,7 +122,9 @@ namespace Alloc::OSAllocator {
         size_t SizeOfLiveRegion = AlignUp(LiveVMARegion::GetSizeWithFlexSet(ReservedRegion->RegionSize), PAGE_SIZE);
         size_t SizePlusManagedData = UsedSize + SizeOfLiveRegion;
 
-        mprotect(reinterpret_cast<void*>(ReservedRegion->Base), SizePlusManagedData, PROT_READ | PROT_WRITE);
+        [[maybe_unused]] auto Res = mprotect(reinterpret_cast<void*>(ReservedRegion->Base), SizePlusManagedData, PROT_READ | PROT_WRITE);
+
+        LOGMAN_THROW_A(Res == 0, "Couldn't mprotect region: %d '%s' Likely occurs when running out of memory or Maximum VMAs", errno, strerror(errno));
 
         LiveVMARegion *LiveRange = new (reinterpret_cast<void*>(ReservedRegion->Base)) LiveVMARegion();
 
@@ -147,7 +149,7 @@ namespace Alloc::OSAllocator {
   };
 
 void OSAllocator_64Bit::DetermineVASize() {
-  const std::vector<uintptr_t> TLBSizes = {{
+  static constexpr std::array<uintptr_t, 7> TLBSizes = {
     1ULL << 57,
     1ULL << 52,
     1ULL << 48,
@@ -155,7 +157,7 @@ void OSAllocator_64Bit::DetermineVASize() {
     1ULL << 42,
     1ULL << 39,
     1ULL << 36,
-  }};
+  };
 
   for (auto Size : TLBSizes) {
     // Just try allocating
@@ -264,15 +266,17 @@ void *OSAllocator_64Bit::Mmap(void *addr, size_t length, int prot, int flags, in
         (StartingPosition - Region->SlabInfo->Base) >> PAGE_SHIFT
         : Region->LastPageAllocation;
       size_t RegionNumberOfPages = Region->SlabInfo->RegionSize >> PAGE_SHIFT;
-      try_again:
-      for (size_t CurrentPage = LastAllocation;
-           CurrentPage < (RegionNumberOfPages - NumberOfPages);) {
-        // If we have enough free space, check if we have enough free pages that are contiguous
-        size_t Remaining = NumberOfPages;
 
-        assert((CurrentPage + Remaining - 1) < RegionNumberOfPages);
+      // Backward scan
+      // We need to do a backward scan first to fill any holes
+      // Otherwise we will very quickly run out of VMA regions (65k maximum)
+      for (size_t CurrentPage = LastAllocation;
+           CurrentPage >= NumberOfPages;) {
+        size_t Remaining = NumberOfPages;
+        assert(Remaining <= CurrentPage);
+
         while (Remaining) {
-          if (Region->UsedPages[CurrentPage + Remaining - 1]) {
+          if (Region->UsedPages[CurrentPage - Remaining]) {
             // Has an intersecting range
             break;
           }
@@ -281,20 +285,51 @@ void *OSAllocator_64Bit::Mmap(void *addr, size_t length, int prot, int flags, in
 
         if (Remaining) {
           // Didn't find a slab range
-          CurrentPage += Remaining;
+          CurrentPage -= Remaining;
         }
         else {
           // We have a slab range
+          CurrentPage -= NumberOfPages;
+
+          // Keep scanning backwards to not introduce ANOTHER gap
+          while (CurrentPage >= 1) {
+            if (Region->UsedPages[CurrentPage - 1]) {
+              // Found a used page, we can leave now
+              break;
+            }
+            --CurrentPage;
+          }
           AllocatedPage = CurrentPage;
           break;
         }
       }
 
-      if (!AllocatedPage && LastAllocation != 0) {
-        // Try again but starting from the beginning
-        LastAllocation = 0;
-        // Using goto so we don't have recursive mutex shenanigans
-        goto try_again;
+      // Foward Scan
+      if (AllocatedPage == 0) {
+        for (size_t CurrentPage = LastAllocation;
+             CurrentPage < (RegionNumberOfPages - NumberOfPages);) {
+          // If we have enough free space, check if we have enough free pages that are contiguous
+          size_t Remaining = NumberOfPages;
+
+          assert((CurrentPage + Remaining - 1) < RegionNumberOfPages);
+          while (Remaining) {
+            if (Region->UsedPages[CurrentPage + Remaining - 1]) {
+              // Has an intersecting range
+              break;
+            }
+            --Remaining;
+          }
+
+          if (Remaining) {
+            // Didn't find a slab range
+            CurrentPage += Remaining;
+          }
+          else {
+            // We have a slab range
+            AllocatedPage = CurrentPage;
+            break;
+          }
+        }
       }
 
       if (AllocatedPage) {
@@ -457,7 +492,7 @@ int OSAllocator_64Bit::Munmap(void *addr, size_t length) {
       // Live region fully encompasses slab range
 
       uint64_t FreedPages{};
-      uint64_t SlabPageBegin = (PtrBegin - RegionBegin) >> PAGE_SHIFT;
+      uint32_t SlabPageBegin = (PtrBegin - RegionBegin) >> PAGE_SHIFT;
       uint64_t PagesToFree = length >> PAGE_SHIFT;
 
       for (size_t i = 0; i < PagesToFree; ++i) {
@@ -476,6 +511,10 @@ int OSAllocator_64Bit::Munmap(void *addr, size_t length) {
 
       (*it)->FreeSpace += FreedPages * 4096;
 
+      // Set the last allocated page to the minimum of last page allocation or this slab
+      // This will let us more quickly fill holes
+      (*it)->LastPageAllocation = std::min((*it)->LastPageAllocation, SlabPageBegin);
+
       // XXX: Move region back to reserved list
       return 0;
     }
@@ -542,7 +581,7 @@ OSAllocator_64Bit::PtrCache *OSAllocator_64Bit::Steal32BitIfOldKernel() {
     // If we managed to allocate and not get the address we want then unmap it
     // This happens with kernels older than 4.17
     if (reinterpret_cast<uintptr_t>(Ptr) + AllocationSize > UPPER_BOUND_32) {
-      munmap(Ptr, AllocationSize);
+      ::munmap(Ptr, AllocationSize);
       Ptr = reinterpret_cast<void*>(~0ULL);
     }
 
@@ -594,7 +633,7 @@ void OSAllocator_64Bit::Clear32BitOnOldKernel(OSAllocator_64Bit::PtrCache *Base)
   for (size_t i = 0;; ++i) {
     void *Ptr = reinterpret_cast<void*>(Base[i].Ptr);
     size_t Size = Base[i].Size;
-    munmap(Ptr, Size);
+    ::munmap(Ptr, Size);
     if (Ptr == Base) {
       break;
     }
@@ -602,7 +641,6 @@ void OSAllocator_64Bit::Clear32BitOnOldKernel(OSAllocator_64Bit::PtrCache *Base)
 }
 
 OSAllocator_64Bit::OSAllocator_64Bit() {
-  malloc_trim(0);
   DetermineVASize();
   auto ArrayPtr = Steal32BitIfOldKernel();
 
@@ -641,7 +679,7 @@ OSAllocator_64Bit::OSAllocator_64Bit() {
     // This happens with kernels older than 4.17
     if (reinterpret_cast<uintptr_t>(Ptr) != MemoryOffset &&
         reinterpret_cast<uintptr_t>(Ptr) < LOWER_BOUND) {
-      munmap(Ptr, AllocationSize);
+      ::munmap(Ptr, AllocationSize);
       Ptr = reinterpret_cast<void*>(~0ULL);
     }
 
@@ -659,8 +697,7 @@ OSAllocator_64Bit::OSAllocator_64Bit() {
       if (!ObjectAlloc) {
         // Steal the first allocation for an intrusive allocator
         // Will be mprotected correctly already
-        int Result = mprotect(Ptr, AllocationSize, PROT_READ | PROT_WRITE);
-        LogMan::Throw::A(Result == 0, "mprotect(%p, 0x%lx) -> %d (%s)", Ptr, AllocationSize, Result, strerror(errno));
+        mprotect(Ptr, AllocationSize, PROT_READ | PROT_WRITE);
         ObjectAlloc = new (Ptr) Alloc::ForwardOnlyIntrusiveArenaAllocator(Ptr, AllocationSize);
         ReservedRegions = ObjectAlloc->new_construct(ReservedRegions, ObjectAlloc);
         LiveRegions = ObjectAlloc->new_construct(LiveRegions, ObjectAlloc);

External/FEXCore/Source/Utils/Allocator/FlexBitSet.h

@@ -14,18 +14,18 @@ struct FlexBitSet final {
 
   T Memory[];
 
-  bool Get(T Element) {
+  bool Get(size_t Element) const {
     return (Memory[Element / MinimumSizeBits] & (1ULL << (Element % MinimumSizeBits))) != 0;
   }
-  bool TestAndClear(T Element) {
+  bool TestAndClear(size_t Element) {
     bool Value = Get(Element);
     Memory[Element / MinimumSizeBits] &= ~(1ULL << (Element % MinimumSizeBits));
     return Value;
   }
-  void Set(T Element) {
+  void Set(size_t Element) {
     Memory[Element / MinimumSizeBits] |= (1ULL << (Element % MinimumSizeBits));
   }
-  void Clear(T Element) {
+  void Clear(size_t Element) {
     Memory[Element / MinimumSizeBits] &= ~(1ULL << (Element % MinimumSizeBits));
   }
   void MemClear(size_t Elements) {
@@ -37,14 +37,14 @@ struct FlexBitSet final {
 
   // This very explicitly doesn't let you take an address
   // Is only a getter
-  bool operator[](T Element) {
+  bool operator[](size_t Element) const {
     return Get(Element);
   }
 
-  static size_t Size(T Elements) {
+  static size_t Size(uint64_t Elements) {
     return Alloc::AlignUp(Elements / MinimumSizeBits, MinimumSizeBits);
   }
 };
 
 static_assert(sizeof(FlexBitSet<uint64_t>) == 0, "This needs to be a flex member");
-static_assert(std::is_trivially_copyable<FlexBitSet<uint64_t>>::value, "Needsto be trivially copyable");
+static_assert(std::is_trivially_copyable_v<FlexBitSet<uint64_t>>, "Needs to be trivially copyable");

External/FEXCore/include/FEXCore/Core/CoreState.h

@@ -26,6 +26,7 @@ namespace FEXCore::Core {
       uint32_t base;
     } gdt[32];
     uint16_t FCW;
+    uint16_t FTW;
   };
   static_assert(offsetof(CPUState, xmm) % 16 == 0, "xmm needs to be 128bit aligned!");
 

External/FEXCore/include/FEXCore/Core/UContext.h

@@ -95,6 +95,34 @@ namespace FEXCore {
   }
 
   namespace x86 {
+    // uc_flags flags
+    ///< Has extended FP state
+    constexpr uint64_t UC_FP_XSTATE         = (1ULL << 0);
+
+    ///< The order of these must match the GNU ordering
+    enum ContextRegs {
+      FEX_REG_GS = 0,
+      FEX_REG_FS,
+      FEX_REG_ES,
+      FEX_REG_DS,
+      FEX_REG_RDI,
+      FEX_REG_RSI,
+      FEX_REG_RBP,
+      FEX_REG_RSP,
+      FEX_REG_RBX,
+      FEX_REG_RDX,
+      FEX_REG_RCX,
+      FEX_REG_RAX,
+      FEX_REG_TRAPNO,
+      FEX_REG_ERR,
+      FEX_REG_EIP,
+      FEX_REG_CS,
+      FEX_REG_EFL,
+      FEX_REG_UESP,
+      FEX_REG_SS
+    };
+    static_assert(FEX_REG_SS == 18, "Oops");
+
     struct FEX_PACKED siginfo_t {
       int si_signo;
       int si_errno;
@@ -117,8 +145,55 @@ namespace FEXCore {
     };
     static_assert(sizeof(FEXCore::x86::siginfo_t) == 128, "This needs to be the right size");
 
+    struct FEX_PACKED stack_t {
+      uint32_t ss_sp; // XXX: should be compat_ptr<void>
+      int ss_flags;
+      uint32_t ss_size;
+    };
+
+    static_assert(sizeof(FEXCore::x86::stack_t) == 12, "This needs to be the right size");
+
+    struct FEX_PACKED mcontext_t {
+      uint32_t gregs[19];
+      uint32_t fpregs; // XXX: should be compat_ptr<FEXCore::x86::_libc_fpstate>
+      uint32_t oldmask;
+      uint32_t cr2;
+    };
+    static_assert(sizeof(FEXCore::x86::mcontext_t) == 88, "This needs to be the right size");
+
+    struct _libc_fpreg {
+      uint16_t significand[4];
+      uint16_t exponent;
+    };
+    static_assert(sizeof(FEXCore::x86::_libc_fpreg) == 10, "This needs to be the right size");
+
+    enum fpstate_magic {
+      // Legacy fpstate
+      MAGIC_FPU = 0xFFFF'0000,
+      // Contains extended state information
+      MAGIC_XFPSTATE = 0x0,
+    };
+    struct FEX_PACKED _libc_fpstate {
+      uint32_t fcw;
+      uint32_t fsw;
+      uint32_t ftw;
+      uint32_t fop;
+      uint32_t cssel;
+      uint32_t dataoff;
+      uint32_t datasel;
+      FEXCore::x86::_libc_fpreg _st[8];
+      uint32_t status;
+    };
+    static_assert(sizeof(FEXCore::x86::_libc_fpstate) == 112, "This needs to be the right size");
+
     struct FEX_PACKED ucontext_t {
-      uint32_t pad[91];
+      uint32_t uc_flags;
+      uint32_t uc_link; // XXX: should be a compat_ptr<FEXCore::x86::ucontext_t>
+      FEXCore::x86::stack_t uc_stack;
+      FEXCore::x86::mcontext_t uc_mcontext;
+      FEXCore::x86_64::sigset_t uc_sigmask; // This matches across architectures
+      FEXCore::x86::_libc_fpstate __fpregs_mem;
+      uint32_t __ssp[4];
     };
     static_assert(sizeof(FEXCore::x86::ucontext_t) == 364, "This needs to be the right size");
 

External/FEXCore/include/FEXCore/Debug/X86Tables.h

@@ -1,6 +1,5 @@
 #pragma once
 
-#include <FEXCore/Core/Context.h>
 #include <FEXCore/Utils/CompilerDefs.h>
 
 #include <cstdint>
@@ -500,6 +499,4 @@ extern FEX_DEFAULT_VISIBILITY X86InstInfo XOPTableGroupOps[MAX_XOP_GROUP_TABLE_S
 
 // EVEX
 extern FEX_DEFAULT_VISIBILITY X86InstInfo EVEXTableOps[MAX_EVEX_TABLE_SIZE];
-
-FEX_DEFAULT_VISIBILITY void InitializeInfoTables(Context::OperatingMode Mode);
 }

External/FEXCore/include/FEXCore/HLE/SyscallHandler.h

@@ -27,6 +27,7 @@ namespace FEXCore::HLE {
   };
 
   enum class SyscallOSABI {
+    OS_UNKNOWN,
     OS_LINUX64,
     OS_LINUX32,
     OS_WIN64,

External/FEXCore/include/FEXCore/IR/IREmitter.h

@@ -398,50 +398,50 @@ friend class FEXCore::IR::PassManager;
   }
 
   void SetJumpTarget(IR::IROp_Jump *Op, OrderedNode *Target) {
-    LOGMAN_THROW_A(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
-        "Tried setting Jump target to %%ssa%d %s",
+    LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
+        "Tried setting Jump target to %ssa{} {}",
         Target->Wrapped(DualListData.ListBegin()).ID(),
-        std::string(IR::GetName(Target->Op(DualListData.DataBegin())->Op)).c_str());
+        IR::GetName(Target->Op(DualListData.DataBegin())->Op));
 
     Op->Header.Args[0].NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
   }
   void SetTrueJumpTarget(IR::IROp_CondJump *Op, OrderedNode *Target) {
-    LOGMAN_THROW_A(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
-        "Tried setting CondJump target to %%ssa%d %s",
+    LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
+        "Tried setting CondJump target to %ssa{} {}",
         Target->Wrapped(DualListData.ListBegin()).ID(),
-        std::string(IR::GetName(Target->Op(DualListData.DataBegin())->Op)).c_str());
+        IR::GetName(Target->Op(DualListData.DataBegin())->Op));
 
     Op->TrueBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
   }
   void SetFalseJumpTarget(IR::IROp_CondJump *Op, OrderedNode *Target) {
-    LOGMAN_THROW_A(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
-        "Tried setting CondJump target to %%ssa%d %s",
+    LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
+        "Tried setting CondJump target to %ssa{} {}",
         Target->Wrapped(DualListData.ListBegin()).ID(),
-        std::string(IR::GetName(Target->Op(DualListData.DataBegin())->Op)).c_str());
+        IR::GetName(Target->Op(DualListData.DataBegin())->Op));
 
     Op->FalseBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
   }
 
   void SetJumpTarget(IRPair<IROp_Jump> Op, OrderedNode *Target) {
-    LOGMAN_THROW_A(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
-        "Tried setting Jump target to %%ssa%d %s",
+    LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
+        "Tried setting Jump target to %ssa{} {}",
         Target->Wrapped(DualListData.ListBegin()).ID(),
-        std::string(IR::GetName(Target->Op(DualListData.DataBegin())->Op)).c_str());
+        IR::GetName(Target->Op(DualListData.DataBegin())->Op));
 
     Op.first->Header.Args[0].NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
   }
   void SetTrueJumpTarget(IRPair<IROp_CondJump> Op, OrderedNode *Target) {
-    LOGMAN_THROW_A(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
-        "Tried setting CondJump target to %%ssa%d %s",
+    LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
+        "Tried setting CondJump target to %ssa{} {}",
         Target->Wrapped(DualListData.ListBegin()).ID(),
-        std::string(IR::GetName(Target->Op(DualListData.DataBegin())->Op)).c_str());
+        IR::GetName(Target->Op(DualListData.DataBegin())->Op));
     Op.first->TrueBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
   }
   void SetFalseJumpTarget(IRPair<IROp_CondJump> Op, OrderedNode *Target) {
-    LOGMAN_THROW_A(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
-        "Tried setting CondJump target to %%ssa%d %s",
+    LOGMAN_THROW_A_FMT(Target->Op(DualListData.DataBegin())->Op == OP_CODEBLOCK,
+        "Tried setting CondJump target to %ssa{} {}",
         Target->Wrapped(DualListData.ListBegin()).ID(),
-        std::string(IR::GetName(Target->Op(DualListData.DataBegin())->Op)).c_str());
+        IR::GetName(Target->Op(DualListData.DataBegin())->Op));
     Op.first->FalseBlock.NodeOffset = Target->Wrapped(DualListData.ListBegin()).NodeOffset;
   }
 
@@ -507,7 +507,7 @@ friend class FEXCore::IR::PassManager;
 
     ReplaceUsesWithAfter(Node, NewNode, Start);
 
-    LOGMAN_THROW_A(Node->NumUses == 0, "Node still used");
+    LOGMAN_THROW_A_FMT(Node->NumUses == 0, "Node still used");
 
     // Since we have deleted ALL uses, we can safely delete the node.
     Remove(Node);
@@ -521,8 +521,8 @@ friend class FEXCore::IR::PassManager;
   OrderedNode *GetPackedRFLAG(bool Lower8);
 
   void CopyData(IREmitter const &rhs) {
-    LOGMAN_THROW_A(rhs.DualListData.DataBackingSize() <= DualListData.DataBackingSize(), "Trying to take ownership of data that is too large");
-    LOGMAN_THROW_A(rhs.DualListData.ListBackingSize() <= DualListData.ListBackingSize(), "Trying to take ownership of data that is too large");
+    LOGMAN_THROW_A_FMT(rhs.DualListData.DataBackingSize() <= DualListData.DataBackingSize(), "Trying to take ownership of data that is too large");
+    LOGMAN_THROW_A_FMT(rhs.DualListData.ListBackingSize() <= DualListData.ListBackingSize(), "Trying to take ownership of data that is too large");
     DualListData.CopyData(rhs.DualListData);
     InvalidNode = rhs.InvalidNode->Wrapped(rhs.DualListData.ListBegin()).GetNode(DualListData.ListBegin());
     CurrentWriteCursor = rhs.CurrentWriteCursor;
@@ -588,7 +588,7 @@ friend class FEXCore::IR::PassManager;
 #endif
     CodeNode->Op(DualListData.DataBegin())->CW<FEXCore::IR::IROp_CodeBlock>();
 
-    LOGMAN_THROW_A(CurrentIROp->Header.Op == IROps::OP_CODEBLOCK, "Invalid");
+    LOGMAN_THROW_A_FMT(CurrentIROp->Header.Op == IROps::OP_CODEBLOCK, "Invalid");
 
     CodeNode->append(DualListData.ListBegin(), Next);
   }

External/FEXCore/include/FEXCore/IR/IntrusiveIRList.h

@@ -197,7 +197,7 @@ public:
 
     // If we are casting to something narrower than just the header, check the opcode.
     if constexpr (!std::is_same<T, IROp_Header>::value) {
-      LOGMAN_THROW_A(Op->OPCODE == Op->Header.Op, "Expected Node to be '%s'. Found '%s' instead", GetName(Op->OPCODE), GetName(Op->Header.Op));
+      LOGMAN_THROW_A_FMT(Op->OPCODE == Op->Header.Op, "Expected Node to be '{}'. Found '{}' instead", GetName(Op->OPCODE), GetName(Op->Header.Op));
     }
 
     return Op;

Source/Common/RootFSSetup.cpp

@@ -5,6 +5,7 @@
 #include <FEXCore/Config/Config.h>
 
 #include <filesystem>
+#include <fstream>
 
 #include <poll.h>
 #include <unistd.h>
@@ -12,8 +13,61 @@
 #include <sys/prctl.h>
 #include <sys/stat.h>
 #include <sys/wait.h>
+#include <sys/utsname.h>
 
 namespace FEX::RootFS {
+
+static std::fstream SquashFSLock{};
+bool SanityCheckPath(std::string const &LDPath) {
+// Check if we have an directory inside our temp folder
+  std::string PathUser = LDPath + "/usr";
+  std::error_code ec{};
+  if (!std::filesystem::exists(PathUser, ec)) {
+    LogMan::Msg::D("Child couldn't mount rootfs, /usr doesn't exist");
+    rmdir(LDPath.c_str());
+    return false;
+  }
+
+  return true;
+}
+
+bool CheckLockExists(std::string const LockPath) {
+  // If the lock file for a squashfs path exists the we can try
+  // to open it and ref counting will keep it alive
+  std::error_code ec{};
+  if (std::filesystem::exists(LockPath, ec)) {
+    SquashFSLock.open(LockPath, std::ios_base::in | std::ios_base::binary);
+    if (SquashFSLock.is_open()) {
+      // We managed to open the file. Which means the mount application has now refcounted our interaction with it
+      // Extract the data in it to know where it was mounted
+      std::string NewPath;
+      SquashFSLock >> NewPath;
+      if (NewPath.empty()) {
+        // Couldn't open for whatever reason
+        SquashFSLock.close();
+        return false;
+      }
+      if (!SanityCheckPath(NewPath)) {
+        // Mount doesn't exist anymore
+        SquashFSLock.close();
+        // Removing the dangling mount directory
+        rmdir(NewPath.c_str());
+
+        // Remove the dangling lock file
+        unlink(LockPath.c_str());
+        return false;
+      }
+      FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, NewPath);
+      return true;
+    }
+  }
+  return false;
+}
+
+void OpenLock(std::string const LockPath) {
+  SquashFSLock.open(LockPath, std::ios_base::in | std::ios_base::binary);
+}
+
 bool Setup(char **const envp) {
   // We need to setup the rootfs here
   // If the configuration is set to use a folder then there is nothing to do
@@ -21,6 +75,20 @@ bool Setup(char **const envp) {
 
   FEX_CONFIG_OPT(LDPath, ROOTFS);
   if (FEX::FormatCheck::IsSquashFS(LDPath())) {
+    // Check if the rootfs is already mounted
+    // We can do this by checking the lock file if it exists
+
+    struct utsname uts{};
+    uname (&uts);
+    std::string LockPath = "/tmp/.FEX-";
+    LockPath += std::filesystem::path(LDPath()).filename();
+    LockPath += ".lock.";
+    LockPath += uts.nodename;
+
+    if (CheckLockExists(LockPath)) {
+      // RootFS already exists. Nothing to do
+      return true;
+    }
     pid_t ParentTID = ::getpid();
     std::string ParentTIDString = std::to_string(ParentTID);
     std::string Tmp = "/tmp/.FEXMount" + ParentTIDString + "-XXXXXX";
@@ -103,17 +171,16 @@ bool Setup(char **const envp) {
         return false;
       }
 
+      // Open the lock to let the daemon know that it has an active user
+      OpenLock(LockPath);
+
       // Check if we have an directory inside our temp folder
-      std::string Path = TempFolder;
-      std::string PathUser = Path + "/usr";
-      if (!std::filesystem::exists(PathUser)) {
-        LogMan::Msg::D("Child couldn't mount rootfs, /usr doesn't exist");
-        rmdir(TempFolder);
+      if (!SanityCheckPath(TempFolder)) {
         return false;
       }
 
       // If everything has passed then we can now update the rootfs path
-      FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, Path);
+      FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, TempFolder);
       return true;
     }
   }
@@ -121,4 +188,10 @@ bool Setup(char **const envp) {
   // Nothing to do
   return true;
 }
+
+void Shutdown() {
+  // Close the FD so our rootfs process can refcount
+  // Even if we crash the rootfs process will see a close event
+  SquashFSLock.close();
+}
 }

Source/Common/RootFSSetup.h

@@ -2,4 +2,5 @@
 
 namespace FEX::RootFS {
   bool Setup(char **const envp);
+  void Shutdown();
 }

Source/Linux/Utils/ELFContainer.cpp

@@ -95,11 +95,12 @@ ELFContainer::ELFContainer(std::string const &Filename, std::string const &RootF
       RawString = &RawFile.at(InterpreterHeader._64->p_offset);
     }
     std::string RootFSLink = RootFS + RawString;
-    while (std::filesystem::is_symlink(RootFSLink)) {
+    std::error_code ec{};
+    while (std::filesystem::is_symlink(RootFSLink, ec)) {
       // Do some special handling if the RootFS's linker is a symlink
       // Ubuntu's rootFS by default provides an absolute location symlink to the linker
       // Resolve this around back to the rootfs
-      auto SymlinkTarget = std::filesystem::read_symlink(RootFSLink);
+      auto SymlinkTarget = std::filesystem::read_symlink(RootFSLink, ec);
       if (SymlinkTarget.is_absolute()) {
         RootFSLink = RootFS + SymlinkTarget.string();
       }

Source/Linux/Utils/ELFParser.h

@@ -22,50 +22,46 @@ struct ELFParser {
   std::string InterpreterElf;
   int fd {-1};
 
-  bool ReadElf(const std::string &file) {
+  bool ReadElf(int NewFD) {
     Closefd();
     static_assert(EI_CLASS == 4);
 
+    fd = NewFD;
     type = ::ELFLoader::ELFContainer::TYPE_NONE;
 
-    std::ifstream elf(file);
-
-    fd = ::open(file.c_str(), O_RDONLY);
-
     if (fd == -1) {
       // Likely just doesn't exist
       return false;
     }
 
-    if (!elf.good()) {
-      LogMan::Msg::E("Failed to open (C++) '%s'", file.c_str());
+    // Get file size
+    off_t Size = lseek(fd, 0, SEEK_END);
+
+    if (Size < 4) {
+      // Likely invalid can't fit header
       return false;
     }
 
-    uint8_t header[5];
-    elf.read((char*)header, sizeof(header));
+    // Reset to beginning
+    lseek(fd, 0, SEEK_SET);
 
-    if (!elf.good()) {
-      LogMan::Msg::E("Failed to read elf header from '%s'", file.c_str());
+    uint8_t header[5];
+    if (pread(fd, header, sizeof(header), 0) == -1) {
+      LogMan::Msg::E("Failed to read elf header from '%d'", fd);
       return false;
     }
 
     if (header[0] != ELFMAG0 || header[1] != ELFMAG1 || header[2] != ELFMAG2 || header[3] != ELFMAG3) {
-      LogMan::Msg::E("Elf header from '%s' doesn't match ELF MAGIC", file.c_str());
+      LogMan::Msg::E("Elf header from '%d' doesn't match ELF MAGIC", fd);
       return false;
     }
 
     type = ::ELFLoader::ELFContainer::TYPE_OTHER_ELF;
 
-    // go to the beggining of the file
-    elf.seekg(0);
-
     if (header[EI_CLASS] == ELFCLASS32) {
       Elf32_Ehdr hdr32;
-      elf.read((char*)&hdr32, sizeof(hdr32));
-
-      if (!elf.good()) {
-        LogMan::Msg::E("Failed to read Ehdr32 from '%s'", file.c_str());
+      if (pread(fd, &hdr32, sizeof(hdr32), 0) == -1) {
+        LogMan::Msg::E("Failed to read Ehdr32 from '%d'", fd);
         return false;
       }
 
@@ -73,13 +69,13 @@ struct ELFParser {
 
       // check elf header
       if (hdr32.e_ehsize != sizeof(hdr32)) {
-        LogMan::Msg::E("Invalid e_ehsize32 from '%s'", file.c_str());
+        LogMan::Msg::E("Invalid e_ehsize32 from '%d'", fd);
         return false;
       }
 
       // check program header
       if (hdr32.e_phentsize != sizeof(Elf32_Phdr)) {
-        LogMan::Msg::E("Invalid e_phentsize32 from '%s'", file.c_str());
+        LogMan::Msg::E("Invalid e_phentsize32 from '%d'", fd);
         return false;
       }
 
@@ -104,63 +100,54 @@ struct ELFParser {
       #undef COPY
 
       if (ehdr.e_machine != EM_386) {
-        LogMan::Msg::E("Invalid e_machine from '%s'", file.c_str());
+        LogMan::Msg::E("Invalid e_machine from '%d'", fd);
         return false;
       }
 
       type = ::ELFLoader::ELFContainer::TYPE_X86_32;
-
     } else if (header[EI_CLASS] == ELFCLASS64) {
-      elf.read((char*)&ehdr, sizeof(ehdr));
-
-      if (!elf.good()) {
-        LogMan::Msg::E("Failed to read Ehdr64 from '%s'", file.c_str());
+      if (pread(fd, &ehdr, sizeof(ehdr), 0) == -1) {
+        LogMan::Msg::E("Failed to read Ehdr64 from '%d'", fd);
         return false;
       }
 
-
       // do the sizes match up as expected?
 
       // check elf header
       if (ehdr.e_ehsize != sizeof(ehdr)) {
-        LogMan::Msg::E("Invalid e_ehsize64 from '%s'", file.c_str());
+        LogMan::Msg::E("Invalid e_ehsize64 from '%d'", fd);
         return false;
       }
 
       // check program header
       if (ehdr.e_phentsize != sizeof(Elf64_Phdr)) {
-        LogMan::Msg::E("Invalid e_phentsize64 from '%s'", file.c_str());
+        LogMan::Msg::E("Invalid e_phentsize64 from '%d'", fd);
         return false;
       }
 
       if (ehdr.e_machine != EM_X86_64) {
-        LogMan::Msg::E("Invalid e_machine64 from '%s'", file.c_str());
+        LogMan::Msg::E("Invalid e_machine64 from '%d'", fd);
         return false;
       }
 
       type = ::ELFLoader::ELFContainer::TYPE_X86_64;
-
     } else {
       // Unexpected elf type
-      LogMan::Msg::E("Unexpected elf type from '%s'", file.c_str());
+      LogMan::Msg::E("Unexpected elf type from '%d'", fd);
       return false;
     }
 
-    // seek to the program header offset
-    elf.seekg(ehdr.e_phoff);
-
     // sanity check program header count
     if (ehdr.e_phnum < 1 || ehdr.e_phnum > 65536 / ehdr.e_phentsize) {
-      LogMan::Msg::E("Too many program headers '%s'", file.c_str());
+      LogMan::Msg::E("Too many program headers '%d'", fd);
       return false;
     }
 
     if (type == ::ELFLoader::ELFContainer::TYPE_X86_32) {
       Elf32_Phdr phdrs32[ehdr.e_phnum];
-      elf.read((char*)phdrs32, sizeof(Elf32_Phdr) * ehdr.e_phnum);
 
-      if (!elf.good()) {
-        LogMan::Msg::E("Failed to read phdr32 from '%s'", file.c_str());
+      if (pread(fd, phdrs32, sizeof(Elf32_Phdr) * ehdr.e_phnum, ehdr.e_phoff) == -1) {
+        LogMan::Msg::E("Failed to read phdr32 from '%d'", fd);
         return false;
       }
 
@@ -184,23 +171,18 @@ struct ELFParser {
     } else {
       phdrs.resize(ehdr.e_phnum);
 
-      elf.read((char*)&phdrs[0], sizeof(Elf64_Phdr) * ehdr.e_phnum);
-
-      if (!elf.good()) {
-        LogMan::Msg::E("Failed to read phdr64 from '%s'", file.c_str());
+      if (pread(fd, &phdrs[0], sizeof(Elf64_Phdr) * ehdr.e_phnum, ehdr.e_phoff) == -1) {
+        LogMan::Msg::E("Failed to read phdr64 from '%d'", fd);
         return false;
       }
     }
 
     for (auto phdr : phdrs) {
       if (phdr.p_type == PT_INTERP) {
-        elf.seekg(phdr.p_offset);
         InterpreterElf.resize(phdr.p_filesz);
 
-        elf.read(&InterpreterElf[0], phdr.p_filesz);
-
-        if (!elf.good()) {
-          LogMan::Msg::E("Failed to read interpreter from '%s'", file.c_str());
+        if (pread(fd, &InterpreterElf[0], phdr.p_filesz, phdr.p_offset) == -1) {
+          LogMan::Msg::E("Failed to read interpreter from '%d'", fd);
           return false;
         }
       }
@@ -209,6 +191,12 @@ struct ELFParser {
     return true;
   }
 
+  bool ReadElf(const std::string &file) {
+    int NewFD = ::open(file.c_str(), O_RDONLY);
+
+    return ReadElf(NewFD);
+  }
+
   void Closefd() {
     if (fd != -1) {
       close(fd);

Source/Tests/CMakeLists.txt

@@ -1,12 +1,16 @@
 add_subdirectory(LinuxSyscalls)
 
-set(LIBS FEXCore Common CommonCore FEX_jemalloc)
+if (ENABLE_JEMALLOC)
+  set (LIBS FEX_jemalloc)
+endif()
+
+list(APPEND LIBS FEXCore Common CommonCore)
 
 add_executable(FEXLoader FEXLoader.cpp)
 target_include_directories(FEXLoader PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/Source/)
 target_include_directories(FEXLoader PRIVATE ${CMAKE_BINARY_DIR}/generated)
 
-target_link_libraries(FEXLoader ${LIBS} LinuxEmulation)
+target_link_libraries(FEXLoader ${LIBS} LinuxEmulation ${STATIC_PIE_OPTIONS} ${PTHREAD_LIB})
 
 if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
   target_link_options(FEXLoader
@@ -40,7 +44,7 @@ install(PROGRAMS "${PROJECT_SOURCE_DIR}/Scripts/FEXUpdateAOTIRCache.sh" DESTINAT
 if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
   add_custom_target(binfmt_misc_32
     echo "Attempting to install FEX-x86 misc now."
-    COMMAND "update-binfmts" "--import" "FEX-x86"
+    COMMAND "update-binfmts" "--importdir=${CMAKE_INSTALL_PREFIX}/share/binfmts/" "--import" "FEX-x86"
     COMMAND ${CMAKE_COMMAND} -E
     echo "binfmt_misc FEX-x86 installed"
   )
@@ -48,7 +52,7 @@ if (CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64")
   add_custom_target(binfmt_misc_64
     COMMAND ${CMAKE_COMMAND} -E
     echo "Attempting to install FEX-x86_64 misc now."
-    COMMAND "update-binfmts" "--import" "FEX-x86_64"
+    COMMAND "update-binfmts" "--importdir=${CMAKE_INSTALL_PREFIX}/share/binfmts/" "--import" "FEX-x86_64"
     COMMAND ${CMAKE_COMMAND} -E
     echo "binfmt_misc FEX-x86_64 installed"
   )
@@ -63,7 +67,7 @@ add_executable(FEXBash FEXBash.cpp)
 target_include_directories(FEXBash PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/Source/)
 target_include_directories(FEXBash PRIVATE ${CMAKE_BINARY_DIR}/generated)
 
-target_link_libraries(FEXBash ${LIBS} LinuxEmulation)
+target_link_libraries(FEXBash ${LIBS} LinuxEmulation ${STATIC_PIE_OPTIONS} ${PTHREAD_LIB})
 
 if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
   target_link_options(FEXBash
@@ -83,12 +87,12 @@ add_executable(TestHarnessRunner TestHarnessRunner.cpp)
 target_include_directories(TestHarnessRunner PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/Source/)
 target_include_directories(TestHarnessRunner PRIVATE ${CMAKE_BINARY_DIR}/generated)
 
-target_link_libraries(TestHarnessRunner ${LIBS} LinuxEmulation)
+target_link_libraries(TestHarnessRunner ${LIBS} LinuxEmulation ${STATIC_PIE_OPTIONS} ${PTHREAD_LIB})
 
 add_executable(UnitTestGenerator UnitTestGenerator.cpp)
 target_include_directories(UnitTestGenerator PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/Source/)
 
-target_link_libraries(UnitTestGenerator ${LIBS})
+target_link_libraries(UnitTestGenerator ${LIBS} ${STATIC_PIE_OPTIONS} ${PTHREAD_LIB})
 
 add_executable(IRLoader
   IRLoader.cpp
@@ -97,5 +101,5 @@ add_executable(IRLoader
 target_include_directories(IRLoader PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/Source/)
 target_include_directories(IRLoader PRIVATE ${CMAKE_BINARY_DIR}/generated)
 
-target_link_libraries(IRLoader ${LIBS} LinuxEmulation)
+target_link_libraries(IRLoader ${LIBS} LinuxEmulation ${STATIC_PIE_OPTIONS} ${PTHREAD_LIB})
 

Source/Tests/ELFCodeLoader2.h

@@ -2,6 +2,7 @@
 #pragma once
 #include "Common/Config.h"
 #include "Common/MathUtils.h"
+#include "Tests/LinuxSyscalls/Syscalls.h"
 #include "Linux/Utils/ELFParser.h"
 #include "Linux/Utils/ELFSymbolDatabase.h"
 
@@ -213,8 +214,43 @@ class ELFCodeLoader2 final : public FEXCore::CodeLoader {
   ELFCodeLoader2(std::string const &Filename, std::string const &RootFS, [[maybe_unused]] std::vector<std::string> const &args, std::vector<std::string> const &ParsedArgs, char **const envp = nullptr, FEXCore::Config::Value<std::string> *AdditionalEnvp = nullptr) :
     Args {args} {
 
-    if (!MainElf.ReadElf(ResolveRootfsFile(Filename, RootFS)) && !MainElf.ReadElf(Filename)) {
-      return;
+    bool LoadedWithFD = false;
+    int FD = getauxval(AT_EXECFD);
+
+    // If we are provided an EXECFD then attempt to execute that first
+    // This happens in the case of binfmt_misc usage
+    if (FD != 0) {
+      if (!MainElf.ReadElf(FD)) {
+        return;
+      }
+      LoadedWithFD = true;
+    }
+    else {
+      if (!MainElf.ReadElf(ResolveRootfsFile(Filename, RootFS)) && !MainElf.ReadElf(Filename)) {
+        return;
+      }
+    }
+
+    // If we have loaded with EXECFD then we have binfmt_misc preserve argv[0] also set
+    // This adds an additional argument to our argument list that we need to ignore
+    // argv[0] = FEXInterpreter
+    // argv[1] = <Path to binary>
+    // argv[2] = <original user typed path to binary>
+    // If our kernel if v5.12 or higher then
+    // We can check if this exists by checking auxv[AT_FLAGS] for AT_FLAGS_PRESERVE_ARGV0
+    // Else we need to make an assumption that if we were loaded with FD that we have preserve enabled
+
+    uint64_t AtFlags = getauxval(AT_FLAGS);
+#ifndef AT_FLAGS_PRESERVE_ARGV0
+#define AT_FLAGS_PRESERVE_ARGV0 1
+#endif
+    uint32_t HostKernel = FEX::HLE::SyscallHandler::CalculateHostKernelVersion();
+    if ((HostKernel >= FEX::HLE::SyscallHandler::KernelVersion(5, 12, 0) &&
+         (AtFlags & AT_FLAGS_PRESERVE_ARGV0)) ||
+       LoadedWithFD){
+
+      // Erase the initial argument from the list in this case
+      Args.erase(Args.begin());
     }
 
     if (!MainElf.InterpreterElf.empty()) {

Source/Tests/FEXLoader.cpp

@@ -39,6 +39,7 @@ $end_info$
 namespace {
 static bool SilentLog;
 static int OutputFD {STDERR_FILENO};
+static bool ExecutedWithFD {false};
 
 void MsgHandler(LogMan::DebugLevels Level, char const *Message) {
   const char *CharLevel{nullptr};
@@ -163,8 +164,12 @@ bool RanAsInterpreter(char *Program) {
 
 bool IsInterpreterInstalled() {
   // The interpreter is installed if both the binfmt_misc handlers are available
-  return std::filesystem::exists("/proc/sys/fs/binfmt_misc/FEX-x86") &&
-         std::filesystem::exists("/proc/sys/fs/binfmt_misc/FEX-x86_64");
+  // Or if we were originally executed with FD. Which means the interpreter is installed
+
+  std::error_code ec{};
+  return ExecutedWithFD ||
+         (std::filesystem::exists("/proc/sys/fs/binfmt_misc/FEX-x86", ec) &&
+         std::filesystem::exists("/proc/sys/fs/binfmt_misc/FEX-x86_64", ec));
 }
 
 void AOTGenSection(FEXCore::Context::Context *CTX, ELFCodeLoader2::LoadedSection &Section) {
@@ -317,12 +322,17 @@ void AOTGenSection(FEXCore::Context::Context *CTX, ELFCodeLoader2::LoadedSection
 
 int main(int argc, char **argv, char **const envp) {
   bool IsInterpreter = RanAsInterpreter(argv[0]);
+
+  ExecutedWithFD = getauxval(AT_EXECFD) != 0;
+
   LogMan::Throw::InstallHandler(AssertHandler);
   LogMan::Msg::InstallHandler(MsgHandler);
 
 #if !(defined(ENABLE_ASAN) && ENABLE_ASAN)
   // LLVM ASAN maps things to the lower 32bits
-  if (!CheckMemMapping()) {
+  // Valgrind also places us in the lower 32-bits
+  if (!getenv("VALGRIND_LAUNCHER") &&
+      !CheckMemMapping()) {
     LogMan::Msg::E("[Unsupported] FEX mapped to lower 32bits! Exiting!");
     return -1;
   }
@@ -352,14 +362,25 @@ int main(int argc, char **argv, char **const envp) {
   std::string Program = Args[0];
 
   // These layers load on initialization
-  FEXCore::Config::AddLayer(std::make_unique<FEX::Config::AppLoader>(std::filesystem::path(Program).filename(), true));
-  FEXCore::Config::AddLayer(std::make_unique<FEX::Config::AppLoader>(std::filesystem::path(Program).filename(), false));
+  auto ProgramName = std::filesystem::path(Program).filename();
+  FEXCore::Config::AddLayer(std::make_unique<FEX::Config::AppLoader>(ProgramName, true));
+  FEXCore::Config::AddLayer(std::make_unique<FEX::Config::AppLoader>(ProgramName, false));
 
   // Reload the meta layer
   FEXCore::Config::ReloadMetaLayer();
   FEXCore::Config::Set(FEXCore::Config::CONFIG_IS_INTERPRETER, IsInterpreter ? "1" : "0");
   FEXCore::Config::Set(FEXCore::Config::CONFIG_INTERPRETER_INSTALLED, IsInterpreterInstalled() ? "1" : "0");
 
+  // Early check for process stall
+  // Doesn't use CONFIG_ROOTFS and we don't want it to spin up a squashfs instance
+  FEX_CONFIG_OPT(StallProcess, STALLPROCESS);
+  if (StallProcess) {
+    while (1) {
+      // Stall this process out forever
+      select(0, nullptr, nullptr, nullptr, nullptr);
+    }
+  }
+
   // Ensure RootFS is setup before config options try to pull CONFIG_ROOTFS
   if (!FEX::RootFS::Setup(envp)) {
     LogMan::Msg::E("RootFS failure");
@@ -390,10 +411,11 @@ int main(int argc, char **argv, char **const envp) {
 
   InterpreterHandler(&Program, LDPath(), &Args);
 
-  if (!std::filesystem::exists(Program)) {
+  std::error_code ec{};
+  if (!std::filesystem::exists(Program, ec)) {
     // Early exit if the program passed in doesn't exist
     // Will prevent a crash later
-    LogMan::Msg::E("%s: command not found", Program.c_str());
+    fprintf(stderr, "%s: command not found\n", Program.c_str());
     return -ENOEXEC;
   }
 
@@ -409,7 +431,16 @@ int main(int argc, char **argv, char **const envp) {
 
   if (!Loader.ELFWasLoaded()) {
     // Loader couldn't load this program for some reason
-    LogMan::Msg::E("Invalid or Unsupported elf file.");
+    fprintf(stderr, "Invalid or Unsupported elf file.\n");
+#ifdef _M_ARM_64
+    fprintf(stderr, "This is likely due to a misconfigured x86-64 RootFS\n");
+    fprintf(stderr, "Current RootFS path set to '%s'\n", LDPath().c_str());
+    std::error_code ec;
+    if (LDPath().size() == 0 ||
+        std::filesystem::exists(LDPath(), ec) == false) {
+      fprintf(stderr, "RootFS path doesn't exist. This is required on AArch64 hosts\n");
+    }
+#endif
     return -ENOEXEC;
   }
 
@@ -520,16 +551,16 @@ int main(int argc, char **argv, char **const envp) {
     FEXCore::Context::RunUntilExit(CTX);
   }
 
-  std::filesystem::create_directories(std::filesystem::path(FEXCore::Config::GetDataDirectory()) / "aotir");
-
-  FEXCore::Context::WriteFilesWithCode(CTX, [](const std::string& fileid, const std::string& filename) {
-    auto filepath = std::filesystem::path(FEXCore::Config::GetDataDirectory()) / "aotir" / (fileid + ".path");
-    int fd = open(filepath.c_str(), O_CREAT | O_EXCL | O_WRONLY, 0644);
-    if (fd != -1) {
-      write(fd, filename.c_str(), filename.size());
-      close(fd);
-    }
-  });
+  if (std::filesystem::create_directories(std::filesystem::path(FEXCore::Config::GetDataDirectory()) / "aotir", ec)) {
+    FEXCore::Context::WriteFilesWithCode(CTX, [](const std::string& fileid, const std::string& filename) {
+      auto filepath = std::filesystem::path(FEXCore::Config::GetDataDirectory()) / "aotir" / (fileid + ".path");
+      int fd = open(filepath.c_str(), O_CREAT | O_EXCL | O_WRONLY, 0644);
+      if (fd != -1) {
+        write(fd, filename.c_str(), filename.size());
+        close(fd);
+      }
+    });
+  }
 
   if (AOTIRCapture() || AOTIRGenerate()) {
 
@@ -549,6 +580,8 @@ int main(int argc, char **argv, char **const envp) {
 
   Loader.FreeSections();
 
+  FEX::RootFS::Shutdown();
+
   FEXCore::Config::Shutdown();
 
   LogMan::Throw::UnInstallHandlers();
@@ -557,6 +590,7 @@ int main(int argc, char **argv, char **const envp) {
   FEXCore::Allocator::ClearHooks();
   // Allocator is now original system allocator
 
+
   if (ShutdownReason == FEXCore::Context::ExitReason::EXIT_SHUTDOWN) {
     return ProgramStatus;
   }

Source/Tests/LinuxSyscalls/CMakeLists.txt

@@ -57,7 +57,7 @@ add_library(LinuxEmulation STATIC
     Syscalls/Stubs.cpp
 )
 
-target_link_libraries(LinuxEmulation FEXCore pthread FEX_Utils)
+target_link_libraries(LinuxEmulation FEXCore FEX_Utils)
 target_include_directories(LinuxEmulation PRIVATE ${CMAKE_BINARY_DIR}/generated)
 target_include_directories(LinuxEmulation PRIVATE ${PROJECT_SOURCE_DIR}/External/drm-headers/include/)
 

Source/Tests/LinuxSyscalls/SignalDelegator.cpp

@@ -19,9 +19,19 @@ $end_info$
 #include <bits/types/stack_t.h>
 #include <sys/mman.h>
 #include <sys/syscall.h>
+#include <sys/signalfd.h>
 #include <unistd.h>
 
 namespace FEX::HLE {
+#ifdef _M_X86_64
+  __attribute__((naked))
+  static void sigrestore() {
+    __asm volatile("syscall;"
+        :: "a" (0xF)
+        : "memory");
+  }
+#endif
+
   constexpr static uint32_t SS_AUTODISARM = (1U << 31);
   constexpr static uint32_t X86_MINSIGSTKSZ  = 0x2000U;
 
@@ -189,21 +199,21 @@ namespace FEX::HLE {
     // Unhandled crash
     // Call back in to the previous handler
     if (Handler.OldAction.sa_flags & SA_SIGINFO) {
-      Handler.OldAction.sa_sigaction(Signal, static_cast<siginfo_t*>(Info), UContext);
+      Handler.OldAction.sigaction(Signal, static_cast<siginfo_t*>(Info), UContext);
     }
-    else if (Handler.OldAction.sa_handler == SIG_IGN ||
-      (Handler.OldAction.sa_handler == SIG_DFL &&
+    else if (Handler.OldAction.handler == SIG_IGN ||
+      (Handler.OldAction.handler == SIG_DFL &&
        Handler.DefaultBehaviour == DEFAULT_IGNORE)) {
       // Do nothing
     }
-    else if (Handler.OldAction.sa_handler == SIG_DFL &&
+    else if (Handler.OldAction.handler == SIG_DFL &&
       (Handler.DefaultBehaviour == DEFAULT_COREDUMP ||
        Handler.DefaultBehaviour == DEFAULT_TERM)) {
       // Reassign back to DFL and crash
       signal(Signal, SIG_DFL);
     }
     else {
-      Handler.OldAction.sa_handler(Signal);
+      Handler.OldAction.handler(Signal);
     }
   }
 
@@ -215,97 +225,61 @@ namespace FEX::HLE {
     }
 
     // Default flags for us
-    SignalHandler.HostAction.sa_flags = SA_SIGINFO | SA_RESTART | SA_ONSTACK;
+    SignalHandler.HostAction.sa_flags = SA_SIGINFO | SA_ONSTACK;
 
-    if (HostHandlers[Signal].Required == false &&
-        (SignalHandler.GuestAction.sigaction_handler.handler == SIG_DFL ||
-         SignalHandler.GuestAction.sigaction_handler.handler == SIG_IGN)) {
-      // If getting set to DFL or IGN on first install then just install to those
-      SignalHandler.HostAction.sa_handler = SignalHandler.GuestAction.sigaction_handler.handler;
-    }
-    else {
-      // Now install the thunk handler
-      SignalHandler.HostAction.sa_sigaction = &SignalHandlerThunk;
-    }
+    bool Result = UpdateHostThunk(Signal);
+
+    SignalHandler.Installed = Result;
+    return Result;
+  }
+
+  bool SignalDelegator::UpdateHostThunk(int Signal) {
+    SignalHandler &SignalHandler = HostHandlers[Signal];
+
+    // Now install the thunk handler
+    SignalHandler.HostAction.sigaction = SignalHandlerThunk;
 
     if (SignalHandler.GuestAction.sa_flags & SA_NODEFER) {
       // If the guest is using NODEFER then make sure to set it for the host as well
       SignalHandler.HostAction.sa_flags |= SA_NODEFER;
     }
 
+    if ((SignalHandler.HostAction.sa_flags ^ SignalHandler.GuestAction.sa_flags) & SA_RESTART) {
+      // If the guest is using SA_RESTART then make sure to set it for the host as well
+      SignalHandler.HostAction.sa_flags &= ~SA_RESTART;
+      SignalHandler.HostAction.sa_flags |= SignalHandler.GuestAction.sa_flags & SA_RESTART;
+    }
+
+#ifdef _M_X86_64
+#define SA_RESTORER 0x04000000
+    SignalHandler.HostAction.sa_flags |= SA_RESTORER;
+    SignalHandler.HostAction.restorer = sigrestore;
+#endif
+
     // Walk the signals we have that are required and make sure to remove it from the mask
     // This'll likely be SIGILL, SIGBUS, SIG63
 
     // If the guest has masked some signals then we need to also mask those signals
-    sigemptyset(&SignalHandler.HostAction.sa_mask);
     for (size_t i = 1; i < HostHandlers.size(); ++i) {
-      if (HostHandlers[i].Required) {
-        sigdelset(&SignalHandler.HostAction.sa_mask, i);
+      if (HostHandlers[i].Required.load(std::memory_order_relaxed)) {
+        SignalHandler.HostAction.sa_mask &= ~(1ULL << (i - 1));
       }
       else if (SigIsMember(&SignalHandler.GuestAction.sa_mask, i)) {
-        sigaddset(&SignalHandler.HostAction.sa_mask, i);
+        SignalHandler.HostAction.sa_mask |= (1ULL << (i - 1));
       }
     }
 
-    // We don't care about the previous handler in this case
-    int Result = sigaction(Signal, &SignalHandler.HostAction, &SignalHandler.OldAction);
-    if (Result < 0 &&
-        !(Signal == 32 || Signal == 33)) {
+    // Only update the old action if we haven't ever been installed
+    int Result = ::syscall(SYS_rt_sigaction, Signal, &SignalHandler.HostAction, SignalHandler.Installed ? nullptr : &SignalHandler.OldAction, 8);
+    if (Result < 0) {
       // Signal 32 and 33 are consumed by glibc. We don't handle this atm
-      LogMan::Msg::E("Failed to install host signal thunk for signal %d: %s", Signal, strerror(errno));
+      LogMan::Msg::A("Failed to install host signal thunk for signal %d: %s", Signal, strerror(errno));
       return false;
     }
 
-    SignalHandler.Installed = true;
     return true;
   }
 
-  void SignalDelegator::UpdateHostThunk(int Signal) {
-    SignalHandler &SignalHandler = HostHandlers[Signal];
-
-    // This only gets called if a guest thunk was already installed and we need to check if we need to update the flags or signal mask
-    if ((SignalHandler.GuestAction.sa_flags ^ SignalHandler.HostAction.sa_flags) & SA_NODEFER) {
-      // NODEFER changed, we need to update this
-      SignalHandler.HostAction.sa_flags |= SignalHandler.GuestAction.sa_flags & SA_NODEFER;
-    }
-
-    if ((SignalHandler.GuestAction.sa_flags ^ SignalHandler.HostAction.sa_flags) & SA_RESTART) {
-      // RESTART changed, we need to update this
-      SignalHandler.HostAction.sa_flags |= SignalHandler.GuestAction.sa_flags & SA_RESTART;
-    }
-
-    if (HostHandlers[Signal].Required == false &&
-        (SignalHandler.GuestAction.sigaction_handler.handler == SIG_DFL ||
-         SignalHandler.GuestAction.sigaction_handler.handler == SIG_IGN)) {
-      // If we are changing a none required signal back to DFL or IGN then we can allow this
-      SignalHandler.HostAction.sa_handler = SignalHandler.GuestAction.sigaction_handler.handler;
-    }
-    else {
-      // Set the handler to host handler
-      SignalHandler.HostAction.sa_sigaction = &SignalHandlerThunk;
-    }
-
-    // Walk the signals we have that are required and make sure to remove it from the mask
-    // This'll likely be SIGILL, SIGBUS, SIG63
-    sigemptyset(&SignalHandler.HostAction.sa_mask);
-    for (size_t i = 1; i < HostHandlers.size(); ++i) {
-      if (HostHandlers[i].Required) {
-        sigdelset(&SignalHandler.HostAction.sa_mask, i);
-      }
-      else if (SigIsMember(&SignalHandler.GuestAction.sa_mask, i)) {
-        sigaddset(&SignalHandler.HostAction.sa_mask, i);
-      }
-    }
-
-    // Only update our host signal here
-    int Result = sigaction(Signal, &SignalHandler.HostAction, nullptr);
-    if (Result < 0 &&
-        !(Signal == 32 || Signal == 33)) {
-      // Signal 32 and 33 are consumed by glibc. We don't handle this atm
-      LogMan::Msg::E("Failed to update host signal thunk for signal %d: %s", Signal, strerror(errno));
-    }
-  }
-
   SignalDelegator::SignalDelegator() {
     // Register this delegate
     LOGMAN_THROW_A(!GlobalDelegator, "Can't register global delegator multiple times!");
@@ -317,13 +291,6 @@ namespace FEX::HLE {
     HostHandlers[SIGKILL].Installed = true;
     HostHandlers[SIGSTOP].Installed = true;
 
-    // glibc reserves these two signals internally
-    // __SIGRTMIN(32) is used for a "cancellation" signal
-    // __SIGRTMIN+1 is used for setuid handling
-    // "Userspace" SIGRTMIN starts at 34 because of this
-    HostHandlers[__SIGRTMIN].Installed   = true;
-    HostHandlers[__SIGRTMIN+1].Installed = true;
-
     // Most signals default to termination
     // These ones are slightly different
     static constexpr std::array<std::pair<int, SignalDelegator::DefaultBehaviour>, 14> SignalDefaultBehaviours = {{
@@ -357,7 +324,7 @@ namespace FEX::HLE {
           ) {
         continue;
       }
-      sigaction(i, &HostHandlers[i].OldAction, nullptr);
+      ::syscall(SYS_rt_sigaction, i, &HostHandlers[i].OldAction, nullptr, 8);
       HostHandlers[i].Installed = false;
     }
     GlobalDelegator = nullptr;
@@ -380,6 +347,9 @@ namespace FEX::HLE {
     if (Result == -1) {
       LogMan::Msg::E("Failed to install alternative signal stack %s", strerror(errno));
     }
+
+    // Get the current host signal mask
+    ::syscall(SYS_rt_sigprocmask, 0, nullptr, &ThreadData.CurrentSignalMask.Val, 8);
   }
 
   void SignalDelegator::UninstallTLSState(FEXCore::Core::InternalThreadState *Thread) {
@@ -587,23 +557,17 @@ namespace FEX::HLE {
         return -EINVAL;
       }
 
+      uint64_t HostMask = ThreadData.CurrentSignalMask.Val;
       // Now actually set the host mask
       // This will hide from the guest that we are not actually setting all of the masks it wants
-      sigset_t HostSet{};
-      sigemptyset(&HostSet);
-
       for (size_t i = 0; i < MAX_SIGNALS; ++i) {
-        if (HostHandlers[i + 1].Required) {
+        if (HostHandlers[i + 1].Required.load(std::memory_order_relaxed)) {
           // If it is a required host signal then we can't mask it
-          continue;
-        }
-
-        if (ThreadData.CurrentSignalMask.Val & (1ULL << i)) {
-          sigaddset(&HostSet, i + 1);
+          HostMask &= ~(1ULL << i);
         }
       }
 
-      pthread_sigmask(SIG_SETMASK, &HostSet, nullptr);
+      ::syscall(SYS_rt_sigprocmask, SIG_SETMASK, &HostMask, nullptr, 8);
     }
 
     CheckForPendingSignals();
@@ -688,4 +652,32 @@ namespace FEX::HLE {
 
     return Result == -1 ? -errno : Result;
   }
+
+  uint64_t SignalDelegator::GuestSignalFD(int fd, const uint64_t *set, size_t sigsetsize, int flags) {
+    if (sigsetsize > sizeof(uint64_t)) {
+      return -EINVAL;
+    }
+
+    sigset_t HostSet{};
+    sigemptyset(&HostSet);
+
+    for (size_t i = 0; i < MAX_SIGNALS; ++i) {
+      if (HostHandlers[i + 1].Required.load(std::memory_order_relaxed)) {
+        // For now skip our internal signals
+        continue;
+      }
+
+      if (ThreadData.CurrentSignalMask.Val & (1ULL << i)) {
+        sigaddset(&HostSet, i + 1);
+      }
+    }
+
+    // XXX: This is a barebones implementation just to get applications that listen for SIGCHLD to work
+    // In the future we need our own listern thread that forwards the result
+    // Thread is necessary to prevent deadlocks for a thread that has signaled on the same thread listening to the FD and blocking is enabled
+    uint64_t Result = signalfd(fd, &HostSet, flags);
+
+    return Result == -1 ? -errno : Result;
+  }
+
 }

Source/Tests/LinuxSyscalls/SignalDelegator.h

@@ -83,6 +83,7 @@ namespace FEX::HLE {
     uint64_t GuestSigPending(uint64_t *set, size_t sigsetsize);
     uint64_t GuestSigSuspend(uint64_t *set, size_t sigsetsize);
     uint64_t GuestSigTimedWait(uint64_t *set, siginfo_t *info, const struct timespec *timeout, size_t sigsetsize);
+    uint64_t GuestSignalFD(int fd, const uint64_t *set, size_t sigsetsize , int flags);
 
     // Called from the thunk handler to handle the signal
     void HandleSignal(int Signal, void *Info, void *UContext);
@@ -98,11 +99,25 @@ namespace FEX::HLE {
       DEFAULT_IGNORE,
     };
 
+    struct kernel_sigaction {
+      union {
+        void (*handler)(int);
+        void (*sigaction)(int, siginfo_t*, void*);
+      };
+
+      uint64_t sa_flags;
+
+#ifdef _M_X86_64
+      void (*restorer)();
+#endif
+      uint64_t sa_mask;
+    };
+
     struct SignalHandler {
       std::atomic<bool> Installed{};
-      bool Required{};
-      struct sigaction HostAction{};
-      struct sigaction OldAction{};
+      std::atomic<bool> Required{};
+      kernel_sigaction HostAction{};
+      kernel_sigaction OldAction{};
       FEXCore::HostSignalDelegatorFunction Handler{};
       FEXCore::HostSignalDelegatorFunction FrontendHandler{};
       FEXCore::HostSignalDelegatorFunctionForGuest GuestHandler{};
@@ -112,7 +127,7 @@ namespace FEX::HLE {
 
     std::array<SignalHandler, MAX_SIGNALS + 1> HostHandlers{};
     bool InstallHostThunk(int Signal);
-    void UpdateHostThunk(int Signal);
+    bool UpdateHostThunk(int Signal);
 
     std::mutex HostDelegatorMutex;
     std::mutex GuestDelegatorMutex;

Source/Tests/LinuxSyscalls/Syscalls.cpp

@@ -362,12 +362,25 @@ uint64_t SyscallHandler::HandleBRK(FEXCore::Core::CpuStateFrame *Frame, void *Ad
           return DataSpace + DataSpaceSize;
         }
 
-        uint64_t NewBRK = (uint64_t)FEXCore::Allocator::mmap((void*)(DataSpace + DataSpaceMaxSize), AllocateNewSize, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+        uint64_t NewBRK{};
+        if (Is64BitMode()) {
+          NewBRK = (uint64_t)FEXCore::Allocator::mmap((void*)(DataSpace + DataSpaceMaxSize), AllocateNewSize, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+        }
+        else {
+          NewBRK = (uint64_t)static_cast<FEX::HLE::x32::x32SyscallHandler*>(FEX::HLE::_SyscallHandler)->GetAllocator()->
+            mmap((void*)(DataSpace + DataSpaceMaxSize), AllocateNewSize, PROT_READ | PROT_WRITE, MAP_FIXED_NOREPLACE | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+        }
 
         if (NewBRK != ~0ULL && NewBRK != (DataSpace + DataSpaceMaxSize)) {
           // Couldn't allocate that the region we wanted
           // Can happen if MAP_FIXED_NOREPLACE isn't understood by the kernel
-          FEXCore::Allocator::munmap(reinterpret_cast<void*>(NewBRK), AllocateNewSize);
+          if (Is64BitMode()) {
+            FEXCore::Allocator::munmap(reinterpret_cast<void*>(NewBRK), AllocateNewSize);
+          }
+          else {
+            static_cast<FEX::HLE::x32::x32SyscallHandler*>(FEX::HLE::_SyscallHandler)->GetAllocator()->
+              munmap(reinterpret_cast<void*>(NewBRK), AllocateNewSize);
+          }
           NewBRK = ~0ULL;
         }
 
@@ -404,7 +417,7 @@ SyscallHandler::SyscallHandler(FEXCore::Context::Context *ctx, FEX::HLE::SignalD
 }
 
 SyscallHandler::~SyscallHandler() {
-  FEXCore::Allocator::munmap(reinterpret_cast<void*>(DataSpace + DataSpaceStartingSize), DataSpaceMaxSize - DataSpaceStartingSize);
+  FEXCore::Allocator::munmap(reinterpret_cast<void*>(DataSpace), DataSpaceMaxSize);
 }
 
 uint32_t SyscallHandler::CalculateHostKernelVersion() {

Source/Tests/LinuxSyscalls/Syscalls/Signals.cpp

@@ -42,6 +42,24 @@ namespace FEX::HLE {
       SYSCALL_ERRNO();
     });
 
+    REGISTER_SYSCALL_IMPL(signalfd, [](FEXCore::Core::CpuStateFrame *Frame, int fd, const uint64_t *mask, size_t sigsetsize) -> uint64_t {
+      return FEX::HLE::_SyscallHandler->GetSignalDelegator()->GuestSignalFD(fd, mask, sigsetsize, 0);
+    });
+
+    REGISTER_SYSCALL_IMPL(signalfd4, [](FEXCore::Core::CpuStateFrame *Frame, int fd, const uint64_t *mask, size_t sigsetsize, int flags) -> uint64_t {
+      return FEX::HLE::_SyscallHandler->GetSignalDelegator()->GuestSignalFD(fd, mask, sigsetsize, flags);
+    });
+
+    REGISTER_SYSCALL_IMPL(rt_sigqueueinfo, [](FEXCore::Core::CpuStateFrame *Frame, pid_t pid, int sig, siginfo_t *info) -> uint64_t {
+      uint64_t Result = ::syscall(SYS_rt_sigqueueinfo, pid, sig, info);
+      SYSCALL_ERRNO();
+    });
+
+    REGISTER_SYSCALL_IMPL(rt_tgsigqueueinfo, [](FEXCore::Core::CpuStateFrame *Frame, pid_t tgid, pid_t tid, int sig, siginfo_t *info) -> uint64_t {
+      uint64_t Result = ::syscall(SYS_rt_tgsigqueueinfo, tgid, tid, sig, info);
+      SYSCALL_ERRNO();
+    });
+
     if (Handler->IsHostKernelVersionAtLeast(5, 1, 0)) {
       REGISTER_SYSCALL_IMPL(pidfd_send_signal, [](FEXCore::Core::CpuStateFrame *Frame, int pidfd, int sig, siginfo_t *info, unsigned int flags) -> uint64_t {
         uint64_t Result = ::syscall(SYS_pidfd_send_signal, pidfd, sig, info, flags);

Source/Tests/LinuxSyscalls/Syscalls/Stubs.cpp

@@ -40,10 +40,6 @@ namespace FEX::HLE {
       return -EPERM;
     });
 
-    REGISTER_SYSCALL_IMPL(rt_sigqueueinfo, [](FEXCore::Core::CpuStateFrame *Frame, pid_t pid, int sig, siginfo_t *uinfo) -> uint64_t {
-      SYSCALL_STUB(rt_sigqueueinfo);
-    });
-
     REGISTER_SYSCALL_IMPL(modify_ldt, [](FEXCore::Core::CpuStateFrame *Frame, int func, void *ptr, unsigned long bytecount) -> uint64_t {
       SYSCALL_STUB(modify_ldt);
     });
@@ -52,18 +48,6 @@ namespace FEX::HLE {
       SYSCALL_STUB(restart_syscall);
     });
 
-    REGISTER_SYSCALL_IMPL(signalfd, [](FEXCore::Core::CpuStateFrame *Frame, int fd, const sigset_t *mask, size_t sizemask) -> uint64_t {
-      SYSCALL_STUB(signalfd);
-    });
-
-    REGISTER_SYSCALL_IMPL(signalfd4, [](FEXCore::Core::CpuStateFrame *Frame, int fd, const sigset_t *mask, size_t sizemask, int flags) -> uint64_t {
-      SYSCALL_STUB(signalfd4);
-    });
-
-    REGISTER_SYSCALL_IMPL(rt_tgsigqueueinfo, [](FEXCore::Core::CpuStateFrame *Frame, pid_t tgid, pid_t tid, int sig, siginfo_t *info) -> uint64_t {
-      SYSCALL_STUB(rt_tgsigqueueinfo);
-    });
-
     REGISTER_SYSCALL_IMPL(rseq, [](FEXCore::Core::CpuStateFrame *Frame,  struct rseq  *rseq, uint32_t rseq_len, int flags, uint32_t sig) -> uint64_t {
       SYSCALL_STUB(rseq);
     });

Source/Tests/LinuxSyscalls/Syscalls/Thread.cpp

@@ -115,12 +115,10 @@ namespace FEX::HLE {
       // Handle child setup now
       if (stack != nullptr) {
         // use specified stack
-        LogMan::Msg::D("@@@@@@@ Fork uses custom stack");
         Frame->State.gregs[FEXCore::X86State::REG_RSP] = reinterpret_cast<uint64_t>(stack);
       } else {
         // In the case of fork and nullptr stack then the child uses the same stack space as the parent
         // Same virtual address, different addressspace
-        LogMan::Msg::D("@@@@@@@ Fork uses parent stack");
       }
 
       if (FEX::HLE::_SyscallHandler->Is64BitMode()) {
@@ -227,12 +225,12 @@ namespace FEX::HLE {
     });
 
     REGISTER_SYSCALL_IMPL(setuid, [](FEXCore::Core::CpuStateFrame *Frame, uid_t uid) -> uint64_t {
-      uint64_t Result = ::setuid(uid);
+      uint64_t Result = ::syscall(SYS_setuid, uid);
       SYSCALL_ERRNO();
     });
 
     REGISTER_SYSCALL_IMPL(setgid, [](FEXCore::Core::CpuStateFrame *Frame, gid_t gid) -> uint64_t {
-      uint64_t Result = ::setgid(gid);
+      uint64_t Result = ::syscall(SYS_setgid, gid);
       SYSCALL_ERRNO();
     });
 
@@ -262,12 +260,12 @@ namespace FEX::HLE {
     });
 
     REGISTER_SYSCALL_IMPL(setreuid, [](FEXCore::Core::CpuStateFrame *Frame, uid_t ruid, uid_t euid) -> uint64_t {
-      uint64_t Result = ::setreuid(ruid, euid);
+      uint64_t Result = ::syscall(SYS_setreuid, ruid, euid);
       SYSCALL_ERRNO();
     });
 
     REGISTER_SYSCALL_IMPL(setregid, [](FEXCore::Core::CpuStateFrame *Frame, gid_t rgid, gid_t egid) -> uint64_t {
-      uint64_t Result = ::setregid(rgid, egid);
+      uint64_t Result = ::syscall(SYS_setregid, rgid, egid);
       SYSCALL_ERRNO();
     });
 
@@ -277,12 +275,12 @@ namespace FEX::HLE {
     });
 
     REGISTER_SYSCALL_IMPL(setgroups, [](FEXCore::Core::CpuStateFrame *Frame, size_t size, const gid_t *list) -> uint64_t {
-      uint64_t Result = ::setgroups(size, list);
+      uint64_t Result = ::syscall(SYS_setgroups, size, list);
       SYSCALL_ERRNO();
     });
 
     REGISTER_SYSCALL_IMPL(setresuid, [](FEXCore::Core::CpuStateFrame *Frame, uid_t ruid, uid_t euid, uid_t suid) -> uint64_t {
-      uint64_t Result = ::setresuid(ruid, euid, suid);
+      uint64_t Result = ::syscall(SYS_setresuid, ruid, euid, suid);
       SYSCALL_ERRNO();
     });
 
@@ -292,7 +290,7 @@ namespace FEX::HLE {
     });
 
     REGISTER_SYSCALL_IMPL(setresgid, [](FEXCore::Core::CpuStateFrame *Frame, gid_t rgid, gid_t egid, gid_t sgid) -> uint64_t {
-      uint64_t Result = ::setresgid(rgid, egid, sgid);
+      uint64_t Result = ::syscall(SYS_setresgid, rgid, egid, sgid);
       SYSCALL_ERRNO();
     });
 

Source/Tests/LinuxSyscalls/x32/Ioctl/sockios.inl

@@ -1,4 +1,10 @@
+#ifndef SIOCGSTAMP_OLD
+#define SIOCGSTAMP_OLD 0x8906
+#endif
 _BASIC_META(SIOCGSTAMP_OLD)
+#ifndef SIOCGSTAMPNS_OLD
+#define SIOCGSTAMPNS_OLD 0x8907
+#endif
 _BASIC_META(SIOCGSTAMPNS_OLD)
 _BASIC_META(SIOCADDRT)
 _BASIC_META(SIOCDELRT)

Source/Tests/UnitTestGenerator.cpp

@@ -2407,7 +2407,7 @@ int main(int argc, char **argv, char **const envp) {
 
   LOGMAN_THROW_A(!Args.empty(), "Not enough arguments");
 
-  FEXCore::X86Tables::InitializeInfoTables(FEXCore::Context::MODE_64BIT);
+  FEXCore::Context::InitializeStaticTables(FEXCore::Context::MODE_64BIT);
 
   Code.reserve(4096*128);
   Filepath = Args[0];

Source/Tools/FEXConfig/Main.cpp

@@ -77,7 +77,8 @@ namespace {
   }
 
   bool OpenFile(std::string Filename,  bool LoadDefault = false) {
-    if (!std::filesystem::exists(Filename)) {
+    std::error_code ec{};
+    if (!std::filesystem::exists(Filename, ec)) {
       if (LoadDefault) {
         LoadDefaultSettings();
         ConfigFilename = Filename;
@@ -98,9 +99,10 @@ namespace {
     std::scoped_lock<std::mutex> lk{NamedRootFSUpdator};
     NamedRootFS.clear();
     std::string RootFS = FEXCore::Config::GetDataDirectory() + "RootFS/";
-    if (!std::filesystem::exists(RootFS)) {
+    std::error_code ec{};
+    if (!std::filesystem::exists(RootFS, ec)) {
       // Doesn't exist, create the the folder as a user convenience
-      if (!std::filesystem::create_directories(RootFS)) {
+      if (!std::filesystem::create_directories(RootFS, ec)) {
         // Well I guess we failed
         return;
       }

Source/Tools/FEXMountDaemon/CMakeLists.txt

@@ -7,3 +7,5 @@ install(TARGETS ${NAME}
   RUNTIME
   DESTINATION bin
   COMPONENT runtime)
+
+target_link_libraries(${NAME} PRIVATE ${STATIC_PIE_OPTIONS})

Source/Tools/FEXMountDaemon/Main.cpp

@@ -2,6 +2,8 @@
 #include <cstdlib>
 #include <cstdint>
 #include <errno.h>
+#include <fcntl.h>
+#include <filesystem>
 #include <poll.h>
 #include <stdio.h>
 #include <string.h>
@@ -11,32 +13,219 @@
 #include <linux/limits.h>
 #include <sys/prctl.h>
 #include <sys/wait.h>
+#include <sys/signal.h>
 #include <sys/inotify.h>
+#include <sys/utsname.h>
 
 namespace {
-static std::atomic<bool> ShuttingDown{};
+static std::atomic<bool> ForceShutdown{};
+static std::atomic<bool> ParentShuttingDown{};
 static int ParentPIDProcess{};
 
 void ActionHandler(int sig, siginfo_t *info, void *context) {
   if (sig == SIGUSR1 &&
       info->si_pid == ParentPIDProcess) {
     // Begin shutdown sequence
-    ShuttingDown = true;
+    ParentShuttingDown = true;
   }
   else if (sig == SIGCHLD) {
-    if (!ShuttingDown.load()) {
+    if (!ParentShuttingDown.load()) {
       // If our child process shutdown while our parent is still running
       // Then the parent loses its rootfs and problems occur
       fprintf(stderr, "FEXMountDaemon child process from squashfuse has closed\n");
       fprintf(stderr, "Expect errors!\n");
-      ShuttingDown = true;
+      ParentShuttingDown = true;
     }
   }
   else {
     // Signal sent directly to process
-    // Ignore it
+    // Force a shutdown
+    fprintf(stderr, "We are being told to shutdown with SIGTERM\n");
+    fprintf(stderr, "Watch out! You might get dangling mount points!\n");
+    ForceShutdown = true;
   }
 }
+
+static int lock_fd {-1};
+static int notify_fd {-1};
+static int watch_fd {-1};
+enum LockFailure {
+  LOCK_FAIL_FATAL,
+  LOCK_FAIL_EXISTS,
+  LOCK_FAIL_CREATION_RACE,
+  LOCK_FAIL_CREATED,
+};
+
+constexpr int USER_PERMS = S_IRWXU | S_IRWXG | S_IRWXO;
+LockFailure CreateINotifyLock(std::string LockPath, const char *MountPath) {
+  lock_fd = open(LockPath.c_str(), O_RDONLY, USER_PERMS);
+  if (lock_fd != -1) {
+    // LockFD already existed!
+    // This will have now refcounted the existing daemon!
+    close(lock_fd);
+    return LOCK_FAIL_EXISTS;
+  }
+
+  lock_fd = open(LockPath.c_str(), O_CREAT | O_RDWR, USER_PERMS);
+  if (lock_fd == -1) {
+    // Couldn't open lock file for some reason
+    // Likely read only file system
+    return LOCK_FAIL_FATAL;
+  }
+
+  LockFailure Failure = LOCK_FAIL_FATAL;
+
+  // Set up the write lock to ensure this doesn't race
+  {
+    // Attempt to open a write lease on the lock file
+    // First thing, mask the signal from the least interface
+    // By default it is SIGIO
+    {
+      sigset_t set;
+      sigemptyset(&set);
+      sigaddset(&set, SIGIO);
+      if (sigprocmask(SIG_BLOCK, &set, nullptr) == -1) {
+        goto err;
+      }
+    }
+
+    // Set the file's lease signal
+    // Even if we set it to default, this is necessary
+    {
+      int Res = fcntl(lock_fd, F_SETSIG, SIGIO);
+      if (Res == -1) {
+        // Shouldn't fail
+        goto err;
+      }
+    }
+
+    // Now attempt to get a write lock on this file
+    {
+      int Res = fcntl(lock_fd, F_SETLEASE, F_WRLCK);
+      if (Res == -1) {
+        // Couldn't get a write lock
+        // This means another FEXMountDaemon is in the process of setting up a rootfs
+        // Early exit, this will be mounted in another process
+        Failure = LOCK_FAIL_CREATION_RACE;
+        goto err;
+      }
+    }
+
+    // Now that we have a lock on the file.
+    // Write where we are going to be mounting
+    // Nothing else can currently open the file for reads yet to see this
+    write(lock_fd, MountPath, strlen(MountPath));
+  }
+
+  // Now while we own the lock on the file, setup our notification handling
+  {
+    notify_fd = inotify_init1(IN_NONBLOCK | IN_CLOEXEC);
+
+    // Watch for lock file opening and closing
+    watch_fd = inotify_add_watch(notify_fd, LockPath.c_str(), IN_OPEN | IN_CLOSE_WRITE | IN_CLOSE_NOWRITE);
+  }
+
+  return LOCK_FAIL_CREATED;
+
+err:
+
+  if (lock_fd != -1) {
+    close (lock_fd);
+  }
+
+  return Failure;
+}
+
+void WatchLock() {
+  // Let go of the file lease file to allow FEX to continue
+  fcntl(lock_fd, F_SETLEASE, F_UNLCK);
+
+  bool BrokenRefCount{};
+  size_t RefCount{};
+  while (true) {
+    constexpr size_t DATA_SIZE = (16 * (sizeof(struct inotify_event) + NAME_MAX + 1));
+    char buf[DATA_SIZE];
+    struct timeval tv{};
+    int Ret{};
+
+    do {
+      fd_set Set{};
+      FD_ZERO(&Set);
+      FD_SET(notify_fd, &Set);
+
+      // Fairly latent ten seconds
+      tv.tv_sec = 10;
+      tv.tv_usec = 0;
+
+      Ret = select(notify_fd + 1, &Set, nullptr, nullptr, &tv);
+      if (Ret == 0 && RefCount == 0) {
+        // We don't have any more users. Clean up
+        // Try to get a write lock again for the squashfs
+        Ret = fcntl(lock_fd, F_SETLEASE, F_WRLCK);
+        if (Ret == 0) {
+          // Managed to grab the lock. Means there aren't any more users on the lock
+          return;
+        }
+        else {
+          // We weren't able to grab the lease on the lock. This means that our Refcounting
+          // was broken by something and our world view is broken now
+          BrokenRefCount = true;
+        }
+      }
+
+      if ((BrokenRefCount && ParentShuttingDown) || ForceShutdown.load()) {
+        // If our ref counting was broken and our parent is gone then try and clean up
+        return;
+      }
+    } while (Ret == 0 || (Ret == -1 && errno == EINTR));
+
+    if (Ret == -1) {
+      return;
+    }
+
+    int Read{};
+    do {
+      Read = read(notify_fd, buf, DATA_SIZE);
+      if (Read > 0) {
+        inotify_event *Event{};
+        for (char *ptr = buf;
+             ptr < (buf + Read);
+             ptr += (sizeof(struct inotify_event) + Event->len)) {
+          Event = reinterpret_cast<inotify_event*>(ptr);
+          if (Event->mask & IN_OPEN) {
+            // Application opened the lock file
+            ++RefCount;
+          }
+
+          if (Event->mask & (IN_CLOSE_WRITE | IN_CLOSE_NOWRITE)) {
+            // Application has finally closed the lock
+            // Either by choice or crashing
+            --RefCount;
+          }
+        }
+      }
+
+    } while (Read > 0);
+  }
+}
+
+void RemoveLock(std::string LockPath) {
+  // Remove the lock file itself
+  unlink(LockPath.c_str());
+
+  // Clear the lease on it since we are shutting down
+  fcntl(lock_fd, F_SETLEASE, F_UNLCK);
+
+  // Now close the watch FD
+  close(watch_fd);
+
+  // Close the notify fd
+  close(notify_fd);
+
+  // Close the lock fd
+  close(lock_fd);
+}
+
 }
 
 int main(int argc, char **argv, char **envp) {
@@ -61,6 +250,30 @@ int main(int argc, char **argv, char **envp) {
   ::prctl(PR_SET_PDEATHSIG, SIGUSR1);
   ::prctl(PR_SET_CHILD_SUBREAPER, 1);
 
+  struct utsname uts{};
+  uname (&uts);
+
+  std::string LockPath = "/tmp/.FEX-";
+  LockPath += std::filesystem::path(SquashFSPath).filename();
+  LockPath += ".lock.";
+  LockPath += uts.nodename;
+
+  // Use lock files to ensure we aren't racing to mount multiple FSes
+  auto Failure = CreateINotifyLock(LockPath, MountPath);
+  if (Failure == LOCK_FAIL_FATAL) {
+    return -1;
+  }
+
+  if (Failure == LOCK_FAIL_EXISTS ||
+      Failure == LOCK_FAIL_CREATION_RACE) {
+    // If the lock already exists
+    // Then we don't need to spin up the mounts at all
+    // Cleanly exit early and let FEX know it can continue
+    uint64_t c = 0;
+    write(pipe_wr, &c, sizeof(c));
+    return 0;
+  }
+
   pid_t pid = fork();
   if (pid == 0) {
     // Child
@@ -128,14 +341,14 @@ int main(int argc, char **argv, char **envp) {
     close(localfds[0]);
 
     // Tell FEX that it can continue booting
+    // FEX will stall on opening the lock file until we let go of the lease
     uint64_t c = 0;
     write(pipe_wr, &c, sizeof(c));
 
-    // Sleep until we receive a shutdown signal
-    // Needs to loop in case of EINTR
-    while (!ShuttingDown.load()) {
-      select(0, nullptr, nullptr, nullptr, nullptr);
-    }
+    // Watch our lock file now for users
+    WatchLock();
+
+    RemoveLock(LockPath);
 
     // fusermount for unmounting the mountpoint, then the squashfuse will exit automatically
     pid = fork();

ThunkLibs/HostLibs/CMakeLists.txt

@@ -46,7 +46,9 @@ add_host_lib(EGL)
 
 generate(libGL function_unpacks tab_function_unpacks ldr ldr_ptrs)
 add_host_lib(GL)
-target_link_libraries(GL-host PRIVATE GL)
+
+find_package(OpenGL REQUIRED)
+target_link_libraries(GL-host PRIVATE OpenGL::GL)
 
 # disabled for now, headers are platform specific
 # find_package(SDL2 REQUIRED)

docs/SourceOutline.md

@@ -1,4 +1,4 @@
-# FEX-2107
+# FEX-2108
 
 ## External/FEXCore
 See [FEXCore/Readme.md](../External/FEXCore/Readme.md) for more details
@@ -71,6 +71,10 @@ Metadata that drives the frontend x86/64 decoding
 - [X86Tables.cpp](../External/FEXCore/Source/Interface/Core/X86Tables.cpp)
 
 #### x86-to-ir
+- [Crypto.cpp](../External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp): Handles x86/64 Crypto instructions to IR
+- [Flags.cpp](../External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp): Handles x86/64 flag generation
+- [Vector.cpp](../External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp): Handles x86/64 Vector instructions to IR
+- [X87.cpp](../External/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp): Handles x86/64 x87 to IR
 - [OpcodeDispatcher.cpp](../External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp): Handles x86/64 ops to IR, no-pf opt, local-flags opt
 
 
@@ -144,6 +148,10 @@ Text -> IR
 - [CPUID.cpp](../External/FEXCore/Source/Interface/Core/CPUID.cpp): Handles presented capability bits for guest cpu
 
 #### dispatcher-implementations
+- [Crypto.cpp](../External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp): Handles x86/64 Crypto instructions to IR
+- [Flags.cpp](../External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp): Handles x86/64 flag generation
+- [Vector.cpp](../External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp): Handles x86/64 Vector instructions to IR
+- [X87.cpp](../External/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp): Handles x86/64 x87 to IR
 - [OpcodeDispatcher.cpp](../External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp): Handles x86/64 ops to IR, no-pf opt, local-flags opt
 
 ## ThunkLibs
@@ -160,10 +168,6 @@ These are generated + glue logic 1:1 thunks unless noted otherwise
 - [libGL_Guest.cpp](../ThunkLibs/libGL/libGL_Guest.cpp): Handles glXGetProcAddress
 - [libGL_Host.cpp](../ThunkLibs/libGL/libGL_Host.cpp): Uses glXGetProcAddress instead of dlsym
 
-#### GLESv2
-- [libGLESv2_Guest.cpp](../ThunkLibs/libGLESv2/libGLESv2_Guest.cpp)
-- [libGLESv2_Host.cpp](../ThunkLibs/libGLESv2/libGLESv2_Host.cpp): Uses eglGetProcAddress instead of dlsym
-
 #### SDL2
 - [libSDL2_Guest.cpp](../ThunkLibs/libSDL2/libSDL2_Guest.cpp): Handles sdlglproc, dload, stubs a few log fns
 - [libSDL2_Host.cpp](../ThunkLibs/libSDL2/libSDL2_Host.cpp)
@@ -282,7 +286,6 @@ x86-64 specific syscall implementations
 - [Thread.cpp](../Source/Tests/LinuxSyscalls/x64/Thread.cpp)
 - [Thread.h](../Source/Tests/LinuxSyscalls/x64/Thread.h)
 - [Time.cpp](../Source/Tests/LinuxSyscalls/x64/Time.cpp)
-- [Types.h](../Source/Tests/LinuxSyscalls/x64/Types.h)
 
 ## unittests
 See [unittests/Readme.md](../unittests/Readme.md) for more details