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Code Issues Packages Projects Releases 67 Wiki Activity
14,721 Commits 11 Branches 71 Tags
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Commit Graph
2721 Commits
Author SHA1 Message Date
Ryan Houdek 921ce59054 Merge pull request #5750 from lioncash/pred 
VectorOps: Make use of unpredicated shifts
 2026-07-15 09:15:04 -07:00
Ryan Houdek a7627ba39a Merge pull request #5751 from lioncash/sq 
VectorOps: Add trivial case handling in VSQXTN2
 2026-07-15 09:06:59 -07:00
Ryan Houdek 0f2463dda2 Merge pull request #5748 from lioncash/invariant 
RegisterAllocationPass: Ensure pair reg invariant
 2026-07-15 09:04:38 -07:00
LC ba8b0afe7a VectorOps: Use unpredicated shifts where applicable for 256-bit scalar shifts 
Lets us trim some output
 2026-07-15 09:10:57 -04:00
LC 98d45a6a9b VectorOps: Make use of unpredicated immediate shifts 
Same behavior, just without introducing a predicate register dependency.
 2026-07-15 08:00:58 -04:00
LC 6bc808cb06 VectorOps: Add trivial case handling in VSQXTN2 
Lets us generate much more optimal code in the event the destination and
lower source are the same.
 2026-07-15 07:49:50 -04:00
LC d6fb60d512 RegisterAllocationPass: Ensure pair reg invariant 
Allows us to actually catch if this requirement ever gets broken in
the future.
 2026-07-15 06:46:24 -04:00
LC ef35474f88 VectorOps: Simplify 256-bit VAddV 
Didn't read the manual close enough on the first read award.
 2026-07-15 04:43:47 -04:00
LC 9e8e87bbb2 AtomicOps: Avoid constrained unpredictable case in TelemetrySetValue() 
STLXR cannot use the same register as both the status register and the
value register, otherwise it's architecturally unpredictable
behavior.

Only applies to hardware without FEAT_LSE, so this only meaningfully
affects hardware using the v8.0 spec, since FEAT_LSE becomes mandatory
in v8.1 and newer.
 2026-07-13 19:08:17 -04:00
LC 2934b01d58 Vector: Indicate 128-bit zero vector in DefaultX87State() 
Same functional behavior, just makes it visually match the store size
below. Technically also avoids delegating off to the 64-bit element
path if a 128-bit constant zero is already loaded.
 2026-07-13 14:07:12 -04:00
Ryan Houdek 28cdae4687 Merge pull request #5737 from lioncash/bsl 
VectorOps: Simplify SVE 256-bit VOrn with BSL2N
 2026-07-13 10:05:08 -07:00
LC 842e22915c VectorOps: Simplify SVE 256-bit VOrn with BSL2N 
Lets us shave off an instruction and also avoid using a temporary
register in some cases. We can also tweak our worst case that requires a
predicate to eliminate the temporary as well.

We can also expand our cmpps cases, so that we can reflect the
BSL2N usages in instcountci.
 2026-07-13 12:27:54 -04:00
LC 24720b67da VectorOps: Make SVE shift==0 case symmetric with ASIMD 
Ensures that we have consistent behavior.
 2026-07-13 10:26:42 -04:00
LC fb2cdc8541 Crypto: Clarify zero vector size in SHA1RNDS4Op() 
This ends up zeroing out the whole 128-bit vector.
 2026-07-12 18:49:27 -04:00
LC 9d3c388664 Crypto: Make use of XAR in SHA1NEXTE when available 
Lets us shave an instruction off on hardware that supports XAR.

Closes #5730
 2026-07-12 16:02:12 -04:00
LC c7f52bcee4 Vector: Centralize masking in InsertScalarFCMPOp 
Ensures that even if someone threw bogus constants in the upper bits of
the immediate, that the special-cased comparison types would still be
handled properly.

We can move the masking in the AVX variant too, just to be consistent.
 2026-07-11 16:07:19 -04:00
LC 929f9a7ad2 Dispatcher: Avoid loading unnecessary reg in vixl single step 
CompileSingleStep only takes one uint64_t, not two.
 2026-07-11 15:03:29 -04:00
Ryan Houdek 821dfe5b98 Merge pull request #5708 from lioncash/mrs 
MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode
 2026-07-11 10:56:27 -07:00
LC 613e9ef701 MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode 
Previously this had the potential to not clear rounding bits properly
depending on incoming FPCR state.
 2026-07-11 10:24:07 -04:00
LC 5080c6ffc5 MemoryOps: Avoid double application of base offset in {Load,Store}ContextIndexed unaligned case 2026-07-11 09:56:56 -04:00
LC 8b0f07b2dc Syscalls: Remove unnecessary usages of namespace FEXCore::IR 
These aren't necessary.
 2026-07-10 21:02:12 -04:00
Ryan Houdek 650f5b784d Merge pull request #5699 from lioncash/spillops 
Arm64Emitter: Wire up conditional FPR spilling in SpillForPreserveAllABICall
 2026-07-10 10:35:19 -07:00
Ryan Houdek c8dd9eefa6 Merge pull request #5698 from lioncash/dead 
ConversionOps: Remove redundant code in Vector_FToS
 2026-07-10 10:35:06 -07:00
Ryan Houdek 37814111de Merge pull request #5692 from lioncash/unary 
Vector: Use unary handler for scalar unary insertions
 2026-07-10 10:26:44 -07:00
Ryan Houdek 1417888a89 Merge pull request #5691 from lioncash/fpr 
Vector: LoadSourceGPR -> LoadSourceFPR for MASKMOVOp
 2026-07-10 10:25:26 -07:00
LC 8436154276 Arm64Emitter: Wire up conditional FPR spilling in SpillForPreserveAllABICall 
Technically, this parameter wasn't being used at all. It was wired up
for filling, but not spilling.
 2026-07-10 10:10:25 -04:00
LC 150b25f29e ConversionOps: Remove redundant code in Vector_FToS 
These are already defined in an outer scope.
 2026-07-10 09:16:35 -04:00
LC 401e542fcd Vector: Use unary handler for scalar unary insertions 
Same behavior, but just uses a more proper handler.
 2026-07-10 07:27:54 -04:00
LC 210514f74b Vector: LoadSourceGPR -> LoadSourceFPR for MASKMOVOp 2026-07-10 07:24:39 -04:00
LC dd838d4ad3 MemoryOps: Make use of current working reg for cache operations 
TMP1 technically isn't initialized properly here until after the first
iteration.
 2026-07-10 07:13:17 -04:00
Ryan Houdek 5f2d19c7aa Merge pull request #5685 from lioncash/faddv 2026-07-10 03:33:43 -07:00
Ryan Houdek 95e7c866cf Merge pull request #5682 from lioncash/pid 2026-07-10 03:20:23 -07:00
Ryan Houdek 2effdb04bd Merge pull request #5684 from lioncash/midr 2026-07-10 03:18:25 -07:00
LC ede09a03db VectorOps: Fix 256-bit FADDV path 
Avoids falling down to the SVE-128 path.
 2026-07-10 05:50:22 -04:00
LC 849d60253c CPUID: Fix MIDR walking in SetupHostHybridFlag() 2026-07-10 05:46:16 -04:00
LC b5660c8a92 MiscOps: Avoid stack misalignment in ProcessorID 
This needs to be an add.
 2026-07-10 05:41:54 -04:00
LC 54263bb5a7 ALUOps: Fix 32-bit MulH case 
These need to be 64-bit multiply and ubfx. Thankfully this case wasn't
actually hit in practice.
 2026-07-10 05:39:14 -04:00
LC caa030714b IR: Remove unused VUShraI 
Given that this is currently unused and that we don't have the signed
equivalent implemented, we can just remove this for now.
 2026-07-10 04:15:52 -04:00
LC 6488dcbb01 ALUOps: Remove unused macros 
These are now unused.
 2026-07-10 03:30:03 -04:00
Ryan Houdek 4a091df8cc Merge pull request #5672 from neobrain/feature_woa_code_cache_bitness 
CodeCache/WoA: Support mixed WoW64/ARM64EC processing
 2026-07-09 14:55:21 -07:00
LC 1b1e46ff6c VectorOps: Join identical branches in VFMLS/VFNMLS 
Same thing, just a little less redundant.
 2026-07-09 16:33:26 -04:00
Ryan Houdek 3370d9af15 Merge pull request #5670 from simon902/MOVDoverride 
Fix movd when prefixed with 0x66
 2026-07-09 13:02:08 -07:00
Ryan Houdek 9306de79ad Merge pull request #5667 from simon902/CVTTSS2SIOverride 
Fix cvttss2si when prefixed with 0x66
 2026-07-09 12:52:00 -07:00
LC 9b7c9f0fb6 Vector: Trim one instruction off insertq 
We can fold a bitwise not and and pair into a bic
 2026-07-09 14:58:04 -04:00
LC 710b85be70 IR: Remove need to specify element size for vector bitwise ops 
Element size doesn't really mean anything here, considering all bits are
acted upon independently of segmentation.

Makes using these ops a little bit less noisy.
 2026-07-09 13:26:51 -04:00
Tony Wasserka 54236df6e0 CodeCache: Record main executable bitness in code map 
Code maps already contain the main executable they were recorded from, so
it's convenient to capture the executable's bitness along the way.
 2026-07-09 17:12:45 +02:00
Simon Scherer fe08b96844 OpcodeDispatcher: Fix cvttss2si when prefixed with 0x66 2026-07-09 11:58:18 +02:00
Simon Scherer 4d78901420 OpcodeDispatcher: Fix movd when prefixed with 0x66 2026-07-09 11:46:48 +02:00
Ryan Houdek 9d18ecc5cb FEXCore: Fixes a crash with multiblock if ProcessorID IR op is encountered 
If during multiblock code discovery a RDTSCP/RDPID instruction was
encountered then ProcessorID has an assert at JIT compile time. Make
sure to early exit with an illegal instruction encoding early instead.
Also make sure to correctly report RDPID support in CPUID, it's
technically a different bit than RDTSCP.

Fixes a crash in Crusader Kings 3's Paradox Launcher installer. Although
the installer seems to fail otherwise for some reason.
 2026-07-08 17:41:03 -07:00
Ryan Houdek 5f2455c502 Merge pull request #5665 from lioncash/blendop 
[SVE256] Handle 256-bit blend operations much more efficiently
 2026-07-08 16:43:20 -07:00