steam-frame/FEX-Emu--FEX
1
0 Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2026-10-06 14:00:16 +02:00
Code Issues Packages Projects Releases 66 Wiki Activity

MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode

Browse Source 
Previously this had the potential to not clear rounding bits properly
depending on incoming FPCR state.
This commit is contained in:
LC committed 2026-07-11 10:24:07 -04:00
1 parent d2f096187c
commit 613e9ef701
3 files changed
+9 -9
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

FEXCore/Source/Interface/Core/JIT/MiscOps.cpp
+1 -1
View File
@@ -168,7 +168,7 @@ DEF_OP(PushRoundingMode) {
} else {
LOGMAN_THROW_A_FMT(Op->RoundMode == 1 || Op->RoundMode == 2, "expect a valid round mode");
and_(ARMEmitter::Size::i64Bit, TMP1, Dest, ~(Op->RoundMode << 22));
and_(ARMEmitter::Size::i64Bit, TMP1, Dest, ~(3 << 22));
orr(ARMEmitter::Size::i64Bit, TMP1, TMP1, (Op->RoundMode == 2 ? 1 : 2) << 22);
}
unittests/InstructionCountCI/AVX128/VEX_map3.json
+4 -4
View File
@@ -2101,7 +2101,7 @@
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffffbfffff",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x800000",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
@@ -2117,7 +2117,7 @@
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff7fffff",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x400000",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
@@ -2179,7 +2179,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, fpcr",
"and x0, x20, #0xffffffffffbfffff",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x800000",
"msr fpcr, x0",
"fcvtn v3.4h, v17.4s",
@@ -2199,7 +2199,7 @@
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff7fffff",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x400000",
"msr fpcr, x0",
"fcvtn v3.4h, v17.4s",
unittests/InstructionCountCI/VEX_map3.json
+4 -4
View File
@@ -2592,7 +2592,7 @@
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffffbfffff",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x800000",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
@@ -2607,7 +2607,7 @@
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff7fffff",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x400000",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
@@ -2662,7 +2662,7 @@
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffffbfffff",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x800000",
"msr fpcr, x0",
"fcvtnt z2.h, p7/m, z17.s",
@@ -2679,7 +2679,7 @@
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff7fffff",
"and x0, x20, #0xffffffffff3fffff",
"orr x0, x0, #0x400000",
"msr fpcr, x0",
"fcvtnt z2.h, p7/m, z17.s",