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VectorOps: Make SVE shift==0 case symmetric with ASIMD

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Ensures that we have consistent behavior.
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LC committed 2026-07-13 10:26:42 -04:00
1 parent 46ec2797ff
commit 24720b67da
1 file changed
+7 -2
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FEXCore/Source/Interface/Core/JIT/VectorOps.cpp
+7 -2
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@@ -3296,8 +3296,13 @@ DEF_OP(VUShrNI) {
const auto Vector = GetVReg(Op->Vector);
if (HostSupportsSVE256 && Is256Bit) {
shrnb(SubRegSize, Dst.Z(), Vector.Z(), BitShift);
uzp1(SubRegSize, Dst.Z(), Dst.Z(), Dst.Z());
if (BitShift == 0) {
mov_imm(ARMEmitter::SubRegSize::i64Bit, VTMP1.Z(), 0);
uzp1(SubRegSize, Dst.Z(), Dst.Z(), VTMP1.Z());
} else {
shrnb(SubRegSize, Dst.Z(), Vector.Z(), BitShift);
uzp1(SubRegSize, Dst.Z(), Dst.Z(), Dst.Z());
}
} else {
if (BitShift == 0) {
xtn(SubRegSize, Dst.D(), Vector.D());