From 24720b67dab9ba8a35963d6f39e7a970792a9c9f Mon Sep 17 00:00:00 2001 From: LC Date: Mon, 13 Jul 2026 09:56:15 -0400 Subject: [PATCH] VectorOps: Make SVE shift==0 case symmetric with ASIMD Ensures that we have consistent behavior. --- FEXCore/Source/Interface/Core/JIT/VectorOps.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp index c491e3445..9e99cc1b2 100644 --- a/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/VectorOps.cpp @@ -3296,8 +3296,13 @@ DEF_OP(VUShrNI) { const auto Vector = GetVReg(Op->Vector); if (HostSupportsSVE256 && Is256Bit) { - shrnb(SubRegSize, Dst.Z(), Vector.Z(), BitShift); - uzp1(SubRegSize, Dst.Z(), Dst.Z(), Dst.Z()); + if (BitShift == 0) { + mov_imm(ARMEmitter::SubRegSize::i64Bit, VTMP1.Z(), 0); + uzp1(SubRegSize, Dst.Z(), Dst.Z(), VTMP1.Z()); + } else { + shrnb(SubRegSize, Dst.Z(), Vector.Z(), BitShift); + uzp1(SubRegSize, Dst.Z(), Dst.Z(), Dst.Z()); + } } else { if (BitShift == 0) { xtn(SubRegSize, Dst.D(), Vector.D());