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MemoryOps: Make use of current working reg for cache operations

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TMP1 technically isn't initialized properly here until after the first
iteration.
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LC committed 2026-07-10 07:13:17 -04:00
1 parent 5f2d19c7aa
commit dd838d4ad3
1 file changed
+2 -2
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FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp
+2 -2
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@@ -2406,7 +2406,7 @@ DEF_OP(CacheLineClear) {
} else {
auto CurrentWorkingReg = MemReg.X();
for (size_t i = 0; i < std::max(1U, 64U / CTX->HostFeatures.DCacheLineSize); ++i) {
dc(ARMEmitter::DataCacheOperation::CIVAC, TMP1);
dc(ARMEmitter::DataCacheOperation::CIVAC, CurrentWorkingReg);
add(ARMEmitter::Size::i64Bit, TMP1, CurrentWorkingReg, CTX->HostFeatures.DCacheLineSize);
CurrentWorkingReg = TMP1;
}
@@ -2435,7 +2435,7 @@ DEF_OP(CacheLineClean) {
} else {
auto CurrentWorkingReg = MemReg.X();
for (size_t i = 0; i < std::max(1U, 64U / CTX->HostFeatures.DCacheLineSize); ++i) {
dc(ARMEmitter::DataCacheOperation::CVAC, TMP1);
dc(ARMEmitter::DataCacheOperation::CVAC, CurrentWorkingReg);
add(ARMEmitter::Size::i64Bit, TMP1, CurrentWorkingReg, CTX->HostFeatures.DCacheLineSize);
CurrentWorkingReg = TMP1;
}