From dd838d4ad3d9fd7d1a88345f85c4abc70e9a130c Mon Sep 17 00:00:00 2001 From: LC Date: Fri, 10 Jul 2026 07:13:15 -0400 Subject: [PATCH] MemoryOps: Make use of current working reg for cache operations TMP1 technically isn't initialized properly here until after the first iteration. --- FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp b/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp index 2cf05d14e..8530fbe98 100644 --- a/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp @@ -2406,7 +2406,7 @@ DEF_OP(CacheLineClear) { } else { auto CurrentWorkingReg = MemReg.X(); for (size_t i = 0; i < std::max(1U, 64U / CTX->HostFeatures.DCacheLineSize); ++i) { - dc(ARMEmitter::DataCacheOperation::CIVAC, TMP1); + dc(ARMEmitter::DataCacheOperation::CIVAC, CurrentWorkingReg); add(ARMEmitter::Size::i64Bit, TMP1, CurrentWorkingReg, CTX->HostFeatures.DCacheLineSize); CurrentWorkingReg = TMP1; } @@ -2435,7 +2435,7 @@ DEF_OP(CacheLineClean) { } else { auto CurrentWorkingReg = MemReg.X(); for (size_t i = 0; i < std::max(1U, 64U / CTX->HostFeatures.DCacheLineSize); ++i) { - dc(ARMEmitter::DataCacheOperation::CVAC, TMP1); + dc(ARMEmitter::DataCacheOperation::CVAC, CurrentWorkingReg); add(ARMEmitter::Size::i64Bit, TMP1, CurrentWorkingReg, CTX->HostFeatures.DCacheLineSize); CurrentWorkingReg = TMP1; }