MiscOps: Avoid stack misalignment in ProcessorID

This needs to be an add.

FEXCore/Source/Interface/Core/JIT/MiscOps.cpp

@@ -282,7 +282,7 @@ DEF_OP(ProcessorID) {
   // Load the values returned by the kernel
   ldp<ARMEmitter::IndexType::OFFSET>(ARMEmitter::WReg::w0, ARMEmitter::WReg::w1, ARMEmitter::Reg::rsp);
   // Deallocate stack space
-  sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 16);
+  add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 16);
 
   // Now that we are done in the syscall we need to carefully peel back the state
   // First unspill the registers from before

unittests/InstructionCountCI/SecondaryGroup.json

@@ -1039,7 +1039,7 @@
         "add x1, sp, #0x4 (4)",
         "svc #0x0",
         "ldp w0, w1, [sp]",
-        "sub sp, sp, #0x10 (16)",
+        "add sp, sp, #0x10 (16)",
         "ldr x25, [x28, #176]",
         "ldr w8, [x28, #1032]",
         "msr nzcv, x8",
@@ -1065,7 +1065,7 @@
         "add x1, sp, #0x4 (4)",
         "svc #0x0",
         "ldp w0, w1, [sp]",
-        "sub sp, sp, #0x10 (16)",
+        "add sp, sp, #0x10 (16)",
         "ldr x25, [x28, #176]",
         "ldr w8, [x28, #1032]",
         "msr nzcv, x8",