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https://github.com/FEX-Emu/FEX.git
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VectorOps: Simplify SVE 256-bit VOrn with BSL2N
Lets us shave off an instruction and also avoid using a temporary register in some cases. We can also tweak our worst case that requires a predicate to eliminate the temporary as well. We can also expand our cmpps cases, so that we can reflect the BSL2N usages in instcountci.
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@@ -1139,9 +1139,16 @@ DEF_OP(VOrn) {
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const auto Vector2 = GetVReg(Op->Vector2);
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if (HostSupportsSVE256 && Is256Bit) {
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const auto Pred = PRED_TMP_32B.Merging();
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not_(ARMEmitter::SubRegSize::i8Bit, VTMP1.Z(), Pred, Vector2.Z());
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orr(Dst.Z(), Vector1.Z(), VTMP1.Z());
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if (Dst == Vector1) {
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bsl2n(Dst.Z(), Dst.Z(), Vector2.Z(), Dst.Z());
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} else if (Dst == Vector2) {
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const auto Pred = PRED_TMP_32B.Merging();
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not_(ARMEmitter::SubRegSize::i8Bit, Dst.Z(), Pred, Dst.Z());
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orr(Dst.Z(), Vector1.Z(), Dst.Z());
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} else {
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movprfx(Dst.Z(), Vector1.Z());
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bsl2n(Dst.Z(), Dst.Z(), Vector2.Z(), Vector1.Z());
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}
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} else if (Is128Bit) {
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orn(Dst.Q(), Vector1.Q(), Vector2.Q());
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} else {
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@@ -1719,6 +1719,331 @@
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x08": {
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"ExpectedInstructionCount": 15,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmeq p0.s, p7/z, z17.s, z17.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z2.s, p0/z, z17.s",
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"orr z2.s, p0/m, z2.s, z0.s",
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"fcmeq p0.s, p7/z, z18.s, z18.s",
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"not z0.s, p0/m, z18.s",
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"movprfx z3.s, p0/z, z18.s",
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"orr z3.s, p0/m, z3.s, z0.s",
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"and z2.d, z2.d, z3.d",
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"fcmeq p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z3.s, p0/z, z17.s",
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"orr z3.s, p0/m, z3.s, z0.s",
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"movprfx z16, z3",
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"bsl2n z16.d, z16.d, z2.d, z3.d"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x09": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmge p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z2.s, p0/z, z17.s",
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"orr z2.s, p0/m, z2.s, z0.s",
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"not z16.b, p7/m, z2.b"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x0A": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmgt p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z2.s, p0/z, z17.s",
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"orr z2.s, p0/m, z2.s, z0.s",
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"not z16.b, p7/m, z2.b"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x0B": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"movi v16.2d, #0x0"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x0C": {
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"ExpectedInstructionCount": 14,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmeq p0.s, p7/z, z17.s, z17.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z2.s, p0/z, z17.s",
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"orr z2.s, p0/m, z2.s, z0.s",
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"fcmeq p0.s, p7/z, z18.s, z18.s",
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"not z0.s, p0/m, z18.s",
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"movprfx z3.s, p0/z, z18.s",
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"orr z3.s, p0/m, z3.s, z0.s",
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"fcmeq p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z4.s, p0/z, z17.s",
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"orr z4.s, p0/m, z4.s, z0.s",
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"bic z2.d, z2.d, z4.d",
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"and z16.d, z2.d, z3.d"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x0D": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmge p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z16.s, p0/z, z17.s",
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x0E": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmgt p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z16.s, p0/z, z17.s",
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x0F": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"mov z16.b, #-1"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x10": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmeq p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z16.s, p0/z, z17.s",
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x11": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmgt p0.s, p7/z, z18.s, z17.s",
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"not z0.s, p0/m, z18.s",
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"movprfx z16.s, p0/z, z18.s",
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x12": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmge p0.s, p7/z, z18.s, z17.s",
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"not z0.s, p0/m, z18.s",
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"movprfx z16.s, p0/z, z18.s",
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x13": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmuo p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z16.s, p0/z, z17.s",
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x14": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmne p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z16.s, p0/z, z17.s",
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x15": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmgt p0.s, p7/z, z18.s, z17.s",
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"not z0.s, p0/m, z18.s",
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"movprfx z2.s, p0/z, z18.s",
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"orr z2.s, p0/m, z2.s, z0.s",
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"not z16.b, p7/m, z2.b"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x16": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmge p0.s, p7/z, z18.s, z17.s",
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"not z0.s, p0/m, z18.s",
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"movprfx z2.s, p0/z, z18.s",
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"orr z2.s, p0/m, z2.s, z0.s",
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"not z16.b, p7/m, z2.b"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x17": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmuo p0.s, p7/z, z17.s, z18.s",
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"not p0.b, p7/z, p0.b",
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"not z0.s, p0/m, z17.s",
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"movprfx z16.s, p0/z, z17.s",
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x18": {
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"ExpectedInstructionCount": 15,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmeq p0.s, p7/z, z17.s, z17.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z2.s, p0/z, z17.s",
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"orr z2.s, p0/m, z2.s, z0.s",
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"fcmeq p0.s, p7/z, z18.s, z18.s",
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"not z0.s, p0/m, z18.s",
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"movprfx z3.s, p0/z, z18.s",
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"orr z3.s, p0/m, z3.s, z0.s",
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"and z2.d, z2.d, z3.d",
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"fcmeq p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z3.s, p0/z, z17.s",
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"orr z3.s, p0/m, z3.s, z0.s",
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"movprfx z16, z3",
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"bsl2n z16.d, z16.d, z2.d, z3.d"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x19": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmge p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z2.s, p0/z, z17.s",
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"orr z2.s, p0/m, z2.s, z0.s",
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"not z16.b, p7/m, z2.b"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x1A": {
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"ExpectedInstructionCount": 5,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmgt p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z2.s, p0/z, z17.s",
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"orr z2.s, p0/m, z2.s, z0.s",
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"not z16.b, p7/m, z2.b"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x1B": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"movi v16.2d, #0x0"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x1C": {
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"ExpectedInstructionCount": 14,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmeq p0.s, p7/z, z17.s, z17.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z2.s, p0/z, z17.s",
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"orr z2.s, p0/m, z2.s, z0.s",
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"fcmeq p0.s, p7/z, z18.s, z18.s",
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"not z0.s, p0/m, z18.s",
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"movprfx z3.s, p0/z, z18.s",
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"orr z3.s, p0/m, z3.s, z0.s",
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"fcmeq p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z4.s, p0/z, z17.s",
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"orr z4.s, p0/m, z4.s, z0.s",
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"bic z2.d, z2.d, z4.d",
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"and z16.d, z2.d, z3.d"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x1D": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmge p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z16.s, p0/z, z17.s",
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x1E": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"fcmgt p0.s, p7/z, z17.s, z18.s",
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"not z0.s, p0/m, z17.s",
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"movprfx z16.s, p0/z, z17.s",
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"orr z16.s, p0/m, z16.s, z0.s"
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]
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},
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"vcmpps ymm0, ymm1, ymm2, 0x1F": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"Map 1 0b00 0xC2 256-bit"
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],
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"ExpectedArm64ASM": [
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"mov z16.b, #-1"
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]
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},
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"vcmppd xmm0, xmm1, xmm2, 0x00": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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