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Code Issues Packages Projects Releases 67 Wiki Activity
14,721 Commits 11 Branches 71 Tags
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3312 Commits
Author SHA1 Message Date
LC 4b4aa1cdbe Arm64Emitter: Pull FillSpecialRegs bools into a struct 
Makes this easily expandable over time without modifying the prototype,
and lets us be a little more informative at call sites.
 2026-07-16 08:07:57 -04:00
Ryan Houdek 921ce59054 Merge pull request #5750 from lioncash/pred 
VectorOps: Make use of unpredicated shifts
 2026-07-15 09:15:04 -07:00
Ryan Houdek a7627ba39a Merge pull request #5751 from lioncash/sq 
VectorOps: Add trivial case handling in VSQXTN2
 2026-07-15 09:06:59 -07:00
Ryan Houdek 34ef28dea5 Merge pull request #5749 from lioncash/calc 
RedundantFlagCalculationElimination: Minor tidying
 2026-07-15 09:05:45 -07:00
Ryan Houdek 0f2463dda2 Merge pull request #5748 from lioncash/invariant 
RegisterAllocationPass: Ensure pair reg invariant
 2026-07-15 09:04:38 -07:00
Ryan Houdek 5ec852637c Merge pull request #5745 from lioncash/addv 
VectorOps: Simplify 256-bit VAddV
 2026-07-15 09:03:57 -07:00
LC ba8b0afe7a VectorOps: Use unpredicated shifts where applicable for 256-bit scalar shifts 
Lets us trim some output
 2026-07-15 09:10:57 -04:00
LC 98d45a6a9b VectorOps: Make use of unpredicated immediate shifts 
Same behavior, just without introducing a predicate register dependency.
 2026-07-15 08:00:58 -04:00
LC 6bc808cb06 VectorOps: Add trivial case handling in VSQXTN2 
Lets us generate much more optimal code in the event the destination and
lower source are the same.
 2026-07-15 07:49:50 -04:00
LC 1325fef703 RFCE: Prefer accessing ops with C instead of CW 
CW is only intended when the op needs to be writable, but most of these
are only reading data.
 2026-07-15 07:06:23 -04:00
LC d2d0ef1803 RFCE: Remove unnecessary std::invoke() 
We can just call this normally (and also make the constituent helper
function internally linked).
 2026-07-15 07:03:09 -04:00
LC d6fb60d512 RegisterAllocationPass: Ensure pair reg invariant 
Allows us to actually catch if this requirement ever gets broken in
the future.
 2026-07-15 06:46:24 -04:00
LC ef35474f88 VectorOps: Simplify 256-bit VAddV 
Didn't read the manual close enough on the first read award.
 2026-07-15 04:43:47 -04:00
LC f2212a497b x87StackOptimizationPass: Remove shadowing variable in PUSHSTACK case 
No behavioral change, since the one in the outer scope does the same thing.
 2026-07-14 08:01:30 -04:00
LC 9e8e87bbb2 AtomicOps: Avoid constrained unpredictable case in TelemetrySetValue() 
STLXR cannot use the same register as both the status register and the
value register, otherwise it's architecturally unpredictable
behavior.

Only applies to hardware without FEAT_LSE, so this only meaningfully
affects hardware using the v8.0 spec, since FEAT_LSE becomes mandatory
in v8.1 and newer.
 2026-07-13 19:08:17 -04:00
LC 4254c0f5a9 RegisterAllocationPass: Function cleanup 
Marks a few functions const or static to clarify usage a little more.
 2026-07-13 15:26:51 -04:00
LC 2934b01d58 Vector: Indicate 128-bit zero vector in DefaultX87State() 
Same functional behavior, just makes it visually match the store size
below. Technically also avoids delegating off to the 64-bit element
path if a 128-bit constant zero is already loaded.
 2026-07-13 14:07:12 -04:00
Ryan Houdek 28cdae4687 Merge pull request #5737 from lioncash/bsl 
VectorOps: Simplify SVE 256-bit VOrn with BSL2N
 2026-07-13 10:05:08 -07:00
LC 842e22915c VectorOps: Simplify SVE 256-bit VOrn with BSL2N 
Lets us shave off an instruction and also avoid using a temporary
register in some cases. We can also tweak our worst case that requires a
predicate to eliminate the temporary as well.

We can also expand our cmpps cases, so that we can reflect the
BSL2N usages in instcountci.
 2026-07-13 12:27:54 -04:00
Ryan Houdek bd150233ce Merge pull request #5736 from lioncash/ushrni 
VectorOps: Make SVE shift==0 case symmetric with ASIMD
 2026-07-13 07:56:25 -07:00
LC 24720b67da VectorOps: Make SVE shift==0 case symmetric with ASIMD 
Ensures that we have consistent behavior.
 2026-07-13 10:26:42 -04:00
Ryan Houdek 356d461123 Merge pull request #5734 from lioncash/bytes 
Common/BitSet: Amend byte size retrieval
 2026-07-13 07:07:00 -07:00
LC c0b2eec5de IR: Enclose straggler Desc comments in brackets 
Ensures the comments get rendered properly in output. We can also
make sure that the IR generation script catches this in the future.
 2026-07-13 08:59:45 -04:00
LC 9b8ae25491 Common/BitSet: Amend byte size retrieval 
This needs to divide by 8 to get a proper byte size for all type sizes.
The only usage of this is currently a uint64_t, so it worked by
coincidence, since sizeof(uint64_t) == 8.
 2026-07-13 08:17:27 -04:00
LC fb2cdc8541 Crypto: Clarify zero vector size in SHA1RNDS4Op() 
This ends up zeroing out the whole 128-bit vector.
 2026-07-12 18:49:27 -04:00
LC 9d3c388664 Crypto: Make use of XAR in SHA1NEXTE when available 
Lets us shave an instruction off on hardware that supports XAR.

Closes #5730
 2026-07-12 16:02:12 -04:00
Ryan Houdek 066250851f Merge pull request #5717 from lioncash/reg 
RegisterAllocationPass: Amend type cast in DecodeSRANode()
 2026-07-11 17:10:27 -07:00
LC 995e2657bb RegisterAllocationPass: Amend type cast in DecodeSRANode() 
Uses the proper type for StoreRegister. Same behavior though, due to
layout.
 2026-07-11 16:39:35 -04:00
LC c7f52bcee4 Vector: Centralize masking in InsertScalarFCMPOp 
Ensures that even if someone threw bogus constants in the upper bits of
the immediate, that the special-cased comparison types would still be
handled properly.

We can move the masking in the AVX variant too, just to be consistent.
 2026-07-11 16:07:19 -04:00
LC 929f9a7ad2 Dispatcher: Avoid loading unnecessary reg in vixl single step 
CompileSingleStep only takes one uint64_t, not two.
 2026-07-11 15:03:29 -04:00
Ryan Houdek 821dfe5b98 Merge pull request #5708 from lioncash/mrs 
MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode
 2026-07-11 10:56:27 -07:00
LC 613e9ef701 MiscOps: Fix round mode clearing for RP/RM modes in PushRoundingMode 
Previously this had the potential to not clear rounding bits properly
depending on incoming FPCR state.
 2026-07-11 10:24:07 -04:00
LC 5080c6ffc5 MemoryOps: Avoid double application of base offset in {Load,Store}ContextIndexed unaligned case 2026-07-11 09:56:56 -04:00
LC 8b0f07b2dc Syscalls: Remove unnecessary usages of namespace FEXCore::IR 
These aren't necessary.
 2026-07-10 21:02:12 -04:00
Ryan Houdek 650f5b784d Merge pull request #5699 from lioncash/spillops 
Arm64Emitter: Wire up conditional FPR spilling in SpillForPreserveAllABICall
 2026-07-10 10:35:19 -07:00
Ryan Houdek c8dd9eefa6 Merge pull request #5698 from lioncash/dead 
ConversionOps: Remove redundant code in Vector_FToS
 2026-07-10 10:35:06 -07:00
Ryan Houdek d5572e322f Merge pull request #5693 from lioncash/ir 
IR: Use begin block type in operator--
 2026-07-10 10:27:13 -07:00
Ryan Houdek 37814111de Merge pull request #5692 from lioncash/unary 
Vector: Use unary handler for scalar unary insertions
 2026-07-10 10:26:44 -07:00
Ryan Houdek 1417888a89 Merge pull request #5691 from lioncash/fpr 
Vector: LoadSourceGPR -> LoadSourceFPR for MASKMOVOp
 2026-07-10 10:25:26 -07:00
LC 8436154276 Arm64Emitter: Wire up conditional FPR spilling in SpillForPreserveAllABICall 
Technically, this parameter wasn't being used at all. It was wired up
for filling, but not spilling.
 2026-07-10 10:10:25 -04:00
LC 150b25f29e ConversionOps: Remove redundant code in Vector_FToS 
These are already defined in an outer scope.
 2026-07-10 09:16:35 -04:00
LC 0bfef9008b IR: Use begin block type in operator-- 
Same behavior, just more correct from a descriptive PoV
 2026-07-10 07:31:25 -04:00
LC 401e542fcd Vector: Use unary handler for scalar unary insertions 
Same behavior, but just uses a more proper handler.
 2026-07-10 07:27:54 -04:00
LC 210514f74b Vector: LoadSourceGPR -> LoadSourceFPR for MASKMOVOp 2026-07-10 07:24:39 -04:00
LC dd838d4ad3 MemoryOps: Make use of current working reg for cache operations 
TMP1 technically isn't initialized properly here until after the first
iteration.
 2026-07-10 07:13:17 -04:00
Ryan Houdek 5f2d19c7aa Merge pull request #5685 from lioncash/faddv 2026-07-10 03:33:43 -07:00
Ryan Houdek 95e7c866cf Merge pull request #5682 from lioncash/pid 2026-07-10 03:20:23 -07:00
Ryan Houdek 2effdb04bd Merge pull request #5684 from lioncash/midr 2026-07-10 03:18:25 -07:00
LC ede09a03db VectorOps: Fix 256-bit FADDV path 
Avoids falling down to the SVE-128 path.
 2026-07-10 05:50:22 -04:00
LC 849d60253c CPUID: Fix MIDR walking in SetupHostHybridFlag() 2026-07-10 05:46:16 -04:00