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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2023-11-17 17:37:24 -04:00
1 parent 2dcae23776
commit cea551c2ac
37 files changed
+20027 -18691
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unittests/InstructionCountCI/AFP/SVE256/Secondary.json
+1 -1
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@@ -25,7 +25,7 @@
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"scvtf v16.2s, v2.2s"
]
}
unittests/InstructionCountCI/AFP/Secondary.json
+1 -1
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@@ -26,7 +26,7 @@
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"scvtf v16.2s, v2.2s"
]
}
unittests/InstructionCountCI/Atomics.json
+682 -862
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unittests/InstructionCountCI/Crypto/H0F3A.json
+2 -2
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@@ -55,7 +55,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2064]",
"ldr q2, [x28, #2080]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
@@ -68,7 +68,7 @@
"0x66 0x0f 0x3a 0xdf"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2064]",
"ldr q2, [x28, #2080]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
unittests/InstructionCountCI/DDD.json
+63 -63
View File
@@ -20,11 +20,11 @@
"0x0f 0x0f 0x0c"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"uzp1 v2.4h, v2.4h, v2.4h",
"sxtl v2.4s, v2.4h",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pi2fd mm0, mm1": {
@@ -33,9 +33,9 @@
"0x0f 0x0f 0x0d"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"scvtf v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pf2iw mm0, mm1": {
@@ -44,11 +44,11 @@
"0x0f 0x0f 0x1c"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fcvtzs v2.2s, v2.2s",
"uzp1 v2.4h, v2.4h, v2.4h",
"sxtl v2.4s, v2.4h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pf2id mm0, mm1": {
@@ -57,9 +57,9 @@
"0x0f 0x0f 0x1d"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrcpv mm0, mm1": {
@@ -68,10 +68,10 @@
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fmov v0.4s, #0x70 (1.0000)",
"fdiv v2.4s, v0.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrsqrtv mm0, mm1": {
@@ -80,57 +80,57 @@
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v2.4s",
"fdiv v2.4s, v0.4s, v1.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfnacc mm0, mm1": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x0f 0x8a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"fsub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfpnacc mm0, mm1": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x0f 0x8e",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"dup v4.2s, v2.s[1]",
"fsub s2, s2, s4",
"faddp v3.4s, v3.4s, v3.4s",
"mov v2.s[1], v3.s[0]",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfcmpge mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0x90",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fcmge v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfmin mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x0f 0x94",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fcmgt v0.4s, v3.4s, v2.4s",
"bif v2.16b, v3.16b, v0.16b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrcp mm0, mm1": {
@@ -139,11 +139,11 @@
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fmov s0, #0x70 (1.0000)",
"fdiv s2, s0, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrsqrt mm0, mm1": {
@@ -152,61 +152,61 @@
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s2",
"fdiv s2, s0, s1",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfsub mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0x9a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fsub v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfadd mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0x9e",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fadd v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfcmpgt mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xa0",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fcmgt v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfmax mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x0f 0xa4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fcmgt v0.4s, v3.4s, v2.4s",
"bit v2.16b, v3.16b, v0.16b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrcpit1 mm0, mm1": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x0f 0xa6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
]
},
"pfrcpit1 mm0, mm0": {
@@ -218,8 +218,8 @@
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x0f 0xa7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
]
},
"pfrsqit1 mm0, mm0": {
@@ -231,38 +231,38 @@
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xaa",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fsub v2.4s, v2.4s, v3.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfcmpeq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xb0",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fcmeq v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfmul mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xb4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"fmul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrcpit2 mm0, mm1": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x0f 0xb6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
]
},
"pfrcpit2 mm0, mm0": {
@@ -278,32 +278,32 @@
"0x0f 0x0f 0xb7"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"smull v2.4s, v2.4h, v3.4h",
"movi v3.4s, #0x80, lsl #8",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #16",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pswapd mm0, mm1": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x0f 0xbb",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"rev64 v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pavgusb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x0f 0xbf",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"urhadd v2.16b, v3.16b, v2.16b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
}
}
unittests/InstructionCountCI/FlagM/Atomics.json
+602 -790
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unittests/InstructionCountCI/FlagM/H0F38.json
+3 -5
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@@ -12,7 +12,7 @@
},
"Instructions": {
"ptest xmm0, xmm1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": [
"0x66 0x0f 0x38 0x17"
],
@@ -25,16 +25,14 @@
"addv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
unittests/InstructionCountCI/FlagM/Primary.json
+888 -1113
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unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+543 -659
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unittests/InstructionCountCI/FlagM/Secondary.json
+142 -188
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@@ -14,7 +14,7 @@
},
"Instructions": {
"ucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": "0x0f 0x2e",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
@@ -31,18 +31,16 @@
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"msr nzcv, x20"
]
},
"comiss xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": "0x0f 0x2f",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
@@ -59,14 +57,12 @@
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"msr nzcv, x20"
]
},
"cmovo ax, bx": {
@@ -296,11 +292,10 @@
]
},
"cmovpe ax, bx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -311,11 +306,10 @@
]
},
"cmovpe eax, ebx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -325,11 +319,10 @@
]
},
"cmovpe rax, rbx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -339,11 +332,10 @@
]
},
"cmovnp ax, bx": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -354,11 +346,10 @@
]
},
"cmovnp eax, ebx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -368,11 +359,10 @@
]
},
"cmovnp rax, rbx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
@@ -553,11 +543,10 @@
]
},
"setpe al": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x9a",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mvn w20, w20",
@@ -566,11 +555,10 @@
]
},
"setnp al": {
"ExpectedInstructionCount": 6,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x9b",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #706]",
"fmov s2, w20",
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"and x20, x20, #0x1",
@@ -680,64 +668,60 @@
]
},
"shld ax, bx, 1": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #1",
"lsr w20, w20, #15",
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x21, #14, #nzCv",
"strb w20, [x28, #706]",
"eor w20, w20, w21",
"eor w20, w26, w21",
"rmif x20, #15, #nzcV"
]
},
"shld ax, bx, 15": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #15",
"lsr w20, w20, #1",
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"rmif x21, #0, #nzCv",
"strb w20, [x28, #706]"
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x21, #0, #nzCv"
]
},
"shld ax, bx, 16": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #16",
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"rmif x21, #63, #nzCv",
"strb w20, [x28, #706]"
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x21, #63, #nzCv"
]
},
"shld ax, bx, 31": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #31",
"lsr w20, w20, #17",
"orr x20, x22, x20",
"bfxil x4, x20, #0, #16",
"cmn wzr, w20, lsl #16",
"rmif x21, #0, #nzCv",
"strb w20, [x28, #706]"
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x21, #0, #nzCv"
]
},
"shld eax, ebx, 1": {
@@ -749,7 +733,7 @@
"extr w4, w21, w20, #31",
"tst w4, w4",
"rmif x21, #30, #nzCv",
"strb w4, [x28, #706]",
"mov x26, x4",
"eor w20, w4, w21",
"rmif x20, #31, #nzcV"
]
@@ -763,7 +747,7 @@
"extr w4, w21, w20, #17",
"tst w4, w4",
"rmif x21, #16, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld eax, ebx, 16": {
@@ -775,7 +759,7 @@
"extr w4, w21, w20, #16",
"tst w4, w4",
"rmif x21, #15, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld eax, ebx, 31": {
@@ -787,7 +771,7 @@
"extr w4, w21, w20, #1",
"tst w4, w4",
"rmif x21, #0, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld rax, rbx, 1": {
@@ -798,7 +782,7 @@
"extr x4, x20, x7, #63",
"tst x4, x4",
"rmif x20, #62, #nzCv",
"strb w4, [x28, #706]",
"mov x26, x4",
"eor x20, x4, x20",
"rmif x20, #63, #nzcV"
]
@@ -811,7 +795,7 @@
"extr x4, x20, x7, #49",
"tst x4, x4",
"rmif x20, #48, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld rax, rbx, 32": {
@@ -822,7 +806,7 @@
"extr x4, x20, x7, #32",
"tst x4, x4",
"rmif x20, #31, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld rax, rbx, 63": {
@@ -833,7 +817,7 @@
"extr x4, x20, x7, #1",
"tst x4, x4",
"rmif x20, #0, #nzCv",
"strb w4, [x28, #706]"
"mov x26, x4"
]
},
"shld ax, bx, cl": {
@@ -861,7 +845,7 @@
"sub w22, w23, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"strb w20, [x28, #706]",
"mov x26, x20",
"eor w20, w21, w20",
"rmif x20, #15, #nzcV"
]
@@ -891,7 +875,7 @@
"sub w22, w23, w22",
"lsr w22, w21, w22",
"rmif x22, #63, #nzCv",
"strb w20, [x28, #706]",
"mov x26, x20",
"eor w20, w21, w20",
"rmif x20, #31, #nzcV"
]
@@ -919,7 +903,7 @@
"sub x21, x23, x21",
"lsr x21, x20, x21",
"rmif x21, #63, #nzCv",
"strb w22, [x28, #706]",
"mov x26, x22",
"eor x20, x20, x22",
"rmif x20, #63, #nzcV"
]
@@ -1104,7 +1088,7 @@
]
},
"cmpxchg al, bl": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
@@ -1116,20 +1100,18 @@
"csel w20, w20, w21, eq",
"bfxil x4, x23, #0, #8",
"bfxil x4, x20, #0, #8",
"sub x20, x22, x23",
"eor w21, w22, w23",
"strb w21, [x28, #708]",
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #24",
"rmif x20, #7, #nzCv",
"eor w21, w22, w23",
"eor w20, w20, w22",
"and w20, w20, w21",
"sub x26, x22, x23",
"eor w27, w22, w23",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"eor w20, w22, w23",
"eor w21, w26, w22",
"and w20, w21, w20",
"rmif x20, #7, #nzcV"
]
},
"cmpxchg [rax], bl": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
@@ -1138,20 +1120,18 @@
"casalb w1, w20, [x4]",
"mov w20, w1",
"bfxil x4, x20, #0, #8",
"sub w22, w21, w20",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"rmif x22, #7, #nzCv",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"eor w20, w21, w20",
"eor w21, w22, w21",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #7, #nzcV"
]
},
"cmpxchg ax, bx": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -1163,20 +1143,18 @@
"csel w20, w20, w21, eq",
"bfxil x4, x23, #0, #16",
"bfxil x4, x20, #0, #16",
"sub x20, x22, x23",
"eor w21, w22, w23",
"strb w21, [x28, #708]",
"strb w20, [x28, #706]",
"cmn wzr, w20, lsl #16",
"rmif x20, #15, #nzCv",
"eor w21, w22, w23",
"eor w20, w20, w22",
"and w20, w20, w21",
"sub x26, x22, x23",
"eor w27, w22, w23",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"eor w20, w22, w23",
"eor w21, w26, w22",
"and w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},
"cmpxchg [rax], bx": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -1185,20 +1163,18 @@
"casalh w1, w20, [x4]",
"mov w20, w1",
"bfxil x4, x20, #0, #16",
"sub w22, w21, w20",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"rmif x22, #15, #nzCv",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"eor w20, w21, w20",
"eor w21, w22, w21",
"eor w21, w26, w21",
"and w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},
"cmpxchg eax, ebx": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -1212,10 +1188,8 @@
"cmp x24, x23",
"csel x4, x21, x22, eq",
"mov x4, x20",
"sub x20, x23, x24",
"eor w21, w23, w24",
"strb w21, [x28, #708]",
"strb w20, [x28, #706]",
"sub x26, x23, x24",
"eor w27, w23, w24",
"cmp w23, w24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1223,7 +1197,7 @@
]
},
"cmpxchg [rax], ebx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -1233,10 +1207,8 @@
"mov w20, w1",
"cmp w20, w21",
"csel x4, x4, x20, eq",
"sub w22, w21, w20",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmp w21, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1244,7 +1216,7 @@
]
},
"cmpxchg rax, rbx": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov x20, x4",
@@ -1254,10 +1226,8 @@
"csel x22, x7, x20, eq",
"mov x4, x21",
"mov x4, x22",
"sub x22, x20, x21",
"eor x23, x20, x21",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"sub x26, x20, x21",
"eor x27, x20, x21",
"cmp x20, x21",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1265,17 +1235,15 @@
]
},
"cmpxchg [rax], rbx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x1, x20",
"casal x1, x7, [x20]",
"mov x4, x1",
"sub x21, x20, x4",
"eor x22, x20, x4",
"strb w22, [x28, #708]",
"strb w21, [x28, #706]",
"sub x26, x20, x4",
"eor x27, x20, x4",
"cmp x20, x4",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -1644,134 +1612,120 @@
]
},
"xadd al, bl": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w7",
"add w22, w20, w21",
"add w26, w20, w21",
"bfxil x7, x20, #0, #8",
"bfxil x4, x22, #0, #8",
"eor w23, w20, w21",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"rmif x22, #7, #nzCv",
"bfxil x4, x26, #0, #8",
"eor w27, w20, w21",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"eor w21, w20, w21",
"eor w20, w22, w20",
"eor w20, w26, w20",
"bic w20, w20, w21",
"rmif x20, #7, #nzcV"
]
},
"xadd [rax], bl": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"ldaddalb w20, w21, [x4]",
"bfxil x7, x21, #0, #8",
"add w22, w21, w20",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #24",
"rmif x22, #7, #nzCv",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"eor w20, w21, w20",
"eor w21, w22, w21",
"eor w21, w26, w21",
"bic w20, w21, w20",
"rmif x20, #7, #nzcV"
]
},
"xadd ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w7",
"add w22, w20, w21",
"add w26, w20, w21",
"bfxil x7, x20, #0, #16",
"bfxil x4, x22, #0, #16",
"eor w23, w20, w21",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"rmif x22, #15, #nzCv",
"bfxil x4, x26, #0, #16",
"eor w27, w20, w21",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"eor w21, w20, w21",
"eor w20, w22, w20",
"eor w20, w26, w20",
"bic w20, w20, w21",
"rmif x20, #15, #nzcV"
]
},
"xadd [rax], bx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ldaddalh w20, w21, [x4]",
"bfxil x7, x21, #0, #16",
"add w22, w21, w20",
"eor w23, w21, w20",
"strb w23, [x28, #708]",
"strb w22, [x28, #706]",
"cmn wzr, w22, lsl #16",
"rmif x22, #15, #nzCv",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"eor w20, w21, w20",
"eor w21, w22, w21",
"eor w21, w26, w21",
"bic w20, w21, w20",
"rmif x20, #15, #nzcV"
]
},
"xadd eax, ebx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w7",
"add w4, w20, w21",
"mov x7, x20",
"eor w22, w20, w21",
"strb w22, [x28, #708]",
"strb w4, [x28, #706]",
"eor w27, w20, w21",
"mov x26, x4",
"cmn w20, w21"
]
},
"xadd [rax], ebx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w7",
"ldaddal w20, w7, [x4]",
"add w21, w7, w20",
"eor w22, w7, w20",
"strb w22, [x28, #708]",
"strb w21, [x28, #706]",
"add w26, w7, w20",
"eor w27, w7, w20",
"cmn w7, w20"
]
},
"xadd rax, rbx": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x7",
"add x4, x20, x21",
"mov x7, x20",
"eor x22, x20, x21",
"strb w22, [x28, #708]",
"strb w4, [x28, #706]",
"eor x27, x20, x21",
"mov x26, x4",
"cmn x20, x21"
]
},
"xadd [rax], rbx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov x20, x7",
"ldaddal x20, x7, [x4]",
"add x21, x7, x20",
"eor x22, x7, x20",
"strb w22, [x28, #708]",
"strb w21, [x28, #706]",
"add x26, x7, x20",
"eor x27, x7, x20",
"cmn x7, x20"
]
},
@@ -1779,7 +1733,7 @@
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"mov x20, #0x201",
"movk x20, #0x804, lsl #16",
"movk x20, #0x2010, lsl #32",
@@ -1797,9 +1751,9 @@
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xf7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"cmlt v2.16b, v2.16b, #0",
"ldr d3, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d4, [x11]",
"bsl v2.8b, v3.8b, v4.8b",
"str d2, [x11]"
unittests/InstructionCountCI/FlagM/SecondaryGroup.json
+99 -111
View File
@@ -759,7 +759,7 @@
"mov w24, w2",
"mov w25, w3",
"mov w20, w24",
"mov w26, w25",
"mov w30, w25",
"cmp x24, x22",
"ccmp x25, x23, #nzcv, eq",
"cset x22, eq",
@@ -767,7 +767,7 @@
"rmif x22, #62, #nZcv",
"cbnz x22, #+0xc",
"mov x4, x20",
"mov x6, x26"
"mov x6, x30"
]
},
"cmpxchg16b [rbp]": {
@@ -786,7 +786,7 @@
"mov x24, x2",
"mov x25, x3",
"mov x20, x24",
"mov x26, x25",
"mov x30, x25",
"cmp x24, x22",
"ccmp x25, x23, #nzcv, eq",
"cset x22, eq",
@@ -794,11 +794,11 @@
"rmif x22, #62, #nZcv",
"cbnz x22, #+0xc",
"mov x4, x20",
"mov x6, x26"
"mov x6, x30"
]
},
"rdrand ax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
@@ -806,16 +806,14 @@
"mov x22, x20",
"mov x20, x21",
"bfxil x4, x22, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdrand eax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
@@ -823,32 +821,28 @@
"mov x22, x20",
"mov x20, x21",
"mov w4, w22",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdrand rax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"cset x21, ne",
"mov x4, x20",
"mov x20, x21",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed ax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
@@ -856,16 +850,14 @@
"mov x22, x20",
"mov x20, x21",
"bfxil x4, x22, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed eax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
@@ -873,26 +865,22 @@
"mov x22, x20",
"mov x20, x21",
"mov w4, w22",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed rax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"cset x21, ne",
"mov x4, x20",
"mov x20, x21",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
@@ -908,9 +896,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlw mm0, 16": {
@@ -918,9 +906,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlw xmm0, 0": {
@@ -956,9 +944,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psraw mm0, 16": {
@@ -966,9 +954,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psraw xmm0, 0": {
@@ -1004,9 +992,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllw mm0, 16": {
@@ -1014,9 +1002,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllw xmm0, 0": {
@@ -1052,9 +1040,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrld mm0, 32": {
@@ -1062,9 +1050,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrld xmm0, 0": {
@@ -1100,9 +1088,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrad mm0, 32": {
@@ -1110,9 +1098,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrad xmm0, 0": {
@@ -1148,9 +1136,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pslld mm0, 32": {
@@ -1158,9 +1146,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pslld xmm0, 0": {
@@ -1196,9 +1184,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlq mm0, 64": {
@@ -1206,9 +1194,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlq xmm0, 0": {
@@ -1267,9 +1255,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllq mm0, 64": {
@@ -1277,9 +1265,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllq xmm0, 0": {
@@ -1308,7 +1296,7 @@
"ExpectedInstructionCount": 58,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1008]",
"ldrh w20, [x28, #1024]",
"strh w20, [x4]",
"mov w20, #0x0",
"ldrb w21, [x28, #747]",
@@ -1322,23 +1310,23 @@
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1010]",
"ldrb w20, [x28, #1026]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #752]",
"str q2, [x4, #32]",
"ldr q2, [x28, #768]",
"str q2, [x4, #48]",
"str q2, [x4, #32]",
"ldr q2, [x28, #784]",
"str q2, [x4, #64]",
"str q2, [x4, #48]",
"ldr q2, [x28, #800]",
"str q2, [x4, #80]",
"str q2, [x4, #64]",
"ldr q2, [x28, #816]",
"str q2, [x4, #96]",
"str q2, [x4, #80]",
"ldr q2, [x28, #832]",
"str q2, [x4, #112]",
"str q2, [x4, #96]",
"ldr q2, [x28, #848]",
"str q2, [x4, #128]",
"str q2, [x4, #112]",
"ldr q2, [x28, #864]",
"str q2, [x4, #128]",
"ldr q2, [x28, #880]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
@@ -1387,7 +1375,7 @@
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1008]",
"strh w20, [x28, #1024]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #747]",
@@ -1400,23 +1388,23 @@
"strb w23, [x28, #746]",
"strb w20, [x28, #750]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1010]",
"strb w20, [x28, #1026]",
"ldr q2, [x4, #32]",
"str q2, [x28, #752]",
"ldr q2, [x4, #48]",
"str q2, [x28, #768]",
"ldr q2, [x4, #64]",
"ldr q2, [x4, #48]",
"str q2, [x28, #784]",
"ldr q2, [x4, #80]",
"ldr q2, [x4, #64]",
"str q2, [x28, #800]",
"ldr q2, [x4, #96]",
"ldr q2, [x4, #80]",
"str q2, [x28, #816]",
"ldr q2, [x4, #112]",
"ldr q2, [x4, #96]",
"str q2, [x28, #832]",
"ldr q2, [x4, #128]",
"ldr q2, [x4, #112]",
"str q2, [x28, #848]",
"ldr q2, [x4, #144]",
"ldr q2, [x4, #128]",
"str q2, [x28, #864]",
"ldr q2, [x4, #144]",
"str q2, [x28, #880]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@@ -1525,7 +1513,7 @@
"ubfx x22, x20, #0, #1",
"cbnz x22, #+0x8",
"b #+0x84",
"ldrh w22, [x28, #1008]",
"ldrh w22, [x28, #1024]",
"strh w22, [x21]",
"mov w22, #0x0",
"ldrb w23, [x28, #747]",
@@ -1533,29 +1521,29 @@
"ldrb w23, [x28, #744]",
"ldrb w24, [x28, #745]",
"ldrb w25, [x28, #746]",
"ldrb w26, [x28, #750]",
"ldrb w30, [x28, #750]",
"orr x22, x22, x23, lsl #8",
"orr x22, x22, x24, lsl #9",
"orr x22, x22, x25, lsl #10",
"orr x22, x22, x26, lsl #14",
"orr x22, x22, x30, lsl #14",
"strh w22, [x21, #2]",
"ldrb w22, [x28, #1010]",
"ldrb w22, [x28, #1026]",
"strb w22, [x21, #4]",
"ldr q2, [x28, #752]",
"str q2, [x21, #32]",
"ldr q2, [x28, #768]",
"str q2, [x21, #48]",
"str q2, [x21, #32]",
"ldr q2, [x28, #784]",
"str q2, [x21, #64]",
"str q2, [x21, #48]",
"ldr q2, [x28, #800]",
"str q2, [x21, #80]",
"str q2, [x21, #64]",
"ldr q2, [x28, #816]",
"str q2, [x21, #96]",
"str q2, [x21, #80]",
"ldr q2, [x28, #832]",
"str q2, [x21, #112]",
"str q2, [x21, #96]",
"ldr q2, [x28, #848]",
"str q2, [x21, #128]",
"str q2, [x21, #112]",
"ldr q2, [x28, #864]",
"str q2, [x21, #128]",
"ldr q2, [x28, #880]",
"str q2, [x21, #144]",
"ubfx x22, x20, #1, #1",
"cbnz x22, #+0x8",
@@ -1610,7 +1598,7 @@
"cbnz x22, #+0x8",
"b #+0x84",
"ldrh w22, [x20]",
"strh w22, [x28, #1008]",
"strh w22, [x28, #1024]",
"ldrh w22, [x20, #2]",
"ubfx w23, w22, #11, #3",
"strb w23, [x28, #747]",
@@ -1623,35 +1611,34 @@
"strb w25, [x28, #746]",
"strb w22, [x28, #750]",
"ldrb w22, [x20, #4]",
"strb w22, [x28, #1010]",
"strb w22, [x28, #1026]",
"ldr q2, [x20, #32]",
"str q2, [x28, #752]",
"ldr q2, [x20, #48]",
"str q2, [x28, #768]",
"ldr q2, [x20, #64]",
"ldr q2, [x20, #48]",
"str q2, [x28, #784]",
"ldr q2, [x20, #80]",
"ldr q2, [x20, #64]",
"str q2, [x28, #800]",
"ldr q2, [x20, #96]",
"ldr q2, [x20, #80]",
"str q2, [x28, #816]",
"ldr q2, [x20, #112]",
"ldr q2, [x20, #96]",
"str q2, [x28, #832]",
"ldr q2, [x20, #128]",
"ldr q2, [x20, #112]",
"str q2, [x28, #848]",
"ldr q2, [x20, #144]",
"ldr q2, [x20, #128]",
"str q2, [x28, #864]",
"ldr q2, [x20, #144]",
"str q2, [x28, #880]",
"b #+0x4c",
"mov w22, #0x0",
"mov w23, #0x37f",
"strh w23, [x28, #1008]",
"strh w23, [x28, #1024]",
"strb w22, [x28, #747]",
"strb w22, [x28, #744]",
"strb w22, [x28, #745]",
"strb w22, [x28, #746]",
"strb w22, [x28, #750]",
"strb w22, [x28, #1010]",
"strb w22, [x28, #1026]",
"movi v2.2d, #0x0",
"str q2, [x28, #752]",
"str q2, [x28, #768]",
"str q2, [x28, #784]",
"str q2, [x28, #800]",
@@ -1659,6 +1646,7 @@
"str q2, [x28, #832]",
"str q2, [x28, #848]",
"str q2, [x28, #864]",
"str q2, [x28, #880]",
"ubfx x22, x21, #1, #1",
"cbnz x22, #+0x8",
"b #+0x48",
unittests/InstructionCountCI/FlagM/SecondaryModRM.json
+9 -5
View File
@@ -14,7 +14,7 @@
},
"Instructions": {
"xgetbv": {
"ExpectedInstructionCount": 50,
"ExpectedInstructionCount": 54,
"Comment": "0xF 0x01 /2 RM-0",
"ExpectedArm64ASM": [
"sub sp, sp, #0xf0 (240)",
@@ -34,13 +34,15 @@
"stp x14, x15, [x28, #88]",
"stp x16, x17, [x28, #104]",
"stp x19, x29, [x28, #120]",
"str x26, [x28, #752]",
"str x27, [x28, #760]",
"add x0, x28, #0xc0 (192)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"ldr x0, [x28, #1096]",
"ldr x2, [x28, #1112]",
"ldr x0, [x28, #1112]",
"ldr x2, [x28, #1128]",
"mov w1, w5",
"blr x2",
"ldr w4, [x28, #728]",
@@ -58,6 +60,8 @@
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"ldr x26, [x28, #752]",
"ldr x27, [x28, #760]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
@@ -81,7 +85,7 @@
"str w0, [x28, #728]",
"str x8, [x28, #40]",
"mov w0, #0x100",
"str x0, [x28, #1040]",
"str x0, [x28, #1056]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
@@ -92,7 +96,7 @@
"ldr w8, [x28, #728]",
"msr nzcv, x8",
"ldr x8, [x28, #40]",
"str xzr, [x28, #1040]",
"str xzr, [x28, #1056]",
"orr x5, x0, x1, lsl #12"
]
}
unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+14 -18
View File
@@ -13,7 +13,7 @@
},
"Instructions": {
"ucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": "0x66 0x0f 0x2e",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
@@ -30,18 +30,16 @@
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"msr nzcv, x20"
]
},
"comisd xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": "0x66 0x0f 0x2f",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
@@ -58,14 +56,12 @@
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"msr nzcv, x20"
]
},
"pmovmskb eax, xmm0": {
unittests/InstructionCountCI/FlagM/Secondary_REP.json
+13 -19
View File
@@ -14,7 +14,7 @@
},
"Instructions": {
"popcnt ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -23,18 +23,16 @@
"addp v0.8b, v0.8b, v0.8b",
"umov w20, v0.b[0]",
"bfxil x4, x20, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
"popcnt eax, ebx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -42,31 +40,27 @@
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"mov w21, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x4, #0x0 (0)",
"cset x22, eq",
"strb w21, [x28, #706]",
"strb w20, [x28, #708]",
"lsl x20, x22, #30",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
"popcnt rax, rbx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"fmov d0, x7",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"mov w21, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x4, #0x0 (0)",
"cset x22, eq",
"strb w21, [x28, #706]",
"strb w20, [x28, #708]",
"lsl x20, x22, #30",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
unittests/InstructionCountCI/FlagM/VEX_map1.json
+28 -36
View File
@@ -15,7 +15,7 @@
},
"Instructions": {
"vucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": [
"Map 1 0b00 0x2e 128-bit"
],
@@ -34,18 +34,16 @@
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"msr nzcv, x20"
]
},
"vucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": [
"Map 1 0b01 0x2e 128-bit"
],
@@ -64,18 +62,16 @@
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"msr nzcv, x20"
]
},
"vcomiss xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": [
"Map 1 0b00 0x2f 128-bit"
],
@@ -94,18 +90,16 @@
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"msr nzcv, x20"
]
},
"vcomisd xmm0, xmm1": {
"ExpectedInstructionCount": 22,
"ExpectedInstructionCount": 20,
"Comment": [
"Map 1 0b01 0x2f 128-bit"
],
@@ -124,14 +118,12 @@
"msr nzcv, x20",
"rmif x22, #63, #nzCv",
"rmif x23, #62, #nZcv",
"eor w20, w21, #0x1",
"strb w20, [x28, #706]",
"mov w20, #0x0",
"mov w21, #0x90000000",
"mrs x22, nzcv",
"bic x21, x22, x21",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"msr nzcv, x20"
]
},
"vpmovmskb rax, xmm0": {
unittests/InstructionCountCI/FlagM/VEX_map2.json
+28 -40
View File
@@ -12,7 +12,7 @@
},
"Instructions": {
"vtestps xmm0, xmm1": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x0e 128-bit"
],
@@ -29,26 +29,24 @@
"addv h2, v2.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"msr nzcv, x24",
"msr nzcv, x22",
"rmif x20, #62, #nZcv",
"rmif x21, #63, #nzCv",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestps ymm0, ymm1": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 34,
"Comment": [
"Map 2 0b01 0x0e 256-bit"
],
@@ -73,26 +71,24 @@
"add v2.8h, v0.8h, v1.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"msr nzcv, x24",
"msr nzcv, x22",
"rmif x20, #62, #nZcv",
"rmif x21, #63, #nzCv",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestpd xmm0, xmm1": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x0f 128-bit"
],
@@ -109,26 +105,24 @@
"addv h2, v2.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"msr nzcv, x24",
"msr nzcv, x22",
"rmif x20, #62, #nZcv",
"rmif x21, #63, #nzCv",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestpd ymm0, ymm1": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 34,
"Comment": [
"Map 2 0b01 0x0f 256-bit"
],
@@ -153,26 +147,24 @@
"add v2.8h, v0.8h, v1.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"msr nzcv, x24",
"msr nzcv, x22",
"rmif x20, #62, #nZcv",
"rmif x21, #63, #nzCv",
"mov w20, #0x90000000",
"mrs x21, nzcv",
"bic x20, x21, x20",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vptest xmm0, xmm1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": [
"Map 2 0b01 0x16 128-bit"
],
@@ -185,21 +177,19 @@
"addv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vptest ymm0, ymm1": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 25,
"Comment": [
"Map 2 0b01 0x16 256-bit"
],
@@ -220,16 +210,14 @@
"add v3.8h, v0.8h, v1.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
@@ -438,7 +426,7 @@
"mov w20, w7",
"mov w21, w5",
"bic w4, w21, w20",
"strb w4, [x28, #706]",
"mov x26, x4",
"tst w4, w4"
]
},
@@ -449,7 +437,7 @@
],
"ExpectedArm64ASM": [
"bic x4, x5, x7",
"strb w4, [x28, #706]",
"mov x26, x4",
"tst x4, x4"
]
},
unittests/InstructionCountCI/FlagM/x87.json
+4935 -3753
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/FlagM/x87_f64.json
+2092 -2004
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/H0F38.json
+165 -153
View File
@@ -17,12 +17,12 @@
"NP 0x0f 0x38 0x00"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"movi v4.16b, #0x87",
"and v3.16b, v3.16b, v4.16b",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pshufb xmm0, xmm1": {
@@ -42,10 +42,10 @@
"NP 0x0f 0x38 0x01"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"addp v2.4h, v3.4h, v2.4h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phaddw xmm0, xmm1": {
@@ -63,10 +63,10 @@
"NP 0x0f 0x38 0x02"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"addp v2.2s, v3.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phaddd xmm0, xmm1": {
@@ -84,12 +84,12 @@
"NP 0x0f 0x38 0x03"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sqadd v2.8h, v4.8h, v2.8h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phaddsw xmm0, xmm1": {
@@ -109,15 +109,15 @@
"NP 0x0f 0x38 0x04"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uxtl v2.8h, v2.8b",
"sxtl v3.8h, v3.8b",
"smull v4.4s, v2.4h, v3.4h",
"smull2 v2.4s, v2.8h, v3.8h",
"addp v2.4s, v4.4s, v2.4s",
"sqxtn v2.4h, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pmaddubsw xmm0, xmm1": {
@@ -147,12 +147,12 @@
"NP 0x0f 0x38 0x05"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sub v2.8h, v4.8h, v2.8h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phsubw xmm0, xmm1": {
@@ -172,12 +172,12 @@
"NP 0x0f 0x38 0x06"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uzp1 v4.2s, v2.2s, v3.2s",
"uzp2 v2.2s, v2.2s, v3.2s",
"sub v2.4s, v4.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phsubd xmm0, xmm1": {
@@ -197,12 +197,12 @@
"NP 0x0f 0x38 0x07"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uzp1 v4.4h, v2.4h, v3.4h",
"uzp2 v2.4h, v2.4h, v3.4h",
"sqsub v2.8h, v4.8h, v2.8h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"phsubsw xmm0, xmm1": {
@@ -222,12 +222,12 @@
"NP 0x0f 0x38 0x08"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sqshl v2.8b, v2.8b, #7",
"srshr v2.8b, v2.8b, #7",
"mul v2.16b, v3.16b, v2.16b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psignb xmm0, xmm1": {
@@ -247,12 +247,12 @@
"NP 0x0f 0x38 0x09"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sqshl v2.4h, v2.4h, #15",
"srshr v2.4h, v2.4h, #15",
"mul v2.8h, v3.8h, v2.8h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psignw xmm0, xmm1": {
@@ -272,12 +272,12 @@
"NP 0x0f 0x38 0x0a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sqshl v2.2s, v2.2s, #31",
"srshr v2.2s, v2.2s, #31",
"mul v2.4s, v3.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psignd xmm0, xmm1": {
@@ -298,14 +298,14 @@
"NP 0x0f 0x38 0x0b"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"smull v2.4s, v2.4h, v3.4h",
"sshr v2.4s, v2.4s, #14",
"movi v3.4s, #0x1, lsl #0",
"add v2.4s, v2.4s, v3.4s",
"shrn v2.4h, v2.4s, #1",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pmulhrsw xmm0, xmm1": {
@@ -389,7 +389,7 @@
]
},
"ptest xmm0, xmm1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": [
"0x66 0x0f 0x38 0x17"
],
@@ -402,16 +402,14 @@
"addv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
@@ -421,9 +419,9 @@
"NP 0x0f 0x38 0x1c"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"abs v2.16b, v2.16b",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pabsb xmm0, xmm1": {
@@ -441,9 +439,9 @@
"NP 0x0f 0x38 0x1d"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"abs v2.8h, v2.8h",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pabsw xmm0, xmm1": {
@@ -461,9 +459,9 @@
"NP 0x0f 0x38 0x1e"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"abs v2.4s, v2.4s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pabsd xmm0, xmm1": {
@@ -629,7 +627,7 @@
"0x66 0x0f 0x38 0x41"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #1952]",
"ldr q2, [x28, #1968]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
@@ -684,117 +682,131 @@
]
},
"sha256rnds2 xmm0, xmm1": {
"ExpectedInstructionCount": 106,
"ExpectedInstructionCount": 120,
"Comment": [
"0x66 0x0f 0x38 0xcb"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x120 (288)",
"sub sp, sp, #0x200 (512)",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"str w23, [sp]",
"mov w23, v17.s[1]",
"mov w24, v17.s[0]",
"str w20, [sp, #96]",
"mov w20, v17.s[2]",
"str w20, [sp, #64]",
"mov w20, v16.s[3]",
"mov w21, v16.s[2]",
"str w21, [sp]",
"mov w21, v17.s[1]",
"str w21, [sp, #32]",
"mov w21, v17.s[0]",
"mov w22, v16.s[1]",
"mov w23, v16.s[0]",
"mov w24, v16.s[0]",
"mov w25, v16.s[1]",
"mov w26, v16.s[0]",
"mov w27, v16.s[0]",
"mov w30, v16.s[1]",
"str w30, [sp, #32]",
"and w30, w23, w24",
"str w24, [sp, #64]",
"bic w24, w25, w23",
"str w25, [sp, #96]",
"eor w24, w30, w24",
"ror w25, w23, #6",
"ror w30, w23, #11",
"eor w25, w25, w30",
"ror w30, w23, #25",
"eor w25, w25, w30",
"add w24, w24, w25",
"add w24, w24, w27",
"add w24, w24, w26",
"and w25, w20, w21",
"and w30, w20, w22",
"eor w25, w25, w30",
"and w30, w21, w22",
"str w25, [sp, #128]",
"ldr w25, [sp, #32]",
"and w30, w25, w21",
"str w21, [sp, #160]",
"str w22, [sp, #128]",
"eor w21, w25, w30",
"add w21, w24, w21",
"ror w22, w20, #2",
"ror w24, w20, #13",
"eor w22, w22, w24",
"ror w24, w20, #22",
"eor w22, w22, w24",
"bic w21, w22, w25",
"str w22, [sp, #192]",
"eor w21, w30, w21",
"ror w22, w25, #6",
"ror w30, w25, #11",
"eor w22, w22, w30",
"ror w30, w25, #25",
"eor w22, w22, w30",
"add w21, w21, w22",
"str w21, [sp, #192]",
"ldr w21, [sp, #64]",
"and w22, w23, w21",
"ldr w24, [sp, #96]",
"bic w25, w24, w23",
"eor w22, w22, w25",
"ror w25, w23, #6",
"ror w30, w23, #11",
"eor w25, w25, w30",
"ror w30, w23, #25",
"eor w25, w25, w30",
"add w22, w22, w25",
"add w22, w22, w27",
"add w22, w22, w26",
"ldr w25, [sp]",
"add w22, w22, w25",
"and w25, w22, w23",
"bic w26, w21, w22",
"eor w25, w25, w26",
"ror w26, w22, #6",
"ror w27, w22, #11",
"eor w26, w26, w27",
"ror w27, w22, #25",
"eor w26, w26, w27",
"add w25, w25, w26",
"ldr w26, [sp, #32]",
"add w25, w25, w26",
"str w26, [sp, #256]",
"add w25, w25, w24",
"str w24, [sp, #224]",
"ldr w24, [sp, #192]",
"and w26, w24, w20",
"ldr w27, [sp, #160]",
"and w30, w24, w27",
"eor w26, w26, w30",
"and w20, w20, w27",
"eor w20, w26, w20",
"add w20, w25, w20",
"ror w25, w24, #2",
"ror w26, w24, #13",
"eor w25, w25, w26",
"ror w26, w24, #22",
"eor w25, w25, w26",
"add w20, w20, w25",
"and w23, w22, w23",
"bic w21, w21, w22",
"eor w21, w23, w21",
"ror w23, w22, #6",
"add w21, w21, w24",
"str w24, [sp, #256]",
"add w21, w21, w23",
"str w23, [sp, #224]",
"ldr w22, [sp, #64]",
"ldr w23, [sp, #96]",
"and w24, w23, w22",
"and w30, w23, w20",
"eor w24, w24, w30",
"and w30, w22, w20",
"str w22, [sp, #320]",
"str w20, [sp, #288]",
"eor w20, w24, w30",
"add w20, w21, w20",
"ror w21, w23, #2",
"ror w22, w23, #13",
"eor w21, w21, w22",
"ror w22, w23, #22",
"eor w21, w21, w22",
"add w20, w20, w21",
"str w20, [sp, #352]",
"ldr w20, [sp, #160]",
"and w21, w25, w20",
"ldr w22, [sp, #192]",
"bic w24, w22, w25",
"eor w21, w21, w24",
"ror w24, w25, #6",
"ror w30, w25, #11",
"eor w24, w24, w30",
"ror w30, w25, #25",
"eor w24, w24, w30",
"add w21, w21, w24",
"ldr w24, [sp, #256]",
"add w21, w21, w24",
"ldr w24, [sp, #224]",
"add w21, w21, w24",
"ldr w24, [sp]",
"add w21, w21, w24",
"and w24, w21, w25",
"bic w30, w20, w21",
"str w20, [sp, #384]",
"eor w20, w24, w30",
"ror w24, w21, #6",
"ror w30, w21, #11",
"eor w24, w24, w30",
"ror w30, w21, #25",
"str w21, [sp, #480]",
"eor w21, w24, w30",
"add w20, w20, w21",
"ldr w21, [sp, #128]",
"add w20, w20, w21",
"str w21, [sp, #448]",
"add w20, w20, w22",
"str w22, [sp, #416]",
"ldr w21, [sp, #352]",
"and w22, w21, w23",
"ldr w24, [sp, #320]",
"and w30, w21, w24",
"eor w22, w22, w30",
"and w23, w23, w24",
"eor w22, w22, w23",
"add w20, w20, w22",
"ror w22, w21, #2",
"ror w23, w21, #13",
"eor w22, w22, w23",
"ror w23, w21, #22",
"eor w22, w22, w23",
"add w20, w20, w22",
"ldr w22, [sp, #480]",
"and w23, w22, w25",
"ldr w24, [sp, #384]",
"bic w24, w24, w22",
"eor w23, w23, w24",
"ror w24, w22, #6",
"ror w25, w22, #11",
"eor w23, w23, w25",
"eor w24, w24, w25",
"ror w25, w22, #25",
"eor w23, w23, w25",
"add w21, w21, w23",
"ldr w23, [sp, #256]",
"add w21, w21, w23",
"ldr w23, [sp, #224]",
"add w21, w21, w23",
"ldr w23, [sp, #128]",
"add w21, w21, w23",
"eor w24, w24, w25",
"add w23, w23, w24",
"ldr w24, [sp, #448]",
"add w23, w23, w24",
"ldr w24, [sp, #416]",
"add w23, w23, w24",
"ldr w24, [sp, #288]",
"add w23, w23, w24",
"mov v2.16b, v16.16b",
"mov v2.s[3], w20",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v2.s[2], w21",
"mov v2.s[1], w23",
"mov v16.16b, v2.16b",
"mov v16.s[0], w22",
"add sp, sp, #0x120 (288)"
"add sp, sp, #0x200 (512)"
]
},
"sha256msg1 xmm0, xmm1": {
@@ -809,26 +821,26 @@
"mov w23, v16.s[1]",
"mov w24, v16.s[0]",
"ror w25, w20, #7",
"ror w26, w20, #18",
"eor w25, w25, w26",
"ror w30, w20, #18",
"eor w25, w25, w30",
"lsr w20, w20, #3",
"eor w20, w25, w20",
"add w20, w21, w20",
"ror w25, w21, #7",
"ror w26, w21, #18",
"eor w25, w25, w26",
"ror w30, w21, #18",
"eor w25, w25, w30",
"lsr w21, w21, #3",
"eor w21, w25, w21",
"add w21, w22, w21",
"ror w25, w22, #7",
"ror w26, w22, #18",
"eor w25, w25, w26",
"ror w30, w22, #18",
"eor w25, w25, w30",
"lsr w22, w22, #3",
"eor w22, w25, w22",
"add w22, w23, w22",
"ror w25, w23, #7",
"ror w26, w23, #18",
"eor w25, w25, w26",
"ror w30, w23, #18",
"eor w25, w25, w30",
"lsr w23, w23, #3",
"eor w23, w25, w23",
"add w23, w24, w23",
unittests/InstructionCountCI/H0F3A.json
+238 -212
View File
@@ -20,8 +20,8 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x28, #752]"
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
]
},
"palignr mm0, mm1, 1": {
@@ -30,10 +30,10 @@
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #752]",
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ext v2.8b, v2.8b, v3.8b, #1",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"palignr mm0, mm1, 255": {
@@ -43,7 +43,7 @@
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"roundps xmm0, xmm1, 00000000b": {
@@ -315,7 +315,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2080]",
"ldr q2, [x28, #2096]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -325,7 +325,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2096]",
"ldr q2, [x28, #2112]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -344,7 +344,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2112]",
"ldr q2, [x28, #2128]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -364,7 +364,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2128]",
"ldr q2, [x28, #2144]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -383,7 +383,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2144]",
"ldr q2, [x28, #2160]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -393,7 +393,7 @@
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2160]",
"ldr q2, [x28, #2176]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
@@ -462,7 +462,7 @@
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1704]",
"ldr x0, [x28, #1720]",
"ldr q2, [x0, #3440]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
@@ -1338,271 +1338,297 @@
]
},
"sha1rnds4 xmm0, xmm1, 00b": {
"ExpectedInstructionCount": 59,
"ExpectedInstructionCount": 65,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x20 (32)",
"sub sp, sp, #0x60 (96)",
"mov w20, #0x7999",
"movk w20, #0x5a82, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v17.s[1]",
"mov w23, v17.s[0]",
"str w23, [sp]",
"mov w23, v16.s[3]",
"mov w24, v16.s[2]",
"mov w25, v16.s[1]",
"mov w26, v16.s[0]",
"and w27, w24, w25",
"bic w30, w26, w24",
"eor w27, w27, w30",
"ror w30, w23, #27",
"add w27, w27, w30",
"add w20, w27, w20",
"mov w27, #0x7999",
"movk w27, #0x5a82, lsl #16",
"add w20, w20, w27",
"ror w24, w24, #2",
"and w27, w23, w24",
"bic w30, w25, w23",
"eor w27, w27, w30",
"ror w30, w20, #27",
"add w27, w27, w30",
"add w21, w27, w21",
"add w21, w21, w26",
"mov w26, #0x7999",
"movk w26, #0x5a82, lsl #16",
"add w21, w21, w26",
"ror w23, w23, #2",
"and w27, w20, w23",
"bic w30, w24, w20",
"eor w27, w27, w30",
"str w21, [sp, #64]",
"mov w21, v17.s[1]",
"str w21, [sp, #32]",
"mov w21, v17.s[0]",
"str w21, [sp]",
"mov w21, v16.s[3]",
"mov w22, v16.s[2]",
"mov w23, v16.s[1]",
"mov w24, v16.s[0]",
"and w25, w22, w23",
"bic w30, w24, w22",
"eor w25, w25, w30",
"ror w30, w21, #27",
"add w27, w27, w30",
"add w22, w27, w22",
"add w22, w22, w25",
"add w22, w22, w26",
"ror w20, w20, #2",
"and w25, w21, w20",
"bic w23, w23, w21",
"eor w23, w25, w23",
"ror w25, w22, #27",
"add w23, w23, w25",
"ldr w25, [sp]",
"add w23, w23, w25",
"add w23, w23, w24",
"add w23, w23, w26",
"add w25, w25, w30",
"add w20, w25, w20",
"mov w25, #0x7999",
"movk w25, #0x5a82, lsl #16",
"add w20, w20, w25",
"ror w22, w22, #2",
"and w25, w21, w22",
"bic w30, w23, w21",
"eor w25, w25, w30",
"ror w30, w20, #27",
"add w25, w25, w30",
"ldr w30, [sp, #64]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0x7999",
"movk w25, #0x5a82, lsl #16",
"add w24, w24, w25",
"ror w21, w21, #2",
"and w25, w20, w21",
"bic w30, w22, w20",
"eor w25, w25, w30",
"ror w30, w24, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w23, w25, w23",
"mov w25, #0x7999",
"movk w25, #0x5a82, lsl #16",
"add w23, w23, w25",
"ror w20, w20, #2",
"and w30, w24, w20",
"bic w21, w21, w24",
"eor w21, w30, w21",
"ror w30, w23, #27",
"add w21, w21, w30",
"ldr w30, [sp]",
"add w21, w21, w30",
"add w21, w21, w22",
"add w21, w21, w25",
"ror w22, w24, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[1], w21",
"mov v2.s[3], w21",
"mov v2.s[2], w23",
"mov v2.s[1], w22",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
"add sp, sp, #0x60 (96)"
]
},
"sha1rnds4 xmm0, xmm1, 01b": {
"ExpectedInstructionCount": 55,
"ExpectedInstructionCount": 61,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x20 (32)",
"sub sp, sp, #0x60 (96)",
"mov w20, #0xeba1",
"movk w20, #0x6ed9, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v17.s[1]",
"mov w23, v17.s[0]",
"str w23, [sp]",
"mov w23, v16.s[3]",
"mov w24, v16.s[2]",
"mov w25, v16.s[1]",
"mov w26, v16.s[0]",
"eor w27, w24, w25",
"eor w27, w27, w26",
"ror w30, w23, #27",
"add w27, w27, w30",
"add w20, w27, w20",
"mov w27, #0xeba1",
"movk w27, #0x6ed9, lsl #16",
"add w20, w20, w27",
"ror w24, w24, #2",
"eor w27, w23, w24",
"eor w27, w27, w25",
"ror w30, w20, #27",
"add w27, w27, w30",
"add w21, w27, w21",
"add w21, w21, w26",
"mov w26, #0xeba1",
"movk w26, #0x6ed9, lsl #16",
"add w21, w21, w26",
"ror w23, w23, #2",
"eor w27, w20, w23",
"eor w27, w27, w24",
"ror w30, w21, #27",
"add w27, w27, w30",
"add w22, w27, w22",
"add w22, w22, w25",
"add w22, w22, w26",
"ror w20, w20, #2",
"eor w25, w21, w20",
"eor w23, w25, w23",
"str w22, [sp, #32]",
"mov w22, v17.s[0]",
"str w22, [sp]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"mov w24, v16.s[1]",
"mov w25, v16.s[0]",
"eor w30, w23, w24",
"eor w30, w30, w25",
"str w25, [sp, #64]",
"ror w25, w22, #27",
"add w23, w23, w25",
"ldr w25, [sp]",
"add w23, w23, w25",
"add w23, w23, w24",
"add w23, w23, w26",
"add w25, w30, w25",
"add w20, w25, w20",
"mov w25, #0xeba1",
"movk w25, #0x6ed9, lsl #16",
"add w20, w20, w25",
"ror w23, w23, #2",
"eor w25, w22, w23",
"eor w25, w25, w24",
"ror w30, w20, #27",
"add w25, w25, w30",
"add w21, w25, w21",
"ldr w25, [sp, #64]",
"add w21, w21, w25",
"mov w25, #0xeba1",
"movk w25, #0x6ed9, lsl #16",
"add w21, w21, w25",
"ror w22, w22, #2",
"eor w25, w20, w22",
"eor w25, w25, w23",
"ror w30, w21, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0xeba1",
"movk w25, #0x6ed9, lsl #16",
"add w24, w24, w25",
"ror w20, w20, #2",
"eor w30, w21, w20",
"eor w22, w30, w22",
"ror w30, w24, #27",
"add w22, w22, w30",
"ldr w30, [sp]",
"add w22, w22, w30",
"add w22, w22, w23",
"add w22, w22, w25",
"ror w21, w21, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[3], w22",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
"add sp, sp, #0x60 (96)"
]
},
"sha1rnds4 xmm0, xmm1, 10b": {
"ExpectedInstructionCount": 67,
"ExpectedInstructionCount": 75,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x20 (32)",
"sub sp, sp, #0x60 (96)",
"mov w20, #0xbcdc",
"movk w20, #0x8f1b, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v17.s[1]",
"mov w23, v17.s[0]",
"str w23, [sp]",
"mov w23, v16.s[3]",
"mov w24, v16.s[2]",
"mov w25, v16.s[1]",
"mov w26, v16.s[0]",
"and w27, w24, w25",
"and w30, w24, w26",
"eor w27, w27, w30",
"and w30, w25, w26",
"eor w27, w27, w30",
"ror w30, w23, #27",
"add w27, w27, w30",
"add w20, w27, w20",
"mov w27, #0xbcdc",
"movk w27, #0x8f1b, lsl #16",
"add w20, w20, w27",
"ror w24, w24, #2",
"and w27, w23, w24",
"and w30, w23, w25",
"eor w27, w27, w30",
"and w30, w24, w25",
"eor w27, w27, w30",
"ror w30, w20, #27",
"add w27, w27, w30",
"add w21, w27, w21",
"add w21, w21, w26",
"mov w26, #0xbcdc",
"movk w26, #0x8f1b, lsl #16",
"add w21, w21, w26",
"ror w23, w23, #2",
"and w27, w20, w23",
"and w30, w20, w24",
"eor w27, w27, w30",
"str w21, [sp, #64]",
"mov w21, v17.s[1]",
"str w21, [sp, #32]",
"mov w21, v17.s[0]",
"str w21, [sp]",
"mov w21, v16.s[3]",
"mov w22, v16.s[2]",
"mov w23, v16.s[1]",
"mov w24, v16.s[0]",
"and w25, w22, w23",
"and w30, w22, w24",
"eor w25, w25, w30",
"and w30, w23, w24",
"eor w27, w27, w30",
"eor w25, w25, w30",
"ror w30, w21, #27",
"add w27, w27, w30",
"add w22, w27, w22",
"add w22, w22, w25",
"add w22, w22, w26",
"ror w20, w20, #2",
"and w25, w21, w20",
"and w27, w21, w23",
"eor w25, w25, w27",
"and w23, w20, w23",
"eor w23, w25, w23",
"ror w25, w22, #27",
"add w23, w23, w25",
"ldr w25, [sp]",
"add w23, w23, w25",
"add w23, w23, w24",
"add w23, w23, w26",
"add w25, w25, w30",
"add w20, w25, w20",
"mov w25, #0xbcdc",
"movk w25, #0x8f1b, lsl #16",
"add w20, w20, w25",
"ror w22, w22, #2",
"and w25, w21, w22",
"and w30, w21, w23",
"eor w25, w25, w30",
"and w30, w22, w23",
"eor w25, w25, w30",
"ror w30, w20, #27",
"add w25, w25, w30",
"ldr w30, [sp, #64]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0xbcdc",
"movk w25, #0x8f1b, lsl #16",
"add w24, w24, w25",
"ror w21, w21, #2",
"and w25, w20, w21",
"and w30, w20, w22",
"eor w25, w25, w30",
"and w30, w21, w22",
"eor w25, w25, w30",
"ror w30, w24, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w23, w25, w23",
"mov w25, #0xbcdc",
"movk w25, #0x8f1b, lsl #16",
"add w23, w23, w25",
"ror w20, w20, #2",
"and w25, w24, w20",
"and w30, w24, w21",
"eor w25, w25, w30",
"and w21, w20, w21",
"eor w21, w25, w21",
"ror w25, w23, #27",
"add w21, w21, w25",
"ldr w25, [sp]",
"add w21, w21, w25",
"add w21, w21, w22",
"mov w22, #0xbcdc",
"movk w22, #0x8f1b, lsl #16",
"add w21, w21, w22",
"ror w22, w24, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[1], w21",
"mov v2.s[3], w21",
"mov v2.s[2], w23",
"mov v2.s[1], w22",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
"add sp, sp, #0x60 (96)"
]
},
"sha1rnds4 xmm0, xmm1, 11b": {
"ExpectedInstructionCount": 55,
"ExpectedInstructionCount": 61,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x20 (32)",
"sub sp, sp, #0x60 (96)",
"mov w20, #0xc1d6",
"movk w20, #0xca62, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v17.s[1]",
"mov w23, v17.s[0]",
"str w23, [sp]",
"mov w23, v16.s[3]",
"mov w24, v16.s[2]",
"mov w25, v16.s[1]",
"mov w26, v16.s[0]",
"eor w27, w24, w25",
"eor w27, w27, w26",
"ror w30, w23, #27",
"add w27, w27, w30",
"add w20, w27, w20",
"mov w27, #0xc1d6",
"movk w27, #0xca62, lsl #16",
"add w20, w20, w27",
"ror w24, w24, #2",
"eor w27, w23, w24",
"eor w27, w27, w25",
"ror w30, w20, #27",
"add w27, w27, w30",
"add w21, w27, w21",
"add w21, w21, w26",
"mov w26, #0xc1d6",
"movk w26, #0xca62, lsl #16",
"add w21, w21, w26",
"ror w23, w23, #2",
"eor w27, w20, w23",
"eor w27, w27, w24",
"ror w30, w21, #27",
"add w27, w27, w30",
"add w22, w27, w22",
"add w22, w22, w25",
"add w22, w22, w26",
"ror w20, w20, #2",
"eor w25, w21, w20",
"eor w23, w25, w23",
"str w22, [sp, #32]",
"mov w22, v17.s[0]",
"str w22, [sp]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"mov w24, v16.s[1]",
"mov w25, v16.s[0]",
"eor w30, w23, w24",
"eor w30, w30, w25",
"str w25, [sp, #64]",
"ror w25, w22, #27",
"add w23, w23, w25",
"ldr w25, [sp]",
"add w23, w23, w25",
"add w23, w23, w24",
"add w23, w23, w26",
"add w25, w30, w25",
"add w20, w25, w20",
"mov w25, #0xc1d6",
"movk w25, #0xca62, lsl #16",
"add w20, w20, w25",
"ror w23, w23, #2",
"eor w25, w22, w23",
"eor w25, w25, w24",
"ror w30, w20, #27",
"add w25, w25, w30",
"add w21, w25, w21",
"ldr w25, [sp, #64]",
"add w21, w21, w25",
"mov w25, #0xc1d6",
"movk w25, #0xca62, lsl #16",
"add w21, w21, w25",
"ror w22, w22, #2",
"eor w25, w20, w22",
"eor w25, w25, w23",
"ror w30, w21, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0xc1d6",
"movk w25, #0xca62, lsl #16",
"add w24, w24, w25",
"ror w20, w20, #2",
"eor w30, w21, w20",
"eor w22, w30, w22",
"ror w30, w24, #27",
"add w22, w22, w30",
"ldr w30, [sp]",
"add w22, w22, w30",
"add w22, w22, w23",
"add w22, w22, w25",
"ror w21, w21, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w23",
"mov v2.s[2], w22",
"mov v2.s[3], w22",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x20 (32)"
"add sp, sp, #0x60 (96)"
]
}
}
unittests/InstructionCountCI/Primary.json
+1018 -1245
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/PrimaryGroup.json
+677 -785
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/Primary_32Bit.json
+109 -137
View File
@@ -27,7 +27,7 @@
"strh w20, [x28, #136]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"ldr w20, [x0, #896]",
"str w20, [x28, #152]"
]
},
@@ -56,7 +56,7 @@
"strh w20, [x28, #140]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"ldr w20, [x0, #896]",
"str w20, [x28, #160]"
]
},
@@ -77,18 +77,16 @@
"strh w20, [x28, #142]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"ldr w20, [x0, #896]",
"str w20, [x28, #164]"
]
},
"daa": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 56,
"Comment": "0x27",
"ExpectedArm64ASM": [
"cset w20, hs",
"ldrb w21, [x28, #708]",
"ldrb w22, [x28, #706]",
"eor w21, w21, w22",
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"uxtb w22, w4",
"mrs x23, nzcv",
@@ -100,10 +98,9 @@
"cset x23, hi",
"orr x21, x21, x23",
"msr nzcv, x24",
"cbnz x21, #+0x10",
"mov w21, #0x0",
"strb w21, [x28, #708]",
"b #+0x30",
"cbnz x21, #+0xc",
"mov w27, #0x0",
"b #+0x2c",
"add x21, x22, #0x6 (6)",
"bfxil w4, w21, #0, #8",
"cset w21, hs",
@@ -112,8 +109,7 @@
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"mov w23, #0x10",
"strb w23, [x28, #708]",
"mov w27, #0x10",
"msr nzcv, x21",
"mrs x21, nzcv",
"cmp x22, #0x99 (153)",
@@ -131,33 +127,28 @@
"mrs x20, nzcv",
"orr w20, w20, #0x20000000",
"msr nzcv, x20",
"uxtb w20, w4",
"and x21, x20, #0x80",
"mrs x22, nzcv",
"uxtb w26, w4",
"and x20, x26, #0x80",
"mrs x21, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, hs",
"mov w0, w21",
"bfi w0, w20, #31, #1",
"mov w20, w0",
"and x21, x26, #0xff",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"strb w20, [x28, #706]",
"ldrb w22, [x28, #708]",
"eor w20, w22, w20",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"cset x21, eq",
"bfi w20, w21, #30, #1",
"eor w27, w27, w26",
"msr nzcv, x20"
]
},
"das": {
"ExpectedInstructionCount": 63,
"ExpectedInstructionCount": 56,
"Comment": "0x2f",
"ExpectedArm64ASM": [
"cset w20, hs",
"ldrb w21, [x28, #708]",
"ldrb w22, [x28, #706]",
"eor w21, w21, w22",
"eor w21, w27, w26",
"ubfx w21, w21, #4, #1",
"uxtb w22, w4",
"mrs x23, nzcv",
@@ -169,10 +160,9 @@
"cset x23, hi",
"orr x21, x21, x23",
"msr nzcv, x24",
"cbnz x21, #+0x10",
"mov w21, #0x0",
"strb w21, [x28, #708]",
"b #+0x30",
"cbnz x21, #+0xc",
"mov w27, #0x0",
"b #+0x2c",
"sub x21, x22, #0x6 (6)",
"bfxil w4, w21, #0, #8",
"cset w21, hs",
@@ -181,8 +171,7 @@
"mov w0, w23",
"bfi w0, w21, #29, #1",
"mov w21, w0",
"mov w23, #0x10",
"strb w23, [x28, #708]",
"mov w27, #0x10",
"msr nzcv, x21",
"mrs x21, nzcv",
"cmp x22, #0x99 (153)",
@@ -200,32 +189,27 @@
"mrs x20, nzcv",
"orr w20, w20, #0x20000000",
"msr nzcv, x20",
"uxtb w20, w4",
"and x21, x20, #0x80",
"mrs x22, nzcv",
"uxtb w26, w4",
"and x20, x26, #0x80",
"mrs x21, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, hs",
"mov w0, w21",
"bfi w0, w20, #31, #1",
"mov w20, w0",
"and x21, x26, #0xff",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"strb w20, [x28, #706]",
"ldrb w22, [x28, #708]",
"eor w20, w22, w20",
"strb w20, [x28, #708]",
"msr nzcv, x21"
"cset x21, eq",
"bfi w20, w21, #30, #1",
"eor w27, w27, w26",
"msr nzcv, x20"
]
},
"aaa": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 24,
"Comment": "0x37",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"ldrb w21, [x28, #706]",
"eor w20, w20, w21",
"eor w20, w27, w26",
"ubfx w20, w20, #4, #1",
"uxtb w21, w4",
"uxth w22, w4",
@@ -235,31 +219,27 @@
"cset x21, hi",
"orr x20, x20, x21",
"msr nzcv, x23",
"cbnz x20, #+0x20",
"cbnz x20, #+0x1c",
"mov w20, #0xff0f",
"and x20, x22, x20",
"bfxil w4, w20, #0, #16",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"msr nzcv, x20",
"b #+0x24",
"mov w27, #0x0",
"msr nzcv, x27",
"b #+0x20",
"add x20, x22, #0x106 (262)",
"mov w21, #0xff0f",
"and x20, x20, x21",
"bfxil w4, w20, #0, #16",
"mov w20, #0x20000000",
"mov w21, #0x10",
"strb w21, [x28, #708]",
"mov w27, #0x10",
"msr nzcv, x20"
]
},
"aas": {
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 25,
"Comment": "0x3f",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"ldrb w21, [x28, #706]",
"eor w20, w20, w21",
"eor w20, w27, w26",
"ubfx w20, w20, #4, #1",
"uxtb w21, w4",
"uxth w22, w4",
@@ -269,75 +249,70 @@
"cset x21, hi",
"orr x20, x20, x21",
"msr nzcv, x23",
"cbnz x20, #+0x20",
"cbnz x20, #+0x1c",
"mov w20, #0xff0f",
"and x20, x22, x20",
"bfxil w4, w20, #0, #16",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"msr nzcv, x20",
"b #+0x28",
"mov w27, #0x0",
"msr nzcv, x27",
"b #+0x24",
"sub x20, x22, #0x6 (6)",
"sub x20, x20, #0x100 (256)",
"mov w21, #0xff0f",
"and x20, x20, x21",
"bfxil w4, w20, #0, #16",
"mov w20, #0x20000000",
"mov w21, #0x10",
"strb w21, [x28, #708]",
"mov w27, #0x10",
"msr nzcv, x20"
]
},
"inc ax": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0x40",
"ExpectedArm64ASM": [
"uxth w20, w4",
"add w21, w20, #0x1 (1)",
"bfxil w4, w21, #0, #16",
"strb w20, [x28, #708]",
"strb w21, [x28, #706]",
"cset w22, hs",
"cmn wzr, w21, lsl #16",
"mrs x23, nzcv",
"bic w20, w21, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"uxth w27, w4",
"add w26, w27, #0x1 (1)",
"bfxil w4, w26, #0, #16",
"cset w20, hs",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"bic w22, w26, w27",
"ubfx x22, x22, #15, #1",
"orr w21, w21, w22, lsl #28",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
]
},
"inc eax": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Comment": "0x40",
"ExpectedArm64ASM": [
"mov w20, w4",
"add w4, w20, #0x1 (1)",
"strb w20, [x28, #708]",
"strb w4, [x28, #706]",
"cset w21, hs",
"cmn w20, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w27, w4",
"add w4, w27, #0x1 (1)",
"mov w26, w4",
"cset w20, hs",
"cmn w27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"dec ax": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0x48",
"ExpectedArm64ASM": [
"uxth w20, w4",
"sub w21, w20, #0x1 (1)",
"bfxil w4, w21, #0, #16",
"strb w20, [x28, #708]",
"strb w21, [x28, #706]",
"cset w22, hs",
"cmn wzr, w21, lsl #16",
"mrs x23, nzcv",
"bic w20, w20, w21",
"ubfx x20, x20, #15, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"uxth w27, w4",
"sub w26, w27, #0x1 (1)",
"bfxil w4, w26, #0, #16",
"cset w20, hs",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"bic w22, w27, w26",
"ubfx x22, x22, #15, #1",
"orr w21, w21, w22, lsl #28",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
]
},
@@ -356,17 +331,18 @@
]
},
"dec eax": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 10,
"Comment": "0x48",
"ExpectedArm64ASM": [
"mov w20, w4",
"sub w4, w20, #0x1 (1)",
"strb w20, [x28, #708]",
"strb w4, [x28, #706]",
"cset w21, hs",
"cmp w20, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"mov w27, w4",
"sub w4, w27, #0x1 (1)",
"mov w26, w4",
"cset w20, hs",
"cmp w27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
@@ -443,7 +419,7 @@
]
},
"aam": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "0xd4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
@@ -454,13 +430,12 @@
"lsl x21, x22, #8",
"add x20, x21, x20",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"cmn wzr, w20, lsl #24",
"strb w20, [x28, #706]"
"uxtb w26, w4",
"cmn wzr, w26, lsl #24"
]
},
"aad": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": "0xd5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
@@ -471,13 +446,12 @@
"add x20, x20, x21",
"and x20, x20, #0xff",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"cmn wzr, w20, lsl #24",
"strb w20, [x28, #706]"
"uxtb w26, w4",
"cmn wzr, w26, lsl #24"
]
},
"db 0xd4, 0x40": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 10,
"Comment": [
"aam with a different immediate byte base",
"0xd4"
@@ -491,13 +465,12 @@
"lsl x21, x22, #8",
"add x20, x21, x20",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"cmn wzr, w20, lsl #24",
"strb w20, [x28, #706]"
"uxtb w26, w4",
"cmn wzr, w26, lsl #24"
]
},
"db 0xd5, 0x40": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 9,
"Comment": [
"aad with a different immediate byte base",
"0xd5"
@@ -510,9 +483,8 @@
"add x20, x20, x21",
"and x20, x20, #0xff",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"cmn wzr, w20, lsl #24",
"strb w20, [x28, #706]"
"uxtb w26, w4",
"cmn wzr, w26, lsl #24"
]
},
"salc": {
unittests/InstructionCountCI/RPRES/DDD.json
+8 -8
View File
@@ -16,9 +16,9 @@
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"frecpe v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrsqrtv mm0, mm1": {
@@ -27,9 +27,9 @@
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"frsqrte v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrcp mm0, mm1": {
@@ -38,10 +38,10 @@
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"frecpe s2, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pfrsqrt mm0, mm1": {
@@ -50,10 +50,10 @@
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d2, [x28, #784]",
"frsqrte s2, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
}
}
unittests/InstructionCountCI/Secondary.json
+414 -460
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/SecondaryGroup.json
+99 -111
View File
@@ -825,7 +825,7 @@
"mov w24, w2",
"mov w25, w3",
"mov w20, w24",
"mov w26, w25",
"mov w30, w25",
"cmp x24, x22",
"ccmp x25, x23, #nzcv, eq",
"cset x22, eq",
@@ -833,7 +833,7 @@
"msr nzcv, x21",
"cbnz x22, #+0xc",
"mov x4, x20",
"mov x6, x26"
"mov x6, x30"
]
},
"cmpxchg16b [rbp]": {
@@ -852,7 +852,7 @@
"mov x24, x2",
"mov x25, x3",
"mov x20, x24",
"mov x26, x25",
"mov x30, x25",
"cmp x24, x22",
"ccmp x25, x23, #nzcv, eq",
"cset x22, eq",
@@ -860,11 +860,11 @@
"msr nzcv, x21",
"cbnz x22, #+0xc",
"mov x4, x20",
"mov x6, x26"
"mov x6, x30"
]
},
"rdrand ax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
@@ -872,16 +872,14 @@
"mov x22, x20",
"mov x20, x21",
"bfxil x4, x22, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdrand eax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
@@ -889,32 +887,28 @@
"mov x22, x20",
"mov x20, x21",
"mov w4, w22",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdrand rax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP9 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"mrs x20, rndr",
"cset x21, ne",
"mov x4, x20",
"mov x20, x21",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed ax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
@@ -922,16 +916,14 @@
"mov x22, x20",
"mov x20, x21",
"bfxil x4, x22, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed eax": {
"ExpectedInstructionCount": 11,
"ExpectedInstructionCount": 9,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
@@ -939,26 +931,22 @@
"mov x22, x20",
"mov x20, x21",
"mov w4, w22",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"rdseed rax": {
"ExpectedInstructionCount": 10,
"ExpectedInstructionCount": 8,
"Comment": "GROUP9 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x20, rndrrs",
"cset x21, ne",
"mov x4, x20",
"mov x20, x21",
"mov w21, #0x0",
"mov w22, #0x1",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"mov w27, #0x0",
"mov w26, #0x1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
@@ -974,9 +962,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlw mm0, 16": {
@@ -984,9 +972,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlw xmm0, 0": {
@@ -1022,9 +1010,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psraw mm0, 16": {
@@ -1032,9 +1020,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psraw xmm0, 0": {
@@ -1070,9 +1058,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.8h, v2.8h, #15",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllw mm0, 16": {
@@ -1080,9 +1068,9 @@
"Type": "MMX",
"Comment": "GROUP12 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllw xmm0, 0": {
@@ -1118,9 +1106,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrld mm0, 32": {
@@ -1128,9 +1116,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrld xmm0, 0": {
@@ -1166,9 +1154,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrad mm0, 32": {
@@ -1176,9 +1164,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sshr v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrad xmm0, 0": {
@@ -1214,9 +1202,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.4s, v2.4s, #31",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pslld mm0, 32": {
@@ -1224,9 +1212,9 @@
"Type": "MMX",
"Comment": "GROUP13 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pslld xmm0, 0": {
@@ -1262,9 +1250,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"ushr v2.2d, v2.2d, #63",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlq mm0, 64": {
@@ -1272,9 +1260,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlq xmm0, 0": {
@@ -1333,9 +1321,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"shl v2.2d, v2.2d, #63",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllq mm0, 64": {
@@ -1343,9 +1331,9 @@
"Type": "MMX",
"Comment": "GROUP14 0x0F 0xC7 /6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"movi v2.2d, #0x0",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllq xmm0, 0": {
@@ -1374,7 +1362,7 @@
"ExpectedInstructionCount": 58,
"Comment": "GROUP15 0x0F 0xAE /0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1008]",
"ldrh w20, [x28, #1024]",
"strh w20, [x4]",
"mov w20, #0x0",
"ldrb w21, [x28, #747]",
@@ -1388,23 +1376,23 @@
"orr x20, x20, x23, lsl #10",
"orr x20, x20, x24, lsl #14",
"strh w20, [x4, #2]",
"ldrb w20, [x28, #1010]",
"ldrb w20, [x28, #1026]",
"strb w20, [x4, #4]",
"ldr q2, [x28, #752]",
"str q2, [x4, #32]",
"ldr q2, [x28, #768]",
"str q2, [x4, #48]",
"str q2, [x4, #32]",
"ldr q2, [x28, #784]",
"str q2, [x4, #64]",
"str q2, [x4, #48]",
"ldr q2, [x28, #800]",
"str q2, [x4, #80]",
"str q2, [x4, #64]",
"ldr q2, [x28, #816]",
"str q2, [x4, #96]",
"str q2, [x4, #80]",
"ldr q2, [x28, #832]",
"str q2, [x4, #112]",
"str q2, [x4, #96]",
"ldr q2, [x28, #848]",
"str q2, [x4, #128]",
"str q2, [x4, #112]",
"ldr q2, [x28, #864]",
"str q2, [x4, #128]",
"ldr q2, [x28, #880]",
"str q2, [x4, #144]",
"str q16, [x4, #160]",
"str q17, [x4, #176]",
@@ -1453,7 +1441,7 @@
"Comment": "GROUP15 0x0F 0xAE /1",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1008]",
"strh w20, [x28, #1024]",
"ldrh w20, [x4, #2]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #747]",
@@ -1466,23 +1454,23 @@
"strb w23, [x28, #746]",
"strb w20, [x28, #750]",
"ldrb w20, [x4, #4]",
"strb w20, [x28, #1010]",
"strb w20, [x28, #1026]",
"ldr q2, [x4, #32]",
"str q2, [x28, #752]",
"ldr q2, [x4, #48]",
"str q2, [x28, #768]",
"ldr q2, [x4, #64]",
"ldr q2, [x4, #48]",
"str q2, [x28, #784]",
"ldr q2, [x4, #80]",
"ldr q2, [x4, #64]",
"str q2, [x28, #800]",
"ldr q2, [x4, #96]",
"ldr q2, [x4, #80]",
"str q2, [x28, #816]",
"ldr q2, [x4, #112]",
"ldr q2, [x4, #96]",
"str q2, [x28, #832]",
"ldr q2, [x4, #128]",
"ldr q2, [x4, #112]",
"str q2, [x28, #848]",
"ldr q2, [x4, #144]",
"ldr q2, [x4, #128]",
"str q2, [x28, #864]",
"ldr q2, [x4, #144]",
"str q2, [x28, #880]",
"ldr q16, [x4, #160]",
"ldr q17, [x4, #176]",
"ldr q18, [x4, #192]",
@@ -1591,7 +1579,7 @@
"ubfx x22, x20, #0, #1",
"cbnz x22, #+0x8",
"b #+0x84",
"ldrh w22, [x28, #1008]",
"ldrh w22, [x28, #1024]",
"strh w22, [x21]",
"mov w22, #0x0",
"ldrb w23, [x28, #747]",
@@ -1599,29 +1587,29 @@
"ldrb w23, [x28, #744]",
"ldrb w24, [x28, #745]",
"ldrb w25, [x28, #746]",
"ldrb w26, [x28, #750]",
"ldrb w30, [x28, #750]",
"orr x22, x22, x23, lsl #8",
"orr x22, x22, x24, lsl #9",
"orr x22, x22, x25, lsl #10",
"orr x22, x22, x26, lsl #14",
"orr x22, x22, x30, lsl #14",
"strh w22, [x21, #2]",
"ldrb w22, [x28, #1010]",
"ldrb w22, [x28, #1026]",
"strb w22, [x21, #4]",
"ldr q2, [x28, #752]",
"str q2, [x21, #32]",
"ldr q2, [x28, #768]",
"str q2, [x21, #48]",
"str q2, [x21, #32]",
"ldr q2, [x28, #784]",
"str q2, [x21, #64]",
"str q2, [x21, #48]",
"ldr q2, [x28, #800]",
"str q2, [x21, #80]",
"str q2, [x21, #64]",
"ldr q2, [x28, #816]",
"str q2, [x21, #96]",
"str q2, [x21, #80]",
"ldr q2, [x28, #832]",
"str q2, [x21, #112]",
"str q2, [x21, #96]",
"ldr q2, [x28, #848]",
"str q2, [x21, #128]",
"str q2, [x21, #112]",
"ldr q2, [x28, #864]",
"str q2, [x21, #128]",
"ldr q2, [x28, #880]",
"str q2, [x21, #144]",
"ubfx x22, x20, #1, #1",
"cbnz x22, #+0x8",
@@ -1676,7 +1664,7 @@
"cbnz x22, #+0x8",
"b #+0x84",
"ldrh w22, [x20]",
"strh w22, [x28, #1008]",
"strh w22, [x28, #1024]",
"ldrh w22, [x20, #2]",
"ubfx w23, w22, #11, #3",
"strb w23, [x28, #747]",
@@ -1689,35 +1677,34 @@
"strb w25, [x28, #746]",
"strb w22, [x28, #750]",
"ldrb w22, [x20, #4]",
"strb w22, [x28, #1010]",
"strb w22, [x28, #1026]",
"ldr q2, [x20, #32]",
"str q2, [x28, #752]",
"ldr q2, [x20, #48]",
"str q2, [x28, #768]",
"ldr q2, [x20, #64]",
"ldr q2, [x20, #48]",
"str q2, [x28, #784]",
"ldr q2, [x20, #80]",
"ldr q2, [x20, #64]",
"str q2, [x28, #800]",
"ldr q2, [x20, #96]",
"ldr q2, [x20, #80]",
"str q2, [x28, #816]",
"ldr q2, [x20, #112]",
"ldr q2, [x20, #96]",
"str q2, [x28, #832]",
"ldr q2, [x20, #128]",
"ldr q2, [x20, #112]",
"str q2, [x28, #848]",
"ldr q2, [x20, #144]",
"ldr q2, [x20, #128]",
"str q2, [x28, #864]",
"ldr q2, [x20, #144]",
"str q2, [x28, #880]",
"b #+0x4c",
"mov w22, #0x0",
"mov w23, #0x37f",
"strh w23, [x28, #1008]",
"strh w23, [x28, #1024]",
"strb w22, [x28, #747]",
"strb w22, [x28, #744]",
"strb w22, [x28, #745]",
"strb w22, [x28, #746]",
"strb w22, [x28, #750]",
"strb w22, [x28, #1010]",
"strb w22, [x28, #1026]",
"movi v2.2d, #0x0",
"str q2, [x28, #752]",
"str q2, [x28, #768]",
"str q2, [x28, #784]",
"str q2, [x28, #800]",
@@ -1725,6 +1712,7 @@
"str q2, [x28, #832]",
"str q2, [x28, #848]",
"str q2, [x28, #864]",
"str q2, [x28, #880]",
"ubfx x22, x21, #1, #1",
"cbnz x22, #+0x8",
"b #+0x48",
unittests/InstructionCountCI/SecondaryModRM.json
+9 -5
View File
@@ -14,7 +14,7 @@
},
"Instructions": {
"xgetbv": {
"ExpectedInstructionCount": 50,
"ExpectedInstructionCount": 54,
"Comment": "0xF 0x01 /2 RM-0",
"ExpectedArm64ASM": [
"sub sp, sp, #0xf0 (240)",
@@ -34,13 +34,15 @@
"stp x14, x15, [x28, #88]",
"stp x16, x17, [x28, #104]",
"stp x19, x29, [x28, #120]",
"str x26, [x28, #752]",
"str x27, [x28, #760]",
"add x0, x28, #0xc0 (192)",
"st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64",
"st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64",
"st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
"st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
"ldr x0, [x28, #1096]",
"ldr x2, [x28, #1112]",
"ldr x0, [x28, #1112]",
"ldr x2, [x28, #1128]",
"mov w1, w5",
"blr x2",
"ldr w4, [x28, #728]",
@@ -58,6 +60,8 @@
"ldp x14, x15, [x28, #88]",
"ldp x16, x17, [x28, #104]",
"ldp x19, x29, [x28, #120]",
"ldr x26, [x28, #752]",
"ldr x27, [x28, #760]",
"ld1 {v2.2d, v3.2d}, [sp], #32",
"ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
@@ -81,7 +85,7 @@
"str w0, [x28, #728]",
"str x8, [x28, #40]",
"mov w0, #0x100",
"str x0, [x28, #1040]",
"str x0, [x28, #1056]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
@@ -92,7 +96,7 @@
"ldr w8, [x28, #728]",
"msr nzcv, x8",
"ldr x8, [x28, #40]",
"str xzr, [x28, #1040]",
"str xzr, [x28, #1056]",
"orr x5, x0, x1, lsl #12"
]
},
unittests/InstructionCountCI/Secondary_32Bit.json
+2 -2
View File
@@ -25,7 +25,7 @@
"strh w20, [x28, #146]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"ldr w20, [x0, #896]",
"str w20, [x28, #176]"
]
},
@@ -46,7 +46,7 @@
"strh w20, [x28, #144]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"ldr w20, [x0, #896]",
"str w20, [x28, #168]"
]
}
unittests/InstructionCountCI/Secondary_OpSize.json
+16 -20
View File
@@ -109,7 +109,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x66 0x0f 0x2a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d2, [x28, #768]",
"sxtl v2.2d, v2.2s",
"scvtf v16.2d, v2.2d"
]
@@ -127,7 +127,7 @@
"ExpectedArm64ASM": [
"fcvtn v2.2s, v16.2d",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"cvtpd2pi mm0, xmm0": {
@@ -137,11 +137,11 @@
"fcvtn v2.2s, v16.2d",
"frinti v2.2s, v2.2s",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"ucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": "0x66 0x0f 0x2e",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
@@ -157,17 +157,15 @@
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"msr nzcv, x20"
]
},
"comisd xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": "0x66 0x0f 0x2f",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
@@ -183,12 +181,10 @@
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"msr nzcv, x20"
]
},
@@ -540,7 +536,7 @@
"0x66 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1672]",
"ldr x0, [x28, #1688]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -554,7 +550,7 @@
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #1672]",
"ldr x0, [x28, #1688]",
"ldr q3, [x0, #16]",
"tbl v16.16b, {v2.16b}, v3.16b"
]
@@ -1032,7 +1028,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0x66 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #2016]",
"ldr q2, [x28, #2032]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.2d, v16.2d, v2.2d"
]
unittests/InstructionCountCI/Secondary_REP.json
+15 -21
View File
@@ -354,7 +354,7 @@
"0xf3 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1664]",
"ldr x0, [x28, #1680]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -399,7 +399,7 @@
]
},
"popcnt ax, bx": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"uxth w20, w7",
@@ -408,18 +408,16 @@
"addp v0.8b, v0.8b, v0.8b",
"umov w20, v0.b[0]",
"bfxil x4, x20, #0, #16",
"mov w21, #0x0",
"mov w22, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"strb w22, [x28, #706]",
"strb w21, [x28, #708]",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
"popcnt eax, ebx": {
"ExpectedInstructionCount": 13,
"ExpectedInstructionCount": 11,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"mov w20, w7",
@@ -427,31 +425,27 @@
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"mov w21, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x4, #0x0 (0)",
"cset x22, eq",
"strb w21, [x28, #706]",
"strb w20, [x28, #708]",
"lsl x20, x22, #30",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
"popcnt rax, rbx": {
"ExpectedInstructionCount": 12,
"ExpectedInstructionCount": 10,
"Comment": "0xf3 0x0f 0xb8",
"ExpectedArm64ASM": [
"fmov d0, x7",
"cnt v0.8b, v0.8b",
"addv b0, v0.8b",
"umov w4, v0.b[0]",
"mov w20, #0x0",
"mov w21, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x4, #0x0 (0)",
"cset x22, eq",
"strb w21, [x28, #706]",
"strb w20, [x28, #708]",
"lsl x20, x22, #30",
"cset x20, eq",
"lsl x20, x20, #30",
"msr nzcv, x20"
]
},
@@ -637,7 +631,7 @@
"ExpectedInstructionCount": 1,
"Comment": "0xf3 0x0f 0xd6",
"ExpectedArm64ASM": [
"ldr d16, [x28, #752]"
"ldr d16, [x28, #768]"
]
},
"cvtdq2pd xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_REPNE.json
+3 -3
View File
@@ -296,7 +296,7 @@
"0xf2 0x0f 0x70"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1656]",
"ldr x0, [x28, #1672]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b}, v2.16b"
]
@@ -452,7 +452,7 @@
"ExpectedInstructionCount": 3,
"Comment": "0xf2 0x0f 0xd0",
"ExpectedArm64ASM": [
"ldr q2, [x28, #1984]",
"ldr q2, [x28, #2000]",
"eor v2.16b, v17.16b, v2.16b",
"fadd v16.4s, v16.4s, v2.4s"
]
@@ -461,7 +461,7 @@
"ExpectedInstructionCount": 1,
"Comment": "0xf2 0x0f 0xd6",
"ExpectedArm64ASM": [
"str d16, [x28, #752]"
"str d16, [x28, #768]"
]
},
"cvtpd2dq xmm0, xmm1": {
unittests/InstructionCountCI/Secondary_SVE128.json
+24 -24
View File
@@ -35,80 +35,80 @@
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsr z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrld mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsr z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrlq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsr z2.d, p6/m, z2.d, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psraw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xe1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"asr z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psrad mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xe2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"asr z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsl z2.h, p6/m, z2.h, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"pslld mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsl z2.s, p6/m, z2.s, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
},
"psllq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #752]",
"ldr d3, [x28, #768]",
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"lsl z2.d, p6/m, z2.d, z3.d",
"str d2, [x28, #752]"
"str d2, [x28, #768]"
]
}
}
unittests/InstructionCountCI/VEX_map1.json
+27 -35
View File
@@ -2755,7 +2755,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1680]",
"ldr x0, [x28, #1696]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2824,7 +2824,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1680]",
"ldr x0, [x28, #1696]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -2893,7 +2893,7 @@
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1680]",
"ldr x0, [x28, #1696]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
@@ -3307,7 +3307,7 @@
]
},
"vucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": [
"Map 1 0b00 0x2e 128-bit"
],
@@ -3325,17 +3325,15 @@
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"msr nzcv, x20"
]
},
"vucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": [
"Map 1 0b01 0x2e 128-bit"
],
@@ -3353,17 +3351,15 @@
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"msr nzcv, x20"
]
},
"vcomiss xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": [
"Map 1 0b00 0x2f 128-bit"
],
@@ -3381,17 +3377,15 @@
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"msr nzcv, x20"
]
},
"vcomisd xmm0, xmm1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": [
"Map 1 0b01 0x2f 128-bit"
],
@@ -3409,12 +3403,10 @@
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w21, w21, #0x1",
"strb w21, [x28, #706]",
"mov w21, #0x0",
"mov w22, #0x90000000",
"bic x20, x20, x22",
"strb w21, [x28, #708]",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"msr nzcv, x20"
]
},
@@ -4374,7 +4366,7 @@
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2016]",
"ldr q2, [x28, #2032]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.2d, v17.2d, v2.2d"
]
@@ -4385,7 +4377,7 @@
"Map 1 0b01 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1576]",
"ldr x0, [x28, #1592]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.d, z17.d, z2.d"
@@ -4397,7 +4389,7 @@
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #1984]",
"ldr q2, [x28, #2000]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.4s, v17.4s, v2.4s"
]
@@ -4408,7 +4400,7 @@
"Map 1 0b11 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1560]",
"ldr x0, [x28, #1576]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.s, z17.s, z2.s"
unittests/InstructionCountCI/VEX_map2.json
+29 -41
View File
@@ -499,7 +499,7 @@
]
},
"vtestps xmm0, xmm1": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x0e 128-bit"
],
@@ -516,26 +516,24 @@
"addv h2, v2.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"mov w0, w24",
"mov w0, w22",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestps ymm0, ymm1": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 34,
"Comment": [
"Map 2 0b01 0x0e 256-bit"
],
@@ -560,26 +558,24 @@
"add v2.8h, v0.8h, v1.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"mov w0, w24",
"mov w0, w22",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestpd xmm0, xmm1": {
"ExpectedInstructionCount": 28,
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x0f 128-bit"
],
@@ -596,26 +592,24 @@
"addv h2, v2.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"mov w0, w24",
"mov w0, w22",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vtestpd ymm0, ymm1": {
"ExpectedInstructionCount": 36,
"ExpectedInstructionCount": 34,
"Comment": [
"Map 2 0b01 0x0f 256-bit"
],
@@ -640,21 +634,19 @@
"add v2.8h, v0.8h, v1.8h",
"umov w20, v3.h[0]",
"umov w21, v2.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mrs x24, nzcv",
"mov w27, #0x0",
"mov w26, #0x1",
"mrs x22, nzcv",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"mov w0, w24",
"mov w0, w22",
"bfi w0, w20, #30, #1",
"mov w20, w0",
"bfi w20, w21, #29, #1",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
@@ -691,7 +683,7 @@
]
},
"vptest xmm0, xmm1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": [
"Map 2 0b01 0x16 128-bit"
],
@@ -704,21 +696,19 @@
"addv h3, v3.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
"vptest ymm0, ymm1": {
"ExpectedInstructionCount": 27,
"ExpectedInstructionCount": 25,
"Comment": [
"Map 2 0b01 0x16 256-bit"
],
@@ -739,16 +729,14 @@
"add v3.8h, v0.8h, v1.8h",
"umov w20, v2.h[0]",
"umov w21, v3.h[0]",
"mov w22, #0x0",
"mov w23, #0x1",
"mov w27, #0x0",
"mov w26, #0x1",
"cmp x20, #0x0 (0)",
"cset x20, eq",
"cmp x21, #0x0 (0)",
"cset x21, eq",
"lsl x20, x20, #30",
"orr w20, w20, w21, lsl #29",
"strb w23, [x28, #706]",
"strb w22, [x28, #708]",
"msr nzcv, x20"
]
},
@@ -1649,7 +1637,7 @@
"Map 2 0b01 0x41 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #1952]",
"ldr q2, [x28, #1968]",
"zip1 v3.8h, v2.8h, v17.8h",
"zip2 v2.8h, v2.8h, v17.8h",
"umin v2.4s, v3.4s, v2.4s",
@@ -3249,7 +3237,7 @@
"mov w20, w7",
"mov w21, w5",
"bic w4, w21, w20",
"strb w4, [x28, #706]",
"mov x26, x4",
"tst w4, w4"
]
},
@@ -3260,7 +3248,7 @@
],
"ExpectedArm64ASM": [
"bic x4, x5, x7",
"strb w4, [x28, #706]",
"mov x26, x4",
"tst x4, x4"
]
},
unittests/InstructionCountCI/VEX_map3.json
+2 -2
View File
@@ -4799,7 +4799,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2064]",
"ldr q2, [x28, #2080]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
@@ -4812,7 +4812,7 @@
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2064]",
"ldr q2, [x28, #2080]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
unittests/InstructionCountCI/x87.json
+4935 -3753
View File
File diff suppressed because it is too large. Load diff
unittests/InstructionCountCI/x87_f64.json
+2092 -2004
View File
File diff suppressed because it is too large. Load diff