mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 12:00:17 +02:00
1024 lines
25 KiB
JSON
1024 lines
25 KiB
JSON
{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"FLAGM",
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"FLAGM2",
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"CRYPTO"
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]
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},
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"Instructions": {
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"pshufb mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"NP 0x0f 0x38 0x00"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #768]",
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"ldr d3, [x28, #784]",
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"movi v4.16b, #0x87",
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"and v3.16b, v3.16b, v4.16b",
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"tbl v2.8b, {v2.16b}, v3.8b",
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"str d2, [x28, #768]"
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]
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},
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"pshufb xmm0, xmm1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0x66 0x0f 0x38 0x00"
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],
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"ExpectedArm64ASM": [
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"movi v2.16b, #0x8f",
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"and v2.16b, v17.16b, v2.16b",
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"tbl v16.16b, {v16.16b}, v2.16b"
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]
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},
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"phaddw mm0, mm1": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"NP 0x0f 0x38 0x01"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #784]",
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"ldr d3, [x28, #768]",
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"addp v2.4h, v3.4h, v2.4h",
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"str d2, [x28, #768]"
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]
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},
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"phaddw xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0x66 0x0f 0x38 0x01"
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],
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"ExpectedArm64ASM": [
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"addp v16.8h, v16.8h, v17.8h"
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]
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},
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"phaddd mm0, mm1": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"NP 0x0f 0x38 0x02"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #784]",
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"ldr d3, [x28, #768]",
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"addp v2.2s, v3.2s, v2.2s",
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"str d2, [x28, #768]"
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]
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},
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"phaddd xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
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"Comment": [
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"0x66 0x0f 0x38 0x02"
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],
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"ExpectedArm64ASM": [
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"addp v16.4s, v16.4s, v17.4s"
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]
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},
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"phaddsw mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"NP 0x0f 0x38 0x03"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #768]",
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"ldr d3, [x28, #784]",
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"uzp1 v4.4h, v2.4h, v3.4h",
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"uzp2 v2.4h, v2.4h, v3.4h",
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"sqadd v2.8h, v4.8h, v2.8h",
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"str d2, [x28, #768]"
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]
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},
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"phaddsw xmm0, xmm1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0x66 0x0f 0x38 0x03"
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],
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"ExpectedArm64ASM": [
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"uzp1 v2.8h, v16.8h, v17.8h",
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"uzp2 v3.8h, v16.8h, v17.8h",
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"sqadd v16.8h, v2.8h, v3.8h"
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]
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},
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"pmaddubsw mm0, mm1": {
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"ExpectedInstructionCount": 9,
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"Comment": [
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"NP 0x0f 0x38 0x04"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #768]",
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"ldr d3, [x28, #784]",
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"uxtl v2.8h, v2.8b",
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"sxtl v3.8h, v3.8b",
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"smull v4.4s, v2.4h, v3.4h",
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"smull2 v2.4s, v2.8h, v3.8h",
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"addp v2.4s, v4.4s, v2.4s",
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"sqxtn v2.4h, v2.4s",
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"str d2, [x28, #768]"
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]
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},
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"pmaddubsw xmm0, xmm1": {
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"ExpectedInstructionCount": 9,
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"Comment": [
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"{u,s}xtl{,2} and uzp{1,2} can be more optimal",
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"Up-front zero extend and sign extend the elements in place",
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"This allows extracting even and odd elements up-front so we don't need the unzips at the end",
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"Requires implementing IR ops for BIC (vector, immediate)",
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"0x66 0x0f 0x38 0x04"
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],
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"ExpectedArm64ASM": [
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"uxtl v2.8h, v16.8b",
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"sxtl v3.8h, v17.8b",
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"mul v2.8h, v2.8h, v3.8h",
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"uxtl2 v3.8h, v16.16b",
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"sxtl2 v4.8h, v17.16b",
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"mul v3.8h, v3.8h, v4.8h",
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"uzp1 v4.8h, v2.8h, v3.8h",
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"uzp2 v2.8h, v2.8h, v3.8h",
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"sqadd v16.8h, v4.8h, v2.8h"
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]
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},
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"phsubw mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"NP 0x0f 0x38 0x05"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #768]",
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"ldr d3, [x28, #784]",
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"uzp1 v4.4h, v2.4h, v3.4h",
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"uzp2 v2.4h, v2.4h, v3.4h",
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"sub v2.8h, v4.8h, v2.8h",
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"str d2, [x28, #768]"
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]
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},
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"phsubw xmm0, xmm1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0x66 0x0f 0x38 0x05"
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],
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"ExpectedArm64ASM": [
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"uzp1 v2.8h, v16.8h, v17.8h",
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"uzp2 v3.8h, v16.8h, v17.8h",
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"sub v16.8h, v2.8h, v3.8h"
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]
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},
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"phsubd mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"NP 0x0f 0x38 0x06"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #768]",
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"ldr d3, [x28, #784]",
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"uzp1 v4.2s, v2.2s, v3.2s",
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"uzp2 v2.2s, v2.2s, v3.2s",
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"sub v2.4s, v4.4s, v2.4s",
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"str d2, [x28, #768]"
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]
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},
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"phsubd xmm0, xmm1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0x66 0x0f 0x38 0x06"
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],
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"ExpectedArm64ASM": [
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"uzp1 v2.4s, v16.4s, v17.4s",
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"uzp2 v3.4s, v16.4s, v17.4s",
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"sub v16.4s, v2.4s, v3.4s"
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]
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},
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"phsubsw mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"NP 0x0f 0x38 0x07"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #768]",
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"ldr d3, [x28, #784]",
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"uzp1 v4.4h, v2.4h, v3.4h",
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"uzp2 v2.4h, v2.4h, v3.4h",
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"sqsub v2.8h, v4.8h, v2.8h",
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"str d2, [x28, #768]"
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]
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},
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"phsubsw xmm0, xmm1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0x66 0x0f 0x38 0x07"
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],
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"ExpectedArm64ASM": [
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"uzp1 v2.8h, v16.8h, v17.8h",
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"uzp2 v3.8h, v16.8h, v17.8h",
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"sqsub v16.8h, v2.8h, v3.8h"
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]
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},
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"psignb mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"NP 0x0f 0x38 0x08"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #784]",
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"ldr d3, [x28, #768]",
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"sqshl v2.8b, v2.8b, #7",
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"srshr v2.8b, v2.8b, #7",
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"mul v2.16b, v3.16b, v2.16b",
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"str d2, [x28, #768]"
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]
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},
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"psignb xmm0, xmm1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0x66 0x0f 0x38 0x08"
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],
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"ExpectedArm64ASM": [
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"sqshl v2.16b, v17.16b, #7",
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"srshr v2.16b, v2.16b, #7",
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"mul v16.16b, v16.16b, v2.16b"
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]
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},
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"psignw mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"NP 0x0f 0x38 0x09"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #784]",
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"ldr d3, [x28, #768]",
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"sqshl v2.4h, v2.4h, #15",
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"srshr v2.4h, v2.4h, #15",
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"mul v2.8h, v3.8h, v2.8h",
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"str d2, [x28, #768]"
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]
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},
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"psignw xmm0, xmm1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0x66 0x0f 0x38 0x09"
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],
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"ExpectedArm64ASM": [
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"sqshl v2.8h, v17.8h, #15",
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"srshr v2.8h, v2.8h, #15",
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"mul v16.8h, v16.8h, v2.8h"
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]
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},
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"psignd mm0, mm1": {
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"ExpectedInstructionCount": 6,
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"Comment": [
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"NP 0x0f 0x38 0x0a"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #784]",
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"ldr d3, [x28, #768]",
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"sqshl v2.2s, v2.2s, #31",
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"srshr v2.2s, v2.2s, #31",
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"mul v2.4s, v3.4s, v2.4s",
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"str d2, [x28, #768]"
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]
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},
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"psignd xmm0, xmm1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
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"0x66 0x0f 0x38 0x0a"
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],
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"ExpectedArm64ASM": [
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"sqshl v2.4s, v17.4s, #31",
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"srshr v2.4s, v2.4s, #31",
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"mul v16.4s, v16.4s, v2.4s"
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]
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},
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"pmulhrsw mm0, mm1": {
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"ExpectedInstructionCount": 8,
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"Comment": [
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"Might be able to use sqdmulh",
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"NP 0x0f 0x38 0x0b"
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],
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"ExpectedArm64ASM": [
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"ldr d2, [x28, #768]",
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"ldr d3, [x28, #784]",
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"smull v2.4s, v2.4h, v3.4h",
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"sshr v2.4s, v2.4s, #14",
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"movi v3.4s, #0x1, lsl #0",
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"add v2.4s, v2.4s, v3.4s",
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"shrn v2.4h, v2.4s, #1",
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"str d2, [x28, #768]"
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]
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},
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"pmulhrsw xmm0, xmm1": {
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"ExpectedInstructionCount": 11,
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"Comment": [
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"Might be able to use sqdmulh",
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"0x66 0x0f 0x38 0x0b"
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],
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"ExpectedArm64ASM": [
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"smull v2.4s, v16.4h, v17.4h",
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"smull2 v3.4s, v16.8h, v17.8h",
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"sshr v2.4s, v2.4s, #14",
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"sshr v3.4s, v3.4s, #14",
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"movi v4.4s, #0x1, lsl #0",
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"add v2.4s, v2.4s, v4.4s",
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"add v3.4s, v3.4s, v4.4s",
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"shrn v2.4h, v2.4s, #1",
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"mov v0.16b, v2.16b",
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"shrn2 v0.8h, v3.4s, #1",
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"mov v16.16b, v0.16b"
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]
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},
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"pblendvb xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0x66 0x0f 0x38 0x10"
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],
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"ExpectedArm64ASM": [
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"sshr v2.16b, v16.16b, #7",
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"bit v16.16b, v17.16b, v2.16b"
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]
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},
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"blendvps xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0x66 0x0f 0x38 0x14"
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],
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"ExpectedArm64ASM": [
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"sshr v2.4s, v16.4s, #31",
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"bit v16.16b, v17.16b, v2.16b"
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]
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},
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"blendvpd xmm0, xmm1": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0x66 0x0f 0x38 0x15"
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],
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"ExpectedArm64ASM": [
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"sshr v2.2d, v16.2d, #63",
|
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"bit v16.16b, v17.16b, v2.16b"
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]
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},
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"pblendvb xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
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"0x66 0x0f 0x38 0x10"
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],
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"ExpectedArm64ASM": [
|
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"sshr v2.16b, v16.16b, #7",
|
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"bit v17.16b, v18.16b, v2.16b"
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]
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},
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"blendvps xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
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"Comment": [
|
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"0x66 0x0f 0x38 0x14"
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],
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"ExpectedArm64ASM": [
|
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"sshr v2.4s, v16.4s, #31",
|
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"bit v17.16b, v18.16b, v2.16b"
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]
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},
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"blendvpd xmm1, xmm2": {
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"ExpectedInstructionCount": 2,
|
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"Comment": [
|
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"0x66 0x0f 0x38 0x15"
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|
],
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"ExpectedArm64ASM": [
|
|
"sshr v2.2d, v16.2d, #63",
|
|
"bit v17.16b, v18.16b, v2.16b"
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]
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},
|
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"ptest xmm0, xmm1": {
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"ExpectedInstructionCount": 17,
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"Comment": [
|
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"0x66 0x0f 0x38 0x17"
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],
|
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"ExpectedArm64ASM": [
|
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"and v2.16b, v16.16b, v17.16b",
|
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"bic v3.16b, v17.16b, v16.16b",
|
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"cnt v2.16b, v2.16b",
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"cnt v3.16b, v3.16b",
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"addv h2, v2.8h",
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"addv h3, v3.8h",
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"umov w20, v2.h[0]",
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"umov w21, v3.h[0]",
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"mov w27, #0x0",
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"mov w26, #0x1",
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"cmp x20, #0x0 (0)",
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"cset x20, eq",
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"cmp x21, #0x0 (0)",
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"cset x21, eq",
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"lsl x20, x20, #30",
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"orr w20, w20, w21, lsl #29",
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"msr nzcv, x20"
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]
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},
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"pabsb mm0, mm1": {
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"ExpectedInstructionCount": 3,
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"Comment": [
|
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"NP 0x0f 0x38 0x1c"
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],
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"ExpectedArm64ASM": [
|
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"ldr d2, [x28, #784]",
|
|
"abs v2.16b, v2.16b",
|
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"str d2, [x28, #768]"
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]
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},
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"pabsb xmm0, xmm1": {
|
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"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
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"0x66 0x0f 0x38 0x1c"
|
|
],
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"ExpectedArm64ASM": [
|
|
"abs v16.16b, v17.16b"
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]
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},
|
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"pabsw mm0, mm1": {
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"ExpectedInstructionCount": 3,
|
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"Comment": [
|
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"NP 0x0f 0x38 0x1d"
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|
],
|
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"ExpectedArm64ASM": [
|
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"ldr d2, [x28, #784]",
|
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"abs v2.8h, v2.8h",
|
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"str d2, [x28, #768]"
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]
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},
|
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"pabsw xmm0, xmm1": {
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"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
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"0x66 0x0f 0x38 0x1d"
|
|
],
|
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"ExpectedArm64ASM": [
|
|
"abs v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pabsd mm0, mm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"NP 0x0f 0x38 0x1e"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #784]",
|
|
"abs v2.4s, v2.4s",
|
|
"str d2, [x28, #768]"
|
|
]
|
|
},
|
|
"pabsd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x1e"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"abs v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"pmovzxbw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x30"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxtl v16.8h, v17.8b"
|
|
]
|
|
},
|
|
"pmovzxbd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x31"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxtl v2.8h, v17.8b",
|
|
"uxtl v16.4s, v2.4h"
|
|
]
|
|
},
|
|
"pmovzxbq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x32"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxtl v2.8h, v17.8b",
|
|
"uxtl v2.4s, v2.4h",
|
|
"uxtl v16.2d, v2.2s"
|
|
]
|
|
},
|
|
"pmovzxwd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x33"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxtl v16.4s, v17.4h"
|
|
]
|
|
},
|
|
"pmovzxwq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x34"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxtl v2.4s, v17.4h",
|
|
"uxtl v16.2d, v2.2s"
|
|
]
|
|
},
|
|
"pmovzxdq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x35"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"uxtl v16.2d, v17.2s"
|
|
]
|
|
},
|
|
"pcmpgtq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x37"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cmgt v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"pminsb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x38"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"smin v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"pminsd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x39"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"smin v16.4s, v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"pminuw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x3a"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"umin v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pminud xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x3b"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"umin v16.4s, v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"pmaxsb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x3c"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"smax v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"pmaxsd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x3d"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"smax v16.4s, v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"pmaxuw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x3e"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"umax v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pmaxud xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x3f"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"umax v16.4s, v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"pmulld xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x40"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mul v16.4s, v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"phminposuw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0x41"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #1968]",
|
|
"zip1 v3.8h, v2.8h, v17.8h",
|
|
"zip2 v2.8h, v2.8h, v17.8h",
|
|
"umin v2.4s, v3.4s, v2.4s",
|
|
"uminv s2, v2.4s",
|
|
"rev32 v16.8h, v2.8h"
|
|
]
|
|
},
|
|
"sha1nexte xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0xc8"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"shl v2.4s, v16.4s, #30",
|
|
"usra v2.4s, v16.4s, #2",
|
|
"add v2.4s, v17.4s, v2.4s",
|
|
"mov v16.16b, v17.16b",
|
|
"mov v16.s[3], v2.s[3]"
|
|
]
|
|
},
|
|
"sha1msg1 xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0xc9"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ext v2.16b, v17.16b, v16.16b, #8",
|
|
"eor v16.16b, v16.16b, v2.16b"
|
|
]
|
|
},
|
|
"sha1msg2 xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0xca"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"movi v2.2d, #0x0",
|
|
"ext v2.16b, v2.16b, v17.16b, #12",
|
|
"eor v2.16b, v16.16b, v2.16b",
|
|
"shl v3.4s, v2.4s, #1",
|
|
"mov v0.16b, v3.16b",
|
|
"usra v0.4s, v2.4s, #31",
|
|
"mov v2.16b, v0.16b",
|
|
"dup v3.4s, v2.s[3]",
|
|
"eor v3.16b, v16.16b, v3.16b",
|
|
"shl v4.4s, v3.4s, #1",
|
|
"mov v0.16b, v4.16b",
|
|
"usra v0.4s, v3.4s, #31",
|
|
"mov v3.16b, v0.16b",
|
|
"mov v16.16b, v2.16b",
|
|
"mov v16.s[0], v3.s[0]"
|
|
]
|
|
},
|
|
"sha256rnds2 xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 120,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0xcb"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sub sp, sp, #0x200 (512)",
|
|
"mov w20, v17.s[3]",
|
|
"str w20, [sp, #96]",
|
|
"mov w20, v17.s[2]",
|
|
"str w20, [sp, #64]",
|
|
"mov w20, v16.s[3]",
|
|
"mov w21, v16.s[2]",
|
|
"str w21, [sp]",
|
|
"mov w21, v17.s[1]",
|
|
"str w21, [sp, #32]",
|
|
"mov w21, v17.s[0]",
|
|
"mov w22, v16.s[1]",
|
|
"mov w23, v16.s[0]",
|
|
"mov w24, v16.s[0]",
|
|
"mov w25, v16.s[1]",
|
|
"str w25, [sp, #128]",
|
|
"ldr w25, [sp, #32]",
|
|
"and w30, w25, w21",
|
|
"str w21, [sp, #160]",
|
|
"bic w21, w22, w25",
|
|
"str w22, [sp, #192]",
|
|
"eor w21, w30, w21",
|
|
"ror w22, w25, #6",
|
|
"ror w30, w25, #11",
|
|
"eor w22, w22, w30",
|
|
"ror w30, w25, #25",
|
|
"eor w22, w22, w30",
|
|
"add w21, w21, w22",
|
|
"add w21, w21, w24",
|
|
"str w24, [sp, #256]",
|
|
"add w21, w21, w23",
|
|
"str w23, [sp, #224]",
|
|
"ldr w22, [sp, #64]",
|
|
"ldr w23, [sp, #96]",
|
|
"and w24, w23, w22",
|
|
"and w30, w23, w20",
|
|
"eor w24, w24, w30",
|
|
"and w30, w22, w20",
|
|
"str w22, [sp, #320]",
|
|
"str w20, [sp, #288]",
|
|
"eor w20, w24, w30",
|
|
"add w20, w21, w20",
|
|
"ror w21, w23, #2",
|
|
"ror w22, w23, #13",
|
|
"eor w21, w21, w22",
|
|
"ror w22, w23, #22",
|
|
"eor w21, w21, w22",
|
|
"add w20, w20, w21",
|
|
"str w20, [sp, #352]",
|
|
"ldr w20, [sp, #160]",
|
|
"and w21, w25, w20",
|
|
"ldr w22, [sp, #192]",
|
|
"bic w24, w22, w25",
|
|
"eor w21, w21, w24",
|
|
"ror w24, w25, #6",
|
|
"ror w30, w25, #11",
|
|
"eor w24, w24, w30",
|
|
"ror w30, w25, #25",
|
|
"eor w24, w24, w30",
|
|
"add w21, w21, w24",
|
|
"ldr w24, [sp, #256]",
|
|
"add w21, w21, w24",
|
|
"ldr w24, [sp, #224]",
|
|
"add w21, w21, w24",
|
|
"ldr w24, [sp]",
|
|
"add w21, w21, w24",
|
|
"and w24, w21, w25",
|
|
"bic w30, w20, w21",
|
|
"str w20, [sp, #384]",
|
|
"eor w20, w24, w30",
|
|
"ror w24, w21, #6",
|
|
"ror w30, w21, #11",
|
|
"eor w24, w24, w30",
|
|
"ror w30, w21, #25",
|
|
"str w21, [sp, #480]",
|
|
"eor w21, w24, w30",
|
|
"add w20, w20, w21",
|
|
"ldr w21, [sp, #128]",
|
|
"add w20, w20, w21",
|
|
"str w21, [sp, #448]",
|
|
"add w20, w20, w22",
|
|
"str w22, [sp, #416]",
|
|
"ldr w21, [sp, #352]",
|
|
"and w22, w21, w23",
|
|
"ldr w24, [sp, #320]",
|
|
"and w30, w21, w24",
|
|
"eor w22, w22, w30",
|
|
"and w23, w23, w24",
|
|
"eor w22, w22, w23",
|
|
"add w20, w20, w22",
|
|
"ror w22, w21, #2",
|
|
"ror w23, w21, #13",
|
|
"eor w22, w22, w23",
|
|
"ror w23, w21, #22",
|
|
"eor w22, w22, w23",
|
|
"add w20, w20, w22",
|
|
"ldr w22, [sp, #480]",
|
|
"and w23, w22, w25",
|
|
"ldr w24, [sp, #384]",
|
|
"bic w24, w24, w22",
|
|
"eor w23, w23, w24",
|
|
"ror w24, w22, #6",
|
|
"ror w25, w22, #11",
|
|
"eor w24, w24, w25",
|
|
"ror w25, w22, #25",
|
|
"eor w24, w24, w25",
|
|
"add w23, w23, w24",
|
|
"ldr w24, [sp, #448]",
|
|
"add w23, w23, w24",
|
|
"ldr w24, [sp, #416]",
|
|
"add w23, w23, w24",
|
|
"ldr w24, [sp, #288]",
|
|
"add w23, w23, w24",
|
|
"mov v2.16b, v16.16b",
|
|
"mov v2.s[3], w20",
|
|
"mov v2.s[2], w21",
|
|
"mov v2.s[1], w23",
|
|
"mov v16.16b, v2.16b",
|
|
"mov v16.s[0], w22",
|
|
"add sp, sp, #0x200 (512)"
|
|
]
|
|
},
|
|
"sha256msg1 xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 35,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0xcc"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, v17.s[0]",
|
|
"mov w21, v16.s[3]",
|
|
"mov w22, v16.s[2]",
|
|
"mov w23, v16.s[1]",
|
|
"mov w24, v16.s[0]",
|
|
"ror w25, w20, #7",
|
|
"ror w30, w20, #18",
|
|
"eor w25, w25, w30",
|
|
"lsr w20, w20, #3",
|
|
"eor w20, w25, w20",
|
|
"add w20, w21, w20",
|
|
"ror w25, w21, #7",
|
|
"ror w30, w21, #18",
|
|
"eor w25, w25, w30",
|
|
"lsr w21, w21, #3",
|
|
"eor w21, w25, w21",
|
|
"add w21, w22, w21",
|
|
"ror w25, w22, #7",
|
|
"ror w30, w22, #18",
|
|
"eor w25, w25, w30",
|
|
"lsr w22, w22, #3",
|
|
"eor w22, w25, w22",
|
|
"add w22, w23, w22",
|
|
"ror w25, w23, #7",
|
|
"ror w30, w23, #18",
|
|
"eor w25, w25, w30",
|
|
"lsr w23, w23, #3",
|
|
"eor w23, w25, w23",
|
|
"add w23, w24, w23",
|
|
"mov v2.16b, v16.16b",
|
|
"mov v2.s[3], w20",
|
|
"mov v2.s[2], w21",
|
|
"mov v2.s[1], w22",
|
|
"mov v16.16b, v2.16b",
|
|
"mov v16.s[0], w23"
|
|
]
|
|
},
|
|
"sha256msg2 xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 36,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0xcd"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, v17.s[2]",
|
|
"mov w21, v17.s[3]",
|
|
"mov w22, v16.s[0]",
|
|
"ror w23, w20, #17",
|
|
"ror w24, w20, #19",
|
|
"eor w23, w23, w24",
|
|
"lsr w20, w20, #10",
|
|
"eor w20, w23, w20",
|
|
"add w20, w22, w20",
|
|
"mov w22, v16.s[1]",
|
|
"ror w23, w21, #17",
|
|
"ror w24, w21, #19",
|
|
"eor w23, w23, w24",
|
|
"lsr w21, w21, #10",
|
|
"eor w21, w23, w21",
|
|
"add w21, w22, w21",
|
|
"mov w22, v16.s[2]",
|
|
"ror w23, w20, #17",
|
|
"ror w24, w20, #19",
|
|
"eor w23, w23, w24",
|
|
"lsr w24, w20, #10",
|
|
"eor w23, w23, w24",
|
|
"add w22, w22, w23",
|
|
"mov w23, v16.s[3]",
|
|
"ror w24, w21, #17",
|
|
"ror w25, w21, #19",
|
|
"eor w24, w24, w25",
|
|
"lsr w25, w21, #10",
|
|
"eor w24, w24, w25",
|
|
"add w23, w23, w24",
|
|
"mov v2.16b, v16.16b",
|
|
"mov v2.s[3], w23",
|
|
"mov v2.s[2], w22",
|
|
"mov v2.s[1], w21",
|
|
"mov v16.16b, v2.16b",
|
|
"mov v16.s[0], w20"
|
|
]
|
|
},
|
|
"movbe ax, word [rbx]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0xf0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrh w20, [x7]",
|
|
"rev w20, w20",
|
|
"bfxil x4, x20, #16, #16"
|
|
]
|
|
},
|
|
"movbe eax, dword [rbx]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0xf0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr w20, [x7]",
|
|
"rev w4, w20"
|
|
]
|
|
},
|
|
"movbe rax, qword [rbx]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"REX.W 0x66 0x0f 0x38 0xf0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x20, [x7]",
|
|
"rev x4, x20"
|
|
]
|
|
},
|
|
"adcx eax, ebx": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0x66 0x0f 0x38 0xf6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"mov w21, w7",
|
|
"mov w22, w4",
|
|
"add w23, w21, w20",
|
|
"add w4, w22, w23",
|
|
"mrs x22, nzcv",
|
|
"cmp w4, w21",
|
|
"cset x23, lo",
|
|
"cmp w4, w21",
|
|
"cset x21, ls",
|
|
"cmp x20, #0x1 (1)",
|
|
"csel x20, x21, x23, eq",
|
|
"mov w0, w22",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"adcx rax, rbx": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0x66 REX.W 0x0f 0x38 0xf6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, hs",
|
|
"add x21, x7, x20",
|
|
"add x4, x4, x21",
|
|
"mrs x21, nzcv",
|
|
"cmp x4, x7",
|
|
"cset x22, lo",
|
|
"cmp x4, x7",
|
|
"cset x23, ls",
|
|
"cmp x20, #0x1 (1)",
|
|
"csel x20, x23, x22, eq",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"adox eax, ebx": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Comment": [
|
|
"0xf3 0x0f 0x38 0xf6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, vs",
|
|
"mov w21, w7",
|
|
"mov w22, w4",
|
|
"add w23, w21, w20",
|
|
"add w4, w22, w23",
|
|
"mrs x22, nzcv",
|
|
"cmp w4, w21",
|
|
"cset x23, lo",
|
|
"cmp w4, w21",
|
|
"cset x21, ls",
|
|
"cmp x20, #0x1 (1)",
|
|
"csel x20, x21, x23, eq",
|
|
"mov w0, w22",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
},
|
|
"adox rax, rbx": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Comment": [
|
|
"0xf3 REX.W 0x0f 0x38 0xf6"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cset w20, vs",
|
|
"add x21, x7, x20",
|
|
"add x4, x4, x21",
|
|
"mrs x21, nzcv",
|
|
"cmp x4, x7",
|
|
"cset x22, lo",
|
|
"cmp x4, x7",
|
|
"cset x23, ls",
|
|
"cmp x20, #0x1 (1)",
|
|
"csel x20, x23, x22, eq",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #28, #1",
|
|
"mov w20, w0",
|
|
"msr nzcv, x20"
|
|
]
|
|
}
|
|
}
|
|
}
|