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FEX-Emu--FEX/unittests/InstructionCountCI/Secondary.json
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Alyssa Rosenzweig cea551c2ac InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-17 17:37:24 -04:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"RPRES",
"AFP",
"FLAGM",
"FLAGM2"
]
},
"Comment": [
"MMX instructions are defined as optimal without SRA being used for these instructions.",
"Could remove a bunch of instructions if those are under SRA",
"Vector shifts by vector elements can be optimized with SVE wide element shifts",
"Vector multiply returning high can be optimized with SVE"
],
"Instructions": {
"femms": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x0b",
"ExpectedArm64ASM": [
"mov w20, #0x0",
"strb w20, [x28, #1026]"
]
},
"movups xmm0, xmm0": {
"ExpectedInstructionCount": 0,
"Comment": "0x0f 0x10",
"ExpectedArm64ASM": []
},
"movups xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x10",
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"movups xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x10",
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
},
"movups [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x11",
"ExpectedArm64ASM": [
"str q16, [x4]"
]
},
"movlps xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x12",
"ExpectedArm64ASM": [
"ld1 {v16.d}[0], [x4]"
]
},
"movlps [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x13",
"ExpectedArm64ASM": [
"str d16, [x4]"
]
},
"movhlps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x12",
"ExpectedArm64ASM": [
"mov v16.d[0], v17.d[1]"
]
},
"unpcklps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x14",
"ExpectedArm64ASM": [
"zip1 v16.4s, v16.4s, v17.4s"
]
},
"unpckhps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x15",
"ExpectedArm64ASM": [
"zip2 v16.4s, v16.4s, v17.4s"
]
},
"movhps xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x16",
"ExpectedArm64ASM": [
"ld1 {v16.d}[1], [x4]"
]
},
"movlhps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x16",
"ExpectedArm64ASM": [
"mov v16.d[1], v17.d[0]"
]
},
"movhps [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x17",
"ExpectedArm64ASM": [
"st1 {v16.d}[1], [x4]"
]
},
"nop": {
"ExpectedInstructionCount": 0,
"Comment": "0x0f 0x19",
"ExpectedArm64ASM": []
},
"movaps xmm0, xmm0": {
"ExpectedInstructionCount": 0,
"Comment": "0x0f 0x28",
"ExpectedArm64ASM": []
},
"movaps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x28",
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"movaps xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x28",
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
},
"movaps [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x29",
"ExpectedArm64ASM": [
"str q16, [x4]"
]
},
"cvtpi2ps xmm0, [rax]": {
"ExpectedInstructionCount": 3,
"Comment": [
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"scvtf v0.2s, v2.2s",
"mov v16.d[0], v0.d[0]"
]
},
"cvtpi2ps xmm0, mm0": {
"ExpectedInstructionCount": 3,
"Comment": [
"0x0f 0x2a"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"scvtf v0.2s, v2.2s",
"mov v16.d[0], v0.d[0]"
]
},
"movntps [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x2b",
"ExpectedArm64ASM": [
"str q16, [x4]"
]
},
"cvttps2pi mm0, [rax]": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x2c",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #768]"
]
},
"cvttps2pi mm0, xmm0": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x2c",
"ExpectedArm64ASM": [
"fcvtzs v2.2s, v16.2s",
"str d2, [x28, #768]"
]
},
"cvtps2pi mm0, [rax]": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x2d",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"frinti v2.2s, v2.2s",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #768]"
]
},
"cvtps2pi mm0, xmm0": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x2d",
"ExpectedArm64ASM": [
"frinti v2.2s, v16.2s",
"fcvtzs v2.2s, v2.2s",
"str d2, [x28, #768]"
]
},
"ucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 18,
"Comment": "0x0f 0x2e",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp s16, s17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"msr nzcv, x20"
]
},
"comiss xmm0, xmm1": {
"ExpectedInstructionCount": 18,
"Comment": "0x0f 0x2f",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"fcmp s16, s17",
"cset x21, eq",
"csinc x21, x21, xzr, vc",
"cset x1, lt",
"bfi x21, x1, #1, #1",
"cset x1, vs",
"bfi x21, x1, #2, #1",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"bfi w20, w22, #29, #1",
"bfi w20, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"mov w21, #0x90000000",
"bic x20, x20, x21",
"msr nzcv, x20"
]
},
"rdtsc": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x31",
"ExpectedArm64ASM": [
"mrs x20, S3_3_c14_c0_2",
"mov w4, w20",
"lsr x6, x20, #32"
]
},
"cmovo ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x40",
"ExpectedArm64ASM": [
"csel w20, w7, w4, vs",
"bfxil x4, x20, #0, #16"
]
},
"cmovo eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x40",
"ExpectedArm64ASM": [
"csel w4, w7, w4, vs"
]
},
"cmovo rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x40",
"ExpectedArm64ASM": [
"csel x4, x7, x4, vs"
]
},
"cmovno ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x41",
"ExpectedArm64ASM": [
"csel w20, w7, w4, vc",
"bfxil x4, x20, #0, #16"
]
},
"cmovno eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x41",
"ExpectedArm64ASM": [
"csel w4, w7, w4, vc"
]
},
"cmovno rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x41",
"ExpectedArm64ASM": [
"csel x4, x7, x4, vc"
]
},
"cmovb ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x42",
"ExpectedArm64ASM": [
"csel w20, w7, w4, hs",
"bfxil x4, x20, #0, #16"
]
},
"cmovb eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x42",
"ExpectedArm64ASM": [
"csel w4, w7, w4, hs"
]
},
"cmovb rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x42",
"ExpectedArm64ASM": [
"csel x4, x7, x4, hs"
]
},
"cmovnb ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x43",
"ExpectedArm64ASM": [
"csel w20, w7, w4, lo",
"bfxil x4, x20, #0, #16"
]
},
"cmovnb eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x43",
"ExpectedArm64ASM": [
"csel w4, w7, w4, lo"
]
},
"cmovnb rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x43",
"ExpectedArm64ASM": [
"csel x4, x7, x4, lo"
]
},
"cmovz ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x44",
"ExpectedArm64ASM": [
"csel w20, w7, w4, eq",
"bfxil x4, x20, #0, #16"
]
},
"cmovz eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x44",
"ExpectedArm64ASM": [
"csel w4, w7, w4, eq"
]
},
"cmovz rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x44",
"ExpectedArm64ASM": [
"csel x4, x7, x4, eq"
]
},
"cmovnz ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x45",
"ExpectedArm64ASM": [
"csel w20, w7, w4, ne",
"bfxil x4, x20, #0, #16"
]
},
"cmovnz eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x45",
"ExpectedArm64ASM": [
"csel w4, w7, w4, ne"
]
},
"cmovnz rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x45",
"ExpectedArm64ASM": [
"csel x4, x7, x4, ne"
]
},
"cmovbe ax, bx": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x46",
"ExpectedArm64ASM": [
"csel w20, w7, w4, hs",
"csel w20, w7, w20, eq",
"bfxil x4, x20, #0, #16"
]
},
"cmovbe eax, ebx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x46",
"ExpectedArm64ASM": [
"csel w20, w7, w4, hs",
"csel w4, w7, w20, eq"
]
},
"cmovbe rax, rbx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x46",
"ExpectedArm64ASM": [
"csel x20, x7, x4, hs",
"csel x4, x7, x20, eq"
]
},
"cmovnbe ax, bx": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x47",
"ExpectedArm64ASM": [
"csel w20, w7, w4, lo",
"csel w20, w20, w4, ne",
"bfxil x4, x20, #0, #16"
]
},
"cmovnbe eax, ebx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x47",
"ExpectedArm64ASM": [
"csel w20, w7, w4, lo",
"csel w4, w20, w4, ne"
]
},
"cmovnbe rax, rbx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x47",
"ExpectedArm64ASM": [
"csel x20, x7, x4, lo",
"csel x4, x20, x4, ne"
]
},
"cmovs ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x48",
"ExpectedArm64ASM": [
"csel w20, w7, w4, mi",
"bfxil x4, x20, #0, #16"
]
},
"cmovs eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x48",
"ExpectedArm64ASM": [
"csel w4, w7, w4, mi"
]
},
"cmovs rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x48",
"ExpectedArm64ASM": [
"csel x4, x7, x4, mi"
]
},
"cmovns ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x49",
"ExpectedArm64ASM": [
"csel w20, w7, w4, pl",
"bfxil x4, x20, #0, #16"
]
},
"cmovns eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x49",
"ExpectedArm64ASM": [
"csel w4, w7, w4, pl"
]
},
"cmovns rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x49",
"ExpectedArm64ASM": [
"csel x4, x7, x4, pl"
]
},
"cmovpe ax, bx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel w20, w7, w4, eq",
"bfxil x4, x20, #0, #16",
"msr nzcv, x21"
]
},
"cmovpe eax, ebx": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel w4, w7, w4, eq",
"msr nzcv, x21"
]
},
"cmovpe rax, rbx": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4a",
"ExpectedArm64ASM": [
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel x4, x7, x4, eq",
"msr nzcv, x21"
]
},
"cmovnp ax, bx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel w20, w7, w4, ne",
"bfxil x4, x20, #0, #16",
"msr nzcv, x21"
]
},
"cmovnp eax, ebx": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel w4, w7, w4, ne",
"msr nzcv, x21"
]
},
"cmovnp rax, rbx": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0x4b",
"ExpectedArm64ASM": [
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mrs x21, nzcv",
"tst w20, #0x1",
"csel x4, x7, x4, ne",
"msr nzcv, x21"
]
},
"cmovl ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x4c",
"ExpectedArm64ASM": [
"csel w20, w7, w4, lt",
"bfxil x4, x20, #0, #16"
]
},
"cmovl eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x4c",
"ExpectedArm64ASM": [
"csel w4, w7, w4, lt"
]
},
"cmovl rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x4c",
"ExpectedArm64ASM": [
"csel x4, x7, x4, lt"
]
},
"cmovnl ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x4d",
"ExpectedArm64ASM": [
"csel w20, w7, w4, ge",
"bfxil x4, x20, #0, #16"
]
},
"cmovnl eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x4d",
"ExpectedArm64ASM": [
"csel w4, w7, w4, ge"
]
},
"cmovnl rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x4d",
"ExpectedArm64ASM": [
"csel x4, x7, x4, ge"
]
},
"cmovle ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x4e",
"ExpectedArm64ASM": [
"csel w20, w7, w4, le",
"bfxil x4, x20, #0, #16"
]
},
"cmovle eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x4e",
"ExpectedArm64ASM": [
"csel w4, w7, w4, le"
]
},
"cmovle rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x4e",
"ExpectedArm64ASM": [
"csel x4, x7, x4, le"
]
},
"cmovnle ax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x4f",
"ExpectedArm64ASM": [
"csel w20, w7, w4, gt",
"bfxil x4, x20, #0, #16"
]
},
"cmovnle eax, ebx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x4f",
"ExpectedArm64ASM": [
"csel w4, w7, w4, gt"
]
},
"cmovnle rax, rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x4f",
"ExpectedArm64ASM": [
"csel x4, x7, x4, gt"
]
},
"movmskps eax, xmm0": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2064]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
]
},
"movmskps rax, xmm0": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x50",
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"ldr q3, [x28, #2064]",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
]
},
"sqrtps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x51",
"ExpectedArm64ASM": [
"fsqrt v16.4s, v17.4s"
]
},
"rsqrtps xmm0, xmm1": {
"ExpectedInstructionCount": 3,
"Comment": [
"0x0f 0x52"
],
"ExpectedArm64ASM": [
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v17.4s",
"fdiv v16.4s, v0.4s, v1.4s"
]
},
"rcpps xmm0, xmm1": {
"ExpectedInstructionCount": 2,
"Comment": [
"0x0f 0x53"
],
"ExpectedArm64ASM": [
"fmov v0.4s, #0x70 (1.0000)",
"fdiv v16.4s, v0.4s, v17.4s"
]
},
"andps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x54",
"ExpectedArm64ASM": [
"and v16.16b, v16.16b, v17.16b"
]
},
"andnps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x55",
"ExpectedArm64ASM": [
"bic v16.16b, v17.16b, v16.16b"
]
},
"orps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x56",
"ExpectedArm64ASM": [
"orr v16.16b, v16.16b, v17.16b"
]
},
"xorps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x57",
"ExpectedArm64ASM": [
"eor v16.16b, v16.16b, v17.16b"
]
},
"addps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x58",
"ExpectedArm64ASM": [
"fadd v16.4s, v16.4s, v17.4s"
]
},
"mulps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x59",
"ExpectedArm64ASM": [
"fmul v16.4s, v16.4s, v17.4s"
]
},
"cvtps2pd xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x5a",
"ExpectedArm64ASM": [
"fcvtl v16.2d, v17.2s"
]
},
"cvtps2pd xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x5a",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"fcvtl v16.2d, v2.2s"
]
},
"cvtdq2ps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x5b",
"ExpectedArm64ASM": [
"scvtf v16.4s, v17.4s"
]
},
"subps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x5c",
"ExpectedArm64ASM": [
"fsub v16.4s, v16.4s, v17.4s"
]
},
"minps xmm0, xmm1": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x5d",
"ExpectedArm64ASM": [
"fcmgt v0.4s, v17.4s, v16.4s",
"bif v16.16b, v17.16b, v0.16b"
]
},
"divps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0x5e",
"ExpectedArm64ASM": [
"fdiv v16.4s, v16.4s, v17.4s"
]
},
"maxps xmm0, xmm1": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x5f",
"ExpectedArm64ASM": [
"fcmgt v0.4s, v17.4s, v16.4s",
"bit v16.16b, v17.16b, v0.16b"
]
},
"punpcklbw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x60",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"zip1 v2.8b, v2.8b, v3.8b",
"str d2, [x28, #768]"
]
},
"punpcklbw mm0, [rax]": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x60",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x4]",
"zip1 v2.8b, v2.8b, v3.8b",
"str d2, [x28, #768]"
]
},
"punpcklwd mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x61",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"zip1 v2.4h, v2.4h, v3.4h",
"str d2, [x28, #768]"
]
},
"punpcklwd mm0, [rax]": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x61",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x4]",
"zip1 v2.4h, v2.4h, v3.4h",
"str d2, [x28, #768]"
]
},
"punpckldq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x62",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"zip1 v2.2s, v2.2s, v3.2s",
"str d2, [x28, #768]"
]
},
"punpckldq mm0, [rax]": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x62",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x4]",
"zip1 v2.2s, v2.2s, v3.2s",
"str d2, [x28, #768]"
]
},
"packsswb mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x63",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"zip1 v2.2d, v2.2d, v3.2d",
"sqxtn v2.8b, v2.8h",
"str d2, [x28, #768]"
]
},
"packsswb mm0, [rax]": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x63",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x4]",
"zip1 v2.2d, v2.2d, v3.2d",
"sqxtn v2.8b, v2.8h",
"str d2, [x28, #768]"
]
},
"packsswb mm0, mm0": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x63",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"zip1 v2.2d, v2.2d, v2.2d",
"sqxtn v2.8b, v2.8h",
"str d2, [x28, #768]"
]
},
"pcmpgtb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x64",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"cmgt v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"pcmpgtw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x65",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"cmgt v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"pcmpgtd mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x66",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"cmgt v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
]
},
"punpckhbw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x68",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"zip2 v2.8b, v2.8b, v3.8b",
"str d2, [x28, #768]"
]
},
"punpckhbw mm0, [rax]": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x68",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x4]",
"zip2 v2.8b, v2.8b, v3.8b",
"str d2, [x28, #768]"
]
},
"punpckhwd mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x69",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"zip2 v2.4h, v2.4h, v3.4h",
"str d2, [x28, #768]"
]
},
"punpckhwd mm0, [rax]": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x69",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x4]",
"zip2 v2.4h, v2.4h, v3.4h",
"str d2, [x28, #768]"
]
},
"punpckhdq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x6a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"zip2 v2.2s, v2.2s, v3.2s",
"str d2, [x28, #768]"
]
},
"punpckhdq mm0, [rax]": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x6a",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x4]",
"zip2 v2.2s, v2.2s, v3.2s",
"str d2, [x28, #768]"
]
},
"packssdw mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x6b",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"zip1 v2.2d, v2.2d, v3.2d",
"sqxtn v2.4h, v2.4s",
"str d2, [x28, #768]"
]
},
"movd mm0, eax": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x6e",
"ExpectedArm64ASM": [
"fmov s2, w4",
"str d2, [x28, #768]"
]
},
"movd mm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x6e",
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str d2, [x28, #768]"
]
},
"movq mm0, mm0": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x6f",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x28, #768]"
]
},
"movq mm0, mm1": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x6f",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
]
},
"movq mm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x6f",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str d2, [x28, #768]"
]
},
"pshufw mm0, mm1, 0": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"dup v2.4h, v2.h[0]",
"str d2, [x28, #768]"
]
},
"pshufw mm0, [rax], 0": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"dup v2.4h, v2.h[0]",
"str d2, [x28, #768]"
]
},
"pshufw mm0, mm1, 1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr x0, [x28, #1672]",
"ldr d3, [x0, #16]",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #768]"
]
},
"pshufw mm0, [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"ldr x0, [x28, #1672]",
"ldr d3, [x0, #16]",
"tbl v2.8b, {v2.16b}, v3.8b",
"str d2, [x28, #768]"
]
},
"pshufw mm0, mm1, 0xff": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"dup v2.4h, v2.h[3]",
"str d2, [x28, #768]"
]
},
"pshufw mm0, [rax], 0xff": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x70",
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"dup v2.4h, v2.h[3]",
"str d2, [x28, #768]"
]
},
"pcmpeqb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x74",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"cmeq v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"pcmpeqw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x75",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"cmeq v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"pcmpeqd mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x76",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"cmeq v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
]
},
"emms": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x77",
"ExpectedArm64ASM": [
"mov w20, #0x0",
"strb w20, [x28, #1026]"
]
},
"movd eax, mm0": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x7e",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"mov w4, v2.s[0]"
]
},
"movd [rax], mm0": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x7e",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str s2, [x4]"
]
},
"db 0x0f, 0x7f, 0xc1": {
"ExpectedInstructionCount": 2,
"Comment": [
"movq mm0, mm1",
"Manual encoded since nasm would encode 0x6f version",
"0x0f 0x7f"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x28, #784]"
]
},
"movq [rax], mm0": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x7f",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x4]"
]
},
"seto al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x90",
"ExpectedArm64ASM": [
"cset x20, vs",
"bfxil x4, x20, #0, #8"
]
},
"setno al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x91",
"ExpectedArm64ASM": [
"cset x20, vc",
"bfxil x4, x20, #0, #8"
]
},
"setb al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x92",
"ExpectedArm64ASM": [
"cset x20, hs",
"bfxil x4, x20, #0, #8"
]
},
"setnb al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x93",
"ExpectedArm64ASM": [
"cset x20, lo",
"bfxil x4, x20, #0, #8"
]
},
"setz al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x94",
"ExpectedArm64ASM": [
"cset x20, eq",
"bfxil x4, x20, #0, #8"
]
},
"setnz al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x95",
"ExpectedArm64ASM": [
"cset x20, ne",
"bfxil x4, x20, #0, #8"
]
},
"setbe al": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0x96",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset x21, hs",
"csel x20, x20, x21, eq",
"bfxil x4, x20, #0, #8"
]
},
"setnbe al": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0x97",
"ExpectedArm64ASM": [
"cset x20, lo",
"csel x20, x20, xzr, ne",
"bfxil x4, x20, #0, #8"
]
},
"sets al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x98",
"ExpectedArm64ASM": [
"cset x20, mi",
"bfxil x4, x20, #0, #8"
]
},
"setns al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x99",
"ExpectedArm64ASM": [
"cset x20, pl",
"bfxil x4, x20, #0, #8"
]
},
"setpe al": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0x9a",
"ExpectedArm64ASM": [
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"mvn w20, w20",
"and x20, x20, #0x1",
"bfxil x4, x20, #0, #8"
]
},
"setnp al": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0x9b",
"ExpectedArm64ASM": [
"fmov s2, w26",
"cnt v2.16b, v2.16b",
"umov w20, v2.b[0]",
"and x20, x20, #0x1",
"bfxil x4, x20, #0, #8"
]
},
"setl al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x9c",
"ExpectedArm64ASM": [
"cset x20, lt",
"bfxil x4, x20, #0, #8"
]
},
"setnl al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x9d",
"ExpectedArm64ASM": [
"cset x20, ge",
"bfxil x4, x20, #0, #8"
]
},
"setle al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x9e",
"ExpectedArm64ASM": [
"cset x20, le",
"bfxil x4, x20, #0, #8"
]
},
"setnle al": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0x9f",
"ExpectedArm64ASM": [
"cset x20, gt",
"bfxil x4, x20, #0, #8"
]
},
"push fs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [
"ldr x20, [x28, #176]",
"str x20, [x8, #-8]!"
]
},
"pop fs": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xa1",
"ExpectedArm64ASM": [
"ldr x20, [x8]",
"add x8, x8, #0x8 (8)",
"strh w20, [x28, #146]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #176]"
]
},
"bt ax, bx": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"and x20, x20, #0xf",
"lsr x20, x4, x20",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt [rax], bx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #13",
"ldrb w20, [x4, x20, sxtx]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt eax, ebx": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"mov w20, w7",
"and x20, x20, #0x1f",
"lsr x20, x4, x20",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt [rax], ebx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"mov w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #29",
"ldrb w20, [x4, x20, sxtx]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt rax, rbx": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"and x20, x7, #0x3f",
"lsr x20, x4, x20",
"ubfx x20, x20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bt [rax], rbx": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xa3",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #3",
"asr x21, x7, #3",
"ldrb w21, [x4, x21, sxtx]",
"lsr w20, w21, w20",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"shld ax, bx, 0": {
"ExpectedInstructionCount": 0,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": []
},
"shld ax, bx, 1": {
"ExpectedInstructionCount": 14,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #1",
"lsr w20, w20, #15",
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x22, x21, #15, #1",
"orr w20, w20, w22, lsl #29",
"eor w21, w26, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"shld ax, bx, 15": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #15",
"lsr w20, w20, #1",
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x21, x21, #1, #1",
"orr w20, w20, w21, lsl #29",
"msr nzcv, x20"
]
},
"shld ax, bx, 16": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #16",
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x21, x21, #0, #1",
"orr w20, w20, w21, lsl #29",
"msr nzcv, x20"
]
},
"shld ax, bx, 31": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"lsl x22, x21, #31",
"lsr w20, w20, #17",
"orr x26, x22, x20",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x21, x21, #1, #1",
"orr w20, w20, w21, lsl #29",
"msr nzcv, x20"
]
},
"shld eax, ebx, 0": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov w4, w4"
]
},
"shld eax, ebx, 1": {
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"extr w4, w21, w20, #31",
"tst w4, w4",
"mrs x20, nzcv",
"ubfx x22, x21, #31, #1",
"orr w20, w20, w22, lsl #29",
"mov x26, x4",
"eor w21, w4, w21",
"ubfx x21, x21, #31, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"shld eax, ebx, 15": {
"ExpectedInstructionCount": 9,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"extr w4, w21, w20, #17",
"tst w4, w4",
"mrs x20, nzcv",
"ubfx x21, x21, #17, #1",
"orr w20, w20, w21, lsl #29",
"mov x26, x4",
"msr nzcv, x20"
]
},
"shld eax, ebx, 16": {
"ExpectedInstructionCount": 9,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"extr w4, w21, w20, #16",
"tst w4, w4",
"mrs x20, nzcv",
"ubfx x21, x21, #16, #1",
"orr w20, w20, w21, lsl #29",
"mov x26, x4",
"msr nzcv, x20"
]
},
"shld eax, ebx, 31": {
"ExpectedInstructionCount": 9,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"extr w4, w21, w20, #1",
"tst w4, w4",
"mrs x20, nzcv",
"ubfx x21, x21, #1, #1",
"orr w20, w20, w21, lsl #29",
"mov x26, x4",
"msr nzcv, x20"
]
},
"shld rax, rbx, 0": {
"ExpectedInstructionCount": 0,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": []
},
"shld rax, rbx, 1": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov x20, x4",
"extr x4, x20, x7, #63",
"tst x4, x4",
"mrs x21, nzcv",
"lsr x22, x20, #63",
"orr w21, w21, w22, lsl #29",
"mov x26, x4",
"eor x20, x4, x20",
"lsr x20, x20, #63",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"shld rax, rbx, 15": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov x20, x4",
"extr x4, x20, x7, #49",
"tst x4, x4",
"mrs x21, nzcv",
"ubfx x20, x20, #49, #1",
"orr w20, w21, w20, lsl #29",
"mov x26, x4",
"msr nzcv, x20"
]
},
"shld rax, rbx, 32": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov x20, x4",
"extr x4, x20, x7, #32",
"tst x4, x4",
"mrs x21, nzcv",
"ubfx x20, x20, #32, #1",
"orr w20, w21, w20, lsl #29",
"mov x26, x4",
"msr nzcv, x20"
]
},
"shld rax, rbx, 63": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xac",
"ExpectedArm64ASM": [
"mov x20, x4",
"extr x4, x20, x7, #1",
"tst x4, x4",
"mrs x21, nzcv",
"ubfx x20, x20, #1, #1",
"orr w20, w21, w20, lsl #29",
"mov x26, x4",
"msr nzcv, x20"
]
},
"shld ax, bx, cl": {
"ExpectedInstructionCount": 28,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"uxtb w22, w5",
"and x22, x22, #0x1f",
"mov w23, #0x10",
"sub x23, x23, x22",
"lsl x24, x21, x22",
"lsr w20, w20, w23",
"orr x20, x24, x20",
"mrs x23, nzcv",
"cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq",
"bfxil x4, x20, #0, #16",
"uxth x20, w20",
"msr nzcv, x23",
"cbz x22, #+0x34",
"cmn wzr, w20, lsl #16",
"mrs x23, nzcv",
"mov w24, #0x10",
"sub w22, w24, w22",
"lsr w22, w21, w22",
"ubfx x22, x22, #0, #1",
"orr w22, w23, w22, lsl #29",
"mov x26, x20",
"eor w20, w21, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"shld eax, ebx, cl": {
"ExpectedInstructionCount": 28,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"uxtb w22, w5",
"and x22, x22, #0x1f",
"mov w23, #0x20",
"sub x23, x23, x22",
"lsl x24, x21, x22",
"lsr w20, w20, w23",
"orr x20, x24, x20",
"mrs x23, nzcv",
"cmp x22, #0x0 (0)",
"csel x20, x21, x20, eq",
"mov w4, w20",
"mov w20, w20",
"msr nzcv, x23",
"cbz x22, #+0x34",
"tst w20, w20",
"mrs x23, nzcv",
"mov w24, #0x20",
"sub w22, w24, w22",
"lsr w22, w21, w22",
"ubfx x22, x22, #0, #1",
"orr w22, w23, w22, lsl #29",
"mov x26, x20",
"eor w20, w21, w20",
"ubfx x20, x20, #31, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"shld rax, rbx, cl": {
"ExpectedInstructionCount": 26,
"Comment": "0x0f 0xad",
"ExpectedArm64ASM": [
"mov x20, x4",
"uxtb w21, w5",
"and x21, x21, #0x3f",
"mov w22, #0x40",
"sub x22, x22, x21",
"lsl x23, x20, x21",
"lsr x22, x7, x22",
"orr x22, x23, x22",
"mrs x23, nzcv",
"cmp x21, #0x0 (0)",
"csel x22, x20, x22, eq",
"mov x4, x22",
"msr nzcv, x23",
"cbz x21, #+0x34",
"tst x22, x22",
"mrs x23, nzcv",
"mov w24, #0x40",
"sub x21, x24, x21",
"lsr x21, x20, x21",
"ubfx x21, x21, #0, #1",
"orr w21, w23, w21, lsl #29",
"mov x26, x22",
"eor x20, x20, x22",
"lsr x20, x20, #63",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"push gs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [
"ldr x20, [x28, #168]",
"str x20, [x8, #-8]!"
]
},
"pop gs": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xa9",
"ExpectedArm64ASM": [
"ldr x20, [x8]",
"add x8, x8, #0x8 (8)",
"strh w20, [x28, #144]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #896]",
"str w20, [x28, #168]"
]
},
"bts ax, bx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
"uxth w20, w7",
"and x20, x20, #0xf",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"orr x20, x4, x20",
"bfxil x4, x20, #0, #16",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts [rax], bx": {
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #13",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldrb w23, [x4, x20, sxtx]",
"lsr w21, w23, w21",
"orr x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts eax, ebx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
"mov w20, w7",
"and x20, x20, #0x1f",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"orr x20, x4, x20",
"mov w4, w20",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts [rax], ebx": {
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
"mov w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #29",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldrb w23, [x4, x20, sxtx]",
"lsr w21, w23, w21",
"orr x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts rax, rbx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
"and x20, x7, #0x3f",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"orr x4, x4, x20",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bts [rax], rbx": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xab",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #3",
"asr x21, x7, #3",
"mov w22, #0x1",
"lsl x22, x22, x20",
"ldrb w23, [x4, x21, sxtx]",
"lsr w20, w23, w20",
"orr x22, x23, x22",
"strb w22, [x4, x21, sxtx]",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock bts [rax], bx": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #13",
"add x20, x4, x20",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldsetalb w22, w20, [x20]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock bts [rax], ebx": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"mov w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #29",
"add x20, x4, x20",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldsetalb w22, w20, [x20]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock bts [rax], rbx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #3",
"asr x21, x7, #3",
"add x21, x4, x21",
"mov w22, #0x1",
"lsl x22, x22, x20",
"ldsetalb w22, w21, [x21]",
"lsr w20, w21, w20",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"imul ax, bx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xaf",
"ExpectedArm64ASM": [
"sxth x20, w4",
"sxth x21, w7",
"mul x20, x20, x21",
"sbfx x21, x20, #16, #16",
"bfxil x4, x20, #0, #16",
"sbfx x20, x20, #15, #1",
"cmp x21, x20",
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul eax, ebx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xaf",
"ExpectedArm64ASM": [
"sxtw x20, w4",
"sxtw x21, w7",
"mul x20, x20, x21",
"asr x21, x20, #32",
"mov w4, w20",
"sbfx x20, x20, #31, #1",
"cmp x21, x20",
"ccmn xzr, #0, #nzCV, eq"
]
},
"imul rax, rbx": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xaf",
"ExpectedArm64ASM": [
"smulh x20, x4, x7",
"mul x4, x4, x7",
"asr x21, x4, #63",
"cmp x20, x21",
"ccmn xzr, #0, #nzCV, eq"
]
},
"cmpxchg al, bl": {
"ExpectedInstructionCount": 21,
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxtb w21, w4",
"uxtb x22, w4",
"cmp x21, x22",
"csel x23, x22, x21, eq",
"cmp x21, x22",
"csel w20, w20, w21, eq",
"bfxil x4, x23, #0, #8",
"bfxil x4, x20, #0, #8",
"sub x26, x22, x23",
"eor w27, w22, w23",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"ubfx x21, x26, #8, #1",
"orr w20, w20, w21, lsl #29",
"eor w21, w22, w23",
"eor w22, w26, w22",
"and w21, w22, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"cmpxchg [rax], bl": {
"ExpectedInstructionCount": 18,
"Comment": "0x0f 0xb0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"uxtb w21, w4",
"mov w1, w21",
"casalb w1, w20, [x4]",
"mov w20, w1",
"bfxil x4, x20, #0, #8",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"ubfx x23, x26, #8, #1",
"orr w22, w22, w23, lsl #29",
"eor w20, w21, w20",
"eor w21, w26, w21",
"and w20, w21, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"cmpxchg ax, bx": {
"ExpectedInstructionCount": 21,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"uxth x22, w4",
"cmp x21, x22",
"csel x23, x22, x21, eq",
"cmp x21, x22",
"csel w20, w20, w21, eq",
"bfxil x4, x23, #0, #16",
"bfxil x4, x20, #0, #16",
"sub x26, x22, x23",
"eor w27, w22, w23",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x21, x26, #16, #1",
"orr w20, w20, w21, lsl #29",
"eor w21, w22, w23",
"eor w22, w26, w22",
"and w21, w22, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"cmpxchg [rax], bx": {
"ExpectedInstructionCount": 18,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"uxth w21, w4",
"mov w1, w21",
"casalh w1, w20, [x4]",
"mov w20, w1",
"bfxil x4, x20, #0, #16",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"ubfx x23, x26, #16, #1",
"orr w22, w22, w23, lsl #29",
"eor w20, w21, w20",
"eor w21, w26, w21",
"and w20, w21, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"cmpxchg eax, ebx": {
"ExpectedInstructionCount": 17,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov x21, x4",
"mov w22, w21",
"mov w23, w21",
"cmp x22, x23",
"csel x24, x23, x22, eq",
"cmp x22, x23",
"csel x20, x20, x21, eq",
"cmp x24, x23",
"csel x4, x21, x22, eq",
"mov x4, x20",
"sub x26, x23, x24",
"eor w27, w23, w24",
"cmp w23, w24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"cmpxchg [rax], ebx": {
"ExpectedInstructionCount": 13,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov w21, w4",
"mov w1, w21",
"casal w1, w20, [x4]",
"mov w20, w1",
"cmp w20, w21",
"csel x4, x4, x20, eq",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmp w21, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"cmpxchg rax, rbx": {
"ExpectedInstructionCount": 13,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov x20, x4",
"cmp x20, x20",
"csel x21, x20, x20, eq",
"cmp x20, x20",
"csel x22, x7, x20, eq",
"mov x4, x21",
"mov x4, x22",
"sub x26, x20, x21",
"eor x27, x20, x21",
"cmp x20, x21",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"cmpxchg [rax], rbx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xb1",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x1, x20",
"casal x1, x7, [x20]",
"mov x4, x1",
"sub x26, x20, x4",
"eor x27, x20, x4",
"cmp x20, x4",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"btr ax, bx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"and x20, x20, #0xf",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"bic x20, x4, x20",
"bfxil x4, x20, #0, #16",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr [rax], bx": {
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #13",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldrb w23, [x4, x20, sxtx]",
"lsr w21, w23, w21",
"bic x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr eax, ebx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"mov w20, w7",
"and x20, x20, #0x1f",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"bic x20, x4, x20",
"mov w4, w20",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr [rax], ebx": {
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"mov w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #29",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldrb w23, [x4, x20, sxtx]",
"lsr w21, w23, w21",
"bic x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr rax, rbx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"and x20, x7, #0x3f",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"bic x4, x4, x20",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btr [rax], rbx": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #3",
"asr x21, x7, #3",
"mov w22, #0x1",
"lsl x22, x22, x20",
"ldrb w23, [x4, x21, sxtx]",
"lsr w20, w23, w20",
"bic x22, x23, x22",
"strb w22, [x4, x21, sxtx]",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"movzx ax, bl": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xb6",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"bfxil x4, x20, #0, #16"
]
},
"lock btr [rax], bx": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #13",
"add x20, x4, x20",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldclralb w22, w20, [x20]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btr [rax], ebx": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"mov w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #29",
"add x20, x4, x20",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldclralb w22, w20, [x20]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btr [rax], rbx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #3",
"asr x21, x7, #3",
"add x21, x4, x21",
"mov w22, #0x1",
"lsl x22, x22, x20",
"ldclralb w22, w21, [x21]",
"lsr w20, w21, w20",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"movzx ax, byte [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xb6",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"bfxil x4, x20, #0, #16"
]
},
"movzx eax, bl": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xb6",
"ExpectedArm64ASM": [
"uxtb w4, w7"
]
},
"movzx eax, byte [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xb6",
"ExpectedArm64ASM": [
"ldrb w4, [x4]"
]
},
"movzx rax, bl": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xb6",
"ExpectedArm64ASM": [
"uxtb w4, w7"
]
},
"movzx rax, byte [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xb6",
"ExpectedArm64ASM": [
"ldrb w4, [x4]"
]
},
"movzx eax, bx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xb7",
"ExpectedArm64ASM": [
"uxth w4, w7"
]
},
"movzx eax, word [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xb7",
"ExpectedArm64ASM": [
"ldrh w4, [x4]"
]
},
"movzx rax, bx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xb7",
"ExpectedArm64ASM": [
"uxth w4, w7"
]
},
"movzx rax, word [rax]": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xb7",
"ExpectedArm64ASM": [
"ldrh w4, [x4]"
]
},
"btc ax, bx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
"uxth w20, w7",
"and x20, x20, #0xf",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"eor x20, x4, x20",
"bfxil x4, x20, #0, #16",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc [rax], bx": {
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #13",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldrb w23, [x4, x20, sxtx]",
"lsr w21, w23, w21",
"eor x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc eax, ebx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
"mov w20, w7",
"and x20, x20, #0x1f",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"eor x20, x4, x20",
"mov w4, w20",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc [rax], ebx": {
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
"mov w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #29",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldrb w23, [x4, x20, sxtx]",
"lsr w21, w23, w21",
"eor x22, x23, x22",
"strb w22, [x4, x20, sxtx]",
"ubfx w20, w21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc rax, rbx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
"and x20, x7, #0x3f",
"lsr x21, x4, x20",
"mov w22, #0x1",
"lsl x20, x22, x20",
"eor x4, x4, x20",
"ubfx x20, x21, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"btc [rax], rbx": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xbb",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #3",
"asr x21, x7, #3",
"mov w22, #0x1",
"lsl x22, x22, x20",
"ldrb w23, [x4, x21, sxtx]",
"lsr w20, w23, w20",
"eor x22, x23, x22",
"strb w22, [x4, x21, sxtx]",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btc [rax], bx": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #13",
"add x20, x4, x20",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldeoralb w22, w20, [x20]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btc [rax], ebx": {
"ExpectedInstructionCount": 11,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"mov w20, w7",
"ubfx w21, w20, #0, #3",
"sbfx x20, x20, #3, #29",
"add x20, x4, x20",
"mov w22, #0x1",
"lsl x22, x22, x21",
"ldeoralb w22, w20, [x20]",
"lsr w20, w20, w21",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"lock btc [rax], rbx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xb3",
"ExpectedArm64ASM": [
"ubfx x20, x7, #0, #3",
"asr x21, x7, #3",
"add x21, x4, x21",
"mov w22, #0x1",
"lsl x22, x22, x20",
"ldeoralb w22, w21, [x21]",
"lsr w20, w21, w20",
"ubfx w20, w20, #0, #1",
"lsl x20, x20, #29",
"msr nzcv, x20"
]
},
"bsf ax, bx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w7",
"uxth w0, w21",
"cmp w0, #0x0 (0)",
"rbit w0, w0",
"clz w22, w0",
"csinv w22, w22, wzr, ne",
"cmn wzr, w21, lsl #16",
"csel x20, x20, x22, eq",
"bfxil x4, x20, #0, #16"
]
},
"bsf eax, ebx": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"mov w20, w7",
"lsr w0, w20, #0",
"cmp w0, #0x0 (0)",
"rbit w0, w0",
"clz w21, w0",
"csinv w21, w21, wzr, ne",
"tst w20, w20",
"csel x4, x4, x21, eq"
]
},
"bsf rax, rbx": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xbc",
"ExpectedArm64ASM": [
"rbit x0, x7",
"cmp x7, #0x0 (0)",
"clz x20, x0",
"csinv x20, x20, xzr, ne",
"tst x7, x7",
"csel x4, x4, x20, eq"
]
},
"bsr ax, bx": {
"ExpectedInstructionCount": 10,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w7",
"mov x0, #0xf",
"lsl w22, w21, #16",
"orr w22, w22, #0x8000",
"clz w22, w22",
"sub x22, x0, x22",
"cmn wzr, w21, lsl #16",
"csel x20, x20, x22, eq",
"bfxil x4, x20, #0, #16"
]
},
"bsr eax, ebx": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"mov w20, w7",
"mov x0, #0x1f",
"clz w21, w20",
"sub x21, x0, x21",
"tst w20, w20",
"csel x4, x4, x21, eq"
]
},
"bsr rax, rbx": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xbd",
"ExpectedArm64ASM": [
"mov x0, #0x3f",
"clz x20, x7",
"sub x20, x0, x20",
"tst x7, x7",
"csel x4, x4, x20, eq"
]
},
"movsx ax, bl": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xbe",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"sxtb x20, w20",
"bfxil x4, x20, #0, #16"
]
},
"movsx ax, byte [rax]": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xbe",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"sxtb x20, w20",
"bfxil x4, x20, #0, #16"
]
},
"movsx eax, bl": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xbe",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"sxtb x20, w20",
"mov w4, w20"
]
},
"movsx eax, byte [rax]": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xbe",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"sxtb x20, w20",
"mov w4, w20"
]
},
"movsx rax, bl": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xbe",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"sxtb x4, w20"
]
},
"movsx rax, byte [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xbe",
"ExpectedArm64ASM": [
"ldrb w20, [x4]",
"sxtb x4, w20"
]
},
"movsx eax, bx": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xbf",
"ExpectedArm64ASM": [
"uxth w20, w7",
"sxth x20, w20",
"mov w4, w20"
]
},
"movsx eax, word [rax]": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xbf",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"sxth x20, w20",
"mov w4, w20"
]
},
"movsx rax, bx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xbf",
"ExpectedArm64ASM": [
"uxth w20, w7",
"sxth x4, w20"
]
},
"movsx rax, word [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xbf",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"sxth x4, w20"
]
},
"xadd al, bl": {
"ExpectedInstructionCount": 16,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxtb w21, w7",
"add w26, w20, w21",
"bfxil x7, x20, #0, #8",
"bfxil x4, x26, #0, #8",
"eor w27, w20, w21",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"ubfx x23, x26, #8, #1",
"orr w22, w22, w23, lsl #29",
"eor w21, w20, w21",
"eor w20, w26, w20",
"bic w20, w20, w21",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"xadd [rax], bl": {
"ExpectedInstructionCount": 15,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"ldaddalb w20, w21, [x4]",
"bfxil x7, x21, #0, #8",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"ubfx x23, x26, #8, #1",
"orr w22, w22, w23, lsl #29",
"eor w20, w21, w20",
"eor w21, w26, w21",
"bic w20, w21, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"xadd ax, bx": {
"ExpectedInstructionCount": 16,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w4",
"uxth w21, w7",
"add w26, w20, w21",
"bfxil x7, x20, #0, #16",
"bfxil x4, x26, #0, #16",
"eor w27, w20, w21",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"ubfx x23, x26, #16, #1",
"orr w22, w22, w23, lsl #29",
"eor w21, w20, w21",
"eor w20, w26, w20",
"bic w20, w20, w21",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"xadd [rax], bx": {
"ExpectedInstructionCount": 15,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ldaddalh w20, w21, [x4]",
"bfxil x7, x21, #0, #16",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"ubfx x23, x26, #16, #1",
"orr w22, w22, w23, lsl #29",
"eor w20, w21, w20",
"eor w21, w26, w21",
"bic w20, w21, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"xadd eax, ebx": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w4",
"mov w21, w7",
"add w4, w20, w21",
"mov x7, x20",
"eor w27, w20, w21",
"mov x26, x4",
"cmn w20, w21"
]
},
"xadd [rax], ebx": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w7",
"ldaddal w20, w7, [x4]",
"add w26, w7, w20",
"eor w27, w7, w20",
"cmn w7, w20"
]
},
"xadd rax, rbx": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov x20, x4",
"mov x21, x7",
"add x4, x20, x21",
"mov x7, x20",
"eor x27, x20, x21",
"mov x26, x4",
"cmn x20, x21"
]
},
"xadd [rax], rbx": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov x20, x7",
"ldaddal x20, x7, [x4]",
"add x26, x7, x20",
"eor x27, x7, x20",
"cmn x7, x20"
]
},
"cmpps xmm0, xmm1, 0": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xc2",
"ExpectedArm64ASM": [
"fcmeq v16.4s, v16.4s, v17.4s"
]
},
"cmpps xmm0, xmm1, 1": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xc2",
"ExpectedArm64ASM": [
"fcmgt v16.4s, v17.4s, v16.4s"
]
},
"cmpps xmm0, xmm1, 2": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xc2",
"ExpectedArm64ASM": [
"fcmge v16.4s, v17.4s, v16.4s"
]
},
"cmpps xmm0, xmm1, 3": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xc2",
"ExpectedArm64ASM": [
"fcmge v0.4s, v16.4s, v17.4s",
"fcmgt v1.4s, v17.4s, v16.4s",
"orr v16.16b, v0.16b, v1.16b",
"mvn v16.16b, v16.16b"
]
},
"cmpps xmm0, xmm1, 4": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xc2",
"ExpectedArm64ASM": [
"fcmeq v16.4s, v16.4s, v17.4s",
"mvn v16.16b, v16.16b"
]
},
"cmpps xmm0, xmm1, 5": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xc2",
"ExpectedArm64ASM": [
"fcmgt v2.4s, v17.4s, v16.4s",
"mvn v16.16b, v2.16b"
]
},
"cmpps xmm0, xmm1, 6": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xc2",
"ExpectedArm64ASM": [
"fcmge v2.4s, v17.4s, v16.4s",
"mvn v16.16b, v2.16b"
]
},
"cmpps xmm0, xmm1, 7": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc2",
"ExpectedArm64ASM": [
"fcmge v0.4s, v16.4s, v17.4s",
"fcmgt v1.4s, v17.4s, v16.4s",
"orr v16.16b, v0.16b, v1.16b"
]
},
"movnti [rax], ebx": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xc3",
"ExpectedArm64ASM": [
"mov w20, w7",
"str w20, [x4]"
]
},
"movnti [rax], rbx": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xc3",
"ExpectedArm64ASM": [
"str x7, [x4]"
]
},
"pinsrw mm0, eax, 0": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"mov v2.h[0], w4",
"str d2, [x28, #768]"
]
},
"pinsrw mm0, eax, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"mov v2.h[1], w4",
"str d2, [x28, #768]"
]
},
"pinsrw mm0, eax, 2": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"mov v2.h[2], w4",
"str d2, [x28, #768]"
]
},
"pinsrw mm0, eax, 3": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"mov v2.h[3], w4",
"str d2, [x28, #768]"
]
},
"pinsrw mm0, eax, 4": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"mov v2.h[0], w4",
"str d2, [x28, #768]"
]
},
"pinsrw mm0, [rax], 0": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ld1 {v2.h}[0], [x4]",
"str d2, [x28, #768]"
]
},
"pinsrw mm0, [rax], 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ld1 {v2.h}[1], [x4]",
"str d2, [x28, #768]"
]
},
"pinsrw mm0, [rax], 2": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ld1 {v2.h}[2], [x4]",
"str d2, [x28, #768]"
]
},
"pinsrw mm0, [rax], 3": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ld1 {v2.h}[3], [x4]",
"str d2, [x28, #768]"
]
},
"pinsrw mm0, [rax], 4": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ld1 {v2.h}[0], [x4]",
"str d2, [x28, #768]"
]
},
"pextrw eax, mm0, 0": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xc5",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"umov w4, v2.h[0]"
]
},
"pextrw eax, mm0, 1": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xc5",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"umov w4, v2.h[1]"
]
},
"pextrw eax, mm0, 2": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xc5",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"umov w4, v2.h[2]"
]
},
"pextrw eax, mm0, 3": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xc5",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"umov w4, v2.h[3]"
]
},
"pextrw eax, mm0, 4": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xc5",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"umov w4, v2.h[0]"
]
},
"shufps xmm0, xmm1, 01000100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Dst[63:0] = Src1[63:0]",
"Dest[127:64] = Src2[63:0]",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"zip1 v16.2d, v16.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 11101110b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Dst[63:0] = Src1[127:64]",
"Dest[127:64] = Src2[127:64]",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"zip2 v16.2d, v16.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 11100100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Dst[63:0] = Src1[63:0]",
"Dest[127:64] = Src2[127:64]",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"mov v16.d[1], v17.d[1]"
]
},
"shufps xmm0, xmm1, 01001110b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Dst[63:0] = Src1[63:0]",
"Dest[127:64] = Src2[127:64]",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"ext v16.16b, v16.16b, v17.16b, #8"
]
},
"shufps xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[0]",
"dup v3.4s, v17.s[0]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 00000101b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[1]",
"dup v3.4s, v17.s[0]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 00001010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[2]",
"dup v3.4s, v17.s[0]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 00001111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[3]",
"dup v3.4s, v17.s[0]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 01010000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[0]",
"dup v3.4s, v17.s[1]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 01010101b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[1]",
"dup v3.4s, v17.s[1]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 01011010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[2]",
"dup v3.4s, v17.s[1]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 01011111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[3]",
"dup v3.4s, v17.s[1]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 10100000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[0]",
"dup v3.4s, v17.s[2]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 10100101b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[1]",
"dup v3.4s, v17.s[2]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 10101010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[2]",
"dup v3.4s, v17.s[2]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 10101111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[3]",
"dup v3.4s, v17.s[2]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 11110000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[0]",
"dup v3.4s, v17.s[3]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 11110101b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[1]",
"dup v3.4s, v17.s[3]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 11111010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[2]",
"dup v3.4s, v17.s[3]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, xmm1, 11100000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Bottom elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[0]",
"zip2 v16.2d, v2.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 11100101b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Bottom elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[1]",
"zip2 v16.2d, v2.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 11101010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Bottom elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[2]",
"zip2 v16.2d, v2.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 11101111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Bottom elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[3]",
"zip2 v16.2d, v2.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 01000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Bottom elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[0]",
"zip1 v16.2d, v2.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 01000101b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Bottom elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[1]",
"zip1 v16.2d, v2.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 01001010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Bottom elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[2]",
"zip1 v16.2d, v2.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 01001111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Bottom elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[3]",
"zip1 v16.2d, v2.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Top elements duplicated, Bottom 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[0]",
"zip1 v16.2d, v16.2d, v2.2d"
]
},
"shufps xmm0, xmm1, 01010100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Top elements duplicated, Bottom 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[1]",
"zip1 v16.2d, v16.2d, v2.2d"
]
},
"shufps xmm0, xmm1, 10100100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Top elements duplicated, Bottom 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[2]",
"zip1 v16.2d, v16.2d, v2.2d"
]
},
"shufps xmm0, xmm1, 11110100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Top elements duplicated, Bottom 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[3]",
"zip1 v16.2d, v16.2d, v2.2d"
]
},
"shufps xmm0, xmm1, 00001110b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Top elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[0]",
"zip2 v16.2d, v16.2d, v2.2d"
]
},
"shufps xmm0, xmm1, 01011110b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Top elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[1]",
"zip2 v16.2d, v16.2d, v2.2d"
]
},
"shufps xmm0, xmm1, 10101110b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Top elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[2]",
"zip2 v16.2d, v16.2d, v2.2d"
]
},
"shufps xmm0, xmm1, 11111110b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Top elements duplicated, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[3]",
"zip2 v16.2d, v16.2d, v2.2d"
]
},
"shufps xmm0, xmm1, 01000111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"odd elements inverted, Low 64-bits inserted",
"SRA quirks with RA fail to understand that v16 is dead",
"Could InsElement directly in to v16 but it does two moves instead",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"mov v2.16b, v16.16b",
"mov v2.s[0], v16.s[3]",
"zip1 v16.2d, v2.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 11100111b": {
"ExpectedInstructionCount": 4,
"Comment": [
"odd elements inverted, Top 64-bits inserted",
"SRA quirks with RA fail to understand that v16 is dead",
"Could InsElement directly in to v16 but it does two moves instead",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"mov v2.16b, v16.16b",
"mov v2.s[0], v16.s[3]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v17.d[1]"
]
},
"shufps xmm0, xmm1, 11100001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Lower 32-bit elements inverted, Top 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"rev64 v2.4s, v16.4s",
"mov v16.16b, v2.16b",
"mov v16.d[1], v17.d[1]"
]
},
"shufps xmm0, xmm1, 01000001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Lower 32-bit elements inverted, Low 64-bits inserted",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"rev64 v2.4s, v16.4s",
"zip1 v16.2d, v2.2d, v17.2d"
]
},
"shufps xmm0, xmm1, 11111111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Duplicate selected element between each 64-bit segment",
"0x0f 0xc6"
],
"ExpectedArm64ASM": [
"dup v2.4s, v16.s[3]",
"dup v3.4s, v17.s[3]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"shufps xmm0, [rax], 0": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"dup v3.4s, v16.s[0]",
"dup v2.4s, v2.s[0]",
"zip1 v16.2d, v3.2d, v2.2d"
]
},
"shufps xmm0, xmm1, 1": {
"ExpectedInstructionCount": 3,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr x0, [x28, #1696]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v16.16b, v17.16b}, v2.16b"
]
},
"shufps xmm1, xmm0, 1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr x0, [x28, #1696]",
"ldr q2, [x0, #16]",
"mov v0.16b, v17.16b",
"mov v1.16b, v16.16b",
"tbl v17.16b, {v0.16b, v1.16b}, v2.16b"
]
},
"shufps xmm0, [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"ldr x0, [x28, #1696]",
"ldr q3, [x0, #16]",
"mov v0.16b, v16.16b",
"mov v1.16b, v2.16b",
"tbl v16.16b, {v0.16b, v1.16b}, v3.16b"
]
},
"shufps xmm0, [rax], 0xFF": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xc6",
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"dup v3.4s, v16.s[3]",
"dup v2.4s, v2.s[3]",
"zip1 v16.2d, v3.2d, v2.2d"
]
},
"bswap eax": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xc8",
"ExpectedArm64ASM": [
"rev w4, w4"
]
},
"bswap rax": {
"ExpectedInstructionCount": 1,
"Comment": "0x0f 0xc8",
"ExpectedArm64ASM": [
"rev x4, x4"
]
},
"psrlw mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xd1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uqshl d0, d3, #57",
"ushr d0, d0, #57",
"dup v0.8h, v0.h[0]",
"neg v0.8h, v0.8h",
"ushl v2.8h, v2.8h, v0.8h",
"str d2, [x28, #768]"
]
},
"psrld mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xd2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uqshl d0, d3, #57",
"ushr d0, d0, #57",
"dup v0.4s, v0.s[0]",
"neg v0.4s, v0.4s",
"ushl v2.4s, v2.4s, v0.4s",
"str d2, [x28, #768]"
]
},
"psrlq mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xd3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uqshl d0, d3, #57",
"ushr d0, d0, #57",
"dup v0.2d, v0.d[0]",
"neg v0.2d, v0.2d",
"ushl v2.2d, v2.2d, v0.2d",
"str d2, [x28, #768]"
]
},
"paddq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"add v2.2d, v3.2d, v2.2d",
"str d2, [x28, #768]"
]
},
"pmullw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd5",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"mul v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"pmovmskb eax, mm0": {
"ExpectedInstructionCount": 12,
"Comment": "0x0f 0xd7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"mov x20, #0x201",
"movk x20, #0x804, lsl #16",
"movk x20, #0x2010, lsl #32",
"movk x20, #0x8040, lsl #48",
"dup v3.2d, x20",
"cmlt v2.16b, v2.16b, #0",
"and v2.16b, v2.16b, v3.16b",
"addp v2.16b, v2.16b, v2.16b",
"addp v2.8b, v2.8b, v2.8b",
"addp v2.8b, v2.8b, v2.8b",
"umov w4, v2.h[0]"
]
},
"psubusb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd8",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"uqsub v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"psubusw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xd9",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"uqsub v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"pminub mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xda",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"umin v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"pand mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xdb",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"and v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"paddusb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xdc",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"uqadd v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"paddusw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xdd",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"uqadd v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"pmaxub mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xde",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"umax v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"pandn mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xdf",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"bic v2.16b, v2.16b, v3.16b",
"str d2, [x28, #768]"
]
},
"pavgb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xe0",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"urhadd v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"psraw mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xe1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uqshl d0, d3, #57",
"ushr d0, d0, #57",
"dup v0.8h, v0.h[0]",
"neg v0.8h, v0.8h",
"sshl v2.8h, v2.8h, v0.8h",
"str d2, [x28, #768]"
]
},
"psrad mm0, mm1": {
"ExpectedInstructionCount": 8,
"Comment": "0x0f 0xe2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uqshl d0, d3, #57",
"ushr d0, d0, #57",
"dup v0.4s, v0.s[0]",
"neg v0.4s, v0.4s",
"sshl v2.4s, v2.4s, v0.4s",
"str d2, [x28, #768]"
]
},
"pavgw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xe3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"urhadd v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"pmulhuw mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xe4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"umull v2.4s, v2.4h, v3.4h",
"shrn v2.4h, v2.4s, #16",
"str d2, [x28, #768]"
]
},
"pmulhw mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xe5",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"smull v2.4s, v2.4h, v3.4h",
"shrn v2.4h, v2.4s, #16",
"str d2, [x28, #768]"
]
},
"movntq [rax], mm0": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xe7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"str d2, [x4]"
]
},
"psubsb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xe8",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sqsub v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"psubsw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xe9",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sqsub v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"pminsw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xea",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"smin v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"por mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xeb",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"orr v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"paddsb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xec",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sqadd v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"paddsw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xed",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sqadd v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"pmaxsw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xee",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"smax v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"pxor mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xef",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"eor v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"psllw mm0, mm1": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xf1",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uqshl d0, d3, #57",
"ushr d0, d0, #57",
"dup v0.8h, v0.h[0]",
"ushl v2.8h, v2.8h, v0.8h",
"str d2, [x28, #768]"
]
},
"pslld mm0, mm1": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xf2",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uqshl d0, d3, #57",
"ushr d0, d0, #57",
"dup v0.4s, v0.s[0]",
"ushl v2.4s, v2.4s, v0.4s",
"str d2, [x28, #768]"
]
},
"psllq mm0, mm1": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xf3",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uqshl d0, d3, #57",
"ushr d0, d0, #57",
"dup v0.2d, v0.d[0]",
"ushl v2.2d, v2.2d, v0.2d",
"str d2, [x28, #768]"
]
},
"pmuludq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf4",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"umull v2.2d, v2.2s, v3.2s",
"str d2, [x28, #768]"
]
},
"pmaddwd mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xf5",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"smull v2.4s, v2.4h, v3.4h",
"addp v2.4s, v2.4s, v2.4s",
"str d2, [x28, #768]"
]
},
"psadbw mm0, mm1": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xf6",
"ExpectedArm64ASM": [
"ldr d2, [x28, #768]",
"ldr d3, [x28, #784]",
"uabdl v2.8h, v2.8b, v3.8b",
"addv h2, v2.8h",
"str d2, [x28, #768]"
]
},
"maskmovq mm0, mm1": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xf7",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"cmlt v2.16b, v2.16b, #0",
"ldr d3, [x28, #768]",
"ldr d4, [x11]",
"bsl v2.8b, v3.8b, v4.8b",
"str d2, [x11]"
]
},
"psubb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf8",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sub v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"psubw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xf9",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sub v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"psubd mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xfa",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sub v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
]
},
"psubq mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xfb",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"sub v2.2d, v3.2d, v2.2d",
"str d2, [x28, #768]"
]
},
"paddb mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xfc",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"add v2.16b, v3.16b, v2.16b",
"str d2, [x28, #768]"
]
},
"paddw mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xfd",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"add v2.8h, v3.8h, v2.8h",
"str d2, [x28, #768]"
]
},
"paddd mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xfe",
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"add v2.4s, v3.4s, v2.4s",
"str d2, [x28, #768]"
]
}
}
}
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