From cea551c2ac8e9a6a1fe886c75ff311e2b9709e21 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 14 Nov 2023 18:40:19 -0400 Subject: [PATCH] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- .../AFP/SVE256/Secondary.json | 2 +- .../InstructionCountCI/AFP/Secondary.json | 2 +- unittests/InstructionCountCI/Atomics.json | 1544 ++- .../InstructionCountCI/Crypto/H0F3A.json | 4 +- unittests/InstructionCountCI/DDD.json | 126 +- .../InstructionCountCI/FlagM/Atomics.json | 1392 ++- unittests/InstructionCountCI/FlagM/H0F38.json | 8 +- .../InstructionCountCI/FlagM/Primary.json | 2001 ++-- .../FlagM/PrimaryGroup.json | 1202 ++- .../InstructionCountCI/FlagM/Secondary.json | 330 +- .../FlagM/SecondaryGroup.json | 210 +- .../FlagM/SecondaryModRM.json | 14 +- .../FlagM/Secondary_OpSize.json | 32 +- .../FlagM/Secondary_REP.json | 32 +- .../InstructionCountCI/FlagM/VEX_map1.json | 64 +- .../InstructionCountCI/FlagM/VEX_map2.json | 68 +- unittests/InstructionCountCI/FlagM/x87.json | 8688 ++++++++++------- .../InstructionCountCI/FlagM/x87_f64.json | 4096 ++++---- unittests/InstructionCountCI/H0F38.json | 318 +- unittests/InstructionCountCI/H0F3A.json | 450 +- unittests/InstructionCountCI/Primary.json | 2263 ++--- .../InstructionCountCI/PrimaryGroup.json | 1462 ++- .../InstructionCountCI/Primary_32Bit.json | 246 +- unittests/InstructionCountCI/RPRES/DDD.json | 16 +- unittests/InstructionCountCI/Secondary.json | 874 +- .../InstructionCountCI/SecondaryGroup.json | 210 +- .../InstructionCountCI/SecondaryModRM.json | 14 +- .../InstructionCountCI/Secondary_32Bit.json | 4 +- .../InstructionCountCI/Secondary_OpSize.json | 36 +- .../InstructionCountCI/Secondary_REP.json | 36 +- .../InstructionCountCI/Secondary_REPNE.json | 6 +- .../InstructionCountCI/Secondary_SVE128.json | 48 +- unittests/InstructionCountCI/VEX_map1.json | 62 +- unittests/InstructionCountCI/VEX_map2.json | 70 +- unittests/InstructionCountCI/VEX_map3.json | 4 +- unittests/InstructionCountCI/x87.json | 8688 ++++++++++------- unittests/InstructionCountCI/x87_f64.json | 4096 ++++---- 37 files changed, 20027 insertions(+), 18691 deletions(-) diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json index 5ea802188..43e9b7143 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json @@ -25,7 +25,7 @@ "0x0f 0x2a" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "scvtf v16.2s, v2.2s" ] } diff --git a/unittests/InstructionCountCI/AFP/Secondary.json b/unittests/InstructionCountCI/AFP/Secondary.json index 0f71f1632..b0194320b 100644 --- a/unittests/InstructionCountCI/AFP/Secondary.json +++ b/unittests/InstructionCountCI/AFP/Secondary.json @@ -26,7 +26,7 @@ "0x0f 0x2a" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "scvtf v16.2s, v2.2s" ] } diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index e1470eee8..6b6bc0810 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -11,93 +11,84 @@ }, "Instructions": { "lock add byte [rax], cl": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0x00", "ExpectedArm64ASM": [ "uxtb w20, w5", "ldaddalb w20, w21, [x4]", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "lock add word [rax], cx": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0x01", "ExpectedArm64ASM": [ "uxth w20, w5", "ldaddalh w20, w21, [x4]", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "lock add dword [rax], ecx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal w5, w20, [x4]", - "add w21, w20, w5", - "eor w22, w20, w5", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add w26, w20, w5", + "eor w27, w20, w5", "cmn w20, w5" ] }, "lock or byte [rax], cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x08", "ExpectedArm64ASM": [ "ldsetalb w5, w20, [x4]", - "orr w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w20, w5", + "cmn wzr, w26, lsl #24" ] }, "lock or word [rax], cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x09", "ExpectedArm64ASM": [ "ldsetalh w5, w20, [x4]", - "orr w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w20, w5", + "cmn wzr, w26, lsl #16" ] }, "lock or dword [rax], ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x09", "ExpectedArm64ASM": [ "ldsetal w5, w20, [x4]", - "orr w20, w20, w5", - "strb w20, [x28, #706]", - "tst w20, w20" + "orr w26, w20, w5", + "tst w26, w26" ] }, "lock adc byte [rax], cl": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0x10", "ExpectedArm64ASM": [ "uxtb w20, w5", @@ -105,21 +96,19 @@ "add w22, w20, w21", "ldaddalb w22, w23, [x4]", "add w22, w23, w22", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", @@ -127,7 +116,7 @@ ] }, "lock adc word [rax], cx": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0x11", "ExpectedArm64ASM": [ "uxth w20, w5", @@ -135,21 +124,19 @@ "add w22, w20, w21", "ldaddalh w22, w23, [x4]", "add w22, w23, w22", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "ubfx x20, x20, #15, #1", "orr w20, w21, w20, lsl #28", @@ -157,22 +144,20 @@ ] }, "lock adc dword [rax], ecx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x11", "ExpectedArm64ASM": [ "mov w20, w5", "cset w21, hs", "add w21, w20, w21", "ldaddal w21, w22, [x4]", - "add w21, w22, w21", - "eor w23, w22, w20", - "strb w23, [x28, #708]", - "strb w21, [x28, #706]", + "add w26, w22, w21", + "eor w27, w22, w20", "adcs wzr, w22, w20" ] }, "lock sbb byte [rax], cl": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0x18", "ExpectedArm64ASM": [ "uxtb w20, w5", @@ -181,21 +166,19 @@ "neg w1, w22", "ldaddalb w1, w23, [x4]", "sub w22, w23, w22", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", @@ -203,7 +186,7 @@ ] }, "lock sbb word [rax], cx": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0x19", "ExpectedArm64ASM": [ "uxth w20, w5", @@ -212,21 +195,19 @@ "neg w1, w22", "ldaddalh w1, w23, [x4]", "sub w22, w23, w22", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "ubfx x20, x20, #15, #1", "orr w20, w21, w20, lsl #28", @@ -234,7 +215,7 @@ ] }, "lock sbb dword [rax], ecx": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0x19", "ExpectedArm64ASM": [ "mov w20, w5", @@ -242,10 +223,8 @@ "add w21, w20, w21", "neg w1, w21", "ldaddal w1, w22, [x4]", - "sub w21, w22, w21", - "eor w23, w22, w20", - "strb w23, [x28, #708]", - "strb w21, [x28, #706]", + "sub w26, w22, w21", + "eor w27, w22, w20", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -256,94 +235,85 @@ ] }, "lock and byte [rax], cl": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x20", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclralb w1, w20, [x4]", - "and w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w20, w5", + "cmn wzr, w26, lsl #24" ] }, "lock and word [rax], cx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x21", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclralh w1, w20, [x4]", - "and w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w20, w5", + "cmn wzr, w26, lsl #16" ] }, "lock and dword [rax], ecx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x21", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclral w1, w20, [x4]", - "and w20, w20, w5", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w20, w5", + "tst w26, w26" ] }, "lock sub byte [rax], cl": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x28", "ExpectedArm64ASM": [ "uxtb w20, w5", "neg w1, w20", "ldaddalb w1, w21, [x4]", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "lock sub word [rax], cx": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x28", "ExpectedArm64ASM": [ "uxth w20, w5", "neg w1, w20", "ldaddalh w1, w21, [x4]", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "lock sub dword [rax], ecx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "0x29", "ExpectedArm64ASM": [ "neg w1, w5", "ldaddal w1, w20, [x4]", - "sub w21, w20, w5", - "eor w22, w20, w5", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "sub w26, w20, w5", + "eor w27, w20, w5", "cmp w20, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -351,44 +321,39 @@ ] }, "lock xor byte [rax], cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x30", "ExpectedArm64ASM": [ "ldeoralb w5, w20, [x4]", - "eor w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w20, w5", + "cmn wzr, w26, lsl #24" ] }, "lock xor word [rax], cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x31", "ExpectedArm64ASM": [ "ldeoralh w5, w20, [x4]", - "eor w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w20, w5", + "cmn wzr, w26, lsl #16" ] }, "lock xor dword [rax], ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x31", "ExpectedArm64ASM": [ "ldeoral w5, w20, [x4]", - "eor w20, w20, w5", - "strb w20, [x28, #706]", - "tst w20, w20" + "eor w26, w20, w5", + "tst w26, w26" ] }, "lock add qword [rax], rcx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal x5, x20, [x4]", - "add x21, x20, x5", - "eor x22, x20, x5", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add x26, x20, x5", + "eor x27, x20, x5", "cmn x20, x5" ] }, @@ -430,397 +395,354 @@ ] }, "xadd byte [rax], bl": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w7", "ldaddalb w20, w21, [x4]", "bfxil x7, x21, #0, #8", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "xadd word [rax], bx": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w7", "ldaddalh w20, w21, [x4]", "bfxil x7, x21, #0, #16", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "xadd dword [rax], ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", - "add w21, w7, w20", - "eor w22, w7, w20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add w26, w7, w20", + "eor w27, w7, w20", "cmn w7, w20" ] }, "xadd qword [rax], rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x7", "ldaddal x20, x7, [x4]", - "add x21, x7, x20", - "eor x22, x7, x20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add x26, x7, x20", + "eor x27, x7, x20", "cmn x7, x20" ] }, "lock add byte [rax], 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddalb w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "ldaddalb w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock add byte [rax], 0xFF": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0xff", "ldaddalb w20, w20, [x4]", - "add w21, w20, #0xff (255)", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", + "add w26, w20, #0xff (255)", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "ubfx x22, x26, #8, #1", + "orr w21, w21, w22, lsl #29", + "bic w20, w20, w26", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "lock add word [rax], 0x100": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", - "ldaddalh w20, w20, [x4]", - "add w21, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "ldaddalh w20, w27, [x4]", + "add w26, w27, #0x100 (256)", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock add word [rax], 0xFFFF": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldaddalh w20, w21, [x4]", - "add w20, w21, w20", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x20, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "add w26, w21, w20", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x22, x26, #16, #1", + "orr w20, w20, w22, lsl #29", + "bic w21, w21, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock add dword [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", - "ldaddal w20, w20, [x4]", - "add w21, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn w20, #0x100 (256)" + "ldaddal w20, w27, [x4]", + "add w26, w27, #0x100 (256)", + "cmn w27, #0x100 (256)" ] }, "lock add dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldaddal w20, w21, [x4]", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "add w26, w21, w20", + "eor w27, w21, w20", "cmn w21, w20" ] }, "lock add qword [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", - "ldaddal x20, x20, [x4]", - "add x21, x20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn x20, #0x100 (256)" + "ldaddal x20, x27, [x4]", + "add x26, x27, #0x100 (256)", + "cmn x27, #0x100 (256)" ] }, "lock add qword [rax], -2147483647": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", - "ldaddal x20, x21, [x4]", - "add x22, x21, x20", - "strb w21, [x28, #708]", - "strb w22, [x28, #706]", - "cmn x21, x20" + "ldaddal x20, x27, [x4]", + "add x26, x27, x20", + "cmn x27, x20" ] }, "lock add word [rax], 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddalh w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "ldaddalh w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock add dword [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddal w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn w20, #0x1 (1)" + "ldaddal w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cmn w27, #0x1 (1)" ] }, "lock add qword [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddal x20, x20, [x4]", - "add x21, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn x20, #0x1 (1)" + "ldaddal x20, x27, [x4]", + "add x26, x27, #0x1 (1)", + "cmn x27, #0x1 (1)" ] }, "lock or byte [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetalb w20, w20, [x4]", - "orr w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w20, #0x1", + "cmn wzr, w26, lsl #24" ] }, "lock or byte [rax], 0xFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "mov w20, #0xff", "ldsetalb w20, w20, [x4]", - "orr w20, w20, #0xff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w20, #0xff", + "cmn wzr, w26, lsl #24" ] }, "lock or word [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldsetalh w20, w20, [x4]", - "orr w20, w20, #0x100", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w20, #0x100", + "cmn wzr, w26, lsl #16" ] }, "lock or word [rax], 0xFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldsetalh w20, w20, [x4]", - "orr w20, w20, #0xffff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w20, #0xffff", + "cmn wzr, w26, lsl #16" ] }, "lock or dword [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldsetal w20, w20, [x4]", - "orr w20, w20, #0x100", - "strb w20, [x28, #706]", - "tst w20, w20" + "orr w26, w20, #0x100", + "tst w26, w26" ] }, "lock or dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldsetal w20, w21, [x4]", - "orr w20, w21, w20", - "strb w20, [x28, #706]", - "tst w20, w20" + "orr w26, w21, w20", + "tst w26, w26" ] }, "lock or qword [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldsetal x20, x20, [x4]", - "orr x20, x20, #0x100", - "strb w20, [x28, #706]", - "tst x20, x20" + "orr x26, x20, #0x100", + "tst x26, x26" ] }, "lock or qword [rax], -2147483647": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "ldsetal x20, x20, [x4]", - "orr x20, x20, #0xffffffff80000001", - "strb w20, [x28, #706]", - "tst x20, x20" + "orr x26, x20, #0xffffffff80000001", + "tst x26, x26" ] }, "lock or word [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetalh w20, w20, [x4]", - "orr w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w20, #0x1", + "cmn wzr, w26, lsl #16" ] }, "lock or dword [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetal w20, w20, [x4]", - "orr w20, w20, #0x1", - "strb w20, [x28, #706]", - "tst w20, w20" + "orr w26, w20, #0x1", + "tst w26, w26" ] }, "lock or qword [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetal x20, x20, [x4]", - "orr x20, x20, #0x1", - "strb w20, [x28, #706]", - "tst x20, x20" + "orr x26, x20, #0x1", + "tst x26, x26" ] }, "lock adc byte [rax], 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "ldaddalb w20, w22, [x4]", - "add w20, w22, w20", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0x1 (1)", - "cset x24, lo", - "cmp w20, #0x1 (1)", - "cset x25, ls", + "ldaddalb w20, w27, [x4]", + "add w20, w27, w20", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0x1 (1)", + "cset x22, lo", + "cmp w26, #0x1 (1)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock adc byte [rax], 0xFF": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -828,54 +750,50 @@ "add w20, w20, w21", "ldaddalb w20, w22, [x4]", "add w20, w22, w20", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0xff (255)", - "cset x24, lo", - "cmp w20, #0xff (255)", - "cset x25, ls", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0xff (255)", + "cset x23, lo", + "cmp w26, #0xff (255)", + "cset x24, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w22, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock adc word [rax], 0x100": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w20, w20, w21", - "ldaddalh w20, w22, [x4]", - "add w20, w22, w20", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, #0x100 (256)", - "cset x24, lo", - "cmp w20, #0x100 (256)", - "cset x25, ls", + "ldaddalh w20, w27, [x4]", + "add w20, w27, w20", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, #0x100 (256)", + "cset x22, lo", + "cmp w26, #0x100 (256)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock adc word [rax], 0xFFFF": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -883,167 +801,149 @@ "add w22, w20, w21", "ldaddalh w22, w23, [x4]", "add w22, w23, w22", - "uxth w22, w22", - "eor w24, w23, #0xffff", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", + "uxth w26, w22", + "eor w27, w23, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", "cset x20, ls", "cmp x21, #0x1 (1)", - "csel x20, x20, x25, eq", - "orr w20, w24, w20, lsl #29", - "bic w21, w23, w22", + "csel x20, x20, x24, eq", + "orr w20, w22, w20, lsl #29", + "bic w21, w23, w26", "ubfx x21, x21, #15, #1", "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock adc dword [rax], 0x100": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w21, w20, w21", - "ldaddal w21, w22, [x4]", - "add w21, w22, w21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "adcs wzr, w22, w20" + "ldaddal w21, w27, [x4]", + "add w26, w27, w21", + "adcs wzr, w27, w20" ] }, "lock adc dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "cset w21, hs", "add w21, w20, w21", "ldaddal w21, w22, [x4]", - "add w21, w22, w21", - "eor w23, w22, w20", - "strb w23, [x28, #708]", - "strb w21, [x28, #706]", + "add w26, w22, w21", + "eor w27, w22, w20", "adcs wzr, w22, w20" ] }, "lock adc qword [rax], 0x100": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add x21, x20, x21", - "ldaddal x21, x22, [x4]", - "add x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "adcs xzr, x22, x20" + "ldaddal x21, x27, [x4]", + "add x26, x27, x21", + "adcs xzr, x27, x20" ] }, "lock adc qword [rax], -2147483647": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "cset w21, hs", "add x21, x20, x21", - "ldaddal x21, x22, [x4]", - "add x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "adcs xzr, x22, x20" + "ldaddal x21, x27, [x4]", + "add x26, x27, x21", + "adcs xzr, x27, x20" ] }, "lock adc word [rax], 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "ldaddalh w20, w22, [x4]", - "add w20, w22, w20", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, #0x1 (1)", - "cset x24, lo", - "cmp w20, #0x1 (1)", - "cset x25, ls", + "ldaddalh w20, w27, [x4]", + "add w20, w27, w20", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, #0x1 (1)", + "cset x22, lo", + "cmp w26, #0x1 (1)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock adc dword [rax], 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", - "ldaddal w21, w22, [x4]", - "add w21, w22, w21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "adcs wzr, w22, w20" + "ldaddal w21, w27, [x4]", + "add w26, w27, w21", + "adcs wzr, w27, w20" ] }, "lock adc qword [rax], 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", - "ldaddal x21, x22, [x4]", - "add x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "adcs xzr, x22, x20" + "ldaddal x21, x27, [x4]", + "add x26, x27, x21", + "adcs xzr, x27, x20" ] }, "lock sbb byte [rax], 1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", "neg w1, w20", - "ldaddalb w1, w22, [x4]", - "sub w20, w22, w20", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "ldaddalb w1, w27, [x4]", + "sub w20, w27, w20", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock sbb byte [rax], 0xFF": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -1052,55 +952,51 @@ "neg w1, w20", "ldaddalb w1, w22, [x4]", "sub w20, w22, w20", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w22", + "cset x23, hi", + "cmp w26, w22", + "cset x24, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w22", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock sbb word [rax], 0x100": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w20, w20, w21", "neg w1, w20", - "ldaddalh w1, w22, [x4]", - "sub w20, w22, w20", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "ldaddalh w1, w27, [x4]", + "sub w20, w27, w20", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock sbb word [rax], 0xFFFF": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -1109,48 +1005,44 @@ "neg w1, w20", "ldaddalh w1, w22, [x4]", "sub w20, w22, w20", - "uxth w20, w20", - "eor w23, w22, #0xffff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxth w26, w20", + "eor w27, w22, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, w22", + "cset x23, hi", + "cmp w26, w22", + "cset x24, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w22", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock sbb dword [rax], 0x100": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w21, w20, w21", "neg w1, w21", - "ldaddal w1, w22, [x4]", - "sub w21, w22, w21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "ldaddal w1, w27, [x4]", + "sub w26, w27, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sbb dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", @@ -1158,10 +1050,8 @@ "add w21, w20, w21", "neg w1, w21", "ldaddal w1, w22, [x4]", - "sub w21, w22, w21", - "eor w23, w22, w20", - "strb w23, [x28, #708]", - "strb w21, [x28, #706]", + "sub w26, w22, w21", + "eor w27, w22, w20", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -1172,358 +1062,325 @@ ] }, "lock sbb qword [rax], 0x100": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add x21, x20, x21", "neg x1, x21", - "ldaddal x1, x22, [x4]", - "sub x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "ldaddal x1, x27, [x4]", + "sub x26, x27, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sbb qword [rax], -2147483647": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "cset w21, hs", "add x21, x20, x21", "neg x1, x21", - "ldaddal x1, x22, [x4]", - "sub x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "ldaddal x1, x27, [x4]", + "sub x26, x27, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sbb word [rax], 1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", "neg w1, w20", - "ldaddalh w1, w22, [x4]", - "sub w20, w22, w20", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "ldaddalh w1, w27, [x4]", + "sub w20, w27, w20", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock sbb dword [rax], 1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", "neg w1, w21", - "ldaddal w1, w22, [x4]", - "sub w21, w22, w21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "ldaddal w1, w27, [x4]", + "sub w26, w27, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sbb qword [rax], 1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", "neg x1, x21", - "ldaddal x1, x22, [x4]", - "sub x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "ldaddal x1, x27, [x4]", + "sub x26, x27, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock and byte [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclralb w1, w20, [x4]", - "and w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w20, #0x1", + "cmn wzr, w26, lsl #24" ] }, "lock and byte [rax], 0xFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "mov w20, #0xff", "mvn w1, w20", "ldclralb w1, w20, [x4]", - "and w20, w20, #0xff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w20, #0xff", + "cmn wzr, w26, lsl #24" ] }, "lock and word [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn w1, w20", "ldclralh w1, w20, [x4]", - "and w20, w20, #0x100", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w20, #0x100", + "cmn wzr, w26, lsl #16" ] }, "lock and word [rax], 0xFFFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0xffff", "mvn w1, w20", "ldclralh w1, w20, [x4]", - "and w20, w20, #0xffff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w20, #0xffff", + "cmn wzr, w26, lsl #16" ] }, "lock and dword [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn w1, w20", "ldclral w1, w20, [x4]", - "and w20, w20, #0x100", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w20, #0x100", + "tst w26, w26" ] }, "lock and dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w1, w20", "ldclral w1, w21, [x4]", - "and w20, w21, w20", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w21, w20", + "tst w26, w26" ] }, "lock and qword [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn x1, x20", "ldclral x1, x20, [x4]", - "and x20, x20, #0x100", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x20, #0x100", + "tst x26, x26" ] }, "lock and qword [rax], -2147483647": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "mvn x1, x20", "ldclral x1, x20, [x4]", - "and x20, x20, #0xffffffff80000001", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x20, #0xffffffff80000001", + "tst x26, x26" ] }, "lock and word [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclralh w1, w20, [x4]", - "and w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w20, #0x1", + "cmn wzr, w26, lsl #16" ] }, "lock and dword [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclral w1, w20, [x4]", - "and w20, w20, #0x1", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w20, #0x1", + "tst w26, w26" ] }, "lock and qword [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn x1, x20", "ldclral x1, x20, [x4]", - "and x20, x20, #0x1", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x20, #0x1", + "tst x26, x26" ] }, "lock sub byte [rax], 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddalb w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "ldaddalb w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock sub byte [rax], 0xFF": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0xff", "neg w1, w20", "ldaddalb w1, w20, [x4]", - "sub w21, w20, #0xff (255)", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", + "sub w26, w20, #0xff (255)", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "ubfx x22, x26, #8, #1", + "orr w21, w21, w22, lsl #29", + "bic w20, w26, w20", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "lock sub word [rax], 0x100": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg w1, w20", - "ldaddalh w1, w20, [x4]", - "sub w21, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "ldaddalh w1, w27, [x4]", + "sub w26, w27, #0x100 (256)", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock sub word [rax], 0xFFFF": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffff", "neg w1, w20", "ldaddalh w1, w21, [x4]", - "sub w20, w21, w20", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x20, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "sub w26, w21, w20", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x22, x26, #16, #1", + "orr w20, w20, w22, lsl #29", + "bic w21, w26, w21", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock sub dword [rax], 0x100": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg w1, w20", - "ldaddal w1, w20, [x4]", - "sub w21, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp w20, #0x100 (256)", + "ldaddal w1, w27, [x4]", + "sub w26, w27, #0x100 (256)", + "cmp w27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "neg w1, w20", "ldaddal w1, w21, [x4]", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1531,227 +1388,204 @@ ] }, "lock sub qword [rax], 0x100": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg x1, x20", - "ldaddal x1, x20, [x4]", - "sub x21, x20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp x20, #0x100 (256)", + "ldaddal x1, x27, [x4]", + "sub x26, x27, #0x100 (256)", + "cmp x27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub qword [rax], -2147483647": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "neg x1, x20", - "ldaddal x1, x21, [x4]", - "sub x22, x21, x20", - "strb w21, [x28, #708]", - "strb w22, [x28, #706]", - "cmp x21, x20", + "ldaddal x1, x27, [x4]", + "sub x26, x27, x20", + "cmp x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub word [rax], 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddalh w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "ldaddalh w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock sub dword [rax], 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddal w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp w20, #0x1 (1)", + "ldaddal w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cmp w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock sub qword [rax], 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg x1, x20", - "ldaddal x1, x20, [x4]", - "sub x21, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp x20, #0x1 (1)", + "ldaddal x1, x27, [x4]", + "sub x26, x27, #0x1 (1)", + "cmp x27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock xor byte [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoralb w20, w20, [x4]", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w20, #0x1", + "cmn wzr, w26, lsl #24" ] }, "lock xor byte [rax], 0xFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "mov w20, #0xff", "ldeoralb w20, w20, [x4]", - "eor w20, w20, #0xff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w20, #0xff", + "cmn wzr, w26, lsl #24" ] }, "lock xor word [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldeoralh w20, w20, [x4]", - "eor w20, w20, #0x100", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w20, #0x100", + "cmn wzr, w26, lsl #16" ] }, "lock xor word [rax], 0xFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldeoralh w20, w20, [x4]", - "eor w20, w20, #0xffff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w20, #0xffff", + "cmn wzr, w26, lsl #16" ] }, "lock xor dword [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldeoral w20, w20, [x4]", - "eor w20, w20, #0x100", - "strb w20, [x28, #706]", - "tst w20, w20" + "eor w26, w20, #0x100", + "tst w26, w26" ] }, "lock xor dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldeoral w20, w21, [x4]", - "eor w20, w21, w20", - "strb w20, [x28, #706]", - "tst w20, w20" + "eor w26, w21, w20", + "tst w26, w26" ] }, "lock xor qword [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldeoral x20, x20, [x4]", - "eor x20, x20, #0x100", - "strb w20, [x28, #706]", - "tst x20, x20" + "eor x26, x20, #0x100", + "tst x26, x26" ] }, "lock xor qword [rax], -2147483647": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "ldeoral x20, x20, [x4]", - "eor x20, x20, #0xffffffff80000001", - "strb w20, [x28, #706]", - "tst x20, x20" + "eor x26, x20, #0xffffffff80000001", + "tst x26, x26" ] }, "lock xor word [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoralh w20, w20, [x4]", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w20, #0x1", + "cmn wzr, w26, lsl #16" ] }, "lock xor dword [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoral w20, w20, [x4]", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", - "tst w20, w20" + "eor w26, w20, #0x1", + "tst w26, w26" ] }, "lock xor qword [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoral x20, x20, [x4]", - "eor x20, x20, #0x1", - "strb w20, [x28, #706]", - "tst x20, x20" + "eor x26, x20, #0x1", + "tst x26, x26" ] }, "lock dec byte [rax]": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "GROUP3 0xfe /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddalb w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #24", - "mrs x23, nzcv", - "bic w20, w20, w21", - "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", - "orr w20, w20, w22, lsl #29", + "ldaddalb w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cset w20, hs", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "bic w22, w27, w26", + "ubfx x22, x22, #7, #1", + "orr w21, w21, w22, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, @@ -1788,102 +1622,92 @@ ] }, "lock neg byte [rax]": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ "ldaxrb w1, [x4]", "neg w2, w1", "stlxrb w3, w2, [x4]", "cbnz w3, #-0xc", - "mov w20, w1", - "neg w21, w20", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "and w20, w21, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "mov w27, w1", + "neg w26, w27", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", + "and w21, w26, w27", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock neg word [rax]": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxrh w1, [x4]", "neg w2, w1", "stlxrh w3, w2, [x4]", "cbnz w3, #-0xc", - "mov w20, w1", - "neg w21, w20", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "and w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "mov w27, w1", + "neg w26, w27", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "and w21, w26, w27", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "lock neg dword [rax]": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr w1, [x4]", "neg w2, w1", "stlxr w3, w2, [x4]", "cbnz w3, #-0xc", - "mov w20, w1", - "neg w21, w20", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp wzr, w20", + "mov w27, w1", + "neg w26, w27", + "cmp wzr, w27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock neg qword [rax]": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr x1, [x4]", "neg x2, x1", "stlxr w3, x2, [x4]", "cbnz x3, #-0xc", - "mov x20, x1", - "neg x21, x20", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp xzr, x20", + "mov x27, x1", + "neg x26, x27", + "cmp xzr, x27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "lock dec word [rax]": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddalh w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #16", - "mrs x23, nzcv", - "bic w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", - "orr w20, w20, w22, lsl #29", + "ldaddalh w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cset w20, hs", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", + "bic w22, w27, w26", + "ubfx x22, x22, #15, #1", + "orr w21, w21, w22, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, @@ -1893,14 +1717,14 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddal w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w21, hs", - "cmp w20, #0x1 (1)", - "mrs x20, nzcv", - "bfi w20, w21, #29, #1", + "ldaddal w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cset w20, hs", + "cmp w27, #0x1 (1)", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, @@ -1910,52 +1734,48 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "neg x1, x20", - "ldaddal x1, x20, [x4]", - "sub x21, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w21, hs", - "cmp x20, #0x1 (1)", - "mrs x20, nzcv", - "bfi w20, w21, #29, #1", + "ldaddal x1, x27, [x4]", + "sub x26, x27, #0x1 (1)", + "cset w20, hs", + "cmp x27, #0x1 (1)", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "lock inc byte [rax]": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddalb w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #24", - "mrs x23, nzcv", - "bic w20, w21, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", - "orr w20, w20, w22, lsl #29", + "ldaddalb w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cset w20, hs", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "bic w22, w26, w27", + "ubfx x22, x22, #7, #1", + "orr w21, w21, w22, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, "lock inc word [rax]": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddalh w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #16", - "mrs x23, nzcv", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", - "orr w20, w20, w22, lsl #29", + "ldaddalh w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cset w20, hs", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", + "bic w22, w26, w27", + "ubfx x22, x22, #15, #1", + "orr w21, w21, w22, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, @@ -1964,14 +1784,14 @@ "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddal w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w21, hs", - "cmn w20, #0x1 (1)", - "mrs x20, nzcv", - "bfi w20, w21, #29, #1", + "ldaddal w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cset w20, hs", + "cmn w27, #0x1 (1)", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, @@ -1980,14 +1800,14 @@ "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddal x20, x20, [x4]", - "add x21, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w21, hs", - "cmn x20, #0x1 (1)", - "mrs x20, nzcv", - "bfi w20, w21, #29, #1", + "ldaddal x20, x27, [x4]", + "add x26, x27, #0x1 (1)", + "cset w20, hs", + "cmn x27, #0x1 (1)", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] } diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index a35ce5a29..28d7f326e 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -55,7 +55,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2064]", + "ldr q2, [x28, #2080]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", @@ -68,7 +68,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2064]", + "ldr q2, [x28, #2080]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json index 2717d7b40..d73d5630a 100644 --- a/unittests/InstructionCountCI/DDD.json +++ b/unittests/InstructionCountCI/DDD.json @@ -20,11 +20,11 @@ "0x0f 0x0f 0x0c" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "uzp1 v2.4h, v2.4h, v2.4h", "sxtl v2.4s, v2.4h", "scvtf v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pi2fd mm0, mm1": { @@ -33,9 +33,9 @@ "0x0f 0x0f 0x0d" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "scvtf v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pf2iw mm0, mm1": { @@ -44,11 +44,11 @@ "0x0f 0x0f 0x1c" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "fcvtzs v2.2s, v2.2s", "uzp1 v2.4h, v2.4h, v2.4h", "sxtl v2.4s, v2.4h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pf2id mm0, mm1": { @@ -57,9 +57,9 @@ "0x0f 0x0f 0x1d" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "fcvtzs v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfrcpv mm0, mm1": { @@ -68,10 +68,10 @@ "0x0f 0x0f 0x86" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "fmov v0.4s, #0x70 (1.0000)", "fdiv v2.4s, v0.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfrsqrtv mm0, mm1": { @@ -80,57 +80,57 @@ "0x0f 0x0f 0x87" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "fmov v0.4s, #0x70 (1.0000)", "fsqrt v1.4s, v2.4s", "fdiv v2.4s, v0.4s, v1.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfnacc mm0, mm1": { "ExpectedInstructionCount": 6, "Comment": "0x0f 0x0f 0x8a", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uzp1 v4.2s, v2.2s, v3.2s", "uzp2 v2.2s, v2.2s, v3.2s", "fsub v2.4s, v4.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfpnacc mm0, mm1": { "ExpectedInstructionCount": 7, "Comment": "0x0f 0x0f 0x8e", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "dup v4.2s, v2.s[1]", "fsub s2, s2, s4", "faddp v3.4s, v3.4s, v3.4s", "mov v2.s[1], v3.s[0]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfcmpge mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x0f 0x90", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "fcmge v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfmin mm0, mm1": { "ExpectedInstructionCount": 5, "Comment": "0x0f 0x0f 0x94", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "fcmgt v0.4s, v3.4s, v2.4s", "bif v2.16b, v3.16b, v0.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfrcp mm0, mm1": { @@ -139,11 +139,11 @@ "0x0f 0x0f 0x96" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "fmov s0, #0x70 (1.0000)", "fdiv s2, s0, s2", "dup v2.2s, v2.s[0]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfrsqrt mm0, mm1": { @@ -152,61 +152,61 @@ "0x0f 0x0f 0x97" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "fmov s0, #0x70 (1.0000)", "fsqrt s1, s2", "fdiv s2, s0, s1", "dup v2.2s, v2.s[0]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfsub mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x0f 0x9a", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "fsub v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfadd mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x0f 0x9e", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "fadd v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfcmpgt mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x0f 0xa0", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "fcmgt v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfmax mm0, mm1": { "ExpectedInstructionCount": 5, "Comment": "0x0f 0x0f 0xa4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "fcmgt v0.4s, v3.4s, v2.4s", "bit v2.16b, v3.16b, v0.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfrcpit1 mm0, mm1": { "ExpectedInstructionCount": 2, "Comment": "0x0f 0x0f 0xa6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "str d2, [x28, #752]" + "ldr d2, [x28, #784]", + "str d2, [x28, #768]" ] }, "pfrcpit1 mm0, mm0": { @@ -218,8 +218,8 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0x0f 0xa7", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "str d2, [x28, #752]" + "ldr d2, [x28, #784]", + "str d2, [x28, #768]" ] }, "pfrsqit1 mm0, mm0": { @@ -231,38 +231,38 @@ "ExpectedInstructionCount": 4, "Comment": "0x0f 0x0f 0xaa", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "fsub v2.4s, v2.4s, v3.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfcmpeq mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x0f 0xb0", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "fcmeq v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfmul mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x0f 0xb4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "fmul v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfrcpit2 mm0, mm1": { "ExpectedInstructionCount": 2, "Comment": "0x0f 0x0f 0xb6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "str d2, [x28, #752]" + "ldr d2, [x28, #784]", + "str d2, [x28, #768]" ] }, "pfrcpit2 mm0, mm0": { @@ -278,32 +278,32 @@ "0x0f 0x0f 0xb7" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "smull v2.4s, v2.4h, v3.4h", "movi v3.4s, #0x80, lsl #8", "add v2.4s, v2.4s, v3.4s", "shrn v2.4h, v2.4s, #16", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pswapd mm0, mm1": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0x0f 0xbb", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "rev64 v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pavgusb mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x0f 0xbf", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "urhadd v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] } } diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index d22b4de5d..c38cd0311 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -12,85 +12,76 @@ }, "Instructions": { "lock add byte [rax], cl": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0x00", "ExpectedArm64ASM": [ "uxtb w20, w5", "ldaddalb w20, w21, [x4]", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "lock add word [rax], cx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0x01", "ExpectedArm64ASM": [ "uxth w20, w5", "ldaddalh w20, w21, [x4]", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "lock add dword [rax], ecx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal w5, w20, [x4]", - "add w21, w20, w5", - "eor w22, w20, w5", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add w26, w20, w5", + "eor w27, w20, w5", "cmn w20, w5" ] }, "lock or byte [rax], cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x08", "ExpectedArm64ASM": [ "ldsetalb w5, w20, [x4]", - "orr w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w20, w5", + "cmn wzr, w26, lsl #24" ] }, "lock or word [rax], cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x09", "ExpectedArm64ASM": [ "ldsetalh w5, w20, [x4]", - "orr w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w20, w5", + "cmn wzr, w26, lsl #16" ] }, "lock or dword [rax], ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x09", "ExpectedArm64ASM": [ "ldsetal w5, w20, [x4]", - "orr w20, w20, w5", - "strb w20, [x28, #706]", - "tst w20, w20" + "orr w26, w20, w5", + "tst w26, w26" ] }, "lock adc byte [rax], cl": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "0x10", "ExpectedArm64ASM": [ "uxtb w20, w5", @@ -98,28 +89,26 @@ "add w22, w20, w21", "ldaddalb w22, w23, [x4]", "add w22, w23, w22", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "msr nzcv, x21", "rmif x20, #7, #nzcV" ] }, "lock adc word [rax], cx": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "0x11", "ExpectedArm64ASM": [ "uxth w20, w5", @@ -127,43 +116,39 @@ "add w22, w20, w21", "ldaddalh w22, w23, [x4]", "add w22, w23, w22", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "msr nzcv, x21", "rmif x20, #15, #nzcV" ] }, "lock adc dword [rax], ecx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x11", "ExpectedArm64ASM": [ "mov w20, w5", "cset w21, hs", "add w21, w20, w21", "ldaddal w21, w22, [x4]", - "add w21, w22, w21", - "eor w23, w22, w20", - "strb w23, [x28, #708]", - "strb w21, [x28, #706]", + "add w26, w22, w21", + "eor w27, w22, w20", "adcs wzr, w22, w20" ] }, "lock sbb byte [rax], cl": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0x18", "ExpectedArm64ASM": [ "uxtb w20, w5", @@ -172,28 +157,26 @@ "neg w1, w22", "ldaddalb w1, w23, [x4]", "sub w22, w23, w22", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "msr nzcv, x21", "rmif x20, #7, #nzcV" ] }, "lock sbb word [rax], cx": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0x19", "ExpectedArm64ASM": [ "uxth w20, w5", @@ -202,28 +185,26 @@ "neg w1, w22", "ldaddalh w1, w23, [x4]", "sub w22, w23, w22", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "msr nzcv, x21", "rmif x20, #15, #nzcV" ] }, "lock sbb dword [rax], ecx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0x19", "ExpectedArm64ASM": [ "mov w20, w5", @@ -231,505 +212,446 @@ "add w21, w20, w21", "neg w1, w21", "ldaddal w1, w22, [x4]", - "sub w21, w22, w21", - "eor w23, w22, w20", - "strb w23, [x28, #708]", - "strb w21, [x28, #706]", + "sub w26, w22, w21", + "eor w27, w22, w20", "cfinv", "sbcs wzr, w22, w20", "cfinv" ] }, "lock and byte [rax], cl": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x20", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclralb w1, w20, [x4]", - "and w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w20, w5", + "cmn wzr, w26, lsl #24" ] }, "lock and word [rax], cx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x21", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclralh w1, w20, [x4]", - "and w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w20, w5", + "cmn wzr, w26, lsl #16" ] }, "lock and dword [rax], ecx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x21", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclral w1, w20, [x4]", - "and w20, w20, w5", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w20, w5", + "tst w26, w26" ] }, "lock sub byte [rax], cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x28", "ExpectedArm64ASM": [ "uxtb w20, w5", "neg w1, w20", "ldaddalb w1, w21, [x4]", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "lock sub word [rax], cx": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x28", "ExpectedArm64ASM": [ "uxth w20, w5", "neg w1, w20", "ldaddalh w1, w21, [x4]", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "lock sub dword [rax], ecx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x29", "ExpectedArm64ASM": [ "neg w1, w5", "ldaddal w1, w20, [x4]", - "sub w21, w20, w5", - "eor w22, w20, w5", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "sub w26, w20, w5", + "eor w27, w20, w5", "cmp w20, w5", "cfinv" ] }, "lock xor byte [rax], cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x30", "ExpectedArm64ASM": [ "ldeoralb w5, w20, [x4]", - "eor w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w20, w5", + "cmn wzr, w26, lsl #24" ] }, "lock xor word [rax], cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x31", "ExpectedArm64ASM": [ "ldeoralh w5, w20, [x4]", - "eor w20, w20, w5", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w20, w5", + "cmn wzr, w26, lsl #16" ] }, "lock xor dword [rax], ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x31", "ExpectedArm64ASM": [ "ldeoral w5, w20, [x4]", - "eor w20, w20, w5", - "strb w20, [x28, #706]", - "tst w20, w20" + "eor w26, w20, w5", + "tst w26, w26" ] }, "lock add qword [rax], rcx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal x5, x20, [x4]", - "add x21, x20, x5", - "eor x22, x20, x5", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add x26, x20, x5", + "eor x27, x20, x5", "cmn x20, x5" ] }, "xadd byte [rax], bl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w7", "ldaddalb w20, w21, [x4]", "bfxil x7, x21, #0, #8", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "xadd word [rax], bx": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w7", "ldaddalh w20, w21, [x4]", "bfxil x7, x21, #0, #16", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "xadd dword [rax], ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", - "add w21, w7, w20", - "eor w22, w7, w20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add w26, w7, w20", + "eor w27, w7, w20", "cmn w7, w20" ] }, "xadd qword [rax], rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x7", "ldaddal x20, x7, [x4]", - "add x21, x7, x20", - "eor x22, x7, x20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add x26, x7, x20", + "eor x27, x7, x20", "cmn x7, x20" ] }, "lock add byte [rax], 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddalb w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w21, w20", + "ldaddalb w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w26, w27", "rmif x20, #7, #nzcV" ] }, "lock add byte [rax], 0xFF": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0xff", "ldaddalb w20, w20, [x4]", - "add w21, w20, #0xff (255)", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w20, w21", + "add w26, w20, #0xff (255)", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w20, w26", "rmif x20, #7, #nzcV" ] }, "lock add word [rax], 0x100": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", - "ldaddalh w20, w20, [x4]", - "add w21, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "bic w20, w21, w20", + "ldaddalh w20, w27, [x4]", + "add w26, w27, #0x100 (256)", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w26, w27", "rmif x20, #15, #nzcV" ] }, "lock add word [rax], 0xFFFF": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldaddalh w20, w21, [x4]", - "add w20, w21, w20", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "rmif x20, #15, #nzCv", - "bic w20, w21, w20", + "add w26, w21, w20", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w21, w26", "rmif x20, #15, #nzcV" ] }, "lock add dword [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", - "ldaddal w20, w20, [x4]", - "add w21, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn w20, #0x100 (256)" + "ldaddal w20, w27, [x4]", + "add w26, w27, #0x100 (256)", + "cmn w27, #0x100 (256)" ] }, "lock add dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldaddal w20, w21, [x4]", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "add w26, w21, w20", + "eor w27, w21, w20", "cmn w21, w20" ] }, "lock add qword [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", - "ldaddal x20, x20, [x4]", - "add x21, x20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn x20, #0x100 (256)" + "ldaddal x20, x27, [x4]", + "add x26, x27, #0x100 (256)", + "cmn x27, #0x100 (256)" ] }, "lock add qword [rax], -2147483647": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", - "ldaddal x20, x21, [x4]", - "add x22, x21, x20", - "strb w21, [x28, #708]", - "strb w22, [x28, #706]", - "cmn x21, x20" + "ldaddal x20, x27, [x4]", + "add x26, x27, x20", + "cmn x27, x20" ] }, "lock add word [rax], 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddalh w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "bic w20, w21, w20", + "ldaddalh w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w26, w27", "rmif x20, #15, #nzcV" ] }, "lock add dword [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddal w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn w20, #0x1 (1)" + "ldaddal w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cmn w27, #0x1 (1)" ] }, "lock add qword [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddal x20, x20, [x4]", - "add x21, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn x20, #0x1 (1)" + "ldaddal x20, x27, [x4]", + "add x26, x27, #0x1 (1)", + "cmn x27, #0x1 (1)" ] }, "lock or byte [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetalb w20, w20, [x4]", - "orr w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w20, #0x1", + "cmn wzr, w26, lsl #24" ] }, "lock or byte [rax], 0xFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "mov w20, #0xff", "ldsetalb w20, w20, [x4]", - "orr w20, w20, #0xff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w20, #0xff", + "cmn wzr, w26, lsl #24" ] }, "lock or word [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldsetalh w20, w20, [x4]", - "orr w20, w20, #0x100", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w20, #0x100", + "cmn wzr, w26, lsl #16" ] }, "lock or word [rax], 0xFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldsetalh w20, w20, [x4]", - "orr w20, w20, #0xffff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w20, #0xffff", + "cmn wzr, w26, lsl #16" ] }, "lock or dword [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldsetal w20, w20, [x4]", - "orr w20, w20, #0x100", - "strb w20, [x28, #706]", - "tst w20, w20" + "orr w26, w20, #0x100", + "tst w26, w26" ] }, "lock or dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldsetal w20, w21, [x4]", - "orr w20, w21, w20", - "strb w20, [x28, #706]", - "tst w20, w20" + "orr w26, w21, w20", + "tst w26, w26" ] }, "lock or qword [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldsetal x20, x20, [x4]", - "orr x20, x20, #0x100", - "strb w20, [x28, #706]", - "tst x20, x20" + "orr x26, x20, #0x100", + "tst x26, x26" ] }, "lock or qword [rax], -2147483647": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "ldsetal x20, x20, [x4]", - "orr x20, x20, #0xffffffff80000001", - "strb w20, [x28, #706]", - "tst x20, x20" + "orr x26, x20, #0xffffffff80000001", + "tst x26, x26" ] }, "lock or word [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetalh w20, w20, [x4]", - "orr w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w20, #0x1", + "cmn wzr, w26, lsl #16" ] }, "lock or dword [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetal w20, w20, [x4]", - "orr w20, w20, #0x1", - "strb w20, [x28, #706]", - "tst w20, w20" + "orr w26, w20, #0x1", + "tst w26, w26" ] }, "lock or qword [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetal x20, x20, [x4]", - "orr x20, x20, #0x1", - "strb w20, [x28, #706]", - "tst x20, x20" + "orr x26, x20, #0x1", + "tst x26, x26" ] }, "lock adc byte [rax], 1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "ldaddalb w20, w22, [x4]", - "add w20, w22, w20", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0x1 (1)", - "cset x24, lo", - "cmp w20, #0x1 (1)", - "cset x25, ls", + "ldaddalb w20, w27, [x4]", + "add w20, w27, w20", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0x1 (1)", + "cset x22, lo", + "cmp w26, #0x1 (1)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "lock adc byte [rax], 0xFF": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -737,52 +659,48 @@ "add w20, w20, w21", "ldaddalb w20, w22, [x4]", "add w20, w22, w20", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0xff (255)", - "cset x24, lo", - "cmp w20, #0xff (255)", - "cset x25, ls", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0xff (255)", + "cset x23, lo", + "cmp w26, #0xff (255)", + "cset x24, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w22, w26", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "lock adc word [rax], 0x100": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w20, w20, w21", - "ldaddalh w20, w22, [x4]", - "add w20, w22, w20", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, #0x100 (256)", - "cset x24, lo", - "cmp w20, #0x100 (256)", - "cset x25, ls", + "ldaddalh w20, w27, [x4]", + "add w20, w27, w20", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, #0x100 (256)", + "cset x22, lo", + "cmp w26, #0x100 (256)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #15, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "msr nzcv, x20", + "rmif x21, #15, #nzcV" ] }, "lock adc word [rax], 0xFFFF": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -790,164 +708,146 @@ "add w22, w20, w21", "ldaddalh w22, w23, [x4]", "add w22, w23, w22", - "uxth w22, w22", - "eor w24, w23, #0xffff", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", + "uxth w26, w22", + "eor w27, w23, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", "cset x20, ls", "cmp x21, #0x1 (1)", - "csel x20, x20, x25, eq", - "orr w20, w24, w20, lsl #29", - "bic w21, w23, w22", + "csel x20, x20, x24, eq", + "orr w20, w22, w20, lsl #29", + "bic w21, w23, w26", "msr nzcv, x20", "rmif x21, #15, #nzcV" ] }, "lock adc dword [rax], 0x100": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w21, w20, w21", - "ldaddal w21, w22, [x4]", - "add w21, w22, w21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "adcs wzr, w22, w20" + "ldaddal w21, w27, [x4]", + "add w26, w27, w21", + "adcs wzr, w27, w20" ] }, "lock adc dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "cset w21, hs", "add w21, w20, w21", "ldaddal w21, w22, [x4]", - "add w21, w22, w21", - "eor w23, w22, w20", - "strb w23, [x28, #708]", - "strb w21, [x28, #706]", + "add w26, w22, w21", + "eor w27, w22, w20", "adcs wzr, w22, w20" ] }, "lock adc qword [rax], 0x100": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add x21, x20, x21", - "ldaddal x21, x22, [x4]", - "add x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "adcs xzr, x22, x20" + "ldaddal x21, x27, [x4]", + "add x26, x27, x21", + "adcs xzr, x27, x20" ] }, "lock adc qword [rax], -2147483647": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "cset w21, hs", "add x21, x20, x21", - "ldaddal x21, x22, [x4]", - "add x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "adcs xzr, x22, x20" + "ldaddal x21, x27, [x4]", + "add x26, x27, x21", + "adcs xzr, x27, x20" ] }, "lock adc word [rax], 1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "ldaddalh w20, w22, [x4]", - "add w20, w22, w20", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, #0x1 (1)", - "cset x24, lo", - "cmp w20, #0x1 (1)", - "cset x25, ls", + "ldaddalh w20, w27, [x4]", + "add w20, w27, w20", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, #0x1 (1)", + "cset x22, lo", + "cmp w26, #0x1 (1)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #15, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "msr nzcv, x20", + "rmif x21, #15, #nzcV" ] }, "lock adc dword [rax], 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", - "ldaddal w21, w22, [x4]", - "add w21, w22, w21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "adcs wzr, w22, w20" + "ldaddal w21, w27, [x4]", + "add w26, w27, w21", + "adcs wzr, w27, w20" ] }, "lock adc qword [rax], 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", - "ldaddal x21, x22, [x4]", - "add x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "adcs xzr, x22, x20" + "ldaddal x21, x27, [x4]", + "add x26, x27, x21", + "adcs xzr, x27, x20" ] }, "lock sbb byte [rax], 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", "neg w1, w20", - "ldaddalb w1, w22, [x4]", - "sub w20, w22, w20", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "ldaddalb w1, w27, [x4]", + "sub w20, w27, w20", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "lock sbb byte [rax], 0xFF": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -956,53 +856,49 @@ "neg w1, w20", "ldaddalb w1, w22, [x4]", "sub w20, w22, w20", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w22", + "cset x23, hi", + "cmp w26, w22", + "cset x24, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w22", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "lock sbb word [rax], 0x100": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w20, w20, w21", "neg w1, w20", - "ldaddalh w1, w22, [x4]", - "sub w20, w22, w20", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "ldaddalh w1, w27, [x4]", + "sub w20, w27, w20", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "msr nzcv, x21", - "rmif x20, #15, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "msr nzcv, x20", + "rmif x21, #15, #nzcV" ] }, "lock sbb word [rax], 0xFFFF": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -1011,43 +907,39 @@ "neg w1, w20", "ldaddalh w1, w22, [x4]", "sub w20, w22, w20", - "uxth w20, w20", - "eor w23, w22, #0xffff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxth w26, w20", + "eor w27, w22, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, w22", + "cset x23, hi", + "cmp w26, w22", + "cset x24, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #15, #nzcV" + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w22", + "msr nzcv, x20", + "rmif x21, #15, #nzcV" ] }, "lock sbb dword [rax], 0x100": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w21, w20, w21", "neg w1, w21", - "ldaddal w1, w22, [x4]", - "sub w21, w22, w21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "ldaddal w1, w27, [x4]", + "sub w26, w27, w21", "cfinv", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "cfinv" ] }, "lock sbb dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", @@ -1055,545 +947,487 @@ "add w21, w20, w21", "neg w1, w21", "ldaddal w1, w22, [x4]", - "sub w21, w22, w21", - "eor w23, w22, w20", - "strb w23, [x28, #708]", - "strb w21, [x28, #706]", + "sub w26, w22, w21", + "eor w27, w22, w20", "cfinv", "sbcs wzr, w22, w20", "cfinv" ] }, "lock sbb qword [rax], 0x100": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add x21, x20, x21", "neg x1, x21", - "ldaddal x1, x22, [x4]", - "sub x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "ldaddal x1, x27, [x4]", + "sub x26, x27, x21", "cfinv", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "cfinv" ] }, "lock sbb qword [rax], -2147483647": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "cset w21, hs", "add x21, x20, x21", "neg x1, x21", - "ldaddal x1, x22, [x4]", - "sub x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "ldaddal x1, x27, [x4]", + "sub x26, x27, x21", "cfinv", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "cfinv" ] }, "lock sbb word [rax], 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", "neg w1, w20", - "ldaddalh w1, w22, [x4]", - "sub w20, w22, w20", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "ldaddalh w1, w27, [x4]", + "sub w20, w27, w20", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "msr nzcv, x21", - "rmif x20, #15, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "msr nzcv, x20", + "rmif x21, #15, #nzcV" ] }, "lock sbb dword [rax], 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", "neg w1, w21", - "ldaddal w1, w22, [x4]", - "sub w21, w22, w21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "ldaddal w1, w27, [x4]", + "sub w26, w27, w21", "cfinv", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "cfinv" ] }, "lock sbb qword [rax], 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", "neg x1, x21", - "ldaddal x1, x22, [x4]", - "sub x21, x22, x21", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "ldaddal x1, x27, [x4]", + "sub x26, x27, x21", "cfinv", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "cfinv" ] }, "lock and byte [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclralb w1, w20, [x4]", - "and w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w20, #0x1", + "cmn wzr, w26, lsl #24" ] }, "lock and byte [rax], 0xFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "mov w20, #0xff", "mvn w1, w20", "ldclralb w1, w20, [x4]", - "and w20, w20, #0xff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w20, #0xff", + "cmn wzr, w26, lsl #24" ] }, "lock and word [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn w1, w20", "ldclralh w1, w20, [x4]", - "and w20, w20, #0x100", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w20, #0x100", + "cmn wzr, w26, lsl #16" ] }, "lock and word [rax], 0xFFFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0xffff", "mvn w1, w20", "ldclralh w1, w20, [x4]", - "and w20, w20, #0xffff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w20, #0xffff", + "cmn wzr, w26, lsl #16" ] }, "lock and dword [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn w1, w20", "ldclral w1, w20, [x4]", - "and w20, w20, #0x100", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w20, #0x100", + "tst w26, w26" ] }, "lock and dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w1, w20", "ldclral w1, w21, [x4]", - "and w20, w21, w20", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w21, w20", + "tst w26, w26" ] }, "lock and qword [rax], 0x100": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn x1, x20", "ldclral x1, x20, [x4]", - "and x20, x20, #0x100", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x20, #0x100", + "tst x26, x26" ] }, "lock and qword [rax], -2147483647": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "mvn x1, x20", "ldclral x1, x20, [x4]", - "and x20, x20, #0xffffffff80000001", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x20, #0xffffffff80000001", + "tst x26, x26" ] }, "lock and word [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclralh w1, w20, [x4]", - "and w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w20, #0x1", + "cmn wzr, w26, lsl #16" ] }, "lock and dword [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclral w1, w20, [x4]", - "and w20, w20, #0x1", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w20, #0x1", + "tst w26, w26" ] }, "lock and qword [rax], 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn x1, x20", "ldclral x1, x20, [x4]", - "and x20, x20, #0x1", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x20, #0x1", + "tst x26, x26" ] }, "lock sub byte [rax], 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddalb w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w20, w21", + "ldaddalb w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w27, w26", "rmif x20, #7, #nzcV" ] }, "lock sub byte [rax], 0xFF": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0xff", "neg w1, w20", "ldaddalb w1, w20, [x4]", - "sub w21, w20, #0xff (255)", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w21, w20", + "sub w26, w20, #0xff (255)", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w26, w20", "rmif x20, #7, #nzcV" ] }, "lock sub word [rax], 0x100": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg w1, w20", - "ldaddalh w1, w20, [x4]", - "sub w21, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "bic w20, w20, w21", + "ldaddalh w1, w27, [x4]", + "sub w26, w27, #0x100 (256)", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w27, w26", "rmif x20, #15, #nzcV" ] }, "lock sub word [rax], 0xFFFF": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffff", "neg w1, w20", "ldaddalh w1, w21, [x4]", - "sub w20, w21, w20", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "rmif x20, #15, #nzCv", - "bic w20, w20, w21", + "sub w26, w21, w20", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w26, w21", "rmif x20, #15, #nzcV" ] }, "lock sub dword [rax], 0x100": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg w1, w20", - "ldaddal w1, w20, [x4]", - "sub w21, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp w20, #0x100 (256)", + "ldaddal w1, w27, [x4]", + "sub w26, w27, #0x100 (256)", + "cmp w27, #0x100 (256)", "cfinv" ] }, "lock sub dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "neg w1, w20", "ldaddal w1, w21, [x4]", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "cfinv" ] }, "lock sub qword [rax], 0x100": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg x1, x20", - "ldaddal x1, x20, [x4]", - "sub x21, x20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp x20, #0x100 (256)", + "ldaddal x1, x27, [x4]", + "sub x26, x27, #0x100 (256)", + "cmp x27, #0x100 (256)", "cfinv" ] }, "lock sub qword [rax], -2147483647": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "neg x1, x20", - "ldaddal x1, x21, [x4]", - "sub x22, x21, x20", - "strb w21, [x28, #708]", - "strb w22, [x28, #706]", - "cmp x21, x20", + "ldaddal x1, x27, [x4]", + "sub x26, x27, x20", + "cmp x27, x20", "cfinv" ] }, "lock sub word [rax], 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddalh w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "bic w20, w20, w21", + "ldaddalh w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w27, w26", "rmif x20, #15, #nzcV" ] }, "lock sub dword [rax], 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddal w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp w20, #0x1 (1)", + "ldaddal w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cmp w27, #0x1 (1)", "cfinv" ] }, "lock sub qword [rax], 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg x1, x20", - "ldaddal x1, x20, [x4]", - "sub x21, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp x20, #0x1 (1)", + "ldaddal x1, x27, [x4]", + "sub x26, x27, #0x1 (1)", + "cmp x27, #0x1 (1)", "cfinv" ] }, "lock xor byte [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoralb w20, w20, [x4]", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w20, #0x1", + "cmn wzr, w26, lsl #24" ] }, "lock xor byte [rax], 0xFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "mov w20, #0xff", "ldeoralb w20, w20, [x4]", - "eor w20, w20, #0xff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w20, #0xff", + "cmn wzr, w26, lsl #24" ] }, "lock xor word [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldeoralh w20, w20, [x4]", - "eor w20, w20, #0x100", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w20, #0x100", + "cmn wzr, w26, lsl #16" ] }, "lock xor word [rax], 0xFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldeoralh w20, w20, [x4]", - "eor w20, w20, #0xffff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w20, #0xffff", + "cmn wzr, w26, lsl #16" ] }, "lock xor dword [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldeoral w20, w20, [x4]", - "eor w20, w20, #0x100", - "strb w20, [x28, #706]", - "tst w20, w20" + "eor w26, w20, #0x100", + "tst w26, w26" ] }, "lock xor dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldeoral w20, w21, [x4]", - "eor w20, w21, w20", - "strb w20, [x28, #706]", - "tst w20, w20" + "eor w26, w21, w20", + "tst w26, w26" ] }, "lock xor qword [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldeoral x20, x20, [x4]", - "eor x20, x20, #0x100", - "strb w20, [x28, #706]", - "tst x20, x20" + "eor x26, x20, #0x100", + "tst x26, x26" ] }, "lock xor qword [rax], -2147483647": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "ldeoral x20, x20, [x4]", - "eor x20, x20, #0xffffffff80000001", - "strb w20, [x28, #706]", - "tst x20, x20" + "eor x26, x20, #0xffffffff80000001", + "tst x26, x26" ] }, "lock xor word [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoralh w20, w20, [x4]", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w20, #0x1", + "cmn wzr, w26, lsl #16" ] }, "lock xor dword [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoral w20, w20, [x4]", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", - "tst w20, w20" + "eor w26, w20, #0x1", + "tst w26, w26" ] }, "lock xor qword [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoral x20, x20, [x4]", - "eor x20, x20, #0x1", - "strb w20, [x28, #706]", - "tst x20, x20" + "eor x26, x20, #0x1", + "tst x26, x26" ] }, "lock dec byte [rax]": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP3 0xfe /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddalb w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #24", - "bic w20, w20, w21", - "rmif x20, #7, #nzcV", - "rmif x22, #63, #nzCv" + "ldaddalb w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cset w20, hs", + "cmn wzr, w26, lsl #24", + "bic w21, w27, w26", + "rmif x21, #7, #nzcV", + "rmif x20, #63, #nzCv" ] }, "lock not byte [rax]": { @@ -1629,178 +1463,156 @@ ] }, "lock neg byte [rax]": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ "ldaxrb w1, [x4]", "neg w2, w1", "stlxrb w3, w2, [x4]", "cbnz w3, #-0xc", - "mov w20, w1", - "neg w21, w20", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "and w20, w21, w20", + "mov w27, w1", + "neg w26, w27", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "and w20, w26, w27", "rmif x20, #7, #nzcV" ] }, "lock neg word [rax]": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxrh w1, [x4]", "neg w2, w1", "stlxrh w3, w2, [x4]", "cbnz w3, #-0xc", - "mov w20, w1", - "neg w21, w20", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "and w20, w21, w20", + "mov w27, w1", + "neg w26, w27", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "and w20, w26, w27", "rmif x20, #15, #nzcV" ] }, "lock neg dword [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr w1, [x4]", "neg w2, w1", "stlxr w3, w2, [x4]", "cbnz w3, #-0xc", - "mov w20, w1", - "neg w21, w20", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp wzr, w20", + "mov w27, w1", + "neg w26, w27", + "cmp wzr, w27", "cfinv" ] }, "lock neg qword [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr x1, [x4]", "neg x2, x1", "stlxr w3, x2, [x4]", "cbnz x3, #-0xc", - "mov x20, x1", - "neg x21, x20", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp xzr, x20", + "mov x27, x1", + "neg x26, x27", + "cmp xzr, x27", "cfinv" ] }, "lock dec word [rax]": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddalh w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #16", - "bic w20, w20, w21", - "rmif x20, #15, #nzcV", - "rmif x22, #63, #nzCv" + "ldaddalh w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cset w20, hs", + "cmn wzr, w26, lsl #16", + "bic w21, w27, w26", + "rmif x21, #15, #nzcV", + "rmif x20, #63, #nzCv" ] }, "lock dec dword [rax]": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", - "ldaddal w1, w20, [x4]", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w21, hs", - "cmp w20, #0x1 (1)", - "rmif x21, #63, #nzCv" + "ldaddal w1, w27, [x4]", + "sub w26, w27, #0x1 (1)", + "cset w20, hs", + "cmp w27, #0x1 (1)", + "rmif x20, #63, #nzCv" ] }, "lock dec qword [rax]": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg x1, x20", - "ldaddal x1, x20, [x4]", - "sub x21, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w21, hs", - "cmp x20, #0x1 (1)", - "rmif x21, #63, #nzCv" + "ldaddal x1, x27, [x4]", + "sub x26, x27, #0x1 (1)", + "cset w20, hs", + "cmp x27, #0x1 (1)", + "rmif x20, #63, #nzCv" ] }, "lock inc byte [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddalb w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #24", - "bic w20, w21, w20", - "rmif x20, #7, #nzcV", - "rmif x22, #63, #nzCv" + "ldaddalb w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cset w20, hs", + "cmn wzr, w26, lsl #24", + "bic w21, w26, w27", + "rmif x21, #7, #nzcV", + "rmif x20, #63, #nzCv" ] }, "lock inc word [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddalh w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #16", - "bic w20, w21, w20", - "rmif x20, #15, #nzcV", - "rmif x22, #63, #nzCv" + "ldaddalh w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cset w20, hs", + "cmn wzr, w26, lsl #16", + "bic w21, w26, w27", + "rmif x21, #15, #nzcV", + "rmif x20, #63, #nzCv" ] }, "lock inc dword [rax]": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddal w20, w20, [x4]", - "add w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w21, hs", - "cmn w20, #0x1 (1)", - "rmif x21, #63, #nzCv" + "ldaddal w20, w27, [x4]", + "add w26, w27, #0x1 (1)", + "cset w20, hs", + "cmn w27, #0x1 (1)", + "rmif x20, #63, #nzCv" ] }, "lock inc qword [rax]": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ "mov w20, #0x1", - "ldaddal x20, x20, [x4]", - "add x21, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w21, hs", - "cmn x20, #0x1 (1)", - "rmif x21, #63, #nzCv" + "ldaddal x20, x27, [x4]", + "add x26, x27, #0x1 (1)", + "cset w20, hs", + "cmn x27, #0x1 (1)", + "rmif x20, #63, #nzCv" ] } } diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json index 9eacb0154..21fadc980 100644 --- a/unittests/InstructionCountCI/FlagM/H0F38.json +++ b/unittests/InstructionCountCI/FlagM/H0F38.json @@ -12,7 +12,7 @@ }, "Instructions": { "ptest xmm0, xmm1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": [ "0x66 0x0f 0x38 0x17" ], @@ -25,16 +25,14 @@ "addv h3, v3.8h", "umov w20, v2.h[0]", "umov w21, v3.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", "lsl x20, x20, #30", "orr w20, w20, w21, lsl #29", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 67ca9cdec..deeba79c6 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -12,69 +12,63 @@ }, "Instructions": { "add bl, cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x00", "ExpectedArm64ASM": [ "uxtb w20, w5", "uxtb w21, w7", - "add w22, w21, w20", - "bfxil x7, x22, #0, #8", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "add w26, w21, w20", + "bfxil x7, x26, #0, #8", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "add bx, cx": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x01", "ExpectedArm64ASM": [ "uxth w20, w5", "uxth w21, w7", - "add w22, w21, w20", - "bfxil x7, x22, #0, #16", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "add w26, w21, w20", + "bfxil x7, x26, #0, #16", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "add ebx, ecx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x01", "ExpectedArm64ASM": [ "mov x20, x7", "add w7, w20, w5", - "eor w21, w20, w5", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor w27, w20, w5", + "mov x26, x7", "cmn w20, w5" ] }, "add rbx, rcx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x01", "ExpectedArm64ASM": [ "mov x20, x7", "add x7, x20, x5", - "eor x21, x20, x5", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor x27, x20, x5", + "mov x26, x7", "cmn x20, x5" ] }, "db 0x02, 0xcb": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": [ "0x02", "add bl, cl but modrm.rm as source" @@ -82,21 +76,19 @@ "ExpectedArm64ASM": [ "uxtb w20, w7", "uxtb w21, w5", - "add w22, w21, w20", - "bfxil x5, x22, #0, #8", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "add w26, w21, w20", + "bfxil x5, x26, #0, #8", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "db 0x66, 0x03, 0xcb": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": [ "0x03", "add bx, cx but modrm.rm as source" @@ -104,21 +96,19 @@ "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w5", - "add w22, w21, w20", - "bfxil x5, x22, #0, #16", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "add w26, w21, w20", + "bfxil x5, x26, #0, #16", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "db 0x03, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": [ "0x03", "add ebx, ecx but modrm.rm as source" @@ -126,14 +116,13 @@ "ExpectedArm64ASM": [ "mov x20, x5", "add w5, w20, w7", - "eor w21, w20, w7", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor w27, w20, w7", + "mov x26, x5", "cmn w20, w7" ] }, "db 0x48, 0x03, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": [ "0x03", "add rbx, rcx but modrm.rm as source" @@ -141,152 +130,136 @@ "ExpectedArm64ASM": [ "mov x20, x5", "add x5, x20, x7", - "eor x21, x20, x7", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor x27, x20, x7", + "mov x26, x5", "cmn x20, x7" ] }, "add al, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x04", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w21, w20", + "uxtb w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w26, w27", "rmif x20, #7, #nzcV" ] }, "add ax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x05", "ExpectedArm64ASM": [ - "uxth w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "bic w20, w21, w20", + "uxth w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w26, w27", "rmif x20, #15, #nzcV" ] }, "add eax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ - "mov x20, x4", - "add w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn w20, #0x1 (1)" + "mov x27, x4", + "add w4, w27, #0x1 (1)", + "mov x26, x4", + "cmn w27, #0x1 (1)" ] }, "add rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn x20, #0x1 (1)" + "mov x27, x4", + "add x4, x27, #0x1 (1)", + "mov x26, x4", + "cmn x27, #0x1 (1)" ] }, "add al, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "0x04", "ExpectedArm64ASM": [ "uxtb w20, w4", - "add w21, w20, #0xff (255)", - "bfxil x4, x21, #0, #8", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w20, w21", + "add w26, w20, #0xff (255)", + "bfxil x4, x26, #0, #8", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w20, w26", "rmif x20, #7, #nzcV" ] }, "add ax, -1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffff", "uxth w21, w4", - "add w20, w21, w20", - "bfxil x4, x20, #0, #16", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "rmif x20, #15, #nzCv", - "bic w20, w21, w20", + "add w26, w21, w20", + "bfxil x4, x26, #0, #16", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w21, w26", "rmif x20, #15, #nzcV" ] }, "add eax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov x21, x4", "add w4, w21, w20", - "eor w22, w21, w20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w21, w20", + "mov x26, x4", "cmn w21, w20" ] }, "add rax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, #0x1 (1)", - "eor x22, x21, x20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x21, x20", + "mov x26, x4", "cmn x21, x20" ] }, "or bl, bh": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "", "ExpectedArm64ASM": [ "lsr w20, w7, #8", - "orr w20, w7, w20", - "bfxil x7, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w7, w20", + "bfxil x7, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "or bl, cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x08", "ExpectedArm64ASM": [ - "orr w20, w7, w5", - "bfxil x7, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w7, w5", + "bfxil x7, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "or bx, cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x09", "ExpectedArm64ASM": [ - "orr w20, w7, w5", - "bfxil x7, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w7, w5", + "bfxil x7, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "or ebx, ecx": { @@ -294,7 +267,7 @@ "Comment": "0x09", "ExpectedArm64ASM": [ "orr w7, w7, w5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst w7, w7" ] }, @@ -303,34 +276,32 @@ "Comment": "0x09", "ExpectedArm64ASM": [ "orr x7, x7, x5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst x7, x7" ] }, "db 0x0A, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x0A", "or bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "orr w20, w5, w7", - "bfxil x5, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w5, w7", + "bfxil x5, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "db 0x66, 0x0B, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x0B", "or bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "orr w20, w5, w7", - "bfxil x5, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w5, w7", + "bfxil x5, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "db 0x0B, 0xcb": { @@ -341,7 +312,7 @@ ], "ExpectedArm64ASM": [ "orr w5, w5, w7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst w5, w5" ] }, @@ -353,28 +324,26 @@ ], "ExpectedArm64ASM": [ "orr x5, x5, x7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst x5, x5" ] }, "or al, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x0C", "ExpectedArm64ASM": [ - "orr w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "or ax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x0D", "ExpectedArm64ASM": [ - "orr w20, w4, #0x1", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w4, #0x1", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "or eax, 1": { @@ -382,7 +351,7 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "orr w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -391,28 +360,26 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "orr x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "or al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x0C", "ExpectedArm64ASM": [ - "orr w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "or ax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x0D", "ExpectedArm64ASM": [ - "orr w20, w4, #0xffff", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w4, #0xffff", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "or eax, -1": { @@ -421,7 +388,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "orr w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -431,12 +398,12 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "orr x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "adc bl, cl": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0x10", "ExpectedArm64ASM": [ "uxtb w20, w5", @@ -445,28 +412,26 @@ "uxtb w23, w7", "add w22, w23, w22", "bfxil x7, x22, #0, #8", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "msr nzcv, x21", "rmif x20, #7, #nzcV" ] }, "adc bx, cx": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0x11", "ExpectedArm64ASM": [ "uxth w20, w5", @@ -475,28 +440,26 @@ "uxth w23, w7", "add w22, w23, w22", "bfxil x7, x22, #0, #16", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "msr nzcv, x21", "rmif x20, #15, #nzcV" ] }, "adc ebx, ecx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x11", "ExpectedArm64ASM": [ "mov w20, w5", @@ -504,28 +467,26 @@ "add w21, w20, w21", "mov w22, w7", "add w7, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x7", "adcs wzr, w22, w20" ] }, "adc rbx, rcx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x11", "ExpectedArm64ASM": [ "cset w20, hs", "add x20, x5, x20", "mov x21, x7", "add x7, x21, x20", - "eor x20, x21, x5", - "strb w20, [x28, #708]", - "strb w7, [x28, #706]", + "eor x27, x21, x5", + "mov x26, x7", "adcs xzr, x21, x5" ] }, "db 0x12, 0xcb": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": [ "0x12", "adc bl, cl but modrm.rm as source" @@ -537,28 +498,26 @@ "uxtb w23, w5", "add w22, w23, w22", "bfxil x5, x22, #0, #8", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "msr nzcv, x21", "rmif x20, #7, #nzcV" ] }, "db 0x66, 0x13, 0xcb": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": [ "0x13", "adc bx, cx but modrm.rm as source" @@ -570,28 +529,26 @@ "uxth w23, w5", "add w22, w23, w22", "bfxil x5, x22, #0, #16", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "msr nzcv, x21", "rmif x20, #15, #nzcV" ] }, "db 0x13, 0xcb": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": [ "0x13", "adc ebx, ecx but modrm.rm as source" @@ -602,14 +559,13 @@ "add w21, w20, w21", "mov w22, w5", "add w5, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x5", "adcs wzr, w22, w20" ] }, "db 0x48, 0x13, 0xcb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": [ "0x13", "adc rbx, rcx but modrm.rm as source" @@ -619,96 +575,89 @@ "add x20, x7, x20", "mov x21, x5", "add x5, x21, x20", - "eor x20, x21, x7", - "strb w20, [x28, #708]", - "strb w5, [x28, #706]", + "eor x27, x21, x7", + "mov x26, x5", "adcs xzr, x21, x7" ] }, "adc al, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0x14", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxtb w22, w4", - "add w20, w22, w20", + "uxtb w27, w4", + "add w20, w27, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0x1 (1)", - "cset x24, lo", - "cmp w20, #0x1 (1)", - "cset x25, ls", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0x1 (1)", + "cset x22, lo", + "cmp w26, #0x1 (1)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "adc ax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxth w22, w4", - "add w20, w22, w20", + "uxth w27, w4", + "add w20, w27, w20", "bfxil x4, x20, #0, #16", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, #0x1 (1)", - "cset x24, lo", - "cmp w20, #0x1 (1)", - "cset x25, ls", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, #0x1 (1)", + "cset x22, lo", + "cmp w26, #0x1 (1)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #15, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "msr nzcv, x20", + "rmif x21, #15, #nzcV" ] }, "adc eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "add w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs wzr, w22, w20" + "mov w27, w4", + "add w4, w27, w21", + "mov x26, x4", + "adcs wzr, w27, w20" ] }, "adc rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "add x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs xzr, x22, x20" + "mov x27, x4", + "add x4, x27, x21", + "mov x26, x4", + "adcs xzr, x27, x20" ] }, "adc al, -1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x14", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -717,26 +666,24 @@ "uxtb w22, w4", "add w20, w22, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0xff (255)", - "cset x24, lo", - "cmp w20, #0xff (255)", - "cset x25, ls", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0xff (255)", + "cset x23, lo", + "cmp w26, #0xff (255)", + "cset x24, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w22, w26", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "adc ax, -1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -745,26 +692,24 @@ "uxth w23, w4", "add w22, w23, w22", "bfxil x4, x22, #0, #16", - "uxth w22, w22", - "eor w24, w23, #0xffff", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", + "uxth w26, w22", + "eor w27, w23, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", "cset x20, ls", "cmp x21, #0x1 (1)", - "csel x20, x20, x25, eq", - "orr w20, w24, w20, lsl #29", - "bic w21, w23, w22", + "csel x20, x20, x24, eq", + "orr w20, w22, w20, lsl #29", + "bic w21, w23, w26", "msr nzcv, x20", "rmif x21, #15, #nzcV" ] }, "adc eax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", @@ -772,14 +717,13 @@ "add w21, w20, w21", "mov w22, w4", "add w4, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x4", "adcs wzr, w22, w20" ] }, "adc rax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x15", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", @@ -787,14 +731,13 @@ "add x21, x20, x21", "mov x22, x4", "add x4, x22, x21", - "eor x21, x22, x20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x22, x20", + "mov x26, x4", "adcs xzr, x22, x20" ] }, "sbb bl, cl": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0x18", "ExpectedArm64ASM": [ "uxtb w20, w5", @@ -803,28 +746,26 @@ "uxtb w23, w7", "sub w22, w23, w22", "bfxil x7, x22, #0, #8", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "msr nzcv, x21", "rmif x20, #7, #nzcV" ] }, "sbb bx, cx": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0x19", "ExpectedArm64ASM": [ "uxth w20, w5", @@ -833,28 +774,26 @@ "uxth w23, w7", "sub w22, w23, w22", "bfxil x7, x22, #0, #16", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "msr nzcv, x21", "rmif x20, #15, #nzcV" ] }, "sbb ebx, ecx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0x19", "ExpectedArm64ASM": [ "mov w20, w5", @@ -862,32 +801,30 @@ "add w21, w20, w21", "mov w22, w7", "sub w7, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x7", "cfinv", "sbcs wzr, w22, w20", "cfinv" ] }, "sbb rbx, rcx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x19", "ExpectedArm64ASM": [ "cset w20, hs", "add x20, x5, x20", "mov x21, x7", "sub x7, x21, x20", - "eor x20, x21, x5", - "strb w20, [x28, #708]", - "strb w7, [x28, #706]", + "eor x27, x21, x5", + "mov x26, x7", "cfinv", "sbcs xzr, x21, x5", "cfinv" ] }, "db 0x1A, 0xcb": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": [ "0x1A", "sbb bl, cl but modrm.rm as source" @@ -899,28 +836,26 @@ "uxtb w23, w5", "sub w22, w23, w22", "bfxil x5, x22, #0, #8", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "msr nzcv, x21", "rmif x20, #7, #nzcV" ] }, "db 0x66, 0x1B, 0xcb": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": [ "0x1B", "sbb bx, cx but modrm.rm as source" @@ -932,28 +867,26 @@ "uxth w23, w5", "sub w22, w23, w22", "bfxil x5, x22, #0, #16", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "msr nzcv, x21", "rmif x20, #15, #nzcV" ] }, "db 0x1B, 0xcb": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0x1B", "sbb ebx, ecx but modrm.rm as source" @@ -964,16 +897,15 @@ "add w21, w20, w21", "mov w22, w5", "sub w5, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x5", "cfinv", "sbcs wzr, w22, w20", "cfinv" ] }, "db 0x48, 0x1B, 0xcb": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": [ "0x1B", "sbb rbx, rcx but modrm.rm as source" @@ -983,102 +915,95 @@ "add x20, x7, x20", "mov x21, x5", "sub x5, x21, x20", - "eor x20, x21, x7", - "strb w20, [x28, #708]", - "strb w5, [x28, #706]", + "eor x27, x21, x7", + "mov x26, x5", "cfinv", "sbcs xzr, x21, x7", "cfinv" ] }, "sbb al, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0x1C", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxtb w22, w4", - "sub w20, w22, w20", + "uxtb w27, w4", + "sub w20, w27, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "sbb ax, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxth w22, w4", - "sub w20, w22, w20", + "uxth w27, w4", + "sub w20, w27, w20", "bfxil x4, x20, #0, #16", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "msr nzcv, x21", - "rmif x20, #15, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "msr nzcv, x20", + "rmif x21, #15, #nzcV" ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "sub w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov w27, w4", + "sub w4, w27, w21", + "mov x26, x4", "cfinv", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "cfinv" ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "sub x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov x27, x4", + "sub x4, x27, x21", + "mov x26, x4", "cfinv", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "cfinv" ] }, "sbb al, -1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x1C", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -1087,26 +1012,24 @@ "uxtb w22, w4", "sub w20, w22, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w22", + "cset x23, hi", + "cmp w26, w22", + "cset x24, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w22", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "sbb ax, -1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -1115,26 +1038,24 @@ "uxth w22, w4", "sub w20, w22, w20", "bfxil x4, x20, #0, #16", - "uxth w20, w20", - "eor w23, w22, #0xffff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxth w26, w20", + "eor w27, w22, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, w22", + "cset x23, hi", + "cmp w26, w22", + "cset x24, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #15, #nzcV" + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w22", + "msr nzcv, x20", + "rmif x21, #15, #nzcV" ] }, "sbb eax, -1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", @@ -1142,16 +1063,15 @@ "add w21, w20, w21", "mov w22, w4", "sub w4, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x4", "cfinv", "sbcs wzr, w22, w20", "cfinv" ] }, "sbb rax, -1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", @@ -1159,32 +1079,29 @@ "add x21, x20, x21", "mov x22, x4", "sub x4, x22, x21", - "eor x21, x22, x20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x22, x20", + "mov x26, x4", "cfinv", "sbcs xzr, x22, x20", "cfinv" ] }, "and bl, cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x20", "ExpectedArm64ASM": [ - "and w20, w7, w5", - "bfxil x7, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w7, w5", + "bfxil x7, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "and bx, cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x21", "ExpectedArm64ASM": [ - "and w20, w7, w5", - "bfxil x7, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w7, w5", + "bfxil x7, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "and ebx, ecx": { @@ -1192,7 +1109,7 @@ "Comment": "0x21", "ExpectedArm64ASM": [ "and w7, w7, w5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst w7, w7" ] }, @@ -1201,34 +1118,32 @@ "Comment": "0x21", "ExpectedArm64ASM": [ "and x7, x7, x5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst x7, x7" ] }, "db 0x22, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x22", "and bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "and w20, w5, w7", - "bfxil x5, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w5, w7", + "bfxil x5, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "db 0x66, 0x23, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x23", "and bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "and w20, w5, w7", - "bfxil x5, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w5, w7", + "bfxil x5, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "db 0x23, 0xcb": { @@ -1239,7 +1154,7 @@ ], "ExpectedArm64ASM": [ "and w5, w5, w7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst w5, w5" ] }, @@ -1251,28 +1166,26 @@ ], "ExpectedArm64ASM": [ "and x5, x5, x7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst x5, x5" ] }, "and al, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x24", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "and ax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x25", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w4, #0x1", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "and eax, 1": { @@ -1280,7 +1193,7 @@ "Comment": "0x25", "ExpectedArm64ASM": [ "and w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1289,28 +1202,26 @@ "Comment": "0x25", "ExpectedArm64ASM": [ "and x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "and al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x24", "ExpectedArm64ASM": [ - "and w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "and ax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x25", "ExpectedArm64ASM": [ - "and w20, w4, #0xffff", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w4, #0xffff", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "and eax, -1": { @@ -1319,7 +1230,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "and w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1329,76 +1240,70 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "and x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "sub bl, cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x28", "ExpectedArm64ASM": [ "uxtb w20, w5", "uxtb w21, w7", - "sub w22, w21, w20", - "bfxil x7, x22, #0, #8", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "sub w26, w21, w20", + "bfxil x7, x26, #0, #8", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "sub bx, cx": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x29", "ExpectedArm64ASM": [ "uxth w20, w5", "uxth w21, w7", - "sub w22, w21, w20", - "bfxil x7, x22, #0, #16", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "sub w26, w21, w20", + "bfxil x7, x26, #0, #16", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "sub ebx, ecx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x29", "ExpectedArm64ASM": [ "mov x20, x7", "sub w7, w20, w5", - "eor w21, w20, w5", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor w27, w20, w5", + "mov x26, x7", "cmp w20, w5", "cfinv" ] }, "sub rbx, rcx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x29", "ExpectedArm64ASM": [ "mov x20, x7", "sub x7, x20, x5", - "eor x21, x20, x5", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor x27, x20, x5", + "mov x26, x7", "cmp x20, x5", "cfinv" ] }, "db 0x2A, 0xcb": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": [ "0x2A", "sub bl, cl but modrm.rm as source" @@ -1406,21 +1311,19 @@ "ExpectedArm64ASM": [ "uxtb w20, w7", "uxtb w21, w5", - "sub w22, w21, w20", - "bfxil x5, x22, #0, #8", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "sub w26, w21, w20", + "bfxil x5, x26, #0, #8", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "db 0x66, 0x2B, 0xcb": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": [ "0x2B", "sub bx, cx but modrm.rm as source" @@ -1428,21 +1331,19 @@ "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w5", - "sub w22, w21, w20", - "bfxil x5, x22, #0, #16", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "sub w26, w21, w20", + "bfxil x5, x26, #0, #16", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "db 0x2B, 0xcb": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": [ "0x2B", "sub ebx, ecx but modrm.rm as source" @@ -1450,15 +1351,14 @@ "ExpectedArm64ASM": [ "mov x20, x5", "sub w5, w20, w7", - "eor w21, w20, w7", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor w27, w20, w7", + "mov x26, x5", "cmp w20, w7", "cfinv" ] }, "db 0x48, 0x2B, 0xcb": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": [ "0x2B", "sub rbx, rcx but modrm.rm as source" @@ -1466,146 +1366,131 @@ "ExpectedArm64ASM": [ "mov x20, x5", "sub x5, x20, x7", - "eor x21, x20, x7", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor x27, x20, x7", + "mov x26, x5", "cmp x20, x7", "cfinv" ] }, "sub al, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x2C", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w20, w21", + "uxtb w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w27, w26", "rmif x20, #7, #nzcV" ] }, "sub ax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x2D", "ExpectedArm64ASM": [ - "uxth w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "bic w20, w20, w21", + "uxth w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w27, w26", "rmif x20, #15, #nzcV" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x2D", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp w20, #0x1 (1)", + "mov x27, x4", + "sub w4, w27, #0x1 (1)", + "mov x26, x4", + "cmp w27, #0x1 (1)", "cfinv" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x2D", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp x20, #0x1 (1)", + "mov x27, x4", + "sub x4, x27, #0x1 (1)", + "mov x26, x4", + "cmp x27, #0x1 (1)", "cfinv" ] }, "sub al, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "0x2C", "ExpectedArm64ASM": [ "uxtb w20, w4", - "sub w21, w20, #0xff (255)", - "bfxil x4, x21, #0, #8", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w21, w20", + "sub w26, w20, #0xff (255)", + "bfxil x4, x26, #0, #8", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w26, w20", "rmif x20, #7, #nzcV" ] }, "sub ax, -1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffff", "uxth w21, w4", - "sub w20, w21, w20", - "bfxil x4, x20, #0, #16", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "rmif x20, #15, #nzCv", - "bic w20, w20, w21", + "sub w26, w21, w20", + "bfxil x4, x26, #0, #16", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w26, w21", "rmif x20, #15, #nzcV" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov x21, x4", "sub w4, w21, w20", - "eor w22, w21, w20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w21, w20", + "mov x26, x4", "cmp w21, w20", "cfinv" ] }, "sub rax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, x20", - "eor x22, x21, x20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x21, x20", + "mov x26, x4", "cmp x21, x20", "cfinv" ] }, "xor bl, cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x30", "ExpectedArm64ASM": [ - "eor w20, w7, w5", - "bfxil x7, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w7, w5", + "bfxil x7, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "xor bx, cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x31", "ExpectedArm64ASM": [ - "eor w20, w7, w5", - "bfxil x7, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w7, w5", + "bfxil x7, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "xor ebx, ecx": { @@ -1613,7 +1498,7 @@ "Comment": "0x31", "ExpectedArm64ASM": [ "eor w7, w7, w5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst w7, w7" ] }, @@ -1622,34 +1507,32 @@ "Comment": "0x31", "ExpectedArm64ASM": [ "eor x7, x7, x5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst x7, x7" ] }, "db 0x32, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x32", "xor bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "eor w20, w5, w7", - "bfxil x5, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w5, w7", + "bfxil x5, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "db 0x66, 0x33, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x33", "xor bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "eor w20, w5, w7", - "bfxil x5, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w5, w7", + "bfxil x5, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "db 0x33, 0xcb": { @@ -1660,7 +1543,7 @@ ], "ExpectedArm64ASM": [ "eor w5, w5, w7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst w5, w5" ] }, @@ -1672,28 +1555,26 @@ ], "ExpectedArm64ASM": [ "eor x5, x5, x7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst x5, x5" ] }, "xor al, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x34", "ExpectedArm64ASM": [ - "eor w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "xor ax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x35", "ExpectedArm64ASM": [ - "eor w20, w4, #0x1", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w4, #0x1", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "xor eax, 1": { @@ -1701,7 +1582,7 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "eor w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1710,46 +1591,42 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "eor x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp bl, cl": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0x38", "ExpectedArm64ASM": [ "uxtb w20, w5", "uxtb w21, w7", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "xor al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x34", "ExpectedArm64ASM": [ - "eor w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "xor ax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x35", "ExpectedArm64ASM": [ - "eor w20, w4, #0xffff", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w4, #0xffff", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "xor eax, -1": { @@ -1758,7 +1635,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "eor w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1768,56 +1645,50 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "eor x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp bx, cx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0x39", "ExpectedArm64ASM": [ "uxth w20, w5", "uxth w21, w7", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "cmp ebx, ecx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x39", "ExpectedArm64ASM": [ "mov w20, w5", "mov w21, w7", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "cfinv" ] }, "cmp rbx, rcx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x39", "ExpectedArm64ASM": [ - "sub x20, x7, x5", - "eor x21, x7, x5", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", + "sub x26, x7, x5", + "eor x27, x7, x5", "cmp x7, x5", "cfinv" ] }, "db 0x3A, 0xcb": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0x3A", "cmp bl, cl but modrm.rm as source" @@ -1825,20 +1696,18 @@ "ExpectedArm64ASM": [ "uxtb w20, w7", "uxtb w21, w5", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "db 0x66, 0x3B, 0xcb": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0x3B", "cmp bx, cx but modrm.rm as source" @@ -1846,20 +1715,18 @@ "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w5", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "db 0x3B, 0xcb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": [ "0x3B", "cmp ebx, ecx but modrm.rm as source" @@ -1867,134 +1734,115 @@ "ExpectedArm64ASM": [ "mov w20, w7", "mov w21, w5", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "cfinv" ] }, "db 0x48, 0x3B, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": [ "0x3B", "cmp rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "sub x20, x5, x7", - "eor x21, x5, x7", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", + "sub x26, x5, x7", + "eor x27, x5, x7", "cmp x5, x7", "cfinv" ] }, "cmp al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x3C", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w20, w21", + "uxtb w27, w4", + "sub w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w27, w26", "rmif x20, #7, #nzcV" ] }, "cmp ax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x3D", "ExpectedArm64ASM": [ - "uxth w20, w4", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "bic w20, w20, w21", + "uxth w27, w4", + "sub w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w27, w26", "rmif x20, #15, #nzcV" ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x3D", "ExpectedArm64ASM": [ - "mov w20, w4", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp w20, #0x1 (1)", + "mov w27, w4", + "sub w26, w27, #0x1 (1)", + "cmp w27, #0x1 (1)", "cfinv" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x3D", "ExpectedArm64ASM": [ - "sub x20, x4, #0x1 (1)", - "strb w4, [x28, #708]", - "strb w20, [x28, #706]", - "cmp x4, #0x1 (1)", + "mov x27, x4", + "sub x26, x27, #0x1 (1)", + "cmp x27, #0x1 (1)", "cfinv" ] }, "cmp al, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x3C", "ExpectedArm64ASM": [ "uxtb w20, w4", - "sub w21, w20, #0xff (255)", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w21, w20", + "sub w26, w20, #0xff (255)", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w26, w20", "rmif x20, #7, #nzcV" ] }, "cmp ax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffff", "uxth w21, w4", - "sub w20, w21, w20", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "rmif x20, #15, #nzCv", - "bic w20, w20, w21", + "sub w26, w21, w20", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w26, w21", "rmif x20, #15, #nzcV" ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov w21, w4", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "cfinv" ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "sub x21, x4, x20", - "eor x22, x4, x20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "sub x26, x4, x20", + "eor x27, x4, x20", "cmp x4, x20", "cfinv" ] @@ -2080,49 +1928,43 @@ ] }, "test al, bl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x84", "ExpectedArm64ASM": [ - "and w20, w4, w7", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, w7", + "cmn wzr, w26, lsl #24" ] }, "test ax, bx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x84", "ExpectedArm64ASM": [ - "and w20, w4, w7", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w4, w7", + "cmn wzr, w26, lsl #16" ] }, "test eax, ebx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x84", "ExpectedArm64ASM": [ - "and w20, w4, w7", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w4, w7", + "tst w26, w26" ] }, "test rax, rbx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x84", "ExpectedArm64ASM": [ - "and x20, x4, x7", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x4, x7", + "tst x26, x26" ] }, "pushf": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 38, "Comment": "0x9c", "ExpectedArm64ASM": [ "cset w20, hs", - "ldrb w21, [x28, #708]", - "ldrb w22, [x28, #706]", - "eor w21, w21, w22", + "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", "ldrb w21, [x28, #712]", @@ -2149,8 +1991,7 @@ "orr x20, x20, x21, lsl #20", "ldrb w21, [x28, #725]", "orr x20, x20, x21, lsl #21", - "ldrb w21, [x28, #706]", - "fmov s2, w21", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w21, v2.b[0]", "orr x21, x21, #0xfffffffffffffffe", @@ -2163,13 +2004,11 @@ ] }, "pushfq": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 38, "Comment": "0x9c", "ExpectedArm64ASM": [ "cset w20, hs", - "ldrb w21, [x28, #708]", - "ldrb w22, [x28, #706]", - "eor w21, w21, w22", + "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", "ldrb w21, [x28, #712]", @@ -2196,8 +2035,7 @@ "orr x20, x20, x21, lsl #20", "ldrb w21, [x28, #725]", "orr x20, x20, x21, lsl #21", - "ldrb w21, [x28, #706]", - "fmov s2, w21", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w21, v2.b[0]", "orr x21, x21, #0xfffffffffffffffe", @@ -2210,74 +2048,67 @@ ] }, "popf": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 32, "Comment": "0x9d", "ExpectedArm64ASM": [ "ldr x20, [x8]", "add x8, x8, #0x8 (8)", "mov w21, #0x202", - "orr x20, x20, x21", - "rmif x20, #63, #nzCv", - "ubfx w21, w20, #2, #1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "strb w20, [x28, #708]", - "rmif x20, #4, #nZcv", - "rmif x20, #4, #Nzcv", - "ubfx w21, w20, #8, #1", - "strb w21, [x28, #712]", - "ubfx w21, w20, #9, #1", - "strb w21, [x28, #713]", - "ubfx w21, w20, #10, #1", - "strb w21, [x28, #714]", - "rmif x20, #11, #nzcV", - "ubfx w21, w20, #12, #1", - "strb w21, [x28, #716]", - "ubfx w21, w20, #14, #1", - "strb w21, [x28, #718]", - "ubfx w21, w20, #16, #1", - "strb w21, [x28, #720]", - "ubfx w21, w20, #17, #1", - "strb w21, [x28, #721]", - "ubfx w21, w20, #18, #1", - "strb w21, [x28, #722]", - "ubfx w21, w20, #19, #1", - "strb w21, [x28, #723]", - "ubfx w21, w20, #20, #1", - "strb w21, [x28, #724]", - "ubfx w20, w20, #21, #1", + "orr x27, x20, x21", + "rmif x27, #63, #nzCv", + "ubfx w20, w27, #2, #1", + "eor w26, w20, #0x1", + "rmif x27, #4, #nZcv", + "rmif x27, #4, #Nzcv", + "ubfx w20, w27, #8, #1", + "strb w20, [x28, #712]", + "ubfx w20, w27, #9, #1", + "strb w20, [x28, #713]", + "ubfx w20, w27, #10, #1", + "strb w20, [x28, #714]", + "rmif x27, #11, #nzcV", + "ubfx w20, w27, #12, #1", + "strb w20, [x28, #716]", + "ubfx w20, w27, #14, #1", + "strb w20, [x28, #718]", + "ubfx w20, w27, #16, #1", + "strb w20, [x28, #720]", + "ubfx w20, w27, #17, #1", + "strb w20, [x28, #721]", + "ubfx w20, w27, #18, #1", + "strb w20, [x28, #722]", + "ubfx w20, w27, #19, #1", + "strb w20, [x28, #723]", + "ubfx w20, w27, #20, #1", + "strb w20, [x28, #724]", + "ubfx w20, w27, #21, #1", "strb w20, [x28, #725]" ] }, "sahf": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "0x9e", "ExpectedArm64ASM": [ "ubfx w20, w4, #8, #8", "mov w21, #0x28", "bic x20, x20, x21", - "orr x20, x20, #0x2", - "rmif x20, #63, #nzCv", - "ubfx w21, w20, #2, #1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "strb w20, [x28, #708]", - "rmif x20, #4, #nZcv", - "rmif x20, #4, #Nzcv" + "orr x27, x20, #0x2", + "rmif x27, #63, #nzCv", + "ubfx w20, w27, #2, #1", + "eor w26, w20, #0x1", + "rmif x27, #4, #nZcv", + "rmif x27, #4, #Nzcv" ] }, "lahf": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Comment": "0x9f", "ExpectedArm64ASM": [ "cset w20, hs", - "ldrb w21, [x28, #708]", - "ldrb w22, [x28, #706]", - "eor w21, w21, w22", + "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", - "ldrb w21, [x28, #706]", - "fmov s2, w21", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w21, v2.b[0]", "orr x21, x21, #0xfffffffffffffffe", @@ -2290,638 +2121,582 @@ ] }, "cmpsb": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": [ "0xa6" ], "ExpectedArm64ASM": [ "ldrb w20, [x11]", "ldrb w21, [x10]", - "sub w22, w21, w20", - "ldrb w23, [x28, #714]", - "mov w24, #0x1", - "sub x23, x24, x23, lsl #1", - "add x11, x11, x23", - "add x10, x10, x23", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "sub w26, w21, w20", + "ldrb w22, [x28, #714]", + "mov w23, #0x1", + "sub x22, x23, x22, lsl #1", + "add x11, x11, x22", + "add x10, x10, x22", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "cmpsw": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": [ "0xa7" ], "ExpectedArm64ASM": [ "ldrh w20, [x11]", "ldrh w21, [x10]", - "sub w22, w21, w20", - "ldrb w23, [x28, #714]", - "mov w24, #0x2", - "sub x23, x24, x23, lsl #2", - "add x11, x11, x23", - "add x10, x10, x23", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "sub w26, w21, w20", + "ldrb w22, [x28, #714]", + "mov w23, #0x2", + "sub x22, x23, x22, lsl #2", + "add x11, x11, x22", + "add x10, x10, x22", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "cmpsd": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": [ "0xa7" ], "ExpectedArm64ASM": [ "ldr w20, [x11]", "ldr w21, [x10]", - "sub w22, w21, w20", - "ldrb w23, [x28, #714]", - "mov w24, #0x4", - "sub x23, x24, x23, lsl #3", - "add x11, x11, x23", - "add x10, x10, x23", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "ldrb w22, [x28, #714]", + "mov w23, #0x4", + "sub x22, x23, x22, lsl #3", + "add x11, x11, x22", + "add x10, x10, x22", + "eor w27, w21, w20", "cmp w21, w20", "cfinv" ] }, "cmpsq": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": [ "0xa7" ], "ExpectedArm64ASM": [ "ldr x20, [x11]", "ldr x21, [x10]", - "sub x22, x21, x20", - "ldrb w23, [x28, #714]", - "mov w24, #0x8", - "sub x23, x24, x23, lsl #4", - "add x11, x11, x23", - "add x10, x10, x23", - "eor x23, x21, x20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub x26, x21, x20", + "ldrb w22, [x28, #714]", + "mov w23, #0x8", + "sub x22, x23, x22, lsl #4", + "add x11, x11, x22", + "add x10, x10, x22", + "eor x27, x21, x20", "cmp x21, x20", "cfinv" ] }, "repz cmpsb": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0xa6", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x1", "sub x20, x21, x20, lsl #1", - "cbz x5, #+0x48", + "cbz x5, #+0x40", "ldrb w21, [x11]", "ldrb w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #24", - "rmif x23, #7, #nzCv", + "sub w26, w22, w21", + "eor w27, w22, w21", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w21, w22, w21", - "eor w22, w23, w22", + "eor w22, w26, w22", "and w21, w22, w21", "rmif x21, #7, #nzcV", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x44" + "cbnz w21, #-0x3c" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x2", "sub x20, x21, x20, lsl #2", - "cbz x5, #+0x48", + "cbz x5, #+0x40", "ldrh w21, [x11]", "ldrh w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #16", - "rmif x23, #15, #nzCv", + "sub w26, w22, w21", + "eor w27, w22, w21", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w21, w22, w21", - "eor w22, w23, w22", + "eor w22, w26, w22", "and w21, w22, w21", "rmif x21, #15, #nzcV", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x44" + "cbnz w21, #-0x3c" ] }, "repz cmpsd": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x38", + "cbz x5, #+0x30", "ldr w21, [x11]", "ldr w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub w26, w22, w21", + "eor w27, w22, w21", "cmp w22, w21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x34" + "cbnz w21, #-0x2c" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x38", + "cbz x5, #+0x30", "ldr x21, [x11]", "ldr x22, [x10]", - "sub x23, x22, x21", - "eor x24, x22, x21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub x26, x22, x21", + "eor x27, x22, x21", "cmp x22, x21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x34" + "cbnz w21, #-0x2c" ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0xa6", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x1", "sub x20, x21, x20, lsl #1", - "cbz x5, #+0x48", + "cbz x5, #+0x40", "ldrb w21, [x11]", "ldrb w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #24", - "rmif x23, #7, #nzCv", + "sub w26, w22, w21", + "eor w27, w22, w21", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w21, w22, w21", - "eor w22, w23, w22", + "eor w22, w26, w22", "and w21, w22, w21", "rmif x21, #7, #nzcV", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x44" + "cbz w21, #-0x3c" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x2", "sub x20, x21, x20, lsl #2", - "cbz x5, #+0x48", + "cbz x5, #+0x40", "ldrh w21, [x11]", "ldrh w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #16", - "rmif x23, #15, #nzCv", + "sub w26, w22, w21", + "eor w27, w22, w21", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w21, w22, w21", - "eor w22, w23, w22", + "eor w22, w26, w22", "and w21, w22, w21", "rmif x21, #15, #nzcV", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x44" + "cbz w21, #-0x3c" ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x38", + "cbz x5, #+0x30", "ldr w21, [x11]", "ldr w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub w26, w22, w21", + "eor w27, w22, w21", "cmp w22, w21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x34" + "cbz w21, #-0x2c" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x38", + "cbz x5, #+0x30", "ldr x21, [x11]", "ldr x22, [x10]", - "sub x23, x22, x21", - "eor x24, x22, x21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub x26, x22, x21", + "eor x27, x22, x21", "cmp x22, x21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x34" + "cbz w21, #-0x2c" ] }, "test al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa8", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, #0x1", + "cmn wzr, w26, lsl #24" ] }, "test ax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w4, #0x1", + "cmn wzr, w26, lsl #16" ] }, "test eax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w4, #0x1", + "tst w26, w26" ] }, "test rax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "and x20, x4, #0x1", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x4, #0x1", + "tst x26, x26" ] }, "test al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa8", "ExpectedArm64ASM": [ - "and w20, w4, #0xff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, #0xff", + "cmn wzr, w26, lsl #24" ] }, "test ax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "and w20, w4, #0xffff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w4, #0xffff", + "cmn wzr, w26, lsl #16" ] }, "test eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0xa9", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "and w20, w4, w20", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w4, w20", + "tst w26, w26" ] }, "test rax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0xa9", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "and x20, x4, x20", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x4, x20", + "tst x26, x26" ] }, "scasb": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0xae", "ExpectedArm64ASM": [ "uxtb w20, w4", "ldrb w21, [x11]", - "sub w22, w20, w21", - "ldrb w23, [x28, #714]", - "mov w24, #0x1", - "sub x23, x24, x23, lsl #1", - "add x11, x11, x23", - "eor w23, w20, w21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "sub w26, w20, w21", + "ldrb w22, [x28, #714]", + "mov w23, #0x1", + "sub x22, x23, x22, lsl #1", + "add x11, x11, x22", + "eor w27, w20, w21", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w21, w20, w21", - "eor w20, w22, w20", + "eor w20, w26, w20", "and w20, w20, w21", "rmif x20, #7, #nzcV" ] }, "scasw": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0xaf", "ExpectedArm64ASM": [ "uxth w20, w4", "ldrh w21, [x11]", - "sub w22, w20, w21", - "ldrb w23, [x28, #714]", - "mov w24, #0x2", - "sub x23, x24, x23, lsl #2", - "add x11, x11, x23", - "eor w23, w20, w21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "sub w26, w20, w21", + "ldrb w22, [x28, #714]", + "mov w23, #0x2", + "sub x22, x23, x22, lsl #2", + "add x11, x11, x22", + "eor w27, w20, w21", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w21, w20, w21", - "eor w20, w22, w20", + "eor w20, w26, w20", "and w20, w20, w21", "rmif x20, #15, #nzcV" ] }, "scasd": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0xaf", "ExpectedArm64ASM": [ "mov w20, w4", "ldr w21, [x11]", - "sub w22, w20, w21", - "ldrb w23, [x28, #714]", - "mov w24, #0x4", - "sub x23, x24, x23, lsl #3", - "add x11, x11, x23", - "eor w23, w20, w21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w20, w21", + "ldrb w22, [x28, #714]", + "mov w23, #0x4", + "sub x22, x23, x22, lsl #3", + "add x11, x11, x22", + "eor w27, w20, w21", "cmp w20, w21", "cfinv" ] }, "scasq": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldr x20, [x11]", - "sub x21, x4, x20", - "ldrb w22, [x28, #714]", - "mov w23, #0x8", - "sub x22, x23, x22, lsl #4", - "add x11, x11, x22", - "eor x22, x4, x20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "sub x26, x4, x20", + "ldrb w21, [x28, #714]", + "mov w22, #0x8", + "sub x21, x22, x21, lsl #4", + "add x11, x11, x21", + "eor x27, x4, x20", "cmp x4, x20", "cfinv" ] }, "repz scasb": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x1", "sub x20, x21, x20, lsl #1", - "cbz x5, #+0x44", + "cbz x5, #+0x3c", "uxtb w21, w4", "ldrb w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #24", - "rmif x23, #7, #nzCv", + "sub w26, w21, w22", + "eor w27, w21, w22", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w22, w21, w22", - "eor w21, w23, w21", + "eor w21, w26, w21", "and w21, w21, w22", "rmif x21, #7, #nzcV", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbnz w21, #-0x40" + "cbnz w21, #-0x38" ] }, "repz scasw": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x2", "sub x20, x21, x20, lsl #2", - "cbz x5, #+0x44", + "cbz x5, #+0x3c", "uxth w21, w4", "ldrh w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #16", - "rmif x23, #15, #nzCv", + "sub w26, w21, w22", + "eor w27, w21, w22", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w22, w21, w22", - "eor w21, w23, w21", + "eor w21, w26, w21", "and w21, w21, w22", "rmif x21, #15, #nzcV", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbnz w21, #-0x40" + "cbnz w21, #-0x38" ] }, "repz scasd": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x34", + "cbz x5, #+0x2c", "mov w21, w4", "ldr w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub w26, w21, w22", + "eor w27, w21, w22", "cmp w21, w22", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbnz w21, #-0x30" + "cbnz w21, #-0x28" ] }, "repz scasq": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x30", + "cbz x5, #+0x28", "ldr x21, [x11]", - "sub x22, x4, x21", - "eor x23, x4, x21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub x26, x4, x21", + "eor x27, x4, x21", "cmp x4, x21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbnz w21, #-0x2c" + "cbnz w21, #-0x24" ] }, "repnz scasb": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x1", "sub x20, x21, x20, lsl #1", - "cbz x5, #+0x44", + "cbz x5, #+0x3c", "uxtb w21, w4", "ldrb w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #24", - "rmif x23, #7, #nzCv", + "sub w26, w21, w22", + "eor w27, w21, w22", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w22, w21, w22", - "eor w21, w23, w21", + "eor w21, w26, w21", "and w21, w21, w22", "rmif x21, #7, #nzcV", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbz w21, #-0x40" + "cbz w21, #-0x38" ] }, "repnz scasw": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x2", "sub x20, x21, x20, lsl #2", - "cbz x5, #+0x44", + "cbz x5, #+0x3c", "uxth w21, w4", "ldrh w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #16", - "rmif x23, #15, #nzCv", + "sub w26, w21, w22", + "eor w27, w21, w22", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w22, w21, w22", - "eor w21, w23, w21", + "eor w21, w26, w21", "and w21, w21, w22", "rmif x21, #15, #nzcV", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbz w21, #-0x40" + "cbz w21, #-0x38" ] }, "repnz scasd": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x34", + "cbz x5, #+0x2c", "mov w21, w4", "ldr w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub w26, w21, w22", + "eor w27, w21, w22", "cmp w21, w22", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbz w21, #-0x30" + "cbz w21, #-0x28" ] }, "repnz scasq": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x30", + "cbz x5, #+0x28", "ldr x21, [x11]", - "sub x22, x4, x21", - "eor x23, x4, x21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub x26, x4, x21", + "eor x27, x4, x21", "cmp x4, x21", "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbz w21, #-0x2c" + "cbz w21, #-0x24" ] }, "cmc": { diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index ec37adf0c..e882995f3 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -12,161 +12,145 @@ }, "Instructions": { "add al, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w21, w20", + "uxtb w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w26, w27", "rmif x20, #7, #nzcV" ] }, "or al, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ - "orr w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "adc al, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxtb w22, w4", - "add w20, w22, w20", + "uxtb w27, w4", + "add w20, w27, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0x1 (1)", - "cset x24, lo", - "cmp w20, #0x1 (1)", - "cset x25, ls", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0x1 (1)", + "cset x22, lo", + "cmp w26, #0x1 (1)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "sbb al, 1": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxtb w22, w4", - "sub w20, w22, w20", + "uxtb w27, w4", + "sub w20, w27, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "and al, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "sub al, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w20, w21", + "uxtb w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w27, w26", "rmif x20, #7, #nzcV" ] }, "xor al, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ - "eor w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "cmp al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w20, w21", + "uxtb w27, w4", + "sub w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w27, w26", "rmif x20, #7, #nzcV" ] }, "add al, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "uxtb w20, w4", - "add w21, w20, #0xff (255)", - "bfxil x4, x21, #0, #8", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w20, w21", + "add w26, w20, #0xff (255)", + "bfxil x4, x26, #0, #8", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w20, w26", "rmif x20, #7, #nzcV" ] }, "or al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ - "orr w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "adc al, -1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -175,26 +159,24 @@ "uxtb w22, w4", "add w20, w22, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0xff (255)", - "cset x24, lo", - "cmp w20, #0xff (255)", - "cset x25, ls", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0xff (255)", + "cset x23, lo", + "cmp w26, #0xff (255)", + "cset x24, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w22, w26", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "sbb al, -1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -203,110 +185,98 @@ "uxtb w22, w4", "sub w20, w22, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w22", + "cset x23, hi", + "cmp w26, w22", + "cset x24, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "msr nzcv, x21", - "rmif x20, #7, #nzcV" + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w22", + "msr nzcv, x20", + "rmif x21, #7, #nzcV" ] }, "and al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ - "and w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "sub al, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", - "sub w21, w20, #0xff (255)", - "bfxil x4, x21, #0, #8", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w21, w20", + "sub w26, w20, #0xff (255)", + "bfxil x4, x26, #0, #8", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w26, w20", "rmif x20, #7, #nzcV" ] }, "xor al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ - "eor w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "cmp al, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "uxtb w20, w4", - "sub w21, w20, #0xff (255)", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "bic w20, w21, w20", + "sub w26, w20, #0xff (255)", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "bic w20, w26, w20", "rmif x20, #7, #nzcV" ] }, "add ax, 256": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "uxth w20, w4", - "add w21, w20, #0x100 (256)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "bic w20, w21, w20", + "uxth w27, w4", + "add w26, w27, #0x100 (256)", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w26, w27", "rmif x20, #15, #nzcV" ] }, "add eax, 256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "mov x20, x4", - "add w4, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn w20, #0x100 (256)" + "mov x27, x4", + "add w4, w27, #0x100 (256)", + "mov x26, x4", + "cmn w27, #0x100 (256)" ] }, "add rax, 256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn x20, #0x100 (256)" + "mov x27, x4", + "add x4, x27, #0x100 (256)", + "mov x26, x4", + "cmn x27, #0x100 (256)" ] }, "or eax, 256": { @@ -314,7 +284,7 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr w4, w4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -323,67 +293,63 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr x4, x4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "adc eax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "add w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs wzr, w22, w20" + "mov w27, w4", + "add w4, w27, w21", + "mov x26, x4", + "adcs wzr, w27, w20" ] }, "adc rax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "add x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs xzr, x22, x20" + "mov x27, x4", + "add x4, x27, x21", + "mov x26, x4", + "adcs xzr, x27, x20" ] }, "sbb eax, 256": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "sub w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov w27, w4", + "sub w4, w27, w21", + "mov x26, x4", "cfinv", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "cfinv" ] }, "sbb rax, 256": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "sub x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov x27, x4", + "sub x4, x27, x21", + "mov x26, x4", "cfinv", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "cfinv" ] }, @@ -392,7 +358,7 @@ "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "and w4, w4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -401,31 +367,29 @@ "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "and x4, x4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "sub eax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub w4, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp w20, #0x100 (256)", + "mov x27, x4", + "sub w4, w27, #0x100 (256)", + "mov x26, x4", + "cmp w27, #0x100 (256)", "cfinv" ] }, "sub rax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x4, x20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp x20, #0x100 (256)", + "mov x27, x4", + "sub x4, x27, #0x100 (256)", + "mov x26, x4", + "cmp x27, #0x100 (256)", "cfinv" ] }, @@ -434,7 +398,7 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor w4, w4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -443,71 +407,64 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor x4, x4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp eax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ - "mov w20, w4", - "sub w21, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp w20, #0x100 (256)", + "mov w27, w4", + "sub w26, w27, #0x100 (256)", + "cmp w27, #0x100 (256)", "cfinv" ] }, "cmp rax, 256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ - "sub x20, x4, #0x100 (256)", - "strb w4, [x28, #708]", - "strb w20, [x28, #706]", - "cmp x4, #0x100 (256)", + "mov x27, x4", + "sub x26, x27, #0x100 (256)", + "cmp x27, #0x100 (256)", "cfinv" ] }, "add ax, -256": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xff00", - "uxth w21, w4", - "add w20, w21, w20", - "bfxil x4, x20, #0, #16", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "rmif x20, #15, #nzCv", - "bic w20, w21, w20", + "uxth w27, w4", + "add w26, w27, w20", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w27, w26", "rmif x20, #15, #nzcV" ] }, "add eax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x21, x4", - "add w4, w21, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", - "cmn w21, w20" + "mov x27, x4", + "add w4, w27, w20", + "mov x26, x4", + "cmn w27, w20" ] }, "add rax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "mov x21, x4", - "sub x4, x21, #0x100 (256)", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", - "cmn x21, x20" + "mov x27, x4", + "sub x4, x27, #0x100 (256)", + "mov x26, x4", + "cmn x27, x20" ] }, "or eax, -256": { @@ -515,7 +472,7 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr w4, w4, #0xffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -524,67 +481,63 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr x4, x4, #0xffffffffffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "adc eax, -256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "add w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs wzr, w22, w20" + "mov w27, w4", + "add w4, w27, w21", + "mov x26, x4", + "adcs wzr, w27, w20" ] }, "adc rax, -256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "add x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs xzr, x22, x20" + "mov x27, x4", + "add x4, x27, x21", + "mov x26, x4", + "adcs xzr, x27, x20" ] }, "sbb eax, -256": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "sub w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov w27, w4", + "sub w4, w27, w21", + "mov x26, x4", "cfinv", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "cfinv" ] }, "sbb rax, -256": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "sub x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov x27, x4", + "sub x4, x27, x21", + "mov x26, x4", "cfinv", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "cfinv" ] }, @@ -593,7 +546,7 @@ "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "and w4, w4, #0xffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -602,33 +555,31 @@ "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "and x4, x4, #0xffffffffffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "sub eax, -256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x21, x4", - "sub w4, w21, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", - "cmp w21, w20", + "mov x27, x4", + "sub w4, w27, w20", + "mov x26, x4", + "cmp w27, w20", "cfinv" ] }, "sub rax, -256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "mov x21, x4", - "sub x4, x21, x20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", - "cmp x21, x20", + "mov x27, x4", + "sub x4, x27, x20", + "mov x26, x4", + "cmp x27, x20", "cfinv" ] }, @@ -637,7 +588,7 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor w4, w4, #0xffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -646,70 +597,63 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor x4, x4, #0xffffffffffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp eax, -256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov w21, w4", - "sub w22, w21, w20", - "strb w21, [x28, #708]", - "strb w22, [x28, #706]", - "cmp w21, w20", + "mov w27, w4", + "sub w26, w27, w20", + "cmp w27, w20", "cfinv" ] }, "cmp rax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "sub x21, x4, x20", - "strb w4, [x28, #708]", - "strb w21, [x28, #706]", - "cmp x4, x20", + "mov x27, x4", + "sub x26, x27, x20", + "cmp x27, x20", "cfinv" ] }, "add ax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ - "uxth w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "bic w20, w21, w20", + "uxth w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w26, w27", "rmif x20, #15, #nzcV" ] }, "add eax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ - "mov x20, x4", - "add w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn w20, #0x1 (1)" + "mov x27, x4", + "add w4, w27, #0x1 (1)", + "mov x26, x4", + "cmn w27, #0x1 (1)" ] }, "add rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn x20, #0x1 (1)" + "mov x27, x4", + "add x4, x27, #0x1 (1)", + "mov x26, x4", + "cmn x27, #0x1 (1)" ] }, "or eax, 1": { @@ -717,7 +661,7 @@ "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "orr w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -726,67 +670,63 @@ "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "orr x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "adc eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "add w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs wzr, w22, w20" + "mov w27, w4", + "add w4, w27, w21", + "mov x26, x4", + "adcs wzr, w27, w20" ] }, "adc rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "add x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs xzr, x22, x20" + "mov x27, x4", + "add x4, x27, x21", + "mov x26, x4", + "adcs xzr, x27, x20" ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "sub w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov w27, w4", + "sub w4, w27, w21", + "mov x26, x4", "cfinv", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "cfinv" ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "sub x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov x27, x4", + "sub x4, x27, x21", + "mov x26, x4", "cfinv", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "cfinv" ] }, @@ -795,7 +735,7 @@ "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "and w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -804,31 +744,29 @@ "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "and x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp w20, #0x1 (1)", + "mov x27, x4", + "sub w4, w27, #0x1 (1)", + "mov x26, x4", + "cmp w27, #0x1 (1)", "cfinv" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp x20, #0x1 (1)", + "mov x27, x4", + "sub x4, x27, #0x1 (1)", + "mov x26, x4", + "cmp x27, #0x1 (1)", "cfinv" ] }, @@ -837,7 +775,7 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "eor w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -846,73 +784,66 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "eor x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ - "mov w20, w4", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp w20, #0x1 (1)", + "mov w27, w4", + "sub w26, w27, #0x1 (1)", + "cmp w27, #0x1 (1)", "cfinv" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ - "sub x20, x4, #0x1 (1)", - "strb w4, [x28, #708]", - "strb w20, [x28, #706]", - "cmp x4, #0x1 (1)", + "mov x27, x4", + "sub x26, x27, #0x1 (1)", + "cmp x27, #0x1 (1)", "cfinv" ] }, "add ax, -1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffff", "uxth w21, w4", - "add w20, w21, w20", - "bfxil x4, x20, #0, #16", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "rmif x20, #15, #nzCv", - "bic w20, w21, w20", + "add w26, w21, w20", + "bfxil x4, x26, #0, #16", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "bic w20, w21, w26", "rmif x20, #15, #nzcV" ] }, "add eax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov x21, x4", "add w4, w21, w20", - "eor w22, w21, w20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w21, w20", + "mov x26, x4", "cmn w21, w20" ] }, "add rax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, #0x1 (1)", - "eor x22, x21, x20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x21, x20", + "mov x26, x4", "cmn x21, x20" ] }, @@ -922,7 +853,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "orr w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -932,12 +863,12 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "orr x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "adc eax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", @@ -945,14 +876,13 @@ "add w21, w20, w21", "mov w22, w4", "add w4, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x4", "adcs wzr, w22, w20" ] }, "adc rax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", @@ -960,14 +890,13 @@ "add x21, x20, x21", "mov x22, x4", "add x4, x22, x21", - "eor x21, x22, x20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x22, x20", + "mov x26, x4", "adcs xzr, x22, x20" ] }, "sbb eax, -1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", @@ -975,16 +904,15 @@ "add w21, w20, w21", "mov w22, w4", "sub w4, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x4", "cfinv", "sbcs wzr, w22, w20", "cfinv" ] }, "sbb rax, -1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", @@ -992,9 +920,8 @@ "add x21, x20, x21", "mov x22, x4", "sub x4, x22, x21", - "eor x21, x22, x20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x22, x20", + "mov x26, x4", "cfinv", "sbcs xzr, x22, x20", "cfinv" @@ -1006,7 +933,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "and w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1016,34 +943,32 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "and x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov x21, x4", "sub w4, w21, w20", - "eor w22, w21, w20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w21, w20", + "mov x26, x4", "cmp w21, w20", "cfinv" ] }, "sub rax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, x20", - "eor x22, x21, x20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x21, x20", + "mov x26, x4", "cmp x21, x20", "cfinv" ] @@ -1054,7 +979,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "eor w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1064,33 +989,29 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "eor x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov w21, w4", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "cfinv" ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "sub x21, x4, x20", - "eor x22, x4, x20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "sub x26, x4, x20", + "eor x27, x4, x20", "cmp x4, x20", "cfinv" ] @@ -1182,42 +1103,39 @@ ] }, "shl al, 2": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC0 /4", "ExpectedArm64ASM": [ "uxtb w20, w4", - "lsl w21, w20, #2", - "bfxil x4, x21, #0, #8", - "cmn wzr, w21, lsl #24", - "rmif x20, #5, #nzCv", - "strb w21, [x28, #706]" + "lsl w26, w20, #2", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "rmif x20, #5, #nzCv" ] }, "shr al, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xC0 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", - "lsr w21, w20, #2", - "bfxil x4, x21, #0, #8", - "cset w22, vs", - "cmn wzr, w21, lsl #24", + "lsr w26, w20, #2", + "bfxil x4, x26, #0, #8", + "cset w21, vs", + "cmn wzr, w26, lsl #24", "rmif x20, #0, #nzCv", - "strb w21, [x28, #706]", - "rmif x22, #0, #nzcV" + "rmif x21, #0, #nzcV" ] }, "sar al, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC0 /7", "ExpectedArm64ASM": [ "uxtb w20, w4", "sxtb x20, w20", - "asr x21, x20, #2", - "bfxil x4, x21, #0, #8", - "cmn wzr, w21, lsl #24", - "rmif x20, #0, #nzCv", - "strb w21, [x28, #706]" + "asr x26, x20, #2", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "rmif x20, #0, #nzCv" ] }, "rol ax, 2": { @@ -1381,15 +1299,14 @@ ] }, "shl ax, 2": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /4", "ExpectedArm64ASM": [ "uxth w20, w4", - "lsl w21, w20, #2", - "bfxil x4, x21, #0, #16", - "cmn wzr, w21, lsl #16", - "rmif x20, #13, #nzCv", - "strb w21, [x28, #706]" + "lsl w26, w20, #2", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x20, #13, #nzCv" ] }, "shl eax, 2": { @@ -1400,7 +1317,7 @@ "lsl w4, w20, #2", "tst w4, w4", "rmif x20, #29, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "shl rax, 2": { @@ -1411,21 +1328,20 @@ "lsl x4, x20, #2", "tst x4, x4", "rmif x20, #61, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "shr ax, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "uxth w20, w4", - "lsr w21, w20, #2", - "bfxil x4, x21, #0, #16", - "cset w22, vs", - "cmn wzr, w21, lsl #16", + "lsr w26, w20, #2", + "bfxil x4, x26, #0, #16", + "cset w21, vs", + "cmn wzr, w26, lsl #16", "rmif x20, #0, #nzCv", - "strb w21, [x28, #706]", - "rmif x22, #0, #nzcV" + "rmif x21, #0, #nzcV" ] }, "shr eax, 2": { @@ -1437,7 +1353,7 @@ "cset w21, vs", "tst w4, w4", "rmif x20, #0, #nzCv", - "strb w4, [x28, #706]", + "mov x26, x4", "rmif x21, #0, #nzcV" ] }, @@ -1450,21 +1366,20 @@ "cset w21, vs", "tst x4, x4", "rmif x20, #0, #nzCv", - "strb w4, [x28, #706]", + "mov x26, x4", "rmif x21, #0, #nzcV" ] }, "sar ax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /7", "ExpectedArm64ASM": [ "uxth w20, w4", "sxth x20, w20", - "asr x21, x20, #2", - "bfxil x4, x21, #0, #16", - "cmn wzr, w21, lsl #16", - "rmif x20, #0, #nzCv", - "strb w21, [x28, #706]" + "asr x26, x20, #2", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x20, #0, #nzCv" ] }, "sar eax, 2": { @@ -1475,7 +1390,7 @@ "asr w4, w20, #2", "tst w4, w4", "rmif x20, #0, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "sar rax, 2": { @@ -1486,7 +1401,7 @@ "asr x4, x20, #2", "tst x4, x4", "rmif x20, #0, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "rol al, 1": { @@ -1547,44 +1462,41 @@ ] }, "shl al, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd0 /4", "ExpectedArm64ASM": [ "uxtb w20, w4", "lsl w21, w20, #1", "bfxil x4, x21, #0, #8", - "uxtb w21, w21", - "cmn wzr, w21, lsl #24", + "uxtb w26, w21", + "cmn wzr, w26, lsl #24", "rmif x20, #6, #nzCv", - "strb w21, [x28, #706]", - "eor w20, w21, w20", + "eor w20, w26, w20", "rmif x20, #7, #nzcV" ] }, "shr al, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd0 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", - "lsr w21, w20, #1", - "bfxil x4, x21, #0, #8", - "cmn wzr, w21, lsl #24", + "lsr w26, w20, #1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", - "strb w21, [x28, #706]", "rmif x20, #7, #nzcV" ] }, "sar al, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd0 /7", "ExpectedArm64ASM": [ "uxtb w20, w4", "sxtb x20, w20", - "asr w21, w20, #1", - "bfxil x4, x21, #0, #8", - "cmn wzr, w21, lsl #24", - "rmif x20, #63, #nzCv", - "strb w21, [x28, #706]" + "asr w26, w20, #1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "rmif x20, #63, #nzCv" ] }, "rol ax, 1": { @@ -1737,17 +1649,16 @@ ] }, "shl ax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ "uxth w20, w4", "lsl w21, w20, #1", "bfxil x4, x21, #0, #16", - "uxth w21, w21", - "cmn wzr, w21, lsl #16", + "uxth w26, w21", + "cmn wzr, w26, lsl #16", "rmif x20, #14, #nzCv", - "strb w21, [x28, #706]", - "eor w20, w21, w20", + "eor w20, w26, w20", "rmif x20, #15, #nzcV" ] }, @@ -1759,7 +1670,7 @@ "lsl w4, w20, #1", "tst w4, w4", "rmif x20, #30, #nzCv", - "strb w4, [x28, #706]", + "mov x26, x4", "eor w20, w4, w20", "rmif x20, #31, #nzcV" ] @@ -1772,21 +1683,20 @@ "lsl x4, x20, #1", "tst x4, x4", "rmif x20, #62, #nzCv", - "strb w4, [x28, #706]", + "mov x26, x4", "eor x20, x4, x20", "rmif x20, #63, #nzcV" ] }, "shr ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd1 /5", "ExpectedArm64ASM": [ "uxth w20, w4", - "lsr w21, w20, #1", - "bfxil x4, x21, #0, #16", - "cmn wzr, w21, lsl #16", + "lsr w26, w20, #1", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", - "strb w21, [x28, #706]", "rmif x20, #15, #nzcV" ] }, @@ -1798,7 +1708,7 @@ "lsr w4, w20, #1", "tst w4, w4", "rmif x20, #63, #nzCv", - "strb w4, [x28, #706]", + "mov x26, x4", "rmif x20, #31, #nzcV" ] }, @@ -1810,21 +1720,20 @@ "lsr x4, x20, #1", "tst x4, x4", "rmif x20, #63, #nzCv", - "strb w4, [x28, #706]", + "mov x26, x4", "rmif x20, #63, #nzcV" ] }, "sar ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd1 /7", "ExpectedArm64ASM": [ "uxth w20, w4", "sxth x20, w20", - "asr w21, w20, #1", - "bfxil x4, x21, #0, #16", - "cmn wzr, w21, lsl #16", - "rmif x20, #63, #nzCv", - "strb w21, [x28, #706]" + "asr w26, w20, #1", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x20, #63, #nzCv" ] }, "sar eax, 1": { @@ -1835,7 +1744,7 @@ "asr w4, w20, #1", "tst w4, w4", "rmif x20, #63, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "sar rax, 1": { @@ -1846,7 +1755,7 @@ "asr x4, x20, #1", "tst x4, x4", "rmif x20, #63, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "rol al, cl": { @@ -1973,7 +1882,7 @@ "sub w21, w23, w21", "lsr w21, w20, w21", "rmif x21, #63, #nzCv", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "rmif x20, #7, #nzcV" ] @@ -1991,7 +1900,7 @@ "sub x21, x21, #0x1 (1)", "lsr w21, w20, w21", "rmif x21, #63, #nzCv", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "rmif x20, #7, #nzcV" ] @@ -2010,7 +1919,7 @@ "sub x21, x21, #0x1 (1)", "lsr x20, x20, x21", "rmif x20, #63, #nzCv", - "strb w22, [x28, #706]" + "mov x26, x22" ] }, "rol ax, cl": { @@ -2161,14 +2070,14 @@ "sub w24, w24, w20", "lsr w24, w22, w24", "mov w25, #0x0", - "mrs x26, nzcv", + "mrs x30, nzcv", "cmp w20, #0x1 (1)", "csel w24, w24, w25, hi", "orr w23, w23, w24", "mov w24, #0x20", "sub w24, w24, w20", "lsr w22, w22, w24", - "msr nzcv, x26", + "msr nzcv, x30", "rmif x22, #63, #nzCv", "sub w20, w20, #0x1 (1)", "lsl x20, x21, x20", @@ -2245,13 +2154,13 @@ "mov w25, #0x21", "sub w25, w25, w21", "lsl w25, w22, w25", - "mrs x26, nzcv", + "mrs x30, nzcv", "cmp w21, #0x1 (1)", "csel w24, w25, w24, hi", "orr w23, w23, w24", "sub w24, w21, #0x1 (1)", "lsr w22, w22, w24", - "msr nzcv, x26", + "msr nzcv, x30", "rmif x22, #63, #nzCv", "mov w22, #0x20", "sub w21, w22, w21", @@ -2304,7 +2213,7 @@ "sub w21, w23, w21", "lsr w21, w20, w21", "rmif x21, #63, #nzCv", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "rmif x20, #15, #nzcV" ] @@ -2323,7 +2232,7 @@ "sub w21, w23, w21", "lsr w21, w20, w21", "rmif x21, #63, #nzCv", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "rmif x20, #31, #nzcV" ] @@ -2342,7 +2251,7 @@ "sub x21, x23, x21", "lsr x21, x20, x21", "rmif x21, #63, #nzCv", - "strb w22, [x28, #706]", + "mov x26, x22", "eor x20, x20, x22", "rmif x20, #63, #nzcV" ] @@ -2360,7 +2269,7 @@ "sub x21, x21, #0x1 (1)", "lsr w21, w20, w21", "rmif x21, #63, #nzCv", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "rmif x20, #15, #nzcV" ] @@ -2378,7 +2287,7 @@ "sub x21, x21, #0x1 (1)", "lsr w21, w20, w21", "rmif x21, #63, #nzCv", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "rmif x20, #31, #nzcV" ] @@ -2396,7 +2305,7 @@ "sub x21, x21, #0x1 (1)", "lsr x21, x20, x21", "rmif x21, #63, #nzCv", - "strb w22, [x28, #706]", + "mov x26, x22", "eor x20, x20, x22", "rmif x20, #63, #nzcV" ] @@ -2415,7 +2324,7 @@ "sub x21, x21, #0x1 (1)", "lsr x20, x20, x21", "rmif x20, #63, #nzCv", - "strb w22, [x28, #706]" + "mov x26, x22" ] }, "sar eax, cl": { @@ -2431,7 +2340,7 @@ "sub x21, x21, #0x1 (1)", "lsr w20, w20, w21", "rmif x20, #63, #nzCv", - "strb w22, [x28, #706]" + "mov x26, x22" ] }, "sar rax, cl": { @@ -2447,16 +2356,15 @@ "sub x21, x21, #0x1 (1)", "lsr x20, x20, x21", "rmif x20, #63, #nzCv", - "strb w22, [x28, #706]" + "mov x26, x22" ] }, "test bl, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf6 /0", "ExpectedArm64ASM": [ - "and w20, w7, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w7, #0x1", + "cmn wzr, w26, lsl #24" ] }, "not bl": { @@ -2467,17 +2375,15 @@ ] }, "neg bl": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ - "uxtb w20, w7", - "neg w21, w20", - "bfxil x7, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "rmif x21, #7, #nzCv", - "and w20, w21, w20", + "uxtb w27, w7", + "neg w26, w27", + "bfxil x7, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "and w20, w26, w27", "rmif x20, #7, #nzcV" ] }, @@ -2545,97 +2451,87 @@ ] }, "test bx, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "and w20, w7, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w7, #0x1", + "cmn wzr, w26, lsl #16" ] }, "test ebx, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "and w20, w7, #0x1", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w7, #0x1", + "tst w26, w26" ] }, "test rbx, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "and x20, x7, #0x1", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x7, #0x1", + "tst x26, x26" ] }, "test bx, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "and w20, w7, #0xffff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w7, #0xffff", + "cmn wzr, w26, lsl #16" ] }, "test ebx, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "and w20, w7, w20", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w7, w20", + "tst w26, w26" ] }, "test rbx, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "and x20, x7, x20", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x7, x20", + "tst x26, x26" ] }, "neg bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "uxth w20, w7", - "neg w21, w20", - "bfxil x7, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "rmif x21, #15, #nzCv", - "and w20, w21, w20", + "uxth w27, w7", + "neg w26, w27", + "bfxil x7, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "and w20, w26, w27", "rmif x20, #15, #nzcV" ] }, "neg ebx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "mov w20, w7", - "neg w7, w20", - "strb w20, [x28, #708]", - "strb w7, [x28, #706]", - "cmp wzr, w20", + "mov w27, w7", + "neg w7, w27", + "mov x26, x7", + "cmp wzr, w27", "cfinv" ] }, "neg rbx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "mov x20, x7", - "neg x7, x20", - "strb w20, [x28, #708]", - "strb w7, [x28, #706]", - "cmp xzr, x20", + "mov x27, x7", + "neg x7, x27", + "mov x26, x7", + "cmp xzr, x27", "cfinv" ] }, @@ -2738,119 +2634,107 @@ ] }, "inc al": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP3 0xfe /0", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #24", - "bic w20, w21, w20", - "rmif x20, #7, #nzcV", - "rmif x22, #63, #nzCv" + "uxtb w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cset w20, hs", + "cmn wzr, w26, lsl #24", + "bic w21, w26, w27", + "rmif x21, #7, #nzcV", + "rmif x20, #63, #nzCv" ] }, "dec al": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP3 0xfe /1", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #24", - "bic w20, w20, w21", - "rmif x20, #7, #nzcV", - "rmif x22, #63, #nzCv" + "uxtb w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cset w20, hs", + "cmn wzr, w26, lsl #24", + "bic w21, w27, w26", + "rmif x21, #7, #nzcV", + "rmif x20, #63, #nzCv" ] }, "inc ax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "uxth w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #16", - "bic w20, w21, w20", - "rmif x20, #15, #nzcV", - "rmif x22, #63, #nzCv" + "uxth w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #16", + "cset w20, hs", + "cmn wzr, w26, lsl #16", + "bic w21, w26, w27", + "rmif x21, #15, #nzcV", + "rmif x20, #63, #nzCv" ] }, "inc eax": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "mov w20, w4", - "add w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cset w21, hs", - "cmn w20, #0x1 (1)", - "rmif x21, #63, #nzCv" + "mov w27, w4", + "add w4, w27, #0x1 (1)", + "mov x26, x4", + "cset w20, hs", + "cmn w27, #0x1 (1)", + "rmif x20, #63, #nzCv" ] }, "inc rax": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cset w21, hs", - "cmn x20, #0x1 (1)", - "rmif x21, #63, #nzCv" + "mov x27, x4", + "add x4, x27, #0x1 (1)", + "mov x26, x4", + "cset w20, hs", + "cmn x27, #0x1 (1)", + "rmif x20, #63, #nzCv" ] }, "dec ax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "uxth w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #16", - "bic w20, w20, w21", - "rmif x20, #15, #nzcV", - "rmif x22, #63, #nzCv" + "uxth w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #16", + "cset w20, hs", + "cmn wzr, w26, lsl #16", + "bic w21, w27, w26", + "rmif x21, #15, #nzcV", + "rmif x20, #63, #nzCv" ] }, "dec eax": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "mov w20, w4", - "sub w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cset w21, hs", - "cmp w20, #0x1 (1)", - "rmif x21, #63, #nzCv" + "mov w27, w4", + "sub w4, w27, #0x1 (1)", + "mov x26, x4", + "cset w20, hs", + "cmp w27, #0x1 (1)", + "rmif x20, #63, #nzCv" ] }, "dec rax": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cset w21, hs", - "cmp x20, #0x1 (1)", - "rmif x21, #63, #nzCv" + "mov x27, x4", + "sub x4, x27, #0x1 (1)", + "mov x26, x4", + "cset w20, hs", + "cmp x27, #0x1 (1)", + "rmif x20, #63, #nzCv" ] } } diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 44554f1d1..66e9f0b5b 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -14,7 +14,7 @@ }, "Instructions": { "ucomiss xmm0, xmm1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x0f 0x2e", "ExpectedArm64ASM": [ "mrs x20, nzcv", @@ -31,18 +31,16 @@ "msr nzcv, x20", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", - "eor w20, w21, #0x1", - "strb w20, [x28, #706]", - "mov w20, #0x0", - "mov w21, #0x90000000", - "mrs x22, nzcv", - "bic x21, x22, x21", - "strb w20, [x28, #708]", - "msr nzcv, x21" + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w20, #0x90000000", + "mrs x21, nzcv", + "bic x20, x21, x20", + "msr nzcv, x20" ] }, "comiss xmm0, xmm1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x0f 0x2f", "ExpectedArm64ASM": [ "mrs x20, nzcv", @@ -59,14 +57,12 @@ "msr nzcv, x20", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", - "eor w20, w21, #0x1", - "strb w20, [x28, #706]", - "mov w20, #0x0", - "mov w21, #0x90000000", - "mrs x22, nzcv", - "bic x21, x22, x21", - "strb w20, [x28, #708]", - "msr nzcv, x21" + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w20, #0x90000000", + "mrs x21, nzcv", + "bic x20, x21, x20", + "msr nzcv, x20" ] }, "cmovo ax, bx": { @@ -296,11 +292,10 @@ ] }, "cmovpe ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0x4a", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -311,11 +306,10 @@ ] }, "cmovpe eax, ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0x4a", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -325,11 +319,10 @@ ] }, "cmovpe rax, rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0x4a", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -339,11 +332,10 @@ ] }, "cmovnp ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0x4b", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -354,11 +346,10 @@ ] }, "cmovnp eax, ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0x4b", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -368,11 +359,10 @@ ] }, "cmovnp rax, rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0x4b", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -553,11 +543,10 @@ ] }, "setpe al": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0x9a", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mvn w20, w20", @@ -566,11 +555,10 @@ ] }, "setnp al": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0x9b", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "and x20, x20, #0x1", @@ -680,64 +668,60 @@ ] }, "shld ax, bx, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w4", "lsl x22, x21, #1", "lsr w20, w20, #15", - "orr x20, x22, x20", - "bfxil x4, x20, #0, #16", - "cmn wzr, w20, lsl #16", + "orr x26, x22, x20", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", "rmif x21, #14, #nzCv", - "strb w20, [x28, #706]", - "eor w20, w20, w21", + "eor w20, w26, w21", "rmif x20, #15, #nzcV" ] }, "shld ax, bx, 15": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w4", "lsl x22, x21, #15", "lsr w20, w20, #1", - "orr x20, x22, x20", - "bfxil x4, x20, #0, #16", - "cmn wzr, w20, lsl #16", - "rmif x21, #0, #nzCv", - "strb w20, [x28, #706]" + "orr x26, x22, x20", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x21, #0, #nzCv" ] }, "shld ax, bx, 16": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w4", "lsl x22, x21, #16", - "orr x20, x22, x20", - "bfxil x4, x20, #0, #16", - "cmn wzr, w20, lsl #16", - "rmif x21, #63, #nzCv", - "strb w20, [x28, #706]" + "orr x26, x22, x20", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x21, #63, #nzCv" ] }, "shld ax, bx, 31": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w4", "lsl x22, x21, #31", "lsr w20, w20, #17", - "orr x20, x22, x20", - "bfxil x4, x20, #0, #16", - "cmn wzr, w20, lsl #16", - "rmif x21, #0, #nzCv", - "strb w20, [x28, #706]" + "orr x26, x22, x20", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "rmif x21, #0, #nzCv" ] }, "shld eax, ebx, 1": { @@ -749,7 +733,7 @@ "extr w4, w21, w20, #31", "tst w4, w4", "rmif x21, #30, #nzCv", - "strb w4, [x28, #706]", + "mov x26, x4", "eor w20, w4, w21", "rmif x20, #31, #nzcV" ] @@ -763,7 +747,7 @@ "extr w4, w21, w20, #17", "tst w4, w4", "rmif x21, #16, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "shld eax, ebx, 16": { @@ -775,7 +759,7 @@ "extr w4, w21, w20, #16", "tst w4, w4", "rmif x21, #15, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "shld eax, ebx, 31": { @@ -787,7 +771,7 @@ "extr w4, w21, w20, #1", "tst w4, w4", "rmif x21, #0, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "shld rax, rbx, 1": { @@ -798,7 +782,7 @@ "extr x4, x20, x7, #63", "tst x4, x4", "rmif x20, #62, #nzCv", - "strb w4, [x28, #706]", + "mov x26, x4", "eor x20, x4, x20", "rmif x20, #63, #nzcV" ] @@ -811,7 +795,7 @@ "extr x4, x20, x7, #49", "tst x4, x4", "rmif x20, #48, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "shld rax, rbx, 32": { @@ -822,7 +806,7 @@ "extr x4, x20, x7, #32", "tst x4, x4", "rmif x20, #31, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "shld rax, rbx, 63": { @@ -833,7 +817,7 @@ "extr x4, x20, x7, #1", "tst x4, x4", "rmif x20, #0, #nzCv", - "strb w4, [x28, #706]" + "mov x26, x4" ] }, "shld ax, bx, cl": { @@ -861,7 +845,7 @@ "sub w22, w23, w22", "lsr w22, w21, w22", "rmif x22, #63, #nzCv", - "strb w20, [x28, #706]", + "mov x26, x20", "eor w20, w21, w20", "rmif x20, #15, #nzcV" ] @@ -891,7 +875,7 @@ "sub w22, w23, w22", "lsr w22, w21, w22", "rmif x22, #63, #nzCv", - "strb w20, [x28, #706]", + "mov x26, x20", "eor w20, w21, w20", "rmif x20, #31, #nzcV" ] @@ -919,7 +903,7 @@ "sub x21, x23, x21", "lsr x21, x20, x21", "rmif x21, #63, #nzCv", - "strb w22, [x28, #706]", + "mov x26, x22", "eor x20, x20, x22", "rmif x20, #63, #nzcV" ] @@ -1104,7 +1088,7 @@ ] }, "cmpxchg al, bl": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "0x0f 0xb0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -1116,20 +1100,18 @@ "csel w20, w20, w21, eq", "bfxil x4, x23, #0, #8", "bfxil x4, x20, #0, #8", - "sub x20, x22, x23", - "eor w21, w22, w23", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "rmif x20, #7, #nzCv", - "eor w21, w22, w23", - "eor w20, w20, w22", - "and w20, w20, w21", + "sub x26, x22, x23", + "eor w27, w22, w23", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", + "eor w20, w22, w23", + "eor w21, w26, w22", + "and w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "cmpxchg [rax], bl": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0x0f 0xb0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -1138,20 +1120,18 @@ "casalb w1, w20, [x4]", "mov w20, w1", "bfxil x4, x20, #0, #8", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "cmpxchg ax, bx": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1163,20 +1143,18 @@ "csel w20, w20, w21, eq", "bfxil x4, x23, #0, #16", "bfxil x4, x20, #0, #16", - "sub x20, x22, x23", - "eor w21, w22, w23", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "rmif x20, #15, #nzCv", - "eor w21, w22, w23", - "eor w20, w20, w22", - "and w20, w20, w21", + "sub x26, x22, x23", + "eor w27, w22, w23", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", + "eor w20, w22, w23", + "eor w21, w26, w22", + "and w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "cmpxchg [rax], bx": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1185,20 +1163,18 @@ "casalh w1, w20, [x4]", "mov w20, w1", "bfxil x4, x20, #0, #16", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "cmpxchg eax, ebx": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", @@ -1212,10 +1188,8 @@ "cmp x24, x23", "csel x4, x21, x22, eq", "mov x4, x20", - "sub x20, x23, x24", - "eor w21, w23, w24", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", + "sub x26, x23, x24", + "eor w27, w23, w24", "cmp w23, w24", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1223,7 +1197,7 @@ ] }, "cmpxchg [rax], ebx": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", @@ -1233,10 +1207,8 @@ "mov w20, w1", "cmp w20, w21", "csel x4, x4, x20, eq", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1244,7 +1216,7 @@ ] }, "cmpxchg rax, rbx": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov x20, x4", @@ -1254,10 +1226,8 @@ "csel x22, x7, x20, eq", "mov x4, x21", "mov x4, x22", - "sub x22, x20, x21", - "eor x23, x20, x21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub x26, x20, x21", + "eor x27, x20, x21", "cmp x20, x21", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1265,17 +1235,15 @@ ] }, "cmpxchg [rax], rbx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov x20, x4", "mov x1, x20", "casal x1, x7, [x20]", "mov x4, x1", - "sub x21, x20, x4", - "eor x22, x20, x4", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "sub x26, x20, x4", + "eor x27, x20, x4", "cmp x20, x4", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1644,134 +1612,120 @@ ] }, "xadd al, bl": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w4", "uxtb w21, w7", - "add w22, w20, w21", + "add w26, w20, w21", "bfxil x7, x20, #0, #8", - "bfxil x4, x22, #0, #8", - "eor w23, w20, w21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "bfxil x4, x26, #0, #8", + "eor w27, w20, w21", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w21, w20, w21", - "eor w20, w22, w20", + "eor w20, w26, w20", "bic w20, w20, w21", "rmif x20, #7, #nzcV" ] }, "xadd [rax], bl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w7", "ldaddalb w20, w21, [x4]", "bfxil x7, x21, #0, #8", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "rmif x22, #7, #nzCv", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "rmif x26, #7, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "rmif x20, #7, #nzcV" ] }, "xadd ax, bx": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w4", "uxth w21, w7", - "add w22, w20, w21", + "add w26, w20, w21", "bfxil x7, x20, #0, #16", - "bfxil x4, x22, #0, #16", - "eor w23, w20, w21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "bfxil x4, x26, #0, #16", + "eor w27, w20, w21", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w21, w20, w21", - "eor w20, w22, w20", + "eor w20, w26, w20", "bic w20, w20, w21", "rmif x20, #15, #nzcV" ] }, "xadd [rax], bx": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w7", "ldaddalh w20, w21, [x4]", "bfxil x7, x21, #0, #16", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "rmif x22, #15, #nzCv", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "rmif x26, #15, #nzCv", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "rmif x20, #15, #nzcV" ] }, "xadd eax, ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w4", "mov w21, w7", "add w4, w20, w21", "mov x7, x20", - "eor w22, w20, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w20, w21", + "mov x26, x4", "cmn w20, w21" ] }, "xadd [rax], ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", - "add w21, w7, w20", - "eor w22, w7, w20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add w26, w7, w20", + "eor w27, w7, w20", "cmn w7, w20" ] }, "xadd rax, rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x4", "mov x21, x7", "add x4, x20, x21", "mov x7, x20", - "eor x22, x20, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x20, x21", + "mov x26, x4", "cmn x20, x21" ] }, "xadd [rax], rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x7", "ldaddal x20, x7, [x4]", - "add x21, x7, x20", - "eor x22, x7, x20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add x26, x7, x20", + "eor x27, x7, x20", "cmn x7, x20" ] }, @@ -1779,7 +1733,7 @@ "ExpectedInstructionCount": 12, "Comment": "0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "mov x20, #0x201", "movk x20, #0x804, lsl #16", "movk x20, #0x2010, lsl #32", @@ -1797,9 +1751,9 @@ "ExpectedInstructionCount": 6, "Comment": "0x0f 0xf7", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "cmlt v2.16b, v2.16b, #0", - "ldr d3, [x28, #752]", + "ldr d3, [x28, #768]", "ldr d4, [x11]", "bsl v2.8b, v3.8b, v4.8b", "str d2, [x11]" diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index 9529aed3c..e45204fe5 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -759,7 +759,7 @@ "mov w24, w2", "mov w25, w3", "mov w20, w24", - "mov w26, w25", + "mov w30, w25", "cmp x24, x22", "ccmp x25, x23, #nzcv, eq", "cset x22, eq", @@ -767,7 +767,7 @@ "rmif x22, #62, #nZcv", "cbnz x22, #+0xc", "mov x4, x20", - "mov x6, x26" + "mov x6, x30" ] }, "cmpxchg16b [rbp]": { @@ -786,7 +786,7 @@ "mov x24, x2", "mov x25, x3", "mov x20, x24", - "mov x26, x25", + "mov x30, x25", "cmp x24, x22", "ccmp x25, x23, #nzcv, eq", "cset x22, eq", @@ -794,11 +794,11 @@ "rmif x22, #62, #nZcv", "cbnz x22, #+0xc", "mov x4, x20", - "mov x6, x26" + "mov x6, x30" ] }, "rdrand ax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", @@ -806,16 +806,14 @@ "mov x22, x20", "mov x20, x21", "bfxil x4, x22, #0, #16", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdrand eax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", @@ -823,32 +821,28 @@ "mov x22, x20", "mov x20, x21", "mov w4, w22", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdrand rax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", "cset x21, ne", "mov x4, x20", "mov x20, x21", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdseed ax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", @@ -856,16 +850,14 @@ "mov x22, x20", "mov x20, x21", "bfxil x4, x22, #0, #16", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdseed eax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", @@ -873,26 +865,22 @@ "mov x22, x20", "mov x20, x21", "mov w4, w22", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdseed rax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", "cset x21, ne", "mov x4, x20", "mov x20, x21", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] @@ -908,9 +896,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ushr v2.8h, v2.8h, #15", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrlw mm0, 16": { @@ -918,9 +906,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrlw xmm0, 0": { @@ -956,9 +944,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "sshr v2.8h, v2.8h, #15", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psraw mm0, 16": { @@ -966,9 +954,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "sshr v2.8h, v2.8h, #15", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psraw xmm0, 0": { @@ -1004,9 +992,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "shl v2.8h, v2.8h, #15", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllw mm0, 16": { @@ -1014,9 +1002,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllw xmm0, 0": { @@ -1052,9 +1040,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ushr v2.4s, v2.4s, #31", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrld mm0, 32": { @@ -1062,9 +1050,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrld xmm0, 0": { @@ -1100,9 +1088,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "sshr v2.4s, v2.4s, #31", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrad mm0, 32": { @@ -1110,9 +1098,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "sshr v2.4s, v2.4s, #31", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrad xmm0, 0": { @@ -1148,9 +1136,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "shl v2.4s, v2.4s, #31", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pslld mm0, 32": { @@ -1158,9 +1146,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pslld xmm0, 0": { @@ -1196,9 +1184,9 @@ "Type": "MMX", "Comment": "GROUP14 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ushr v2.2d, v2.2d, #63", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrlq mm0, 64": { @@ -1206,9 +1194,9 @@ "Type": "MMX", "Comment": "GROUP14 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrlq xmm0, 0": { @@ -1267,9 +1255,9 @@ "Type": "MMX", "Comment": "GROUP14 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "shl v2.2d, v2.2d, #63", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllq mm0, 64": { @@ -1277,9 +1265,9 @@ "Type": "MMX", "Comment": "GROUP14 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllq xmm0, 0": { @@ -1308,7 +1296,7 @@ "ExpectedInstructionCount": 58, "Comment": "GROUP15 0x0F 0xAE /0", "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1008]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -1322,23 +1310,23 @@ "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", "strh w20, [x4, #2]", - "ldrb w20, [x28, #1010]", + "ldrb w20, [x28, #1026]", "strb w20, [x4, #4]", - "ldr q2, [x28, #752]", - "str q2, [x4, #32]", "ldr q2, [x28, #768]", - "str q2, [x4, #48]", + "str q2, [x4, #32]", "ldr q2, [x28, #784]", - "str q2, [x4, #64]", + "str q2, [x4, #48]", "ldr q2, [x28, #800]", - "str q2, [x4, #80]", + "str q2, [x4, #64]", "ldr q2, [x28, #816]", - "str q2, [x4, #96]", + "str q2, [x4, #80]", "ldr q2, [x28, #832]", - "str q2, [x4, #112]", + "str q2, [x4, #96]", "ldr q2, [x28, #848]", - "str q2, [x4, #128]", + "str q2, [x4, #112]", "ldr q2, [x28, #864]", + "str q2, [x4, #128]", + "ldr q2, [x28, #880]", "str q2, [x4, #144]", "str q16, [x4, #160]", "str q17, [x4, #176]", @@ -1387,7 +1375,7 @@ "Comment": "GROUP15 0x0F 0xAE /1", "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "ldrh w20, [x4, #2]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -1400,23 +1388,23 @@ "strb w23, [x28, #746]", "strb w20, [x28, #750]", "ldrb w20, [x4, #4]", - "strb w20, [x28, #1010]", + "strb w20, [x28, #1026]", "ldr q2, [x4, #32]", - "str q2, [x28, #752]", - "ldr q2, [x4, #48]", "str q2, [x28, #768]", - "ldr q2, [x4, #64]", + "ldr q2, [x4, #48]", "str q2, [x28, #784]", - "ldr q2, [x4, #80]", + "ldr q2, [x4, #64]", "str q2, [x28, #800]", - "ldr q2, [x4, #96]", + "ldr q2, [x4, #80]", "str q2, [x28, #816]", - "ldr q2, [x4, #112]", + "ldr q2, [x4, #96]", "str q2, [x28, #832]", - "ldr q2, [x4, #128]", + "ldr q2, [x4, #112]", "str q2, [x28, #848]", - "ldr q2, [x4, #144]", + "ldr q2, [x4, #128]", "str q2, [x28, #864]", + "ldr q2, [x4, #144]", + "str q2, [x28, #880]", "ldr q16, [x4, #160]", "ldr q17, [x4, #176]", "ldr q18, [x4, #192]", @@ -1525,7 +1513,7 @@ "ubfx x22, x20, #0, #1", "cbnz x22, #+0x8", "b #+0x84", - "ldrh w22, [x28, #1008]", + "ldrh w22, [x28, #1024]", "strh w22, [x21]", "mov w22, #0x0", "ldrb w23, [x28, #747]", @@ -1533,29 +1521,29 @@ "ldrb w23, [x28, #744]", "ldrb w24, [x28, #745]", "ldrb w25, [x28, #746]", - "ldrb w26, [x28, #750]", + "ldrb w30, [x28, #750]", "orr x22, x22, x23, lsl #8", "orr x22, x22, x24, lsl #9", "orr x22, x22, x25, lsl #10", - "orr x22, x22, x26, lsl #14", + "orr x22, x22, x30, lsl #14", "strh w22, [x21, #2]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "strb w22, [x21, #4]", - "ldr q2, [x28, #752]", - "str q2, [x21, #32]", "ldr q2, [x28, #768]", - "str q2, [x21, #48]", + "str q2, [x21, #32]", "ldr q2, [x28, #784]", - "str q2, [x21, #64]", + "str q2, [x21, #48]", "ldr q2, [x28, #800]", - "str q2, [x21, #80]", + "str q2, [x21, #64]", "ldr q2, [x28, #816]", - "str q2, [x21, #96]", + "str q2, [x21, #80]", "ldr q2, [x28, #832]", - "str q2, [x21, #112]", + "str q2, [x21, #96]", "ldr q2, [x28, #848]", - "str q2, [x21, #128]", + "str q2, [x21, #112]", "ldr q2, [x28, #864]", + "str q2, [x21, #128]", + "ldr q2, [x28, #880]", "str q2, [x21, #144]", "ubfx x22, x20, #1, #1", "cbnz x22, #+0x8", @@ -1610,7 +1598,7 @@ "cbnz x22, #+0x8", "b #+0x84", "ldrh w22, [x20]", - "strh w22, [x28, #1008]", + "strh w22, [x28, #1024]", "ldrh w22, [x20, #2]", "ubfx w23, w22, #11, #3", "strb w23, [x28, #747]", @@ -1623,35 +1611,34 @@ "strb w25, [x28, #746]", "strb w22, [x28, #750]", "ldrb w22, [x20, #4]", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "ldr q2, [x20, #32]", - "str q2, [x28, #752]", - "ldr q2, [x20, #48]", "str q2, [x28, #768]", - "ldr q2, [x20, #64]", + "ldr q2, [x20, #48]", "str q2, [x28, #784]", - "ldr q2, [x20, #80]", + "ldr q2, [x20, #64]", "str q2, [x28, #800]", - "ldr q2, [x20, #96]", + "ldr q2, [x20, #80]", "str q2, [x28, #816]", - "ldr q2, [x20, #112]", + "ldr q2, [x20, #96]", "str q2, [x28, #832]", - "ldr q2, [x20, #128]", + "ldr q2, [x20, #112]", "str q2, [x28, #848]", - "ldr q2, [x20, #144]", + "ldr q2, [x20, #128]", "str q2, [x28, #864]", + "ldr q2, [x20, #144]", + "str q2, [x28, #880]", "b #+0x4c", "mov w22, #0x0", "mov w23, #0x37f", - "strh w23, [x28, #1008]", + "strh w23, [x28, #1024]", "strb w22, [x28, #747]", "strb w22, [x28, #744]", "strb w22, [x28, #745]", "strb w22, [x28, #746]", "strb w22, [x28, #750]", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "movi v2.2d, #0x0", - "str q2, [x28, #752]", "str q2, [x28, #768]", "str q2, [x28, #784]", "str q2, [x28, #800]", @@ -1659,6 +1646,7 @@ "str q2, [x28, #832]", "str q2, [x28, #848]", "str q2, [x28, #864]", + "str q2, [x28, #880]", "ubfx x22, x21, #1, #1", "cbnz x22, #+0x8", "b #+0x48", diff --git a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json index 2de195747..d9ea31488 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json @@ -14,7 +14,7 @@ }, "Instructions": { "xgetbv": { - "ExpectedInstructionCount": 50, + "ExpectedInstructionCount": 54, "Comment": "0xF 0x01 /2 RM-0", "ExpectedArm64ASM": [ "sub sp, sp, #0xf0 (240)", @@ -34,13 +34,15 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "ldr x0, [x28, #1096]", - "ldr x2, [x28, #1112]", + "ldr x0, [x28, #1112]", + "ldr x2, [x28, #1128]", "mov w1, w5", "blr x2", "ldr w4, [x28, #728]", @@ -58,6 +60,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -81,7 +85,7 @@ "str w0, [x28, #728]", "str x8, [x28, #40]", "mov w0, #0x100", - "str x0, [x28, #1040]", + "str x0, [x28, #1056]", "sub sp, sp, #0x10 (16)", "mov w8, #0xa8", "mov x0, sp", @@ -92,7 +96,7 @@ "ldr w8, [x28, #728]", "msr nzcv, x8", "ldr x8, [x28, #40]", - "str xzr, [x28, #1040]", + "str xzr, [x28, #1056]", "orr x5, x0, x1, lsl #12" ] } diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index f87363d2e..82e4900f8 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -13,7 +13,7 @@ }, "Instructions": { "ucomisd xmm0, xmm1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x66 0x0f 0x2e", "ExpectedArm64ASM": [ "mrs x20, nzcv", @@ -30,18 +30,16 @@ "msr nzcv, x20", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", - "eor w20, w21, #0x1", - "strb w20, [x28, #706]", - "mov w20, #0x0", - "mov w21, #0x90000000", - "mrs x22, nzcv", - "bic x21, x22, x21", - "strb w20, [x28, #708]", - "msr nzcv, x21" + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w20, #0x90000000", + "mrs x21, nzcv", + "bic x20, x21, x20", + "msr nzcv, x20" ] }, "comisd xmm0, xmm1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x66 0x0f 0x2f", "ExpectedArm64ASM": [ "mrs x20, nzcv", @@ -58,14 +56,12 @@ "msr nzcv, x20", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", - "eor w20, w21, #0x1", - "strb w20, [x28, #706]", - "mov w20, #0x0", - "mov w21, #0x90000000", - "mrs x22, nzcv", - "bic x21, x22, x21", - "strb w20, [x28, #708]", - "msr nzcv, x21" + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w20, #0x90000000", + "mrs x21, nzcv", + "bic x20, x21, x20", + "msr nzcv, x20" ] }, "pmovmskb eax, xmm0": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json index 8a33730e6..5e8037620 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json @@ -14,7 +14,7 @@ }, "Instructions": { "popcnt ax, bx": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "0xf3 0x0f 0xb8", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -23,18 +23,16 @@ "addp v0.8b, v0.8b, v0.8b", "umov w20, v0.b[0]", "bfxil x4, x20, #0, #16", - "mov w21, #0x0", - "mov w22, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x20, #0x0 (0)", "cset x20, eq", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", "lsl x20, x20, #30", "msr nzcv, x20" ] }, "popcnt eax, ebx": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0xf3 0x0f 0xb8", "ExpectedArm64ASM": [ "mov w20, w7", @@ -42,31 +40,27 @@ "cnt v0.8b, v0.8b", "addv b0, v0.8b", "umov w4, v0.b[0]", - "mov w20, #0x0", - "mov w21, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x4, #0x0 (0)", - "cset x22, eq", - "strb w21, [x28, #706]", - "strb w20, [x28, #708]", - "lsl x20, x22, #30", + "cset x20, eq", + "lsl x20, x20, #30", "msr nzcv, x20" ] }, "popcnt rax, rbx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0xf3 0x0f 0xb8", "ExpectedArm64ASM": [ "fmov d0, x7", "cnt v0.8b, v0.8b", "addv b0, v0.8b", "umov w4, v0.b[0]", - "mov w20, #0x0", - "mov w21, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x4, #0x0 (0)", - "cset x22, eq", - "strb w21, [x28, #706]", - "strb w20, [x28, #708]", - "lsl x20, x22, #30", + "cset x20, eq", + "lsl x20, x20, #30", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index 2cd56da40..8246c07ee 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -15,7 +15,7 @@ }, "Instructions": { "vucomiss xmm0, xmm1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": [ "Map 1 0b00 0x2e 128-bit" ], @@ -34,18 +34,16 @@ "msr nzcv, x20", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", - "eor w20, w21, #0x1", - "strb w20, [x28, #706]", - "mov w20, #0x0", - "mov w21, #0x90000000", - "mrs x22, nzcv", - "bic x21, x22, x21", - "strb w20, [x28, #708]", - "msr nzcv, x21" + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w20, #0x90000000", + "mrs x21, nzcv", + "bic x20, x21, x20", + "msr nzcv, x20" ] }, "vucomisd xmm0, xmm1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": [ "Map 1 0b01 0x2e 128-bit" ], @@ -64,18 +62,16 @@ "msr nzcv, x20", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", - "eor w20, w21, #0x1", - "strb w20, [x28, #706]", - "mov w20, #0x0", - "mov w21, #0x90000000", - "mrs x22, nzcv", - "bic x21, x22, x21", - "strb w20, [x28, #708]", - "msr nzcv, x21" + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w20, #0x90000000", + "mrs x21, nzcv", + "bic x20, x21, x20", + "msr nzcv, x20" ] }, "vcomiss xmm0, xmm1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": [ "Map 1 0b00 0x2f 128-bit" ], @@ -94,18 +90,16 @@ "msr nzcv, x20", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", - "eor w20, w21, #0x1", - "strb w20, [x28, #706]", - "mov w20, #0x0", - "mov w21, #0x90000000", - "mrs x22, nzcv", - "bic x21, x22, x21", - "strb w20, [x28, #708]", - "msr nzcv, x21" + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w20, #0x90000000", + "mrs x21, nzcv", + "bic x20, x21, x20", + "msr nzcv, x20" ] }, "vcomisd xmm0, xmm1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": [ "Map 1 0b01 0x2f 128-bit" ], @@ -124,14 +118,12 @@ "msr nzcv, x20", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", - "eor w20, w21, #0x1", - "strb w20, [x28, #706]", - "mov w20, #0x0", - "mov w21, #0x90000000", - "mrs x22, nzcv", - "bic x21, x22, x21", - "strb w20, [x28, #708]", - "msr nzcv, x21" + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w20, #0x90000000", + "mrs x21, nzcv", + "bic x20, x21, x20", + "msr nzcv, x20" ] }, "vpmovmskb rax, xmm0": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json index 96beab8f9..4feb53190 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map2.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json @@ -12,7 +12,7 @@ }, "Instructions": { "vtestps xmm0, xmm1": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 26, "Comment": [ "Map 2 0b01 0x0e 128-bit" ], @@ -29,26 +29,24 @@ "addv h2, v2.8h", "umov w20, v3.h[0]", "umov w21, v2.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", - "mrs x24, nzcv", + "mov w27, #0x0", + "mov w26, #0x1", + "mrs x22, nzcv", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", - "msr nzcv, x24", + "msr nzcv, x22", "rmif x20, #62, #nZcv", "rmif x21, #63, #nzCv", "mov w20, #0x90000000", "mrs x21, nzcv", "bic x20, x21, x20", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, "vtestps ymm0, ymm1": { - "ExpectedInstructionCount": 36, + "ExpectedInstructionCount": 34, "Comment": [ "Map 2 0b01 0x0e 256-bit" ], @@ -73,26 +71,24 @@ "add v2.8h, v0.8h, v1.8h", "umov w20, v3.h[0]", "umov w21, v2.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", - "mrs x24, nzcv", + "mov w27, #0x0", + "mov w26, #0x1", + "mrs x22, nzcv", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", - "msr nzcv, x24", + "msr nzcv, x22", "rmif x20, #62, #nZcv", "rmif x21, #63, #nzCv", "mov w20, #0x90000000", "mrs x21, nzcv", "bic x20, x21, x20", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, "vtestpd xmm0, xmm1": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 26, "Comment": [ "Map 2 0b01 0x0f 128-bit" ], @@ -109,26 +105,24 @@ "addv h2, v2.8h", "umov w20, v3.h[0]", "umov w21, v2.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", - "mrs x24, nzcv", + "mov w27, #0x0", + "mov w26, #0x1", + "mrs x22, nzcv", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", - "msr nzcv, x24", + "msr nzcv, x22", "rmif x20, #62, #nZcv", "rmif x21, #63, #nzCv", "mov w20, #0x90000000", "mrs x21, nzcv", "bic x20, x21, x20", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, "vtestpd ymm0, ymm1": { - "ExpectedInstructionCount": 36, + "ExpectedInstructionCount": 34, "Comment": [ "Map 2 0b01 0x0f 256-bit" ], @@ -153,26 +147,24 @@ "add v2.8h, v0.8h, v1.8h", "umov w20, v3.h[0]", "umov w21, v2.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", - "mrs x24, nzcv", + "mov w27, #0x0", + "mov w26, #0x1", + "mrs x22, nzcv", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", - "msr nzcv, x24", + "msr nzcv, x22", "rmif x20, #62, #nZcv", "rmif x21, #63, #nzCv", "mov w20, #0x90000000", "mrs x21, nzcv", "bic x20, x21, x20", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, "vptest xmm0, xmm1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": [ "Map 2 0b01 0x16 128-bit" ], @@ -185,21 +177,19 @@ "addv h3, v3.8h", "umov w20, v2.h[0]", "umov w21, v3.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", "lsl x20, x20, #30", "orr w20, w20, w21, lsl #29", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, "vptest ymm0, ymm1": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 25, "Comment": [ "Map 2 0b01 0x16 256-bit" ], @@ -220,16 +210,14 @@ "add v3.8h, v0.8h, v1.8h", "umov w20, v2.h[0]", "umov w21, v3.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", "lsl x20, x20, #30", "orr w20, w20, w21, lsl #29", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, @@ -438,7 +426,7 @@ "mov w20, w7", "mov w21, w5", "bic w4, w21, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -449,7 +437,7 @@ ], "ExpectedArm64ASM": [ "bic x4, x5, x7", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 76a4083b3..1f1cf4834 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -14,7 +14,7 @@ }, "Instructions": { "fadd dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /0" ], @@ -31,6 +31,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -44,8 +46,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -67,11 +69,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -82,6 +86,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -94,12 +100,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -121,15 +127,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /1" ], @@ -146,6 +154,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -159,8 +169,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -182,11 +192,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -197,6 +209,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -209,12 +223,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -236,15 +250,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcom dword [rax]": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 121, "Comment": [ "0xd8 !11b /2" ], @@ -261,6 +277,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -274,8 +292,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -297,11 +315,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -312,6 +332,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -324,12 +346,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -351,6 +373,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -365,7 +389,7 @@ ] }, "fcomp dword [rax]": { - "ExpectedInstructionCount": 121, + "ExpectedInstructionCount": 129, "Comment": [ "0xd8 !11b /3" ], @@ -382,6 +406,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -395,8 +421,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -418,11 +444,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -433,6 +461,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -445,12 +475,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -472,6 +502,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -483,18 +515,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fsub dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /4" ], @@ -511,6 +543,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -524,8 +558,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -547,11 +581,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -562,6 +598,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -574,12 +612,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -601,15 +639,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /5" ], @@ -626,6 +666,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -639,8 +681,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -662,11 +704,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -677,6 +721,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -689,12 +735,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -716,15 +762,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /6" ], @@ -741,6 +789,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -754,8 +804,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -777,11 +827,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -792,6 +844,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -804,12 +858,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -831,15 +885,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /7" ], @@ -856,6 +912,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -869,8 +927,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -892,11 +950,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -907,6 +967,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -919,12 +981,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -946,15 +1008,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc0 /0" ], @@ -963,9 +1027,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -976,6 +1040,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -988,12 +1054,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1015,15 +1081,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc1 /0" ], @@ -1032,9 +1100,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1045,6 +1113,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1057,12 +1127,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1084,15 +1154,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc2 /0" ], @@ -1101,9 +1173,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1114,6 +1186,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1126,12 +1200,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1153,15 +1227,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc3 /0" ], @@ -1170,9 +1246,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1183,6 +1259,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1195,12 +1273,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1222,15 +1300,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc4 /0" ], @@ -1239,9 +1319,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1252,6 +1332,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1264,12 +1346,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1291,15 +1373,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc5 /0" ], @@ -1308,9 +1392,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1321,6 +1405,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1333,12 +1419,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1360,15 +1446,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc6 /0" ], @@ -1377,9 +1465,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1390,6 +1478,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1402,12 +1492,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1429,15 +1519,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc7 /0" ], @@ -1446,9 +1538,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1459,6 +1551,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1471,12 +1565,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1498,15 +1592,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc8 /1" ], @@ -1515,9 +1611,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1528,6 +1624,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1540,12 +1638,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1567,15 +1665,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc9 /1" ], @@ -1584,9 +1684,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1597,6 +1697,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1609,12 +1711,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1636,15 +1738,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xca /1" ], @@ -1653,9 +1757,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1666,6 +1770,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1678,12 +1784,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1705,15 +1811,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xcb /1" ], @@ -1722,9 +1830,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1735,6 +1843,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1747,12 +1857,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1774,15 +1884,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xcc /1" ], @@ -1791,9 +1903,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1804,6 +1916,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1816,12 +1930,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1843,15 +1957,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xcd /1" ], @@ -1860,9 +1976,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1873,6 +1989,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1885,12 +2003,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1912,15 +2030,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xce /1" ], @@ -1929,9 +2049,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1942,6 +2062,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1954,12 +2076,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1981,15 +2103,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xcf /1" ], @@ -1998,9 +2122,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2011,6 +2135,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2023,12 +2149,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2050,15 +2176,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd0 /2" ], @@ -2068,9 +2196,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2081,6 +2209,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2093,12 +2223,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2120,6 +2250,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x22, x20, #1, #1", "ubfx x23, x20, #0, #1", @@ -2133,7 +2265,7 @@ ] }, "fcom st0, st1": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd1 /2" ], @@ -2142,9 +2274,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2155,6 +2287,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2167,12 +2301,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2194,6 +2328,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2208,7 +2344,7 @@ ] }, "fcom st0, st2": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd2 /2" ], @@ -2217,9 +2353,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2230,6 +2366,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2242,12 +2380,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2269,6 +2407,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2283,7 +2423,7 @@ ] }, "fcom st0, st3": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd3 /2" ], @@ -2292,9 +2432,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2305,6 +2445,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2317,12 +2459,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2344,6 +2486,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2358,7 +2502,7 @@ ] }, "fcom st0, st4": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd4 /2" ], @@ -2367,9 +2511,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2380,6 +2524,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2392,12 +2538,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2419,6 +2565,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2433,7 +2581,7 @@ ] }, "fcom st0, st5": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd5 /2" ], @@ -2442,9 +2590,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2455,6 +2603,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2467,12 +2617,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2494,6 +2644,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2508,7 +2660,7 @@ ] }, "fcom st0, st6": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd6 /2" ], @@ -2517,9 +2669,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2530,6 +2682,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2542,12 +2696,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2569,6 +2723,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2583,7 +2739,7 @@ ] }, "fcom st0, st7": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd7 /2" ], @@ -2592,9 +2748,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2605,6 +2761,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2617,12 +2775,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2644,6 +2802,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2658,7 +2818,7 @@ ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xd8 /3" ], @@ -2668,9 +2828,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2681,6 +2841,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2693,12 +2855,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2720,6 +2882,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -2730,18 +2894,18 @@ "strb w21, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st1": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xd9 /3" ], @@ -2751,9 +2915,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2764,6 +2928,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2776,12 +2942,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2803,6 +2969,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -2814,17 +2982,17 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st2": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xda /3" ], @@ -2833,9 +3001,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2846,6 +3014,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2858,12 +3028,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2885,6 +3055,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -2896,18 +3068,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st3": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xdb /3" ], @@ -2916,9 +3088,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2929,6 +3101,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2941,12 +3115,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2968,6 +3142,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -2979,18 +3155,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st4": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xdc /3" ], @@ -2999,9 +3175,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3012,6 +3188,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3024,12 +3202,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3051,6 +3229,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -3062,18 +3242,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st5": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xdd /3" ], @@ -3082,9 +3262,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3095,6 +3275,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3107,12 +3289,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3134,6 +3316,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -3145,18 +3329,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st6": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xde /3" ], @@ -3165,9 +3349,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3178,6 +3362,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3190,12 +3376,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3217,6 +3403,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -3228,18 +3416,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st7": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xdf /3" ], @@ -3248,9 +3436,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3261,6 +3449,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3273,12 +3463,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3300,6 +3490,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -3311,18 +3503,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fsub st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe0 /4" ], @@ -3331,9 +3523,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3344,6 +3536,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3356,12 +3550,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3383,15 +3577,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe1 /4" ], @@ -3400,9 +3596,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3413,6 +3609,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3425,12 +3623,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3452,15 +3650,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe2 /4" ], @@ -3469,9 +3669,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3482,6 +3682,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3494,12 +3696,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3521,15 +3723,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe3 /4" ], @@ -3538,9 +3742,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3551,6 +3755,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3563,12 +3769,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3590,15 +3796,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe4 /4" ], @@ -3607,9 +3815,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3620,6 +3828,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3632,12 +3842,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3659,15 +3869,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe5 /4" ], @@ -3676,9 +3888,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3689,6 +3901,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3701,12 +3915,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3728,15 +3942,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe6 /4" ], @@ -3745,9 +3961,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3758,6 +3974,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3770,12 +3988,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3797,15 +4015,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe7 /4" ], @@ -3814,9 +4034,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3827,6 +4047,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3839,12 +4061,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3866,15 +4088,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe8 /5" ], @@ -3883,9 +4107,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3896,6 +4120,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3908,12 +4134,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3935,15 +4161,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe9 /5" ], @@ -3952,9 +4180,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3965,6 +4193,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3977,12 +4207,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4004,15 +4234,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xea /5" ], @@ -4021,9 +4253,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4034,6 +4266,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4046,12 +4280,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4073,15 +4307,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xeb /5" ], @@ -4090,9 +4326,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4103,6 +4339,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4115,12 +4353,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4142,15 +4380,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xec /5" ], @@ -4159,9 +4399,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4172,6 +4412,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4184,12 +4426,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4211,15 +4453,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xed /5" ], @@ -4228,9 +4472,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4241,6 +4485,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4253,12 +4499,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4280,15 +4526,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xee /5" ], @@ -4297,9 +4545,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4310,6 +4558,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4322,12 +4572,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4349,15 +4599,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xef /5" ], @@ -4366,9 +4618,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4379,6 +4631,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4391,12 +4645,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4418,15 +4672,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf0 /6" ], @@ -4435,9 +4691,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4448,6 +4704,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4460,12 +4718,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4487,15 +4745,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf1 /6" ], @@ -4504,9 +4764,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4517,6 +4777,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4529,12 +4791,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4556,15 +4818,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf2 /6" ], @@ -4573,9 +4837,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4586,6 +4850,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4598,12 +4864,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4625,15 +4891,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf3 /6" ], @@ -4642,9 +4910,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4655,6 +4923,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4667,12 +4937,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4694,15 +4964,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf4 /6" ], @@ -4711,9 +4983,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4724,6 +4996,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4736,12 +5010,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4763,15 +5037,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf5 /6" ], @@ -4780,9 +5056,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4793,6 +5069,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4805,12 +5083,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4832,15 +5110,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf6 /6" ], @@ -4849,9 +5129,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4862,6 +5142,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4874,12 +5156,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4901,15 +5183,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf7 /6" ], @@ -4918,9 +5202,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4931,6 +5215,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4943,12 +5229,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4970,15 +5256,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf8 /7" ], @@ -4987,9 +5275,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5000,6 +5288,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5012,12 +5302,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5039,15 +5329,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf9 /7" ], @@ -5056,9 +5348,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5069,6 +5361,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5081,12 +5375,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5108,15 +5402,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xfa /7" ], @@ -5125,9 +5421,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5138,6 +5434,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5150,12 +5448,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5177,15 +5475,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xfb /7" ], @@ -5194,9 +5494,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5207,6 +5507,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5219,12 +5521,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5246,15 +5548,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xfc /7" ], @@ -5263,9 +5567,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5276,6 +5580,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5288,12 +5594,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5315,15 +5621,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xfd /7" ], @@ -5332,9 +5640,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5345,6 +5653,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5357,12 +5667,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5384,15 +5694,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xfe /7" ], @@ -5401,9 +5713,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5414,6 +5726,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5426,12 +5740,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5453,15 +5767,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xff /7" ], @@ -5470,9 +5786,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5483,6 +5799,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5495,12 +5813,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5522,15 +5840,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld dword [rax]": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd9 !11b /0" ], @@ -5547,6 +5867,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5560,8 +5882,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5583,30 +5905,32 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst dword [rax]": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 56, "Comment": [ "0xd9 !11b /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5617,6 +5941,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5629,10 +5955,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1160]", + "ldr x3, [x28, #1176]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5654,19 +5980,21 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "fmov s2, s0", "str s2, [x4]" ] }, "fstp dword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xd9 !11b /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5677,6 +6005,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5689,10 +6019,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1160]", + "ldr x3, [x28, #1176]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5714,13 +6044,15 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "fmov s2, s0", "str s2, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -5733,7 +6065,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -5778,7 +6110,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1010]", + "strb w20, [x28, #1026]", "msr nzcv, x22" ] }, @@ -5789,7 +6121,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1008]" + "strh w20, [x28, #1024]" ] }, "fnstenv [rax]": { @@ -5798,7 +6130,7 @@ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1008]", + "ldrh w20, [x28, #1024]", "str w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -5814,7 +6146,7 @@ "orr x21, x21, x24, lsl #10", "orr x21, x21, x25, lsl #14", "str w21, [x4, #4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "and w22, w21, #0x1", "mov w23, #0x3", "mrs x24, nzcv", @@ -5870,7 +6202,7 @@ "0xd9 !11b /7" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1008]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]" ] }, @@ -5884,17 +6216,17 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st1": { @@ -5908,16 +6240,16 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st2": { @@ -5930,17 +6262,17 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st3": { @@ -5953,17 +6285,17 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st4": { @@ -5976,17 +6308,17 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st5": { @@ -5999,17 +6331,17 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st6": { @@ -6022,17 +6354,17 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st7": { @@ -6045,17 +6377,17 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st0": { @@ -6068,13 +6400,13 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st1": { @@ -6087,13 +6419,13 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st2": { @@ -6106,13 +6438,13 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st3": { @@ -6125,13 +6457,13 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st4": { @@ -6144,13 +6476,13 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st5": { @@ -6163,13 +6495,13 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st6": { @@ -6182,13 +6514,13 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st7": { @@ -6201,13 +6533,13 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fnop": { @@ -6225,14 +6557,14 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x0", "mov w22, #0x8000", "fmov d3, x21", "mov v3.d[1], x22", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fabs": { @@ -6243,25 +6575,25 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov x21, #0xffffffffffffffff", "mov w22, #0x7fff", "fmov d3, x21", "mov v3.d[1], x22", "and v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "ftst": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 68, "Comment": [ "0xd9 11b 0xe4 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w20, #0x0", "fmov d3, x20", "mrs x0, nzcv", @@ -6274,6 +6606,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -6286,12 +6620,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6313,6 +6647,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -6333,11 +6669,11 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov x21, v2.d[1]", "ubfx x21, x21, #15, #1", "strb w21, [x28, #745]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "lsr w20, w21, w20", "and w20, w20, #0x1", "mrs x21, nzcv", @@ -6359,17 +6695,17 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x8000000000000000", "mov w22, #0x3fff", "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldl2t": { @@ -6382,10 +6718,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x8afe", "movk x21, #0xcd1b, lsl #16", @@ -6395,7 +6731,7 @@ "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldl2e": { @@ -6408,10 +6744,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xf0bc", "movk x21, #0x5c17, lsl #16", @@ -6421,7 +6757,7 @@ "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldpi": { @@ -6434,10 +6770,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xc235", "movk x21, #0x2168, lsl #16", @@ -6447,7 +6783,7 @@ "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldlg2": { @@ -6460,10 +6796,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xf799", "movk x21, #0xfbcf, lsl #16", @@ -6473,7 +6809,7 @@ "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldln2": { @@ -6486,10 +6822,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x79ac", "movk x21, #0xd1cf, lsl #16", @@ -6499,7 +6835,7 @@ "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldz": { @@ -6512,27 +6848,27 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov w21, #0x0", "fmov d2, x21", "mov v2.d[1], x21", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "f2xm1": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 59, "Comment": [ "0xd9 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -6543,6 +6879,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -6555,10 +6893,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1328]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6580,32 +6918,34 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fyl2x": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd9 11b 0xf1 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -6616,6 +6956,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -6628,353 +6970,7 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "mov x3, v3.d[0]", - "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fptan": { - "ExpectedInstructionCount": 71, - "Comment": [ - "0xd9 11b 0xf2 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1320]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "mov x21, #0x8000000000000000", - "mov w23, #0x3fff", - "fmov d3, x21", - "mov v3.d[1], x23", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str q3, [x0, #752]" - ] - }, - "fpatan": { - "ExpectedInstructionCount": 67, - "Comment": [ - "0xd9 11b 0xf3 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1010]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fxtract": { - "ExpectedInstructionCount": 115, - "Comment": [ - "0xd9 11b 0xf4 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1352]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v3.16b, v3.16b, v3.16b", - "mov v3.d[0], x0", - "mov v3.h[4], w1", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1360]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fprem1": { - "ExpectedInstructionCount": 63, - "Comment": [ - "0xd9 11b 0xf5 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", @@ -7001,13 +6997,381 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fptan": { + "ExpectedInstructionCount": 75, + "Comment": [ + "0xd9 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1336]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x21, #0x8000000000000000", + "mov w23, #0x3fff", + "fmov d3, x21", + "mov v3.d[1], x23", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str q3, [x0, #768]" + ] + }, + "fpatan": { + "ExpectedInstructionCount": 71, + "Comment": [ + "0xd9 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1026]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1026]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1440]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fxtract": { + "ExpectedInstructionCount": 123, + "Comment": [ + "0xd9 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1368]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1376]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fprem1": { + "ExpectedInstructionCount": 67, + "Comment": [ + "0xd9 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1448]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "mov w21, #0x0", "strb w21, [x28, #746]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdecstp": { @@ -7035,7 +7399,7 @@ ] }, "fprem": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 67, "Comment": [ "0xd9 11b 0xf8 /7" ], @@ -7044,9 +7408,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7057,6 +7421,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7069,12 +7435,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1440]", + "ldr x5, [x28, #1456]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7096,34 +7462,36 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "mov w21, #0x0", "strb w21, [x28, #746]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fyl2xp1": { - "ExpectedInstructionCount": 123, + "ExpectedInstructionCount": 131, "Comment": [ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mov x20, #0x8000000000000000", "mov w22, #0x3fff", "fmov d4, x20", @@ -7138,6 +7506,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7150,12 +7520,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v4.d[0]", "umov w4, v4.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7177,6 +7547,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7190,6 +7562,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7202,11 +7576,735 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", + "ldr x5, [x28, #1432]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fsqrt": { + "ExpectedInstructionCount": 59, + "Comment": [ + "0xd9 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1344]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fsincos": { + "ExpectedInstructionCount": 125, + "Comment": [ + "0xd9 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1352]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1360]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #768]" + ] + }, + "frndint": { + "ExpectedInstructionCount": 59, + "Comment": [ + "0xd9 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1320]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fscale": { + "ExpectedInstructionCount": 65, + "Comment": [ + "0xd9 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1464]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fsin": { + "ExpectedInstructionCount": 61, + "Comment": [ + "0xd9 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1352]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fcos": { + "ExpectedInstructionCount": 61, + "Comment": [ + "0xd9 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1360]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fiadd dword [rax]": { + "ExpectedInstructionCount": 115, + "Comment": [ + "0xda !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov w1, w21", + "ldr x2, [x28, #1312]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fimul dword [rax]": { + "ExpectedInstructionCount": 115, + "Comment": [ + "0xda !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov w1, w21", + "ldr x2, [x28, #1312]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", @@ -7229,695 +8327,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fsqrt": { - "ExpectedInstructionCount": 55, - "Comment": [ - "0xd9 11b 0xfa /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1328]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fsincos": { - "ExpectedInstructionCount": 117, - "Comment": [ - "0xd9 11b 0xfb /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1336]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v3.16b, v3.16b, v3.16b", - "mov v3.d[0], x0", - "mov v3.h[4], w1", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1344]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" - ] - }, - "frndint": { - "ExpectedInstructionCount": 55, - "Comment": [ - "0xd9 11b 0xfc /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1304]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fscale": { - "ExpectedInstructionCount": 61, - "Comment": [ - "0xd9 11b 0xfd /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "mov x3, v3.d[0]", - "umov w4, v3.h[4]", - "ldr x5, [x28, #1448]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fsin": { - "ExpectedInstructionCount": 57, - "Comment": [ - "0xd9 11b 0xfe /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1336]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fcos": { - "ExpectedInstructionCount": 57, - "Comment": [ - "0xd9 11b 0xff /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1344]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fiadd dword [rax]": { - "ExpectedInstructionCount": 107, - "Comment": [ - "0xda !11b /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldr w21, [x4]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov w1, w21", - "ldr x2, [x28, #1296]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fimul dword [rax]": { - "ExpectedInstructionCount": 107, - "Comment": [ - "0xda !11b /1" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldr w21, [x4]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov w1, w21", - "ldr x2, [x28, #1296]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "ficom dword [rax]": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 121, "Comment": [ "0xda !11b /2" ], @@ -7934,6 +8354,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7946,9 +8368,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7970,11 +8392,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7985,6 +8409,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7997,12 +8423,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8024,6 +8450,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -8038,7 +8466,7 @@ ] }, "ficomp dword [rax]": { - "ExpectedInstructionCount": 121, + "ExpectedInstructionCount": 129, "Comment": [ "0xda !11b /3" ], @@ -8055,6 +8483,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8067,9 +8497,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8091,11 +8521,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -8106,6 +8538,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8118,12 +8552,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8145,6 +8579,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -8156,18 +8592,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fisub dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xda !11b /4" ], @@ -8184,6 +8620,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8196,9 +8634,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8220,11 +8658,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -8235,6 +8675,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8247,12 +8689,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8274,15 +8716,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fisubr dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xda !11b /5" ], @@ -8299,6 +8743,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8311,9 +8757,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8335,11 +8781,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -8350,6 +8798,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8362,12 +8812,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8389,15 +8839,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fidiv dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xda !11b /6" ], @@ -8414,6 +8866,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8426,9 +8880,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8450,11 +8904,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -8465,6 +8921,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8477,12 +8935,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8504,15 +8962,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fidivr dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xda !11b /7" ], @@ -8529,6 +8989,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8541,9 +9003,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8565,11 +9027,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -8580,6 +9044,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8592,12 +9058,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8619,11 +9085,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st0": { @@ -8638,12 +9106,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st1": { @@ -8658,12 +9126,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st2": { @@ -8678,12 +9146,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st3": { @@ -8698,12 +9166,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st4": { @@ -8718,12 +9186,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st5": { @@ -8738,12 +9206,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st6": { @@ -8758,12 +9226,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st7": { @@ -8778,12 +9246,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st0": { @@ -8798,12 +9266,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st1": { @@ -8818,12 +9286,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st2": { @@ -8838,12 +9306,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st3": { @@ -8858,12 +9326,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st4": { @@ -8878,12 +9346,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st5": { @@ -8898,12 +9366,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st6": { @@ -8918,12 +9386,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st7": { @@ -8938,12 +9406,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st0": { @@ -8960,12 +9428,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st1": { @@ -8982,12 +9450,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st2": { @@ -9004,12 +9472,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st3": { @@ -9026,12 +9494,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st4": { @@ -9048,12 +9516,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st5": { @@ -9070,12 +9538,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st6": { @@ -9092,12 +9560,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st7": { @@ -9114,22 +9582,21 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovu st0, st0": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xd8 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9140,23 +9607,22 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xd9 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9167,23 +9633,22 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st2": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xda /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9194,23 +9659,22 @@ "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st3": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdb /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9221,23 +9685,22 @@ "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st4": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdc /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9248,23 +9711,22 @@ "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st5": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdd /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9275,23 +9737,22 @@ "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st6": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xde /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9302,23 +9763,22 @@ "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st7": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdf /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9329,17 +9789,17 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fucompp": { - "ExpectedInstructionCount": 80, + "ExpectedInstructionCount": 84, "Comment": [ "0xda 11b 0xe9 /5" ], @@ -9349,9 +9809,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -9362,6 +9822,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -9374,12 +9836,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9401,6 +9863,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -9412,22 +9876,22 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fild dword [rax]": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 35, "Comment": [ "0xdf !11b /5" ], @@ -9436,47 +9900,48 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr w21, [x4]", "mov w22, #0x0", "sxtw x21, w21", - "mrs x23, nzcv", + "mrs x22, nzcv", "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", + "mov w23, #0x8000", + "csel x23, x23, xzr, lt", "cneg x21, x21, mi", - "mov w25, #0x3f", + "mov w24, #0x3f", "mov x0, #0x3f", - "clz x26, x21", - "sub x26, x0, x26", - "sub x25, x25, x26", - "lsl x26, x21, x25", - "mov w27, #0x403e", - "sub x25, x27, x25", + "clz x25, x21", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x21, x24", + "mov w30, #0x403e", + "sub x24, x30, x24", + "mov w30, #0x0", "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x26", + "csel x21, x30, x24, eq", + "orr x21, x23, x21", + "fmov d2, x25", "fmov d3, x21", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", - "msr nzcv, x23" + "str q2, [x0, #768]", + "msr nzcv, x22" ] }, "fisttp dword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdb !11b /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -9487,6 +9952,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -9499,10 +9966,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1208]", + "ldr x3, [x28, #1224]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9524,27 +9991,29 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov w21, w0", "str w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fist dword [rax]": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 56, "Comment": [ "0xdb !11b /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -9555,6 +10024,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -9567,10 +10038,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1184]", + "ldr x3, [x28, #1200]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9592,19 +10063,21 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov w20, w0", "str w20, [x4]" ] }, "fistp dword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdf !11b /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -9615,6 +10088,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -9627,10 +10102,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1184]", + "ldr x3, [x28, #1200]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9652,13 +10127,15 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov w21, w0", "str w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -9675,13 +10152,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fstp tword [rax]": { @@ -9692,15 +10169,15 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -9718,12 +10195,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st1": { @@ -9738,12 +10215,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st2": { @@ -9758,12 +10235,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st3": { @@ -9778,12 +10255,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st4": { @@ -9798,12 +10275,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st5": { @@ -9818,12 +10295,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st6": { @@ -9838,12 +10315,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st7": { @@ -9858,12 +10335,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st0": { @@ -9878,12 +10355,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st1": { @@ -9898,12 +10375,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st2": { @@ -9918,12 +10395,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st3": { @@ -9938,12 +10415,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st4": { @@ -9958,12 +10435,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st5": { @@ -9978,12 +10455,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st6": { @@ -9998,12 +10475,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st7": { @@ -10018,12 +10495,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st0": { @@ -10039,12 +10516,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st1": { @@ -10060,12 +10537,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st2": { @@ -10081,12 +10558,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st3": { @@ -10102,12 +10579,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st4": { @@ -10123,12 +10600,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st5": { @@ -10144,12 +10621,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st6": { @@ -10165,12 +10642,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st7": { @@ -10186,22 +10663,21 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnu st0, st0": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xd8 /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10212,23 +10688,22 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xd9 /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10239,23 +10714,22 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st2": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xda /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10266,23 +10740,22 @@ "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st3": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdb /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10293,23 +10766,22 @@ "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st4": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdc /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10320,23 +10792,22 @@ "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st5": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdd /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10347,23 +10818,22 @@ "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st6": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xde /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10374,23 +10844,22 @@ "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st7": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdf /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10401,12 +10870,12 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, @@ -10425,17 +10894,17 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x37f", - "strh w21, [x28, #1008]", + "strh w21, [x28, #1024]", "strb w20, [x28, #747]", "strb w20, [x28, #744]", "strb w20, [x28, #745]", "strb w20, [x28, #746]", "strb w20, [x28, #750]", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xe8 /5" ], @@ -10444,9 +10913,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10457,6 +10926,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10469,12 +10940,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10496,6 +10967,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10504,12 +10977,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fucomi st0, st1": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xe9 /5" ], @@ -10518,9 +10990,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10531,6 +11003,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10543,12 +11017,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10570,6 +11044,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10578,12 +11054,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fucomi st0, st2": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xea /5" ], @@ -10592,9 +11067,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10605,6 +11080,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10617,12 +11094,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10644,6 +11121,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10652,12 +11131,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fucomi st0, st3": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xeb /5" ], @@ -10666,9 +11144,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10679,6 +11157,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10691,12 +11171,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10718,6 +11198,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10726,12 +11208,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fucomi st0, st4": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xec /5" ], @@ -10740,9 +11221,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10753,6 +11234,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10765,12 +11248,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10792,6 +11275,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10800,12 +11285,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fucomi st0, st5": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xed /5" ], @@ -10814,9 +11298,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10827,6 +11311,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10839,12 +11325,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10866,6 +11352,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10874,12 +11362,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fucomi st0, st6": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xee /5" ], @@ -10888,9 +11375,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10901,6 +11388,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10913,12 +11402,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10940,6 +11429,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10948,12 +11439,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fucomi st0, st7": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xef /5" ], @@ -10962,9 +11452,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10975,6 +11465,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10987,12 +11479,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11014,6 +11506,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11022,12 +11516,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xf0 /6" ], @@ -11036,9 +11529,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11049,6 +11542,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11061,12 +11556,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11088,6 +11583,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11096,12 +11593,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fcomi st0, st1": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xf1 /6" ], @@ -11110,9 +11606,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11123,6 +11619,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11135,12 +11633,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11162,6 +11660,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11170,12 +11670,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fcomi st0, st2": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xf2 /6" ], @@ -11184,9 +11683,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11197,6 +11696,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11209,12 +11710,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11236,6 +11737,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11244,12 +11747,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fcomi st0, st3": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xf3 /6" ], @@ -11258,9 +11760,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11271,6 +11773,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11283,12 +11787,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11310,6 +11814,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11318,12 +11824,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fcomi st0, st4": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xf4 /6" ], @@ -11332,9 +11837,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11345,6 +11850,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11357,12 +11864,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11384,6 +11891,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11392,12 +11901,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fcomi st0, st5": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xf5 /6" ], @@ -11406,9 +11914,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11419,6 +11927,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11431,12 +11941,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11458,6 +11968,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11466,12 +11978,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fcomi st0, st6": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xf6 /6" ], @@ -11480,9 +11991,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11493,6 +12004,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11505,12 +12018,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11532,6 +12045,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11540,12 +12055,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fcomi st0, st7": { - "ExpectedInstructionCount": 66, + "ExpectedInstructionCount": 69, "Comment": [ "0xdb 11b 0xf7 /6" ], @@ -11554,9 +12068,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11567,6 +12081,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11579,12 +12095,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11606,6 +12122,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11614,12 +12132,11 @@ "orr w22, w22, w20", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]" + "eor w26, w20, #0x1" ] }, "fadd qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /0" ], @@ -11636,6 +12153,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11649,8 +12168,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11672,11 +12191,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11687,6 +12208,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11699,12 +12222,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11726,15 +12249,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /1" ], @@ -11751,6 +12276,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11764,8 +12291,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11787,11 +12314,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11802,6 +12331,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11814,12 +12345,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11841,15 +12372,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcom qword [rax]": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 121, "Comment": [ "0xdc !11b /2" ], @@ -11866,6 +12399,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11879,8 +12414,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11902,11 +12437,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11917,6 +12454,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11929,12 +12468,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11956,6 +12495,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11970,7 +12511,7 @@ ] }, "fcomp qword [rax]": { - "ExpectedInstructionCount": 121, + "ExpectedInstructionCount": 129, "Comment": [ "0xdc !11b /3" ], @@ -11987,6 +12528,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12000,8 +12543,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12023,11 +12566,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12038,6 +12583,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12050,12 +12597,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12077,6 +12624,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -12088,18 +12637,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fsub qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /4" ], @@ -12116,6 +12665,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12129,8 +12680,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12152,11 +12703,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12167,6 +12720,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12179,12 +12734,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12206,15 +12761,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /5" ], @@ -12231,6 +12788,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12244,8 +12803,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12267,11 +12826,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12282,6 +12843,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12294,12 +12857,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12321,15 +12884,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /6" ], @@ -12346,6 +12911,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12359,8 +12926,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12382,11 +12949,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12397,6 +12966,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12409,12 +12980,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12436,15 +13007,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /7" ], @@ -12461,6 +13034,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12474,8 +13049,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12497,11 +13072,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12512,6 +13089,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12524,12 +13103,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12551,15 +13130,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xc0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fadd st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -12570,9 +13151,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12583,6 +13164,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12595,12 +13178,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12622,15 +13205,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc1 /0" ], @@ -12639,9 +13224,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12652,6 +13237,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12664,12 +13251,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12691,15 +13278,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc2 /0" ], @@ -12708,9 +13297,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12721,6 +13310,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12733,12 +13324,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12760,15 +13351,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc3 /0" ], @@ -12777,9 +13370,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12790,6 +13383,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12802,12 +13397,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12829,15 +13424,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc4 /0" ], @@ -12846,9 +13443,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12859,6 +13456,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12871,12 +13470,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12898,15 +13497,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc5 /0" ], @@ -12915,9 +13516,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12928,6 +13529,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12940,12 +13543,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12967,15 +13570,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc6 /0" ], @@ -12984,9 +13589,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12997,6 +13602,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13009,12 +13616,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13036,15 +13643,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc7 /0" ], @@ -13053,9 +13662,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13066,6 +13675,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13078,12 +13689,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13105,15 +13716,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xc8": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fmul st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -13124,9 +13737,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13137,6 +13750,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13149,12 +13764,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13176,15 +13791,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc9 /1" ], @@ -13193,9 +13810,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13206,6 +13823,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13218,12 +13837,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13245,15 +13864,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xca /1" ], @@ -13262,9 +13883,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13275,6 +13896,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13287,12 +13910,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13314,15 +13937,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xcb /1" ], @@ -13331,9 +13956,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13344,6 +13969,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13356,12 +13983,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13383,15 +14010,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xcc /1" ], @@ -13400,9 +14029,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13413,6 +14042,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13425,12 +14056,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13452,15 +14083,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xcd /1" ], @@ -13469,9 +14102,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13482,6 +14115,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13494,12 +14129,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13521,15 +14156,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xce /1" ], @@ -13538,9 +14175,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13551,6 +14188,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13563,12 +14202,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13590,15 +14229,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xcf /1" ], @@ -13607,9 +14248,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13620,6 +14261,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13632,12 +14275,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13659,15 +14302,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xe0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fsubr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -13678,9 +14323,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13691,6 +14336,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13703,12 +14350,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13730,15 +14377,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe1 /4" ], @@ -13747,9 +14396,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13760,6 +14409,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13772,12 +14423,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13799,15 +14450,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe2 /4" ], @@ -13816,9 +14469,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13829,6 +14482,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13841,12 +14496,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13868,15 +14523,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe3 /4" ], @@ -13885,9 +14542,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13898,6 +14555,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13910,12 +14569,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13937,15 +14596,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe4 /4" ], @@ -13954,9 +14615,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13967,6 +14628,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13979,12 +14642,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14006,15 +14669,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe5 /4" ], @@ -14023,9 +14688,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14036,6 +14701,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14048,12 +14715,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14075,15 +14742,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe6 /4" ], @@ -14092,9 +14761,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14105,6 +14774,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14117,12 +14788,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14144,15 +14815,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe7 /4" ], @@ -14161,9 +14834,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14174,6 +14847,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14186,12 +14861,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14213,15 +14888,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xe8": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fsub st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -14232,9 +14909,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14245,6 +14922,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14257,12 +14936,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14284,15 +14963,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe9 /5" ], @@ -14301,9 +14982,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14314,6 +14995,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14326,12 +15009,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14353,15 +15036,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xea /5" ], @@ -14370,9 +15055,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14383,6 +15068,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14395,12 +15082,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14422,15 +15109,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xeb /5" ], @@ -14439,9 +15128,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14452,6 +15141,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14464,12 +15155,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14491,15 +15182,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xec /5" ], @@ -14508,9 +15201,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14521,6 +15214,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14533,12 +15228,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14560,15 +15255,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xed /5" ], @@ -14577,9 +15274,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14590,6 +15287,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14602,12 +15301,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14629,15 +15328,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xee /5" ], @@ -14646,9 +15347,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14659,6 +15360,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14671,12 +15374,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14698,15 +15401,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xef /5" ], @@ -14715,9 +15420,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14728,6 +15433,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14740,12 +15447,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14767,15 +15474,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xf0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fdivr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -14786,9 +15495,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14799,6 +15508,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14811,12 +15522,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14838,15 +15549,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf1 /6" ], @@ -14855,9 +15568,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14868,6 +15581,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14880,12 +15595,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14907,15 +15622,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf2 /6" ], @@ -14924,9 +15641,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14937,6 +15654,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14949,12 +15668,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14976,15 +15695,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf3 /6" ], @@ -14993,9 +15714,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15006,6 +15727,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15018,12 +15741,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15045,15 +15768,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf4 /6" ], @@ -15062,9 +15787,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15075,6 +15800,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15087,12 +15814,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15114,15 +15841,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf5 /6" ], @@ -15131,9 +15860,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15144,6 +15873,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15156,12 +15887,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15183,15 +15914,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf6 /6" ], @@ -15200,9 +15933,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15213,6 +15946,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15225,12 +15960,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15252,15 +15987,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf7 /6" ], @@ -15269,9 +16006,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15282,6 +16019,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15294,12 +16033,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15321,15 +16060,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xf8": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fdiv st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -15340,9 +16081,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15353,6 +16094,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15365,12 +16108,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15392,15 +16135,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf9 /7" ], @@ -15409,9 +16154,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15422,6 +16167,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15434,12 +16181,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15461,15 +16208,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xfa /7" ], @@ -15478,9 +16227,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15491,6 +16240,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15503,12 +16254,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15530,15 +16281,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xfb /7" ], @@ -15547,9 +16300,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15560,6 +16313,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15572,12 +16327,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15599,15 +16354,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xfc /7" ], @@ -15616,9 +16373,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15629,6 +16386,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15641,12 +16400,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15668,15 +16427,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xfd /7" ], @@ -15685,9 +16446,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15698,6 +16459,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15710,12 +16473,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15737,15 +16500,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xfe /7" ], @@ -15754,9 +16519,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15767,6 +16532,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15779,12 +16546,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15806,15 +16573,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xff /7" ], @@ -15823,9 +16592,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15836,6 +16605,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15848,12 +16619,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15875,15 +16646,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld qword [rax]": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdd !11b /0" ], @@ -15900,6 +16673,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15913,8 +16688,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15936,30 +16711,32 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fisttp qword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdd !11b /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15970,6 +16747,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15982,10 +16761,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1216]", + "ldr x3, [x28, #1232]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16007,27 +16786,29 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "str x21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fst qword [rax]": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 56, "Comment": [ "0xdd !11b /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -16038,6 +16819,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -16050,10 +16833,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16075,19 +16858,21 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "str d2, [x4]" ] }, "fstp qword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdd !11b /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -16098,6 +16883,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -16110,10 +16897,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16135,13 +16922,15 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "str d2, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16154,7 +16943,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -16199,7 +16988,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1010]", + "strb w20, [x28, #1026]", "add x20, x4, #0x1c (28)", "mov x22, #0xffffffffffffffff", "mov w24, #0xffff", @@ -16208,49 +16997,49 @@ "ldur q3, [x4, #28]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x20, #10]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x22, #10]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x20, #10]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x22, #10]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x20, #10]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x22, #10]", "and v2.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -16258,7 +17047,7 @@ "ldr h3, [x22, #8]", "mov v2.h[4], v3.h[0]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x23" ] }, @@ -16269,7 +17058,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrh w21, [x28, #1008]", + "ldrh w21, [x28, #1024]", "str w21, [x4]", "mov w21, #0x0", "mov x22, x21", @@ -16277,49 +17066,49 @@ "ldrb w23, [x28, #744]", "ldrb w24, [x28, #745]", "ldrb w25, [x28, #746]", - "ldrb w26, [x28, #750]", + "ldrb w30, [x28, #750]", "orr x22, x22, x23, lsl #8", "orr x22, x22, x24, lsl #9", "orr x22, x22, x25, lsl #10", - "orr x22, x22, x26, lsl #14", + "orr x22, x22, x30, lsl #14", "str w22, [x4, #4]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "and w23, w22, #0x1", "mov w24, #0x3", "mrs x25, nzcv", "cmp x23, #0x0 (0)", "csel x23, x24, x21, eq", "orr w23, w21, w23", - "lsr w26, w22, #1", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #2", - "lsr w26, w22, #2", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #4", - "lsr w26, w22, #3", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #6", - "lsr w26, w22, #4", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #8", - "lsr w26, w22, #5", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #10", - "lsr w26, w22, #6", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #12", + "lsr w30, w22, #1", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #2", + "lsr w30, w22, #2", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #4", + "lsr w30, w22, #3", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #6", + "lsr w30, w22, #4", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #8", + "lsr w30, w22, #5", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #10", + "lsr w30, w22, #6", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #12", "lsr w22, w22, #7", "and w22, w22, #0x1", "cmp x22, #0x0 (0)", @@ -16332,60 +17121,60 @@ "str w21, [x4, #24]", "add x22, x4, #0x1c (28)", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x4, #28]", "add x23, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x22, #10]", "add x22, x23, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x23, #10]", "add x23, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x22, #10]", "add x22, x23, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x23, #10]", "add x23, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x22, #10]", "add x22, x23, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x23, #10]", "add x23, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur d2, [x22, #10]", "dup v2.8h, v2.h[4]", "str h2, [x23, #8]", "mov w20, #0x37f", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "msr nzcv, x25" ] }, @@ -16418,11 +17207,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x0 (0)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st1": { @@ -16435,10 +17224,10 @@ "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w20, w21, w20", "bic w20, w22, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st2": { @@ -16450,11 +17239,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x2 (2)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st3": { @@ -16466,11 +17255,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x3 (3)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st4": { @@ -16482,11 +17271,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x4 (4)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st5": { @@ -16498,11 +17287,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x5 (5)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st6": { @@ -16514,11 +17303,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x6 (6)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st7": { @@ -16530,11 +17319,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "fst st0": { @@ -16547,9 +17336,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st1": { @@ -16562,9 +17351,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st2": { @@ -16577,9 +17366,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st3": { @@ -16592,9 +17381,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st4": { @@ -16607,9 +17396,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st5": { @@ -16622,9 +17411,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st6": { @@ -16637,9 +17426,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st7": { @@ -16652,9 +17441,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fstp st0": { @@ -16667,14 +17456,14 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16691,13 +17480,13 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]", - "ldrb w22, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16713,14 +17502,14 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16736,14 +17525,14 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16759,14 +17548,14 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16782,14 +17571,14 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16805,14 +17594,14 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16828,21 +17617,21 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucom st0": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe0 /4" ], @@ -16852,9 +17641,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -16865,6 +17654,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -16877,12 +17668,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16904,6 +17695,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x22, x20, #1, #1", "ubfx x23, x20, #0, #1", @@ -16917,7 +17710,7 @@ ] }, "fucom st1": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe1 /4" ], @@ -16926,9 +17719,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -16939,6 +17732,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -16951,12 +17746,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16978,6 +17773,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -16992,7 +17789,7 @@ ] }, "fucom st2": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe2 /4" ], @@ -17001,9 +17798,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17014,6 +17811,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17026,12 +17825,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17053,6 +17852,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17067,7 +17868,7 @@ ] }, "fucom st3": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe3 /4" ], @@ -17076,9 +17877,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17089,6 +17890,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17101,12 +17904,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17128,6 +17931,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17142,7 +17947,7 @@ ] }, "fucom st4": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe4 /4" ], @@ -17151,9 +17956,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17164,6 +17969,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17176,12 +17983,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17203,6 +18010,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17217,7 +18026,7 @@ ] }, "fucom st5": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe5 /4" ], @@ -17226,9 +18035,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17239,6 +18048,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17251,12 +18062,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17278,6 +18089,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17292,7 +18105,7 @@ ] }, "fucom st6": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe6 /4" ], @@ -17301,9 +18114,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17314,6 +18127,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17326,12 +18141,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17353,6 +18168,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17367,7 +18184,7 @@ ] }, "fucom st7": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe7 /4" ], @@ -17376,9 +18193,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17389,6 +18206,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17401,12 +18220,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17428,6 +18247,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17442,7 +18263,7 @@ ] }, "fucomp st0": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xe8 /5" ], @@ -17452,9 +18273,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17465,6 +18286,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17477,12 +18300,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17504,6 +18327,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -17514,18 +18339,18 @@ "strb w21, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st1": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xe9 /5" ], @@ -17535,9 +18360,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17548,6 +18373,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17560,12 +18387,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17587,6 +18414,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -17598,17 +18427,17 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st2": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xea /5" ], @@ -17617,9 +18446,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17630,6 +18459,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17642,12 +18473,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17669,6 +18500,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -17680,18 +18513,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st3": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xeb /5" ], @@ -17700,9 +18533,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17713,6 +18546,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17725,12 +18560,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17752,6 +18587,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -17763,18 +18600,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st4": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xec /5" ], @@ -17783,9 +18620,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17796,6 +18633,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17808,12 +18647,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17835,6 +18674,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -17846,18 +18687,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st5": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xed /5" ], @@ -17866,9 +18707,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17879,6 +18720,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17891,12 +18734,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17918,6 +18761,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -17929,18 +18774,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st6": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xee /5" ], @@ -17949,9 +18794,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17962,6 +18807,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17974,12 +18821,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18001,6 +18848,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -18012,18 +18861,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st7": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xef /5" ], @@ -18032,9 +18881,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18045,6 +18894,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18057,12 +18908,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18084,6 +18935,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -18095,18 +18948,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fiadd word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /0" ], @@ -18123,6 +18976,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18135,9 +18990,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18159,11 +19014,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18174,6 +19031,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18186,12 +19045,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18213,15 +19072,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fimul word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /1" ], @@ -18238,6 +19099,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18250,9 +19113,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18274,11 +19137,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18289,6 +19154,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18301,12 +19168,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18328,15 +19195,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "ficom word [rax]": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 121, "Comment": [ "0xde !11b /2" ], @@ -18353,6 +19222,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18365,9 +19236,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18389,11 +19260,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18404,6 +19277,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18416,12 +19291,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18443,6 +19318,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -18457,7 +19334,7 @@ ] }, "ficomp word [rax]": { - "ExpectedInstructionCount": 121, + "ExpectedInstructionCount": 129, "Comment": [ "0xde !11b /3" ], @@ -18474,6 +19351,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18486,9 +19365,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18510,11 +19389,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18525,6 +19406,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18537,12 +19420,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18564,6 +19447,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -18575,18 +19460,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fisub word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /4" ], @@ -18603,6 +19488,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18615,9 +19502,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18639,11 +19526,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18654,6 +19543,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18666,12 +19557,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18693,15 +19584,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fisubr word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /5" ], @@ -18718,6 +19611,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18730,9 +19625,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18754,11 +19649,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18769,6 +19666,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18781,12 +19680,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18808,15 +19707,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fidiv word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /6" ], @@ -18833,6 +19734,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18845,9 +19748,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18869,11 +19772,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18884,6 +19789,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18896,12 +19803,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18923,15 +19830,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fidivr word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /7" ], @@ -18948,6 +19857,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18960,9 +19871,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18984,11 +19895,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18999,6 +19912,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19011,12 +19926,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19038,15 +19953,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "faddp st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xd8 11b 0xc0 /0" ], @@ -19055,9 +19972,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19068,6 +19985,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19080,12 +19999,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19107,23 +20026,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "faddp st1": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xc1 /0" ], @@ -19133,9 +20054,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19146,6 +20067,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19158,545 +20081,7 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w20", - "bic w21, w23, w21", - "strb w21, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st2": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc2 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st3": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc3 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st4": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc4 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st5": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc5 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st6": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc6 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st7": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc7 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fmulp st0": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc8 /1" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", @@ -19723,23 +20108,591 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #768]" + ] + }, + "faddp st2": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" + ] + }, + "faddp st3": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "faddp st4": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "faddp st5": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "faddp st6": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "faddp st7": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fmulp st0": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" ] }, "fmulp st1": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xc9 /1" ], @@ -19749,9 +20702,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19762,6 +20715,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19774,12 +20729,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19801,22 +20756,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st2": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xca /1" ], @@ -19825,9 +20782,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19838,6 +20795,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19850,12 +20809,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19877,23 +20836,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st3": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xcb /1" ], @@ -19902,9 +20863,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19915,6 +20876,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19927,12 +20890,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19954,23 +20917,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st4": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xcc /1" ], @@ -19979,9 +20944,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19992,6 +20957,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20004,12 +20971,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20031,23 +20998,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st5": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xcd /1" ], @@ -20056,9 +21025,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20069,6 +21038,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20081,12 +21052,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20108,23 +21079,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st6": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xce /1" ], @@ -20133,9 +21106,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20146,6 +21119,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20158,12 +21133,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20185,23 +21160,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st7": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xcf /1" ], @@ -20210,9 +21187,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20223,6 +21200,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20235,12 +21214,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20262,23 +21241,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcompp": { - "ExpectedInstructionCount": 80, + "ExpectedInstructionCount": 84, "Comment": [ "0xde 11b 0xd9 /3" ], @@ -20288,9 +21269,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20301,6 +21282,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20313,12 +21296,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20340,6 +21323,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -20351,22 +21336,22 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "db 0xde, 0xe0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "fsubrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -20377,9 +21362,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20390,6 +21375,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20402,12 +21389,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20429,23 +21416,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st1, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe1 /4" ], @@ -20455,9 +21444,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20468,6 +21457,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20480,12 +21471,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20507,22 +21498,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st2, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe2 /4" ], @@ -20531,9 +21524,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20544,6 +21537,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20556,12 +21551,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20583,23 +21578,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st3, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe3 /4" ], @@ -20608,9 +21605,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20621,6 +21618,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20633,12 +21632,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20660,23 +21659,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st4, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe4 /4" ], @@ -20685,9 +21686,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20698,6 +21699,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20710,12 +21713,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20737,23 +21740,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st5, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe5 /4" ], @@ -20762,9 +21767,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20775,6 +21780,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20787,12 +21794,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20814,23 +21821,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st6, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe6 /4" ], @@ -20839,9 +21848,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20852,6 +21861,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20864,12 +21875,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20891,23 +21902,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st7, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe7 /4" ], @@ -20916,9 +21929,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20929,6 +21942,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20941,12 +21956,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20968,23 +21983,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xde, 0xe8": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "fsubp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -20995,9 +22012,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21008,6 +22025,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21020,12 +22039,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21047,23 +22066,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st1, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe9 /5" ], @@ -21073,9 +22094,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21086,6 +22107,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21098,12 +22121,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21125,22 +22148,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st2, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xea /5" ], @@ -21149,9 +22174,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21162,6 +22187,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21174,12 +22201,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21201,23 +22228,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st3, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xeb /5" ], @@ -21226,9 +22255,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21239,6 +22268,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21251,12 +22282,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21278,23 +22309,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st4, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xec /5" ], @@ -21303,9 +22336,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21316,6 +22349,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21328,12 +22363,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21355,23 +22390,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st5, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xed /5" ], @@ -21380,9 +22417,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21393,6 +22430,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21405,12 +22444,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21432,23 +22471,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st6, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xee /5" ], @@ -21457,9 +22498,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21470,6 +22511,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21482,12 +22525,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21509,23 +22552,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st7, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xef /5" ], @@ -21534,9 +22579,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21547,6 +22592,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21559,12 +22606,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21586,23 +22633,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xde, 0xf0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "fdivrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -21613,9 +22662,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21626,6 +22675,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21638,12 +22689,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21665,23 +22716,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st1, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf1 /6" ], @@ -21691,9 +22744,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21704,6 +22757,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21716,12 +22771,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21743,22 +22798,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st2, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf2 /6" ], @@ -21767,9 +22824,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21780,6 +22837,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21792,12 +22851,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21819,23 +22878,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st3, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf3 /6" ], @@ -21844,9 +22905,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21857,6 +22918,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21869,12 +22932,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21896,23 +22959,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st4, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf4 /6" ], @@ -21921,9 +22986,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21934,6 +22999,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21946,12 +23013,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21973,23 +23040,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st5, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf5 /6" ], @@ -21998,9 +23067,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22011,6 +23080,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22023,12 +23094,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22050,23 +23121,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st6, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf6 /6" ], @@ -22075,9 +23148,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22088,6 +23161,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22100,12 +23175,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22127,23 +23202,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st7, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf7 /6" ], @@ -22152,9 +23229,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22165,6 +23242,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22177,12 +23256,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22204,23 +23283,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xde, 0xf8": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "fdivp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -22231,9 +23312,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22244,6 +23325,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22256,12 +23339,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22283,23 +23366,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st1, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf9 /7" ], @@ -22309,9 +23394,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22322,6 +23407,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22334,12 +23421,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22361,22 +23448,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st2, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xfa /7" ], @@ -22385,9 +23474,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22398,6 +23487,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22410,12 +23501,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22437,23 +23528,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st3, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xfb /7" ], @@ -22462,9 +23555,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22475,6 +23568,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22487,12 +23582,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22514,23 +23609,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st4, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xfc /7" ], @@ -22539,9 +23636,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22552,6 +23649,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22564,12 +23663,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22591,23 +23690,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st5, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xfd /7" ], @@ -22616,9 +23717,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22629,6 +23730,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22641,12 +23744,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22668,23 +23771,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st6, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xfe /7" ], @@ -22693,9 +23798,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22706,6 +23811,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22718,12 +23825,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22745,23 +23852,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st7, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xff /7" ], @@ -22770,9 +23879,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22783,6 +23892,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22795,12 +23906,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22822,23 +23933,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fild word [rax]": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 35, "Comment": [ "0xdf !11b /0" ], @@ -22847,47 +23960,48 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldrh w21, [x4]", "mov w22, #0x0", "sxth x21, w21", - "mrs x23, nzcv", + "mrs x22, nzcv", "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", + "mov w23, #0x8000", + "csel x23, x23, xzr, lt", "cneg x21, x21, mi", - "mov w25, #0x3f", + "mov w24, #0x3f", "mov x0, #0x3f", - "clz x26, x21", - "sub x26, x0, x26", - "sub x25, x25, x26", - "lsl x26, x21, x25", - "mov w27, #0x403e", - "sub x25, x27, x25", + "clz x25, x21", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x21, x24", + "mov w30, #0x403e", + "sub x24, x30, x24", + "mov w30, #0x0", "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x26", + "csel x21, x30, x24, eq", + "orr x21, x23, x21", + "fmov d2, x25", "fmov d3, x21", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", - "msr nzcv, x23" + "str q2, [x0, #768]", + "msr nzcv, x22" ] }, "fisttp word [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdf !11b /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22898,6 +24012,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22910,10 +24026,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1200]", + "ldr x3, [x28, #1216]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22935,27 +24051,29 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "sxth x21, w0", "strh w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fist word [rax]": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 56, "Comment": [ "0xdf !11b /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22966,6 +24084,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22978,10 +24098,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1176]", + "ldr x3, [x28, #1192]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23003,19 +24123,21 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "sxth x20, w0", "strh w20, [x4]" ] }, "fistp word [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdf !11b /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23026,6 +24148,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23038,10 +24162,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1176]", + "ldr x3, [x28, #1192]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23063,20 +24187,22 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "sxth x21, w0", "strh w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fbld tword [rax]": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 66, "Comment": [ "0xdf !11b /4" ], @@ -23085,10 +24211,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -23101,6 +24227,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23113,10 +24241,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1376]", + "ldr x3, [x28, #1392]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23138,22 +24266,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fbstp tword [rax]": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 68, "Comment": [ "0xdf !11b /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23164,6 +24294,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23176,10 +24308,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1368]", + "ldr x3, [x28, #1384]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23201,17 +24333,19 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -23334,7 +24468,7 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xe8 /5" ], @@ -23343,9 +24477,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23356,6 +24490,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23368,12 +24504,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23395,6 +24531,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23404,19 +24542,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomip st1": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xe9 /5" ], @@ -23426,9 +24563,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23439,6 +24576,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23451,12 +24590,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23478,6 +24617,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -23486,19 +24627,18 @@ "orr w24, w24, w22", "rmif x23, #63, #nzCv", "rmif x24, #62, #nZcv", - "eor w22, w22, #0x1", - "strb w22, [x28, #706]", - "ldrb w22, [x28, #1010]", + "eor w26, w22, #0x1", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomip st2": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xea /5" ], @@ -23507,9 +24647,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23520,6 +24660,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23532,12 +24674,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23559,6 +24701,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23568,19 +24712,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomip st3": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xeb /5" ], @@ -23589,9 +24732,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23602,6 +24745,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23614,12 +24759,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23641,6 +24786,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23650,19 +24797,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomip st4": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xec /5" ], @@ -23671,9 +24817,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23684,6 +24830,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23696,12 +24844,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23723,6 +24871,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23732,19 +24882,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomip st5": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xed /5" ], @@ -23753,9 +24902,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23766,6 +24915,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23778,12 +24929,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23805,6 +24956,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23814,19 +24967,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomip st6": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xee /5" ], @@ -23835,9 +24987,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23848,6 +25000,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23860,12 +25014,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23887,6 +25041,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23896,19 +25052,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomip st7": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xef /5" ], @@ -23917,9 +25072,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23930,6 +25085,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23942,12 +25099,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23969,6 +25126,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23978,19 +25137,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomip st0": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xf0 /6" ], @@ -23999,9 +25157,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24012,6 +25170,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24024,12 +25184,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24051,6 +25211,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24060,19 +25222,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomip st1": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xf1 /6" ], @@ -24082,9 +25243,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24095,6 +25256,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24107,12 +25270,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24134,6 +25297,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -24142,19 +25307,18 @@ "orr w24, w24, w22", "rmif x23, #63, #nzCv", "rmif x24, #62, #nZcv", - "eor w22, w22, #0x1", - "strb w22, [x28, #706]", - "ldrb w22, [x28, #1010]", + "eor w26, w22, #0x1", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomip st2": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xf2 /6" ], @@ -24163,9 +25327,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24176,6 +25340,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24188,12 +25354,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24215,6 +25381,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24224,19 +25392,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomip st3": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xf3 /6" ], @@ -24245,9 +25412,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24258,6 +25425,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24270,12 +25439,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24297,6 +25466,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24306,19 +25477,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomip st4": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xf4 /6" ], @@ -24327,9 +25497,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24340,6 +25510,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24352,12 +25524,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24379,6 +25551,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24388,19 +25562,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomip st5": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xf5 /6" ], @@ -24409,9 +25582,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24422,6 +25595,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24434,12 +25609,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24461,6 +25636,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24470,19 +25647,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomip st6": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xf6 /6" ], @@ -24491,9 +25667,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24504,6 +25680,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24516,12 +25694,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24543,6 +25721,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24552,19 +25732,18 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomip st7": { - "ExpectedInstructionCount": 74, + "ExpectedInstructionCount": 77, "Comment": [ "0xdf 11b 0xf7 /6" ], @@ -24573,9 +25752,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24586,6 +25765,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24598,12 +25779,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24625,6 +25806,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24634,12 +25817,11 @@ "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 43b332bff..1a133dc11 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -25,10 +25,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul dword [rax]": { @@ -41,10 +41,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcom dword [rax]": { @@ -57,7 +57,7 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -89,7 +89,7 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -108,11 +108,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -129,10 +129,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr dword [rax]": { @@ -145,10 +145,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv dword [rax]": { @@ -161,10 +161,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr dword [rax]": { @@ -177,10 +177,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st0": { @@ -193,12 +193,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st1": { @@ -211,12 +211,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st2": { @@ -229,12 +229,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st3": { @@ -247,12 +247,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st4": { @@ -265,12 +265,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st5": { @@ -283,12 +283,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st6": { @@ -301,12 +301,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st7": { @@ -319,12 +319,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st0": { @@ -337,12 +337,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st1": { @@ -355,12 +355,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st2": { @@ -373,12 +373,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st3": { @@ -391,12 +391,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st4": { @@ -409,12 +409,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st5": { @@ -427,12 +427,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st6": { @@ -445,12 +445,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st7": { @@ -463,12 +463,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcom st0, st0": { @@ -482,9 +482,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -515,9 +515,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -549,9 +549,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -583,9 +583,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -617,9 +617,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -651,9 +651,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -685,9 +685,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -719,9 +719,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -754,9 +754,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -774,11 +774,11 @@ "strb w21, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -796,9 +796,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -817,10 +817,10 @@ "strb w24, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -837,9 +837,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -858,11 +858,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -879,9 +879,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -900,11 +900,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -921,9 +921,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -942,11 +942,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -963,9 +963,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -984,11 +984,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -1005,9 +1005,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -1026,11 +1026,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -1047,9 +1047,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -1068,11 +1068,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -1089,12 +1089,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st1": { @@ -1107,12 +1107,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st2": { @@ -1125,12 +1125,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st3": { @@ -1143,12 +1143,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st4": { @@ -1161,12 +1161,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st5": { @@ -1179,12 +1179,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st6": { @@ -1197,12 +1197,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st7": { @@ -1215,12 +1215,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st0": { @@ -1233,12 +1233,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st1": { @@ -1251,12 +1251,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st2": { @@ -1269,12 +1269,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st3": { @@ -1287,12 +1287,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st4": { @@ -1305,12 +1305,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st5": { @@ -1323,12 +1323,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st6": { @@ -1341,12 +1341,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st7": { @@ -1359,12 +1359,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st0": { @@ -1377,12 +1377,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st1": { @@ -1395,12 +1395,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st2": { @@ -1413,12 +1413,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st3": { @@ -1431,12 +1431,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st4": { @@ -1449,12 +1449,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st5": { @@ -1467,12 +1467,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st6": { @@ -1485,12 +1485,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st7": { @@ -1503,12 +1503,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st0": { @@ -1521,12 +1521,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st1": { @@ -1539,12 +1539,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st2": { @@ -1557,12 +1557,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st3": { @@ -1575,12 +1575,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st4": { @@ -1593,12 +1593,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st5": { @@ -1611,12 +1611,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st6": { @@ -1629,12 +1629,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st7": { @@ -1647,12 +1647,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld dword [rax]": { @@ -1667,13 +1667,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fst dword [rax]": { @@ -1684,7 +1684,7 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fcvt s2, d2", "str s2, [x4]" ] @@ -1697,14 +1697,14 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fcvt s2, d2", "str s2, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -1725,7 +1725,7 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -1770,7 +1770,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1010]", + "strb w20, [x28, #1026]", "msr nzcv, x22" ] }, @@ -1789,7 +1789,7 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1008]" + "strh w20, [x28, #1024]" ] }, "fnstenv [rax]": { @@ -1798,7 +1798,7 @@ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1008]", + "ldrh w20, [x28, #1024]", "str w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -1814,7 +1814,7 @@ "orr x21, x21, x24, lsl #10", "orr x21, x21, x25, lsl #14", "str w21, [x4, #4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "and w22, w21, #0x1", "mov w23, #0x3", "mrs x24, nzcv", @@ -1870,7 +1870,7 @@ "0xd9 !11b /7" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1008]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]" ] }, @@ -1884,17 +1884,17 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st1": { @@ -1908,16 +1908,16 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st2": { @@ -1930,17 +1930,17 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st3": { @@ -1953,17 +1953,17 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st4": { @@ -1976,17 +1976,17 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st5": { @@ -1999,17 +1999,17 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st6": { @@ -2022,17 +2022,17 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st7": { @@ -2045,17 +2045,17 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fxch st0, st0": { @@ -2068,13 +2068,13 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st1": { @@ -2087,13 +2087,13 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st2": { @@ -2106,13 +2106,13 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st3": { @@ -2125,13 +2125,13 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st4": { @@ -2144,13 +2144,13 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st5": { @@ -2163,13 +2163,13 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st6": { @@ -2182,13 +2182,13 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st7": { @@ -2201,13 +2201,13 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fnop": { @@ -2225,10 +2225,10 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fneg v2.2d, v2.2d", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fabs": { @@ -2239,10 +2239,10 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fabs d2, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "ftst": { @@ -2253,7 +2253,7 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w20, #0x0", "fmov d3, x20", "mrs x21, nzcv", @@ -2284,11 +2284,11 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov x21, v2.d[0]", "lsr x21, x21, #63", "strb w21, [x28, #745]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "lsr w20, w21, w20", "mov w21, #0x1", "and w20, w20, #0x1", @@ -2312,15 +2312,15 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x3ff0000000000000", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldl2t": { @@ -2333,10 +2333,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xa372", "movk x21, #0x979, lsl #16", @@ -2344,7 +2344,7 @@ "movk x21, #0x400a, lsl #48", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldl2e": { @@ -2357,10 +2357,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x82fe", "movk x21, #0x652b, lsl #16", @@ -2368,7 +2368,7 @@ "movk x21, #0x3ff7, lsl #48", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldpi": { @@ -2381,10 +2381,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x2d18", "movk x21, #0x5444, lsl #16", @@ -2392,7 +2392,7 @@ "movk x21, #0x4009, lsl #48", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldlg2": { @@ -2405,10 +2405,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x79ff", "movk x21, #0x509f, lsl #16", @@ -2416,7 +2416,7 @@ "movk x21, #0x3fd3, lsl #48", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldln2": { @@ -2429,10 +2429,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x39ef", "movk x21, #0xfefa, lsl #16", @@ -2440,7 +2440,7 @@ "movk x21, #0x3fe6, lsl #48", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldz": { @@ -2453,26 +2453,26 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov w21, #0x0", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "f2xm1": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 56, "Comment": [ "0xd9 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2483,6 +2483,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2496,8 +2498,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1488]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1504]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2519,30 +2521,32 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fyl2x": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 67, "Comment": [ "0xd9 11b 0xf1 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2553,6 +2557,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2567,248 +2573,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1496]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fptan": { - "ExpectedInstructionCount": 66, - "Comment": [ - "0xd9 11b 0xf2 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1472]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "mov x21, #0x3ff0000000000000", - "fmov d3, x21", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str d3, [x0, #752]" - ] - }, - "fpatan": { - "ExpectedInstructionCount": 63, - "Comment": [ - "0xd9 11b 0xf3 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1010]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v3.8b", - "mov v1.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1480]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fxtract": { - "ExpectedInstructionCount": 23, - "Comment": [ - "0xd9 11b 0xf4 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "mov x21, v2.d[0]", - "and x23, x21, #0x7ff0000000000000", - "lsr x23, x23, #52", - "sub x23, x23, #0x3ff (1023)", - "scvtf d2, x23", - "and x21, x21, #0x800fffffffffffff", - "orr x21, x21, #0x3ff0000000000000", - "fmov d3, x21", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str d3, [x0, #752]" - ] - }, - "fprem1": { - "ExpectedInstructionCount": 59, - "Comment": [ - "0xd9 11b 0xf5 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "mov v1.8b, v3.8b", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "ldr x1, [x28, #1512]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", @@ -2831,11 +2596,266 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fptan": { + "ExpectedInstructionCount": 70, + "Comment": [ + "0xd9 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1488]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "mov x21, #0x3ff0000000000000", + "fmov d3, x21", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str d3, [x0, #768]" + ] + }, + "fpatan": { + "ExpectedInstructionCount": 67, + "Comment": [ + "0xd9 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1026]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1026]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v3.8b", + "mov v1.8b, v2.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1496]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fxtract": { + "ExpectedInstructionCount": 23, + "Comment": [ + "0xd9 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "mov x21, v2.d[0]", + "and x23, x21, #0x7ff0000000000000", + "lsr x23, x23, #52", + "sub x23, x23, #0x3ff (1023)", + "scvtf d2, x23", + "and x21, x21, #0x800fffffffffffff", + "orr x21, x21, #0x3ff0000000000000", + "fmov d3, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str d3, [x0, #768]" + ] + }, + "fprem1": { + "ExpectedInstructionCount": 63, + "Comment": [ + "0xd9 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1528]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "mov w21, #0x0", "strb w21, [x28, #746]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdecstp": { @@ -2863,7 +2883,7 @@ ] }, "fprem": { - "ExpectedInstructionCount": 59, + "ExpectedInstructionCount": 63, "Comment": [ "0xd9 11b 0xf8 /7" ], @@ -2872,9 +2892,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2885,6 +2905,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2899,295 +2921,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1504]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fyl2xp1": { - "ExpectedInstructionCount": 66, - "Comment": [ - "0xd9 11b 0xf9 /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1010]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", - "mov x20, #0x3ff0000000000000", - "fmov d4, x20", - "fadd d2, d2, d4", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "mov v1.8b, v3.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1496]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fsqrt": { - "ExpectedInstructionCount": 6, - "Comment": [ - "0xd9 11b 0xfa /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "fsqrt d2, d2", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fsincos": { - "ExpectedInstructionCount": 111, - "Comment": [ - "0xd9 11b 0xfb /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1456]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v3.8b, v0.8b", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1464]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str d3, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" - ] - }, - "frndint": { - "ExpectedInstructionCount": 6, - "Comment": [ - "0xd9 11b 0xfc /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "frinti d2, d2", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fscale": { - "ExpectedInstructionCount": 57, - "Comment": [ - "0xd9 11b 0xfd /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "mov v1.8b, v3.8b", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "ldr x1, [x28, #1520]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", @@ -3210,20 +2944,326 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fyl2xp1": { + "ExpectedInstructionCount": 70, + "Comment": [ + "0xd9 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1026]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1026]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #768]", + "mov x20, #0x3ff0000000000000", + "fmov d4, x20", + "fadd d2, d2, d4", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1512]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fsqrt": { + "ExpectedInstructionCount": 6, + "Comment": [ + "0xd9 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "fsqrt d2, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fsincos": { + "ExpectedInstructionCount": 119, + "Comment": [ + "0xd9 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1472]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v3.8b, v0.8b", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1480]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d3, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #768]" + ] + }, + "frndint": { + "ExpectedInstructionCount": 6, + "Comment": [ + "0xd9 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "frinti d2, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fscale": { + "ExpectedInstructionCount": 61, + "Comment": [ + "0xd9 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1536]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsin": { - "ExpectedInstructionCount": 54, + "ExpectedInstructionCount": 58, "Comment": [ "0xd9 11b 0xfe /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3234,6 +3274,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3247,8 +3289,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1456]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1472]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3270,22 +3312,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "mov w21, #0x0", "strb w21, [x28, #746]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcos": { - "ExpectedInstructionCount": 54, + "ExpectedInstructionCount": 58, "Comment": [ "0xd9 11b 0xff /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3296,6 +3340,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3309,8 +3355,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1464]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1480]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3332,11 +3378,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "mov w21, #0x0", "strb w21, [x28, #746]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fiadd dword [rax]": { @@ -3349,10 +3397,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fimul dword [rax]": { @@ -3365,10 +3413,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "ficom dword [rax]": { @@ -3381,7 +3429,7 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -3413,7 +3461,7 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -3432,11 +3480,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -3453,10 +3501,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fisubr dword [rax]": { @@ -3469,10 +3517,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fidiv dword [rax]": { @@ -3485,10 +3533,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fidivr dword [rax]": { @@ -3501,10 +3549,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcmovb st0, st0": { @@ -3519,12 +3567,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st1": { @@ -3539,12 +3587,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st2": { @@ -3559,12 +3607,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st3": { @@ -3579,12 +3627,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st4": { @@ -3599,12 +3647,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st5": { @@ -3619,12 +3667,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st6": { @@ -3639,12 +3687,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st7": { @@ -3659,12 +3707,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st0": { @@ -3679,12 +3727,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st1": { @@ -3699,12 +3747,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st2": { @@ -3719,12 +3767,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st3": { @@ -3739,12 +3787,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st4": { @@ -3759,12 +3807,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st5": { @@ -3779,12 +3827,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st6": { @@ -3799,12 +3847,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st7": { @@ -3819,12 +3867,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st0": { @@ -3841,12 +3889,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st1": { @@ -3863,12 +3911,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st2": { @@ -3885,12 +3933,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st3": { @@ -3907,12 +3955,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st4": { @@ -3929,12 +3977,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st5": { @@ -3951,12 +3999,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st6": { @@ -3973,12 +4021,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st7": { @@ -3995,22 +4043,21 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovu st0, st0": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xd8 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4021,23 +4068,22 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xd9 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4048,23 +4094,22 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st2": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xda /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4075,23 +4120,22 @@ "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st3": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdb /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4102,23 +4146,22 @@ "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st4": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdc /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4129,23 +4172,22 @@ "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st5": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdd /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4156,23 +4198,22 @@ "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st6": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xde /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4183,23 +4224,22 @@ "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st7": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdf /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4210,12 +4250,12 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, @@ -4230,9 +4270,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -4251,15 +4291,15 @@ "strb w24, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w24, w21, w20", "bic w23, w23, w24", - "strb w23, [x28, #1010]", + "strb w23, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -4276,15 +4316,15 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fisttp dword [rax]": { @@ -4295,14 +4335,14 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fcvtzs w21, d2", "str w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4316,7 +4356,7 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "frinti d0, d2", "fcvtzs w20, d0", "str w20, [x4]" @@ -4330,22 +4370,22 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "frinti d0, d2", "fcvtzs w21, d0", "str w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fld tword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdb !11b /5" ], @@ -4362,6 +4402,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4374,10 +4416,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4399,28 +4441,30 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fstp tword [rax]": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 67, "Comment": [ "0xdb !11b /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4431,6 +4475,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4444,8 +4490,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4467,17 +4513,19 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4495,12 +4543,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st1": { @@ -4515,12 +4563,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st2": { @@ -4535,12 +4583,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st3": { @@ -4555,12 +4603,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st4": { @@ -4575,12 +4623,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st5": { @@ -4595,12 +4643,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st6": { @@ -4615,12 +4663,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st7": { @@ -4635,12 +4683,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st0": { @@ -4655,12 +4703,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st1": { @@ -4675,12 +4723,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st2": { @@ -4695,12 +4743,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st3": { @@ -4715,12 +4763,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st4": { @@ -4735,12 +4783,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st5": { @@ -4755,12 +4803,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st6": { @@ -4775,12 +4823,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st7": { @@ -4795,12 +4843,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st0": { @@ -4816,12 +4864,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st1": { @@ -4837,12 +4885,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st2": { @@ -4858,12 +4906,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st3": { @@ -4879,12 +4927,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st4": { @@ -4900,12 +4948,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st5": { @@ -4921,12 +4969,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st6": { @@ -4942,12 +4990,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st7": { @@ -4963,22 +5011,21 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnu st0, st0": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xd8 /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4989,23 +5036,22 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xd9 /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5016,23 +5062,22 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st2": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xda /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5043,23 +5088,22 @@ "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st3": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdb /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5070,23 +5114,22 @@ "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st4": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdc /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5097,23 +5140,22 @@ "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st5": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdd /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5124,23 +5166,22 @@ "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st6": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xde /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5151,23 +5192,22 @@ "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st7": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdf /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5178,12 +5218,12 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, @@ -5209,17 +5249,17 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1010]" + "strb w21, [x28, #1026]" ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xe8 /5" ], @@ -5228,9 +5268,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5245,13 +5285,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xe9 /5" ], @@ -5260,9 +5299,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5277,13 +5316,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st2": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xea /5" ], @@ -5292,9 +5330,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5309,13 +5347,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st3": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xeb /5" ], @@ -5324,9 +5361,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5341,13 +5378,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st4": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xec /5" ], @@ -5356,9 +5392,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5373,13 +5409,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st5": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xed /5" ], @@ -5388,9 +5423,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5405,13 +5440,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st6": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xee /5" ], @@ -5420,9 +5454,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5437,13 +5471,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st7": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xef /5" ], @@ -5452,9 +5485,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5469,13 +5502,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf0 /6" ], @@ -5484,9 +5516,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5501,13 +5533,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf1 /6" ], @@ -5516,9 +5547,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5533,13 +5564,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st2": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf2 /6" ], @@ -5548,9 +5578,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5565,13 +5595,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st3": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf3 /6" ], @@ -5580,9 +5609,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5597,13 +5626,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st4": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf4 /6" ], @@ -5612,9 +5640,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5629,13 +5657,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st5": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf5 /6" ], @@ -5644,9 +5671,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5661,13 +5688,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st6": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf6 /6" ], @@ -5676,9 +5702,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5693,13 +5719,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st7": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf7 /6" ], @@ -5708,9 +5733,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5725,8 +5750,7 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, @@ -5739,10 +5763,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul qword [rax]": { @@ -5754,10 +5778,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcom qword [rax]": { @@ -5769,7 +5793,7 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -5800,7 +5824,7 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -5819,11 +5843,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -5839,10 +5863,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr qword [rax]": { @@ -5854,10 +5878,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv qword [rax]": { @@ -5869,10 +5893,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr qword [rax]": { @@ -5884,10 +5908,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xc0": { @@ -5902,12 +5926,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st1, st0": { @@ -5920,12 +5944,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st2, st0": { @@ -5938,12 +5962,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st3, st0": { @@ -5956,12 +5980,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st4, st0": { @@ -5974,12 +5998,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st5, st0": { @@ -5992,12 +6016,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st6, st0": { @@ -6010,12 +6034,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st7, st0": { @@ -6028,12 +6052,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xc8": { @@ -6048,12 +6072,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st1, st0": { @@ -6066,12 +6090,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st2, st0": { @@ -6084,12 +6108,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st3, st0": { @@ -6102,12 +6126,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st4, st0": { @@ -6120,12 +6144,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st5, st0": { @@ -6138,12 +6162,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st6, st0": { @@ -6156,12 +6180,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st7, st0": { @@ -6174,12 +6198,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xe0": { @@ -6194,12 +6218,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st1, st0": { @@ -6212,12 +6236,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st2, st0": { @@ -6230,12 +6254,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st3, st0": { @@ -6248,12 +6272,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st4, st0": { @@ -6266,12 +6290,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st5, st0": { @@ -6284,12 +6308,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st6, st0": { @@ -6302,12 +6326,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st7, st0": { @@ -6320,12 +6344,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xe8": { @@ -6340,12 +6364,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st1, st0": { @@ -6358,12 +6382,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st2, st0": { @@ -6376,12 +6400,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st3, st0": { @@ -6394,12 +6418,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st4, st0": { @@ -6412,12 +6436,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st5, st0": { @@ -6430,12 +6454,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st6, st0": { @@ -6448,12 +6472,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st7, st0": { @@ -6466,12 +6490,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xf0": { @@ -6486,12 +6510,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st1, st0": { @@ -6504,12 +6528,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st2, st0": { @@ -6522,12 +6546,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st3, st0": { @@ -6540,12 +6564,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st4, st0": { @@ -6558,12 +6582,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st5, st0": { @@ -6576,12 +6600,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st6, st0": { @@ -6594,12 +6618,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st7, st0": { @@ -6612,12 +6636,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xf8": { @@ -6632,12 +6656,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st1, st0": { @@ -6650,12 +6674,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st2, st0": { @@ -6668,12 +6692,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st3, st0": { @@ -6686,12 +6710,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st4, st0": { @@ -6704,12 +6728,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st5, st0": { @@ -6722,12 +6746,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st6, st0": { @@ -6740,12 +6764,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st7, st0": { @@ -6758,12 +6782,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld qword [rax]": { @@ -6777,13 +6801,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fisttp qword [rax]": { @@ -6794,14 +6818,14 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fcvtzs x21, d2", "str x21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -6815,7 +6839,7 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "str d2, [x4]" ] }, @@ -6827,20 +6851,20 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "str d2, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "frstor [rax]": { - "ExpectedInstructionCount": 501, + "ExpectedInstructionCount": 533, "Comment": [ "0xdd !11b /4" ], @@ -6855,8 +6879,8 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1008]", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -6901,7 +6925,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1010]", + "strb w20, [x28, #1026]", "add x20, x4, #0x1c (28)", "mov x22, #0xffffffffffffffff", "mov w24, #0xffff", @@ -6919,6 +6943,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -6931,10 +6957,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6956,9 +6982,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -6974,6 +7002,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -6986,10 +7016,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7011,9 +7041,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7029,6 +7061,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7041,10 +7075,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7066,9 +7100,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7084,6 +7120,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7096,10 +7134,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7121,9 +7159,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7139,6 +7179,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7151,10 +7193,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7176,9 +7218,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7194,6 +7238,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7206,10 +7252,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7231,9 +7277,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7249,6 +7297,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7261,10 +7311,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7286,9 +7336,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]", + "str d2, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7305,6 +7357,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7317,10 +7371,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7342,20 +7396,22 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]", + "str d2, [x0, #768]", "msr nzcv, x23" ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 511, + "ExpectedInstructionCount": 543, "Comment": [ "0xdd !11b /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrh w21, [x28, #1008]", + "ldrh w21, [x28, #1024]", "str w21, [x4]", "mov w21, #0x0", "mov x22, x21", @@ -7363,49 +7419,49 @@ "ldrb w23, [x28, #744]", "ldrb w24, [x28, #745]", "ldrb w25, [x28, #746]", - "ldrb w26, [x28, #750]", + "ldrb w30, [x28, #750]", "orr x22, x22, x23, lsl #8", "orr x22, x22, x24, lsl #9", "orr x22, x22, x25, lsl #10", - "orr x22, x22, x26, lsl #14", + "orr x22, x22, x30, lsl #14", "str w22, [x4, #4]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "and w23, w22, #0x1", "mov w24, #0x3", "mrs x25, nzcv", "cmp x23, #0x0 (0)", "csel x23, x24, x21, eq", "orr w23, w21, w23", - "lsr w26, w22, #1", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #2", - "lsr w26, w22, #2", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #4", - "lsr w26, w22, #3", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #6", - "lsr w26, w22, #4", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #8", - "lsr w26, w22, #5", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #10", - "lsr w26, w22, #6", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #12", + "lsr w30, w22, #1", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #2", + "lsr w30, w22, #2", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #4", + "lsr w30, w22, #3", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #6", + "lsr w30, w22, #4", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #8", + "lsr w30, w22, #5", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #10", + "lsr w30, w22, #6", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #12", "lsr w22, w22, #7", "and w22, w22, #0x1", "cmp x22, #0x0 (0)", @@ -7418,7 +7474,7 @@ "str w21, [x4, #24]", "add x22, x4, #0x1c (28)", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7429,6 +7485,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7442,8 +7500,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7465,6 +7523,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7473,7 +7533,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7484,6 +7544,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7497,8 +7559,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7520,6 +7582,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7528,7 +7592,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7539,6 +7603,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7552,8 +7618,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7575,6 +7641,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7583,7 +7651,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7594,6 +7662,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7607,8 +7677,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7630,6 +7700,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7638,7 +7710,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7649,6 +7721,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7662,8 +7736,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7685,6 +7759,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7693,7 +7769,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7704,6 +7780,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7717,8 +7795,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7740,6 +7818,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7748,7 +7828,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7759,6 +7839,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7772,8 +7854,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7795,6 +7877,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7803,7 +7887,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7814,6 +7898,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7827,8 +7913,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7850,6 +7936,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7857,13 +7945,13 @@ "dup v2.8h, v2.h[4]", "str h2, [x23, #8]", "mov w20, #0x37f", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "msr nzcv, x25" ] }, @@ -7896,11 +7984,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x0 (0)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st1": { @@ -7913,10 +8001,10 @@ "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w20, w21, w20", "bic w20, w22, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st2": { @@ -7928,11 +8016,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x2 (2)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st3": { @@ -7944,11 +8032,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x3 (3)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st4": { @@ -7960,11 +8048,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x4 (4)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st5": { @@ -7976,11 +8064,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x5 (5)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st6": { @@ -7992,11 +8080,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x6 (6)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st7": { @@ -8008,11 +8096,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "fst st0": { @@ -8025,9 +8113,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st1": { @@ -8040,9 +8128,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st2": { @@ -8055,9 +8143,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st3": { @@ -8070,9 +8158,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st4": { @@ -8085,9 +8173,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st5": { @@ -8100,9 +8188,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st6": { @@ -8115,9 +8203,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st7": { @@ -8130,9 +8218,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fstp st0": { @@ -8145,14 +8233,14 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8169,13 +8257,13 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]", - "ldrb w22, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8191,14 +8279,14 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8214,14 +8302,14 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8237,14 +8325,14 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8260,14 +8348,14 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8283,14 +8371,14 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8306,14 +8394,14 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8330,9 +8418,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8363,9 +8451,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8397,9 +8485,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8431,9 +8519,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8465,9 +8553,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8499,9 +8587,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8533,9 +8621,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8567,9 +8655,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8602,9 +8690,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -8622,11 +8710,11 @@ "strb w21, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8644,9 +8732,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -8665,10 +8753,10 @@ "strb w24, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8685,9 +8773,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8706,11 +8794,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8727,9 +8815,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8748,11 +8836,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8769,9 +8857,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8790,11 +8878,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8811,9 +8899,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8832,11 +8920,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8853,9 +8941,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8874,11 +8962,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8895,9 +8983,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8916,11 +9004,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8938,10 +9026,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fimul word [rax]": { @@ -8955,10 +9043,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "ficom word [rax]": { @@ -8972,7 +9060,7 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -9005,7 +9093,7 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -9024,11 +9112,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9046,10 +9134,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fisubr word [rax]": { @@ -9063,10 +9151,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fidiv word [rax]": { @@ -9080,10 +9168,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fidivr word [rax]": { @@ -9097,10 +9185,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st0": { @@ -9113,20 +9201,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st1": { @@ -9140,19 +9228,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st2": { @@ -9165,20 +9253,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st3": { @@ -9191,20 +9279,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st4": { @@ -9217,20 +9305,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st5": { @@ -9243,20 +9331,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st6": { @@ -9269,20 +9357,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st7": { @@ -9295,20 +9383,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st0": { @@ -9321,20 +9409,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st1": { @@ -9348,19 +9436,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st2": { @@ -9373,20 +9461,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st3": { @@ -9399,20 +9487,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st4": { @@ -9425,20 +9513,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st5": { @@ -9451,20 +9539,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st6": { @@ -9477,20 +9565,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st7": { @@ -9503,20 +9591,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcompp": { @@ -9530,9 +9618,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -9551,15 +9639,15 @@ "strb w24, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w24, w21, w20", "bic w23, w23, w24", - "strb w23, [x28, #1010]", + "strb w23, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9578,20 +9666,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st1, st0": { @@ -9605,19 +9693,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st2, st0": { @@ -9630,20 +9718,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st3, st0": { @@ -9656,20 +9744,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st4, st0": { @@ -9682,20 +9770,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st5, st0": { @@ -9708,20 +9796,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st6, st0": { @@ -9734,20 +9822,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st7, st0": { @@ -9760,20 +9848,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xde, 0xe8": { @@ -9788,20 +9876,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st1, st0": { @@ -9815,19 +9903,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st2, st0": { @@ -9840,20 +9928,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st3, st0": { @@ -9866,20 +9954,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st4, st0": { @@ -9892,20 +9980,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st5, st0": { @@ -9918,20 +10006,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st6, st0": { @@ -9944,20 +10032,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st7, st0": { @@ -9970,20 +10058,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xde, 0xf0": { @@ -9998,20 +10086,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st1, st0": { @@ -10025,19 +10113,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st2, st0": { @@ -10050,20 +10138,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st3, st0": { @@ -10076,20 +10164,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st4, st0": { @@ -10102,20 +10190,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st5, st0": { @@ -10128,20 +10216,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st6, st0": { @@ -10154,20 +10242,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st7, st0": { @@ -10180,20 +10268,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xde, 0xf8": { @@ -10208,20 +10296,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st1, st0": { @@ -10235,19 +10323,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st2, st0": { @@ -10260,20 +10348,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st3, st0": { @@ -10286,20 +10374,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st4, st0": { @@ -10312,20 +10400,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st5, st0": { @@ -10338,20 +10426,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st6, st0": { @@ -10364,20 +10452,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st7, st0": { @@ -10390,20 +10478,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fild word [rax]": { @@ -10416,16 +10504,16 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldrh w21, [x4]", "sxth x21, w21", "scvtf d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fisttp word [rax]": { @@ -10436,14 +10524,14 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fcvtzs x21, d2", "strh w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10457,7 +10545,7 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "frinti d0, d2", "fcvtzs x20, d0", "strh w20, [x4]" @@ -10471,22 +10559,22 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "frinti d0, d2", "fcvtzs x21, d0", "strh w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fbld tword [rax]": { - "ExpectedInstructionCount": 110, + "ExpectedInstructionCount": 118, "Comment": [ "0xdf !11b /4" ], @@ -10495,10 +10583,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -10511,6 +10599,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10523,10 +10613,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1376]", + "ldr x3, [x28, #1392]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10548,6 +10638,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -10561,6 +10653,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10573,10 +10667,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10598,20 +10692,22 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fbstp tword [rax]": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 121, "Comment": [ "0xdf !11b /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10622,6 +10718,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10635,8 +10733,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10658,6 +10756,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -10671,6 +10771,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10683,10 +10785,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1368]", + "ldr x3, [x28, #1384]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10708,17 +10810,19 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10841,7 +10945,7 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xe8 /5" ], @@ -10850,9 +10954,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -10868,12 +10972,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10881,7 +10984,7 @@ ] }, "fucomip st1": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xe9 /5" ], @@ -10891,9 +10994,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x22, eq", "csinc x22, x22, xzr, vc", @@ -10908,12 +11011,11 @@ "orr w24, w24, w22", "lsl x23, x23, #29", "orr w23, w23, w24, lsl #30", - "eor w22, w22, #0x1", - "strb w22, [x28, #706]", - "ldrb w22, [x28, #1010]", + "eor w26, w22, #0x1", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10921,7 +11023,7 @@ ] }, "fucomip st2": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xea /5" ], @@ -10930,9 +11032,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -10948,12 +11050,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10961,7 +11062,7 @@ ] }, "fucomip st3": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xeb /5" ], @@ -10970,9 +11071,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -10988,12 +11089,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11001,7 +11101,7 @@ ] }, "fucomip st4": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xec /5" ], @@ -11010,9 +11110,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11028,12 +11128,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11041,7 +11140,7 @@ ] }, "fucomip st5": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xed /5" ], @@ -11050,9 +11149,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11068,12 +11167,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11081,7 +11179,7 @@ ] }, "fucomip st6": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xee /5" ], @@ -11090,9 +11188,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11108,12 +11206,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11121,7 +11218,7 @@ ] }, "fucomip st7": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xef /5" ], @@ -11130,9 +11227,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11148,12 +11245,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11161,7 +11257,7 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf0 /6" ], @@ -11170,9 +11266,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11188,12 +11284,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11201,7 +11296,7 @@ ] }, "fcomip st1": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf1 /6" ], @@ -11211,9 +11306,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x22, eq", "csinc x22, x22, xzr, vc", @@ -11228,12 +11323,11 @@ "orr w24, w24, w22", "lsl x23, x23, #29", "orr w23, w23, w24, lsl #30", - "eor w22, w22, #0x1", - "strb w22, [x28, #706]", - "ldrb w22, [x28, #1010]", + "eor w26, w22, #0x1", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11241,7 +11335,7 @@ ] }, "fcomip st2": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf2 /6" ], @@ -11250,9 +11344,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11268,12 +11362,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11281,7 +11374,7 @@ ] }, "fcomip st3": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf3 /6" ], @@ -11290,9 +11383,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11308,12 +11401,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11321,7 +11413,7 @@ ] }, "fcomip st4": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf4 /6" ], @@ -11330,9 +11422,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11348,12 +11440,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11361,7 +11452,7 @@ ] }, "fcomip st5": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf5 /6" ], @@ -11370,9 +11461,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11388,12 +11479,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11401,7 +11491,7 @@ ] }, "fcomip st6": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf6 /6" ], @@ -11410,9 +11500,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11428,12 +11518,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11441,7 +11530,7 @@ ] }, "fcomip st7": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf7 /6" ], @@ -11450,9 +11539,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11468,12 +11557,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index 4a420f690..51410d939 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -17,12 +17,12 @@ "NP 0x0f 0x38 0x00" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "movi v4.16b, #0x87", "and v3.16b, v3.16b, v4.16b", "tbl v2.8b, {v2.16b}, v3.8b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pshufb xmm0, xmm1": { @@ -42,10 +42,10 @@ "NP 0x0f 0x38 0x01" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "addp v2.4h, v3.4h, v2.4h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "phaddw xmm0, xmm1": { @@ -63,10 +63,10 @@ "NP 0x0f 0x38 0x02" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "addp v2.2s, v3.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "phaddd xmm0, xmm1": { @@ -84,12 +84,12 @@ "NP 0x0f 0x38 0x03" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uzp1 v4.4h, v2.4h, v3.4h", "uzp2 v2.4h, v2.4h, v3.4h", "sqadd v2.8h, v4.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "phaddsw xmm0, xmm1": { @@ -109,15 +109,15 @@ "NP 0x0f 0x38 0x04" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uxtl v2.8h, v2.8b", "sxtl v3.8h, v3.8b", "smull v4.4s, v2.4h, v3.4h", "smull2 v2.4s, v2.8h, v3.8h", "addp v2.4s, v4.4s, v2.4s", "sqxtn v2.4h, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pmaddubsw xmm0, xmm1": { @@ -147,12 +147,12 @@ "NP 0x0f 0x38 0x05" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uzp1 v4.4h, v2.4h, v3.4h", "uzp2 v2.4h, v2.4h, v3.4h", "sub v2.8h, v4.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "phsubw xmm0, xmm1": { @@ -172,12 +172,12 @@ "NP 0x0f 0x38 0x06" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uzp1 v4.2s, v2.2s, v3.2s", "uzp2 v2.2s, v2.2s, v3.2s", "sub v2.4s, v4.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "phsubd xmm0, xmm1": { @@ -197,12 +197,12 @@ "NP 0x0f 0x38 0x07" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uzp1 v4.4h, v2.4h, v3.4h", "uzp2 v2.4h, v2.4h, v3.4h", "sqsub v2.8h, v4.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "phsubsw xmm0, xmm1": { @@ -222,12 +222,12 @@ "NP 0x0f 0x38 0x08" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sqshl v2.8b, v2.8b, #7", "srshr v2.8b, v2.8b, #7", "mul v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psignb xmm0, xmm1": { @@ -247,12 +247,12 @@ "NP 0x0f 0x38 0x09" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sqshl v2.4h, v2.4h, #15", "srshr v2.4h, v2.4h, #15", "mul v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psignw xmm0, xmm1": { @@ -272,12 +272,12 @@ "NP 0x0f 0x38 0x0a" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sqshl v2.2s, v2.2s, #31", "srshr v2.2s, v2.2s, #31", "mul v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psignd xmm0, xmm1": { @@ -298,14 +298,14 @@ "NP 0x0f 0x38 0x0b" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "smull v2.4s, v2.4h, v3.4h", "sshr v2.4s, v2.4s, #14", "movi v3.4s, #0x1, lsl #0", "add v2.4s, v2.4s, v3.4s", "shrn v2.4h, v2.4s, #1", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pmulhrsw xmm0, xmm1": { @@ -389,7 +389,7 @@ ] }, "ptest xmm0, xmm1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": [ "0x66 0x0f 0x38 0x17" ], @@ -402,16 +402,14 @@ "addv h3, v3.8h", "umov w20, v2.h[0]", "umov w21, v3.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", "lsl x20, x20, #30", "orr w20, w20, w21, lsl #29", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, @@ -421,9 +419,9 @@ "NP 0x0f 0x38 0x1c" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "abs v2.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pabsb xmm0, xmm1": { @@ -441,9 +439,9 @@ "NP 0x0f 0x38 0x1d" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "abs v2.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pabsw xmm0, xmm1": { @@ -461,9 +459,9 @@ "NP 0x0f 0x38 0x1e" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "abs v2.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pabsd xmm0, xmm1": { @@ -629,7 +627,7 @@ "0x66 0x0f 0x38 0x41" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #1952]", + "ldr q2, [x28, #1968]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -684,117 +682,131 @@ ] }, "sha256rnds2 xmm0, xmm1": { - "ExpectedInstructionCount": 106, + "ExpectedInstructionCount": 120, "Comment": [ "0x66 0x0f 0x38 0xcb" ], "ExpectedArm64ASM": [ - "sub sp, sp, #0x120 (288)", + "sub sp, sp, #0x200 (512)", "mov w20, v17.s[3]", - "mov w21, v17.s[2]", - "mov w22, v16.s[3]", - "mov w23, v16.s[2]", - "str w23, [sp]", - "mov w23, v17.s[1]", - "mov w24, v17.s[0]", + "str w20, [sp, #96]", + "mov w20, v17.s[2]", + "str w20, [sp, #64]", + "mov w20, v16.s[3]", + "mov w21, v16.s[2]", + "str w21, [sp]", + "mov w21, v17.s[1]", + "str w21, [sp, #32]", + "mov w21, v17.s[0]", + "mov w22, v16.s[1]", + "mov w23, v16.s[0]", + "mov w24, v16.s[0]", "mov w25, v16.s[1]", - "mov w26, v16.s[0]", - "mov w27, v16.s[0]", - "mov w30, v16.s[1]", - "str w30, [sp, #32]", - "and w30, w23, w24", - "str w24, [sp, #64]", - "bic w24, w25, w23", - "str w25, [sp, #96]", - "eor w24, w30, w24", - "ror w25, w23, #6", - "ror w30, w23, #11", - "eor w25, w25, w30", - "ror w30, w23, #25", - "eor w25, w25, w30", - "add w24, w24, w25", - "add w24, w24, w27", - "add w24, w24, w26", - "and w25, w20, w21", - "and w30, w20, w22", - "eor w25, w25, w30", - "and w30, w21, w22", + "str w25, [sp, #128]", + "ldr w25, [sp, #32]", + "and w30, w25, w21", "str w21, [sp, #160]", - "str w22, [sp, #128]", - "eor w21, w25, w30", - "add w21, w24, w21", - "ror w22, w20, #2", - "ror w24, w20, #13", - "eor w22, w22, w24", - "ror w24, w20, #22", - "eor w22, w22, w24", + "bic w21, w22, w25", + "str w22, [sp, #192]", + "eor w21, w30, w21", + "ror w22, w25, #6", + "ror w30, w25, #11", + "eor w22, w22, w30", + "ror w30, w25, #25", + "eor w22, w22, w30", "add w21, w21, w22", - "str w21, [sp, #192]", - "ldr w21, [sp, #64]", - "and w22, w23, w21", - "ldr w24, [sp, #96]", - "bic w25, w24, w23", - "eor w22, w22, w25", - "ror w25, w23, #6", - "ror w30, w23, #11", - "eor w25, w25, w30", - "ror w30, w23, #25", - "eor w25, w25, w30", - "add w22, w22, w25", - "add w22, w22, w27", - "add w22, w22, w26", - "ldr w25, [sp]", - "add w22, w22, w25", - "and w25, w22, w23", - "bic w26, w21, w22", - "eor w25, w25, w26", - "ror w26, w22, #6", - "ror w27, w22, #11", - "eor w26, w26, w27", - "ror w27, w22, #25", - "eor w26, w26, w27", - "add w25, w25, w26", - "ldr w26, [sp, #32]", - "add w25, w25, w26", - "str w26, [sp, #256]", - "add w25, w25, w24", - "str w24, [sp, #224]", - "ldr w24, [sp, #192]", - "and w26, w24, w20", - "ldr w27, [sp, #160]", - "and w30, w24, w27", - "eor w26, w26, w30", - "and w20, w20, w27", - "eor w20, w26, w20", - "add w20, w25, w20", - "ror w25, w24, #2", - "ror w26, w24, #13", - "eor w25, w25, w26", - "ror w26, w24, #22", - "eor w25, w25, w26", - "add w20, w20, w25", - "and w23, w22, w23", - "bic w21, w21, w22", - "eor w21, w23, w21", - "ror w23, w22, #6", + "add w21, w21, w24", + "str w24, [sp, #256]", + "add w21, w21, w23", + "str w23, [sp, #224]", + "ldr w22, [sp, #64]", + "ldr w23, [sp, #96]", + "and w24, w23, w22", + "and w30, w23, w20", + "eor w24, w24, w30", + "and w30, w22, w20", + "str w22, [sp, #320]", + "str w20, [sp, #288]", + "eor w20, w24, w30", + "add w20, w21, w20", + "ror w21, w23, #2", + "ror w22, w23, #13", + "eor w21, w21, w22", + "ror w22, w23, #22", + "eor w21, w21, w22", + "add w20, w20, w21", + "str w20, [sp, #352]", + "ldr w20, [sp, #160]", + "and w21, w25, w20", + "ldr w22, [sp, #192]", + "bic w24, w22, w25", + "eor w21, w21, w24", + "ror w24, w25, #6", + "ror w30, w25, #11", + "eor w24, w24, w30", + "ror w30, w25, #25", + "eor w24, w24, w30", + "add w21, w21, w24", + "ldr w24, [sp, #256]", + "add w21, w21, w24", + "ldr w24, [sp, #224]", + "add w21, w21, w24", + "ldr w24, [sp]", + "add w21, w21, w24", + "and w24, w21, w25", + "bic w30, w20, w21", + "str w20, [sp, #384]", + "eor w20, w24, w30", + "ror w24, w21, #6", + "ror w30, w21, #11", + "eor w24, w24, w30", + "ror w30, w21, #25", + "str w21, [sp, #480]", + "eor w21, w24, w30", + "add w20, w20, w21", + "ldr w21, [sp, #128]", + "add w20, w20, w21", + "str w21, [sp, #448]", + "add w20, w20, w22", + "str w22, [sp, #416]", + "ldr w21, [sp, #352]", + "and w22, w21, w23", + "ldr w24, [sp, #320]", + "and w30, w21, w24", + "eor w22, w22, w30", + "and w23, w23, w24", + "eor w22, w22, w23", + "add w20, w20, w22", + "ror w22, w21, #2", + "ror w23, w21, #13", + "eor w22, w22, w23", + "ror w23, w21, #22", + "eor w22, w22, w23", + "add w20, w20, w22", + "ldr w22, [sp, #480]", + "and w23, w22, w25", + "ldr w24, [sp, #384]", + "bic w24, w24, w22", + "eor w23, w23, w24", + "ror w24, w22, #6", "ror w25, w22, #11", - "eor w23, w23, w25", + "eor w24, w24, w25", "ror w25, w22, #25", - "eor w23, w23, w25", - "add w21, w21, w23", - "ldr w23, [sp, #256]", - "add w21, w21, w23", - "ldr w23, [sp, #224]", - "add w21, w21, w23", - "ldr w23, [sp, #128]", - "add w21, w21, w23", + "eor w24, w24, w25", + "add w23, w23, w24", + "ldr w24, [sp, #448]", + "add w23, w23, w24", + "ldr w24, [sp, #416]", + "add w23, w23, w24", + "ldr w24, [sp, #288]", + "add w23, w23, w24", "mov v2.16b, v16.16b", "mov v2.s[3], w20", - "mov v2.s[2], w24", - "mov v2.s[1], w21", + "mov v2.s[2], w21", + "mov v2.s[1], w23", "mov v16.16b, v2.16b", "mov v16.s[0], w22", - "add sp, sp, #0x120 (288)" + "add sp, sp, #0x200 (512)" ] }, "sha256msg1 xmm0, xmm1": { @@ -809,26 +821,26 @@ "mov w23, v16.s[1]", "mov w24, v16.s[0]", "ror w25, w20, #7", - "ror w26, w20, #18", - "eor w25, w25, w26", + "ror w30, w20, #18", + "eor w25, w25, w30", "lsr w20, w20, #3", "eor w20, w25, w20", "add w20, w21, w20", "ror w25, w21, #7", - "ror w26, w21, #18", - "eor w25, w25, w26", + "ror w30, w21, #18", + "eor w25, w25, w30", "lsr w21, w21, #3", "eor w21, w25, w21", "add w21, w22, w21", "ror w25, w22, #7", - "ror w26, w22, #18", - "eor w25, w25, w26", + "ror w30, w22, #18", + "eor w25, w25, w30", "lsr w22, w22, #3", "eor w22, w25, w22", "add w22, w23, w22", "ror w25, w23, #7", - "ror w26, w23, #18", - "eor w25, w25, w26", + "ror w30, w23, #18", + "eor w25, w25, w30", "lsr w23, w23, #3", "eor w23, w25, w23", "add w23, w24, w23", diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index 71ce4030a..4b37479f6 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -20,8 +20,8 @@ "NP 0x0f 0x3a 0x0f" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "str d2, [x28, #752]" + "ldr d2, [x28, #784]", + "str d2, [x28, #768]" ] }, "palignr mm0, mm1, 1": { @@ -30,10 +30,10 @@ "NP 0x0f 0x3a 0x0f" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "ext v2.8b, v2.8b, v3.8b, #1", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "palignr mm0, mm1, 255": { @@ -43,7 +43,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "roundps xmm0, xmm1, 00000000b": { @@ -315,7 +315,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2080]", + "ldr q2, [x28, #2096]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -325,7 +325,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2096]", + "ldr q2, [x28, #2112]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -344,7 +344,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2112]", + "ldr q2, [x28, #2128]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -364,7 +364,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2128]", + "ldr q2, [x28, #2144]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -383,7 +383,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2144]", + "ldr q2, [x28, #2160]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -393,7 +393,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2160]", + "ldr q2, [x28, #2176]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -462,7 +462,7 @@ "0x66 0x0f 0x3a 0x0e" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1704]", + "ldr x0, [x28, #1720]", "ldr q2, [x0, #3440]", "tbx v16.16b, {v17.16b}, v2.16b" ] @@ -1338,271 +1338,297 @@ ] }, "sha1rnds4 xmm0, xmm1, 00b": { - "ExpectedInstructionCount": 59, + "ExpectedInstructionCount": 65, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "sub sp, sp, #0x20 (32)", + "sub sp, sp, #0x60 (96)", "mov w20, #0x7999", "movk w20, #0x5a82, lsl #16", "mov w20, v17.s[3]", "mov w21, v17.s[2]", - "mov w22, v17.s[1]", - "mov w23, v17.s[0]", - "str w23, [sp]", - "mov w23, v16.s[3]", - "mov w24, v16.s[2]", - "mov w25, v16.s[1]", - "mov w26, v16.s[0]", - "and w27, w24, w25", - "bic w30, w26, w24", - "eor w27, w27, w30", - "ror w30, w23, #27", - "add w27, w27, w30", - "add w20, w27, w20", - "mov w27, #0x7999", - "movk w27, #0x5a82, lsl #16", - "add w20, w20, w27", - "ror w24, w24, #2", - "and w27, w23, w24", - "bic w30, w25, w23", - "eor w27, w27, w30", - "ror w30, w20, #27", - "add w27, w27, w30", - "add w21, w27, w21", - "add w21, w21, w26", - "mov w26, #0x7999", - "movk w26, #0x5a82, lsl #16", - "add w21, w21, w26", - "ror w23, w23, #2", - "and w27, w20, w23", - "bic w30, w24, w20", - "eor w27, w27, w30", + "str w21, [sp, #64]", + "mov w21, v17.s[1]", + "str w21, [sp, #32]", + "mov w21, v17.s[0]", + "str w21, [sp]", + "mov w21, v16.s[3]", + "mov w22, v16.s[2]", + "mov w23, v16.s[1]", + "mov w24, v16.s[0]", + "and w25, w22, w23", + "bic w30, w24, w22", + "eor w25, w25, w30", "ror w30, w21, #27", - "add w27, w27, w30", - "add w22, w27, w22", - "add w22, w22, w25", - "add w22, w22, w26", - "ror w20, w20, #2", - "and w25, w21, w20", - "bic w23, w23, w21", - "eor w23, w25, w23", - "ror w25, w22, #27", - "add w23, w23, w25", - "ldr w25, [sp]", - "add w23, w23, w25", - "add w23, w23, w24", - "add w23, w23, w26", + "add w25, w25, w30", + "add w20, w25, w20", + "mov w25, #0x7999", + "movk w25, #0x5a82, lsl #16", + "add w20, w20, w25", + "ror w22, w22, #2", + "and w25, w21, w22", + "bic w30, w23, w21", + "eor w25, w25, w30", + "ror w30, w20, #27", + "add w25, w25, w30", + "ldr w30, [sp, #64]", + "add w25, w25, w30", + "add w24, w25, w24", + "mov w25, #0x7999", + "movk w25, #0x5a82, lsl #16", + "add w24, w24, w25", "ror w21, w21, #2", + "and w25, w20, w21", + "bic w30, w22, w20", + "eor w25, w25, w30", + "ror w30, w24, #27", + "add w25, w25, w30", + "ldr w30, [sp, #32]", + "add w25, w25, w30", + "add w23, w25, w23", + "mov w25, #0x7999", + "movk w25, #0x5a82, lsl #16", + "add w23, w23, w25", + "ror w20, w20, #2", + "and w30, w24, w20", + "bic w21, w21, w24", + "eor w21, w30, w21", + "ror w30, w23, #27", + "add w21, w21, w30", + "ldr w30, [sp]", + "add w21, w21, w30", + "add w21, w21, w22", + "add w21, w21, w25", + "ror w22, w24, #2", "mov v2.16b, v16.16b", - "mov v2.s[3], w23", - "mov v2.s[2], w22", - "mov v2.s[1], w21", + "mov v2.s[3], w21", + "mov v2.s[2], w23", + "mov v2.s[1], w22", "mov v16.16b, v2.16b", "mov v16.s[0], w20", - "add sp, sp, #0x20 (32)" + "add sp, sp, #0x60 (96)" ] }, "sha1rnds4 xmm0, xmm1, 01b": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 61, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "sub sp, sp, #0x20 (32)", + "sub sp, sp, #0x60 (96)", "mov w20, #0xeba1", "movk w20, #0x6ed9, lsl #16", "mov w20, v17.s[3]", "mov w21, v17.s[2]", "mov w22, v17.s[1]", - "mov w23, v17.s[0]", - "str w23, [sp]", - "mov w23, v16.s[3]", - "mov w24, v16.s[2]", - "mov w25, v16.s[1]", - "mov w26, v16.s[0]", - "eor w27, w24, w25", - "eor w27, w27, w26", - "ror w30, w23, #27", - "add w27, w27, w30", - "add w20, w27, w20", - "mov w27, #0xeba1", - "movk w27, #0x6ed9, lsl #16", - "add w20, w20, w27", - "ror w24, w24, #2", - "eor w27, w23, w24", - "eor w27, w27, w25", - "ror w30, w20, #27", - "add w27, w27, w30", - "add w21, w27, w21", - "add w21, w21, w26", - "mov w26, #0xeba1", - "movk w26, #0x6ed9, lsl #16", - "add w21, w21, w26", - "ror w23, w23, #2", - "eor w27, w20, w23", - "eor w27, w27, w24", - "ror w30, w21, #27", - "add w27, w27, w30", - "add w22, w27, w22", - "add w22, w22, w25", - "add w22, w22, w26", - "ror w20, w20, #2", - "eor w25, w21, w20", - "eor w23, w25, w23", + "str w22, [sp, #32]", + "mov w22, v17.s[0]", + "str w22, [sp]", + "mov w22, v16.s[3]", + "mov w23, v16.s[2]", + "mov w24, v16.s[1]", + "mov w25, v16.s[0]", + "eor w30, w23, w24", + "eor w30, w30, w25", + "str w25, [sp, #64]", "ror w25, w22, #27", - "add w23, w23, w25", - "ldr w25, [sp]", - "add w23, w23, w25", - "add w23, w23, w24", - "add w23, w23, w26", + "add w25, w30, w25", + "add w20, w25, w20", + "mov w25, #0xeba1", + "movk w25, #0x6ed9, lsl #16", + "add w20, w20, w25", + "ror w23, w23, #2", + "eor w25, w22, w23", + "eor w25, w25, w24", + "ror w30, w20, #27", + "add w25, w25, w30", + "add w21, w25, w21", + "ldr w25, [sp, #64]", + "add w21, w21, w25", + "mov w25, #0xeba1", + "movk w25, #0x6ed9, lsl #16", + "add w21, w21, w25", + "ror w22, w22, #2", + "eor w25, w20, w22", + "eor w25, w25, w23", + "ror w30, w21, #27", + "add w25, w25, w30", + "ldr w30, [sp, #32]", + "add w25, w25, w30", + "add w24, w25, w24", + "mov w25, #0xeba1", + "movk w25, #0x6ed9, lsl #16", + "add w24, w24, w25", + "ror w20, w20, #2", + "eor w30, w21, w20", + "eor w22, w30, w22", + "ror w30, w24, #27", + "add w22, w22, w30", + "ldr w30, [sp]", + "add w22, w22, w30", + "add w22, w22, w23", + "add w22, w22, w25", "ror w21, w21, #2", "mov v2.16b, v16.16b", - "mov v2.s[3], w23", - "mov v2.s[2], w22", + "mov v2.s[3], w22", + "mov v2.s[2], w24", "mov v2.s[1], w21", "mov v16.16b, v2.16b", "mov v16.s[0], w20", - "add sp, sp, #0x20 (32)" + "add sp, sp, #0x60 (96)" ] }, "sha1rnds4 xmm0, xmm1, 10b": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 75, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "sub sp, sp, #0x20 (32)", + "sub sp, sp, #0x60 (96)", "mov w20, #0xbcdc", "movk w20, #0x8f1b, lsl #16", "mov w20, v17.s[3]", "mov w21, v17.s[2]", - "mov w22, v17.s[1]", - "mov w23, v17.s[0]", - "str w23, [sp]", - "mov w23, v16.s[3]", - "mov w24, v16.s[2]", - "mov w25, v16.s[1]", - "mov w26, v16.s[0]", - "and w27, w24, w25", - "and w30, w24, w26", - "eor w27, w27, w30", - "and w30, w25, w26", - "eor w27, w27, w30", - "ror w30, w23, #27", - "add w27, w27, w30", - "add w20, w27, w20", - "mov w27, #0xbcdc", - "movk w27, #0x8f1b, lsl #16", - "add w20, w20, w27", - "ror w24, w24, #2", - "and w27, w23, w24", - "and w30, w23, w25", - "eor w27, w27, w30", - "and w30, w24, w25", - "eor w27, w27, w30", - "ror w30, w20, #27", - "add w27, w27, w30", - "add w21, w27, w21", - "add w21, w21, w26", - "mov w26, #0xbcdc", - "movk w26, #0x8f1b, lsl #16", - "add w21, w21, w26", - "ror w23, w23, #2", - "and w27, w20, w23", - "and w30, w20, w24", - "eor w27, w27, w30", + "str w21, [sp, #64]", + "mov w21, v17.s[1]", + "str w21, [sp, #32]", + "mov w21, v17.s[0]", + "str w21, [sp]", + "mov w21, v16.s[3]", + "mov w22, v16.s[2]", + "mov w23, v16.s[1]", + "mov w24, v16.s[0]", + "and w25, w22, w23", + "and w30, w22, w24", + "eor w25, w25, w30", "and w30, w23, w24", - "eor w27, w27, w30", + "eor w25, w25, w30", "ror w30, w21, #27", - "add w27, w27, w30", - "add w22, w27, w22", - "add w22, w22, w25", - "add w22, w22, w26", - "ror w20, w20, #2", - "and w25, w21, w20", - "and w27, w21, w23", - "eor w25, w25, w27", - "and w23, w20, w23", - "eor w23, w25, w23", - "ror w25, w22, #27", - "add w23, w23, w25", - "ldr w25, [sp]", - "add w23, w23, w25", - "add w23, w23, w24", - "add w23, w23, w26", + "add w25, w25, w30", + "add w20, w25, w20", + "mov w25, #0xbcdc", + "movk w25, #0x8f1b, lsl #16", + "add w20, w20, w25", + "ror w22, w22, #2", + "and w25, w21, w22", + "and w30, w21, w23", + "eor w25, w25, w30", + "and w30, w22, w23", + "eor w25, w25, w30", + "ror w30, w20, #27", + "add w25, w25, w30", + "ldr w30, [sp, #64]", + "add w25, w25, w30", + "add w24, w25, w24", + "mov w25, #0xbcdc", + "movk w25, #0x8f1b, lsl #16", + "add w24, w24, w25", "ror w21, w21, #2", + "and w25, w20, w21", + "and w30, w20, w22", + "eor w25, w25, w30", + "and w30, w21, w22", + "eor w25, w25, w30", + "ror w30, w24, #27", + "add w25, w25, w30", + "ldr w30, [sp, #32]", + "add w25, w25, w30", + "add w23, w25, w23", + "mov w25, #0xbcdc", + "movk w25, #0x8f1b, lsl #16", + "add w23, w23, w25", + "ror w20, w20, #2", + "and w25, w24, w20", + "and w30, w24, w21", + "eor w25, w25, w30", + "and w21, w20, w21", + "eor w21, w25, w21", + "ror w25, w23, #27", + "add w21, w21, w25", + "ldr w25, [sp]", + "add w21, w21, w25", + "add w21, w21, w22", + "mov w22, #0xbcdc", + "movk w22, #0x8f1b, lsl #16", + "add w21, w21, w22", + "ror w22, w24, #2", "mov v2.16b, v16.16b", - "mov v2.s[3], w23", - "mov v2.s[2], w22", - "mov v2.s[1], w21", + "mov v2.s[3], w21", + "mov v2.s[2], w23", + "mov v2.s[1], w22", "mov v16.16b, v2.16b", "mov v16.s[0], w20", - "add sp, sp, #0x20 (32)" + "add sp, sp, #0x60 (96)" ] }, "sha1rnds4 xmm0, xmm1, 11b": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 61, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "sub sp, sp, #0x20 (32)", + "sub sp, sp, #0x60 (96)", "mov w20, #0xc1d6", "movk w20, #0xca62, lsl #16", "mov w20, v17.s[3]", "mov w21, v17.s[2]", "mov w22, v17.s[1]", - "mov w23, v17.s[0]", - "str w23, [sp]", - "mov w23, v16.s[3]", - "mov w24, v16.s[2]", - "mov w25, v16.s[1]", - "mov w26, v16.s[0]", - "eor w27, w24, w25", - "eor w27, w27, w26", - "ror w30, w23, #27", - "add w27, w27, w30", - "add w20, w27, w20", - "mov w27, #0xc1d6", - "movk w27, #0xca62, lsl #16", - "add w20, w20, w27", - "ror w24, w24, #2", - "eor w27, w23, w24", - "eor w27, w27, w25", - "ror w30, w20, #27", - "add w27, w27, w30", - "add w21, w27, w21", - "add w21, w21, w26", - "mov w26, #0xc1d6", - "movk w26, #0xca62, lsl #16", - "add w21, w21, w26", - "ror w23, w23, #2", - "eor w27, w20, w23", - "eor w27, w27, w24", - "ror w30, w21, #27", - "add w27, w27, w30", - "add w22, w27, w22", - "add w22, w22, w25", - "add w22, w22, w26", - "ror w20, w20, #2", - "eor w25, w21, w20", - "eor w23, w25, w23", + "str w22, [sp, #32]", + "mov w22, v17.s[0]", + "str w22, [sp]", + "mov w22, v16.s[3]", + "mov w23, v16.s[2]", + "mov w24, v16.s[1]", + "mov w25, v16.s[0]", + "eor w30, w23, w24", + "eor w30, w30, w25", + "str w25, [sp, #64]", "ror w25, w22, #27", - "add w23, w23, w25", - "ldr w25, [sp]", - "add w23, w23, w25", - "add w23, w23, w24", - "add w23, w23, w26", + "add w25, w30, w25", + "add w20, w25, w20", + "mov w25, #0xc1d6", + "movk w25, #0xca62, lsl #16", + "add w20, w20, w25", + "ror w23, w23, #2", + "eor w25, w22, w23", + "eor w25, w25, w24", + "ror w30, w20, #27", + "add w25, w25, w30", + "add w21, w25, w21", + "ldr w25, [sp, #64]", + "add w21, w21, w25", + "mov w25, #0xc1d6", + "movk w25, #0xca62, lsl #16", + "add w21, w21, w25", + "ror w22, w22, #2", + "eor w25, w20, w22", + "eor w25, w25, w23", + "ror w30, w21, #27", + "add w25, w25, w30", + "ldr w30, [sp, #32]", + "add w25, w25, w30", + "add w24, w25, w24", + "mov w25, #0xc1d6", + "movk w25, #0xca62, lsl #16", + "add w24, w24, w25", + "ror w20, w20, #2", + "eor w30, w21, w20", + "eor w22, w30, w22", + "ror w30, w24, #27", + "add w22, w22, w30", + "ldr w30, [sp]", + "add w22, w22, w30", + "add w22, w22, w23", + "add w22, w22, w25", "ror w21, w21, #2", "mov v2.16b, v16.16b", - "mov v2.s[3], w23", - "mov v2.s[2], w22", + "mov v2.s[3], w22", + "mov v2.s[2], w24", "mov v2.s[1], w21", "mov v16.16b, v2.16b", "mov v16.s[0], w20", - "add sp, sp, #0x20 (32)" + "add sp, sp, #0x60 (96)" ] } } diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 0990f60a8..e33ac8472 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -11,77 +11,71 @@ }, "Instructions": { "add bl, cl": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x00", "ExpectedArm64ASM": [ "uxtb w20, w5", "uxtb w21, w7", - "add w22, w21, w20", - "bfxil x7, x22, #0, #8", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "add w26, w21, w20", + "bfxil x7, x26, #0, #8", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "add bx, cx": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x01", "ExpectedArm64ASM": [ "uxth w20, w5", "uxth w21, w7", - "add w22, w21, w20", - "bfxil x7, x22, #0, #16", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "add w26, w21, w20", + "bfxil x7, x26, #0, #16", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "add ebx, ecx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x01", "ExpectedArm64ASM": [ "mov x20, x7", "add w7, w20, w5", - "eor w21, w20, w5", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor w27, w20, w5", + "mov x26, x7", "cmn w20, w5" ] }, "add rbx, rcx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x01", "ExpectedArm64ASM": [ "mov x20, x7", "add x7, x20, x5", - "eor x21, x20, x5", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor x27, x20, x5", + "mov x26, x7", "cmn x20, x5" ] }, "db 0x02, 0xcb": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": [ "0x02", "add bl, cl but modrm.rm as source" @@ -89,25 +83,23 @@ "ExpectedArm64ASM": [ "uxtb w20, w7", "uxtb w21, w5", - "add w22, w21, w20", - "bfxil x5, x22, #0, #8", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "add w26, w21, w20", + "bfxil x5, x26, #0, #8", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "db 0x66, 0x03, 0xcb": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": [ "0x03", "add bx, cx but modrm.rm as source" @@ -115,25 +107,23 @@ "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w5", - "add w22, w21, w20", - "bfxil x5, x22, #0, #16", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "add w26, w21, w20", + "bfxil x5, x26, #0, #16", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "db 0x03, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": [ "0x03", "add ebx, ecx but modrm.rm as source" @@ -141,14 +131,13 @@ "ExpectedArm64ASM": [ "mov x20, x5", "add w5, w20, w7", - "eor w21, w20, w7", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor w27, w20, w7", + "mov x26, x5", "cmn w20, w7" ] }, "db 0x48, 0x03, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": [ "0x03", "add rbx, rcx but modrm.rm as source" @@ -156,168 +145,152 @@ "ExpectedArm64ASM": [ "mov x20, x5", "add x5, x20, x7", - "eor x21, x20, x7", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor x27, x20, x7", + "mov x26, x5", "cmn x20, x7" ] }, "add al, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x04", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "uxtb w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "add ax, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x05", "ExpectedArm64ASM": [ - "uxth w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "uxth w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "add eax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ - "mov x20, x4", - "add w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn w20, #0x1 (1)" + "mov x27, x4", + "add w4, w27, #0x1 (1)", + "mov x26, x4", + "cmn w27, #0x1 (1)" ] }, "add rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn x20, #0x1 (1)" + "mov x27, x4", + "add x4, x27, #0x1 (1)", + "mov x26, x4", + "cmn x27, #0x1 (1)" ] }, "add al, -1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "0x04", "ExpectedArm64ASM": [ "uxtb w20, w4", - "add w21, w20, #0xff (255)", - "bfxil x4, x21, #0, #8", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", + "add w26, w20, #0xff (255)", + "bfxil x4, x26, #0, #8", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "ubfx x22, x26, #8, #1", + "orr w21, w21, w22, lsl #29", + "bic w20, w20, w26", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "add ax, -1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffff", "uxth w21, w4", - "add w20, w21, w20", - "bfxil x4, x20, #0, #16", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x20, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "add w26, w21, w20", + "bfxil x4, x26, #0, #16", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x22, x26, #16, #1", + "orr w20, w20, w22, lsl #29", + "bic w21, w21, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "add eax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov x21, x4", "add w4, w21, w20", - "eor w22, w21, w20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w21, w20", + "mov x26, x4", "cmn w21, w20" ] }, "add rax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, #0x1 (1)", - "eor x22, x21, x20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x21, x20", + "mov x26, x4", "cmn x21, x20" ] }, "or bl, bh": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "", "ExpectedArm64ASM": [ "lsr w20, w7, #8", - "orr w20, w7, w20", - "bfxil x7, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w7, w20", + "bfxil x7, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "or bl, cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x08", "ExpectedArm64ASM": [ - "orr w20, w7, w5", - "bfxil x7, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w7, w5", + "bfxil x7, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "or bx, cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x09", "ExpectedArm64ASM": [ - "orr w20, w7, w5", - "bfxil x7, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w7, w5", + "bfxil x7, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "or ebx, ecx": { @@ -325,7 +298,7 @@ "Comment": "0x09", "ExpectedArm64ASM": [ "orr w7, w7, w5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst w7, w7" ] }, @@ -334,34 +307,32 @@ "Comment": "0x09", "ExpectedArm64ASM": [ "orr x7, x7, x5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst x7, x7" ] }, "db 0x0A, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x0A", "or bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "orr w20, w5, w7", - "bfxil x5, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w5, w7", + "bfxil x5, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "db 0x66, 0x0B, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x0B", "or bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "orr w20, w5, w7", - "bfxil x5, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w5, w7", + "bfxil x5, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "db 0x0B, 0xcb": { @@ -372,7 +343,7 @@ ], "ExpectedArm64ASM": [ "orr w5, w5, w7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst w5, w5" ] }, @@ -384,28 +355,26 @@ ], "ExpectedArm64ASM": [ "orr x5, x5, x7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst x5, x5" ] }, "or al, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x0C", "ExpectedArm64ASM": [ - "orr w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "or ax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x0D", "ExpectedArm64ASM": [ - "orr w20, w4, #0x1", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w4, #0x1", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "or eax, 1": { @@ -413,7 +382,7 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "orr w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -422,28 +391,26 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "orr x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "or al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x0C", "ExpectedArm64ASM": [ - "orr w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "or ax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x0D", "ExpectedArm64ASM": [ - "orr w20, w4, #0xffff", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "orr w26, w4, #0xffff", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "or eax, -1": { @@ -452,7 +419,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "orr w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -462,12 +429,12 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "orr x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "adc bl, cl": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0x10", "ExpectedArm64ASM": [ "uxtb w20, w5", @@ -476,21 +443,19 @@ "uxtb w23, w7", "add w22, w23, w22", "bfxil x7, x22, #0, #8", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", @@ -498,7 +463,7 @@ ] }, "adc bx, cx": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0x11", "ExpectedArm64ASM": [ "uxth w20, w5", @@ -507,21 +472,19 @@ "uxth w23, w7", "add w22, w23, w22", "bfxil x7, x22, #0, #16", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "ubfx x20, x20, #15, #1", "orr w20, w21, w20, lsl #28", @@ -529,7 +492,7 @@ ] }, "adc ebx, ecx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x11", "ExpectedArm64ASM": [ "mov w20, w5", @@ -537,28 +500,26 @@ "add w21, w20, w21", "mov w22, w7", "add w7, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x7", "adcs wzr, w22, w20" ] }, "adc rbx, rcx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x11", "ExpectedArm64ASM": [ "cset w20, hs", "add x20, x5, x20", "mov x21, x7", "add x7, x21, x20", - "eor x20, x21, x5", - "strb w20, [x28, #708]", - "strb w7, [x28, #706]", + "eor x27, x21, x5", + "mov x26, x7", "adcs xzr, x21, x5" ] }, "db 0x12, 0xcb": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": [ "0x12", "adc bl, cl but modrm.rm as source" @@ -570,21 +531,19 @@ "uxtb w23, w5", "add w22, w23, w22", "bfxil x5, x22, #0, #8", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", @@ -592,7 +551,7 @@ ] }, "db 0x66, 0x13, 0xcb": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": [ "0x13", "adc bx, cx but modrm.rm as source" @@ -604,21 +563,19 @@ "uxth w23, w5", "add w22, w23, w22", "bfxil x5, x22, #0, #16", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", - "cset x26, ls", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", + "cset x25, ls", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "bic w20, w22, w20", "ubfx x20, x20, #15, #1", "orr w20, w21, w20, lsl #28", @@ -626,7 +583,7 @@ ] }, "db 0x13, 0xcb": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": [ "0x13", "adc ebx, ecx but modrm.rm as source" @@ -637,14 +594,13 @@ "add w21, w20, w21", "mov w22, w5", "add w5, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x5", "adcs wzr, w22, w20" ] }, "db 0x48, 0x13, 0xcb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": [ "0x13", "adc rbx, rcx but modrm.rm as source" @@ -654,98 +610,91 @@ "add x20, x7, x20", "mov x21, x5", "add x5, x21, x20", - "eor x20, x21, x7", - "strb w20, [x28, #708]", - "strb w5, [x28, #706]", + "eor x27, x21, x7", + "mov x26, x5", "adcs xzr, x21, x7" ] }, "adc al, 1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x14", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxtb w22, w4", - "add w20, w22, w20", + "uxtb w27, w4", + "add w20, w27, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0x1 (1)", - "cset x24, lo", - "cmp w20, #0x1 (1)", - "cset x25, ls", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0x1 (1)", + "cset x22, lo", + "cmp w26, #0x1 (1)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "adc ax, 1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxth w22, w4", - "add w20, w22, w20", + "uxth w27, w4", + "add w20, w27, w20", "bfxil x4, x20, #0, #16", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, #0x1 (1)", - "cset x24, lo", - "cmp w20, #0x1 (1)", - "cset x25, ls", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, #0x1 (1)", + "cset x22, lo", + "cmp w26, #0x1 (1)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "adc eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "add w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs wzr, w22, w20" + "mov w27, w4", + "add w4, w27, w21", + "mov x26, x4", + "adcs wzr, w27, w20" ] }, "adc rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "add x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs xzr, x22, x20" + "mov x27, x4", + "add x4, x27, x21", + "mov x26, x4", + "adcs xzr, x27, x20" ] }, "adc al, -1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "0x14", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -754,27 +703,25 @@ "uxtb w22, w4", "add w20, w22, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0xff (255)", - "cset x24, lo", - "cmp w20, #0xff (255)", - "cset x25, ls", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0xff (255)", + "cset x23, lo", + "cmp w26, #0xff (255)", + "cset x24, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w22, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "adc ax, -1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -783,27 +730,25 @@ "uxth w23, w4", "add w22, w23, w22", "bfxil x4, x22, #0, #16", - "uxth w22, w22", - "eor w24, w23, #0xffff", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w20", - "cset x25, lo", - "cmp w22, w20", + "uxth w26, w22", + "eor w27, w23, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w20", + "cset x24, lo", + "cmp w26, w20", "cset x20, ls", "cmp x21, #0x1 (1)", - "csel x20, x20, x25, eq", - "orr w20, w24, w20, lsl #29", - "bic w21, w23, w22", + "csel x20, x20, x24, eq", + "orr w20, w22, w20, lsl #29", + "bic w21, w23, w26", "ubfx x21, x21, #15, #1", "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "adc eax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", @@ -811,14 +756,13 @@ "add w21, w20, w21", "mov w22, w4", "add w4, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x4", "adcs wzr, w22, w20" ] }, "adc rax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x15", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", @@ -826,14 +770,13 @@ "add x21, x20, x21", "mov x22, x4", "add x4, x22, x21", - "eor x21, x22, x20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x22, x20", + "mov x26, x4", "adcs xzr, x22, x20" ] }, "sbb bl, cl": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0x18", "ExpectedArm64ASM": [ "uxtb w20, w5", @@ -842,21 +785,19 @@ "uxtb w23, w7", "sub w22, w23, w22", "bfxil x7, x22, #0, #8", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", @@ -864,7 +805,7 @@ ] }, "sbb bx, cx": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0x19", "ExpectedArm64ASM": [ "uxth w20, w5", @@ -873,21 +814,19 @@ "uxth w23, w7", "sub w22, w23, w22", "bfxil x7, x22, #0, #16", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "ubfx x20, x20, #15, #1", "orr w20, w21, w20, lsl #28", @@ -895,7 +834,7 @@ ] }, "sbb ebx, ecx": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "0x19", "ExpectedArm64ASM": [ "mov w20, w5", @@ -903,9 +842,8 @@ "add w21, w20, w21", "mov w22, w7", "sub w7, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x7", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -916,16 +854,15 @@ ] }, "sbb rbx, rcx": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "0x19", "ExpectedArm64ASM": [ "cset w20, hs", "add x20, x5, x20", "mov x21, x7", "sub x7, x21, x20", - "eor x20, x21, x5", - "strb w20, [x28, #708]", - "strb w7, [x28, #706]", + "eor x27, x21, x5", + "mov x26, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20", @@ -936,7 +873,7 @@ ] }, "db 0x1A, 0xcb": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": [ "0x1A", "sbb bl, cl but modrm.rm as source" @@ -948,21 +885,19 @@ "uxtb w23, w5", "sub w22, w23, w22", "bfxil x5, x22, #0, #8", - "uxtb w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxtb w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", @@ -970,7 +905,7 @@ ] }, "db 0x66, 0x1B, 0xcb": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": [ "0x1B", "sbb bx, cx but modrm.rm as source" @@ -982,21 +917,19 @@ "uxth w23, w5", "sub w22, w23, w22", "bfxil x5, x22, #0, #16", - "uxth w22, w22", - "eor w24, w23, w20", - "strb w24, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x24, nzcv", - "cmp w22, w23", - "cset x25, hi", - "cmp w22, w23", - "cset x26, hs", + "uxth w26, w22", + "eor w27, w23, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "cmp w26, w23", + "cset x24, hi", + "cmp w26, w23", + "cset x25, hs", "cmp x21, #0x1 (1)", - "csel x21, x26, x25, eq", - "orr w21, w24, w21, lsl #29", + "csel x21, x25, x24, eq", + "orr w21, w22, w21, lsl #29", "eor w20, w23, w20", - "eor w22, w22, w23", + "eor w22, w26, w23", "and w20, w22, w20", "ubfx x20, x20, #15, #1", "orr w20, w21, w20, lsl #28", @@ -1004,7 +937,7 @@ ] }, "db 0x1B, 0xcb": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": [ "0x1B", "sbb ebx, ecx but modrm.rm as source" @@ -1015,9 +948,8 @@ "add w21, w20, w21", "mov w22, w5", "sub w5, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x5", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -1028,7 +960,7 @@ ] }, "db 0x48, 0x1B, 0xcb": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": [ "0x1B", "sbb rbx, rcx but modrm.rm as source" @@ -1038,9 +970,8 @@ "add x20, x7, x20", "mov x21, x5", "sub x5, x21, x20", - "eor x20, x21, x7", - "strb w20, [x28, #708]", - "strb w5, [x28, #706]", + "eor x27, x21, x7", + "mov x26, x5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20", @@ -1051,103 +982,97 @@ ] }, "sbb al, 1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x1C", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxtb w22, w4", - "sub w20, w22, w20", + "uxtb w27, w4", + "sub w20, w27, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sbb ax, 1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxth w22, w4", - "sub w20, w22, w20", + "uxth w27, w4", + "sub w20, w27, w20", "bfxil x4, x20, #0, #16", - "uxth w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxth w26, w20", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "sub w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov w27, w4", + "sub w4, w27, w21", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "sub x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov x27, x4", + "sub x4, x27, x21", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "sbb al, -1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "0x1C", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -1156,27 +1081,25 @@ "uxtb w22, w4", "sub w20, w22, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w22", + "cset x23, hi", + "cmp w26, w22", + "cset x24, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w22", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sbb ax, -1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -1185,27 +1108,25 @@ "uxth w22, w4", "sub w20, w22, w20", "bfxil x4, x20, #0, #16", - "uxth w20, w20", - "eor w23, w22, #0xffff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxth w26, w20", + "eor w27, w22, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "cmp w26, w22", + "cset x23, hi", + "cmp w26, w22", + "cset x24, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w22", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sbb eax, -1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", @@ -1213,9 +1134,8 @@ "add w21, w20, w21", "mov w22, w4", "sub w4, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -1226,7 +1146,7 @@ ] }, "sbb rax, -1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", @@ -1234,9 +1154,8 @@ "add x21, x20, x21", "mov x22, x4", "sub x4, x22, x21", - "eor x21, x22, x20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x22, x20", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -1247,23 +1166,21 @@ ] }, "and bl, cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x20", "ExpectedArm64ASM": [ - "and w20, w7, w5", - "bfxil x7, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w7, w5", + "bfxil x7, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "and bx, cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x21", "ExpectedArm64ASM": [ - "and w20, w7, w5", - "bfxil x7, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w7, w5", + "bfxil x7, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "and ebx, ecx": { @@ -1271,7 +1188,7 @@ "Comment": "0x21", "ExpectedArm64ASM": [ "and w7, w7, w5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst w7, w7" ] }, @@ -1280,34 +1197,32 @@ "Comment": "0x21", "ExpectedArm64ASM": [ "and x7, x7, x5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst x7, x7" ] }, "db 0x22, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x22", "and bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "and w20, w5, w7", - "bfxil x5, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w5, w7", + "bfxil x5, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "db 0x66, 0x23, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x23", "and bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "and w20, w5, w7", - "bfxil x5, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w5, w7", + "bfxil x5, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "db 0x23, 0xcb": { @@ -1318,7 +1233,7 @@ ], "ExpectedArm64ASM": [ "and w5, w5, w7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst w5, w5" ] }, @@ -1330,28 +1245,26 @@ ], "ExpectedArm64ASM": [ "and x5, x5, x7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst x5, x5" ] }, "and al, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x24", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "and ax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x25", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w4, #0x1", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "and eax, 1": { @@ -1359,7 +1272,7 @@ "Comment": "0x25", "ExpectedArm64ASM": [ "and w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1368,28 +1281,26 @@ "Comment": "0x25", "ExpectedArm64ASM": [ "and x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "and al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x24", "ExpectedArm64ASM": [ - "and w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "and ax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x25", "ExpectedArm64ASM": [ - "and w20, w4, #0xffff", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w4, #0xffff", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "and eax, -1": { @@ -1398,7 +1309,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "and w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1408,65 +1319,60 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "and x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "sub bl, cl": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x28", "ExpectedArm64ASM": [ "uxtb w20, w5", "uxtb w21, w7", - "sub w22, w21, w20", - "bfxil x7, x22, #0, #8", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "bfxil x7, x26, #0, #8", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "sub bx, cx": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x29", "ExpectedArm64ASM": [ "uxth w20, w5", "uxth w21, w7", - "sub w22, w21, w20", - "bfxil x7, x22, #0, #16", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "bfxil x7, x26, #0, #16", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "sub ebx, ecx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x29", "ExpectedArm64ASM": [ "mov x20, x7", "sub w7, w20, w5", - "eor w21, w20, w5", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor w27, w20, w5", + "mov x26, x7", "cmp w20, w5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1474,14 +1380,13 @@ ] }, "sub rbx, rcx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x29", "ExpectedArm64ASM": [ "mov x20, x7", "sub x7, x20, x5", - "eor x21, x20, x5", - "strb w21, [x28, #708]", - "strb w7, [x28, #706]", + "eor x27, x20, x5", + "mov x26, x7", "cmp x20, x5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1489,7 +1394,7 @@ ] }, "db 0x2A, 0xcb": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": [ "0x2A", "sub bl, cl but modrm.rm as source" @@ -1497,25 +1402,23 @@ "ExpectedArm64ASM": [ "uxtb w20, w7", "uxtb w21, w5", - "sub w22, w21, w20", - "bfxil x5, x22, #0, #8", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "bfxil x5, x26, #0, #8", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "db 0x66, 0x2B, 0xcb": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": [ "0x2B", "sub bx, cx but modrm.rm as source" @@ -1523,25 +1426,23 @@ "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w5", - "sub w22, w21, w20", - "bfxil x5, x22, #0, #16", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "bfxil x5, x26, #0, #16", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "db 0x2B, 0xcb": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": [ "0x2B", "sub ebx, ecx but modrm.rm as source" @@ -1549,9 +1450,8 @@ "ExpectedArm64ASM": [ "mov x20, x5", "sub w5, w20, w7", - "eor w21, w20, w7", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor w27, w20, w7", + "mov x26, x5", "cmp w20, w7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1559,7 +1459,7 @@ ] }, "db 0x48, 0x2B, 0xcb": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": [ "0x2B", "sub rbx, rcx but modrm.rm as source" @@ -1567,9 +1467,8 @@ "ExpectedArm64ASM": [ "mov x20, x5", "sub x5, x20, x7", - "eor x21, x20, x7", - "strb w21, [x28, #708]", - "strb w5, [x28, #706]", + "eor x27, x20, x7", + "mov x26, x5", "cmp x20, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1577,122 +1476,111 @@ ] }, "sub al, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x2C", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "uxtb w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sub ax, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x2D", "ExpectedArm64ASM": [ - "uxth w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "uxth w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x2D", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp w20, #0x1 (1)", + "mov x27, x4", + "sub w4, w27, #0x1 (1)", + "mov x26, x4", + "cmp w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x2D", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp x20, #0x1 (1)", + "mov x27, x4", + "sub x4, x27, #0x1 (1)", + "mov x26, x4", + "cmp x27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "sub al, -1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "0x2C", "ExpectedArm64ASM": [ "uxtb w20, w4", - "sub w21, w20, #0xff (255)", - "bfxil x4, x21, #0, #8", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", + "sub w26, w20, #0xff (255)", + "bfxil x4, x26, #0, #8", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "ubfx x22, x26, #8, #1", + "orr w21, w21, w22, lsl #29", + "bic w20, w26, w20", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "sub ax, -1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffff", "uxth w21, w4", - "sub w20, w21, w20", - "bfxil x4, x20, #0, #16", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x20, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "sub w26, w21, w20", + "bfxil x4, x26, #0, #16", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x22, x26, #16, #1", + "orr w20, w20, w22, lsl #29", + "bic w21, w26, w21", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov x21, x4", "sub w4, w21, w20", - "eor w22, w21, w20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w21, w20", + "mov x26, x4", "cmp w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1700,15 +1588,14 @@ ] }, "sub rax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, x20", - "eor x22, x21, x20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x21, x20", + "mov x26, x4", "cmp x21, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1716,23 +1603,21 @@ ] }, "xor bl, cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x30", "ExpectedArm64ASM": [ - "eor w20, w7, w5", - "bfxil x7, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w7, w5", + "bfxil x7, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "xor bx, cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x31", "ExpectedArm64ASM": [ - "eor w20, w7, w5", - "bfxil x7, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w7, w5", + "bfxil x7, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "xor ebx, ecx": { @@ -1740,7 +1625,7 @@ "Comment": "0x31", "ExpectedArm64ASM": [ "eor w7, w7, w5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst w7, w7" ] }, @@ -1749,34 +1634,32 @@ "Comment": "0x31", "ExpectedArm64ASM": [ "eor x7, x7, x5", - "strb w7, [x28, #706]", + "mov x26, x7", "tst x7, x7" ] }, "db 0x32, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x32", "xor bl, cl but modrm.rm as source" ], "ExpectedArm64ASM": [ - "eor w20, w5, w7", - "bfxil x5, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w5, w7", + "bfxil x5, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "db 0x66, 0x33, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x33", "xor bx, cx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "eor w20, w5, w7", - "bfxil x5, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w5, w7", + "bfxil x5, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "db 0x33, 0xcb": { @@ -1787,7 +1670,7 @@ ], "ExpectedArm64ASM": [ "eor w5, w5, w7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst w5, w5" ] }, @@ -1799,28 +1682,26 @@ ], "ExpectedArm64ASM": [ "eor x5, x5, x7", - "strb w5, [x28, #706]", + "mov x26, x5", "tst x5, x5" ] }, "xor al, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x34", "ExpectedArm64ASM": [ - "eor w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "xor ax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x35", "ExpectedArm64ASM": [ - "eor w20, w4, #0x1", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w4, #0x1", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "xor eax, 1": { @@ -1828,7 +1709,7 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "eor w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1837,50 +1718,46 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "eor x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp bl, cl": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0x38", "ExpectedArm64ASM": [ "uxtb w20, w5", "uxtb w21, w7", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "xor al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x34", "ExpectedArm64ASM": [ - "eor w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "xor ax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x35", "ExpectedArm64ASM": [ - "eor w20, w4, #0xffff", - "bfxil x4, x20, #0, #16", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "eor w26, w4, #0xffff", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16" ] }, "xor eax, -1": { @@ -1889,7 +1766,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "eor w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1899,42 +1776,38 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "eor x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp bx, cx": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": "0x39", "ExpectedArm64ASM": [ "uxth w20, w5", "uxth w21, w7", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "cmp ebx, ecx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "0x39", "ExpectedArm64ASM": [ "mov w20, w5", "mov w21, w7", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1942,13 +1815,11 @@ ] }, "cmp rbx, rcx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x39", "ExpectedArm64ASM": [ - "sub x20, x7, x5", - "eor x21, x7, x5", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", + "sub x26, x7, x5", + "eor x27, x7, x5", "cmp x7, x5", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1956,7 +1827,7 @@ ] }, "db 0x3A, 0xcb": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": [ "0x3A", "cmp bl, cl but modrm.rm as source" @@ -1964,24 +1835,22 @@ "ExpectedArm64ASM": [ "uxtb w20, w7", "uxtb w21, w5", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "db 0x66, 0x3B, 0xcb": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 14, "Comment": [ "0x3B", "cmp bx, cx but modrm.rm as source" @@ -1989,24 +1858,22 @@ "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w5", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "db 0x3B, 0xcb": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": [ "0x3B", "cmp ebx, ecx but modrm.rm as source" @@ -2014,10 +1881,8 @@ "ExpectedArm64ASM": [ "mov w20, w7", "mov w21, w5", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -2025,16 +1890,14 @@ ] }, "db 0x48, 0x3B, 0xcb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": [ "0x3B", "cmp rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ - "sub x20, x5, x7", - "eor x21, x5, x7", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", + "sub x26, x5, x7", + "eor x27, x5, x7", "cmp x5, x7", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -2042,117 +1905,104 @@ ] }, "cmp al, 1": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0x3C", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "uxtb w27, w4", + "sub w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "cmp ax, 1": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0x3D", "ExpectedArm64ASM": [ - "uxth w20, w4", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "uxth w27, w4", + "sub w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x3D", "ExpectedArm64ASM": [ - "mov w20, w4", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp w20, #0x1 (1)", + "mov w27, w4", + "sub w26, w27, #0x1 (1)", + "cmp w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x3D", "ExpectedArm64ASM": [ - "sub x20, x4, #0x1 (1)", - "strb w4, [x28, #708]", - "strb w20, [x28, #706]", - "cmp x4, #0x1 (1)", + "mov x27, x4", + "sub x26, x27, #0x1 (1)", + "cmp x27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp al, -1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x3C", "ExpectedArm64ASM": [ "uxtb w20, w4", - "sub w21, w20, #0xff (255)", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", + "sub w26, w20, #0xff (255)", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "ubfx x22, x26, #8, #1", + "orr w21, w21, w22, lsl #29", + "bic w20, w26, w20", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "cmp ax, -1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffff", "uxth w21, w4", - "sub w20, w21, w20", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x20, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "sub w26, w21, w20", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x22, x26, #16, #1", + "orr w20, w20, w22, lsl #29", + "bic w21, w26, w21", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov w21, w4", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -2160,14 +2010,12 @@ ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "sub x21, x4, x20", - "eor x22, x4, x20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "sub x26, x4, x20", + "eor x27, x4, x20", "cmp x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -2334,39 +2182,35 @@ ] }, "test al, bl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x84", "ExpectedArm64ASM": [ - "and w20, w4, w7", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, w7", + "cmn wzr, w26, lsl #24" ] }, "test ax, bx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x84", "ExpectedArm64ASM": [ - "and w20, w4, w7", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w4, w7", + "cmn wzr, w26, lsl #16" ] }, "test eax, ebx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x84", "ExpectedArm64ASM": [ - "and w20, w4, w7", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w4, w7", + "tst w26, w26" ] }, "test rax, rbx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x84", "ExpectedArm64ASM": [ - "and x20, x4, x7", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x4, x7", + "tst x26, x26" ] }, "xchg bl, cl": { @@ -2753,7 +2597,7 @@ "strh w20, [x28, #136]", "ubfx w20, w20, #3, #13", "add x0, x28, x20, lsl #2", - "ldr w20, [x0, #880]", + "ldr w20, [x0, #896]", "str w20, [x28, #152]" ] }, @@ -2765,7 +2609,7 @@ "strh w20, [x28, #140]", "ubfx w20, w20, #3, #13", "add x0, x28, x20, lsl #2", - "ldr w20, [x0, #880]", + "ldr w20, [x0, #896]", "str w20, [x28, #160]" ] }, @@ -2777,7 +2621,7 @@ "strh w20, [x28, #142]", "ubfx w20, w20, #3, #13", "add x0, x28, x20, lsl #2", - "ldr w20, [x0, #880]", + "ldr w20, [x0, #896]", "str w20, [x28, #164]" ] }, @@ -2898,13 +2742,11 @@ "ExpectedArm64ASM": [] }, "pushf": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 38, "Comment": "0x9c", "ExpectedArm64ASM": [ "cset w20, hs", - "ldrb w21, [x28, #708]", - "ldrb w22, [x28, #706]", - "eor w21, w21, w22", + "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", "ldrb w21, [x28, #712]", @@ -2931,8 +2773,7 @@ "orr x20, x20, x21, lsl #20", "ldrb w21, [x28, #725]", "orr x20, x20, x21, lsl #21", - "ldrb w21, [x28, #706]", - "fmov s2, w21", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w21, v2.b[0]", "orr x21, x21, #0xfffffffffffffffe", @@ -2945,13 +2786,11 @@ ] }, "pushfq": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 38, "Comment": "0x9c", "ExpectedArm64ASM": [ "cset w20, hs", - "ldrb w21, [x28, #708]", - "ldrb w22, [x28, #706]", - "eor w21, w21, w22", + "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", "ldrb w21, [x28, #712]", @@ -2978,8 +2817,7 @@ "orr x20, x20, x21, lsl #20", "ldrb w21, [x28, #725]", "orr x20, x20, x21, lsl #21", - "ldrb w21, [x28, #706]", - "fmov s2, w21", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w21, v2.b[0]", "orr x21, x21, #0xfffffffffffffffe", @@ -2992,88 +2830,79 @@ ] }, "popf": { - "ExpectedInstructionCount": 39, + "ExpectedInstructionCount": 37, "Comment": "0x9d", "ExpectedArm64ASM": [ "ldr x20, [x8]", "add x8, x8, #0x8 (8)", "mov w21, #0x202", - "orr x20, x20, x21", - "ubfx x21, x20, #0, #1", - "lsl x21, x21, #29", - "ubfx w22, w20, #2, #1", - "eor w22, w22, #0x1", - "strb w22, [x28, #706]", - "strb w20, [x28, #708]", - "ubfx x22, x20, #6, #1", - "orr w21, w21, w22, lsl #30", - "ubfx x22, x20, #7, #1", - "orr w21, w21, w22, lsl #31", - "ubfx w22, w20, #8, #1", - "strb w22, [x28, #712]", - "ubfx w22, w20, #9, #1", - "strb w22, [x28, #713]", - "ubfx w22, w20, #10, #1", - "strb w22, [x28, #714]", - "ubfx x22, x20, #11, #1", - "orr w21, w21, w22, lsl #28", - "ubfx w22, w20, #12, #1", - "strb w22, [x28, #716]", - "ubfx w22, w20, #14, #1", - "strb w22, [x28, #718]", - "ubfx w22, w20, #16, #1", - "strb w22, [x28, #720]", - "ubfx w22, w20, #17, #1", - "strb w22, [x28, #721]", - "ubfx w22, w20, #18, #1", - "strb w22, [x28, #722]", - "ubfx w22, w20, #19, #1", - "strb w22, [x28, #723]", - "ubfx w22, w20, #20, #1", - "strb w22, [x28, #724]", - "ubfx w20, w20, #21, #1", - "strb w20, [x28, #725]", - "msr nzcv, x21" + "orr x27, x20, x21", + "ubfx x20, x27, #0, #1", + "lsl x20, x20, #29", + "ubfx w21, w27, #2, #1", + "eor w26, w21, #0x1", + "ubfx x21, x27, #6, #1", + "orr w20, w20, w21, lsl #30", + "ubfx x21, x27, #7, #1", + "orr w20, w20, w21, lsl #31", + "ubfx w21, w27, #8, #1", + "strb w21, [x28, #712]", + "ubfx w21, w27, #9, #1", + "strb w21, [x28, #713]", + "ubfx w21, w27, #10, #1", + "strb w21, [x28, #714]", + "ubfx x21, x27, #11, #1", + "orr w20, w20, w21, lsl #28", + "ubfx w21, w27, #12, #1", + "strb w21, [x28, #716]", + "ubfx w21, w27, #14, #1", + "strb w21, [x28, #718]", + "ubfx w21, w27, #16, #1", + "strb w21, [x28, #720]", + "ubfx w21, w27, #17, #1", + "strb w21, [x28, #721]", + "ubfx w21, w27, #18, #1", + "strb w21, [x28, #722]", + "ubfx w21, w27, #19, #1", + "strb w21, [x28, #723]", + "ubfx w21, w27, #20, #1", + "strb w21, [x28, #724]", + "ubfx w21, w27, #21, #1", + "strb w21, [x28, #725]", + "msr nzcv, x20" ] }, "sahf": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 16, "Comment": "0x9e", "ExpectedArm64ASM": [ "ubfx w20, w4, #8, #8", "mov w21, #0x28", "bic x20, x20, x21", - "orr x20, x20, #0x2", - "ubfx x21, x20, #0, #1", - "mrs x22, nzcv", - "mov w0, w22", - "bfi w0, w21, #29, #1", - "mov w21, w0", - "ubfx w22, w20, #2, #1", - "eor w22, w22, #0x1", - "strb w22, [x28, #706]", - "strb w20, [x28, #708]", - "ubfx x22, x20, #6, #1", - "bfi w21, w22, #30, #1", - "ubfx x20, x20, #7, #1", + "orr x27, x20, #0x2", + "ubfx x20, x27, #0, #1", + "mrs x21, nzcv", "mov w0, w21", - "bfi w0, w20, #31, #1", + "bfi w0, w20, #29, #1", "mov w20, w0", + "ubfx w21, w27, #2, #1", + "eor w26, w21, #0x1", + "ubfx x21, x27, #6, #1", + "bfi w20, w21, #30, #1", + "ubfx x21, x27, #7, #1", + "bfi w20, w21, #31, #1", "msr nzcv, x20" ] }, "lahf": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 14, "Comment": "0x9f", "ExpectedArm64ASM": [ "cset w20, hs", - "ldrb w21, [x28, #708]", - "ldrb w22, [x28, #706]", - "eor w21, w21, w22", + "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", - "ldrb w21, [x28, #706]", - "fmov s2, w21", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w21, v2.b[0]", "orr x21, x21, #0xfffffffffffffffe", @@ -3339,80 +3168,74 @@ ] }, "cmpsb": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": [ "0xa6" ], "ExpectedArm64ASM": [ "ldrb w20, [x11]", "ldrb w21, [x10]", - "sub w22, w21, w20", - "ldrb w23, [x28, #714]", - "mov w24, #0x1", - "sub x23, x24, x23, lsl #1", - "add x11, x11, x23", - "add x10, x10, x23", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "ldrb w22, [x28, #714]", + "mov w23, #0x1", + "sub x22, x23, x22, lsl #1", + "add x11, x11, x22", + "add x10, x10, x22", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "cmpsw": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": [ "0xa7" ], "ExpectedArm64ASM": [ "ldrh w20, [x11]", "ldrh w21, [x10]", - "sub w22, w21, w20", - "ldrb w23, [x28, #714]", - "mov w24, #0x2", - "sub x23, x24, x23, lsl #2", - "add x11, x11, x23", - "add x10, x10, x23", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "ldrb w22, [x28, #714]", + "mov w23, #0x2", + "sub x22, x23, x22, lsl #2", + "add x11, x11, x22", + "add x10, x10, x22", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "cmpsd": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": [ "0xa7" ], "ExpectedArm64ASM": [ "ldr w20, [x11]", "ldr w21, [x10]", - "sub w22, w21, w20", - "ldrb w23, [x28, #714]", - "mov w24, #0x4", - "sub x23, x24, x23, lsl #3", - "add x11, x11, x23", - "add x10, x10, x23", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "ldrb w22, [x28, #714]", + "mov w23, #0x4", + "sub x22, x23, x22, lsl #3", + "add x11, x11, x22", + "add x10, x10, x22", + "eor w27, w21, w20", "cmp w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -3420,22 +3243,20 @@ ] }, "cmpsq": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": [ "0xa7" ], "ExpectedArm64ASM": [ "ldr x20, [x11]", "ldr x21, [x10]", - "sub x22, x21, x20", - "ldrb w23, [x28, #714]", - "mov w24, #0x8", - "sub x23, x24, x23, lsl #4", - "add x11, x11, x23", - "add x10, x10, x23", - "eor x23, x21, x20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub x26, x21, x20", + "ldrb w22, [x28, #714]", + "mov w23, #0x8", + "sub x22, x23, x22, lsl #4", + "add x11, x11, x22", + "add x10, x10, x22", + "eor x27, x21, x20", "cmp x21, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -3443,81 +3264,75 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0xa6", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x1", "sub x20, x21, x20, lsl #1", - "cbz x5, #+0x58", + "cbz x5, #+0x50", "ldrb w21, [x11]", "ldrb w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #24", - "mrs x24, nzcv", - "ubfx x25, x23, #8, #1", - "orr w24, w24, w25, lsl #29", + "sub w26, w22, w21", + "eor w27, w22, w21", + "cmn wzr, w26, lsl #24", + "mrs x23, nzcv", + "ubfx x24, x26, #8, #1", + "orr w23, w23, w24, lsl #29", "eor w21, w22, w21", - "eor w22, w23, w22", + "eor w22, w26, w22", "and w21, w22, w21", "ubfx x21, x21, #7, #1", - "orr w21, w24, w21, lsl #28", + "orr w21, w23, w21, lsl #28", "msr nzcv, x21", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x54" + "cbnz w21, #-0x4c" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x2", "sub x20, x21, x20, lsl #2", - "cbz x5, #+0x58", + "cbz x5, #+0x50", "ldrh w21, [x11]", "ldrh w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #16", - "mrs x24, nzcv", - "ubfx x25, x23, #16, #1", - "orr w24, w24, w25, lsl #29", + "sub w26, w22, w21", + "eor w27, w22, w21", + "cmn wzr, w26, lsl #16", + "mrs x23, nzcv", + "ubfx x24, x26, #16, #1", + "orr w23, w23, w24, lsl #29", "eor w21, w22, w21", - "eor w22, w23, w22", + "eor w22, w26, w22", "and w21, w22, w21", "ubfx x21, x21, #15, #1", - "orr w21, w24, w21, lsl #28", + "orr w21, w23, w21, lsl #28", "msr nzcv, x21", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x54" + "cbnz w21, #-0x4c" ] }, "repz cmpsd": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x40", + "cbz x5, #+0x38", "ldr w21, [x11]", "ldr w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub w26, w22, w21", + "eor w27, w22, w21", "cmp w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -3526,23 +3341,21 @@ "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x3c" + "cbnz w21, #-0x34" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x40", + "cbz x5, #+0x38", "ldr x21, [x11]", "ldr x22, [x10]", - "sub x23, x22, x21", - "eor x24, x22, x21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub x26, x22, x21", + "eor x27, x22, x21", "cmp x22, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -3551,85 +3364,79 @@ "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbnz w21, #-0x3c" + "cbnz w21, #-0x34" ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0xa6", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x1", "sub x20, x21, x20, lsl #1", - "cbz x5, #+0x58", + "cbz x5, #+0x50", "ldrb w21, [x11]", "ldrb w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #24", - "mrs x24, nzcv", - "ubfx x25, x23, #8, #1", - "orr w24, w24, w25, lsl #29", + "sub w26, w22, w21", + "eor w27, w22, w21", + "cmn wzr, w26, lsl #24", + "mrs x23, nzcv", + "ubfx x24, x26, #8, #1", + "orr w23, w23, w24, lsl #29", "eor w21, w22, w21", - "eor w22, w23, w22", + "eor w22, w26, w22", "and w21, w22, w21", "ubfx x21, x21, #7, #1", - "orr w21, w24, w21, lsl #28", + "orr w21, w23, w21, lsl #28", "msr nzcv, x21", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x54" + "cbz w21, #-0x4c" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x2", "sub x20, x21, x20, lsl #2", - "cbz x5, #+0x58", + "cbz x5, #+0x50", "ldrh w21, [x11]", "ldrh w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #16", - "mrs x24, nzcv", - "ubfx x25, x23, #16, #1", - "orr w24, w24, w25, lsl #29", + "sub w26, w22, w21", + "eor w27, w22, w21", + "cmn wzr, w26, lsl #16", + "mrs x23, nzcv", + "ubfx x24, x26, #16, #1", + "orr w23, w23, w24, lsl #29", "eor w21, w22, w21", - "eor w22, w23, w22", + "eor w22, w26, w22", "and w21, w22, w21", "ubfx x21, x21, #15, #1", - "orr w21, w24, w21, lsl #28", + "orr w21, w23, w21, lsl #28", "msr nzcv, x21", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x54" + "cbz w21, #-0x4c" ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x40", + "cbz x5, #+0x38", "ldr w21, [x11]", "ldr w22, [x10]", - "sub w23, w22, w21", - "eor w24, w22, w21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub w26, w22, w21", + "eor w27, w22, w21", "cmp w22, w21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -3638,23 +3445,21 @@ "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x3c" + "cbz w21, #-0x34" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "0xa7", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x40", + "cbz x5, #+0x38", "ldr x21, [x11]", "ldr x22, [x10]", - "sub x23, x22, x21", - "eor x24, x22, x21", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub x26, x22, x21", + "eor x27, x22, x21", "cmp x22, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -3663,81 +3468,73 @@ "add x11, x11, x20", "add x10, x10, x20", "cset w21, eq", - "cbz w21, #-0x3c" + "cbz w21, #-0x34" ] }, "test al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa8", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, #0x1", + "cmn wzr, w26, lsl #24" ] }, "test ax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w4, #0x1", + "cmn wzr, w26, lsl #16" ] }, "test eax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w4, #0x1", + "tst w26, w26" ] }, "test rax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "and x20, x4, #0x1", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x4, #0x1", + "tst x26, x26" ] }, "test al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa8", "ExpectedArm64ASM": [ - "and w20, w4, #0xff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w4, #0xff", + "cmn wzr, w26, lsl #24" ] }, "test ax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "and w20, w4, #0xffff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w4, #0xffff", + "cmn wzr, w26, lsl #16" ] }, "test eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0xa9", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "and w20, w4, w20", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w4, w20", + "tst w26, w26" ] }, "test rax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0xa9", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "and x20, x4, x20", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x4, x20", + "tst x26, x26" ] }, "stosb": { @@ -3987,71 +3784,65 @@ ] }, "scasb": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0xae", "ExpectedArm64ASM": [ "uxtb w20, w4", "ldrb w21, [x11]", - "sub w22, w20, w21", - "ldrb w23, [x28, #714]", - "mov w24, #0x1", - "sub x23, x24, x23, lsl #1", - "add x11, x11, x23", - "eor w23, w20, w21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w20, w21", + "ldrb w22, [x28, #714]", + "mov w23, #0x1", + "sub x22, x23, x22, lsl #1", + "add x11, x11, x22", + "eor w27, w20, w21", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w21, w20, w21", - "eor w20, w22, w20", + "eor w20, w26, w20", "and w20, w20, w21", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "scasw": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0xaf", "ExpectedArm64ASM": [ "uxth w20, w4", "ldrh w21, [x11]", - "sub w22, w20, w21", - "ldrb w23, [x28, #714]", - "mov w24, #0x2", - "sub x23, x24, x23, lsl #2", - "add x11, x11, x23", - "eor w23, w20, w21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w20, w21", + "ldrb w22, [x28, #714]", + "mov w23, #0x2", + "sub x22, x23, x22, lsl #2", + "add x11, x11, x22", + "eor w27, w20, w21", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w21, w20, w21", - "eor w20, w22, w20", + "eor w20, w26, w20", "and w20, w20, w21", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "scasd": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "0xaf", "ExpectedArm64ASM": [ "mov w20, w4", "ldr w21, [x11]", - "sub w22, w20, w21", - "ldrb w23, [x28, #714]", - "mov w24, #0x4", - "sub x23, x24, x23, lsl #3", - "add x11, x11, x23", - "eor w23, w20, w21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w20, w21", + "ldrb w22, [x28, #714]", + "mov w23, #0x4", + "sub x22, x23, x22, lsl #3", + "add x11, x11, x22", + "eor w27, w20, w21", "cmp w20, w21", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -4059,18 +3850,16 @@ ] }, "scasq": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldr x20, [x11]", - "sub x21, x4, x20", - "ldrb w22, [x28, #714]", - "mov w23, #0x8", - "sub x22, x23, x22, lsl #4", - "add x11, x11, x22", - "eor x22, x4, x20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "sub x26, x4, x20", + "ldrb w21, [x28, #714]", + "mov w22, #0x8", + "sub x21, x22, x21, lsl #4", + "add x11, x11, x21", + "eor x27, x4, x20", "cmp x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -4078,79 +3867,73 @@ ] }, "repz scasb": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x1", "sub x20, x21, x20, lsl #1", - "cbz x5, #+0x54", + "cbz x5, #+0x4c", "uxtb w21, w4", "ldrb w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #24", - "mrs x24, nzcv", - "ubfx x25, x23, #8, #1", - "orr w24, w24, w25, lsl #29", + "sub w26, w21, w22", + "eor w27, w21, w22", + "cmn wzr, w26, lsl #24", + "mrs x23, nzcv", + "ubfx x24, x26, #8, #1", + "orr w23, w23, w24, lsl #29", "eor w22, w21, w22", - "eor w21, w23, w21", + "eor w21, w26, w21", "and w21, w21, w22", "ubfx x21, x21, #7, #1", - "orr w21, w24, w21, lsl #28", + "orr w21, w23, w21, lsl #28", "msr nzcv, x21", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbnz w21, #-0x50" + "cbnz w21, #-0x48" ] }, "repz scasw": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x2", "sub x20, x21, x20, lsl #2", - "cbz x5, #+0x54", + "cbz x5, #+0x4c", "uxth w21, w4", "ldrh w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #16", - "mrs x24, nzcv", - "ubfx x25, x23, #16, #1", - "orr w24, w24, w25, lsl #29", + "sub w26, w21, w22", + "eor w27, w21, w22", + "cmn wzr, w26, lsl #16", + "mrs x23, nzcv", + "ubfx x24, x26, #16, #1", + "orr w23, w23, w24, lsl #29", "eor w22, w21, w22", - "eor w21, w23, w21", + "eor w21, w26, w21", "and w21, w21, w22", "ubfx x21, x21, #15, #1", - "orr w21, w24, w21, lsl #28", + "orr w21, w23, w21, lsl #28", "msr nzcv, x21", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbnz w21, #-0x50" + "cbnz w21, #-0x48" ] }, "repz scasd": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x3c", + "cbz x5, #+0x34", "mov w21, w4", "ldr w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub w26, w21, w22", + "eor w27, w21, w22", "cmp w21, w22", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -4158,22 +3941,20 @@ "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbnz w21, #-0x38" + "cbnz w21, #-0x30" ] }, "repz scasq": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x38", + "cbz x5, #+0x30", "ldr x21, [x11]", - "sub x22, x4, x21", - "eor x23, x4, x21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub x26, x4, x21", + "eor x27, x4, x21", "cmp x4, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -4181,83 +3962,77 @@ "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbnz w21, #-0x34" + "cbnz w21, #-0x2c" ] }, "repnz scasb": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x1", "sub x20, x21, x20, lsl #1", - "cbz x5, #+0x54", + "cbz x5, #+0x4c", "uxtb w21, w4", "ldrb w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #24", - "mrs x24, nzcv", - "ubfx x25, x23, #8, #1", - "orr w24, w24, w25, lsl #29", + "sub w26, w21, w22", + "eor w27, w21, w22", + "cmn wzr, w26, lsl #24", + "mrs x23, nzcv", + "ubfx x24, x26, #8, #1", + "orr w23, w23, w24, lsl #29", "eor w22, w21, w22", - "eor w21, w23, w21", + "eor w21, w26, w21", "and w21, w21, w22", "ubfx x21, x21, #7, #1", - "orr w21, w24, w21, lsl #28", + "orr w21, w23, w21, lsl #28", "msr nzcv, x21", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbz w21, #-0x50" + "cbz w21, #-0x48" ] }, "repnz scasw": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 22, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x2", "sub x20, x21, x20, lsl #2", - "cbz x5, #+0x54", + "cbz x5, #+0x4c", "uxth w21, w4", "ldrh w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", - "cmn wzr, w23, lsl #16", - "mrs x24, nzcv", - "ubfx x25, x23, #16, #1", - "orr w24, w24, w25, lsl #29", + "sub w26, w21, w22", + "eor w27, w21, w22", + "cmn wzr, w26, lsl #16", + "mrs x23, nzcv", + "ubfx x24, x26, #16, #1", + "orr w23, w23, w24, lsl #29", "eor w22, w21, w22", - "eor w21, w23, w21", + "eor w21, w26, w21", "and w21, w21, w22", "ubfx x21, x21, #15, #1", - "orr w21, w24, w21, lsl #28", + "orr w21, w23, w21, lsl #28", "msr nzcv, x21", "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbz w21, #-0x50" + "cbz w21, #-0x48" ] }, "repnz scasd": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x4", "sub x20, x21, x20, lsl #3", - "cbz x5, #+0x3c", + "cbz x5, #+0x34", "mov w21, w4", "ldr w22, [x11]", - "sub w23, w21, w22", - "eor w24, w21, w22", - "strb w24, [x28, #708]", - "strb w23, [x28, #706]", + "sub w26, w21, w22", + "eor w27, w21, w22", "cmp w21, w22", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -4265,22 +4040,20 @@ "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbz w21, #-0x38" + "cbz w21, #-0x30" ] }, "repnz scasq": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrb w20, [x28, #714]", "mov w21, #0x8", "sub x20, x21, x20, lsl #4", - "cbz x5, #+0x38", + "cbz x5, #+0x30", "ldr x21, [x11]", - "sub x22, x4, x21", - "eor x23, x4, x21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub x26, x4, x21", + "eor x27, x4, x21", "cmp x4, x21", "mrs x21, nzcv", "eor w21, w21, #0x20000000", @@ -4288,7 +4061,7 @@ "sub x5, x5, #0x1 (1)", "add x11, x11, x20", "cset w21, eq", - "cbz w21, #-0x34" + "cbz w21, #-0x2c" ] }, "mov al, 0xff": { diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index b09b7c68d..16fd16b0d 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -15,179 +15,163 @@ ], "Instructions": { "add al, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "uxtb w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "or al, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ - "orr w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "adc al, 1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxtb w22, w4", - "add w20, w22, w20", + "uxtb w27, w4", + "add w20, w27, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0x1 (1)", - "cset x24, lo", - "cmp w20, #0x1 (1)", - "cset x25, ls", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0x1 (1)", + "cset x22, lo", + "cmp w26, #0x1 (1)", + "cset x23, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sbb al, 1": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 20, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w20, w20, w21", - "uxtb w22, w4", - "sub w20, w22, w20", + "uxtb w27, w4", + "sub w20, w27, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxtb w26, w20", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w27", + "cset x22, hi", + "cmp w26, w27", + "cset x23, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", + "csel x21, x23, x22, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", + "msr nzcv, x20" + ] + }, + "and al, 1": { + "ExpectedInstructionCount": 3, + "Comment": "GROUP1 0x80 /4", + "ExpectedArm64ASM": [ + "and w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" + ] + }, + "sub al, 1": { + "ExpectedInstructionCount": 11, + "Comment": "GROUP1 0x80 /5", + "ExpectedArm64ASM": [ + "uxtb w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", + "msr nzcv, x20" + ] + }, + "xor al, 1": { + "ExpectedInstructionCount": 3, + "Comment": "GROUP1 0x80 /6", + "ExpectedArm64ASM": [ + "eor w26, w4, #0x1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" + ] + }, + "cmp al, 1": { + "ExpectedInstructionCount": 10, + "Comment": "GROUP1 0x80 /7", + "ExpectedArm64ASM": [ + "uxtb w27, w4", + "sub w26, w27, #0x1 (1)", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", + "msr nzcv, x20" + ] + }, + "add al, -1": { + "ExpectedInstructionCount": 12, + "Comment": "GROUP1 0x80 /0", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "add w26, w20, #0xff (255)", + "bfxil x4, x26, #0, #8", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "ubfx x22, x26, #8, #1", + "orr w21, w21, w22, lsl #29", + "bic w20, w20, w26", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, - "and al, 1": { - "ExpectedInstructionCount": 4, - "Comment": "GROUP1 0x80 /4", - "ExpectedArm64ASM": [ - "and w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" - ] - }, - "sub al, 1": { - "ExpectedInstructionCount": 13, - "Comment": "GROUP1 0x80 /5", - "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", - "msr nzcv, x20" - ] - }, - "xor al, 1": { - "ExpectedInstructionCount": 4, - "Comment": "GROUP1 0x80 /6", - "ExpectedArm64ASM": [ - "eor w20, w4, #0x1", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" - ] - }, - "cmp al, 1": { - "ExpectedInstructionCount": 12, - "Comment": "GROUP1 0x80 /7", - "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", - "msr nzcv, x20" - ] - }, - "add al, -1": { - "ExpectedInstructionCount": 14, - "Comment": "GROUP1 0x80 /0", - "ExpectedArm64ASM": [ - "uxtb w20, w4", - "add w21, w20, #0xff (255)", - "bfxil x4, x21, #0, #8", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w20, w21", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", - "msr nzcv, x20" - ] - }, "or al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ - "orr w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "orr w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "adc al, -1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -196,27 +180,25 @@ "uxtb w22, w4", "add w20, w22, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, #0xff (255)", - "cset x24, lo", - "cmp w20, #0xff (255)", - "cset x25, ls", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, #0xff (255)", + "cset x23, lo", + "cmp w26, #0xff (255)", + "cset x24, ls", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w22, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w22, w26", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sbb al, -1": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -225,123 +207,111 @@ "uxtb w22, w4", "sub w20, w22, w20", "bfxil x4, x20, #0, #8", - "uxtb w20, w20", - "eor w23, w22, #0xff", - "strb w23, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x23, nzcv", - "cmp w20, w22", - "cset x24, hi", - "cmp w20, w22", - "cset x25, hs", + "uxtb w26, w20", + "eor w27, w22, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "cmp w26, w22", + "cset x23, hi", + "cmp w26, w22", + "cset x24, hs", "cmp x21, #0x1 (1)", - "csel x21, x25, x24, eq", - "orr w21, w23, w21, lsl #29", - "bic w20, w20, w22", + "csel x21, x24, x23, eq", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w22", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", + "msr nzcv, x20" + ] + }, + "and al, -1": { + "ExpectedInstructionCount": 3, + "Comment": "GROUP1 0x80 /4", + "ExpectedArm64ASM": [ + "and w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" + ] + }, + "sub al, -1": { + "ExpectedInstructionCount": 12, + "Comment": "GROUP1 0x80 /5", + "ExpectedArm64ASM": [ + "uxtb w20, w4", + "sub w26, w20, #0xff (255)", + "bfxil x4, x26, #0, #8", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "ubfx x22, x26, #8, #1", + "orr w21, w21, w22, lsl #29", + "bic w20, w26, w20", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, - "and al, -1": { - "ExpectedInstructionCount": 4, - "Comment": "GROUP1 0x80 /4", - "ExpectedArm64ASM": [ - "and w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" - ] - }, - "sub al, -1": { - "ExpectedInstructionCount": 14, - "Comment": "GROUP1 0x80 /5", - "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0xff (255)", - "bfxil x4, x21, #0, #8", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", - "msr nzcv, x20" - ] - }, "xor al, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ - "eor w20, w4, #0xff", - "bfxil x4, x20, #0, #8", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "eor w26, w4, #0xff", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24" ] }, "cmp al, -1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "uxtb w20, w4", - "sub w21, w20, #0xff (255)", - "eor w22, w20, #0xff", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", + "sub w26, w20, #0xff (255)", + "eor w27, w20, #0xff", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "ubfx x22, x26, #8, #1", + "orr w21, w21, w22, lsl #29", + "bic w20, w26, w20", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "add ax, 256": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "uxth w20, w4", - "add w21, w20, #0x100 (256)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "uxth w27, w4", + "add w26, w27, #0x100 (256)", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "add eax, 256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "mov x20, x4", - "add w4, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn w20, #0x100 (256)" + "mov x27, x4", + "add w4, w27, #0x100 (256)", + "mov x26, x4", + "cmn w27, #0x100 (256)" ] }, "add rax, 256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn x20, #0x100 (256)" + "mov x27, x4", + "add x4, x27, #0x100 (256)", + "mov x26, x4", + "cmn x27, #0x100 (256)" ] }, "or eax, 256": { @@ -349,7 +319,7 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr w4, w4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -358,73 +328,69 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr x4, x4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "adc eax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "add w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs wzr, w22, w20" + "mov w27, w4", + "add w4, w27, w21", + "mov x26, x4", + "adcs wzr, w27, w20" ] }, "adc rax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "add x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs xzr, x22, x20" + "mov x27, x4", + "add x4, x27, x21", + "mov x26, x4", + "adcs xzr, x27, x20" ] }, "sbb eax, 256": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "sub w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov w27, w4", + "sub w4, w27, w21", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "sbb rax, 256": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "sub x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov x27, x4", + "sub x4, x27, x21", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -435,7 +401,7 @@ "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "and w4, w4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -444,33 +410,31 @@ "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "and x4, x4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "sub eax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub w4, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp w20, #0x100 (256)", + "mov x27, x4", + "sub w4, w27, #0x100 (256)", + "mov x26, x4", + "cmp w27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "sub rax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x4, x20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp x20, #0x100 (256)", + "mov x27, x4", + "sub x4, x27, #0x100 (256)", + "mov x26, x4", + "cmp x27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -481,7 +445,7 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor w4, w4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -490,79 +454,72 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor x4, x4, #0x100", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp eax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ - "mov w20, w4", - "sub w21, w20, #0x100 (256)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp w20, #0x100 (256)", + "mov w27, w4", + "sub w26, w27, #0x100 (256)", + "cmp w27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rax, 256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ - "sub x20, x4, #0x100 (256)", - "strb w4, [x28, #708]", - "strb w20, [x28, #706]", - "cmp x4, #0x100 (256)", + "mov x27, x4", + "sub x26, x27, #0x100 (256)", + "cmp x27, #0x100 (256)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "add ax, -256": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xff00", - "uxth w21, w4", - "add w20, w21, w20", - "bfxil x4, x20, #0, #16", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x20, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "uxth w27, w4", + "add w26, w27, w20", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w27, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "add eax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x21, x4", - "add w4, w21, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", - "cmn w21, w20" + "mov x27, x4", + "add w4, w27, w20", + "mov x26, x4", + "cmn w27, w20" ] }, "add rax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "mov x21, x4", - "sub x4, x21, #0x100 (256)", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", - "cmn x21, x20" + "mov x27, x4", + "sub x4, x27, #0x100 (256)", + "mov x26, x4", + "cmn x27, x20" ] }, "or eax, -256": { @@ -570,7 +527,7 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr w4, w4, #0xffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -579,73 +536,69 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr x4, x4, #0xffffffffffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "adc eax, -256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "add w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs wzr, w22, w20" + "mov w27, w4", + "add w4, w27, w21", + "mov x26, x4", + "adcs wzr, w27, w20" ] }, "adc rax, -256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "add x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs xzr, x22, x20" + "mov x27, x4", + "add x4, x27, x21", + "mov x26, x4", + "adcs xzr, x27, x20" ] }, "sbb eax, -256": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "sub w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov w27, w4", + "sub w4, w27, w21", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "sbb rax, -256": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "sub x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov x27, x4", + "sub x4, x27, x21", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -656,7 +609,7 @@ "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "and w4, w4, #0xffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -665,35 +618,33 @@ "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "and x4, x4, #0xffffffffffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "sub eax, -256": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov x21, x4", - "sub w4, w21, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", - "cmp w21, w20", + "mov x27, x4", + "sub w4, w27, w20", + "mov x26, x4", + "cmp w27, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "sub rax, -256": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "mov x21, x4", - "sub x4, x21, x20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", - "cmp x21, x20", + "mov x27, x4", + "sub x4, x27, x20", + "mov x26, x4", + "cmp x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -704,7 +655,7 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor w4, w4, #0xffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -713,78 +664,71 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor x4, x4, #0xffffffffffffff00", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp eax, -256": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mov w21, w4", - "sub w22, w21, w20", - "strb w21, [x28, #708]", - "strb w22, [x28, #706]", - "cmp w21, w20", + "mov w27, w4", + "sub w26, w27, w20", + "cmp w27, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rax, -256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "sub x21, x4, x20", - "strb w4, [x28, #708]", - "strb w21, [x28, #706]", - "cmp x4, x20", + "mov x27, x4", + "sub x26, x27, x20", + "cmp x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "add ax, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ - "uxth w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "uxth w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "bic w21, w26, w27", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "add eax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ - "mov x20, x4", - "add w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn w20, #0x1 (1)" + "mov x27, x4", + "add w4, w27, #0x1 (1)", + "mov x26, x4", + "cmn w27, #0x1 (1)" ] }, "add rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmn x20, #0x1 (1)" + "mov x27, x4", + "add x4, x27, #0x1 (1)", + "mov x26, x4", + "cmn x27, #0x1 (1)" ] }, "or eax, 1": { @@ -792,7 +736,7 @@ "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "orr w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -801,73 +745,69 @@ "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "orr x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "adc eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "add w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs wzr, w22, w20" + "mov w27, w4", + "add w4, w27, w21", + "mov x26, x4", + "adcs wzr, w27, w20" ] }, "adc rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "add x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", - "adcs xzr, x22, x20" + "mov x27, x4", + "add x4, x27, x21", + "mov x26, x4", + "adcs xzr, x27, x20" ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add w21, w20, w21", - "mov w22, w4", - "sub w4, w22, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov w27, w4", + "sub w4, w27, w21", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs wzr, w22, w20", + "sbcs wzr, w27, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", "cset w21, hs", "add x21, x20, x21", - "mov x22, x4", - "sub x4, x22, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "mov x27, x4", + "sub x4, x27, x21", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", - "sbcs xzr, x22, x20", + "sbcs xzr, x27, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -878,7 +818,7 @@ "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "and w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -887,33 +827,31 @@ "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "and x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp w20, #0x1 (1)", + "mov x27, x4", + "sub w4, w27, #0x1 (1)", + "mov x26, x4", + "cmp w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cmp x20, #0x1 (1)", + "mov x27, x4", + "sub x4, x27, #0x1 (1)", + "mov x26, x4", + "cmp x27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -924,7 +862,7 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "eor w4, w4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -933,81 +871,74 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "eor x4, x4, #0x1", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ - "mov w20, w4", - "sub w21, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmp w20, #0x1 (1)", + "mov w27, w4", + "sub w26, w27, #0x1 (1)", + "cmp w27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ - "sub x20, x4, #0x1 (1)", - "strb w4, [x28, #708]", - "strb w20, [x28, #706]", - "cmp x4, #0x1 (1)", + "mov x27, x4", + "sub x26, x27, #0x1 (1)", + "cmp x27, #0x1 (1)", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "add ax, -1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffff", "uxth w21, w4", - "add w20, w21, w20", - "bfxil x4, x20, #0, #16", - "eor w22, w21, #0xffff", - "strb w22, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x20, #16, #1", - "orr w22, w22, w23, lsl #29", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "add w26, w21, w20", + "bfxil x4, x26, #0, #16", + "eor w27, w21, #0xffff", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x22, x26, #16, #1", + "orr w20, w20, w22, lsl #29", + "bic w21, w21, w26", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "add eax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov x21, x4", "add w4, w21, w20", - "eor w22, w21, w20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w21, w20", + "mov x26, x4", "cmn w21, w20" ] }, "add rax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, #0x1 (1)", - "eor x22, x21, x20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x21, x20", + "mov x26, x4", "cmn x21, x20" ] }, @@ -1017,7 +948,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "orr w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1027,12 +958,12 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "orr x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "adc eax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", @@ -1040,14 +971,13 @@ "add w21, w20, w21", "mov w22, w4", "add w4, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x4", "adcs wzr, w22, w20" ] }, "adc rax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", @@ -1055,14 +985,13 @@ "add x21, x20, x21", "mov x22, x4", "add x4, x22, x21", - "eor x21, x22, x20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x22, x20", + "mov x26, x4", "adcs xzr, x22, x20" ] }, "sbb eax, -1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", @@ -1070,9 +999,8 @@ "add w21, w20, w21", "mov w22, w4", "sub w4, w22, w21", - "eor w21, w22, w20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w22, w20", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -1083,7 +1011,7 @@ ] }, "sbb rax, -1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", @@ -1091,9 +1019,8 @@ "add x21, x20, x21", "mov x22, x4", "sub x4, x22, x21", - "eor x21, x22, x20", - "strb w21, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x22, x20", + "mov x26, x4", "mrs x21, nzcv", "eor w21, w21, #0x20000000", "msr nzcv, x21", @@ -1109,7 +1036,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "and w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1119,20 +1046,19 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "and x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov x21, x4", "sub w4, w21, w20", - "eor w22, w21, w20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w21, w20", + "mov x26, x4", "cmp w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1140,15 +1066,14 @@ ] }, "sub rax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mov x21, x4", "sub x4, x21, x20", - "eor x22, x21, x20", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x21, x20", + "mov x26, x4", "cmp x21, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1161,7 +1086,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "eor w4, w4, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -1171,20 +1096,18 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "eor x4, x4, x20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mov w21, w4", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1192,14 +1115,12 @@ ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "sub x21, x4, x20", - "eor x22, x4, x20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "sub x26, x4, x20", + "eor x27, x4, x20", "cmp x4, x20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -1305,50 +1226,47 @@ ] }, "shl al, 2": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC0 /4", "ExpectedArm64ASM": [ "uxtb w20, w4", - "lsl w21, w20, #2", - "bfxil x4, x21, #0, #8", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", + "lsl w26, w20, #2", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", "ubfx x20, x20, #6, #1", - "orr w20, w22, w20, lsl #29", - "strb w21, [x28, #706]", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, "shr al, 2": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xC0 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", - "lsr w21, w20, #2", - "bfxil x4, x21, #0, #8", - "cset w22, vs", - "cmn wzr, w21, lsl #24", - "mrs x23, nzcv", + "lsr w26, w20, #2", + "bfxil x4, x26, #0, #8", + "cset w21, vs", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", "ubfx x20, x20, #1, #1", - "orr w20, w23, w20, lsl #29", - "strb w21, [x28, #706]", - "orr w20, w20, w22, lsl #28", + "orr w20, w22, w20, lsl #29", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sar al, 2": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC0 /7", "ExpectedArm64ASM": [ "uxtb w20, w4", "sxtb x20, w20", - "asr x21, x20, #2", - "bfxil x4, x21, #0, #8", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", + "asr x26, x20, #2", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", "ubfx x20, x20, #1, #1", - "orr w20, w22, w20, lsl #29", - "strb w21, [x28, #706]", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, @@ -1549,17 +1467,16 @@ ] }, "shl ax, 2": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /4", "ExpectedArm64ASM": [ "uxth w20, w4", - "lsl w21, w20, #2", - "bfxil x4, x21, #0, #16", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", + "lsl w26, w20, #2", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", "ubfx x20, x20, #14, #1", - "orr w20, w22, w20, lsl #29", - "strb w21, [x28, #706]", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, @@ -1573,7 +1490,7 @@ "mrs x21, nzcv", "ubfx x20, x20, #30, #1", "orr w20, w21, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -1587,24 +1504,23 @@ "mrs x21, nzcv", "ubfx x20, x20, #62, #1", "orr w20, w21, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, "shr ax, 2": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "uxth w20, w4", - "lsr w21, w20, #2", - "bfxil x4, x21, #0, #16", - "cset w22, vs", - "cmn wzr, w21, lsl #16", - "mrs x23, nzcv", + "lsr w26, w20, #2", + "bfxil x4, x26, #0, #16", + "cset w21, vs", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", "ubfx x20, x20, #1, #1", - "orr w20, w23, w20, lsl #29", - "strb w21, [x28, #706]", - "orr w20, w20, w22, lsl #28", + "orr w20, w22, w20, lsl #29", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, @@ -1619,7 +1535,7 @@ "mrs x22, nzcv", "ubfx x20, x20, #1, #1", "orr w20, w22, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] @@ -1635,24 +1551,23 @@ "mrs x22, nzcv", "ubfx x20, x20, #1, #1", "orr w20, w22, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "sar ax, 2": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /7", "ExpectedArm64ASM": [ "uxth w20, w4", "sxth x20, w20", - "asr x21, x20, #2", - "bfxil x4, x21, #0, #16", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", + "asr x26, x20, #2", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", "ubfx x20, x20, #1, #1", - "orr w20, w22, w20, lsl #29", - "strb w21, [x28, #706]", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, @@ -1666,7 +1581,7 @@ "mrs x21, nzcv", "ubfx x20, x20, #1, #1", "orr w20, w21, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -1680,7 +1595,7 @@ "mrs x21, nzcv", "ubfx x20, x20, #1, #1", "orr w20, w21, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -1767,54 +1682,51 @@ ] }, "shl al, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd0 /4", "ExpectedArm64ASM": [ "uxtb w20, w4", "lsl w21, w20, #1", "bfxil x4, x21, #0, #8", - "uxtb w21, w21", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x20, #7, #1", - "orr w22, w22, w23, lsl #29", - "strb w21, [x28, #706]", - "eor w20, w21, w20", + "uxtb w26, w21", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "ubfx x22, x20, #7, #1", + "orr w21, w21, w22, lsl #29", + "eor w20, w26, w20", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "shr al, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd0 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", - "lsr w21, w20, #1", - "bfxil x4, x21, #0, #8", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x20, #0, #1", - "orr w22, w22, w23, lsl #29", - "strb w21, [x28, #706]", + "lsr w26, w20, #1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "ubfx x22, x20, #0, #1", + "orr w21, w21, w22, lsl #29", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "sar al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd0 /7", "ExpectedArm64ASM": [ "uxtb w20, w4", "sxtb x20, w20", - "asr w21, w20, #1", - "bfxil x4, x21, #0, #8", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", + "asr w26, w20, #1", + "bfxil x4, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", "ubfx x20, x20, #0, #1", - "orr w20, w22, w20, lsl #29", - "strb w21, [x28, #706]", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, @@ -2039,21 +1951,20 @@ ] }, "shl ax, 1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ "uxth w20, w4", "lsl w21, w20, #1", "bfxil x4, x21, #0, #16", - "uxth w21, w21", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x20, #15, #1", - "orr w22, w22, w23, lsl #29", - "strb w21, [x28, #706]", - "eor w20, w21, w20", + "uxth w26, w21", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", + "ubfx x22, x20, #15, #1", + "orr w21, w21, w22, lsl #29", + "eor w20, w26, w20", "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, @@ -2067,7 +1978,7 @@ "mrs x21, nzcv", "ubfx x22, x20, #31, #1", "orr w21, w21, w22, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "eor w20, w4, w20", "ubfx x20, x20, #31, #1", "orr w20, w21, w20, lsl #28", @@ -2084,7 +1995,7 @@ "mrs x21, nzcv", "lsr x22, x20, #63", "orr w21, w21, w22, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "eor x20, x4, x20", "lsr x20, x20, #63", "orr w20, w21, w20, lsl #28", @@ -2092,19 +2003,18 @@ ] }, "shr ax, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd1 /5", "ExpectedArm64ASM": [ "uxth w20, w4", - "lsr w21, w20, #1", - "bfxil x4, x21, #0, #16", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x20, #0, #1", - "orr w22, w22, w23, lsl #29", - "strb w21, [x28, #706]", + "lsr w26, w20, #1", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", + "ubfx x22, x20, #0, #1", + "orr w21, w21, w22, lsl #29", "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, @@ -2118,7 +2028,7 @@ "mrs x21, nzcv", "ubfx x22, x20, #0, #1", "orr w21, w21, w22, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "ubfx x20, x20, #31, #1", "orr w20, w21, w20, lsl #28", "msr nzcv, x20" @@ -2134,25 +2044,24 @@ "mrs x21, nzcv", "ubfx x22, x20, #0, #1", "orr w21, w21, w22, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "lsr x20, x20, #63", "orr w20, w21, w20, lsl #28", "msr nzcv, x20" ] }, "sar ax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd1 /7", "ExpectedArm64ASM": [ "uxth w20, w4", "sxth x20, w20", - "asr w21, w20, #1", - "bfxil x4, x21, #0, #16", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", + "asr w26, w20, #1", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", "ubfx x20, x20, #0, #1", - "orr w20, w22, w20, lsl #29", - "strb w21, [x28, #706]", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, @@ -2166,7 +2075,7 @@ "mrs x21, nzcv", "ubfx x20, x20, #0, #1", "orr w20, w21, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -2180,7 +2089,7 @@ "mrs x21, nzcv", "ubfx x20, x20, #0, #1", "orr w20, w21, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -2324,7 +2233,7 @@ "lsr w21, w20, w21", "ubfx x21, x21, #0, #1", "orr w21, w23, w21, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", @@ -2346,7 +2255,7 @@ "lsr w21, w20, w21", "ubfx x21, x21, #0, #1", "orr w21, w23, w21, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "ubfx x20, x20, #7, #1", "orr w20, w21, w20, lsl #28", @@ -2369,7 +2278,7 @@ "lsr x20, x20, x21", "ubfx x20, x20, #0, #1", "orr w20, w23, w20, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "msr nzcv, x20" ] }, @@ -2553,7 +2462,7 @@ "sub w24, w24, w20", "lsr w24, w22, w24", "mov w25, #0x0", - "mrs x26, nzcv", + "mrs x30, nzcv", "cmp w20, #0x1 (1)", "csel w24, w24, w25, hi", "orr w23, w23, w24", @@ -2561,7 +2470,7 @@ "sub w24, w24, w20", "lsr w22, w22, w24", "ubfx x24, x22, #0, #1", - "mov w0, w26", + "mov w0, w30", "bfi w0, w24, #29, #1", "mov w24, w0", "sub w20, w20, #0x1 (1)", @@ -2651,14 +2560,14 @@ "mov w25, #0x21", "sub w25, w25, w21", "lsl w25, w22, w25", - "mrs x26, nzcv", + "mrs x30, nzcv", "cmp w21, #0x1 (1)", "csel w24, w25, w24, hi", "orr w23, w23, w24", "sub w24, w21, #0x1 (1)", "lsr w22, w22, w24", "ubfx x22, x22, #0, #1", - "mov w0, w26", + "mov w0, w30", "bfi w0, w22, #29, #1", "mov w22, w0", "mov w24, #0x20", @@ -2724,7 +2633,7 @@ "lsr w21, w20, w21", "ubfx x21, x21, #0, #1", "orr w21, w23, w21, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "ubfx x20, x20, #15, #1", "orr w20, w21, w20, lsl #28", @@ -2747,7 +2656,7 @@ "lsr w21, w20, w21", "ubfx x21, x21, #0, #1", "orr w21, w23, w21, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "ubfx x20, x20, #31, #1", "orr w20, w21, w20, lsl #28", @@ -2770,7 +2679,7 @@ "lsr x21, x20, x21", "ubfx x21, x21, #0, #1", "orr w21, w23, w21, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "eor x20, x20, x22", "lsr x20, x20, #63", "orr w20, w21, w20, lsl #28", @@ -2792,7 +2701,7 @@ "lsr w21, w20, w21", "ubfx x21, x21, #0, #1", "orr w21, w23, w21, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "ubfx x20, x20, #15, #1", "orr w20, w21, w20, lsl #28", @@ -2814,7 +2723,7 @@ "lsr w21, w20, w21", "ubfx x21, x21, #0, #1", "orr w21, w23, w21, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "eor w20, w20, w22", "ubfx x20, x20, #31, #1", "orr w20, w21, w20, lsl #28", @@ -2836,7 +2745,7 @@ "lsr x21, x20, x21", "ubfx x21, x21, #0, #1", "orr w21, w23, w21, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "eor x20, x20, x22", "lsr x20, x20, #63", "orr w20, w21, w20, lsl #28", @@ -2859,7 +2768,7 @@ "lsr x20, x20, x21", "ubfx x20, x20, #0, #1", "orr w20, w23, w20, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "msr nzcv, x20" ] }, @@ -2878,7 +2787,7 @@ "lsr w20, w20, w21", "ubfx x20, x20, #0, #1", "orr w20, w23, w20, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "msr nzcv, x20" ] }, @@ -2897,17 +2806,16 @@ "lsr x20, x20, x21", "ubfx x20, x20, #0, #1", "orr w20, w23, w20, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "msr nzcv, x20" ] }, "test bl, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf6 /0", "ExpectedArm64ASM": [ - "and w20, w7, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24" + "and w26, w7, #0x1", + "cmn wzr, w26, lsl #24" ] }, "not bl": { @@ -2925,21 +2833,19 @@ ] }, "neg bl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ - "uxtb w20, w7", - "neg w21, w20", - "bfxil x7, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #24", - "mrs x22, nzcv", - "ubfx x23, x21, #8, #1", - "orr w22, w22, w23, lsl #29", - "and w20, w21, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "uxtb w27, w7", + "neg w26, w27", + "bfxil x7, x26, #0, #8", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", + "and w21, w26, w27", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, @@ -3007,59 +2913,53 @@ ] }, "test bx, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "and w20, w7, #0x1", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w7, #0x1", + "cmn wzr, w26, lsl #16" ] }, "test ebx, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "and w20, w7, #0x1", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w7, #0x1", + "tst w26, w26" ] }, "test rbx, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "and x20, x7, #0x1", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x7, #0x1", + "tst x26, x26" ] }, "test bx, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "and w20, w7, #0xffff", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16" + "and w26, w7, #0xffff", + "cmn wzr, w26, lsl #16" ] }, "test ebx, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "and w20, w7, w20", - "strb w20, [x28, #706]", - "tst w20, w20" + "and w26, w7, w20", + "tst w26, w26" ] }, "test rbx, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", - "and x20, x7, x20", - "strb w20, [x28, #706]", - "tst x20, x20" + "and x26, x7, x20", + "tst x26, x26" ] }, "not bx": { @@ -3084,47 +2984,43 @@ ] }, "neg bx": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "uxth w20, w7", - "neg w21, w20", - "bfxil x7, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cmn wzr, w21, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #16, #1", - "orr w22, w22, w23, lsl #29", - "and w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "uxth w27, w7", + "neg w26, w27", + "bfxil x7, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", + "and w21, w26, w27", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "neg ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "mov w20, w7", - "neg w7, w20", - "strb w20, [x28, #708]", - "strb w7, [x28, #706]", - "cmp wzr, w20", + "mov w27, w7", + "neg w7, w27", + "mov x26, x7", + "cmp wzr, w27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "neg rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ - "mov x20, x7", - "neg x7, x20", - "strb w20, [x28, #708]", - "strb w7, [x28, #706]", - "cmp xzr, x20", + "mov x27, x7", + "neg x7, x27", + "mov x26, x7", + "cmp xzr, x27", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" @@ -3255,7 +3151,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #2208]", + "ldr x3, [x28, #2224]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3266,7 +3162,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #2224]", + "ldr x3, [x28, #2240]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3327,7 +3223,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #2216]", + "ldr x3, [x28, #2232]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3340,7 +3236,7 @@ "mov x0, x6", "mov x1, x20", "mov x2, x7", - "ldr x3, [x28, #2232]", + "ldr x3, [x28, #2248]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -3351,138 +3247,134 @@ ] }, "inc al": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP3 0xfe /0", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #24", - "mrs x23, nzcv", - "bic w20, w21, w20", - "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", - "orr w20, w20, w22, lsl #29", + "uxtb w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cset w20, hs", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "bic w22, w26, w27", + "ubfx x22, x22, #7, #1", + "orr w21, w21, w22, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, "dec al": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP3 0xfe /1", "ExpectedArm64ASM": [ - "uxtb w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #8", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #24", - "mrs x23, nzcv", - "bic w20, w20, w21", - "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", - "orr w20, w20, w22, lsl #29", + "uxtb w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #8", + "cset w20, hs", + "cmn wzr, w26, lsl #24", + "mrs x21, nzcv", + "bic w22, w27, w26", + "ubfx x22, x22, #7, #1", + "orr w21, w21, w22, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, "inc ax": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "uxth w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #16", - "mrs x23, nzcv", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", - "orr w20, w20, w22, lsl #29", + "uxth w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #16", + "cset w20, hs", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", + "bic w22, w26, w27", + "ubfx x22, x22, #15, #1", + "orr w21, w21, w22, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, "inc eax": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "mov w20, w4", - "add w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cset w21, hs", - "cmn w20, #0x1 (1)", - "mrs x20, nzcv", - "bfi w20, w21, #29, #1", + "mov w27, w4", + "add w4, w27, #0x1 (1)", + "mov x26, x4", + "cset w20, hs", + "cmn w27, #0x1 (1)", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "inc rax": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "mov x20, x4", - "add x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cset w21, hs", - "cmn x20, #0x1 (1)", - "mrs x20, nzcv", - "bfi w20, w21, #29, #1", + "mov x27, x4", + "add x4, x27, #0x1 (1)", + "mov x26, x4", + "cset w20, hs", + "cmn x27, #0x1 (1)", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "dec ax": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "uxth w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil x4, x21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #16", - "mrs x23, nzcv", - "bic w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", - "orr w20, w20, w22, lsl #29", + "uxth w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil x4, x26, #0, #16", + "cset w20, hs", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", + "bic w22, w27, w26", + "ubfx x22, x22, #15, #1", + "orr w21, w21, w22, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, "dec eax": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "mov w20, w4", - "sub w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cset w21, hs", - "cmp w20, #0x1 (1)", - "mrs x20, nzcv", - "bfi w20, w21, #29, #1", + "mov w27, w4", + "sub w4, w27, #0x1 (1)", + "mov x26, x4", + "cset w20, hs", + "cmp w27, #0x1 (1)", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "dec rax": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "mov x20, x4", - "sub x4, x20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cset w21, hs", - "cmp x20, #0x1 (1)", - "mrs x20, nzcv", - "bfi w20, w21, #29, #1", + "mov x27, x4", + "sub x4, x27, #0x1 (1)", + "mov x26, x4", + "cset w20, hs", + "cmp x27, #0x1 (1)", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index 243a36482..6f07b271d 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -27,7 +27,7 @@ "strh w20, [x28, #136]", "ubfx w20, w20, #3, #13", "add x0, x28, x20, lsl #2", - "ldr w20, [x0, #880]", + "ldr w20, [x0, #896]", "str w20, [x28, #152]" ] }, @@ -56,7 +56,7 @@ "strh w20, [x28, #140]", "ubfx w20, w20, #3, #13", "add x0, x28, x20, lsl #2", - "ldr w20, [x0, #880]", + "ldr w20, [x0, #896]", "str w20, [x28, #160]" ] }, @@ -77,18 +77,16 @@ "strh w20, [x28, #142]", "ubfx w20, w20, #3, #13", "add x0, x28, x20, lsl #2", - "ldr w20, [x0, #880]", + "ldr w20, [x0, #896]", "str w20, [x28, #164]" ] }, "daa": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 56, "Comment": "0x27", "ExpectedArm64ASM": [ "cset w20, hs", - "ldrb w21, [x28, #708]", - "ldrb w22, [x28, #706]", - "eor w21, w21, w22", + "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "uxtb w22, w4", "mrs x23, nzcv", @@ -100,10 +98,9 @@ "cset x23, hi", "orr x21, x21, x23", "msr nzcv, x24", - "cbnz x21, #+0x10", - "mov w21, #0x0", - "strb w21, [x28, #708]", - "b #+0x30", + "cbnz x21, #+0xc", + "mov w27, #0x0", + "b #+0x2c", "add x21, x22, #0x6 (6)", "bfxil w4, w21, #0, #8", "cset w21, hs", @@ -112,8 +109,7 @@ "mov w0, w23", "bfi w0, w21, #29, #1", "mov w21, w0", - "mov w23, #0x10", - "strb w23, [x28, #708]", + "mov w27, #0x10", "msr nzcv, x21", "mrs x21, nzcv", "cmp x22, #0x99 (153)", @@ -131,33 +127,28 @@ "mrs x20, nzcv", "orr w20, w20, #0x20000000", "msr nzcv, x20", - "uxtb w20, w4", - "and x21, x20, #0x80", - "mrs x22, nzcv", + "uxtb w26, w4", + "and x20, x26, #0x80", + "mrs x21, nzcv", + "cmp x20, #0x0 (0)", + "cset x20, hs", + "mov w0, w21", + "bfi w0, w20, #31, #1", + "mov w20, w0", + "and x21, x26, #0xff", "cmp x21, #0x0 (0)", - "cset x21, hs", - "mov w0, w22", - "bfi w0, w21, #31, #1", - "mov w21, w0", - "and x22, x20, #0xff", - "cmp x22, #0x0 (0)", - "cset x22, eq", - "bfi w21, w22, #30, #1", - "strb w20, [x28, #706]", - "ldrb w22, [x28, #708]", - "eor w20, w22, w20", - "strb w20, [x28, #708]", - "msr nzcv, x21" + "cset x21, eq", + "bfi w20, w21, #30, #1", + "eor w27, w27, w26", + "msr nzcv, x20" ] }, "das": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 56, "Comment": "0x2f", "ExpectedArm64ASM": [ "cset w20, hs", - "ldrb w21, [x28, #708]", - "ldrb w22, [x28, #706]", - "eor w21, w21, w22", + "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "uxtb w22, w4", "mrs x23, nzcv", @@ -169,10 +160,9 @@ "cset x23, hi", "orr x21, x21, x23", "msr nzcv, x24", - "cbnz x21, #+0x10", - "mov w21, #0x0", - "strb w21, [x28, #708]", - "b #+0x30", + "cbnz x21, #+0xc", + "mov w27, #0x0", + "b #+0x2c", "sub x21, x22, #0x6 (6)", "bfxil w4, w21, #0, #8", "cset w21, hs", @@ -181,8 +171,7 @@ "mov w0, w23", "bfi w0, w21, #29, #1", "mov w21, w0", - "mov w23, #0x10", - "strb w23, [x28, #708]", + "mov w27, #0x10", "msr nzcv, x21", "mrs x21, nzcv", "cmp x22, #0x99 (153)", @@ -200,32 +189,27 @@ "mrs x20, nzcv", "orr w20, w20, #0x20000000", "msr nzcv, x20", - "uxtb w20, w4", - "and x21, x20, #0x80", - "mrs x22, nzcv", + "uxtb w26, w4", + "and x20, x26, #0x80", + "mrs x21, nzcv", + "cmp x20, #0x0 (0)", + "cset x20, hs", + "mov w0, w21", + "bfi w0, w20, #31, #1", + "mov w20, w0", + "and x21, x26, #0xff", "cmp x21, #0x0 (0)", - "cset x21, hs", - "mov w0, w22", - "bfi w0, w21, #31, #1", - "mov w21, w0", - "and x22, x20, #0xff", - "cmp x22, #0x0 (0)", - "cset x22, eq", - "bfi w21, w22, #30, #1", - "strb w20, [x28, #706]", - "ldrb w22, [x28, #708]", - "eor w20, w22, w20", - "strb w20, [x28, #708]", - "msr nzcv, x21" + "cset x21, eq", + "bfi w20, w21, #30, #1", + "eor w27, w27, w26", + "msr nzcv, x20" ] }, "aaa": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 24, "Comment": "0x37", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #708]", - "ldrb w21, [x28, #706]", - "eor w20, w20, w21", + "eor w20, w27, w26", "ubfx w20, w20, #4, #1", "uxtb w21, w4", "uxth w22, w4", @@ -235,31 +219,27 @@ "cset x21, hi", "orr x20, x20, x21", "msr nzcv, x23", - "cbnz x20, #+0x20", + "cbnz x20, #+0x1c", "mov w20, #0xff0f", "and x20, x22, x20", "bfxil w4, w20, #0, #16", - "mov w20, #0x0", - "strb w20, [x28, #708]", - "msr nzcv, x20", - "b #+0x24", + "mov w27, #0x0", + "msr nzcv, x27", + "b #+0x20", "add x20, x22, #0x106 (262)", "mov w21, #0xff0f", "and x20, x20, x21", "bfxil w4, w20, #0, #16", "mov w20, #0x20000000", - "mov w21, #0x10", - "strb w21, [x28, #708]", + "mov w27, #0x10", "msr nzcv, x20" ] }, "aas": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 25, "Comment": "0x3f", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #708]", - "ldrb w21, [x28, #706]", - "eor w20, w20, w21", + "eor w20, w27, w26", "ubfx w20, w20, #4, #1", "uxtb w21, w4", "uxth w22, w4", @@ -269,75 +249,70 @@ "cset x21, hi", "orr x20, x20, x21", "msr nzcv, x23", - "cbnz x20, #+0x20", + "cbnz x20, #+0x1c", "mov w20, #0xff0f", "and x20, x22, x20", "bfxil w4, w20, #0, #16", - "mov w20, #0x0", - "strb w20, [x28, #708]", - "msr nzcv, x20", - "b #+0x28", + "mov w27, #0x0", + "msr nzcv, x27", + "b #+0x24", "sub x20, x22, #0x6 (6)", "sub x20, x20, #0x100 (256)", "mov w21, #0xff0f", "and x20, x20, x21", "bfxil w4, w20, #0, #16", "mov w20, #0x20000000", - "mov w21, #0x10", - "strb w21, [x28, #708]", + "mov w27, #0x10", "msr nzcv, x20" ] }, "inc ax": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x40", "ExpectedArm64ASM": [ - "uxth w20, w4", - "add w21, w20, #0x1 (1)", - "bfxil w4, w21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #16", - "mrs x23, nzcv", - "bic w20, w21, w20", - "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", - "orr w20, w20, w22, lsl #29", + "uxth w27, w4", + "add w26, w27, #0x1 (1)", + "bfxil w4, w26, #0, #16", + "cset w20, hs", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", + "bic w22, w26, w27", + "ubfx x22, x22, #15, #1", + "orr w21, w21, w22, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, "inc eax": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x40", "ExpectedArm64ASM": [ - "mov w20, w4", - "add w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cset w21, hs", - "cmn w20, #0x1 (1)", - "mrs x20, nzcv", - "bfi w20, w21, #29, #1", + "mov w27, w4", + "add w4, w27, #0x1 (1)", + "mov w26, w4", + "cset w20, hs", + "cmn w27, #0x1 (1)", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "dec ax": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0x48", "ExpectedArm64ASM": [ - "uxth w20, w4", - "sub w21, w20, #0x1 (1)", - "bfxil w4, w21, #0, #16", - "strb w20, [x28, #708]", - "strb w21, [x28, #706]", - "cset w22, hs", - "cmn wzr, w21, lsl #16", - "mrs x23, nzcv", - "bic w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", - "orr w20, w20, w22, lsl #29", + "uxth w27, w4", + "sub w26, w27, #0x1 (1)", + "bfxil w4, w26, #0, #16", + "cset w20, hs", + "cmn wzr, w26, lsl #16", + "mrs x21, nzcv", + "bic w22, w27, w26", + "ubfx x22, x22, #15, #1", + "orr w21, w21, w22, lsl #28", + "orr w20, w21, w20, lsl #29", "msr nzcv, x20" ] }, @@ -356,17 +331,18 @@ ] }, "dec eax": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x48", "ExpectedArm64ASM": [ - "mov w20, w4", - "sub w4, w20, #0x1 (1)", - "strb w20, [x28, #708]", - "strb w4, [x28, #706]", - "cset w21, hs", - "cmp w20, #0x1 (1)", - "mrs x20, nzcv", - "bfi w20, w21, #29, #1", + "mov w27, w4", + "sub w4, w27, #0x1 (1)", + "mov w26, w4", + "cset w20, hs", + "cmp w27, #0x1 (1)", + "mrs x21, nzcv", + "mov w0, w21", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, @@ -443,7 +419,7 @@ ] }, "aam": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0xd4", "ExpectedArm64ASM": [ "uxtb w20, w4", @@ -454,13 +430,12 @@ "lsl x21, x22, #8", "add x20, x21, x20", "bfxil w4, w20, #0, #16", - "uxtb w20, w4", - "cmn wzr, w20, lsl #24", - "strb w20, [x28, #706]" + "uxtb w26, w4", + "cmn wzr, w26, lsl #24" ] }, "aad": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0xd5", "ExpectedArm64ASM": [ "uxtb w20, w4", @@ -471,13 +446,12 @@ "add x20, x20, x21", "and x20, x20, #0xff", "bfxil w4, w20, #0, #16", - "uxtb w20, w4", - "cmn wzr, w20, lsl #24", - "strb w20, [x28, #706]" + "uxtb w26, w4", + "cmn wzr, w26, lsl #24" ] }, "db 0xd4, 0x40": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "aam with a different immediate byte base", "0xd4" @@ -491,13 +465,12 @@ "lsl x21, x22, #8", "add x20, x21, x20", "bfxil w4, w20, #0, #16", - "uxtb w20, w4", - "cmn wzr, w20, lsl #24", - "strb w20, [x28, #706]" + "uxtb w26, w4", + "cmn wzr, w26, lsl #24" ] }, "db 0xd5, 0x40": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": [ "aad with a different immediate byte base", "0xd5" @@ -510,9 +483,8 @@ "add x20, x20, x21", "and x20, x20, #0xff", "bfxil w4, w20, #0, #16", - "uxtb w20, w4", - "cmn wzr, w20, lsl #24", - "strb w20, [x28, #706]" + "uxtb w26, w4", + "cmn wzr, w26, lsl #24" ] }, "salc": { diff --git a/unittests/InstructionCountCI/RPRES/DDD.json b/unittests/InstructionCountCI/RPRES/DDD.json index edccdc66e..7992e959d 100644 --- a/unittests/InstructionCountCI/RPRES/DDD.json +++ b/unittests/InstructionCountCI/RPRES/DDD.json @@ -16,9 +16,9 @@ "0x0f 0x0f 0x86" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "frecpe v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfrsqrtv mm0, mm1": { @@ -27,9 +27,9 @@ "0x0f 0x0f 0x87" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "frsqrte v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfrcp mm0, mm1": { @@ -38,10 +38,10 @@ "0x0f 0x0f 0x96" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "frecpe s2, s2", "dup v2.2s, v2.s[0]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pfrsqrt mm0, mm1": { @@ -50,10 +50,10 @@ "0x0f 0x0f 0x97" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "frsqrte s2, s2", "dup v2.2s, v2.s[0]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] } } diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 32fb3de20..cd5b4cbd1 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -23,7 +23,7 @@ "Comment": "0x0f 0x0b", "ExpectedArm64ASM": [ "mov w20, #0x0", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "movups xmm0, xmm0": { @@ -156,7 +156,7 @@ "0x0f 0x2a" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "scvtf v0.2s, v2.2s", "mov v16.d[0], v0.d[0]" ] @@ -174,7 +174,7 @@ "ExpectedArm64ASM": [ "ldr d2, [x4]", "fcvtzs v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "cvttps2pi mm0, xmm0": { @@ -182,7 +182,7 @@ "Comment": "0x0f 0x2c", "ExpectedArm64ASM": [ "fcvtzs v2.2s, v16.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "cvtps2pi mm0, [rax]": { @@ -192,7 +192,7 @@ "ldr d2, [x4]", "frinti v2.2s, v2.2s", "fcvtzs v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "cvtps2pi mm0, xmm0": { @@ -201,11 +201,11 @@ "ExpectedArm64ASM": [ "frinti v2.2s, v16.2s", "fcvtzs v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "ucomiss xmm0, xmm1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0x0f 0x2e", "ExpectedArm64ASM": [ "mrs x20, nzcv", @@ -221,17 +221,15 @@ "ubfx x21, x21, #2, #1", "bfi w20, w22, #29, #1", "bfi w20, w23, #30, #1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "mov w21, #0x0", - "mov w22, #0x90000000", - "bic x20, x20, x22", - "strb w21, [x28, #708]", + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w21, #0x90000000", + "bic x20, x20, x21", "msr nzcv, x20" ] }, "comiss xmm0, xmm1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0x0f 0x2f", "ExpectedArm64ASM": [ "mrs x20, nzcv", @@ -247,12 +245,10 @@ "ubfx x21, x21, #2, #1", "bfi w20, w22, #29, #1", "bfi w20, w23, #30, #1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "mov w21, #0x0", - "mov w22, #0x90000000", - "bic x20, x20, x22", - "strb w21, [x28, #708]", + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w21, #0x90000000", + "bic x20, x20, x21", "msr nzcv, x20" ] }, @@ -492,11 +488,10 @@ ] }, "cmovpe ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0x4a", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -507,11 +502,10 @@ ] }, "cmovpe eax, ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0x4a", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -521,11 +515,10 @@ ] }, "cmovpe rax, rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0x4a", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -535,11 +528,10 @@ ] }, "cmovnp ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0x4b", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -550,11 +542,10 @@ ] }, "cmovnp eax, ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0x4b", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -564,11 +555,10 @@ ] }, "cmovnp rax, rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0x4b", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -670,7 +660,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #2048]", + "ldr q3, [x28, #2064]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -681,7 +671,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #2048]", + "ldr q3, [x28, #2064]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -813,193 +803,193 @@ "ExpectedInstructionCount": 4, "Comment": "0x0f 0x60", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "zip1 v2.8b, v2.8b, v3.8b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpcklbw mm0, [rax]": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x60", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ldr d3, [x4]", "zip1 v2.8b, v2.8b, v3.8b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpcklwd mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x61", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "zip1 v2.4h, v2.4h, v3.4h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpcklwd mm0, [rax]": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x61", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ldr d3, [x4]", "zip1 v2.4h, v2.4h, v3.4h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpckldq mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x62", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "zip1 v2.2s, v2.2s, v3.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpckldq mm0, [rax]": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x62", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ldr d3, [x4]", "zip1 v2.2s, v2.2s, v3.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "packsswb mm0, mm1": { "ExpectedInstructionCount": 5, "Comment": "0x0f 0x63", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "zip1 v2.2d, v2.2d, v3.2d", "sqxtn v2.8b, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "packsswb mm0, [rax]": { "ExpectedInstructionCount": 5, "Comment": "0x0f 0x63", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ldr d3, [x4]", "zip1 v2.2d, v2.2d, v3.2d", "sqxtn v2.8b, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "packsswb mm0, mm0": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x63", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "zip1 v2.2d, v2.2d, v2.2d", "sqxtn v2.8b, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pcmpgtb mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x64", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "cmgt v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pcmpgtw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x65", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "cmgt v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pcmpgtd mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x66", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "cmgt v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpckhbw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x68", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "zip2 v2.8b, v2.8b, v3.8b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpckhbw mm0, [rax]": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x68", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ldr d3, [x4]", "zip2 v2.8b, v2.8b, v3.8b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpckhwd mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x69", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "zip2 v2.4h, v2.4h, v3.4h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpckhwd mm0, [rax]": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x69", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ldr d3, [x4]", "zip2 v2.4h, v2.4h, v3.4h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpckhdq mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x6a", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "zip2 v2.2s, v2.2s, v3.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "punpckhdq mm0, [rax]": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x6a", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ldr d3, [x4]", "zip2 v2.2s, v2.2s, v3.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "packssdw mm0, mm1": { "ExpectedInstructionCount": 5, "Comment": "0x0f 0x6b", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "zip1 v2.2d, v2.2d, v3.2d", "sqxtn v2.4h, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "movd mm0, eax": { @@ -1007,7 +997,7 @@ "Comment": "0x0f 0x6e", "ExpectedArm64ASM": [ "fmov s2, w4", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "movd mm0, [rax]": { @@ -1015,23 +1005,23 @@ "Comment": "0x0f 0x6e", "ExpectedArm64ASM": [ "ldr s2, [x4]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "movq mm0, mm0": { "ExpectedInstructionCount": 2, "Comment": "0x0f 0x6f", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "str d2, [x28, #752]" + "ldr d2, [x28, #768]", + "str d2, [x28, #768]" ] }, "movq mm0, mm1": { "ExpectedInstructionCount": 2, "Comment": "0x0f 0x6f", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "str d2, [x28, #752]" + "ldr d2, [x28, #784]", + "str d2, [x28, #768]" ] }, "movq mm0, [rax]": { @@ -1039,16 +1029,16 @@ "Comment": "0x0f 0x6f", "ExpectedArm64ASM": [ "ldr d2, [x4]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pshufw mm0, mm1, 0": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "dup v2.4h, v2.h[0]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pshufw mm0, [rax], 0": { @@ -1057,18 +1047,18 @@ "ExpectedArm64ASM": [ "ldr d2, [x4]", "dup v2.4h, v2.h[0]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pshufw mm0, mm1, 1": { "ExpectedInstructionCount": 5, "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr x0, [x28, #1656]", + "ldr d2, [x28, #784]", + "ldr x0, [x28, #1672]", "ldr d3, [x0, #16]", "tbl v2.8b, {v2.16b}, v3.8b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pshufw mm0, [rax], 1": { @@ -1076,19 +1066,19 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d2, [x4]", - "ldr x0, [x28, #1656]", + "ldr x0, [x28, #1672]", "ldr d3, [x0, #16]", "tbl v2.8b, {v2.16b}, v3.8b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pshufw mm0, mm1, 0xff": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "dup v2.4h, v2.h[3]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pshufw mm0, [rax], 0xff": { @@ -1097,37 +1087,37 @@ "ExpectedArm64ASM": [ "ldr d2, [x4]", "dup v2.4h, v2.h[3]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pcmpeqb mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x74", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "cmeq v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pcmpeqw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x75", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "cmeq v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pcmpeqd mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0x76", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "cmeq v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "emms": { @@ -1135,14 +1125,14 @@ "Comment": "0x0f 0x77", "ExpectedArm64ASM": [ "mov w20, #0x0", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "movd eax, mm0": { "ExpectedInstructionCount": 2, "Comment": "0x0f 0x7e", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "mov w4, v2.s[0]" ] }, @@ -1150,7 +1140,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0x7e", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "str s2, [x4]" ] }, @@ -1162,15 +1152,15 @@ "0x0f 0x7f" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "str d2, [x28, #768]" + "ldr d2, [x28, #768]", + "str d2, [x28, #784]" ] }, "movq [rax], mm0": { "ExpectedInstructionCount": 2, "Comment": "0x0f 0x7f", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "str d2, [x4]" ] }, @@ -1258,11 +1248,10 @@ ] }, "setpe al": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0x9a", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mvn w20, w20", @@ -1271,11 +1260,10 @@ ] }, "setnp al": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0x9b", "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "and x20, x20, #0x1", @@ -1331,7 +1319,7 @@ "strh w20, [x28, #146]", "ubfx w20, w20, #3, #13", "add x0, x28, x20, lsl #2", - "ldr w20, [x0, #880]", + "ldr w20, [x0, #896]", "str w20, [x28, #176]" ] }, @@ -1417,77 +1405,73 @@ "ExpectedArm64ASM": [] }, "shld ax, bx, 1": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 14, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w4", "lsl x22, x21, #1", "lsr w20, w20, #15", - "orr x20, x22, x20", - "bfxil x4, x20, #0, #16", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", - "ubfx x23, x21, #15, #1", - "orr w22, w22, w23, lsl #29", - "strb w20, [x28, #706]", - "eor w20, w20, w21", - "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "orr x26, x22, x20", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x22, x21, #15, #1", + "orr w20, w20, w22, lsl #29", + "eor w21, w26, w21", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "shld ax, bx, 15": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w4", "lsl x22, x21, #15", "lsr w20, w20, #1", - "orr x20, x22, x20", - "bfxil x4, x20, #0, #16", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", + "orr x26, x22, x20", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", "ubfx x21, x21, #1, #1", - "orr w21, w22, w21, lsl #29", - "strb w20, [x28, #706]", - "msr nzcv, x21" + "orr w20, w20, w21, lsl #29", + "msr nzcv, x20" ] }, "shld ax, bx, 16": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w4", "lsl x22, x21, #16", - "orr x20, x22, x20", - "bfxil x4, x20, #0, #16", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", + "orr x26, x22, x20", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", "ubfx x21, x21, #0, #1", - "orr w21, w22, w21, lsl #29", - "strb w20, [x28, #706]", - "msr nzcv, x21" + "orr w20, w20, w21, lsl #29", + "msr nzcv, x20" ] }, "shld ax, bx, 31": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w4", "lsl x22, x21, #31", "lsr w20, w20, #17", - "orr x20, x22, x20", - "bfxil x4, x20, #0, #16", - "cmn wzr, w20, lsl #16", - "mrs x22, nzcv", + "orr x26, x22, x20", + "bfxil x4, x26, #0, #16", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", "ubfx x21, x21, #1, #1", - "orr w21, w22, w21, lsl #29", - "strb w20, [x28, #706]", - "msr nzcv, x21" + "orr w20, w20, w21, lsl #29", + "msr nzcv, x20" ] }, "shld eax, ebx, 0": { @@ -1508,7 +1492,7 @@ "mrs x20, nzcv", "ubfx x22, x21, #31, #1", "orr w20, w20, w22, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "eor w21, w4, w21", "ubfx x21, x21, #31, #1", "orr w20, w20, w21, lsl #28", @@ -1526,7 +1510,7 @@ "mrs x20, nzcv", "ubfx x21, x21, #17, #1", "orr w20, w20, w21, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -1541,7 +1525,7 @@ "mrs x20, nzcv", "ubfx x21, x21, #16, #1", "orr w20, w20, w21, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -1556,7 +1540,7 @@ "mrs x20, nzcv", "ubfx x21, x21, #1, #1", "orr w20, w20, w21, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -1575,7 +1559,7 @@ "mrs x21, nzcv", "lsr x22, x20, #63", "orr w21, w21, w22, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "eor x20, x4, x20", "lsr x20, x20, #63", "orr w20, w21, w20, lsl #28", @@ -1592,7 +1576,7 @@ "mrs x21, nzcv", "ubfx x20, x20, #49, #1", "orr w20, w21, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -1606,7 +1590,7 @@ "mrs x21, nzcv", "ubfx x20, x20, #32, #1", "orr w20, w21, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -1620,7 +1604,7 @@ "mrs x21, nzcv", "ubfx x20, x20, #1, #1", "orr w20, w21, w20, lsl #29", - "strb w4, [x28, #706]", + "mov x26, x4", "msr nzcv, x20" ] }, @@ -1651,7 +1635,7 @@ "lsr w22, w21, w22", "ubfx x22, x22, #0, #1", "orr w22, w23, w22, lsl #29", - "strb w20, [x28, #706]", + "mov x26, x20", "eor w20, w21, w20", "ubfx x20, x20, #15, #1", "orr w20, w22, w20, lsl #28", @@ -1685,7 +1669,7 @@ "lsr w22, w21, w22", "ubfx x22, x22, #0, #1", "orr w22, w23, w22, lsl #29", - "strb w20, [x28, #706]", + "mov x26, x20", "eor w20, w21, w20", "ubfx x20, x20, #31, #1", "orr w20, w22, w20, lsl #28", @@ -1717,7 +1701,7 @@ "lsr x21, x20, x21", "ubfx x21, x21, #0, #1", "orr w21, w23, w21, lsl #29", - "strb w22, [x28, #706]", + "mov x26, x22", "eor x20, x20, x22", "lsr x20, x20, #63", "orr w20, w21, w20, lsl #28", @@ -1741,7 +1725,7 @@ "strh w20, [x28, #144]", "ubfx w20, w20, #3, #13", "add x0, x28, x20, lsl #2", - "ldr w20, [x0, #880]", + "ldr w20, [x0, #896]", "str w20, [x28, #168]" ] }, @@ -1934,7 +1918,7 @@ ] }, "cmpxchg al, bl": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "0x0f 0xb0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -1946,24 +1930,22 @@ "csel w20, w20, w21, eq", "bfxil x4, x23, #0, #8", "bfxil x4, x20, #0, #8", - "sub x20, x22, x23", + "sub x26, x22, x23", + "eor w27, w22, w23", + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "ubfx x21, x26, #8, #1", + "orr w20, w20, w21, lsl #29", "eor w21, w22, w23", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #24", - "mrs x21, nzcv", - "ubfx x24, x20, #8, #1", - "orr w21, w21, w24, lsl #29", - "eor w23, w22, w23", - "eor w20, w20, w22", - "and w20, w20, w23", - "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "eor w22, w26, w22", + "and w21, w22, w21", + "ubfx x21, x21, #7, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "cmpxchg [rax], bl": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0x0f 0xb0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -1972,24 +1954,22 @@ "casalb w1, w20, [x4]", "mov w20, w1", "bfxil x4, x20, #0, #8", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "cmpxchg ax, bx": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 21, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -2001,24 +1981,22 @@ "csel w20, w20, w21, eq", "bfxil x4, x23, #0, #16", "bfxil x4, x20, #0, #16", - "sub x20, x22, x23", + "sub x26, x22, x23", + "eor w27, w22, w23", + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "ubfx x21, x26, #16, #1", + "orr w20, w20, w21, lsl #29", "eor w21, w22, w23", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", - "cmn wzr, w20, lsl #16", - "mrs x21, nzcv", - "ubfx x24, x20, #16, #1", - "orr w21, w21, w24, lsl #29", - "eor w23, w22, w23", - "eor w20, w20, w22", - "and w20, w20, w23", - "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "eor w22, w26, w22", + "and w21, w22, w21", + "ubfx x21, x21, #15, #1", + "orr w20, w20, w21, lsl #28", "msr nzcv, x20" ] }, "cmpxchg [rax], bx": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -2027,24 +2005,22 @@ "casalh w1, w20, [x4]", "mov w20, w1", "bfxil x4, x20, #0, #16", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "sub w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "and w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "cmpxchg eax, ebx": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", @@ -2058,10 +2034,8 @@ "cmp x24, x23", "csel x4, x21, x22, eq", "mov x4, x20", - "sub x20, x23, x24", - "eor w21, w23, w24", - "strb w21, [x28, #708]", - "strb w20, [x28, #706]", + "sub x26, x23, x24", + "eor w27, w23, w24", "cmp w23, w24", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -2069,7 +2043,7 @@ ] }, "cmpxchg [rax], ebx": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", @@ -2079,10 +2053,8 @@ "mov w20, w1", "cmp w20, w21", "csel x4, x4, x20, eq", - "sub w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub w26, w21, w20", + "eor w27, w21, w20", "cmp w21, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -2090,7 +2062,7 @@ ] }, "cmpxchg rax, rbx": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov x20, x4", @@ -2100,10 +2072,8 @@ "csel x22, x7, x20, eq", "mov x4, x21", "mov x4, x22", - "sub x22, x20, x21", - "eor x23, x20, x21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", + "sub x26, x20, x21", + "eor x27, x20, x21", "cmp x20, x21", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -2111,17 +2081,15 @@ ] }, "cmpxchg [rax], rbx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov x20, x4", "mov x1, x20", "casal x1, x7, [x20]", "mov x4, x1", - "sub x21, x20, x4", - "eor x22, x20, x4", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "sub x26, x20, x4", + "eor x27, x20, x4", "cmp x20, x4", "mrs x20, nzcv", "eor w20, w20, #0x20000000", @@ -2666,150 +2634,136 @@ ] }, "xadd al, bl": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w4", "uxtb w21, w7", - "add w22, w20, w21", + "add w26, w20, w21", "bfxil x7, x20, #0, #8", - "bfxil x4, x22, #0, #8", - "eor w23, w20, w21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "bfxil x4, x26, #0, #8", + "eor w27, w20, w21", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w21, w20, w21", - "eor w20, w22, w20", + "eor w20, w26, w20", "bic w20, w20, w21", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "xadd [rax], bl": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w7", "ldaddalb w20, w21, [x4]", "bfxil x7, x21, #0, #8", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #24", - "mrs x23, nzcv", - "ubfx x24, x22, #8, #1", - "orr w23, w23, w24, lsl #29", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #24", + "mrs x22, nzcv", + "ubfx x23, x26, #8, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "xadd ax, bx": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 16, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w4", "uxth w21, w7", - "add w22, w20, w21", + "add w26, w20, w21", "bfxil x7, x20, #0, #16", - "bfxil x4, x22, #0, #16", - "eor w23, w20, w21", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "bfxil x4, x26, #0, #16", + "eor w27, w20, w21", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w21, w20, w21", - "eor w20, w22, w20", + "eor w20, w26, w20", "bic w20, w20, w21", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "xadd [rax], bx": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 15, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w7", "ldaddalh w20, w21, [x4]", "bfxil x7, x21, #0, #16", - "add w22, w21, w20", - "eor w23, w21, w20", - "strb w23, [x28, #708]", - "strb w22, [x28, #706]", - "cmn wzr, w22, lsl #16", - "mrs x23, nzcv", - "ubfx x24, x22, #16, #1", - "orr w23, w23, w24, lsl #29", + "add w26, w21, w20", + "eor w27, w21, w20", + "cmn wzr, w26, lsl #16", + "mrs x22, nzcv", + "ubfx x23, x26, #16, #1", + "orr w22, w22, w23, lsl #29", "eor w20, w21, w20", - "eor w21, w22, w21", + "eor w21, w26, w21", "bic w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w23, w20, lsl #28", + "orr w20, w22, w20, lsl #28", "msr nzcv, x20" ] }, "xadd eax, ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w4", "mov w21, w7", "add w4, w20, w21", "mov x7, x20", - "eor w22, w20, w21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor w27, w20, w21", + "mov x26, x4", "cmn w20, w21" ] }, "xadd [rax], ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", - "add w21, w7, w20", - "eor w22, w7, w20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add w26, w7, w20", + "eor w27, w7, w20", "cmn w7, w20" ] }, "xadd rax, rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x4", "mov x21, x7", "add x4, x20, x21", "mov x7, x20", - "eor x22, x20, x21", - "strb w22, [x28, #708]", - "strb w4, [x28, #706]", + "eor x27, x20, x21", + "mov x26, x4", "cmn x20, x21" ] }, "xadd [rax], rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov x20, x7", "ldaddal x20, x7, [x4]", - "add x21, x7, x20", - "eor x22, x7, x20", - "strb w22, [x28, #708]", - "strb w21, [x28, #706]", + "add x26, x7, x20", + "eor x27, x7, x20", "cmn x7, x20" ] }, @@ -2896,97 +2850,97 @@ "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "mov v2.h[0], w4", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pinsrw mm0, eax, 1": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "mov v2.h[1], w4", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pinsrw mm0, eax, 2": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "mov v2.h[2], w4", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pinsrw mm0, eax, 3": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "mov v2.h[3], w4", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pinsrw mm0, eax, 4": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "mov v2.h[0], w4", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pinsrw mm0, [rax], 0": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ld1 {v2.h}[0], [x4]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pinsrw mm0, [rax], 1": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ld1 {v2.h}[1], [x4]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pinsrw mm0, [rax], 2": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ld1 {v2.h}[2], [x4]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pinsrw mm0, [rax], 3": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ld1 {v2.h}[3], [x4]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pinsrw mm0, [rax], 4": { "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ld1 {v2.h}[0], [x4]", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pextrw eax, mm0, 0": { "ExpectedInstructionCount": 2, "Comment": "0x0f 0xc5", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "umov w4, v2.h[0]" ] }, @@ -2994,7 +2948,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0xc5", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "umov w4, v2.h[1]" ] }, @@ -3002,7 +2956,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0xc5", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "umov w4, v2.h[2]" ] }, @@ -3010,7 +2964,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0xc5", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "umov w4, v2.h[3]" ] }, @@ -3018,7 +2972,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0xc5", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "umov w4, v2.h[0]" ] }, @@ -3500,7 +3454,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #1680]", + "ldr x0, [x28, #1696]", "ldr q2, [x0, #16]", "tbl v16.16b, {v16.16b, v17.16b}, v2.16b" ] @@ -3509,7 +3463,7 @@ "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #1680]", + "ldr x0, [x28, #1696]", "ldr q2, [x0, #16]", "mov v0.16b, v17.16b", "mov v1.16b, v16.16b", @@ -3521,7 +3475,7 @@ "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #1680]", + "ldr x0, [x28, #1696]", "ldr q3, [x0, #16]", "mov v0.16b, v16.16b", "mov v1.16b, v2.16b", @@ -3556,69 +3510,69 @@ "ExpectedInstructionCount": 8, "Comment": "0x0f 0xd1", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uqshl d0, d3, #57", "ushr d0, d0, #57", "dup v0.8h, v0.h[0]", "neg v0.8h, v0.8h", "ushl v2.8h, v2.8h, v0.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrld mm0, mm1": { "ExpectedInstructionCount": 8, "Comment": "0x0f 0xd2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uqshl d0, d3, #57", "ushr d0, d0, #57", "dup v0.4s, v0.s[0]", "neg v0.4s, v0.4s", "ushl v2.4s, v2.4s, v0.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrlq mm0, mm1": { "ExpectedInstructionCount": 8, "Comment": "0x0f 0xd3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uqshl d0, d3, #57", "ushr d0, d0, #57", "dup v0.2d, v0.d[0]", "neg v0.2d, v0.2d", "ushl v2.2d, v2.2d, v0.2d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "paddq mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xd4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "add v2.2d, v3.2d, v2.2d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pmullw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xd5", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "mul v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pmovmskb eax, mm0": { "ExpectedInstructionCount": 12, "Comment": "0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "mov x20, #0x201", "movk x20, #0x804, lsl #16", "movk x20, #0x2010, lsl #32", @@ -3636,157 +3590,157 @@ "ExpectedInstructionCount": 4, "Comment": "0x0f 0xd8", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "uqsub v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psubusw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xd9", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "uqsub v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pminub mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xda", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "umin v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pand mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xdb", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "and v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "paddusb mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xdc", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "uqadd v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "paddusw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xdd", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "uqadd v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pmaxub mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xde", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "umax v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pandn mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xdf", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "bic v2.16b, v2.16b, v3.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pavgb mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xe0", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "urhadd v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psraw mm0, mm1": { "ExpectedInstructionCount": 8, "Comment": "0x0f 0xe1", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uqshl d0, d3, #57", "ushr d0, d0, #57", "dup v0.8h, v0.h[0]", "neg v0.8h, v0.8h", "sshl v2.8h, v2.8h, v0.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrad mm0, mm1": { "ExpectedInstructionCount": 8, "Comment": "0x0f 0xe2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uqshl d0, d3, #57", "ushr d0, d0, #57", "dup v0.4s, v0.s[0]", "neg v0.4s, v0.4s", "sshl v2.4s, v2.4s, v0.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pavgw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xe3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "urhadd v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pmulhuw mm0, mm1": { "ExpectedInstructionCount": 5, "Comment": "0x0f 0xe4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "umull v2.4s, v2.4h, v3.4h", "shrn v2.4h, v2.4s, #16", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pmulhw mm0, mm1": { "ExpectedInstructionCount": 5, "Comment": "0x0f 0xe5", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "smull v2.4s, v2.4h, v3.4h", "shrn v2.4h, v2.4s, #16", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "movntq [rax], mm0": { "ExpectedInstructionCount": 2, "Comment": "0x0f 0xe7", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "str d2, [x4]" ] }, @@ -3794,160 +3748,160 @@ "ExpectedInstructionCount": 4, "Comment": "0x0f 0xe8", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sqsub v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psubsw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xe9", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sqsub v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pminsw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xea", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "smin v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "por mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xeb", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "orr v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "paddsb mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xec", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sqadd v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "paddsw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xed", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sqadd v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pmaxsw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xee", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "smax v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pxor mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xef", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "eor v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllw mm0, mm1": { "ExpectedInstructionCount": 7, "Comment": "0x0f 0xf1", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uqshl d0, d3, #57", "ushr d0, d0, #57", "dup v0.8h, v0.h[0]", "ushl v2.8h, v2.8h, v0.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pslld mm0, mm1": { "ExpectedInstructionCount": 7, "Comment": "0x0f 0xf2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uqshl d0, d3, #57", "ushr d0, d0, #57", "dup v0.4s, v0.s[0]", "ushl v2.4s, v2.4s, v0.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllq mm0, mm1": { "ExpectedInstructionCount": 7, "Comment": "0x0f 0xf3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uqshl d0, d3, #57", "ushr d0, d0, #57", "dup v0.2d, v0.d[0]", "ushl v2.2d, v2.2d, v0.2d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pmuludq mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xf4", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "umull v2.2d, v2.2s, v3.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pmaddwd mm0, mm1": { "ExpectedInstructionCount": 5, "Comment": "0x0f 0xf5", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "smull v2.4s, v2.4h, v3.4h", "addp v2.4s, v2.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psadbw mm0, mm1": { "ExpectedInstructionCount": 5, "Comment": "0x0f 0xf6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "uabdl v2.8h, v2.8b, v3.8b", "addv h2, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "maskmovq mm0, mm1": { "ExpectedInstructionCount": 6, "Comment": "0x0f 0xf7", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", + "ldr d2, [x28, #784]", "cmlt v2.16b, v2.16b, #0", - "ldr d3, [x28, #752]", + "ldr d3, [x28, #768]", "ldr d4, [x11]", "bsl v2.8b, v3.8b, v4.8b", "str d2, [x11]" @@ -3957,70 +3911,70 @@ "ExpectedInstructionCount": 4, "Comment": "0x0f 0xf8", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sub v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psubw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xf9", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sub v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psubd mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xfa", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sub v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psubq mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xfb", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "sub v2.2d, v3.2d, v2.2d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "paddb mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xfc", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "add v2.16b, v3.16b, v2.16b", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "paddw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xfd", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "add v2.8h, v3.8h, v2.8h", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "paddd mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xfe", "ExpectedArm64ASM": [ - "ldr d2, [x28, #768]", - "ldr d3, [x28, #752]", + "ldr d2, [x28, #784]", + "ldr d3, [x28, #768]", "add v2.4s, v3.4s, v2.4s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] } } diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index 66196b8e0..4871653b5 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -825,7 +825,7 @@ "mov w24, w2", "mov w25, w3", "mov w20, w24", - "mov w26, w25", + "mov w30, w25", "cmp x24, x22", "ccmp x25, x23, #nzcv, eq", "cset x22, eq", @@ -833,7 +833,7 @@ "msr nzcv, x21", "cbnz x22, #+0xc", "mov x4, x20", - "mov x6, x26" + "mov x6, x30" ] }, "cmpxchg16b [rbp]": { @@ -852,7 +852,7 @@ "mov x24, x2", "mov x25, x3", "mov x20, x24", - "mov x26, x25", + "mov x30, x25", "cmp x24, x22", "ccmp x25, x23, #nzcv, eq", "cset x22, eq", @@ -860,11 +860,11 @@ "msr nzcv, x21", "cbnz x22, #+0xc", "mov x4, x20", - "mov x6, x26" + "mov x6, x30" ] }, "rdrand ax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", @@ -872,16 +872,14 @@ "mov x22, x20", "mov x20, x21", "bfxil x4, x22, #0, #16", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdrand eax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", @@ -889,32 +887,28 @@ "mov x22, x20", "mov x20, x21", "mov w4, w22", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdrand rax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", "cset x21, ne", "mov x4, x20", "mov x20, x21", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdseed ax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", @@ -922,16 +916,14 @@ "mov x22, x20", "mov x20, x21", "bfxil x4, x22, #0, #16", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdseed eax": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", @@ -939,26 +931,22 @@ "mov x22, x20", "mov x20, x21", "mov w4, w22", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdseed rax": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", "cset x21, ne", "mov x4, x20", "mov x20, x21", - "mov w21, #0x0", - "mov w22, #0x1", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", + "mov w27, #0x0", + "mov w26, #0x1", "lsl x20, x20, #29", "msr nzcv, x20" ] @@ -974,9 +962,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ushr v2.8h, v2.8h, #15", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrlw mm0, 16": { @@ -984,9 +972,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrlw xmm0, 0": { @@ -1022,9 +1010,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "sshr v2.8h, v2.8h, #15", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psraw mm0, 16": { @@ -1032,9 +1020,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "sshr v2.8h, v2.8h, #15", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psraw xmm0, 0": { @@ -1070,9 +1058,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "shl v2.8h, v2.8h, #15", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllw mm0, 16": { @@ -1080,9 +1068,9 @@ "Type": "MMX", "Comment": "GROUP12 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllw xmm0, 0": { @@ -1118,9 +1106,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ushr v2.4s, v2.4s, #31", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrld mm0, 32": { @@ -1128,9 +1116,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrld xmm0, 0": { @@ -1166,9 +1154,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "sshr v2.4s, v2.4s, #31", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrad mm0, 32": { @@ -1176,9 +1164,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "sshr v2.4s, v2.4s, #31", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrad xmm0, 0": { @@ -1214,9 +1202,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "shl v2.4s, v2.4s, #31", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pslld mm0, 32": { @@ -1224,9 +1212,9 @@ "Type": "MMX", "Comment": "GROUP13 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pslld xmm0, 0": { @@ -1262,9 +1250,9 @@ "Type": "MMX", "Comment": "GROUP14 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "ushr v2.2d, v2.2d, #63", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrlq mm0, 64": { @@ -1272,9 +1260,9 @@ "Type": "MMX", "Comment": "GROUP14 0x0F 0xC7 /2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrlq xmm0, 0": { @@ -1333,9 +1321,9 @@ "Type": "MMX", "Comment": "GROUP14 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "shl v2.2d, v2.2d, #63", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllq mm0, 64": { @@ -1343,9 +1331,9 @@ "Type": "MMX", "Comment": "GROUP14 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "movi v2.2d, #0x0", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllq xmm0, 0": { @@ -1374,7 +1362,7 @@ "ExpectedInstructionCount": 58, "Comment": "GROUP15 0x0F 0xAE /0", "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1008]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -1388,23 +1376,23 @@ "orr x20, x20, x23, lsl #10", "orr x20, x20, x24, lsl #14", "strh w20, [x4, #2]", - "ldrb w20, [x28, #1010]", + "ldrb w20, [x28, #1026]", "strb w20, [x4, #4]", - "ldr q2, [x28, #752]", - "str q2, [x4, #32]", "ldr q2, [x28, #768]", - "str q2, [x4, #48]", + "str q2, [x4, #32]", "ldr q2, [x28, #784]", - "str q2, [x4, #64]", + "str q2, [x4, #48]", "ldr q2, [x28, #800]", - "str q2, [x4, #80]", + "str q2, [x4, #64]", "ldr q2, [x28, #816]", - "str q2, [x4, #96]", + "str q2, [x4, #80]", "ldr q2, [x28, #832]", - "str q2, [x4, #112]", + "str q2, [x4, #96]", "ldr q2, [x28, #848]", - "str q2, [x4, #128]", + "str q2, [x4, #112]", "ldr q2, [x28, #864]", + "str q2, [x4, #128]", + "ldr q2, [x28, #880]", "str q2, [x4, #144]", "str q16, [x4, #160]", "str q17, [x4, #176]", @@ -1453,7 +1441,7 @@ "Comment": "GROUP15 0x0F 0xAE /1", "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "ldrh w20, [x4, #2]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -1466,23 +1454,23 @@ "strb w23, [x28, #746]", "strb w20, [x28, #750]", "ldrb w20, [x4, #4]", - "strb w20, [x28, #1010]", + "strb w20, [x28, #1026]", "ldr q2, [x4, #32]", - "str q2, [x28, #752]", - "ldr q2, [x4, #48]", "str q2, [x28, #768]", - "ldr q2, [x4, #64]", + "ldr q2, [x4, #48]", "str q2, [x28, #784]", - "ldr q2, [x4, #80]", + "ldr q2, [x4, #64]", "str q2, [x28, #800]", - "ldr q2, [x4, #96]", + "ldr q2, [x4, #80]", "str q2, [x28, #816]", - "ldr q2, [x4, #112]", + "ldr q2, [x4, #96]", "str q2, [x28, #832]", - "ldr q2, [x4, #128]", + "ldr q2, [x4, #112]", "str q2, [x28, #848]", - "ldr q2, [x4, #144]", + "ldr q2, [x4, #128]", "str q2, [x28, #864]", + "ldr q2, [x4, #144]", + "str q2, [x28, #880]", "ldr q16, [x4, #160]", "ldr q17, [x4, #176]", "ldr q18, [x4, #192]", @@ -1591,7 +1579,7 @@ "ubfx x22, x20, #0, #1", "cbnz x22, #+0x8", "b #+0x84", - "ldrh w22, [x28, #1008]", + "ldrh w22, [x28, #1024]", "strh w22, [x21]", "mov w22, #0x0", "ldrb w23, [x28, #747]", @@ -1599,29 +1587,29 @@ "ldrb w23, [x28, #744]", "ldrb w24, [x28, #745]", "ldrb w25, [x28, #746]", - "ldrb w26, [x28, #750]", + "ldrb w30, [x28, #750]", "orr x22, x22, x23, lsl #8", "orr x22, x22, x24, lsl #9", "orr x22, x22, x25, lsl #10", - "orr x22, x22, x26, lsl #14", + "orr x22, x22, x30, lsl #14", "strh w22, [x21, #2]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "strb w22, [x21, #4]", - "ldr q2, [x28, #752]", - "str q2, [x21, #32]", "ldr q2, [x28, #768]", - "str q2, [x21, #48]", + "str q2, [x21, #32]", "ldr q2, [x28, #784]", - "str q2, [x21, #64]", + "str q2, [x21, #48]", "ldr q2, [x28, #800]", - "str q2, [x21, #80]", + "str q2, [x21, #64]", "ldr q2, [x28, #816]", - "str q2, [x21, #96]", + "str q2, [x21, #80]", "ldr q2, [x28, #832]", - "str q2, [x21, #112]", + "str q2, [x21, #96]", "ldr q2, [x28, #848]", - "str q2, [x21, #128]", + "str q2, [x21, #112]", "ldr q2, [x28, #864]", + "str q2, [x21, #128]", + "ldr q2, [x28, #880]", "str q2, [x21, #144]", "ubfx x22, x20, #1, #1", "cbnz x22, #+0x8", @@ -1676,7 +1664,7 @@ "cbnz x22, #+0x8", "b #+0x84", "ldrh w22, [x20]", - "strh w22, [x28, #1008]", + "strh w22, [x28, #1024]", "ldrh w22, [x20, #2]", "ubfx w23, w22, #11, #3", "strb w23, [x28, #747]", @@ -1689,35 +1677,34 @@ "strb w25, [x28, #746]", "strb w22, [x28, #750]", "ldrb w22, [x20, #4]", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "ldr q2, [x20, #32]", - "str q2, [x28, #752]", - "ldr q2, [x20, #48]", "str q2, [x28, #768]", - "ldr q2, [x20, #64]", + "ldr q2, [x20, #48]", "str q2, [x28, #784]", - "ldr q2, [x20, #80]", + "ldr q2, [x20, #64]", "str q2, [x28, #800]", - "ldr q2, [x20, #96]", + "ldr q2, [x20, #80]", "str q2, [x28, #816]", - "ldr q2, [x20, #112]", + "ldr q2, [x20, #96]", "str q2, [x28, #832]", - "ldr q2, [x20, #128]", + "ldr q2, [x20, #112]", "str q2, [x28, #848]", - "ldr q2, [x20, #144]", + "ldr q2, [x20, #128]", "str q2, [x28, #864]", + "ldr q2, [x20, #144]", + "str q2, [x28, #880]", "b #+0x4c", "mov w22, #0x0", "mov w23, #0x37f", - "strh w23, [x28, #1008]", + "strh w23, [x28, #1024]", "strb w22, [x28, #747]", "strb w22, [x28, #744]", "strb w22, [x28, #745]", "strb w22, [x28, #746]", "strb w22, [x28, #750]", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "movi v2.2d, #0x0", - "str q2, [x28, #752]", "str q2, [x28, #768]", "str q2, [x28, #784]", "str q2, [x28, #800]", @@ -1725,6 +1712,7 @@ "str q2, [x28, #832]", "str q2, [x28, #848]", "str q2, [x28, #864]", + "str q2, [x28, #880]", "ubfx x22, x21, #1, #1", "cbnz x22, #+0x8", "b #+0x48", diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json index e15c45543..fcdf34aaf 100644 --- a/unittests/InstructionCountCI/SecondaryModRM.json +++ b/unittests/InstructionCountCI/SecondaryModRM.json @@ -14,7 +14,7 @@ }, "Instructions": { "xgetbv": { - "ExpectedInstructionCount": 50, + "ExpectedInstructionCount": 54, "Comment": "0xF 0x01 /2 RM-0", "ExpectedArm64ASM": [ "sub sp, sp, #0xf0 (240)", @@ -34,13 +34,15 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "ldr x0, [x28, #1096]", - "ldr x2, [x28, #1112]", + "ldr x0, [x28, #1112]", + "ldr x2, [x28, #1128]", "mov w1, w5", "blr x2", "ldr w4, [x28, #728]", @@ -58,6 +60,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", @@ -81,7 +85,7 @@ "str w0, [x28, #728]", "str x8, [x28, #40]", "mov w0, #0x100", - "str x0, [x28, #1040]", + "str x0, [x28, #1056]", "sub sp, sp, #0x10 (16)", "mov w8, #0xa8", "mov x0, sp", @@ -92,7 +96,7 @@ "ldr w8, [x28, #728]", "msr nzcv, x8", "ldr x8, [x28, #40]", - "str xzr, [x28, #1040]", + "str xzr, [x28, #1056]", "orr x5, x0, x1, lsl #12" ] }, diff --git a/unittests/InstructionCountCI/Secondary_32Bit.json b/unittests/InstructionCountCI/Secondary_32Bit.json index 2242ca84d..28c698182 100644 --- a/unittests/InstructionCountCI/Secondary_32Bit.json +++ b/unittests/InstructionCountCI/Secondary_32Bit.json @@ -25,7 +25,7 @@ "strh w20, [x28, #146]", "ubfx w20, w20, #3, #13", "add x0, x28, x20, lsl #2", - "ldr w20, [x0, #880]", + "ldr w20, [x0, #896]", "str w20, [x28, #176]" ] }, @@ -46,7 +46,7 @@ "strh w20, [x28, #144]", "ubfx w20, w20, #3, #13", "add x0, x28, x20, lsl #2", - "ldr w20, [x0, #880]", + "ldr w20, [x0, #896]", "str w20, [x28, #168]" ] } diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 31b21283b..b2b9c1616 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -109,7 +109,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x66 0x0f 0x2a", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", + "ldr d2, [x28, #768]", "sxtl v2.2d, v2.2s", "scvtf v16.2d, v2.2d" ] @@ -127,7 +127,7 @@ "ExpectedArm64ASM": [ "fcvtn v2.2s, v16.2d", "fcvtzs v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "cvtpd2pi mm0, xmm0": { @@ -137,11 +137,11 @@ "fcvtn v2.2s, v16.2d", "frinti v2.2s, v2.2s", "fcvtzs v2.2s, v2.2s", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "ucomisd xmm0, xmm1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0x66 0x0f 0x2e", "ExpectedArm64ASM": [ "mrs x20, nzcv", @@ -157,17 +157,15 @@ "ubfx x21, x21, #2, #1", "bfi w20, w22, #29, #1", "bfi w20, w23, #30, #1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "mov w21, #0x0", - "mov w22, #0x90000000", - "bic x20, x20, x22", - "strb w21, [x28, #708]", + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w21, #0x90000000", + "bic x20, x20, x21", "msr nzcv, x20" ] }, "comisd xmm0, xmm1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": "0x66 0x0f 0x2f", "ExpectedArm64ASM": [ "mrs x20, nzcv", @@ -183,12 +181,10 @@ "ubfx x21, x21, #2, #1", "bfi w20, w22, #29, #1", "bfi w20, w23, #30, #1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "mov w21, #0x0", - "mov w22, #0x90000000", - "bic x20, x20, x22", - "strb w21, [x28, #708]", + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w21, #0x90000000", + "bic x20, x20, x21", "msr nzcv, x20" ] }, @@ -540,7 +536,7 @@ "0x66 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1672]", + "ldr x0, [x28, #1688]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -554,7 +550,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #1672]", + "ldr x0, [x28, #1688]", "ldr q3, [x0, #16]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -1032,7 +1028,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x66 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2016]", + "ldr q2, [x28, #2032]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.2d, v16.2d, v2.2d" ] diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index e9efa4940..4b10818f6 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -354,7 +354,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1664]", + "ldr x0, [x28, #1680]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -399,7 +399,7 @@ ] }, "popcnt ax, bx": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": "0xf3 0x0f 0xb8", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -408,18 +408,16 @@ "addp v0.8b, v0.8b, v0.8b", "umov w20, v0.b[0]", "bfxil x4, x20, #0, #16", - "mov w21, #0x0", - "mov w22, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x20, #0x0 (0)", "cset x20, eq", - "strb w22, [x28, #706]", - "strb w21, [x28, #708]", "lsl x20, x20, #30", "msr nzcv, x20" ] }, "popcnt eax, ebx": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 11, "Comment": "0xf3 0x0f 0xb8", "ExpectedArm64ASM": [ "mov w20, w7", @@ -427,31 +425,27 @@ "cnt v0.8b, v0.8b", "addv b0, v0.8b", "umov w4, v0.b[0]", - "mov w20, #0x0", - "mov w21, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x4, #0x0 (0)", - "cset x22, eq", - "strb w21, [x28, #706]", - "strb w20, [x28, #708]", - "lsl x20, x22, #30", + "cset x20, eq", + "lsl x20, x20, #30", "msr nzcv, x20" ] }, "popcnt rax, rbx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": "0xf3 0x0f 0xb8", "ExpectedArm64ASM": [ "fmov d0, x7", "cnt v0.8b, v0.8b", "addv b0, v0.8b", "umov w4, v0.b[0]", - "mov w20, #0x0", - "mov w21, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x4, #0x0 (0)", - "cset x22, eq", - "strb w21, [x28, #706]", - "strb w20, [x28, #708]", - "lsl x20, x22, #30", + "cset x20, eq", + "lsl x20, x20, #30", "msr nzcv, x20" ] }, @@ -637,7 +631,7 @@ "ExpectedInstructionCount": 1, "Comment": "0xf3 0x0f 0xd6", "ExpectedArm64ASM": [ - "ldr d16, [x28, #752]" + "ldr d16, [x28, #768]" ] }, "cvtdq2pd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 70119d1d8..da29314b7 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -296,7 +296,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1656]", + "ldr x0, [x28, #1672]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -452,7 +452,7 @@ "ExpectedInstructionCount": 3, "Comment": "0xf2 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #1984]", + "ldr q2, [x28, #2000]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.4s, v16.4s, v2.4s" ] @@ -461,7 +461,7 @@ "ExpectedInstructionCount": 1, "Comment": "0xf2 0x0f 0xd6", "ExpectedArm64ASM": [ - "str d16, [x28, #752]" + "str d16, [x28, #768]" ] }, "cvtpd2dq xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_SVE128.json b/unittests/InstructionCountCI/Secondary_SVE128.json index 36b3b8970..e7dc32671 100644 --- a/unittests/InstructionCountCI/Secondary_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_SVE128.json @@ -35,80 +35,80 @@ "ExpectedInstructionCount": 4, "Comment": "0x0f 0xd1", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "lsr z2.h, p6/m, z2.h, z3.d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrld mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xd2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "lsr z2.s, p6/m, z2.s, z3.d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrlq mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xd3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "lsr z2.d, p6/m, z2.d, z3.d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psraw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xe1", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "asr z2.h, p6/m, z2.h, z3.d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psrad mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xe2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "asr z2.s, p6/m, z2.s, z3.d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllw mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xf1", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "lsl z2.h, p6/m, z2.h, z3.d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "pslld mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xf2", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "lsl z2.s, p6/m, z2.s, z3.d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] }, "psllq mm0, mm1": { "ExpectedInstructionCount": 4, "Comment": "0x0f 0xf3", "ExpectedArm64ASM": [ - "ldr d2, [x28, #752]", - "ldr d3, [x28, #768]", + "ldr d2, [x28, #768]", + "ldr d3, [x28, #784]", "lsl z2.d, p6/m, z2.d, z3.d", - "str d2, [x28, #752]" + "str d2, [x28, #768]" ] } } diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 8f85dd9c2..b9e13dd8e 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -2755,7 +2755,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1680]", + "ldr x0, [x28, #1696]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2824,7 +2824,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1680]", + "ldr x0, [x28, #1696]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2893,7 +2893,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1680]", + "ldr x0, [x28, #1696]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -3307,7 +3307,7 @@ ] }, "vucomiss xmm0, xmm1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": [ "Map 1 0b00 0x2e 128-bit" ], @@ -3325,17 +3325,15 @@ "ubfx x21, x21, #2, #1", "bfi w20, w22, #29, #1", "bfi w20, w23, #30, #1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "mov w21, #0x0", - "mov w22, #0x90000000", - "bic x20, x20, x22", - "strb w21, [x28, #708]", + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w21, #0x90000000", + "bic x20, x20, x21", "msr nzcv, x20" ] }, "vucomisd xmm0, xmm1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": [ "Map 1 0b01 0x2e 128-bit" ], @@ -3353,17 +3351,15 @@ "ubfx x21, x21, #2, #1", "bfi w20, w22, #29, #1", "bfi w20, w23, #30, #1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "mov w21, #0x0", - "mov w22, #0x90000000", - "bic x20, x20, x22", - "strb w21, [x28, #708]", + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w21, #0x90000000", + "bic x20, x20, x21", "msr nzcv, x20" ] }, "vcomiss xmm0, xmm1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": [ "Map 1 0b00 0x2f 128-bit" ], @@ -3381,17 +3377,15 @@ "ubfx x21, x21, #2, #1", "bfi w20, w22, #29, #1", "bfi w20, w23, #30, #1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "mov w21, #0x0", - "mov w22, #0x90000000", - "bic x20, x20, x22", - "strb w21, [x28, #708]", + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w21, #0x90000000", + "bic x20, x20, x21", "msr nzcv, x20" ] }, "vcomisd xmm0, xmm1": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 18, "Comment": [ "Map 1 0b01 0x2f 128-bit" ], @@ -3409,12 +3403,10 @@ "ubfx x21, x21, #2, #1", "bfi w20, w22, #29, #1", "bfi w20, w23, #30, #1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "mov w21, #0x0", - "mov w22, #0x90000000", - "bic x20, x20, x22", - "strb w21, [x28, #708]", + "eor w26, w21, #0x1", + "mov w27, #0x0", + "mov w21, #0x90000000", + "bic x20, x20, x21", "msr nzcv, x20" ] }, @@ -4374,7 +4366,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2016]", + "ldr q2, [x28, #2032]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d" ] @@ -4385,7 +4377,7 @@ "Map 1 0b01 0xd0 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1576]", + "ldr x0, [x28, #1592]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "fadd z16.d, z17.d, z2.d" @@ -4397,7 +4389,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #1984]", + "ldr q2, [x28, #2000]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s" ] @@ -4408,7 +4400,7 @@ "Map 1 0b11 0xd0 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #1560]", + "ldr x0, [x28, #1576]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "fadd z16.s, z17.s, z2.s" diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index fd4636f17..6961b0dd2 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -499,7 +499,7 @@ ] }, "vtestps xmm0, xmm1": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 26, "Comment": [ "Map 2 0b01 0x0e 128-bit" ], @@ -516,26 +516,24 @@ "addv h2, v2.8h", "umov w20, v3.h[0]", "umov w21, v2.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", - "mrs x24, nzcv", + "mov w27, #0x0", + "mov w26, #0x1", + "mrs x22, nzcv", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", - "mov w0, w24", + "mov w0, w22", "bfi w0, w20, #30, #1", "mov w20, w0", "bfi w20, w21, #29, #1", "mov w21, #0x90000000", "bic x20, x20, x21", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, "vtestps ymm0, ymm1": { - "ExpectedInstructionCount": 36, + "ExpectedInstructionCount": 34, "Comment": [ "Map 2 0b01 0x0e 256-bit" ], @@ -560,26 +558,24 @@ "add v2.8h, v0.8h, v1.8h", "umov w20, v3.h[0]", "umov w21, v2.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", - "mrs x24, nzcv", + "mov w27, #0x0", + "mov w26, #0x1", + "mrs x22, nzcv", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", - "mov w0, w24", + "mov w0, w22", "bfi w0, w20, #30, #1", "mov w20, w0", "bfi w20, w21, #29, #1", "mov w21, #0x90000000", "bic x20, x20, x21", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, "vtestpd xmm0, xmm1": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 26, "Comment": [ "Map 2 0b01 0x0f 128-bit" ], @@ -596,26 +592,24 @@ "addv h2, v2.8h", "umov w20, v3.h[0]", "umov w21, v2.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", - "mrs x24, nzcv", + "mov w27, #0x0", + "mov w26, #0x1", + "mrs x22, nzcv", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", - "mov w0, w24", + "mov w0, w22", "bfi w0, w20, #30, #1", "mov w20, w0", "bfi w20, w21, #29, #1", "mov w21, #0x90000000", "bic x20, x20, x21", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, "vtestpd ymm0, ymm1": { - "ExpectedInstructionCount": 36, + "ExpectedInstructionCount": 34, "Comment": [ "Map 2 0b01 0x0f 256-bit" ], @@ -640,21 +634,19 @@ "add v2.8h, v0.8h, v1.8h", "umov w20, v3.h[0]", "umov w21, v2.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", - "mrs x24, nzcv", + "mov w27, #0x0", + "mov w26, #0x1", + "mrs x22, nzcv", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", - "mov w0, w24", + "mov w0, w22", "bfi w0, w20, #30, #1", "mov w20, w0", "bfi w20, w21, #29, #1", "mov w21, #0x90000000", "bic x20, x20, x21", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, @@ -691,7 +683,7 @@ ] }, "vptest xmm0, xmm1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 17, "Comment": [ "Map 2 0b01 0x16 128-bit" ], @@ -704,21 +696,19 @@ "addv h3, v3.8h", "umov w20, v2.h[0]", "umov w21, v3.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", "lsl x20, x20, #30", "orr w20, w20, w21, lsl #29", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, "vptest ymm0, ymm1": { - "ExpectedInstructionCount": 27, + "ExpectedInstructionCount": 25, "Comment": [ "Map 2 0b01 0x16 256-bit" ], @@ -739,16 +729,14 @@ "add v3.8h, v0.8h, v1.8h", "umov w20, v2.h[0]", "umov w21, v3.h[0]", - "mov w22, #0x0", - "mov w23, #0x1", + "mov w27, #0x0", + "mov w26, #0x1", "cmp x20, #0x0 (0)", "cset x20, eq", "cmp x21, #0x0 (0)", "cset x21, eq", "lsl x20, x20, #30", "orr w20, w20, w21, lsl #29", - "strb w23, [x28, #706]", - "strb w22, [x28, #708]", "msr nzcv, x20" ] }, @@ -1649,7 +1637,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #1952]", + "ldr q2, [x28, #1968]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -3249,7 +3237,7 @@ "mov w20, w7", "mov w21, w5", "bic w4, w21, w20", - "strb w4, [x28, #706]", + "mov x26, x4", "tst w4, w4" ] }, @@ -3260,7 +3248,7 @@ ], "ExpectedArm64ASM": [ "bic x4, x5, x7", - "strb w4, [x28, #706]", + "mov x26, x4", "tst x4, x4" ] }, diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 011a9f860..94612c74d 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -4799,7 +4799,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2064]", + "ldr q2, [x28, #2080]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", @@ -4812,7 +4812,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2064]", + "ldr q2, [x28, #2080]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 6be48ec5e..4539ade4a 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -13,7 +13,7 @@ }, "Instructions": { "fadd dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /0" ], @@ -30,6 +30,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -43,8 +45,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -66,11 +68,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -81,6 +85,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -93,12 +99,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -120,15 +126,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /1" ], @@ -145,6 +153,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -158,8 +168,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -181,11 +191,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -196,6 +208,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -208,12 +222,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -235,15 +249,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcom dword [rax]": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 121, "Comment": [ "0xd8 !11b /2" ], @@ -260,6 +276,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -273,8 +291,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -296,11 +314,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -311,6 +331,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -323,12 +345,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -350,6 +372,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -364,7 +388,7 @@ ] }, "fcomp dword [rax]": { - "ExpectedInstructionCount": 121, + "ExpectedInstructionCount": 129, "Comment": [ "0xd8 !11b /3" ], @@ -381,6 +405,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -394,8 +420,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -417,11 +443,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -432,6 +460,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -444,12 +474,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -471,6 +501,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -482,18 +514,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fsub dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /4" ], @@ -510,6 +542,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -523,8 +557,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -546,11 +580,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -561,6 +597,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -573,12 +611,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -600,15 +638,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /5" ], @@ -625,6 +665,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -638,8 +680,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -661,11 +703,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -676,6 +720,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -688,12 +734,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -715,15 +761,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /6" ], @@ -740,6 +788,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -753,8 +803,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -776,11 +826,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -791,6 +843,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -803,12 +857,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -830,15 +884,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xd8 !11b /7" ], @@ -855,6 +911,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -868,8 +926,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -891,11 +949,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -906,6 +966,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -918,12 +980,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -945,15 +1007,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc0 /0" ], @@ -962,9 +1026,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -975,6 +1039,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -987,12 +1053,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1014,15 +1080,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc1 /0" ], @@ -1031,9 +1099,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1044,6 +1112,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1056,12 +1126,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1083,15 +1153,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc2 /0" ], @@ -1100,9 +1172,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1113,6 +1185,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1125,12 +1199,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1152,15 +1226,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc3 /0" ], @@ -1169,9 +1245,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1182,6 +1258,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1194,12 +1272,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1221,15 +1299,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc4 /0" ], @@ -1238,9 +1318,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1251,6 +1331,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1263,12 +1345,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1290,15 +1372,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc5 /0" ], @@ -1307,9 +1391,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1320,6 +1404,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1332,12 +1418,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1359,15 +1445,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc6 /0" ], @@ -1376,9 +1464,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1389,6 +1477,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1401,12 +1491,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1428,15 +1518,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc7 /0" ], @@ -1445,9 +1537,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1458,6 +1550,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1470,12 +1564,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1497,15 +1591,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc8 /1" ], @@ -1514,9 +1610,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1527,6 +1623,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1539,12 +1637,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1566,15 +1664,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xc9 /1" ], @@ -1583,9 +1683,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1596,6 +1696,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1608,12 +1710,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1635,15 +1737,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xca /1" ], @@ -1652,9 +1756,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1665,6 +1769,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1677,12 +1783,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1704,15 +1810,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xcb /1" ], @@ -1721,9 +1829,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1734,6 +1842,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1746,12 +1856,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1773,15 +1883,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xcc /1" ], @@ -1790,9 +1902,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1803,6 +1915,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1815,12 +1929,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1842,15 +1956,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xcd /1" ], @@ -1859,9 +1975,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1872,6 +1988,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1884,12 +2002,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1911,15 +2029,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xce /1" ], @@ -1928,9 +2048,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -1941,6 +2061,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -1953,12 +2075,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -1980,15 +2102,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xcf /1" ], @@ -1997,9 +2121,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2010,6 +2134,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2022,12 +2148,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2049,15 +2175,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcom st0, st0": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd0 /2" ], @@ -2067,9 +2195,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2080,6 +2208,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2092,12 +2222,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2119,6 +2249,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x22, x20, #1, #1", "ubfx x23, x20, #0, #1", @@ -2132,7 +2264,7 @@ ] }, "fcom st0, st1": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd1 /2" ], @@ -2141,9 +2273,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2154,6 +2286,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2166,12 +2300,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2193,6 +2327,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2207,7 +2343,7 @@ ] }, "fcom st0, st2": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd2 /2" ], @@ -2216,9 +2352,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2229,6 +2365,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2241,12 +2379,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2268,6 +2406,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2282,7 +2422,7 @@ ] }, "fcom st0, st3": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd3 /2" ], @@ -2291,9 +2431,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2304,6 +2444,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2316,12 +2458,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2343,6 +2485,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2357,7 +2501,7 @@ ] }, "fcom st0, st4": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd4 /2" ], @@ -2366,9 +2510,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2379,6 +2523,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2391,12 +2537,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2418,6 +2564,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2432,7 +2580,7 @@ ] }, "fcom st0, st5": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd5 /2" ], @@ -2441,9 +2589,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2454,6 +2602,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2466,12 +2616,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2493,6 +2643,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2507,7 +2659,7 @@ ] }, "fcom st0, st6": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd6 /2" ], @@ -2516,9 +2668,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2529,6 +2681,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2541,12 +2695,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2568,6 +2722,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2582,7 +2738,7 @@ ] }, "fcom st0, st7": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd8 11b 0xd7 /2" ], @@ -2591,9 +2747,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2604,6 +2760,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2616,12 +2774,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2643,6 +2801,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -2657,7 +2817,7 @@ ] }, "fcomp st0, st0": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xd8 /3" ], @@ -2667,9 +2827,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2680,6 +2840,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2692,12 +2854,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2719,6 +2881,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -2729,18 +2893,18 @@ "strb w21, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st1": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xd9 /3" ], @@ -2750,9 +2914,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2763,6 +2927,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2775,12 +2941,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2802,6 +2968,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -2813,17 +2981,17 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st2": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xda /3" ], @@ -2832,9 +3000,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2845,6 +3013,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2857,12 +3027,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2884,6 +3054,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -2895,18 +3067,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st3": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xdb /3" ], @@ -2915,9 +3087,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2928,6 +3100,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2940,12 +3114,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2967,6 +3141,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -2978,18 +3154,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st4": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xdc /3" ], @@ -2998,9 +3174,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3011,6 +3187,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3023,12 +3201,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3050,6 +3228,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -3061,18 +3241,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st5": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xdd /3" ], @@ -3081,9 +3261,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3094,6 +3274,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3106,12 +3288,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3133,6 +3315,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -3144,18 +3328,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st6": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xde /3" ], @@ -3164,9 +3348,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3177,6 +3361,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3189,12 +3375,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3216,6 +3402,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -3227,18 +3415,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fcomp st0, st7": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xd8 11b 0xdf /3" ], @@ -3247,9 +3435,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3260,6 +3448,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3272,12 +3462,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3299,6 +3489,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -3310,18 +3502,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fsub st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe0 /4" ], @@ -3330,9 +3522,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3343,6 +3535,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3355,12 +3549,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3382,15 +3576,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe1 /4" ], @@ -3399,9 +3595,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3412,6 +3608,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3424,12 +3622,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3451,15 +3649,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe2 /4" ], @@ -3468,9 +3668,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3481,6 +3681,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3493,12 +3695,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3520,15 +3722,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe3 /4" ], @@ -3537,9 +3741,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3550,6 +3754,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3562,12 +3768,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3589,15 +3795,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe4 /4" ], @@ -3606,9 +3814,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3619,6 +3827,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3631,12 +3841,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3658,15 +3868,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe5 /4" ], @@ -3675,9 +3887,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3688,6 +3900,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3700,12 +3914,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3727,15 +3941,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe6 /4" ], @@ -3744,9 +3960,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3757,6 +3973,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3769,12 +3987,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3796,15 +4014,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe7 /4" ], @@ -3813,9 +4033,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3826,6 +4046,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3838,12 +4060,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3865,15 +4087,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe8 /5" ], @@ -3882,9 +4106,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3895,6 +4119,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3907,12 +4133,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3934,15 +4160,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xe9 /5" ], @@ -3951,9 +4179,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3964,6 +4192,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3976,12 +4206,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4003,15 +4233,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xea /5" ], @@ -4020,9 +4252,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4033,6 +4265,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4045,12 +4279,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4072,15 +4306,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xeb /5" ], @@ -4089,9 +4325,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4102,6 +4338,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4114,12 +4352,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4141,15 +4379,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xec /5" ], @@ -4158,9 +4398,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4171,6 +4411,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4183,12 +4425,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4210,15 +4452,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xed /5" ], @@ -4227,9 +4471,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4240,6 +4484,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4252,12 +4498,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4279,15 +4525,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xee /5" ], @@ -4296,9 +4544,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4309,6 +4557,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4321,12 +4571,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4348,15 +4598,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xef /5" ], @@ -4365,9 +4617,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4378,6 +4630,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4390,12 +4644,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4417,15 +4671,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf0 /6" ], @@ -4434,9 +4690,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4447,6 +4703,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4459,12 +4717,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4486,15 +4744,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf1 /6" ], @@ -4503,9 +4763,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4516,6 +4776,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4528,12 +4790,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4555,15 +4817,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf2 /6" ], @@ -4572,9 +4836,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4585,6 +4849,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4597,12 +4863,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4624,15 +4890,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf3 /6" ], @@ -4641,9 +4909,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4654,6 +4922,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4666,12 +4936,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4693,15 +4963,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf4 /6" ], @@ -4710,9 +4982,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4723,6 +4995,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4735,12 +5009,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4762,15 +5036,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf5 /6" ], @@ -4779,9 +5055,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4792,6 +5068,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4804,12 +5082,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4831,15 +5109,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf6 /6" ], @@ -4848,9 +5128,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4861,6 +5141,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4873,12 +5155,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4900,15 +5182,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf7 /6" ], @@ -4917,9 +5201,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4930,6 +5214,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4942,12 +5228,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4969,15 +5255,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf8 /7" ], @@ -4986,9 +5274,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4999,6 +5287,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5011,12 +5301,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5038,15 +5328,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st1": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xf9 /7" ], @@ -5055,9 +5347,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5068,6 +5360,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5080,12 +5374,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5107,15 +5401,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st2": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xfa /7" ], @@ -5124,9 +5420,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5137,6 +5433,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5149,12 +5447,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5176,15 +5474,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st3": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xfb /7" ], @@ -5193,9 +5493,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5206,6 +5506,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5218,12 +5520,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5245,15 +5547,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st4": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xfc /7" ], @@ -5262,9 +5566,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5275,6 +5579,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5287,12 +5593,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5314,15 +5620,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st5": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xfd /7" ], @@ -5331,9 +5639,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5344,6 +5652,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5356,12 +5666,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5383,15 +5693,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st6": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xfe /7" ], @@ -5400,9 +5712,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5413,6 +5725,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5425,12 +5739,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5452,15 +5766,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st0, st7": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd8 11b 0xff /7" ], @@ -5469,9 +5785,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5482,6 +5798,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5494,12 +5812,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5521,15 +5839,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld dword [rax]": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xd9 !11b /0" ], @@ -5546,6 +5866,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5559,8 +5881,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "fmov s0, s2", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1144]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1160]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5582,30 +5904,32 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst dword [rax]": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 56, "Comment": [ "0xd9 !11b /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5616,6 +5940,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5628,10 +5954,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1160]", + "ldr x3, [x28, #1176]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5653,19 +5979,21 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "fmov s2, s0", "str s2, [x4]" ] }, "fstp dword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xd9 !11b /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -5676,6 +6004,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -5688,10 +6018,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1160]", + "ldr x3, [x28, #1176]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -5713,13 +6043,15 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "fmov s2, s0", "str s2, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -5732,7 +6064,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -5777,7 +6109,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1010]", + "strb w20, [x28, #1026]", "msr nzcv, x22" ] }, @@ -5788,7 +6120,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1008]" + "strh w20, [x28, #1024]" ] }, "fnstenv [rax]": { @@ -5797,7 +6129,7 @@ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1008]", + "ldrh w20, [x28, #1024]", "str w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -5813,7 +6145,7 @@ "orr x21, x21, x24, lsl #10", "orr x21, x21, x25, lsl #14", "str w21, [x4, #4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "and w22, w21, #0x1", "mov w23, #0x3", "mrs x24, nzcv", @@ -5869,7 +6201,7 @@ "0xd9 !11b /7" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1008]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]" ] }, @@ -5883,17 +6215,17 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st1": { @@ -5907,16 +6239,16 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st2": { @@ -5929,17 +6261,17 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st3": { @@ -5952,17 +6284,17 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st4": { @@ -5975,17 +6307,17 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st5": { @@ -5998,17 +6330,17 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st6": { @@ -6021,17 +6353,17 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld st7": { @@ -6044,17 +6376,17 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st0": { @@ -6067,13 +6399,13 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st1": { @@ -6086,13 +6418,13 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st2": { @@ -6105,13 +6437,13 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st3": { @@ -6124,13 +6456,13 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st4": { @@ -6143,13 +6475,13 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st5": { @@ -6162,13 +6494,13 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st6": { @@ -6181,13 +6513,13 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st7": { @@ -6200,13 +6532,13 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fnop": { @@ -6224,14 +6556,14 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w21, #0x0", "mov w22, #0x8000", "fmov d3, x21", "mov v3.d[1], x22", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fabs": { @@ -6242,25 +6574,25 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov x21, #0xffffffffffffffff", "mov w22, #0x7fff", "fmov d3, x21", "mov v3.d[1], x22", "and v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "ftst": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 68, "Comment": [ "0xd9 11b 0xe4 /4" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov w20, #0x0", "fmov d3, x20", "mrs x0, nzcv", @@ -6273,6 +6605,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -6285,12 +6619,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6312,6 +6646,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -6332,11 +6668,11 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mov x21, v2.d[1]", "ubfx x21, x21, #15, #1", "strb w21, [x28, #745]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "lsr w20, w21, w20", "and w20, w20, #0x1", "mrs x21, nzcv", @@ -6358,17 +6694,17 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x8000000000000000", "mov w22, #0x3fff", "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldl2t": { @@ -6381,10 +6717,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x8afe", "movk x21, #0xcd1b, lsl #16", @@ -6394,7 +6730,7 @@ "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldl2e": { @@ -6407,10 +6743,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xf0bc", "movk x21, #0x5c17, lsl #16", @@ -6420,7 +6756,7 @@ "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldpi": { @@ -6433,10 +6769,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xc235", "movk x21, #0x2168, lsl #16", @@ -6446,7 +6782,7 @@ "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldlg2": { @@ -6459,10 +6795,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xf799", "movk x21, #0xfbcf, lsl #16", @@ -6472,7 +6808,7 @@ "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldln2": { @@ -6485,10 +6821,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x79ac", "movk x21, #0xd1cf, lsl #16", @@ -6498,7 +6834,7 @@ "fmov d2, x21", "mov v2.d[1], x22", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fldz": { @@ -6511,27 +6847,27 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov w21, #0x0", "fmov d2, x21", "mov v2.d[1], x21", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "f2xm1": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 59, "Comment": [ "0xd9 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -6542,6 +6878,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -6554,10 +6892,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1312]", + "ldr x3, [x28, #1328]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6579,32 +6917,34 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fyl2x": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xd9 11b 0xf1 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -6615,6 +6955,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -6627,353 +6969,7 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "mov x3, v3.d[0]", - "umov w4, v3.h[4]", - "ldr x5, [x28, #1416]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fptan": { - "ExpectedInstructionCount": 71, - "Comment": [ - "0xd9 11b 0xf2 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1320]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "mov x21, #0x8000000000000000", - "mov w23, #0x3fff", - "fmov d3, x21", - "mov v3.d[1], x23", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str q3, [x0, #752]" - ] - }, - "fpatan": { - "ExpectedInstructionCount": 67, - "Comment": [ - "0xd9 11b 0xf3 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1010]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1424]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fxtract": { - "ExpectedInstructionCount": 115, - "Comment": [ - "0xd9 11b 0xf4 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1352]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v3.16b, v3.16b, v3.16b", - "mov v3.d[0], x0", - "mov v3.h[4], w1", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1360]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fprem1": { - "ExpectedInstructionCount": 63, - "Comment": [ - "0xd9 11b 0xf5 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", @@ -7000,13 +6996,381 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fptan": { + "ExpectedInstructionCount": 75, + "Comment": [ + "0xd9 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1336]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov x21, #0x8000000000000000", + "mov w23, #0x3fff", + "fmov d3, x21", + "mov v3.d[1], x23", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str q3, [x0, #768]" + ] + }, + "fpatan": { + "ExpectedInstructionCount": 71, + "Comment": [ + "0xd9 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1026]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1026]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1440]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fxtract": { + "ExpectedInstructionCount": 123, + "Comment": [ + "0xd9 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1368]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1376]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fprem1": { + "ExpectedInstructionCount": 67, + "Comment": [ + "0xd9 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1448]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "mov w21, #0x0", "strb w21, [x28, #746]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdecstp": { @@ -7034,7 +7398,7 @@ ] }, "fprem": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 67, "Comment": [ "0xd9 11b 0xf8 /7" ], @@ -7043,9 +7407,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7056,6 +7420,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7068,12 +7434,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1440]", + "ldr x5, [x28, #1456]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7095,34 +7461,36 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "mov w21, #0x0", "strb w21, [x28, #746]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fyl2xp1": { - "ExpectedInstructionCount": 123, + "ExpectedInstructionCount": 131, "Comment": [ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mov x20, #0x8000000000000000", "mov w22, #0x3fff", "fmov d4, x20", @@ -7137,6 +7505,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7149,12 +7519,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v4.d[0]", "umov w4, v4.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7176,6 +7546,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7189,6 +7561,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7201,11 +7575,735 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", + "ldr x5, [x28, #1432]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fsqrt": { + "ExpectedInstructionCount": 59, + "Comment": [ + "0xd9 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1344]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fsincos": { + "ExpectedInstructionCount": 125, + "Comment": [ + "0xd9 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1352]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v3.16b, v3.16b, v3.16b", + "mov v3.d[0], x0", + "mov v3.h[4], w1", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1360]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q3, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #768]" + ] + }, + "frndint": { + "ExpectedInstructionCount": 59, + "Comment": [ + "0xd9 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1320]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fscale": { + "ExpectedInstructionCount": 65, + "Comment": [ + "0xd9 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "mov x3, v3.d[0]", + "umov w4, v3.h[4]", + "ldr x5, [x28, #1464]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fsin": { + "ExpectedInstructionCount": 61, + "Comment": [ + "0xd9 11b 0xfe /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1352]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fcos": { + "ExpectedInstructionCount": 61, + "Comment": [ + "0xd9 11b 0xff /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr q2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v2.d[0]", + "umov w2, v2.h[4]", + "ldr x3, [x28, #1360]", + "blr x3", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fiadd dword [rax]": { + "ExpectedInstructionCount": 115, + "Comment": [ + "0xda !11b /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov w1, w21", + "ldr x2, [x28, #1312]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fimul dword [rax]": { + "ExpectedInstructionCount": 115, + "Comment": [ + "0xda !11b /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldr w21, [x4]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov w1, w21", + "ldr x2, [x28, #1312]", + "blr x2", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", @@ -7228,695 +8326,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fsqrt": { - "ExpectedInstructionCount": 55, - "Comment": [ - "0xd9 11b 0xfa /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1328]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fsincos": { - "ExpectedInstructionCount": 117, - "Comment": [ - "0xd9 11b 0xfb /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1336]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v3.16b, v3.16b, v3.16b", - "mov v3.d[0], x0", - "mov v3.h[4], w1", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1344]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" - ] - }, - "frndint": { - "ExpectedInstructionCount": 55, - "Comment": [ - "0xd9 11b 0xfc /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1304]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fscale": { - "ExpectedInstructionCount": 61, - "Comment": [ - "0xd9 11b 0xfd /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "mov x3, v3.d[0]", - "umov w4, v3.h[4]", - "ldr x5, [x28, #1448]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fsin": { - "ExpectedInstructionCount": 57, - "Comment": [ - "0xd9 11b 0xfe /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1336]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fcos": { - "ExpectedInstructionCount": 57, - "Comment": [ - "0xd9 11b 0xff /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v2.d[0]", - "umov w2, v2.h[4]", - "ldr x3, [x28, #1344]", - "blr x3", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fiadd dword [rax]": { - "ExpectedInstructionCount": 107, - "Comment": [ - "0xda !11b /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldr w21, [x4]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov w1, w21", - "ldr x2, [x28, #1296]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fimul dword [rax]": { - "ExpectedInstructionCount": 107, - "Comment": [ - "0xda !11b /1" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldr w21, [x4]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov w1, w21", - "ldr x2, [x28, #1296]", - "blr x2", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "ficom dword [rax]": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 121, "Comment": [ "0xda !11b /2" ], @@ -7933,6 +8353,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7945,9 +8367,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7969,11 +8391,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7984,6 +8408,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7996,12 +8422,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8023,6 +8449,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -8037,7 +8465,7 @@ ] }, "ficomp dword [rax]": { - "ExpectedInstructionCount": 121, + "ExpectedInstructionCount": 129, "Comment": [ "0xda !11b /3" ], @@ -8054,6 +8482,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8066,9 +8496,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8090,11 +8520,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -8105,6 +8537,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8117,12 +8551,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8144,6 +8578,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -8155,18 +8591,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fisub dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xda !11b /4" ], @@ -8183,6 +8619,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8195,9 +8633,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8219,11 +8657,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -8234,6 +8674,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8246,12 +8688,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8273,15 +8715,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fisubr dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xda !11b /5" ], @@ -8298,6 +8742,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8310,9 +8756,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8334,11 +8780,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -8349,6 +8797,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8361,12 +8811,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8388,15 +8838,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fidiv dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xda !11b /6" ], @@ -8413,6 +8865,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8425,9 +8879,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8449,11 +8903,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -8464,6 +8920,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8476,12 +8934,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8503,15 +8961,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fidivr dword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xda !11b /7" ], @@ -8528,6 +8988,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8540,9 +9002,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov w1, w21", - "ldr x2, [x28, #1296]", + "ldr x2, [x28, #1312]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8564,11 +9026,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -8579,6 +9043,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -8591,12 +9057,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -8618,11 +9084,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st0": { @@ -8637,12 +9105,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st1": { @@ -8657,12 +9125,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st2": { @@ -8677,12 +9145,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st3": { @@ -8697,12 +9165,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st4": { @@ -8717,12 +9185,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st5": { @@ -8737,12 +9205,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st6": { @@ -8757,12 +9225,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st7": { @@ -8777,12 +9245,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st0": { @@ -8797,12 +9265,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st1": { @@ -8817,12 +9285,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st2": { @@ -8837,12 +9305,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st3": { @@ -8857,12 +9325,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st4": { @@ -8877,12 +9345,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st5": { @@ -8897,12 +9365,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st6": { @@ -8917,12 +9385,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st7": { @@ -8937,12 +9405,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st0": { @@ -8959,12 +9427,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st1": { @@ -8981,12 +9449,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st2": { @@ -9003,12 +9471,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st3": { @@ -9025,12 +9493,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st4": { @@ -9047,12 +9515,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st5": { @@ -9069,12 +9537,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st6": { @@ -9091,12 +9559,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st7": { @@ -9113,22 +9581,21 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovu st0, st0": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xd8 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9139,23 +9606,22 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xd9 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9166,23 +9632,22 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st2": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xda /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9193,23 +9658,22 @@ "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st3": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdb /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9220,23 +9684,22 @@ "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st4": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdc /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9247,23 +9710,22 @@ "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st5": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdd /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9274,23 +9736,22 @@ "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st6": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xde /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9301,23 +9762,22 @@ "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st7": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdf /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -9328,17 +9788,17 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fucompp": { - "ExpectedInstructionCount": 80, + "ExpectedInstructionCount": 84, "Comment": [ "0xda 11b 0xe9 /5" ], @@ -9348,9 +9808,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -9361,6 +9821,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -9373,12 +9835,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9400,6 +9862,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -9411,22 +9875,22 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fild dword [rax]": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 35, "Comment": [ "0xdf !11b /5" ], @@ -9435,47 +9899,48 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr w21, [x4]", "mov w22, #0x0", "sxtw x21, w21", - "mrs x23, nzcv", + "mrs x22, nzcv", "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", + "mov w23, #0x8000", + "csel x23, x23, xzr, lt", "cneg x21, x21, mi", - "mov w25, #0x3f", + "mov w24, #0x3f", "mov x0, #0x3f", - "clz x26, x21", - "sub x26, x0, x26", - "sub x25, x25, x26", - "lsl x26, x21, x25", - "mov w27, #0x403e", - "sub x25, x27, x25", + "clz x25, x21", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x21, x24", + "mov w30, #0x403e", + "sub x24, x30, x24", + "mov w30, #0x0", "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x26", + "csel x21, x30, x24, eq", + "orr x21, x23, x21", + "fmov d2, x25", "fmov d3, x21", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", - "msr nzcv, x23" + "str q2, [x0, #768]", + "msr nzcv, x22" ] }, "fisttp dword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdb !11b /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -9486,6 +9951,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -9498,10 +9965,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1208]", + "ldr x3, [x28, #1224]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9523,27 +9990,29 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov w21, w0", "str w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fist dword [rax]": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 56, "Comment": [ "0xdb !11b /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -9554,6 +10023,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -9566,10 +10037,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1184]", + "ldr x3, [x28, #1200]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9591,19 +10062,21 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov w20, w0", "str w20, [x4]" ] }, "fistp dword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdf !11b /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -9614,6 +10087,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -9626,10 +10101,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1184]", + "ldr x3, [x28, #1200]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -9651,13 +10126,15 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov w21, w0", "str w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -9674,13 +10151,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fstp tword [rax]": { @@ -9691,15 +10168,15 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -9717,12 +10194,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st1": { @@ -9737,12 +10214,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st2": { @@ -9757,12 +10234,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st3": { @@ -9777,12 +10254,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st4": { @@ -9797,12 +10274,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st5": { @@ -9817,12 +10294,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st6": { @@ -9837,12 +10314,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st7": { @@ -9857,12 +10334,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st0": { @@ -9877,12 +10354,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st1": { @@ -9897,12 +10374,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st2": { @@ -9917,12 +10394,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st3": { @@ -9937,12 +10414,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st4": { @@ -9957,12 +10434,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st5": { @@ -9977,12 +10454,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st6": { @@ -9997,12 +10474,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st7": { @@ -10017,12 +10494,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st0": { @@ -10038,12 +10515,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st1": { @@ -10059,12 +10536,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st2": { @@ -10080,12 +10557,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st3": { @@ -10101,12 +10578,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st4": { @@ -10122,12 +10599,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st5": { @@ -10143,12 +10620,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st6": { @@ -10164,12 +10641,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st7": { @@ -10185,22 +10662,21 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnu st0, st0": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xd8 /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10211,23 +10687,22 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xd9 /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10238,23 +10713,22 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st2": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xda /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10265,23 +10739,22 @@ "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st3": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdb /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10292,23 +10765,22 @@ "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st4": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdc /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10319,23 +10791,22 @@ "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st5": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdd /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10346,23 +10817,22 @@ "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st6": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xde /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10373,23 +10843,22 @@ "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st7": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdf /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -10400,12 +10869,12 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, @@ -10424,17 +10893,17 @@ "ExpectedArm64ASM": [ "mov w20, #0x0", "mov w21, #0x37f", - "strh w21, [x28, #1008]", + "strh w21, [x28, #1024]", "strb w20, [x28, #747]", "strb w20, [x28, #744]", "strb w20, [x28, #745]", "strb w20, [x28, #746]", "strb w20, [x28, #750]", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xe8 /5" ], @@ -10443,9 +10912,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10456,6 +10925,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10468,12 +10939,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10495,6 +10966,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10503,13 +10976,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st1": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xe9 /5" ], @@ -10518,9 +10990,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10531,6 +11003,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10543,12 +11017,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10570,6 +11044,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10578,13 +11054,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st2": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xea /5" ], @@ -10593,9 +11068,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10606,6 +11081,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10618,12 +11095,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10645,6 +11122,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10653,13 +11132,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st3": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xeb /5" ], @@ -10668,9 +11146,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10681,6 +11159,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10693,12 +11173,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10720,6 +11200,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10728,13 +11210,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st4": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xec /5" ], @@ -10743,9 +11224,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10756,6 +11237,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10768,12 +11251,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10795,6 +11278,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10803,13 +11288,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st5": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xed /5" ], @@ -10818,9 +11302,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10831,6 +11315,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10843,12 +11329,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10870,6 +11356,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10878,13 +11366,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st6": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xee /5" ], @@ -10893,9 +11380,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10906,6 +11393,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10918,12 +11407,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10945,6 +11434,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -10953,13 +11444,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st7": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xef /5" ], @@ -10968,9 +11458,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10981,6 +11471,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10993,12 +11485,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11020,6 +11512,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11028,13 +11522,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xf0 /6" ], @@ -11043,9 +11536,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11056,6 +11549,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11068,12 +11563,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11095,6 +11590,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11103,13 +11600,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st1": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xf1 /6" ], @@ -11118,9 +11614,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11131,6 +11627,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11143,12 +11641,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11170,6 +11668,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11178,13 +11678,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st2": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xf2 /6" ], @@ -11193,9 +11692,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11206,6 +11705,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11218,12 +11719,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11245,6 +11746,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11253,13 +11756,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st3": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xf3 /6" ], @@ -11268,9 +11770,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11281,6 +11783,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11293,12 +11797,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11320,6 +11824,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11328,13 +11834,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st4": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xf4 /6" ], @@ -11343,9 +11848,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11356,6 +11861,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11368,12 +11875,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11395,6 +11902,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11403,13 +11912,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st5": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xf5 /6" ], @@ -11418,9 +11926,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11431,6 +11939,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11443,12 +11953,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11470,6 +11980,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11478,13 +11990,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st6": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xf6 /6" ], @@ -11493,9 +12004,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11506,6 +12017,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11518,12 +12031,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11545,6 +12058,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11553,13 +12068,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st7": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 70, "Comment": [ "0xdb 11b 0xf7 /6" ], @@ -11568,9 +12082,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11581,6 +12095,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11593,12 +12109,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11620,6 +12136,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11628,13 +12146,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fadd qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /0" ], @@ -11651,6 +12168,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11664,8 +12183,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11687,11 +12206,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11702,6 +12223,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11714,12 +12237,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11741,15 +12264,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /1" ], @@ -11766,6 +12291,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11779,8 +12306,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11802,11 +12329,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11817,6 +12346,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11829,12 +12360,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11856,15 +12387,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcom qword [rax]": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 121, "Comment": [ "0xdc !11b /2" ], @@ -11881,6 +12414,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11894,8 +12429,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11917,11 +12452,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -11932,6 +12469,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -11944,12 +12483,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -11971,6 +12510,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -11985,7 +12526,7 @@ ] }, "fcomp qword [rax]": { - "ExpectedInstructionCount": 121, + "ExpectedInstructionCount": 129, "Comment": [ "0xdc !11b /3" ], @@ -12002,6 +12543,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12015,8 +12558,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12038,11 +12581,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12053,6 +12598,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12065,12 +12612,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12092,6 +12639,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -12103,18 +12652,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fsub qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /4" ], @@ -12131,6 +12680,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12144,8 +12695,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12167,11 +12718,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12182,6 +12735,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12194,12 +12749,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12221,15 +12776,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /5" ], @@ -12246,6 +12803,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12259,8 +12818,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12282,11 +12841,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12297,6 +12858,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12309,12 +12872,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12336,15 +12899,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /6" ], @@ -12361,6 +12926,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12374,8 +12941,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12397,11 +12964,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12412,6 +12981,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12424,12 +12995,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12451,15 +13022,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr qword [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xdc !11b /7" ], @@ -12476,6 +13049,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12489,8 +13064,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12512,11 +13087,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12527,6 +13104,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12539,12 +13118,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12566,15 +13145,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xc0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fadd st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -12585,9 +13166,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12598,6 +13179,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12610,12 +13193,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12637,15 +13220,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc1 /0" ], @@ -12654,9 +13239,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12667,6 +13252,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12679,12 +13266,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12706,15 +13293,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc2 /0" ], @@ -12723,9 +13312,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12736,6 +13325,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12748,12 +13339,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12775,15 +13366,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc3 /0" ], @@ -12792,9 +13385,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12805,6 +13398,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12817,12 +13412,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12844,15 +13439,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc4 /0" ], @@ -12861,9 +13458,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12874,6 +13471,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12886,12 +13485,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12913,15 +13512,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc5 /0" ], @@ -12930,9 +13531,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -12943,6 +13544,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -12955,12 +13558,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -12982,15 +13585,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc6 /0" ], @@ -12999,9 +13604,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13012,6 +13617,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13024,12 +13631,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13051,15 +13658,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fadd st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc7 /0" ], @@ -13068,9 +13677,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13081,6 +13690,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13093,12 +13704,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13120,15 +13731,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xc8": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fmul st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -13139,9 +13752,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13152,6 +13765,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13164,12 +13779,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13191,15 +13806,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xc9 /1" ], @@ -13208,9 +13825,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13221,6 +13838,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13233,12 +13852,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13260,15 +13879,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xca /1" ], @@ -13277,9 +13898,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13290,6 +13911,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13302,12 +13925,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13329,15 +13952,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xcb /1" ], @@ -13346,9 +13971,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13359,6 +13984,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13371,12 +13998,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13398,15 +14025,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xcc /1" ], @@ -13415,9 +14044,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13428,6 +14057,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13440,12 +14071,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13467,15 +14098,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xcd /1" ], @@ -13484,9 +14117,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13497,6 +14130,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13509,12 +14144,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13536,15 +14171,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xce /1" ], @@ -13553,9 +14190,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13566,6 +14203,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13578,12 +14217,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13605,15 +14244,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmul st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xcf /1" ], @@ -13622,9 +14263,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13635,6 +14276,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13647,12 +14290,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13674,15 +14317,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xe0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fsubr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -13693,9 +14338,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13706,6 +14351,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13718,12 +14365,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13745,15 +14392,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe1 /4" ], @@ -13762,9 +14411,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13775,6 +14424,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13787,12 +14438,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13814,15 +14465,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe2 /4" ], @@ -13831,9 +14484,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13844,6 +14497,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13856,12 +14511,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13883,15 +14538,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe3 /4" ], @@ -13900,9 +14557,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13913,6 +14570,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13925,12 +14584,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -13952,15 +14611,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe4 /4" ], @@ -13969,9 +14630,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -13982,6 +14643,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -13994,12 +14657,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14021,15 +14684,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe5 /4" ], @@ -14038,9 +14703,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14051,6 +14716,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14063,12 +14730,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14090,15 +14757,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe6 /4" ], @@ -14107,9 +14776,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14120,6 +14789,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14132,12 +14803,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14159,15 +14830,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubr st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe7 /4" ], @@ -14176,9 +14849,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14189,6 +14862,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14201,12 +14876,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14228,15 +14903,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xe8": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fsub st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -14247,9 +14924,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14260,6 +14937,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14272,12 +14951,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14299,15 +14978,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xe9 /5" ], @@ -14316,9 +14997,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14329,6 +15010,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14341,12 +15024,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14368,15 +15051,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xea /5" ], @@ -14385,9 +15070,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14398,6 +15083,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14410,12 +15097,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14437,15 +15124,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xeb /5" ], @@ -14454,9 +15143,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14467,6 +15156,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14479,12 +15170,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14506,15 +15197,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xec /5" ], @@ -14523,9 +15216,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14536,6 +15229,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14548,12 +15243,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14575,15 +15270,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xed /5" ], @@ -14592,9 +15289,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14605,6 +15302,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14617,12 +15316,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14644,15 +15343,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xee /5" ], @@ -14661,9 +15362,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14674,6 +15375,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14686,12 +15389,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14713,15 +15416,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsub st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xef /5" ], @@ -14730,9 +15435,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14743,6 +15448,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14755,12 +15462,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14782,15 +15489,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xf0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fdivr st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -14801,9 +15510,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14814,6 +15523,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14826,12 +15537,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14853,15 +15564,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf1 /6" ], @@ -14870,9 +15583,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14883,6 +15596,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14895,12 +15610,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14922,15 +15637,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf2 /6" ], @@ -14939,9 +15656,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -14952,6 +15669,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -14964,12 +15683,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -14991,15 +15710,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf3 /6" ], @@ -15008,9 +15729,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15021,6 +15742,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15033,12 +15756,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15060,15 +15783,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf4 /6" ], @@ -15077,9 +15802,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15090,6 +15815,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15102,12 +15829,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15129,15 +15856,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf5 /6" ], @@ -15146,9 +15875,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15159,6 +15888,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15171,12 +15902,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15198,15 +15929,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf6 /6" ], @@ -15215,9 +15948,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15228,6 +15961,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15240,12 +15975,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15267,15 +16002,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivr st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf7 /6" ], @@ -15284,9 +16021,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15297,6 +16034,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15309,12 +16048,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15336,15 +16075,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xdc, 0xf8": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "fdiv st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -15355,9 +16096,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15368,6 +16109,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15380,12 +16123,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15407,15 +16150,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st1, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xf9 /7" ], @@ -15424,9 +16169,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15437,6 +16182,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15449,12 +16196,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15476,15 +16223,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st2, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xfa /7" ], @@ -15493,9 +16242,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15506,6 +16255,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15518,12 +16269,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15545,15 +16296,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st3, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xfb /7" ], @@ -15562,9 +16315,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15575,6 +16328,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15587,12 +16342,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15614,15 +16369,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st4, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xfc /7" ], @@ -15631,9 +16388,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15644,6 +16401,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15656,12 +16415,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15683,15 +16442,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st5, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xfd /7" ], @@ -15700,9 +16461,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15713,6 +16474,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15725,12 +16488,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15752,15 +16515,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st6, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xfe /7" ], @@ -15769,9 +16534,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15782,6 +16547,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15794,12 +16561,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15821,15 +16588,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdiv st7, st0": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdc 11b 0xff /7" ], @@ -15838,9 +16607,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15851,6 +16620,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15863,12 +16634,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15890,15 +16661,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fld qword [rax]": { - "ExpectedInstructionCount": 61, + "ExpectedInstructionCount": 65, "Comment": [ "0xdd !11b /0" ], @@ -15915,6 +16688,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15928,8 +16703,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -15951,30 +16726,32 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fisttp qword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdd !11b /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -15985,6 +16762,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -15997,10 +16776,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1216]", + "ldr x3, [x28, #1232]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16022,27 +16801,29 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "str x21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fst qword [rax]": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 56, "Comment": [ "0xdd !11b /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -16053,6 +16834,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -16065,10 +16848,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16090,19 +16873,21 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "str d2, [x4]" ] }, "fstp qword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdd !11b /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -16113,6 +16898,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -16125,10 +16912,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16150,13 +16937,15 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "str d2, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16169,7 +16958,7 @@ ], "ExpectedArm64ASM": [ "ldrh w20, [x4]", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -16214,7 +17003,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1010]", + "strb w20, [x28, #1026]", "add x20, x4, #0x1c (28)", "mov x22, #0xffffffffffffffff", "mov w24, #0xffff", @@ -16223,49 +17012,49 @@ "ldur q3, [x4, #28]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x20, #10]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x22, #10]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x20, #10]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x22, #10]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x20, #10]", "and v3.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", "ldur q3, [x22, #10]", "and v2.16b, v3.16b, v2.16b", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -16273,7 +17062,7 @@ "ldr h3, [x22, #8]", "mov v2.h[4], v3.h[0]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x23" ] }, @@ -16284,7 +17073,7 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrh w21, [x28, #1008]", + "ldrh w21, [x28, #1024]", "str w21, [x4]", "mov w21, #0x0", "mov x22, x21", @@ -16292,49 +17081,49 @@ "ldrb w23, [x28, #744]", "ldrb w24, [x28, #745]", "ldrb w25, [x28, #746]", - "ldrb w26, [x28, #750]", + "ldrb w30, [x28, #750]", "orr x22, x22, x23, lsl #8", "orr x22, x22, x24, lsl #9", "orr x22, x22, x25, lsl #10", - "orr x22, x22, x26, lsl #14", + "orr x22, x22, x30, lsl #14", "str w22, [x4, #4]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "and w23, w22, #0x1", "mov w24, #0x3", "mrs x25, nzcv", "cmp x23, #0x0 (0)", "csel x23, x24, x21, eq", "orr w23, w21, w23", - "lsr w26, w22, #1", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #2", - "lsr w26, w22, #2", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #4", - "lsr w26, w22, #3", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #6", - "lsr w26, w22, #4", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #8", - "lsr w26, w22, #5", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #10", - "lsr w26, w22, #6", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #12", + "lsr w30, w22, #1", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #2", + "lsr w30, w22, #2", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #4", + "lsr w30, w22, #3", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #6", + "lsr w30, w22, #4", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #8", + "lsr w30, w22, #5", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #10", + "lsr w30, w22, #6", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #12", "lsr w22, w22, #7", "and w22, w22, #0x1", "cmp x22, #0x0 (0)", @@ -16347,60 +17136,60 @@ "str w21, [x4, #24]", "add x22, x4, #0x1c (28)", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x4, #28]", "add x23, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x22, #10]", "add x22, x23, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x23, #10]", "add x23, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x22, #10]", "add x22, x23, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x23, #10]", "add x23, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x22, #10]", "add x22, x23, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur q2, [x23, #10]", "add x23, x22, #0xa (10)", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "stur d2, [x22, #10]", "dup v2.8h, v2.h[4]", "str h2, [x23, #8]", "mov w20, #0x37f", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "msr nzcv, x25" ] }, @@ -16433,11 +17222,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x0 (0)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st1": { @@ -16450,10 +17239,10 @@ "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w20, w21, w20", "bic w20, w22, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st2": { @@ -16465,11 +17254,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x2 (2)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st3": { @@ -16481,11 +17270,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x3 (3)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st4": { @@ -16497,11 +17286,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x4 (4)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st5": { @@ -16513,11 +17302,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x5 (5)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st6": { @@ -16529,11 +17318,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x6 (6)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st7": { @@ -16545,11 +17334,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "fst st0": { @@ -16562,9 +17351,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st1": { @@ -16577,9 +17366,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st2": { @@ -16592,9 +17381,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st3": { @@ -16607,9 +17396,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st4": { @@ -16622,9 +17411,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st5": { @@ -16637,9 +17426,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st6": { @@ -16652,9 +17441,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st7": { @@ -16667,9 +17456,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fstp st0": { @@ -16682,14 +17471,14 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16706,13 +17495,13 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]", - "ldrb w22, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16728,14 +17517,14 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16751,14 +17540,14 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16774,14 +17563,14 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16797,14 +17586,14 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16820,14 +17609,14 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -16843,21 +17632,21 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucom st0": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe0 /4" ], @@ -16867,9 +17656,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -16880,6 +17669,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -16892,12 +17683,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16919,6 +17710,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x22, x20, #1, #1", "ubfx x23, x20, #0, #1", @@ -16932,7 +17725,7 @@ ] }, "fucom st1": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe1 /4" ], @@ -16941,9 +17734,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -16954,6 +17747,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -16966,12 +17761,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -16993,6 +17788,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17007,7 +17804,7 @@ ] }, "fucom st2": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe2 /4" ], @@ -17016,9 +17813,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17029,6 +17826,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17041,12 +17840,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17068,6 +17867,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17082,7 +17883,7 @@ ] }, "fucom st3": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe3 /4" ], @@ -17091,9 +17892,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17104,6 +17905,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17116,12 +17919,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17143,6 +17946,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17157,7 +17962,7 @@ ] }, "fucom st4": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe4 /4" ], @@ -17166,9 +17971,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17179,6 +17984,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17191,12 +17998,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17218,6 +18025,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17232,7 +18041,7 @@ ] }, "fucom st5": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe5 /4" ], @@ -17241,9 +18050,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17254,6 +18063,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17266,12 +18077,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17293,6 +18104,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17307,7 +18120,7 @@ ] }, "fucom st6": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe6 /4" ], @@ -17316,9 +18129,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17329,6 +18142,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17341,12 +18156,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17368,6 +18183,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17382,7 +18199,7 @@ ] }, "fucom st7": { - "ExpectedInstructionCount": 67, + "ExpectedInstructionCount": 71, "Comment": [ "0xdd 11b 0xe7 /4" ], @@ -17391,9 +18208,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17404,6 +18221,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17416,12 +18235,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17443,6 +18262,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -17457,7 +18278,7 @@ ] }, "fucomp st0": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xe8 /5" ], @@ -17467,9 +18288,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17480,6 +18301,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17492,12 +18315,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17519,6 +18342,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -17529,18 +18354,18 @@ "strb w21, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st1": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xe9 /5" ], @@ -17550,9 +18375,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17563,6 +18388,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17575,12 +18402,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17602,6 +18429,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -17613,17 +18442,17 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st2": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xea /5" ], @@ -17632,9 +18461,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17645,6 +18474,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17657,12 +18488,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17684,6 +18515,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -17695,18 +18528,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st3": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xeb /5" ], @@ -17715,9 +18548,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17728,6 +18561,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17740,12 +18575,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17767,6 +18602,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -17778,18 +18615,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st4": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xec /5" ], @@ -17798,9 +18635,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17811,6 +18648,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17823,12 +18662,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17850,6 +18689,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -17861,18 +18702,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st5": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xed /5" ], @@ -17881,9 +18722,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17894,6 +18735,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17906,12 +18749,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -17933,6 +18776,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -17944,18 +18789,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st6": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xee /5" ], @@ -17964,9 +18809,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -17977,6 +18822,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -17989,12 +18836,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18016,6 +18863,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -18027,18 +18876,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fucomp st7": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 79, "Comment": [ "0xdd 11b 0xef /5" ], @@ -18047,9 +18896,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18060,6 +18909,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18072,12 +18923,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18099,6 +18950,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -18110,18 +18963,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fiadd word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /0" ], @@ -18138,6 +18991,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18150,9 +19005,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18174,11 +19029,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18189,6 +19046,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18201,12 +19060,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18228,15 +19087,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fimul word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /1" ], @@ -18253,6 +19114,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18265,9 +19128,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18289,11 +19152,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18304,6 +19169,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18316,12 +19183,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18343,15 +19210,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "ficom word [rax]": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 121, "Comment": [ "0xde !11b /2" ], @@ -18368,6 +19237,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18380,9 +19251,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18404,11 +19275,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18419,6 +19292,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18431,12 +19306,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18458,6 +19333,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x20, x0", "ubfx x21, x20, #1, #1", "ubfx x22, x20, #0, #1", @@ -18472,7 +19349,7 @@ ] }, "ficomp word [rax]": { - "ExpectedInstructionCount": 121, + "ExpectedInstructionCount": 129, "Comment": [ "0xde !11b /3" ], @@ -18489,6 +19366,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18501,9 +19380,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18525,11 +19404,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18540,6 +19421,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18552,12 +19435,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18579,6 +19462,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -18590,18 +19475,18 @@ "strb w22, [x28, #745]", "strb w21, [x28, #746]", "strb w23, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fisub word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /4" ], @@ -18618,6 +19503,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18630,9 +19517,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18654,11 +19541,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18669,6 +19558,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18681,12 +19572,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18708,15 +19599,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fisubr word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /5" ], @@ -18733,6 +19626,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18745,9 +19640,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18769,11 +19664,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18784,6 +19681,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18796,12 +19695,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18823,15 +19722,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fidiv word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /6" ], @@ -18848,6 +19749,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18860,9 +19763,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18884,11 +19787,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -18899,6 +19804,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18911,12 +19818,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18938,15 +19845,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fidivr word [rax]": { - "ExpectedInstructionCount": 107, + "ExpectedInstructionCount": 115, "Comment": [ "0xde !11b /7" ], @@ -18963,6 +19872,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -18975,9 +19886,9 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "sxth w1, w21", - "ldr x2, [x28, #1288]", + "ldr x2, [x28, #1304]", "blr x2", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -18999,11 +19910,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19014,6 +19927,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19026,12 +19941,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19053,15 +19968,17 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "faddp st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xd8 11b 0xc0 /0" ], @@ -19070,9 +19987,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19083,6 +20000,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19095,12 +20014,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", + "ldr x5, [x28, #1400]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19122,23 +20041,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "faddp st1": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xc1 /0" ], @@ -19148,9 +20069,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19161,6 +20082,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19173,545 +20096,7 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w20", - "bic w21, w23, w21", - "strb w21, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st2": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc2 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x2 (2)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st3": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc3 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x3 (3)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st4": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc4 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x4 (4)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st5": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc5 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x5 (5)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st6": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc6 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x6 (6)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "faddp st7": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc7 /0" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x7 (7)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", - "mov x1, v3.d[0]", - "umov w2, v3.h[4]", - "mov x3, v2.d[0]", - "umov w4, v2.h[4]", - "ldr x5, [x28, #1384]", - "blr x5", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "eor v2.16b, v2.16b, v2.16b", - "mov v2.d[0], x0", - "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", - "mov w23, #0x1", - "lsl w23, w23, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1010]", - "add w20, w20, #0x1 (1)", - "and w20, w20, #0x7", - "strb w20, [x28, #747]", - "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" - ] - }, - "fmulp st0": { - "ExpectedInstructionCount": 69, - "Comment": [ - "0xde 11b 0xc8 /1" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x0 (0)", - "and w21, w21, #0x7", - "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", - "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", @@ -19738,23 +20123,591 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w20", + "bic w21, w23, w21", + "strb w21, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x22, lsl #4", + "str q2, [x0, #768]" + ] + }, + "faddp st2": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc2 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" + ] + }, + "faddp st3": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc3 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "faddp st4": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc4 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "faddp st5": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc5 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x5 (5)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "faddp st6": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc6 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "faddp st7": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc7 /0" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1400]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" + ] + }, + "fmulp st0": { + "ExpectedInstructionCount": 73, + "Comment": [ + "0xde 11b 0xc8 /1" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x0 (0)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", + "ldr q2, [x0, #768]", + "add x0, x28, x20, lsl #4", + "ldr q3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "ldrh w0, [x28, #1024]", + "mov x1, v3.d[0]", + "umov w2, v3.h[4]", + "mov x3, v2.d[0]", + "umov w4, v2.h[4]", + "ldr x5, [x28, #1416]", + "blr x5", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "eor v2.16b, v2.16b, v2.16b", + "mov v2.d[0], x0", + "mov v2.h[4], w1", + "ldrb w22, [x28, #1026]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1026]", + "add w20, w20, #0x1 (1)", + "and w20, w20, #0x7", + "strb w20, [x28, #747]", + "add x0, x28, x21, lsl #4", + "str q2, [x0, #768]" ] }, "fmulp st1": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xc9 /1" ], @@ -19764,9 +20717,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19777,6 +20730,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19789,12 +20744,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19816,22 +20771,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st2": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xca /1" ], @@ -19840,9 +20797,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19853,6 +20810,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19865,12 +20824,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19892,23 +20851,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st3": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xcb /1" ], @@ -19917,9 +20878,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -19930,6 +20891,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -19942,12 +20905,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -19969,23 +20932,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st4": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xcc /1" ], @@ -19994,9 +20959,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20007,6 +20972,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20019,12 +20986,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20046,23 +21013,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st5": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xcd /1" ], @@ -20071,9 +21040,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20084,6 +21053,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20096,12 +21067,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20123,23 +21094,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st6": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xce /1" ], @@ -20148,9 +21121,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20161,6 +21134,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20173,12 +21148,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20200,23 +21175,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fmulp st7": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xcf /1" ], @@ -20225,9 +21202,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20238,6 +21215,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20250,12 +21229,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1400]", + "ldr x5, [x28, #1416]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20277,23 +21256,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcompp": { - "ExpectedInstructionCount": 80, + "ExpectedInstructionCount": 84, "Comment": [ "0xde 11b 0xd9 /3" ], @@ -20303,9 +21284,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20316,6 +21297,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20328,12 +21311,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20355,6 +21338,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -20366,22 +21351,22 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w23, w21, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "db 0xde, 0xe0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "fsubrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -20392,9 +21377,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20405,6 +21390,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20417,12 +21404,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20444,23 +21431,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st1, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe1 /4" ], @@ -20470,9 +21459,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20483,6 +21472,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20495,12 +21486,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20522,22 +21513,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st2, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe2 /4" ], @@ -20546,9 +21539,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20559,6 +21552,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20571,12 +21566,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20598,23 +21593,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st3, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe3 /4" ], @@ -20623,9 +21620,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20636,6 +21633,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20648,12 +21647,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20675,23 +21674,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st4, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe4 /4" ], @@ -20700,9 +21701,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20713,6 +21714,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20725,12 +21728,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20752,23 +21755,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st5, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe5 /4" ], @@ -20777,9 +21782,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20790,6 +21795,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20802,12 +21809,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20829,23 +21836,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st6, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe6 /4" ], @@ -20854,9 +21863,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20867,6 +21876,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20879,12 +21890,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20906,23 +21917,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubrp st7, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe7 /4" ], @@ -20931,9 +21944,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -20944,6 +21957,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -20956,12 +21971,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -20983,23 +21998,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xde, 0xe8": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "fsubp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -21010,9 +22027,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21023,6 +22040,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21035,12 +22054,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21062,23 +22081,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st1, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xe9 /5" ], @@ -21088,9 +22109,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21101,6 +22122,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21113,12 +22136,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21140,22 +22163,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st2, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xea /5" ], @@ -21164,9 +22189,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21177,6 +22202,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21189,12 +22216,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21216,23 +22243,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st3, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xeb /5" ], @@ -21241,9 +22270,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21254,6 +22283,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21266,12 +22297,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21293,23 +22324,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st4, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xec /5" ], @@ -21318,9 +22351,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21331,6 +22364,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21343,12 +22378,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21370,23 +22405,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st5, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xed /5" ], @@ -21395,9 +22432,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21408,6 +22445,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21420,12 +22459,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21447,23 +22486,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st6, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xee /5" ], @@ -21472,9 +22513,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21485,6 +22526,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21497,12 +22540,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21524,23 +22567,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fsubp st7, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xef /5" ], @@ -21549,9 +22594,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21562,6 +22607,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21574,12 +22621,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1392]", + "ldr x5, [x28, #1408]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21601,23 +22648,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xde, 0xf0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "fdivrp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -21628,9 +22677,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21641,6 +22690,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21653,12 +22704,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21680,23 +22731,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st1, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf1 /6" ], @@ -21706,9 +22759,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21719,6 +22772,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21731,12 +22786,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21758,22 +22813,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st2, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf2 /6" ], @@ -21782,9 +22839,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21795,6 +22852,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21807,12 +22866,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21834,23 +22893,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st3, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf3 /6" ], @@ -21859,9 +22920,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21872,6 +22933,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21884,12 +22947,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21911,23 +22974,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st4, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf4 /6" ], @@ -21936,9 +23001,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -21949,6 +23014,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -21961,12 +23028,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -21988,23 +23055,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st5, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf5 /6" ], @@ -22013,9 +23082,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22026,6 +23095,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22038,12 +23109,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22065,23 +23136,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st6, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf6 /6" ], @@ -22090,9 +23163,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22103,6 +23176,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22115,12 +23190,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22142,23 +23217,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivrp st7, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf7 /6" ], @@ -22167,9 +23244,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22180,6 +23257,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22192,12 +23271,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22219,23 +23298,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "db 0xde, 0xf8": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "fdivp st0, st0", "Needs manual encoding since otherwise nasm will emit the 0xd8 variant.", @@ -22246,9 +23327,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22259,6 +23340,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22271,12 +23354,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22298,23 +23381,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st1, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xf9 /7" ], @@ -22324,9 +23409,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22337,6 +23422,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22349,12 +23436,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22376,22 +23463,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st2, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xfa /7" ], @@ -22400,9 +23489,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22413,6 +23502,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22425,12 +23516,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22452,23 +23543,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st3, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xfb /7" ], @@ -22477,9 +23570,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22490,6 +23583,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22502,12 +23597,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22529,23 +23624,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st4, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xfc /7" ], @@ -22554,9 +23651,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22567,6 +23664,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22579,12 +23678,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22606,23 +23705,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st5, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xfd /7" ], @@ -22631,9 +23732,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22644,6 +23745,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22656,12 +23759,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22683,23 +23786,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st6, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xfe /7" ], @@ -22708,9 +23813,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22721,6 +23826,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22733,12 +23840,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22760,23 +23867,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fdivp st7, st0": { - "ExpectedInstructionCount": 69, + "ExpectedInstructionCount": 73, "Comment": [ "0xde 11b 0xff /7" ], @@ -22785,9 +23894,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22798,6 +23907,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22810,12 +23921,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", "mov x3, v3.d[0]", "umov w4, v3.h[4]", - "ldr x5, [x28, #1408]", + "ldr x5, [x28, #1424]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22837,23 +23948,25 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fild word [rax]": { - "ExpectedInstructionCount": 34, + "ExpectedInstructionCount": 35, "Comment": [ "0xdf !11b /0" ], @@ -22862,47 +23975,48 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldrh w21, [x4]", "mov w22, #0x0", "sxth x21, w21", - "mrs x23, nzcv", + "mrs x22, nzcv", "cmp x21, #0x0 (0)", - "mov w24, #0x8000", - "csel x24, x24, xzr, lt", + "mov w23, #0x8000", + "csel x23, x23, xzr, lt", "cneg x21, x21, mi", - "mov w25, #0x3f", + "mov w24, #0x3f", "mov x0, #0x3f", - "clz x26, x21", - "sub x26, x0, x26", - "sub x25, x25, x26", - "lsl x26, x21, x25", - "mov w27, #0x403e", - "sub x25, x27, x25", + "clz x25, x21", + "sub x25, x0, x25", + "sub x24, x24, x25", + "lsl x25, x21, x24", + "mov w30, #0x403e", + "sub x24, x30, x24", + "mov w30, #0x0", "cmp x21, #0x0 (0)", - "csel x21, x22, x25, eq", - "orr x21, x24, x21", - "fmov d2, x26", + "csel x21, x30, x24, eq", + "orr x21, x23, x21", + "fmov d2, x25", "fmov d3, x21", "mov v2.d[1], v3.d[0]", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", - "msr nzcv, x23" + "str q2, [x0, #768]", + "msr nzcv, x22" ] }, "fisttp word [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdf !11b /1" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22913,6 +24027,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22925,10 +24041,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1200]", + "ldr x3, [x28, #1216]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -22950,27 +24066,29 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "sxth x21, w0", "strh w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fist word [rax]": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 56, "Comment": [ "0xdf !11b /2" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -22981,6 +24099,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -22993,10 +24113,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1176]", + "ldr x3, [x28, #1192]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23018,19 +24138,21 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "sxth x20, w0", "strh w20, [x4]" ] }, "fistp word [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdf !11b /3" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23041,6 +24163,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23053,10 +24177,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1176]", + "ldr x3, [x28, #1192]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23078,20 +24202,22 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "sxth x21, w0", "strh w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fbld tword [rax]": { - "ExpectedInstructionCount": 62, + "ExpectedInstructionCount": 66, "Comment": [ "0xdf !11b /4" ], @@ -23100,10 +24226,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -23116,6 +24242,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23128,10 +24256,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1376]", + "ldr x3, [x28, #1392]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23153,22 +24281,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fbstp tword [rax]": { - "ExpectedInstructionCount": 64, + "ExpectedInstructionCount": 68, "Comment": [ "0xdf !11b /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23179,6 +24309,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23191,10 +24323,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1368]", + "ldr x3, [x28, #1384]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23216,17 +24348,19 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -23349,7 +24483,7 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xe8 /5" ], @@ -23358,9 +24492,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23371,6 +24505,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23383,12 +24519,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23410,6 +24546,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23419,12 +24557,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23432,7 +24569,7 @@ ] }, "fucomip st1": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xe9 /5" ], @@ -23442,9 +24579,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23455,6 +24592,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23467,12 +24606,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23494,6 +24633,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -23502,12 +24643,11 @@ "orr w24, w24, w22", "lsl x23, x23, #29", "orr w23, w23, w24, lsl #30", - "eor w22, w22, #0x1", - "strb w22, [x28, #706]", - "ldrb w22, [x28, #1010]", + "eor w26, w22, #0x1", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23515,7 +24655,7 @@ ] }, "fucomip st2": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xea /5" ], @@ -23524,9 +24664,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23537,6 +24677,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23549,12 +24691,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23576,6 +24718,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23585,12 +24729,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23598,7 +24741,7 @@ ] }, "fucomip st3": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xeb /5" ], @@ -23607,9 +24750,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23620,6 +24763,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23632,12 +24777,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23659,6 +24804,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23668,12 +24815,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23681,7 +24827,7 @@ ] }, "fucomip st4": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xec /5" ], @@ -23690,9 +24836,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23703,6 +24849,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23715,12 +24863,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23742,6 +24890,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23751,12 +24901,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23764,7 +24913,7 @@ ] }, "fucomip st5": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xed /5" ], @@ -23773,9 +24922,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23786,6 +24935,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23798,12 +24949,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23825,6 +24976,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23834,12 +24987,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23847,7 +24999,7 @@ ] }, "fucomip st6": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xee /5" ], @@ -23856,9 +25008,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23869,6 +25021,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23881,12 +25035,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23908,6 +25062,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -23917,12 +25073,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -23930,7 +25085,7 @@ ] }, "fucomip st7": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xef /5" ], @@ -23939,9 +25094,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -23952,6 +25107,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -23964,12 +25121,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -23991,6 +25148,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24000,12 +25159,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24013,7 +25171,7 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xf0 /6" ], @@ -24022,9 +25180,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24035,6 +25193,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24047,12 +25207,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24074,6 +25234,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24083,12 +25245,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24096,7 +25257,7 @@ ] }, "fcomip st1": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xf1 /6" ], @@ -24106,9 +25267,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24119,6 +25280,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24131,12 +25294,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24158,6 +25321,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x22, x0", "ubfx x23, x22, #1, #1", "ubfx x24, x22, #0, #1", @@ -24166,12 +25331,11 @@ "orr w24, w24, w22", "lsl x23, x23, #29", "orr w23, w23, w24, lsl #30", - "eor w22, w22, #0x1", - "strb w22, [x28, #706]", - "ldrb w22, [x28, #1010]", + "eor w26, w22, #0x1", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24179,7 +25343,7 @@ ] }, "fcomip st2": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xf2 /6" ], @@ -24188,9 +25352,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24201,6 +25365,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24213,12 +25379,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24240,6 +25406,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24249,12 +25417,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24262,7 +25429,7 @@ ] }, "fcomip st3": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xf3 /6" ], @@ -24271,9 +25438,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24284,6 +25451,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24296,12 +25465,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24323,6 +25492,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24332,12 +25503,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24345,7 +25515,7 @@ ] }, "fcomip st4": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xf4 /6" ], @@ -24354,9 +25524,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24367,6 +25537,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24379,12 +25551,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24406,6 +25578,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24415,12 +25589,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24428,7 +25601,7 @@ ] }, "fcomip st5": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xf5 /6" ], @@ -24437,9 +25610,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24450,6 +25623,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24462,12 +25637,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24489,6 +25664,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24498,12 +25675,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24511,7 +25687,7 @@ ] }, "fcomip st6": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xf6 /6" ], @@ -24520,9 +25696,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24533,6 +25709,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24545,12 +25723,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24572,6 +25750,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24581,12 +25761,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -24594,7 +25773,7 @@ ] }, "fcomip st7": { - "ExpectedInstructionCount": 75, + "ExpectedInstructionCount": 78, "Comment": [ "0xdf 11b 0xf7 /6" ], @@ -24603,9 +25782,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -24616,6 +25795,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -24628,12 +25809,12 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", "mov x3, v2.d[0]", "umov w4, v2.h[4]", - "ldr x5, [x28, #1280]", + "ldr x5, [x28, #1296]", "blr x5", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -24655,6 +25836,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov x21, x0", "ubfx x22, x21, #1, #1", "ubfx x23, x21, #0, #1", @@ -24664,12 +25847,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index b6637c2d0..86e401671 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -24,10 +24,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul dword [rax]": { @@ -40,10 +40,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcom dword [rax]": { @@ -56,7 +56,7 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -88,7 +88,7 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -107,11 +107,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -128,10 +128,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr dword [rax]": { @@ -144,10 +144,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv dword [rax]": { @@ -160,10 +160,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr dword [rax]": { @@ -176,10 +176,10 @@ "ldr s2, [x4]", "fcvt d2, s2", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st0": { @@ -192,12 +192,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st1": { @@ -210,12 +210,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st2": { @@ -228,12 +228,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st3": { @@ -246,12 +246,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st4": { @@ -264,12 +264,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st5": { @@ -282,12 +282,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st6": { @@ -300,12 +300,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st0, st7": { @@ -318,12 +318,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st0": { @@ -336,12 +336,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st1": { @@ -354,12 +354,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st2": { @@ -372,12 +372,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st3": { @@ -390,12 +390,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st4": { @@ -408,12 +408,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st5": { @@ -426,12 +426,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st6": { @@ -444,12 +444,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st0, st7": { @@ -462,12 +462,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcom st0, st0": { @@ -481,9 +481,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -514,9 +514,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -548,9 +548,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -582,9 +582,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -616,9 +616,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -650,9 +650,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -684,9 +684,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -718,9 +718,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -753,9 +753,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -773,11 +773,11 @@ "strb w21, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -795,9 +795,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -816,10 +816,10 @@ "strb w24, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -836,9 +836,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -857,11 +857,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -878,9 +878,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -899,11 +899,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -920,9 +920,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -941,11 +941,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -962,9 +962,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -983,11 +983,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -1004,9 +1004,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -1025,11 +1025,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -1046,9 +1046,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -1067,11 +1067,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -1088,12 +1088,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st1": { @@ -1106,12 +1106,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st2": { @@ -1124,12 +1124,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st3": { @@ -1142,12 +1142,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st4": { @@ -1160,12 +1160,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st5": { @@ -1178,12 +1178,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st6": { @@ -1196,12 +1196,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st0, st7": { @@ -1214,12 +1214,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st0": { @@ -1232,12 +1232,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st1": { @@ -1250,12 +1250,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st2": { @@ -1268,12 +1268,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st3": { @@ -1286,12 +1286,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st4": { @@ -1304,12 +1304,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st5": { @@ -1322,12 +1322,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st6": { @@ -1340,12 +1340,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st0, st7": { @@ -1358,12 +1358,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st0": { @@ -1376,12 +1376,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st1": { @@ -1394,12 +1394,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st2": { @@ -1412,12 +1412,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st3": { @@ -1430,12 +1430,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st4": { @@ -1448,12 +1448,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st5": { @@ -1466,12 +1466,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st6": { @@ -1484,12 +1484,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st0, st7": { @@ -1502,12 +1502,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st0": { @@ -1520,12 +1520,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st1": { @@ -1538,12 +1538,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st2": { @@ -1556,12 +1556,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st3": { @@ -1574,12 +1574,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st4": { @@ -1592,12 +1592,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st5": { @@ -1610,12 +1610,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st6": { @@ -1628,12 +1628,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st0, st7": { @@ -1646,12 +1646,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld dword [rax]": { @@ -1666,13 +1666,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fst dword [rax]": { @@ -1683,7 +1683,7 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fcvt s2, d2", "str s2, [x4]" ] @@ -1696,14 +1696,14 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fcvt s2, d2", "str s2, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -1724,7 +1724,7 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -1769,7 +1769,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w21, w20, lsl #7", - "strb w20, [x28, #1010]", + "strb w20, [x28, #1026]", "msr nzcv, x22" ] }, @@ -1788,7 +1788,7 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1008]" + "strh w20, [x28, #1024]" ] }, "fnstenv [rax]": { @@ -1797,7 +1797,7 @@ "0xd9 !11b /6" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1008]", + "ldrh w20, [x28, #1024]", "str w20, [x4]", "mov w20, #0x0", "ldrb w21, [x28, #747]", @@ -1813,7 +1813,7 @@ "orr x21, x21, x24, lsl #10", "orr x21, x21, x25, lsl #14", "str w21, [x4, #4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "and w22, w21, #0x1", "mov w23, #0x3", "mrs x24, nzcv", @@ -1869,7 +1869,7 @@ "0xd9 !11b /7" ], "ExpectedArm64ASM": [ - "ldrh w20, [x28, #1008]", + "ldrh w20, [x28, #1024]", "strh w20, [x4]" ] }, @@ -1883,17 +1883,17 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st1": { @@ -1907,16 +1907,16 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st2": { @@ -1929,17 +1929,17 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st3": { @@ -1952,17 +1952,17 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st4": { @@ -1975,17 +1975,17 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st5": { @@ -1998,17 +1998,17 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st6": { @@ -2021,17 +2021,17 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld st7": { @@ -2044,17 +2044,17 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fxch st0, st0": { @@ -2067,13 +2067,13 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st1": { @@ -2086,13 +2086,13 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st2": { @@ -2105,13 +2105,13 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st3": { @@ -2124,13 +2124,13 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st4": { @@ -2143,13 +2143,13 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st5": { @@ -2162,13 +2162,13 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st6": { @@ -2181,13 +2181,13 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fxch st0, st7": { @@ -2200,13 +2200,13 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x20, lsl #4", - "str q3, [x0, #752]", + "str q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fnop": { @@ -2224,10 +2224,10 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fneg v2.2d, v2.2d", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fabs": { @@ -2238,10 +2238,10 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fabs d2, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "ftst": { @@ -2252,7 +2252,7 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov w20, #0x0", "fmov d3, x20", "mrs x21, nzcv", @@ -2283,11 +2283,11 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mov x21, v2.d[0]", "lsr x21, x21, #63", "strb w21, [x28, #745]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "lsr w20, w21, w20", "mov w21, #0x1", "and w20, w20, #0x1", @@ -2311,15 +2311,15 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x3ff0000000000000", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldl2t": { @@ -2332,10 +2332,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0xa372", "movk x21, #0x979, lsl #16", @@ -2343,7 +2343,7 @@ "movk x21, #0x400a, lsl #48", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldl2e": { @@ -2356,10 +2356,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x82fe", "movk x21, #0x652b, lsl #16", @@ -2367,7 +2367,7 @@ "movk x21, #0x3ff7, lsl #48", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldpi": { @@ -2380,10 +2380,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x2d18", "movk x21, #0x5444, lsl #16", @@ -2391,7 +2391,7 @@ "movk x21, #0x4009, lsl #48", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldlg2": { @@ -2404,10 +2404,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x79ff", "movk x21, #0x509f, lsl #16", @@ -2415,7 +2415,7 @@ "movk x21, #0x3fd3, lsl #48", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldln2": { @@ -2428,10 +2428,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov x21, #0x39ef", "movk x21, #0xfefa, lsl #16", @@ -2439,7 +2439,7 @@ "movk x21, #0x3fe6, lsl #48", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fldz": { @@ -2452,26 +2452,26 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "mov w21, #0x0", "fmov d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "f2xm1": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 56, "Comment": [ "0xd9 11b 0xf0 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2482,6 +2482,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2495,8 +2497,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1488]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1504]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -2518,30 +2520,32 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fyl2x": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 67, "Comment": [ "0xd9 11b 0xf1 /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2552,6 +2556,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2566,248 +2572,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1496]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fptan": { - "ExpectedInstructionCount": 66, - "Comment": [ - "0xd9 11b 0xf2 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1472]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "mov x21, #0x3ff0000000000000", - "fmov d3, x21", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str d3, [x0, #752]" - ] - }, - "fpatan": { - "ExpectedInstructionCount": 63, - "Comment": [ - "0xd9 11b 0xf3 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1010]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v3.8b", - "mov v1.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1480]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fxtract": { - "ExpectedInstructionCount": 23, - "Comment": [ - "0xd9 11b 0xf4 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "mov x21, v2.d[0]", - "and x23, x21, #0x7ff0000000000000", - "lsr x23, x23, #52", - "sub x23, x23, #0x3ff (1023)", - "scvtf d2, x23", - "and x21, x21, #0x800fffffffffffff", - "orr x21, x21, #0x3ff0000000000000", - "fmov d3, x21", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str d3, [x0, #752]" - ] - }, - "fprem1": { - "ExpectedInstructionCount": 59, - "Comment": [ - "0xd9 11b 0xf5 /6" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "mov v1.8b, v3.8b", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "ldr x1, [x28, #1512]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", @@ -2830,11 +2595,266 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fptan": { + "ExpectedInstructionCount": 70, + "Comment": [ + "0xd9 11b 0xf2 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1488]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "mov x21, #0x3ff0000000000000", + "fmov d3, x21", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str d3, [x0, #768]" + ] + }, + "fpatan": { + "ExpectedInstructionCount": 67, + "Comment": [ + "0xd9 11b 0xf3 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1026]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1026]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v3.8b", + "mov v1.8b, v2.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1496]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fxtract": { + "ExpectedInstructionCount": 23, + "Comment": [ + "0xd9 11b 0xf4 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "mov x21, v2.d[0]", + "and x23, x21, #0x7ff0000000000000", + "lsr x23, x23, #52", + "sub x23, x23, #0x3ff (1023)", + "scvtf d2, x23", + "and x21, x21, #0x800fffffffffffff", + "orr x21, x21, #0x3ff0000000000000", + "fmov d3, x21", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str d3, [x0, #768]" + ] + }, + "fprem1": { + "ExpectedInstructionCount": 63, + "Comment": [ + "0xd9 11b 0xf5 /6" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1528]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "mov w21, #0x0", "strb w21, [x28, #746]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdecstp": { @@ -2862,7 +2882,7 @@ ] }, "fprem": { - "ExpectedInstructionCount": 59, + "ExpectedInstructionCount": 63, "Comment": [ "0xd9 11b 0xf8 /7" ], @@ -2871,9 +2891,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -2884,6 +2904,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -2898,295 +2920,7 @@ "str x30, [x0]", "mov v0.8b, v2.8b", "mov v1.8b, v3.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1504]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fyl2xp1": { - "ExpectedInstructionCount": 66, - "Comment": [ - "0xd9 11b 0xf9 /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "ldrb w21, [x28, #1010]", - "mov w22, #0x1", - "lsl w22, w22, w20", - "bic w21, w21, w22", - "strb w21, [x28, #1010]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "strb w21, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", - "mov x20, #0x3ff0000000000000", - "fmov d4, x20", - "fadd d2, d2, d4", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "mov v1.8b, v3.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1496]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fsqrt": { - "ExpectedInstructionCount": 6, - "Comment": [ - "0xd9 11b 0xfa /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "fsqrt d2, d2", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fsincos": { - "ExpectedInstructionCount": 111, - "Comment": [ - "0xd9 11b 0xfb /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "mov w21, #0x1", - "sub w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1010]", - "lsl w21, w21, w22", - "orr w21, w23, w21", - "strb w21, [x28, #1010]", - "strb w22, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1456]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v3.8b, v0.8b", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1464]", - "blr x1", - "ld1 {v2.2d, v3.2d}, [sp], #32", - "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", - "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", - "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", - "ldr x30, [sp], #16", - "ldr w4, [x28, #728]", - "msr nzcv, x4", - "add x4, x28, #0xc0 (192)", - "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", - "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", - "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", - "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", - "ldp x4, x5, [x28, #8]", - "ldp x6, x7, [x28, #24]", - "ldp x8, x9, [x28, #40]", - "ldp x10, x11, [x28, #56]", - "ldp x12, x13, [x28, #72]", - "ldp x14, x15, [x28, #88]", - "ldp x16, x17, [x28, #104]", - "ldp x19, x29, [x28, #120]", - "mov v2.8b, v0.8b", - "mov w21, #0x0", - "strb w21, [x28, #746]", - "add x0, x28, x20, lsl #4", - "str d3, [x0, #752]", - "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" - ] - }, - "frndint": { - "ExpectedInstructionCount": 6, - "Comment": [ - "0xd9 11b 0xfc /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "frinti d2, d2", - "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" - ] - }, - "fscale": { - "ExpectedInstructionCount": 57, - "Comment": [ - "0xd9 11b 0xfd /7" - ], - "ExpectedArm64ASM": [ - "ldrb w20, [x28, #747]", - "add w21, w20, #0x1 (1)", - "and w21, w21, #0x7", - "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", - "add x0, x28, x21, lsl #4", - "ldr d3, [x0, #752]", - "mrs x0, nzcv", - "str w0, [x28, #728]", - "stp x4, x5, [x28, #8]", - "stp x6, x7, [x28, #24]", - "stp x8, x9, [x28, #40]", - "stp x10, x11, [x28, #56]", - "stp x12, x13, [x28, #72]", - "stp x14, x15, [x28, #88]", - "stp x16, x17, [x28, #104]", - "stp x19, x29, [x28, #120]", - "add x0, x28, #0xc0 (192)", - "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", - "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", - "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", - "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", - "sub sp, sp, #0xf0 (240)", - "mov x0, sp", - "st1 {v2.2d, v3.2d}, [x0], #32", - "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", - "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", - "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", - "str x30, [x0]", - "mov v0.8b, v2.8b", - "mov v1.8b, v3.8b", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "ldr x1, [x28, #1520]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", @@ -3209,20 +2943,326 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fyl2xp1": { + "ExpectedInstructionCount": 70, + "Comment": [ + "0xd9 11b 0xf9 /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "ldrb w21, [x28, #1026]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", + "strb w21, [x28, #1026]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "strb w21, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #768]", + "mov x20, #0x3ff0000000000000", + "fmov d4, x20", + "fadd d2, d2, d4", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1512]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "add x0, x28, x21, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fsqrt": { + "ExpectedInstructionCount": 6, + "Comment": [ + "0xd9 11b 0xfa /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "fsqrt d2, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fsincos": { + "ExpectedInstructionCount": 119, + "Comment": [ + "0xd9 11b 0xfb /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "mov w21, #0x1", + "sub w22, w20, #0x1 (1)", + "and w22, w22, #0x7", + "ldrb w23, [x28, #1026]", + "lsl w21, w21, w22", + "orr w21, w23, w21", + "strb w21, [x28, #1026]", + "strb w22, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1472]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v3.8b, v0.8b", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1480]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", + "mov v2.8b, v0.8b", + "mov w21, #0x0", + "strb w21, [x28, #746]", + "add x0, x28, x20, lsl #4", + "str d3, [x0, #768]", + "add x0, x28, x22, lsl #4", + "str d2, [x0, #768]" + ] + }, + "frndint": { + "ExpectedInstructionCount": 6, + "Comment": [ + "0xd9 11b 0xfc /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "frinti d2, d2", + "add x0, x28, x20, lsl #4", + "str d2, [x0, #768]" + ] + }, + "fscale": { + "ExpectedInstructionCount": 61, + "Comment": [ + "0xd9 11b 0xfd /7" + ], + "ExpectedArm64ASM": [ + "ldrb w20, [x28, #747]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x20, lsl #4", + "ldr d2, [x0, #768]", + "add x0, x28, x21, lsl #4", + "ldr d3, [x0, #768]", + "mrs x0, nzcv", + "str w0, [x28, #728]", + "stp x4, x5, [x28, #8]", + "stp x6, x7, [x28, #24]", + "stp x8, x9, [x28, #40]", + "stp x10, x11, [x28, #56]", + "stp x12, x13, [x28, #72]", + "stp x14, x15, [x28, #88]", + "stp x16, x17, [x28, #104]", + "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", + "add x0, x28, #0xc0 (192)", + "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", + "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", + "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64", + "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64", + "sub sp, sp, #0xf0 (240)", + "mov x0, sp", + "st1 {v2.2d, v3.2d}, [x0], #32", + "st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64", + "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", + "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", + "str x30, [x0]", + "mov v0.8b, v2.8b", + "mov v1.8b, v3.8b", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1536]", + "blr x1", + "ld1 {v2.2d, v3.2d}, [sp], #32", + "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", + "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64", + "ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64", + "ldr x30, [sp], #16", + "ldr w4, [x28, #728]", + "msr nzcv, x4", + "add x4, x28, #0xc0 (192)", + "ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64", + "ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64", + "ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64", + "ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64", + "ldp x4, x5, [x28, #8]", + "ldp x6, x7, [x28, #24]", + "ldp x8, x9, [x28, #40]", + "ldp x10, x11, [x28, #56]", + "ldp x12, x13, [x28, #72]", + "ldp x14, x15, [x28, #88]", + "ldp x16, x17, [x28, #104]", + "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsin": { - "ExpectedInstructionCount": 54, + "ExpectedInstructionCount": 58, "Comment": [ "0xd9 11b 0xfe /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3233,6 +3273,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3246,8 +3288,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1456]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1472]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3269,22 +3311,24 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "mov w21, #0x0", "strb w21, [x28, #746]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcos": { - "ExpectedInstructionCount": 54, + "ExpectedInstructionCount": 58, "Comment": [ "0xd9 11b 0xff /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -3295,6 +3339,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -3308,8 +3354,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1464]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1480]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -3331,11 +3377,13 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "mov w21, #0x0", "strb w21, [x28, #746]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fiadd dword [rax]": { @@ -3348,10 +3396,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fimul dword [rax]": { @@ -3364,10 +3412,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "ficom dword [rax]": { @@ -3380,7 +3428,7 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -3412,7 +3460,7 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -3431,11 +3479,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -3452,10 +3500,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fisubr dword [rax]": { @@ -3468,10 +3516,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fidiv dword [rax]": { @@ -3484,10 +3532,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fidivr dword [rax]": { @@ -3500,10 +3548,10 @@ "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcmovb st0, st0": { @@ -3518,12 +3566,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st1": { @@ -3538,12 +3586,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st2": { @@ -3558,12 +3606,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st3": { @@ -3578,12 +3626,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st4": { @@ -3598,12 +3646,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st5": { @@ -3618,12 +3666,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st6": { @@ -3638,12 +3686,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovb st0, st7": { @@ -3658,12 +3706,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st0": { @@ -3678,12 +3726,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st1": { @@ -3698,12 +3746,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st2": { @@ -3718,12 +3766,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st3": { @@ -3738,12 +3786,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st4": { @@ -3758,12 +3806,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st5": { @@ -3778,12 +3826,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st6": { @@ -3798,12 +3846,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmove st0, st7": { @@ -3818,12 +3866,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st0": { @@ -3840,12 +3888,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st1": { @@ -3862,12 +3910,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st2": { @@ -3884,12 +3932,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st3": { @@ -3906,12 +3954,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st4": { @@ -3928,12 +3976,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st5": { @@ -3950,12 +3998,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st6": { @@ -3972,12 +4020,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovbe st0, st7": { @@ -3994,22 +4042,21 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovu st0, st0": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xd8 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4020,23 +4067,22 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xd9 /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4047,23 +4093,22 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st2": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xda /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4074,23 +4119,22 @@ "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st3": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdb /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4101,23 +4145,22 @@ "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st4": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdc /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4128,23 +4171,22 @@ "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st5": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdd /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4155,23 +4197,22 @@ "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st6": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xde /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4182,23 +4223,22 @@ "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovu st0, st7": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xda 11b 0xdf /1" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4209,12 +4249,12 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, @@ -4229,9 +4269,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -4250,15 +4290,15 @@ "strb w24, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w24, w21, w20", "bic w23, w23, w24", - "strb w23, [x28, #1010]", + "strb w23, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -4275,15 +4315,15 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr w21, [x4]", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fisttp dword [rax]": { @@ -4294,14 +4334,14 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fcvtzs w21, d2", "str w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4315,7 +4355,7 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "frinti d0, d2", "fcvtzs w20, d0", "str w20, [x4]" @@ -4329,22 +4369,22 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "frinti d0, d2", "fcvtzs w21, d0", "str w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fld tword [rax]": { - "ExpectedInstructionCount": 60, + "ExpectedInstructionCount": 64, "Comment": [ "0xdb !11b /5" ], @@ -4361,6 +4401,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4373,10 +4415,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4398,28 +4440,30 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fstp tword [rax]": { - "ExpectedInstructionCount": 63, + "ExpectedInstructionCount": 67, "Comment": [ "0xdb !11b /7" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -4430,6 +4474,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -4443,8 +4489,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -4466,17 +4512,19 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -4494,12 +4542,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st1": { @@ -4514,12 +4562,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st2": { @@ -4534,12 +4582,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st3": { @@ -4554,12 +4602,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st4": { @@ -4574,12 +4622,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st5": { @@ -4594,12 +4642,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st6": { @@ -4614,12 +4662,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnb st0, st7": { @@ -4634,12 +4682,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st0": { @@ -4654,12 +4702,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st1": { @@ -4674,12 +4722,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st2": { @@ -4694,12 +4742,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st3": { @@ -4714,12 +4762,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st4": { @@ -4734,12 +4782,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st5": { @@ -4754,12 +4802,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st6": { @@ -4774,12 +4822,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovne st0, st7": { @@ -4794,12 +4842,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st0": { @@ -4815,12 +4863,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st1": { @@ -4836,12 +4884,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st2": { @@ -4857,12 +4905,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st3": { @@ -4878,12 +4926,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st4": { @@ -4899,12 +4947,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st5": { @@ -4920,12 +4968,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st6": { @@ -4941,12 +4989,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnbe st0, st7": { @@ -4962,22 +5010,21 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x21, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fcmovnu st0, st0": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xd8 /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -4988,23 +5035,22 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xd9 /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5015,23 +5061,22 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st2": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xda /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5042,23 +5087,22 @@ "add w22, w20, #0x2 (2)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st3": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdb /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5069,23 +5113,22 @@ "add w22, w20, #0x3 (3)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st4": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdc /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5096,23 +5139,22 @@ "add w22, w20, #0x4 (4)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st5": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdd /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5123,23 +5165,22 @@ "add w22, w20, #0x5 (5)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st6": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xde /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5150,23 +5191,22 @@ "add w22, w20, #0x6 (6)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, "fcmovnu st0, st7": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdb 11b 0xdf /3" ], "ExpectedArm64ASM": [ - "ldrb w20, [x28, #706]", - "fmov s2, w20", + "fmov s2, w26", "cnt v2.16b, v2.16b", "umov w20, v2.b[0]", "mrs x21, nzcv", @@ -5177,12 +5217,12 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q3, [x0, #752]", + "ldr q3, [x0, #768]", "add x0, x28, x22, lsl #4", - "ldr q4, [x0, #752]", + "ldr q4, [x0, #768]", "bsl v2.16b, v4.16b, v3.16b", "add x0, x28, x20, lsl #4", - "str q2, [x0, #752]", + "str q2, [x0, #768]", "msr nzcv, x21" ] }, @@ -5208,17 +5248,17 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1010]" + "strb w21, [x28, #1026]" ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xe8 /5" ], @@ -5227,9 +5267,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5244,13 +5284,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xe9 /5" ], @@ -5259,9 +5298,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5276,13 +5315,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st2": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xea /5" ], @@ -5291,9 +5329,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5308,13 +5346,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st3": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xeb /5" ], @@ -5323,9 +5360,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5340,13 +5377,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st4": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xec /5" ], @@ -5355,9 +5391,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5372,13 +5408,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st5": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xed /5" ], @@ -5387,9 +5422,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5404,13 +5439,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st6": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xee /5" ], @@ -5419,9 +5453,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5436,13 +5470,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fucomi st0, st7": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xef /5" ], @@ -5451,9 +5484,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5468,13 +5501,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf0 /6" ], @@ -5483,9 +5515,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5500,13 +5532,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st1": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf1 /6" ], @@ -5515,9 +5546,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5532,13 +5563,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st2": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf2 /6" ], @@ -5547,9 +5577,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5564,13 +5594,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st3": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf3 /6" ], @@ -5579,9 +5608,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5596,13 +5625,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st4": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf4 /6" ], @@ -5611,9 +5639,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5628,13 +5656,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st5": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf5 /6" ], @@ -5643,9 +5670,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5660,13 +5687,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st6": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf6 /6" ], @@ -5675,9 +5701,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5692,13 +5718,12 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, "fcomi st0, st7": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": [ "0xdb 11b 0xf7 /6" ], @@ -5707,9 +5732,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x20, eq", "csinc x20, x20, xzr, vc", @@ -5724,8 +5749,7 @@ "orr w22, w22, w20", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", - "eor w20, w20, #0x1", - "strb w20, [x28, #706]", + "eor w26, w20, #0x1", "msr nzcv, x21" ] }, @@ -5738,10 +5762,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul qword [rax]": { @@ -5753,10 +5777,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcom qword [rax]": { @@ -5768,7 +5792,7 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -5799,7 +5823,7 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -5818,11 +5842,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -5838,10 +5862,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr qword [rax]": { @@ -5853,10 +5877,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv qword [rax]": { @@ -5868,10 +5892,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr qword [rax]": { @@ -5883,10 +5907,10 @@ "ldrb w20, [x28, #747]", "ldr d2, [x4]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xc0": { @@ -5901,12 +5925,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st1, st0": { @@ -5919,12 +5943,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st2, st0": { @@ -5937,12 +5961,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st3, st0": { @@ -5955,12 +5979,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st4, st0": { @@ -5973,12 +5997,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st5, st0": { @@ -5991,12 +6015,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st6, st0": { @@ -6009,12 +6033,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fadd st7, st0": { @@ -6027,12 +6051,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xc8": { @@ -6047,12 +6071,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st1, st0": { @@ -6065,12 +6089,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st2, st0": { @@ -6083,12 +6107,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st3, st0": { @@ -6101,12 +6125,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st4, st0": { @@ -6119,12 +6143,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st5, st0": { @@ -6137,12 +6161,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st6, st0": { @@ -6155,12 +6179,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmul st7, st0": { @@ -6173,12 +6197,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xe0": { @@ -6193,12 +6217,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st1, st0": { @@ -6211,12 +6235,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st2, st0": { @@ -6229,12 +6253,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st3, st0": { @@ -6247,12 +6271,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st4, st0": { @@ -6265,12 +6289,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st5, st0": { @@ -6283,12 +6307,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st6, st0": { @@ -6301,12 +6325,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubr st7, st0": { @@ -6319,12 +6343,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xe8": { @@ -6339,12 +6363,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st1, st0": { @@ -6357,12 +6381,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st2, st0": { @@ -6375,12 +6399,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st3, st0": { @@ -6393,12 +6417,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st4, st0": { @@ -6411,12 +6435,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st5, st0": { @@ -6429,12 +6453,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st6, st0": { @@ -6447,12 +6471,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsub st7, st0": { @@ -6465,12 +6489,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xf0": { @@ -6485,12 +6509,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st1, st0": { @@ -6503,12 +6527,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st2, st0": { @@ -6521,12 +6545,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st3, st0": { @@ -6539,12 +6563,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st4, st0": { @@ -6557,12 +6581,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st5, st0": { @@ -6575,12 +6599,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st6, st0": { @@ -6593,12 +6617,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivr st7, st0": { @@ -6611,12 +6635,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xdc, 0xf8": { @@ -6631,12 +6655,12 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st1, st0": { @@ -6649,12 +6673,12 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st2, st0": { @@ -6667,12 +6691,12 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st3, st0": { @@ -6685,12 +6709,12 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st4, st0": { @@ -6703,12 +6727,12 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st5, st0": { @@ -6721,12 +6745,12 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st6, st0": { @@ -6739,12 +6763,12 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdiv st7, st0": { @@ -6757,12 +6781,12 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fld qword [rax]": { @@ -6776,13 +6800,13 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fisttp qword [rax]": { @@ -6793,14 +6817,14 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fcvtzs x21, d2", "str x21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -6814,7 +6838,7 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "str d2, [x4]" ] }, @@ -6826,20 +6850,20 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "str d2, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "frstor [rax]": { - "ExpectedInstructionCount": 501, + "ExpectedInstructionCount": 533, "Comment": [ "0xdd !11b /4" ], @@ -6854,8 +6878,8 @@ "lsr x1, x21, #2", "bfi x0, x1, #24, #1", "msr fpcr, x0", - "strh w20, [x28, #1008]", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", + "strh w20, [x28, #1024]", "ldr w20, [x4, #4]", "ubfx w21, w20, #11, #3", "strb w21, [x28, #747]", @@ -6900,7 +6924,7 @@ "cmp x20, #0x3 (3)", "cset x20, ne", "orr w20, w22, w20, lsl #7", - "strb w20, [x28, #1010]", + "strb w20, [x28, #1026]", "add x20, x4, #0x1c (28)", "mov x22, #0xffffffffffffffff", "mov w24, #0xffff", @@ -6918,6 +6942,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -6930,10 +6956,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -6955,9 +6981,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -6973,6 +7001,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -6985,10 +7015,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7010,9 +7040,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7028,6 +7060,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7040,10 +7074,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7065,9 +7099,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7083,6 +7119,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7095,10 +7133,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7120,9 +7158,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7138,6 +7178,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7150,10 +7192,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7175,9 +7217,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7193,6 +7237,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7205,10 +7251,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v3.d[0]", "umov w2, v3.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7230,9 +7276,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v3.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d3, [x0, #752]", + "str d3, [x0, #768]", "add x20, x22, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7248,6 +7296,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7260,10 +7310,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7285,9 +7335,11 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]", + "str d2, [x0, #768]", "add x22, x20, #0xa (10)", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", @@ -7304,6 +7356,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7316,10 +7370,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7341,20 +7395,22 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]", + "str d2, [x0, #768]", "msr nzcv, x23" ] }, "fnsave [rax]": { - "ExpectedInstructionCount": 511, + "ExpectedInstructionCount": 543, "Comment": [ "0xdd !11b /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", - "ldrh w21, [x28, #1008]", + "ldrh w21, [x28, #1024]", "str w21, [x4]", "mov w21, #0x0", "mov x22, x21", @@ -7362,49 +7418,49 @@ "ldrb w23, [x28, #744]", "ldrb w24, [x28, #745]", "ldrb w25, [x28, #746]", - "ldrb w26, [x28, #750]", + "ldrb w30, [x28, #750]", "orr x22, x22, x23, lsl #8", "orr x22, x22, x24, lsl #9", "orr x22, x22, x25, lsl #10", - "orr x22, x22, x26, lsl #14", + "orr x22, x22, x30, lsl #14", "str w22, [x4, #4]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "and w23, w22, #0x1", "mov w24, #0x3", "mrs x25, nzcv", "cmp x23, #0x0 (0)", "csel x23, x24, x21, eq", "orr w23, w21, w23", - "lsr w26, w22, #1", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #2", - "lsr w26, w22, #2", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #4", - "lsr w26, w22, #3", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #6", - "lsr w26, w22, #4", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #8", - "lsr w26, w22, #5", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #10", - "lsr w26, w22, #6", - "and w26, w26, #0x1", - "cmp x26, #0x0 (0)", - "csel x26, x24, x21, eq", - "orr w23, w23, w26, lsl #12", + "lsr w30, w22, #1", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #2", + "lsr w30, w22, #2", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #4", + "lsr w30, w22, #3", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #6", + "lsr w30, w22, #4", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #8", + "lsr w30, w22, #5", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #10", + "lsr w30, w22, #6", + "and w30, w30, #0x1", + "cmp x30, #0x0 (0)", + "csel x30, x24, x21, eq", + "orr w23, w23, w30, lsl #12", "lsr w22, w22, #7", "and w22, w22, #0x1", "cmp x22, #0x0 (0)", @@ -7417,7 +7473,7 @@ "str w21, [x4, #24]", "add x22, x4, #0x1c (28)", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7428,6 +7484,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7441,8 +7499,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7464,6 +7522,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7472,7 +7532,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7483,6 +7543,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7496,8 +7558,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7519,6 +7581,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7527,7 +7591,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7538,6 +7602,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7551,8 +7617,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7574,6 +7640,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7582,7 +7650,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7593,6 +7661,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7606,8 +7676,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7629,6 +7699,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7637,7 +7709,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7648,6 +7720,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7661,8 +7735,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7684,6 +7758,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7692,7 +7768,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7703,6 +7779,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7716,8 +7794,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7739,6 +7817,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7747,7 +7827,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7758,6 +7838,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7771,8 +7853,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7794,6 +7876,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7802,7 +7886,7 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -7813,6 +7897,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -7826,8 +7912,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -7849,6 +7935,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -7856,13 +7944,13 @@ "dup v2.8h, v2.h[4]", "str h2, [x23, #8]", "mov w20, #0x37f", - "strh w20, [x28, #1008]", + "strh w20, [x28, #1024]", "strb w21, [x28, #747]", "strb w21, [x28, #744]", "strb w21, [x28, #745]", "strb w21, [x28, #746]", "strb w21, [x28, #750]", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "msr nzcv, x25" ] }, @@ -7895,11 +7983,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x0 (0)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st1": { @@ -7912,10 +8000,10 @@ "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w20, w21, w20", "bic w20, w22, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st2": { @@ -7927,11 +8015,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x2 (2)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st3": { @@ -7943,11 +8031,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x3 (3)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st4": { @@ -7959,11 +8047,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x4 (4)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st5": { @@ -7975,11 +8063,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x5 (5)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st6": { @@ -7991,11 +8079,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x6 (6)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "ffree st7": { @@ -8007,11 +8095,11 @@ "ldrb w20, [x28, #747]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w20, w22, w20", "bic w20, w21, w20", - "strb w20, [x28, #1010]" + "strb w20, [x28, #1026]" ] }, "fst st0": { @@ -8024,9 +8112,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st1": { @@ -8039,9 +8127,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st2": { @@ -8054,9 +8142,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st3": { @@ -8069,9 +8157,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st4": { @@ -8084,9 +8172,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st5": { @@ -8099,9 +8187,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st6": { @@ -8114,9 +8202,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fst st7": { @@ -8129,9 +8217,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]" + "str q2, [x0, #768]" ] }, "fstp st0": { @@ -8144,14 +8232,14 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8168,13 +8256,13 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x22, lsl #4", - "str q2, [x0, #752]", - "ldrb w22, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8190,14 +8278,14 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8213,14 +8301,14 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8236,14 +8324,14 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8259,14 +8347,14 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8282,14 +8370,14 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8305,14 +8393,14 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x20, lsl #4", - "ldr q2, [x0, #752]", + "ldr q2, [x0, #768]", "add x0, x28, x21, lsl #4", - "str q2, [x0, #752]", - "ldrb w21, [x28, #1010]", + "str q2, [x0, #768]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -8329,9 +8417,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8362,9 +8450,9 @@ "add w21, w20, #0x1 (1)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8396,9 +8484,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8430,9 +8518,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8464,9 +8552,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8498,9 +8586,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8532,9 +8620,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8566,9 +8654,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -8601,9 +8689,9 @@ "add w22, w20, #0x0 (0)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -8621,11 +8709,11 @@ "strb w21, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8643,9 +8731,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -8664,10 +8752,10 @@ "strb w24, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8684,9 +8772,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8705,11 +8793,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8726,9 +8814,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8747,11 +8835,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8768,9 +8856,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8789,11 +8877,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8810,9 +8898,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8831,11 +8919,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8852,9 +8940,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8873,11 +8961,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8894,9 +8982,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -8915,11 +9003,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -8937,10 +9025,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fimul word [rax]": { @@ -8954,10 +9042,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "ficom word [rax]": { @@ -8971,7 +9059,7 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x20, nzcv", "fcmp d3, d2", "cset x21, eq", @@ -9004,7 +9092,7 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x21, nzcv", "fcmp d3, d2", "cset x22, eq", @@ -9023,11 +9111,11 @@ "strb w23, [x28, #745]", "strb w22, [x28, #746]", "strb w24, [x28, #750]", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9045,10 +9133,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fisubr word [rax]": { @@ -9062,10 +9150,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fidiv word [rax]": { @@ -9079,10 +9167,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fidivr word [rax]": { @@ -9096,10 +9184,10 @@ "sxth x21, w21", "scvtf d2, w21", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st0": { @@ -9112,20 +9200,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st1": { @@ -9139,19 +9227,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st2": { @@ -9164,20 +9252,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st3": { @@ -9190,20 +9278,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st4": { @@ -9216,20 +9304,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st5": { @@ -9242,20 +9330,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st6": { @@ -9268,20 +9356,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "faddp st7": { @@ -9294,20 +9382,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fadd d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st0": { @@ -9320,20 +9408,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st1": { @@ -9347,19 +9435,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st2": { @@ -9372,20 +9460,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st3": { @@ -9398,20 +9486,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st4": { @@ -9424,20 +9512,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st5": { @@ -9450,20 +9538,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st6": { @@ -9476,20 +9564,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fmulp st7": { @@ -9502,20 +9590,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fmul d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fcompp": { @@ -9529,9 +9617,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "mrs x22, nzcv", "fcmp d3, d2", "cset x23, eq", @@ -9550,15 +9638,15 @@ "strb w24, [x28, #745]", "strb w23, [x28, #746]", "strb w25, [x28, #750]", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w24, w21, w20", "bic w23, w23, w24", - "strb w23, [x28, #1010]", + "strb w23, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -9577,20 +9665,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st1, st0": { @@ -9604,19 +9692,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st2, st0": { @@ -9629,20 +9717,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st3, st0": { @@ -9655,20 +9743,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st4, st0": { @@ -9681,20 +9769,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st5, st0": { @@ -9707,20 +9795,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st6, st0": { @@ -9733,20 +9821,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubrp st7, st0": { @@ -9759,20 +9847,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xde, 0xe8": { @@ -9787,20 +9875,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st1, st0": { @@ -9814,19 +9902,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st2, st0": { @@ -9839,20 +9927,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st3, st0": { @@ -9865,20 +9953,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st4, st0": { @@ -9891,20 +9979,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st5, st0": { @@ -9917,20 +10005,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st6, st0": { @@ -9943,20 +10031,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fsubp st7, st0": { @@ -9969,20 +10057,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fsub d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xde, 0xf0": { @@ -9997,20 +10085,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st1, st0": { @@ -10024,19 +10112,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st2, st0": { @@ -10049,20 +10137,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st3, st0": { @@ -10075,20 +10163,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st4, st0": { @@ -10101,20 +10189,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st5, st0": { @@ -10127,20 +10215,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st6, st0": { @@ -10153,20 +10241,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivrp st7, st0": { @@ -10179,20 +10267,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d3, d2", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "db 0xde, 0xf8": { @@ -10207,20 +10295,20 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st1, st0": { @@ -10234,19 +10322,19 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w23, [x28, #1010]", + "ldrb w23, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w23, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x22, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st2, st0": { @@ -10259,20 +10347,20 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st3, st0": { @@ -10285,20 +10373,20 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st4, st0": { @@ -10311,20 +10399,20 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st5, st0": { @@ -10337,20 +10425,20 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st6, st0": { @@ -10363,20 +10451,20 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fdivp st7, st0": { @@ -10389,20 +10477,20 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fdiv d2, d2, d3", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "mov w23, #0x1", "lsl w23, w23, w20", "bic w22, w22, w23", - "strb w22, [x28, #1010]", + "strb w22, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", "add x0, x28, x21, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fild word [rax]": { @@ -10415,16 +10503,16 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldrh w21, [x4]", "sxth x21, w21", "scvtf d2, x21", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fisttp word [rax]": { @@ -10435,14 +10523,14 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "fcvtzs x21, d2", "strh w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10456,7 +10544,7 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "frinti d0, d2", "fcvtzs x20, d0", "strh w20, [x4]" @@ -10470,22 +10558,22 @@ "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "frinti d0, d2", "fcvtzs x21, d0", "strh w21, [x4]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" ] }, "fbld tword [rax]": { - "ExpectedInstructionCount": 110, + "ExpectedInstructionCount": 118, "Comment": [ "0xdf !11b /4" ], @@ -10494,10 +10582,10 @@ "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1010]", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "orr w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "strb w20, [x28, #747]", "ldr q2, [x4]", "mrs x0, nzcv", @@ -10510,6 +10598,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10522,10 +10612,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1376]", + "ldr x3, [x28, #1392]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10547,6 +10637,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -10560,6 +10652,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10572,10 +10666,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1168]", + "ldr x3, [x28, #1184]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10597,20 +10691,22 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "mov v2.8b, v0.8b", "add x0, x28, x20, lsl #4", - "str d2, [x0, #752]" + "str d2, [x0, #768]" ] }, "fbstp tword [rax]": { - "ExpectedInstructionCount": 113, + "ExpectedInstructionCount": 121, "Comment": [ "0xdf !11b /6" ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #747]", "add x0, x28, x20, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "mrs x0, nzcv", "str w0, [x28, #728]", "stp x4, x5, [x28, #8]", @@ -10621,6 +10717,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10634,8 +10732,8 @@ "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", "mov v0.8b, v2.8b", - "ldrh w0, [x28, #1008]", - "ldr x1, [x28, #1152]", + "ldrh w0, [x28, #1024]", + "ldr x1, [x28, #1168]", "blr x1", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10657,6 +10755,8 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", @@ -10670,6 +10770,8 @@ "stp x14, x15, [x28, #88]", "stp x16, x17, [x28, #104]", "stp x19, x29, [x28, #120]", + "str x26, [x28, #752]", + "str x27, [x28, #760]", "add x0, x28, #0xc0 (192)", "st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64", "st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64", @@ -10682,10 +10784,10 @@ "st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64", "st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64", "str x30, [x0]", - "ldrh w0, [x28, #1008]", + "ldrh w0, [x28, #1024]", "mov x1, v2.d[0]", "umov w2, v2.h[4]", - "ldr x3, [x28, #1368]", + "ldr x3, [x28, #1384]", "blr x3", "ld1 {v2.2d, v3.2d}, [sp], #32", "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", @@ -10707,17 +10809,19 @@ "ldp x14, x15, [x28, #88]", "ldp x16, x17, [x28, #104]", "ldp x19, x29, [x28, #120]", + "ldr x26, [x28, #752]", + "ldr x27, [x28, #760]", "eor v2.16b, v2.16b, v2.16b", "mov v2.d[0], x0", "mov v2.h[4], w1", "str d2, [x4]", "mov x21, v2.d[1]", "strh w21, [x4, #8]", - "ldrb w21, [x28, #1010]", + "ldrb w21, [x28, #1026]", "mov w22, #0x1", "lsl w22, w22, w20", "bic w21, w21, w22", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]" @@ -10840,7 +10944,7 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xe8 /5" ], @@ -10849,9 +10953,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -10867,12 +10971,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10880,7 +10983,7 @@ ] }, "fucomip st1": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xe9 /5" ], @@ -10890,9 +10993,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x22, eq", "csinc x22, x22, xzr, vc", @@ -10907,12 +11010,11 @@ "orr w24, w24, w22", "lsl x23, x23, #29", "orr w23, w23, w24, lsl #30", - "eor w22, w22, #0x1", - "strb w22, [x28, #706]", - "ldrb w22, [x28, #1010]", + "eor w26, w22, #0x1", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10920,7 +11022,7 @@ ] }, "fucomip st2": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xea /5" ], @@ -10929,9 +11031,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -10947,12 +11049,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -10960,7 +11061,7 @@ ] }, "fucomip st3": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xeb /5" ], @@ -10969,9 +11070,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -10987,12 +11088,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11000,7 +11100,7 @@ ] }, "fucomip st4": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xec /5" ], @@ -11009,9 +11109,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11027,12 +11127,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11040,7 +11139,7 @@ ] }, "fucomip st5": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xed /5" ], @@ -11049,9 +11148,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11067,12 +11166,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11080,7 +11178,7 @@ ] }, "fucomip st6": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xee /5" ], @@ -11089,9 +11187,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11107,12 +11205,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11120,7 +11217,7 @@ ] }, "fucomip st7": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xef /5" ], @@ -11129,9 +11226,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11147,12 +11244,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11160,7 +11256,7 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf0 /6" ], @@ -11169,9 +11265,9 @@ "add w21, w20, #0x0 (0)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11187,12 +11283,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11200,7 +11295,7 @@ ] }, "fcomip st1": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf1 /6" ], @@ -11210,9 +11305,9 @@ "add w22, w20, #0x1 (1)", "and w22, w22, #0x7", "add x0, x28, x22, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x22, eq", "csinc x22, x22, xzr, vc", @@ -11227,12 +11322,11 @@ "orr w24, w24, w22", "lsl x23, x23, #29", "orr w23, w23, w24, lsl #30", - "eor w22, w22, #0x1", - "strb w22, [x28, #706]", - "ldrb w22, [x28, #1010]", + "eor w26, w22, #0x1", + "ldrb w22, [x28, #1026]", "lsl w21, w21, w20", "bic w21, w22, w21", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11240,7 +11334,7 @@ ] }, "fcomip st2": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf2 /6" ], @@ -11249,9 +11343,9 @@ "add w21, w20, #0x2 (2)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11267,12 +11361,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11280,7 +11373,7 @@ ] }, "fcomip st3": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf3 /6" ], @@ -11289,9 +11382,9 @@ "add w21, w20, #0x3 (3)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11307,12 +11400,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11320,7 +11412,7 @@ ] }, "fcomip st4": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf4 /6" ], @@ -11329,9 +11421,9 @@ "add w21, w20, #0x4 (4)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11347,12 +11439,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11360,7 +11451,7 @@ ] }, "fcomip st5": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf5 /6" ], @@ -11369,9 +11460,9 @@ "add w21, w20, #0x5 (5)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11387,12 +11478,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11400,7 +11490,7 @@ ] }, "fcomip st6": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf6 /6" ], @@ -11409,9 +11499,9 @@ "add w21, w20, #0x6 (6)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11427,12 +11517,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]", @@ -11440,7 +11529,7 @@ ] }, "fcomip st7": { - "ExpectedInstructionCount": 32, + "ExpectedInstructionCount": 31, "Comment": [ "0xdf 11b 0xf7 /6" ], @@ -11449,9 +11538,9 @@ "add w21, w20, #0x7 (7)", "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", - "ldr d2, [x0, #752]", + "ldr d2, [x0, #768]", "add x0, x28, x20, lsl #4", - "ldr d3, [x0, #752]", + "ldr d3, [x0, #768]", "fcmp d3, d2", "cset x21, eq", "csinc x21, x21, xzr, vc", @@ -11467,12 +11556,11 @@ "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", - "eor w21, w21, #0x1", - "strb w21, [x28, #706]", - "ldrb w21, [x28, #1010]", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1026]", "lsl w23, w23, w20", "bic w21, w21, w23", - "strb w21, [x28, #1010]", + "strb w21, [x28, #1026]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #747]",