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FEX-Emu--FEX/unittests/InstructionCountCI/Atomics.json
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Alyssa Rosenzweig cea551c2ac InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-17 17:37:24 -04:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"FLAGM",
"FLAGM2"
]
},
"Instructions": {
"lock add byte [rax], cl": {
"ExpectedInstructionCount": 14,
"Comment": "0x00",
"ExpectedArm64ASM": [
"uxtb w20, w5",
"ldaddalb w20, w21, [x4]",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"ubfx x23, x26, #8, #1",
"orr w22, w22, w23, lsl #29",
"eor w20, w21, w20",
"eor w21, w26, w21",
"bic w20, w21, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock add word [rax], cx": {
"ExpectedInstructionCount": 14,
"Comment": "0x01",
"ExpectedArm64ASM": [
"uxth w20, w5",
"ldaddalh w20, w21, [x4]",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"ubfx x23, x26, #16, #1",
"orr w22, w22, w23, lsl #29",
"eor w20, w21, w20",
"eor w21, w26, w21",
"bic w20, w21, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock add dword [rax], ecx": {
"ExpectedInstructionCount": 4,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddal w5, w20, [x4]",
"add w26, w20, w5",
"eor w27, w20, w5",
"cmn w20, w5"
]
},
"lock or byte [rax], cl": {
"ExpectedInstructionCount": 3,
"Comment": "0x08",
"ExpectedArm64ASM": [
"ldsetalb w5, w20, [x4]",
"orr w26, w20, w5",
"cmn wzr, w26, lsl #24"
]
},
"lock or word [rax], cx": {
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetalh w5, w20, [x4]",
"orr w26, w20, w5",
"cmn wzr, w26, lsl #16"
]
},
"lock or dword [rax], ecx": {
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetal w5, w20, [x4]",
"orr w26, w20, w5",
"tst w26, w26"
]
},
"lock adc byte [rax], cl": {
"ExpectedInstructionCount": 22,
"Comment": "0x10",
"ExpectedArm64ASM": [
"uxtb w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"ldaddalb w22, w23, [x4]",
"add w22, w23, w22",
"uxtb w26, w22",
"eor w27, w23, w20",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp w26, w20",
"cset x24, lo",
"cmp w26, w20",
"cset x25, ls",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"bic w20, w22, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock adc word [rax], cx": {
"ExpectedInstructionCount": 22,
"Comment": "0x11",
"ExpectedArm64ASM": [
"uxth w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"ldaddalh w22, w23, [x4]",
"add w22, w23, w22",
"uxth w26, w22",
"eor w27, w23, w20",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp w26, w20",
"cset x24, lo",
"cmp w26, w20",
"cset x25, ls",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"bic w20, w22, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock adc dword [rax], ecx": {
"ExpectedInstructionCount": 7,
"Comment": "0x11",
"ExpectedArm64ASM": [
"mov w20, w5",
"cset w21, hs",
"add w21, w20, w21",
"ldaddal w21, w22, [x4]",
"add w26, w22, w21",
"eor w27, w22, w20",
"adcs wzr, w22, w20"
]
},
"lock sbb byte [rax], cl": {
"ExpectedInstructionCount": 23,
"Comment": "0x18",
"ExpectedArm64ASM": [
"uxtb w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"neg w1, w22",
"ldaddalb w1, w23, [x4]",
"sub w22, w23, w22",
"uxtb w26, w22",
"eor w27, w23, w20",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb word [rax], cx": {
"ExpectedInstructionCount": 23,
"Comment": "0x19",
"ExpectedArm64ASM": [
"uxth w20, w5",
"cset w21, hs",
"add w22, w20, w21",
"neg w1, w22",
"ldaddalh w1, w23, [x4]",
"sub w22, w23, w22",
"uxth w26, w22",
"eor w27, w23, w20",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp w26, w23",
"cset x24, hi",
"cmp w26, w23",
"cset x25, hs",
"cmp x21, #0x1 (1)",
"csel x21, x25, x24, eq",
"orr w21, w22, w21, lsl #29",
"eor w20, w23, w20",
"eor w22, w26, w23",
"and w20, w22, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], ecx": {
"ExpectedInstructionCount": 14,
"Comment": "0x19",
"ExpectedArm64ASM": [
"mov w20, w5",
"cset w21, hs",
"add w21, w20, w21",
"neg w1, w21",
"ldaddal w1, w22, [x4]",
"sub w26, w22, w21",
"eor w27, w22, w20",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w22, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock and byte [rax], cl": {
"ExpectedInstructionCount": 4,
"Comment": "0x20",
"ExpectedArm64ASM": [
"mvn w1, w5",
"ldclralb w1, w20, [x4]",
"and w26, w20, w5",
"cmn wzr, w26, lsl #24"
]
},
"lock and word [rax], cx": {
"ExpectedInstructionCount": 4,
"Comment": "0x21",
"ExpectedArm64ASM": [
"mvn w1, w5",
"ldclralh w1, w20, [x4]",
"and w26, w20, w5",
"cmn wzr, w26, lsl #16"
]
},
"lock and dword [rax], ecx": {
"ExpectedInstructionCount": 4,
"Comment": "0x21",
"ExpectedArm64ASM": [
"mvn w1, w5",
"ldclral w1, w20, [x4]",
"and w26, w20, w5",
"tst w26, w26"
]
},
"lock sub byte [rax], cl": {
"ExpectedInstructionCount": 15,
"Comment": "0x28",
"ExpectedArm64ASM": [
"uxtb w20, w5",
"neg w1, w20",
"ldaddalb w1, w21, [x4]",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"ubfx x23, x26, #8, #1",
"orr w22, w22, w23, lsl #29",
"eor w20, w21, w20",
"eor w21, w26, w21",
"and w20, w21, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sub word [rax], cx": {
"ExpectedInstructionCount": 15,
"Comment": "0x28",
"ExpectedArm64ASM": [
"uxth w20, w5",
"neg w1, w20",
"ldaddalh w1, w21, [x4]",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"ubfx x23, x26, #16, #1",
"orr w22, w22, w23, lsl #29",
"eor w20, w21, w20",
"eor w21, w26, w21",
"and w20, w21, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sub dword [rax], ecx": {
"ExpectedInstructionCount": 8,
"Comment": "0x29",
"ExpectedArm64ASM": [
"neg w1, w5",
"ldaddal w1, w20, [x4]",
"sub w26, w20, w5",
"eor w27, w20, w5",
"cmp w20, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock xor byte [rax], cl": {
"ExpectedInstructionCount": 3,
"Comment": "0x30",
"ExpectedArm64ASM": [
"ldeoralb w5, w20, [x4]",
"eor w26, w20, w5",
"cmn wzr, w26, lsl #24"
]
},
"lock xor word [rax], cx": {
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoralh w5, w20, [x4]",
"eor w26, w20, w5",
"cmn wzr, w26, lsl #16"
]
},
"lock xor dword [rax], ecx": {
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoral w5, w20, [x4]",
"eor w26, w20, w5",
"tst w26, w26"
]
},
"lock add qword [rax], rcx": {
"ExpectedInstructionCount": 4,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddal x5, x20, [x4]",
"add x26, x20, x5",
"eor x27, x20, x5",
"cmn x20, x5"
]
},
"xchg byte [rax], cl": {
"ExpectedInstructionCount": 4,
"Comment": "0x86",
"ExpectedArm64ASM": [
"uxtb w20, w5",
"mov w1, w20",
"swpalb w1, w20, [x4]",
"bfxil x5, x20, #0, #8"
]
},
"xchg word [rax], cx": {
"ExpectedInstructionCount": 4,
"Comment": "0x87",
"ExpectedArm64ASM": [
"uxth w20, w5",
"mov w1, w20",
"swpalh w1, w20, [x4]",
"bfxil x5, x20, #0, #16"
]
},
"xchg dword [rax], ecx": {
"ExpectedInstructionCount": 3,
"Comment": "0x87",
"ExpectedArm64ASM": [
"mov w20, w5",
"mov w1, w20",
"swpal w1, w5, [x4]"
]
},
"xchg qword [rax], rcx": {
"ExpectedInstructionCount": 2,
"Comment": "0x87",
"ExpectedArm64ASM": [
"mov x1, x5",
"swpal x1, x5, [x4]"
]
},
"xadd byte [rax], bl": {
"ExpectedInstructionCount": 15,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"ldaddalb w20, w21, [x4]",
"bfxil x7, x21, #0, #8",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"ubfx x23, x26, #8, #1",
"orr w22, w22, w23, lsl #29",
"eor w20, w21, w20",
"eor w21, w26, w21",
"bic w20, w21, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"xadd word [rax], bx": {
"ExpectedInstructionCount": 15,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ldaddalh w20, w21, [x4]",
"bfxil x7, x21, #0, #16",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"ubfx x23, x26, #16, #1",
"orr w22, w22, w23, lsl #29",
"eor w20, w21, w20",
"eor w21, w26, w21",
"bic w20, w21, w20",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"xadd dword [rax], ebx": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w7",
"ldaddal w20, w7, [x4]",
"add w26, w7, w20",
"eor w27, w7, w20",
"cmn w7, w20"
]
},
"xadd qword [rax], rbx": {
"ExpectedInstructionCount": 5,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov x20, x7",
"ldaddal x20, x7, [x4]",
"add x26, x7, x20",
"eor x27, x7, x20",
"cmn x7, x20"
]
},
"lock add byte [rax], 1": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalb w20, w27, [x4]",
"add w26, w27, #0x1 (1)",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"ubfx x21, x26, #8, #1",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock add byte [rax], 0xFF": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldaddalb w20, w20, [x4]",
"add w26, w20, #0xff (255)",
"eor w27, w20, #0xff",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"ubfx x22, x26, #8, #1",
"orr w21, w21, w22, lsl #29",
"bic w20, w20, w26",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock add word [rax], 0x100": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldaddalh w20, w27, [x4]",
"add w26, w27, #0x100 (256)",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x21, x26, #16, #1",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock add word [rax], 0xFFFF": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldaddalh w20, w21, [x4]",
"add w26, w21, w20",
"eor w27, w21, #0xffff",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x22, x26, #16, #1",
"orr w20, w20, w22, lsl #29",
"bic w21, w21, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock add dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldaddal w20, w27, [x4]",
"add w26, w27, #0x100 (256)",
"cmn w27, #0x100 (256)"
]
},
"lock add dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldaddal w20, w21, [x4]",
"add w26, w21, w20",
"eor w27, w21, w20",
"cmn w21, w20"
]
},
"lock add qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldaddal x20, x27, [x4]",
"add x26, x27, #0x100 (256)",
"cmn x27, #0x100 (256)"
]
},
"lock add qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldaddal x20, x27, [x4]",
"add x26, x27, x20",
"cmn x27, x20"
]
},
"lock add word [rax], 1": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalh w20, w27, [x4]",
"add w26, w27, #0x1 (1)",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x21, x26, #16, #1",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock add dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal w20, w27, [x4]",
"add w26, w27, #0x1 (1)",
"cmn w27, #0x1 (1)"
]
},
"lock add qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal x20, x27, [x4]",
"add x26, x27, #0x1 (1)",
"cmn x27, #0x1 (1)"
]
},
"lock or byte [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x80 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetalb w20, w20, [x4]",
"orr w26, w20, #0x1",
"cmn wzr, w26, lsl #24"
]
},
"lock or byte [rax], 0xFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x80 /1",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldsetalb w20, w20, [x4]",
"orr w26, w20, #0xff",
"cmn wzr, w26, lsl #24"
]
},
"lock or word [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetalh w20, w20, [x4]",
"orr w26, w20, #0x100",
"cmn wzr, w26, lsl #16"
]
},
"lock or word [rax], 0xFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldsetalh w20, w20, [x4]",
"orr w26, w20, #0xffff",
"cmn wzr, w26, lsl #16"
]
},
"lock or dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal w20, w20, [x4]",
"orr w26, w20, #0x100",
"tst w26, w26"
]
},
"lock or dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldsetal w20, w21, [x4]",
"orr w26, w21, w20",
"tst w26, w26"
]
},
"lock or qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0x100",
"tst x26, x26"
]
},
"lock or qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0xffffffff80000001",
"tst x26, x26"
]
},
"lock or word [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetalh w20, w20, [x4]",
"orr w26, w20, #0x1",
"cmn wzr, w26, lsl #16"
]
},
"lock or dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal w20, w20, [x4]",
"orr w26, w20, #0x1",
"tst w26, w26"
]
},
"lock or qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0x1",
"tst x26, x26"
]
},
"lock adc byte [rax], 1": {
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w20, w20, w21",
"ldaddalb w20, w27, [x4]",
"add w20, w27, w20",
"uxtb w26, w20",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock adc byte [rax], 0xFF": {
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"cset w21, hs",
"add w20, w20, w21",
"ldaddalb w20, w22, [x4]",
"add w20, w22, w20",
"uxtb w26, w20",
"eor w27, w22, #0xff",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, #0xff (255)",
"cset x23, lo",
"cmp w26, #0xff (255)",
"cset x24, ls",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w22, w26",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock adc word [rax], 0x100": {
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add w20, w20, w21",
"ldaddalh w20, w27, [x4]",
"add w20, w27, w20",
"uxth w26, w20",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, #0x100 (256)",
"cset x22, lo",
"cmp w26, #0x100 (256)",
"cset x23, ls",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock adc word [rax], 0xFFFF": {
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"cset w21, hs",
"add w22, w20, w21",
"ldaddalh w22, w23, [x4]",
"add w22, w23, w22",
"uxth w26, w22",
"eor w27, w23, #0xffff",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"cmp w26, w20",
"cset x24, lo",
"cmp w26, w20",
"cset x20, ls",
"cmp x21, #0x1 (1)",
"csel x20, x20, x24, eq",
"orr w20, w22, w20, lsl #29",
"bic w21, w23, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock adc dword [rax], 0x100": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add w21, w20, w21",
"ldaddal w21, w27, [x4]",
"add w26, w27, w21",
"adcs wzr, w27, w20"
]
},
"lock adc dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"cset w21, hs",
"add w21, w20, w21",
"ldaddal w21, w22, [x4]",
"add w26, w22, w21",
"eor w27, w22, w20",
"adcs wzr, w22, w20"
]
},
"lock adc qword [rax], 0x100": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add x21, x20, x21",
"ldaddal x21, x27, [x4]",
"add x26, x27, x21",
"adcs xzr, x27, x20"
]
},
"lock adc qword [rax], -2147483647": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"cset w21, hs",
"add x21, x20, x21",
"ldaddal x21, x27, [x4]",
"add x26, x27, x21",
"adcs xzr, x27, x20"
]
},
"lock adc word [rax], 1": {
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w20, w20, w21",
"ldaddalh w20, w27, [x4]",
"add w20, w27, w20",
"uxth w26, w20",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, #0x1 (1)",
"cset x22, lo",
"cmp w26, #0x1 (1)",
"cset x23, ls",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w27",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock adc dword [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w21, w20, w21",
"ldaddal w21, w27, [x4]",
"add w26, w27, w21",
"adcs wzr, w27, w20"
]
},
"lock adc qword [rax], 1": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add x21, x20, x21",
"ldaddal x21, x27, [x4]",
"add x26, x27, x21",
"adcs xzr, x27, x20"
]
},
"lock sbb byte [rax], 1": {
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalb w1, w27, [x4]",
"sub w20, w27, w20",
"uxtb w26, w20",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cmp w26, w27",
"cset x23, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb byte [rax], 0xFF": {
"ExpectedInstructionCount": 21,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalb w1, w22, [x4]",
"sub w20, w22, w20",
"uxtb w26, w20",
"eor w27, w22, #0xff",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb word [rax], 0x100": {
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"sub w20, w27, w20",
"uxth w26, w20",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cmp w26, w27",
"cset x23, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb word [rax], 0xFFFF": {
"ExpectedInstructionCount": 21,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalh w1, w22, [x4]",
"sub w20, w22, w20",
"uxth w26, w20",
"eor w27, w22, #0xffff",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w22",
"cset x23, hi",
"cmp w26, w22",
"cset x24, hs",
"cmp x21, #0x1 (1)",
"csel x21, x24, x23, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w26, w22",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], 0x100": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add w21, w20, w21",
"neg w1, w21",
"ldaddal w1, w27, [x4]",
"sub w26, w27, w21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w27, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"cset w21, hs",
"add w21, w20, w21",
"neg w1, w21",
"ldaddal w1, w22, [x4]",
"sub w26, w22, w21",
"eor w27, w22, w20",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w22, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb qword [rax], 0x100": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"cset w21, hs",
"add x21, x20, x21",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sub x26, x27, x21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb qword [rax], -2147483647": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"cset w21, hs",
"add x21, x20, x21",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sub x26, x27, x21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb word [rax], 1": {
"ExpectedInstructionCount": 20,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w20, w20, w21",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"sub w20, w27, w20",
"uxth w26, w20",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"cmp w26, w27",
"cset x22, hi",
"cmp w26, w27",
"cset x23, hs",
"cmp x21, #0x1 (1)",
"csel x21, x23, x22, eq",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], 1": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add w21, w20, w21",
"neg w1, w21",
"ldaddal w1, w27, [x4]",
"sub w26, w27, w21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs wzr, w27, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb qword [rax], 1": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"cset w21, hs",
"add x21, x20, x21",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"sub x26, x27, x21",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs xzr, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock and byte [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x80 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn w1, w20",
"ldclralb w1, w20, [x4]",
"and w26, w20, #0x1",
"cmn wzr, w26, lsl #24"
]
},
"lock and byte [rax], 0xFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x80 /4",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"mvn w1, w20",
"ldclralb w1, w20, [x4]",
"and w26, w20, #0xff",
"cmn wzr, w26, lsl #24"
]
},
"lock and word [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mvn w1, w20",
"ldclralh w1, w20, [x4]",
"and w26, w20, #0x100",
"cmn wzr, w26, lsl #16"
]
},
"lock and word [rax], 0xFFFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"mvn w1, w20",
"ldclralh w1, w20, [x4]",
"and w26, w20, #0xffff",
"cmn wzr, w26, lsl #16"
]
},
"lock and dword [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mvn w1, w20",
"ldclral w1, w20, [x4]",
"and w26, w20, #0x100",
"tst w26, w26"
]
},
"lock and dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mvn w1, w20",
"ldclral w1, w21, [x4]",
"and w26, w21, w20",
"tst w26, w26"
]
},
"lock and qword [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mvn x1, x20",
"ldclral x1, x20, [x4]",
"and x26, x20, #0x100",
"tst x26, x26"
]
},
"lock and qword [rax], -2147483647": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"mvn x1, x20",
"ldclral x1, x20, [x4]",
"and x26, x20, #0xffffffff80000001",
"tst x26, x26"
]
},
"lock and word [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn w1, w20",
"ldclralh w1, w20, [x4]",
"and w26, w20, #0x1",
"cmn wzr, w26, lsl #16"
]
},
"lock and dword [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn w1, w20",
"ldclral w1, w20, [x4]",
"and w26, w20, #0x1",
"tst w26, w26"
]
},
"lock and qword [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn x1, x20",
"ldclral x1, x20, [x4]",
"and x26, x20, #0x1",
"tst x26, x26"
]
},
"lock sub byte [rax], 1": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalb w1, w27, [x4]",
"sub w26, w27, #0x1 (1)",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"ubfx x21, x26, #8, #1",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sub byte [rax], 0xFF": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"neg w1, w20",
"ldaddalb w1, w20, [x4]",
"sub w26, w20, #0xff (255)",
"eor w27, w20, #0xff",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"ubfx x22, x26, #8, #1",
"orr w21, w21, w22, lsl #29",
"bic w20, w26, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sub word [rax], 0x100": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"sub w26, w27, #0x100 (256)",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x21, x26, #16, #1",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sub word [rax], 0xFFFF": {
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"neg w1, w20",
"ldaddalh w1, w21, [x4]",
"sub w26, w21, w20",
"eor w27, w21, #0xffff",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x22, x26, #16, #1",
"orr w20, w20, w22, lsl #29",
"bic w21, w26, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sub dword [rax], 0x100": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"neg w1, w20",
"ldaddal w1, w27, [x4]",
"sub w26, w27, #0x100 (256)",
"cmp w27, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"neg w1, w20",
"ldaddal w1, w21, [x4]",
"sub w26, w21, w20",
"eor w27, w21, w20",
"cmp w21, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub qword [rax], 0x100": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"sub x26, x27, #0x100 (256)",
"cmp x27, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub qword [rax], -2147483647": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"sub x26, x27, x20",
"cmp x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub word [rax], 1": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"sub w26, w27, #0x1 (1)",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x21, x26, #16, #1",
"orr w20, w20, w21, lsl #29",
"bic w21, w27, w26",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sub dword [rax], 1": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddal w1, w27, [x4]",
"sub w26, w27, #0x1 (1)",
"cmp w27, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub qword [rax], 1": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"sub x26, x27, #0x1 (1)",
"cmp x27, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock xor byte [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x80 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoralb w20, w20, [x4]",
"eor w26, w20, #0x1",
"cmn wzr, w26, lsl #24"
]
},
"lock xor byte [rax], 0xFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x80 /6",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldeoralb w20, w20, [x4]",
"eor w26, w20, #0xff",
"cmn wzr, w26, lsl #24"
]
},
"lock xor word [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoralh w20, w20, [x4]",
"eor w26, w20, #0x100",
"cmn wzr, w26, lsl #16"
]
},
"lock xor word [rax], 0xFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldeoralh w20, w20, [x4]",
"eor w26, w20, #0xffff",
"cmn wzr, w26, lsl #16"
]
},
"lock xor dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral w20, w20, [x4]",
"eor w26, w20, #0x100",
"tst w26, w26"
]
},
"lock xor dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldeoral w20, w21, [x4]",
"eor w26, w21, w20",
"tst w26, w26"
]
},
"lock xor qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0x100",
"tst x26, x26"
]
},
"lock xor qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0xffffffff80000001",
"tst x26, x26"
]
},
"lock xor word [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoralh w20, w20, [x4]",
"eor w26, w20, #0x1",
"cmn wzr, w26, lsl #16"
]
},
"lock xor dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral w20, w20, [x4]",
"eor w26, w20, #0x1",
"tst w26, w26"
]
},
"lock xor qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0x1",
"tst x26, x26"
]
},
"lock dec byte [rax]": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP3 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalb w1, w27, [x4]",
"sub w26, w27, #0x1 (1)",
"cset w20, hs",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"bic w22, w27, w26",
"ubfx x22, x22, #7, #1",
"orr w21, w21, w22, lsl #28",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
]
},
"lock not byte [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf6 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"steorlb w20, [x4]"
]
},
"lock not word [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"steorlh w20, [x4]"
]
},
"lock not dword [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"steorl w20, [x4]"
]
},
"lock not qword [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"steorl x20, [x4]"
]
},
"lock neg byte [rax]": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"ldaxrb w1, [x4]",
"neg w2, w1",
"stlxrb w3, w2, [x4]",
"cbnz w3, #-0xc",
"mov w27, w1",
"neg w26, w27",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"ubfx x21, x26, #8, #1",
"orr w20, w20, w21, lsl #29",
"and w21, w26, w27",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock neg word [rax]": {
"ExpectedInstructionCount": 14,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxrh w1, [x4]",
"neg w2, w1",
"stlxrh w3, w2, [x4]",
"cbnz w3, #-0xc",
"mov w27, w1",
"neg w26, w27",
"cmn wzr, w26, lsl #16",
"mrs x20, nzcv",
"ubfx x21, x26, #16, #1",
"orr w20, w20, w21, lsl #29",
"and w21, w26, w27",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock neg dword [rax]": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxr w1, [x4]",
"neg w2, w1",
"stlxr w3, w2, [x4]",
"cbnz w3, #-0xc",
"mov w27, w1",
"neg w26, w27",
"cmp wzr, w27",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock neg qword [rax]": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxr x1, [x4]",
"neg x2, x1",
"stlxr w3, x2, [x4]",
"cbnz x3, #-0xc",
"mov x27, x1",
"neg x26, x27",
"cmp xzr, x27",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock dec word [rax]": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"sub w26, w27, #0x1 (1)",
"cset w20, hs",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"bic w22, w27, w26",
"ubfx x22, x22, #15, #1",
"orr w21, w21, w22, lsl #28",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
]
},
"lock dec dword [rax]": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddal w1, w27, [x4]",
"sub w26, w27, #0x1 (1)",
"cset w20, hs",
"cmp w27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"lock dec qword [rax]": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"sub x26, x27, #0x1 (1)",
"cset w20, hs",
"cmp x27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"lock inc byte [rax]": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalb w20, w27, [x4]",
"add w26, w27, #0x1 (1)",
"cset w20, hs",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"bic w22, w26, w27",
"ubfx x22, x22, #7, #1",
"orr w21, w21, w22, lsl #28",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
]
},
"lock inc word [rax]": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalh w20, w27, [x4]",
"add w26, w27, #0x1 (1)",
"cset w20, hs",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"bic w22, w26, w27",
"ubfx x22, x22, #15, #1",
"orr w21, w21, w22, lsl #28",
"orr w20, w21, w20, lsl #29",
"msr nzcv, x20"
]
},
"lock inc dword [rax]": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal w20, w27, [x4]",
"add w26, w27, #0x1 (1)",
"cset w20, hs",
"cmn w27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
},
"lock inc qword [rax]": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal x20, x27, [x4]",
"add x26, x27, #0x1 (1)",
"cset w20, hs",
"cmn x27, #0x1 (1)",
"mrs x21, nzcv",
"mov w0, w21",
"bfi w0, w20, #29, #1",
"mov w20, w0",
"msr nzcv, x20"
]
}
}
}
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