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FEX-Emu--FEX/unittests/InstructionCountCI/RPRES/DDD.json
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Alyssa Rosenzweig cea551c2ac InstCountCI: Update
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-17 17:37:24 -04:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [
"RPRES"
],
"DisabledHostFeatures": [
"SVE128",
"SVE256"
]
},
"Instructions": {
"pfrcpv mm0, mm1": {
"ExpectedInstructionCount": 3,
"Comment": [
"0x0f 0x0f 0x86"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"frecpe v2.2s, v2.2s",
"str d2, [x28, #768]"
]
},
"pfrsqrtv mm0, mm1": {
"ExpectedInstructionCount": 3,
"Comment": [
"0x0f 0x0f 0x87"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"frsqrte v2.2s, v2.2s",
"str d2, [x28, #768]"
]
},
"pfrcp mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": [
"0x0f 0x0f 0x96"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"frecpe s2, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #768]"
]
},
"pfrsqrt mm0, mm1": {
"ExpectedInstructionCount": 4,
"Comment": [
"0x0f 0x0f 0x97"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"frsqrte s2, s2",
"dup v2.2s, v2.s[0]",
"str d2, [x28, #768]"
]
}
}
}