Docs: Update for release FEX-2601

FEXCore: Cleanup pointers structure

.github/workflows/steamrt4.yml

@@ -75,5 +75,5 @@ jobs:
         overwrite: true
         name: steamrt4_steampipe_depot
         path: ${{runner.workspace}}/install/*
-        retention-days: 1
+        retention-days: 60
         compression-level: 9

CMakeLists.txt

@@ -1,47 +1,49 @@
 cmake_minimum_required(VERSION 3.14)
 project(FEX C CXX ASM)
 
-INCLUDE (CheckIncludeFiles)
-CHECK_INCLUDE_FILES ("gdb/jit-reader.h" HAVE_GDB_JIT_READER_H)
+include(CheckIncludeFiles)
+check_include_files("gdb/jit-reader.h" HAVE_GDB_JIT_READER_H)
 
-option(BUILD_FEX_LINUX_TESTS "Build FEXLinuxTests, requires x86 compiler" FALSE)
+option(BUILD_FEX_LINUX_TESTS "Build FEXLinuxTests (requires x86 compiler)" FALSE)
 option(BUILD_THUNKS "Build thunks" FALSE)
 option(BUILD_FEXCONFIG "Build FEXConfig" TRUE)
 option(ENABLE_CLANG_THUNKS "Build thunks with clang" TRUE)
-option(ENABLE_IWYU "Enables include what you use program" FALSE)
+option(ENABLE_IWYU "Enable the Include What You Use sanitizer" FALSE)
 option(ENABLE_LTO "Enable LTO with compilation" TRUE)
 option(ENABLE_XRAY "Enable building with LLVM X-Ray" FALSE)
-set(USE_LINKER "" CACHE STRING "Allow overriding the linker path directly")
-option(ENABLE_UBSAN "Enables Clang UBSAN" FALSE)
-option(ENABLE_ASAN "Enables Clang ASAN" FALSE)
-option(ENABLE_TSAN "Enables Clang TSAN" FALSE)
-option(ENABLE_COVERAGE "Enables Coverage" FALSE)
-option(ENABLE_ASSERTIONS "Enables assertions in build" FALSE)
-option(ENABLE_GDB_SYMBOLS "Enables GDBSymbols integration support" ${HAVE_GDB_JIT_READER_H})
-option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
-option(ENABLE_WERROR "Enables -Werror" FALSE)
-option(ENABLE_JEMALLOC "Enables jemalloc allocator" TRUE)
-option(ENABLE_JEMALLOC_GLIBC_ALLOC "Enables jemalloc glibc allocator" TRUE)
-option(ENABLE_OFFLINE_TELEMETRY "Enables FEX offline telemetry" TRUE)
-option(ENABLE_COMPILE_TIME_TRACE "Enables time trace compile option" FALSE)
-option(ENABLE_LIBCXX "Enables LLVM libc++" FALSE)
-option(ENABLE_CCACHE "Enables ccache for compile caching" TRUE)
-option(ENABLE_VIXL_SIMULATOR "Enable use of VIXL simulator for emulation (only useful for CI testing)" FALSE)
-option(ENABLE_VIXL_DISASSEMBLER "Enables debug disassembler output with VIXL" FALSE)
-option(USE_LEGACY_BINFMTMISC "Uses legacy method of setting up binfmt_misc" FALSE)
-option(ENABLE_FEXCORE_PROFILER "Enables use of the FEXCore timeline profiling capabilities" FALSE)
-set (FEXCORE_PROFILER_BACKEND "gpuvis" CACHE STRING "Set which backend to use for the FEXCore profiler (gpuvis, tracy)")
+set(USE_LINKER "" CACHE STRING "Path to a custom linker program")
+option(ENABLE_UBSAN "Enable the Clang Undefined Behavior Sanitizer" FALSE)
+option(ENABLE_ASAN "Enable the Clang Address Sanitizer" FALSE)
+option(ENABLE_TSAN "Enable the Clang Thread Sanitizer" FALSE)
+option(ENABLE_COVERAGE "Enable Code Coverage" FALSE)
+option(ENABLE_ASSERTIONS "Enable debug assertions" FALSE)
+option(ENABLE_GDB_SYMBOLS "Enable GDBSymbols integration support" ${HAVE_GDB_JIT_READER_H})
+option(ENABLE_STRICT_WERROR "Enable stricter -Werror" FALSE)
+option(ENABLE_WERROR "Enable -Werror" FALSE)
+option(ENABLE_JEMALLOC "Enable jemalloc allocator" TRUE)
+option(ENABLE_JEMALLOC_GLIBC_ALLOC "Enable jemalloc glibc allocator" TRUE)
+option(ENABLE_OFFLINE_TELEMETRY "Enable FEX offline telemetry" TRUE)
+option(ENABLE_COMPILE_TIME_TRACE "Enable time trace compile option" FALSE)
+option(ENABLE_LIBCXX "Use LLVM's libc++ instead of the GNU libstdc++" FALSE)
+option(ENABLE_CCACHE "Enable ccache for build caching" TRUE)
+option(ENABLE_VIXL_SIMULATOR "Use the VIXL simulator for emulation (only useful for CI testing)" FALSE)
+option(ENABLE_VIXL_DISASSEMBLER "Enable debug disassembler output with VIXL" FALSE)
+option(USE_LEGACY_BINFMTMISC "Use legacy method of setting up binfmt_misc" FALSE)
+option(ENABLE_FEXCORE_PROFILER "Enable FEXCore's timeline profiling capabilities" FALSE)
+set(FEXCORE_PROFILER_BACKEND "gpuvis" CACHE STRING "Set which backend to use for FEXCore's profiler")
+set_property(CACHE FEXCORE_PROFILER_BACKEND PROPERTY STRINGS gpuvis tracy)
 option(ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT "Enables glibc memory allocation hooking with fault for CI testing")
-option(USE_PDB_DEBUGINFO "Builds debug info in PDB format" FALSE)
-option(BUILD_STEAM_SUPPORT "Builds FEX for integration into Steam" FALSE)
+option(USE_PDB_DEBUGINFO "Build debug info in PDB format" FALSE)
+option(BUILD_STEAM_SUPPORT "Enable Steam integration" FALSE)
+
+set(X86_32_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/toolchain_x86_32.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting i686")
+set(X86_64_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/toolchain_x86_64.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting x86_64")
+set(X86_DEV_ROOTFS "/" CACHE FILEPATH "Path to the sysroot used for cross-compiling for i686 and x86_64")
+set(DATA_DIRECTORY "" CACHE PATH "Global data directory (override)")
+set(HOSTLIBS_DATA_DIRECTORY "" CACHE PATH "Global data directory (override)")
 
-set (X86_32_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/toolchain_x86_32.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting i686")
-set (X86_64_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/Data/CMake/toolchain_x86_64.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting x86_64")
-set (X86_DEV_ROOTFS "/" CACHE FILEPATH "Path to the sysroot used for cross-compiling for i686 and x86_64")
-set (DATA_DIRECTORY "" CACHE PATH "Global data directory (override)")
-set (HOSTLIBS_DATA_DIRECTORY "" CACHE PATH "Global data directory (override)")
 if (NOT DATA_DIRECTORY)
-  set (DATA_DIRECTORY "${CMAKE_INSTALL_PREFIX}/share/fex-emu")
+  set(DATA_DIRECTORY "${CMAKE_INSTALL_PREFIX}/share/fex-emu")
 endif()
 
 include(GNUInstallDirs)
@@ -49,22 +51,70 @@ if (NOT HOSTLIBS_DATA_DIRECTORY)
   set(HOSTLIBS_DATA_DIRECTORY "${CMAKE_INSTALL_FULL_LIBDIR}/fex-emu")
 endif()
 
-string(FIND ${CMAKE_BASE_NAME} mingw CONTAINS_MINGW)
-if (NOT CONTAINS_MINGW EQUAL -1)
-  message (STATUS "Mingw build")
-  set (MINGW_BUILD TRUE)
-  set (ENABLE_JEMALLOC TRUE)
-  set (ENABLE_JEMALLOC_GLIBC_ALLOC FALSE)
+## Platform Checks ##
+# Only 64-bit Linux and Windows are supported
+
+# NB: SIZEOF_VOID_P is in bytes, not bits
+# On 32-bit systems this is set to 4
+if (NOT CMAKE_SIZEOF_VOID_P EQUAL 8)
+  message(FATAL_ERROR "Unsupported pointer size ${CMAKE_SIZEOF_VOID_P}."
+    " FEX only supports 64-bit (8-byte pointer) systems."
+    " If you believe this is in error, file an issue.")
+elseif (NOT (WIN32 OR CMAKE_SYSTEM_NAME STREQUAL "Linux"))
+  message(FATAL_ERROR "Unsupported system type ${CMAKE_SYSTEM_NAME}."
+    " FEX only supports Linux and Windows."
+    " If you believe this is in error, file an issue.")
 endif()
 
-if (NOT MINGW_BUILD)
-  message (STATUS "Clang version ${CMAKE_CXX_COMPILER_VERSION}")
-  set (CLANG_MINIMUM_VERSION 13.0)
+## Compiler Checks ##
+# GCC and MSVC are unsupported
+if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
+  message(FATAL_ERROR "FEX doesn't support GCC! Use Clang instead.")
+elseif (MSVC)
+  message(FATAL_ERROR "FEX doesn't support MSVC! Use Clang on MinGW instead.")
+elseif (MINGW)
+  message(STATUS "Building for MinGW")
+  set(ENABLE_JEMALLOC TRUE)
+  set(ENABLE_JEMALLOC_GLIBC_ALLOC FALSE)
+else ()
+  message(STATUS "Clang version ${CMAKE_CXX_COMPILER_VERSION}")
+  set(CLANG_MINIMUM_VERSION 13.0)
   if (CMAKE_CXX_COMPILER_VERSION VERSION_LESS ${CLANG_MINIMUM_VERSION})
-    message (FATAL_ERROR "Clang version too old for FEX. Need at least ${CLANG_MINIMUM_VERSION} but has ${CMAKE_CXX_COMPILER_VERSION}")
+    message(FATAL_ERROR "Clang version too old for FEX. Need at least ${CLANG_MINIMUM_VERSION} but has ${CMAKE_CXX_COMPILER_VERSION}")
   endif()
 endif()
 
+## Architecture Handling ##
+string(TOLOWER ${CMAKE_SYSTEM_PROCESSOR} processor)
+if (processor MATCHES "x86|amd64")
+  option(ENABLE_X86_HOST_DEBUG "Enables compiling on x86_64 host" FALSE)
+  if (NOT ENABLE_X86_HOST_DEBUG)
+    message(FATAL_ERROR
+      " FEX doesn't support compiling for x86-64 hosts!"
+      " This is /only/ a supported configuration for FEX CI and nothing else!")
+  else()
+    message(STATUS "x86_64 debug build")
+  endif()
+
+  set(ARCHITECTURE_x86_64 1)
+  add_definitions(-DARCHITECTURE_x86_64=1)
+  set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
+elseif (processor MATCHES "^aarch64|^arm64|^armv8\.*")
+  set(ARCHITECTURE_arm64 1)
+  add_definitions(-DARCHITECTURE_arm64=1)
+
+  # arm64ec needs to define both arm64 and arm64ec
+  if (processor MATCHES "^arm64ec")
+    set(ARCHITECTURE_arm64ec 1)
+    add_definitions(-DARCHITECTURE_arm64ec=1)
+  endif()
+endif()
+
+if (NOT (ARCHITECTURE_arm64 OR ARCHITECTURE_arm64ec OR ARCHITECTURE_x86_64))
+  message(FATAL_ERROR "Unsupported processor type ${processor}."
+    " If you believe this is in error, file an issue.")
+endif()
+
 if (BUILD_STEAM_SUPPORT)
   add_definitions(-DFEX_STEAM_SUPPORT=1)
 endif()
@@ -88,8 +138,8 @@ if (ENABLE_FEXCORE_PROFILER)
     add_definitions(-DTRACY_NO_SAMPLING=1)
     # This pulls in libbacktrace which allocators in global constructors (before FEX can set up its allocator hooks)
     add_definitions(-DTRACY_NO_CALLSTACK=1)
-    if (MINGW_BUILD)
-      message(FATAL_ERROR "Tracy profiler not supported")
+    if (MINGW)
+      message(FATAL_ERROR "Tracy profiler not supported on MinGW")
     endif()
   else()
     message(FATAL_ERROR "Unknown FEXCore profiler backend ${FEXCORE_PROFILER_BACKEND}")
@@ -116,9 +166,10 @@ if(NOT TARGET uninstall)
 endif()
 
 # These options are meant for package management
-set (TUNE_CPU "native" CACHE STRING "Override the CPU the build is tuned for")
-set (TUNE_ARCH "generic" CACHE STRING "Override the Arch the build is tuned for")
-set (OVERRIDE_VERSION "detect" CACHE STRING "Override the FEX version in the format of <MMYY>{.<REV>}")
+set(TUNE_CPU "native" CACHE STRING "Override the CPU the build is tuned for")
+set(TUNE_ARCH "generic" CACHE STRING "Override the Arch the build is tuned for")
+set(OVERRIDE_VERSION "detect" CACHE STRING "Override the FEX version")
+set(OVERRIDE_HASH "detect" CACHE STRING "Override the FEX git hash")
 
 string(TOUPPER "${CMAKE_BUILD_TYPE}" CMAKE_BUILD_TYPE)
 if (CMAKE_BUILD_TYPE MATCHES "DEBUG")
@@ -135,7 +186,6 @@ if (ENABLE_GDB_SYMBOLS)
   add_definitions(-DGDB_SYMBOLS_ENABLED=1)
 endif()
 
-
 set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/Bin)
@@ -145,33 +195,7 @@ cmake_policy(SET CMP0083 NEW) # Follow new PIE policy
 include(CheckPIESupported)
 check_pie_supported()
 
-if (ENABLE_LTO)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-else()
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION FALSE)
-endif()
-
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
-  option(ENABLE_X86_HOST_DEBUG "Enables compiling on x86_64 host" FALSE)
-  if (NOT ENABLE_X86_HOST_DEBUG)
-    message(FATAL_ERROR
-    " FEX-Emu doesn't support compiling for x86-64 hosts!"
-    " This is /only/ a supported configuration for FEX CI and nothing else!")
-  endif()
-  set(_M_X86_64 1)
-  add_definitions(-D_M_X86_64=1)
-  set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
-endif()
-
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "^aarch64|^arm64|^armv8\.*")
-  set(_M_ARM_64 1)
-  add_definitions(-D_M_ARM_64=1)
-endif()
-
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "^arm64ec")
-  set(_M_ARM_64EC 1)
-  add_definitions(-D_M_ARM_64EC=1)
-endif()
+set(CMAKE_INTERPROCEDURAL_OPTIMIZATION ${ENABLE_LTO})
 
 include(CheckCXXSourceCompiles)
 set(CMAKE_REQUIRED_FLAGS "-std=c++11 -Wattributes -Werror=attributes")
@@ -187,15 +211,15 @@ check_cxx_source_compiles(
   HAS_CLANG_PRESERVE_ALL)
 unset(CMAKE_REQUIRED_FLAGS)
 if (HAS_CLANG_PRESERVE_ALL)
-  if (MINGW_BUILD)
+  if (MINGW)
     message(STATUS "Ignoring broken clang::preserve_all support")
     set(HAS_CLANG_PRESERVE_ALL FALSE)
   else()
     message(STATUS "Has clang::preserve_all")
   endif()
-endif ()
+endif()
 
-if (_M_ARM_64 AND HAS_CLANG_PRESERVE_ALL)
+if (ARCHITECTURE_arm64 AND HAS_CLANG_PRESERVE_ALL)
   add_definitions("-DFEX_PRESERVE_ALL_ATTR=__attribute__((preserve_all))" "-DFEX_HAS_PRESERVE_ALL_ATTR=1")
 else()
   add_definitions("-DFEX_PRESERVE_ALL_ATTR=" "-DFEX_HAS_PRESERVE_ALL_ATTR=0")
@@ -224,7 +248,7 @@ if (ENABLE_COMPILE_TIME_TRACE)
   link_libraries(-ftime-trace)
 endif()
 
-set (PTHREAD_LIB pthread)
+set(PTHREAD_LIB pthread)
 
 if (USE_LINKER)
   message(STATUS "Overriding linker to: ${USE_LINKER}")
@@ -276,8 +300,8 @@ if (ENABLE_JEMALLOC_GLIBC_ALLOC)
   # Required for thunks to work.
   # All host native libraries will use this allocator, while *most* other FEX internal allocations will use the other jemalloc allocator.
   add_subdirectory(External/jemalloc_glibc/)
-elseif (NOT MINGW_BUILD)
-  message (STATUS
+elseif (NOT MINGW)
+  message(STATUS
     " jemalloc glibc allocator disabled!\n"
     " This is not a recommended configuration!\n"
     " This will very explicitly break thunk execution!\n"
@@ -287,8 +311,8 @@ endif()
 if (ENABLE_JEMALLOC)
   # The jemalloc subproject that all FEXCore fextl objects allocate through.
   add_subdirectory(External/jemalloc/)
-elseif (NOT MINGW_BUILD)
-  message (STATUS
+elseif (NOT MINGW)
+  message(STATUS
     " jemalloc disabled!\n"
     " This is not a recommended configuration!\n"
     " This will very explicitly break 32-bit application execution!\n"
@@ -300,12 +324,18 @@ if (USE_PDB_DEBUGINFO)
   add_link_options(-g -Wl,--pdb=)
 endif()
 
-set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
-set (CMAKE_LINKER_FLAGS_RELWITHDEBINFO "${CMAKE_LINKER_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
+set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "${CMAKE_CXX_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
+set(CMAKE_LINKER_FLAGS_RELWITHDEBINFO "${CMAKE_LINKER_FLAGS_RELWITHDEBINFO} -fno-omit-frame-pointer")
 
-set (CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -fomit-frame-pointer")
-set (CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-pointer")
+set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -fomit-frame-pointer")
+set(CMAKE_LINKER_FLAGS_RELEASE "${CMAKE_LINKER_FLAGS_RELEASE} -fomit-frame-pointer")
 
+## Modules ##
+list(APPEND CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/Data/CMake/)
+
+include(LinkerGC)
+
+## Externals ##
 include_directories(External/robin-map/include/)
 
 include(CTest)
@@ -318,20 +348,16 @@ if (ENABLE_FEXCORE_PROFILER AND FEXCORE_PROFILER_BACKEND STREQUAL "TRACY")
   add_subdirectory(External/tracy)
 endif()
 
-if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
-  # This means we were attempted to get compiled with GCC
-  message(FATAL_ERROR "FEX doesn't support getting compiled with GCC!")
-endif()
-
 find_package(PkgConfig REQUIRED)
 find_package(Python 3.9 REQUIRED COMPONENTS Interpreter)
 
 set(BUILD_SHARED_LIBS OFF)
 
-pkg_search_module(xxhash IMPORTED_TARGET xxhash libxxhash)
-if (TARGET PkgConfig::xxhash AND NOT CMAKE_CROSSCOMPILING)
-  add_library(xxHash::xxhash ALIAS PkgConfig::xxhash)
-else()
+if (NOT CMAKE_CROSSCOMPILING)
+  find_package(xxhash MODULE QUIET)
+endif()
+
+if (NOT TARGET xxHash::xxhash)
   set(XXHASH_BUNDLED_MODE TRUE)
   set(XXHASH_BUILD_XXHSUM FALSE)
   add_subdirectory(External/xxhash/cmake_unofficial/)
@@ -412,7 +438,7 @@ if (NOT TUNE_ARCH STREQUAL "generic")
 endif()
 
 if (TUNE_CPU STREQUAL "native")
-  if(_M_ARM_64)
+  if(ARCHITECTURE_arm64)
     if (CMAKE_CXX_COMPILER_VERSION VERSION_GREATER_EQUAL 999999.0)
       # Clang 12.0 fixed the -mcpu=native bug with mixed big.little implementers
       # Clang can not currently check for native Apple M1 type in hypervisor. Currently disabled
@@ -453,6 +479,40 @@ elseif (NOT TUNE_CPU STREQUAL "none")
   endif()
 endif()
 
+set(GIT_DESCRIBE_STRING "FEX-Unknown")
+
+if (OVERRIDE_VERSION STREQUAL "detect")
+  find_package(Git)
+
+  if (GIT_FOUND)
+    execute_process(
+      COMMAND ${GIT_EXECUTABLE} describe --abbrev=7
+      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
+      OUTPUT_VARIABLE GIT_DESCRIBE_STRING
+      ERROR_QUIET
+      OUTPUT_STRIP_TRAILING_WHITESPACE)
+  endif()
+else()
+  set(GIT_DESCRIBE_STRING "${OVERRIDE_VERSION}")
+endif()
+
+set(GIT_SHORT_HASH "Unknown")
+
+if (OVERRIDE_HASH STREQUAL "detect")
+  find_package(Git)
+
+  if (GIT_FOUND)
+    execute_process(
+      COMMAND ${GIT_EXECUTABLE} rev-parse --short=7 HEAD
+      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
+      OUTPUT_VARIABLE GIT_SHORT_HASH
+      ERROR_QUIET
+      OUTPUT_STRIP_TRAILING_WHITESPACE)
+  endif()
+else()
+  set(GIT_SHORT_HASH "${OVERRIDE_HASH}")
+endif()
+
 if (ENABLE_IWYU)
   find_program(IWYU_EXE "iwyu")
   if (IWYU_EXE)
@@ -466,7 +526,7 @@ add_compile_options(-Wall)
 if (BUILD_TESTING)
   message(STATUS "Unit tests are enabled")
 
-  set (TEST_JOB_COUNT "" CACHE STRING "Override number of parallel jobs to use while running tests")
+  set(TEST_JOB_COUNT "" CACHE STRING "Override number of parallel jobs to use while running tests")
   if (TEST_JOB_COUNT)
     message(STATUS "Running tests with ${TEST_JOB_COUNT} jobs")
   elseif(CMAKE_VERSION VERSION_LESS "3.29")
@@ -481,7 +541,7 @@ add_subdirectory(FEXHeaderUtils/)
 add_subdirectory(CodeEmitter/)
 add_subdirectory(FEXCore/)
 
-if (_M_ARM_64 AND NOT MINGW_BUILD AND NOT BUILD_STEAM_SUPPORT)
+if (ARCHITECTURE_arm64 AND NOT MINGW AND NOT BUILD_STEAM_SUPPORT)
   # Binfmt_misc files must be installed prior to Source/ installs
   add_subdirectory(Data/binfmts/)
 endif()
@@ -507,7 +567,7 @@ if (BUILD_TESTING)
 endif()
 
 if (BUILD_THUNKS)
-  set (FEX_PROJECT_SOURCE_DIR ${PROJECT_SOURCE_DIR})
+  set(FEX_PROJECT_SOURCE_DIR ${PROJECT_SOURCE_DIR})
   add_subdirectory(ThunkLibs/Generator)
 
   # Thunk targets for both host libraries and IDE integration
@@ -534,8 +594,7 @@ if (BUILD_THUNKS)
       "-DX86_DEV_ROOTFS=${X86_DEV_ROOTFS}"
     INSTALL_COMMAND ""
     BUILD_ALWAYS ON
-    DEPENDS thunkgen
-  )
+    DEPENDS thunkgen)
 
   ExternalProject_Add(guest-libs-32
     PREFIX guest-libs-32
@@ -553,38 +612,31 @@ if (BUILD_THUNKS)
       "-DX86_DEV_ROOTFS=${X86_DEV_ROOTFS}"
     INSTALL_COMMAND ""
     BUILD_ALWAYS ON
-    DEPENDS thunkgen
-  )
+    DEPENDS thunkgen)
 
   install(
-    CODE "MESSAGE(\"-- Installing: guest-libs\")"
+    CODE "message(\"-- Installing: guest-libs\")"
     CODE "
-    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target install
-    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest
-    )"
+      execute_process(COMMAND ${CMAKE_COMMAND} --build . --target install
+        WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest)"
     DEPENDS guest-libs
-    COMPONENT Runtime
-  )
+    COMPONENT Runtime)
 
   install(
-    CODE "MESSAGE(\"-- Installing: guest-libs-32\")"
+    CODE "message(\"-- Installing: guest-libs-32\")"
     CODE "
-    EXECUTE_PROCESS(COMMAND ${CMAKE_COMMAND} --build . --target install
-    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest_32
-    )"
+      execute_process(COMMAND ${CMAKE_COMMAND} --build . --target install
+        WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest_32)"
     DEPENDS guest-libs-32
-    COMPONENT Runtime
-  )
+    COMPONENT Runtime)
 
   add_custom_target(uninstall_guest-libs
     COMMAND ${CMAKE_COMMAND} "--build" "." "--target" "uninstall"
-    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest
-  )
+    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest)
 
   add_custom_target(uninstall_guest-libs-32
     COMMAND ${CMAKE_COMMAND} "--build" "." "--target" "uninstall"
-    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest_32
-  )
+    WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/Guest_32)
 
   add_dependencies(uninstall uninstall_guest-libs)
   add_dependencies(uninstall uninstall_guest-libs-32)
@@ -593,29 +645,3 @@ endif()
 if (BUILD_STEAM_SUPPORT)
   add_subdirectory(Source/Steam/)
 endif()
-
-set(FEX_VERSION_MAJOR "0")
-set(FEX_VERSION_MINOR "0")
-set(FEX_VERSION_PATCH "0")
-
-if (OVERRIDE_VERSION STREQUAL "detect")
-  find_package(Git)
-  if (GIT_FOUND)
-    execute_process(
-      COMMAND ${GIT_EXECUTABLE} describe --abbrev=0
-      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
-      OUTPUT_VARIABLE GIT_DESCRIBE_STRING
-      RESULT_VARIABLE GIT_ERROR
-      ERROR_QUIET
-      OUTPUT_STRIP_TRAILING_WHITESPACE
-    )
-
-    if (NOT ${GIT_ERROR} EQUAL 0)
-      # Likely built in a way that doesn't have tags
-      # Setup a version tag that is unknown
-      set(GIT_DESCRIBE_STRING "FEX-0000")
-    endif()
-  endif()
-else()
-  set(GIT_DESCRIBE_STRING "FEX-${OVERRIDE_VERSION}")
-endif()

CMakeSettings.json

@@ -129,4 +129,4 @@
 			"variables": []
 		}
 	]
-}
+}

Data/AppConfig/CMakeLists.txt

@@ -15,13 +15,10 @@ foreach(GEN_CONFIG_SRC ${GEN_CONFIG_SOURCES})
   get_filename_component(CONFIG_NAME ${GEN_CONFIG_SRC} NAME_WLE)
 
   # Configure it
-  configure_file(
-    ${GEN_CONFIG_SRC}
-    ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME})
+  configure_file(${GEN_CONFIG_SRC} ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME})
 
   # Then install the configured json
-  install(
-    FILES ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}
+  install(FILES ${CMAKE_BINARY_DIR}/Data/AppConfig/${CONFIG_NAME}
     DESTINATION ${DATA_DIRECTORY}/AppConfig/
     COMPONENT Runtime)
 endforeach()

Data/CMake/Findxxhash.cmake

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: MIT
+
+include(FindPackageHandleStandardArgs)
+
+find_package(PkgConfig QUIET)
+pkg_search_module(xxhash QUIET IMPORTED_TARGET xxhash libxxhash)
+find_package_handle_standard_args(xxhash
+    REQUIRED_VARS xxhash_LINK_LIBRARIES
+    VERSION_VAR xxhash_VERSION
+)
+
+if (xxhash_FOUND AND NOT TARGET xxHash::xxhash)
+    if (TARGET PkgConfig::xxhash)
+        add_library(xxHash::xxhash ALIAS PkgConfig::xxhash)
+    else()
+        add_library(xxHash::xxhash ALIAS xxhash)
+    endif()
+endif()

Data/CMake/LinkerGC.cmake

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: MIT
+
+# This applies some common linker options that reduce code size and linking time in Release mode. Namely:
+# --gc-sections: Linktime garbage collection, discards unused sections from the final output
+# --strip-all  : Similar to running `strip`, discards the symbol table from the final output
+# --as-needed  : Only includes libraries that are actually needed in the final output.
+
+macro(LinkerGC target)
+  if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
+    target_link_options(${target} PRIVATE
+      "LINKER:--gc-sections"
+      "LINKER:--strip-all"
+      "LINKER:--as-needed")
+  endif()
+endmacro()

Data/binfmts/CMakeLists.txt

@@ -3,13 +3,10 @@ function(GenBinFmt Name)
   get_filename_component(FMT_NAME ${Name} NAME_WE)
 
   # Configure it
-  configure_file(
-    ${Name}
-    ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME})
+  configure_file(${Name} ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME})
 
   # Then install the configured binfmt
-  install(
-    FILES ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME}
+  install(FILES ${CMAKE_BINARY_DIR}/Data/binfmts/${FMT_NAME}
     DESTINATION ${CMAKE_INSTALL_PREFIX}/share/binfmts/
     COMPONENT Runtime)
 endfunction()
@@ -18,8 +15,7 @@ if (NOT USE_LEGACY_BINFMTMISC)
   configure_file(FEX-x86.conf.in ${CMAKE_BINARY_DIR}/Data/binfmts/FEX-x86.conf)
   configure_file(FEX-x86_64.conf.in ${CMAKE_BINARY_DIR}/Data/binfmts/FEX-x86_64.conf)
 
-  install(
-    FILES ${CMAKE_BINARY_DIR}/Data/binfmts/FEX-x86.conf ${CMAKE_BINARY_DIR}/Data/binfmts/FEX-x86_64.conf
+  install(FILES ${CMAKE_BINARY_DIR}/Data/binfmts/FEX-x86.conf ${CMAKE_BINARY_DIR}/Data/binfmts/FEX-x86_64.conf
     DESTINATION ${CMAKE_INSTALL_PREFIX}/lib/binfmt.d/
     COMPONENT Runtime)
 else()

External/SoftFloat-3e/CMakeLists.txt

@@ -1,5 +1,5 @@
 
-set (SRCS
+add_library(softfloat_3e STATIC
   # F80 support
   src/extF80_add.c
   src/extF80_div.c
@@ -84,7 +84,7 @@ set (SRCS
   src/s_normSubnormalF32Sig.c
   src/s_f32UIToCommonNaN.c)
 
-if (_M_ARM_64 AND HAS_CLANG_PRESERVE_ALL)
+if (ARCHITECTURE_arm64 AND HAS_CLANG_PRESERVE_ALL)
   list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=__attribute__((preserve_all));-DFEXCORE_HAS_PRESERVE_ALL_ATTR=1")
 else()
   list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=;-DFEXCORE_HAS_PRESERVE_ALL_ATTR=0")
@@ -92,7 +92,6 @@ endif()
 
 list(APPEND DEFINES "-DSOFTFLOAT_BUILTIN_CLZ=1;-DINLINE=static inline;-DINLINE_LEVEL=4;-DSOFTFLOAT_FAST_INT64=1;-DSOFTFLOAT_FAST_DIV32TO16=1;-DSOFTFLOAT_FAST_DIV64TO32=1")
 
-add_library(softfloat_3e STATIC ${SRCS})
 target_include_directories(softfloat_3e PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include/)
 target_include_directories(softfloat_3e PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include/SoftFloat-3e/)
 target_compile_definitions(softfloat_3e PUBLIC ${DEFINES})

External/cephes/CMakeLists.txt

@@ -1,4 +1,4 @@
-set(SRCS_128BIT
+add_library(cephes_128bit STATIC
   src/128bit/Impl.cpp
   src/128bit/atanll.c
   src/128bit/constll.c
@@ -11,7 +11,6 @@ set(SRCS_128BIT
   src/128bit/tanll.c)
 
 # 128-bit library
-add_library(cephes_128bit STATIC ${SRCS_128BIT})
 target_link_libraries(cephes_128bit softfloat_3e)
 target_include_directories(cephes_128bit PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include/)
 target_compile_options(cephes_128bit PRIVATE -fno-builtin)

External/code-format-helper/requirements_formatting.txt

@@ -306,9 +306,9 @@ typing-extensions==4.14.1 \
     --hash=sha256:38b39f4aeeab64884ce9f74c94263ef78f3c22467c8724005483154c26648d36 \
     --hash=sha256:d1e1e3b58374dc93031d6eda2420a48ea44a36c2b4766a4fdeb3710755731d76
     # via pygithub
-urllib3==2.5.0 \
-    --hash=sha256:3fc47733c7e419d4bc3f6b3dc2b4f890bb743906a30d56ba4a5bfa4bbff92760 \
-    --hash=sha256:e6b01673c0fa6a13e374b50871808eb3bf7046c4b125b216f6bf1cc604cff0dc
+urllib3==2.6.0 \
+    --hash=sha256:c90f7a39f716c572c4e3e58509581ebd83f9b59cced005b7db7ad2d22b0db99f \
+    --hash=sha256:cb9bcef5a4b345d5da5d145dc3e30834f58e8018828cbc724d30b4cb7d4d49f1
     # via
     #   -r requirements_formatting.txt.in
     #   pygithub

External/code-format-helper/requirements_formatting.txt.in

@@ -2,7 +2,7 @@ black~=25.1
 darker==2.1.1
 PyGithub==2.6.1
 cryptography>=43.0.1
-urllib3>=2.5.0
+urllib3>=2.6.0
 requests>=2.32.4
 idna>=3.7
 certifi>=2024.7.4

FEXCore/CMakeLists.txt

@@ -1,16 +1,16 @@
 cmake_minimum_required(VERSION 3.14)
-set (PROJECT_NAME FEXCore)
+set(PROJECT_NAME FEXCore)
 project(${PROJECT_NAME}
   VERSION 0.01
   LANGUAGES CXX)
 
 if (CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
-  set(_M_X86_64 1)
+  set(ARCHITECTURE_x86_64 1)
   set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mcx16")
 endif()
 
 if (CMAKE_SYSTEM_PROCESSOR MATCHES "^aarch64|^arm64|^armv8\.*")
-  set(_M_ARM_64 1)
+  set(ARCHITECTURE_arm64 1)
 endif()
 
 set(CMAKE_POSITION_INDEPENDENT_CODE ON)
@@ -25,44 +25,15 @@ include(CheckIncludeFileCXX)
 include(CheckCXXSourceCompiles)
 
 if (EXISTS ${CMAKE_CURRENT_DIR}/External/vixl/)
-    # Useful to have for freestanding libFEXCore
-    add_subdirectory(External/vixl/)
-    include_directories(External/vixl/src/)
+  # Useful to have for freestanding libFEXCore
+  add_subdirectory(External/vixl/)
+  include_directories(External/vixl/src/)
 endif()
 
 set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 
-set(GIT_SHORT_HASH "Unknown")
-set(GIT_DESCRIBE_STRING "FEX-Unknown")
-
-if (OVERRIDE_VERSION STREQUAL "detect")
-# Find our git hash
-  find_package(Git)
-
-  if (GIT_FOUND)
-    execute_process(
-      COMMAND ${GIT_EXECUTABLE} rev-parse --short=7 HEAD
-      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
-      OUTPUT_VARIABLE GIT_SHORT_HASH
-      ERROR_QUIET
-      OUTPUT_STRIP_TRAILING_WHITESPACE
-    )
-    execute_process(
-      COMMAND ${GIT_EXECUTABLE} describe --abbrev=7
-      WORKING_DIRECTORY "${CMAKE_SOURCE_DIR}"
-      OUTPUT_VARIABLE GIT_DESCRIBE_STRING
-      ERROR_QUIET
-      OUTPUT_STRIP_TRAILING_WHITESPACE
-    )
-  endif()
-else()
-  set(GIT_SHORT_HASH "${OVERRIDE_VERSION}")
-  set(GIT_DESCRIBE_STRING "FEX-${OVERRIDE_VERSION}")
-endif()
-
-configure_file(
-  ${CMAKE_CURRENT_SOURCE_DIR}/include/git_version.h.in
+configure_file(${CMAKE_CURRENT_SOURCE_DIR}/include/git_version.h.in
   ${CMAKE_BINARY_DIR}/generated/git_version.h)
 
 include_directories(${CMAKE_BINARY_DIR}/generated)

FEXCore/Source/CMakeLists.txt

@@ -1,20 +1,19 @@
-set (MAN_DIR share/man CACHE PATH "MAN_DIR")
+set(MAN_DIR share/man CACHE PATH "MAN_DIR")
 
-set (FEXCORE_BASE_SRCS
+set(FEXCORE_BASE_SRCS
   Interface/Config/Config.cpp
   Utils/Allocator.cpp
   Utils/FileLoading.cpp
   Utils/ForcedAssert.cpp
   Utils/LogManager.cpp
-  Utils/SpinWaitLock.cpp
-  )
+  Utils/SpinWaitLock.cpp)
 
-if (NOT MINGW_BUILD)
+if (NOT MINGW)
   list(APPEND FEXCORE_BASE_SRCS
     Utils/Allocator/64BitAllocator.cpp)
 endif()
 
-set (SRCS
+set(SRCS
   Common/JitSymbols.cpp
   Interface/Context/Context.cpp
   Interface/Core/LookupCache.cpp
@@ -68,10 +67,9 @@ set (SRCS
   Utils/LongJump.cpp
   Utils/Telemetry.cpp
   Utils/Threads.cpp
-  Utils/Profiler.cpp
-  )
+  Utils/Profiler.cpp)
 
-if (_M_ARM_64)
+if (ARCHITECTURE_arm64)
   list(APPEND SRCS Utils/ArchHelpers/Arm64.cpp)
 else()
   list(APPEND SRCS Utils/ArchHelpers/Arm64_stubs.cpp)
@@ -84,42 +82,41 @@ endif()
 
 set(DEFINES -DJIT_ARM64)
 
-if (_M_X86_64)
-  list(APPEND DEFINES -D_M_X86_64=1)
+if (ARCHITECTURE_x86_64)
+  list(APPEND DEFINES -DARCHITECTURE_x86_64=1)
 endif()
 
-if (_M_ARM_64)
-  list(APPEND DEFINES -D_M_ARM_64=1)
+if (ARCHITECTURE_arm64)
+  list(APPEND DEFINES -DARCHITECTURE_arm64=1)
 endif()
 
 if (ENABLE_VIXL_DISASSEMBLER)
   list(APPEND DEFINES -DVIXL_DISASSEMBLER=1)
 endif()
 
-if (_M_ARM_64 AND HAS_CLANG_PRESERVE_ALL)
+if (ARCHITECTURE_arm64 AND HAS_CLANG_PRESERVE_ALL)
   list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=__attribute__((preserve_all));-DFEXCORE_HAS_PRESERVE_ALL_ATTR=1")
 else()
   list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=;-DFEXCORE_HAS_PRESERVE_ALL_ATTR=0")
 endif()
 
-set (LIBS fmt::fmt xxHash::xxhash FEXHeaderUtils CodeEmitter cephes_128bit)
+set(LIBS fmt::fmt xxHash::xxhash FEXHeaderUtils CodeEmitter cephes_128bit)
 
 if (ENABLE_VIXL_DISASSEMBLER OR ENABLE_VIXL_SIMULATOR)
-  list (APPEND LIBS vixl)
+  list(APPEND LIBS vixl)
 endif()
 
-if (NOT MINGW_BUILD)
-  list (APPEND LIBS dl)
+if (NOT MINGW)
+  list(APPEND LIBS dl)
 else()
-  list (APPEND LIBS synchronization)
-  if (_M_ARM_64EC)
-    list (APPEND LIBS mincore)
+  list(APPEND LIBS synchronization)
+  if (ARCHITECTURE_arm64ec)
+    list(APPEND LIBS mincore)
   endif()
 endif()
 
 # Generate config
-configure_file(
-  ${CMAKE_CURRENT_SOURCE_DIR}/Interface/Config/Config.json.in
+configure_file(${CMAKE_CURRENT_SOURCE_DIR}/Interface/Config/Config.json.in
   ${CMAKE_BINARY_DIR}/generated/Config/Config.json)
 
 # Generate IR include file
@@ -134,11 +131,10 @@ add_custom_command(
   OUTPUT "${OUTPUT_NAME}" "${OUTPUT_DISPATCHER_NAME}"
   DEPENDS "${INPUT_NAME}"
   DEPENDS "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/json_ir_generator.py"
-  COMMAND "python3" "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/json_ir_generator.py" "${INPUT_NAME}" "${OUTPUT_NAME}" "${OUTPUT_DISPATCHER_NAME}"
-  )
+  COMMAND "python3" "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/json_ir_generator.py"
+    "${INPUT_NAME}" "${OUTPUT_NAME}" "${OUTPUT_DISPATCHER_NAME}")
 
-set_source_files_properties(${OUTPUT_NAME} PROPERTIES
-  GENERATED TRUE)
+set_source_files_properties(${OUTPUT_NAME} PROPERTIES GENERATED TRUE)
 
 # Generate IR documentation
 set(OUTPUT_IR_DOC "${CMAKE_BINARY_DIR}/IR.md")
@@ -147,11 +143,10 @@ add_custom_command(
   OUTPUT "${OUTPUT_IR_DOC}"
   DEPENDS "${INPUT_NAME}"
   DEPENDS "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/json_ir_doc_generator.py"
-  COMMAND "python3" "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/json_ir_doc_generator.py" "${INPUT_NAME}" "${OUTPUT_IR_DOC}"
-  )
+  COMMAND "python3" "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/json_ir_doc_generator.py"
+    "${INPUT_NAME}" "${OUTPUT_IR_DOC}")
 
-set_source_files_properties(${OUTPUT_IR_NAME} PROPERTIES
-  GENERATED TRUE)
+set_source_files_properties(${OUTPUT_IR_NAME} PROPERTIES GENERATED TRUE)
 
 # Create the target
 add_custom_target(IR_INC
@@ -175,14 +170,12 @@ add_custom_command(
   DEPENDS "${INPUT_CONFIG_NAME}"
   DEPENDS "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/config_generator.py"
   COMMAND "python3" "${CMAKE_CURRENT_SOURCE_DIR}/../Scripts/config_generator.py" "${INPUT_CONFIG_NAME}" "${OUTPUT_CONFIG_NAME}" "${OUTPUT_MAN_NAME}"
-  "${OUTPUT_CONFIG_OPTION_NAME}"
-  )
+  "${OUTPUT_CONFIG_OPTION_NAME}")
 
 add_custom_command(
   OUTPUT "${OUTPUT_MAN_NAME_COMPRESS}"
   DEPENDS "${OUTPUT_MAN_NAME}"
-  COMMAND "gzip" "-kf9n" "${OUTPUT_MAN_NAME}"
-  )
+  COMMAND "gzip" "-kf9n" "${OUTPUT_MAN_NAME}")
 
 set_source_files_properties(${OUTPUT_CONFIG_NAME} PROPERTIES
   GENERATED TRUE)
@@ -226,8 +219,7 @@ function(AddDefaultOptionsToTarget Name)
   target_compile_definitions(${Name} PRIVATE ${DEFINES})
   add_dependencies(${Name} CONFIG_INC IR_INC)
 
-  target_compile_options(${Name}
-    PRIVATE
+  target_compile_options(${Name} PRIVATE
     -Wall
     -Werror=cast-qual
     -Werror=ignored-qualifiers
@@ -235,31 +227,20 @@ function(AddDefaultOptionsToTarget Name)
 
     -Wno-trigraphs
     -ffunction-sections
-    -fwrapv
-  )
+    -fwrapv)
 
   if (GCC_COLOR)
-    target_compile_options(${Name}
-      PRIVATE
-      "-fdiagnostics-color=always")
-  endif()
-  if (CLANG_COLOR)
-    target_compile_options(${Name}
-      PRIVATE
-      "-fcolor-diagnostics")
+    target_compile_options(${Name} PRIVATE "-fdiagnostics-color=always")
   endif()
 
-  if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
-    target_link_options(${Name}
-      PRIVATE
-      "LINKER:--gc-sections"
-      "LINKER:--strip-all"
-      "LINKER:--as-needed"
-    )
+  if (CLANG_COLOR)
+    target_compile_options(${Name} PRIVATE "-fcolor-diagnostics")
   endif()
+
+  LinkerGC(${Name})
 endfunction()
 
-# Build FEXCore_Config static library
+# Build FEXCore_Base static library
 add_library(FEXCore_Base STATIC ${FEXCORE_BASE_SRCS})
 target_link_libraries(FEXCore_Base ${LIBS})
 AddDefaultOptionsToTarget(FEXCore_Base)
@@ -268,34 +249,34 @@ if (ENABLE_FEXCORE_PROFILER AND FEXCORE_PROFILER_BACKEND STREQUAL "TRACY")
   target_link_libraries(FEXCore_Base TracyClient)
 endif()
 
-function(AddObject Name Type)
-  add_library(${Name} ${Type} ${SRCS})
+function(AddObject Name)
+  add_library(${Name} OBJECT ${SRCS})
 
-  target_link_libraries(${Name} FEXCore_Base)
+  target_link_libraries(${Name} PRIVATE FEXCore_Base)
   target_compile_options(${Name} PRIVATE ${FEX_TUNE_COMPILE_FLAGS})
   AddDefaultOptionsToTarget(${Name})
-
-  set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
 endfunction()
 
 function(AddLibrary Name Type)
   add_library(${Name} ${Type} $<TARGET_OBJECTS:${PROJECT_NAME}_object>)
-  target_link_libraries(${Name} FEXCore_Base)
-  target_compile_options(${Name} PRIVATE ${FEX_TUNE_COMPILE_FLAGS})
   set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
 
+  # During generation of the import library (dll.a), MinGW needs some extra symbols from libraries
+  # such as fmt, which are propagated by FEXCore_Base. Wonderful.
+  if (MINGW)
+    target_link_libraries(${Name} FEXCore_Base)
+  endif()
   AddDefaultOptionsToTarget(${Name})
 endfunction()
 
-AddObject(${PROJECT_NAME}_object OBJECT)
+AddObject(${PROJECT_NAME}_object)
 AddLibrary(${PROJECT_NAME} STATIC)
 AddLibrary(${PROJECT_NAME}_shared SHARED)
 
-if (NOT MINGW_BUILD AND NOT BUILD_STEAM_SUPPORT)
-  install(TARGETS ${PROJECT_NAME}_shared
-    LIBRARY
-      DESTINATION ${CMAKE_INSTALL_LIBDIR}
-      COMPONENT Libraries)
+if (NOT MINGW AND NOT BUILD_STEAM_SUPPORT)
+  install(TARGETS ${PROJECT_NAME}_shared LIBRARY
+    DESTINATION ${CMAKE_INSTALL_LIBDIR}
+    COMPONENT Libraries)
 endif()
 
 # Meta-library to link jemalloc libraries enabled in the build configuration.
@@ -310,7 +291,7 @@ if (ENABLE_JEMALLOC_GLIBC_ALLOC)
   target_link_libraries(JemallocLibs INTERFACE FEX_jemalloc_glibc)
 endif()
 
-if (NOT MINGW_BUILD)
+if (NOT MINGW)
   # Dummy project to use for host tools.
   # This overrides use of jemalloc in FEXCore with the normal glibc allocator.
   add_library(JemallocDummy STATIC Utils/AllocatorHooks.cpp)

FEXCore/Source/Common/SoftFloat.h

@@ -19,7 +19,7 @@ extern "C" {
 }
 
 struct FEX_PACKED X80SoftFloat {
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
 // Define this to push some operations to x87
 // Only useful to see if precision loss is killing something
 // #define DEBUG_X86_FLOAT
@@ -30,7 +30,7 @@ struct FEX_PACKED X80SoftFloat {
 #define BIGFLOAT float128_t
 #define BIGFLOATSIZE 16
 #endif
-#elif defined(_M_ARM_64)
+#elif defined(ARCHITECTURE_arm64)
 #define BIGFLOAT float128_t
 #define BIGFLOATSIZE 16
 #else

FEXCore/Source/Common/VectorRegType.h

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: MIT
 #pragma once
 
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
 #include <xmmintrin.h>
 #include <immintrin.h>
 #else
@@ -13,7 +13,7 @@ struct VectorScalarF64Pair {
   double val[2];
 };
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 // Can't use uint8x16_t directly from arm_neon.h here.
 // Overrides softfloat-3e's defines which causes problems.
 using VectorRegType = __attribute__((neon_vector_type(16))) uint8_t;
@@ -25,7 +25,7 @@ static inline VectorRegPairType MakeVectorRegPair(VectorRegType low, VectorRegTy
   return VectorRegPairType {low, high};
 }
 
-#elif defined(_M_X86_64)
+#elif defined(ARCHITECTURE_x86_64)
 using VectorRegType = __m128i;
 using VectorRegPairType = __m256i;
 

FEXCore/Source/Interface/Config/Config.json.in

@@ -23,6 +23,13 @@
           "Enable the code caching subsystem"
         ]
       },
+      "EnableCodeCacheValidation": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Enable expensive validation when loading code caches"
+        ]
+      },
       "HostFeatures": {
         "Type": "strenum",
         "Default": "FEXCore::Config::HostFeatures::OFF",
@@ -364,7 +371,7 @@
         "Default": "server",
         "Desc": [
           "File to write FEX output to.",
-          "[stdout, stderr, server, <Filename>]"
+          "[stderr, server, <Filename>]"
         ]
       },
       "TelemetryDirectory": {

FEXCore/Source/Interface/Context/Context.h

@@ -70,12 +70,30 @@ public:
   ~CodeCache();
 
   ContextImpl& CTX;
+  fextl::unique_ptr<ContextImpl> ValidationCTX;
+  fextl::unique_ptr<Core::InternalThreadState> ValidationThread;
+  FEXCore::Core::CPUState::gdt_segment ValidationGDT[32] {};
   bool IsGeneratingCache = false;
 
-  uint64_t ComputeCodeMapId(std::string_view Filename, int FD) override;
+  FEX_CONFIG_OPT(EnableCodeCaching, ENABLECODECACHINGWIP);
+  FEX_CONFIG_OPT(EnableCodeCacheValidation, ENABLECODECACHEVALIDATION);
 
-  void LoadData(Core::InternalThreadState&, std::byte* MappedCacheFile, const ExecutableFileSectionInfo&) override;
+  uint64_t ComputeCodeMapId(std::string_view Filename, int FD) override;
   bool SaveData(Core::InternalThreadState&, int TargetFD, const ExecutableFileSectionInfo&, uint64_t SerializedBaseAddress) override;
+  bool LoadData(Core::InternalThreadState*, std::byte* MappedCacheFile, const ExecutableFileSectionInfo&) override;
+
+  /**
+   * Performs expensive extra validation on the loaded code cache data.
+   *
+   * This kicks off an in-process recompile of all cached blocks and compares
+   * them with the cached data. Differences will be reported as fatal errors,
+   * which can uncover bugs like for example:
+   * - mismatches of the JIT configuration used during cache generation
+   * - hidden position dependencies due to missing FEX relocations
+   * - incorrect instruction padding
+   */
+  void Validate(const ExecutableFileSectionInfo&, fextl::set<uint64_t> GuestBlocks, const fextl::set<uint64_t>& HostBlocks,
+                std::span<std::byte> CachedCode);
 
   void InitiateCacheGeneration() override {
     IsGeneratingCache = true;

FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp

@@ -41,7 +41,7 @@ namespace FEXCore::CPU {
 //    r19-r29 and SP.
 
 namespace x64 {
-#ifndef _M_ARM_64EC
+#ifndef ARCHITECTURE_arm64ec
   // All but x19 and x29 are caller saved
   // Note that rax/rdx are rearranged here so we can coalesce cmpxchg.
   constexpr std::array<ARMEmitter::Register, 18> SRA = {
@@ -417,18 +417,34 @@ FEXCore::X86State::X86Reg Arm64Emitter::GetX86RegRelationToARMReg(ARMEmitter::Re
   return FEXCore::X86State::X86Reg::REG_INVALID;
 }
 
-void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad) {
+void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, uint64_t Constant, PadType Pad, int MaxBytes) {
+  bool NOPPad = false;
+  if (Pad == PadType::DOPAD) {
+    NOPPad = true;
+  } else if (Pad == PadType::NOPAD) {
+    NOPPad = false;
+  } else if (Pad == PadType::AUTOPAD) {
+    // Force NOP padding to ensure relocated constants always have enough encoding space available
+    NOPPad = EnableCodeCaching;
+  }
+
   bool Is64Bit = s == ARMEmitter::Size::i64Bit;
-  int Segments = Is64Bit ? 4 : 2;
+  const auto UpperBound = Is64Bit ? 4 : 2;
+  int Segments = MaxBytes ? (MaxBytes / 2) : UpperBound;
+
+  LOGMAN_THROW_A_FMT(MaxBytes >= 0 && MaxBytes <= (UpperBound * 2) && (MaxBytes & 1) == 0,
+                     "MaxBytes must be bounded in the range of [0, {}] and 16-bit aligned", UpperBound);
+  // If MaxBytes specified then make sure to sanity check incoming data.
+  LOGMAN_THROW_A_FMT(MaxBytes == 0 || (Constant >> (MaxBytes * 8)) == 0, "MaxBytes provided but data can't fit within provided range.");
 
   if (Is64Bit && ((~Constant) >> 16) == 0) {
-    movn(s, Reg, (~Constant) & 0xFFFF);
-
     if (NOPPad) {
       nop();
       nop();
       nop();
     }
+
+    movn(s, Reg, (~Constant) & 0xFFFF);
     return;
   }
 
@@ -436,17 +452,17 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
     // If the upper 32-bits is all zero, we can now switch to a 32-bit move.
     s = ARMEmitter::Size::i32Bit;
     Is64Bit = false;
-    Segments = 2;
+    Segments = std::min(Segments, 2);
   }
 
   if (!Is64Bit && ((~Constant) & 0xFFFF0000) == 0) {
-    movn(s, Reg.W(), (~Constant) & 0xFFFF);
-
     if (NOPPad) {
       nop();
       nop();
       nop();
     }
+
+    movn(s, Reg.W(), (~Constant) & 0xFFFF);
     return;
   }
 
@@ -467,24 +483,24 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
     // `movz` is better than `orr` since hardware will rename or merge if possible when `movz` is used.
     const auto IsImm = ARMEmitter::Emitter::IsImmLogical(Constant, RegSizeInBits(s));
     if (IsImm) {
-      orr(s, Reg, ARMEmitter::Reg::zr, Constant);
       if (NOPPad) {
         nop();
         nop();
         nop();
       }
+      orr(s, Reg, ARMEmitter::Reg::zr, Constant);
       return;
     }
   }
 
   // If we can't handle negatives with the orr, try with movn+movk
   if (Is64Bit && ((~Constant) >> 32) == 0) {
-    movn(s, Reg, (~Constant) & 0xFFFF);
-    movk(s, Reg, (Constant >> 16) & 0xFFFF, 16);
     if (NOPPad) {
       nop();
       nop();
     }
+    movn(s, Reg, (~Constant) & 0xFFFF);
+    movk(s, Reg, (Constant >> 16) & 0xFFFF, 16);
     return;
   }
 
@@ -786,7 +802,7 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
   auto TmpReg = *OptionalReg;
   auto TmpReg2 = *OptionalReg2;
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
   // Load STATE in from the CPU area as x28 is not callee saved in the ARM64EC ABI.
   ldr(TmpReg.X(), ARMEmitter::Reg::r18, TEB_CPU_AREA_OFFSET);
   ldr(STATE, TmpReg, CPU_AREA_EMULATOR_DATA_OFFSET);

FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h

@@ -1,9 +1,10 @@
 // SPDX-License-Identifier: MIT
 #pragma once
 
+#include <FEXCore/Config/Config.h>
+
 #ifdef VIXL_DISASSEMBLER
 #include <aarch64/disasm-aarch64.h>
-#include <FEXCore/Config/Config.h>
 #include <FEXCore/fextl/memory.h>
 #include <FEXCore/fextl/vector.h>
 #endif
@@ -31,7 +32,7 @@ namespace FEXCore::CPU {
 // Contains the address to the currently available CPU state
 constexpr auto STATE = ARMEmitter::XReg::x28;
 
-#ifndef _M_ARM_64EC
+#ifndef ARCHITECTURE_arm64ec
 // GPR temporaries. Only x3 can be used across spill boundaries
 // so if these ever need to change, be very careful about that.
 constexpr auto TMP1 = ARMEmitter::XReg::x0;
@@ -108,7 +109,15 @@ class Arm64Emitter : public ARMEmitter::Emitter {
 public:
   Arm64Emitter(FEXCore::Context::ContextImpl* ctx, void* EmissionPtr = nullptr, size_t size = 0);
 
-  void LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad = false);
+  enum class PadType {
+    // Explicitly does not need padding, even if code-caching is enabled.
+    NOPAD,
+    // Explicitly needs padding, even if code-caching is disabled.
+    DOPAD,
+    // Choose to pad or not depending on if code-caching is enabled.
+    AUTOPAD,
+  };
+  void LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, uint64_t Constant, PadType Pad = PadType::NOPAD, int MaxBytes = 0);
 
 protected:
   FEXCore::Context::ContextImpl* EmitterCTX;
@@ -272,6 +281,8 @@ protected:
 
   FEX_CONFIG_OPT(Disassemble, DISASSEMBLE);
 #endif
+
+  FEX_CONFIG_OPT(EnableCodeCaching, ENABLECODECACHINGWIP);
 };
 
 } // namespace FEXCore::CPU

FEXCore/Source/Interface/Core/CPUBackend.cpp

@@ -277,37 +277,37 @@ namespace CPU {
     : ThreadState(ThreadState)
     , CodeBuffers(CodeBuffers) {
 
-    auto& Common = ThreadState->CurrentFrame->Pointers.Common;
+    auto& Ptrs = ThreadState->CurrentFrame->Pointers;
 
     // Initialize named vector constants.
     for (size_t i = 0; i < FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX; ++i) {
-      Common.NamedVectorConstantPointers[i] = reinterpret_cast<uint64_t>(NamedVectorConstants[i]);
+      Ptrs.NamedVectorConstantPointers[i] = reinterpret_cast<uint64_t>(NamedVectorConstants[i]);
     }
 
     // Copy named vector constants.
-    memcpy(Common.NamedVectorConstants, NamedVectorConstants, sizeof(NamedVectorConstants));
+    memcpy(Ptrs.NamedVectorConstants, NamedVectorConstants, sizeof(NamedVectorConstants));
 
     // Initialize Indexed named vector constants.
-    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFLW] =
+    Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFLW] =
       reinterpret_cast<uint64_t>(PSHUFLW_LUT.data());
-    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFHW] =
+    Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFHW] =
       reinterpret_cast<uint64_t>(PSHUFHW_LUT.data());
-    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFD] =
+    Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFD] =
       reinterpret_cast<uint64_t>(PSHUFD_LUT.data());
-    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_SHUFPS] =
+    Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_SHUFPS] =
       reinterpret_cast<uint64_t>(SHUFPS_LUT.data());
-    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPS_MASK] =
+    Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPS_MASK] =
       reinterpret_cast<uint64_t>(DPPS_MASK.data());
-    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPD_MASK] =
+    Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPD_MASK] =
       reinterpret_cast<uint64_t>(DPPD_MASK.data());
-    Common.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PBLENDW] =
+    Ptrs.IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PBLENDW] =
       reinterpret_cast<uint64_t>(PBLENDW_LUT.data());
 
 #ifndef FEX_DISABLE_TELEMETRY
     // Fill in telemetry values
     for (size_t i = 0; i < FEXCore::Telemetry::TYPE_LAST; ++i) {
       auto& Telem = FEXCore::Telemetry::GetTelemetryValue(static_cast<FEXCore::Telemetry::TelemetryType>(i));
-      Common.TelemetryValueAddresses[i] = reinterpret_cast<uint64_t>(&Telem);
+      Ptrs.TelemetryValueAddresses[i] = reinterpret_cast<uint64_t>(&Telem);
     }
 #endif
   }

FEXCore/Source/Interface/Core/CPUID.cpp

@@ -24,7 +24,7 @@ $end_info$
 
 namespace FEXCore {
 namespace ProductNames {
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
   static const char ARM_UNKNOWN[] = "Unknown ARM CPU";
   static const char ARM_A57[] = "Cortex-A57";
   static const char ARM_A72[] = "Cortex-A72";
@@ -140,7 +140,7 @@ constexpr uint32_t FAMILY_IDENTIFIER = GenerateFamily(CPUFamily {
 });
 #endif
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 uint32_t GetCycleCounterFrequency() {
   uint64_t Result {};
   __asm("mrs %[Res], CNTFRQ_EL0" : [Res] "=r"(Result));
@@ -857,10 +857,10 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_4000_0001h(uint32_t Leaf) con
   constexpr uint32_t MaximumSubLeafNumber = 2;
   if (Leaf == 0) {
     // EAX[3:0] Is the host architecture that FEX is running under
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
     // EAX[3:0] = 1 = x86_64 host architecture
     Res.eax |= 0b0001;
-#elif defined(_M_ARM_64)
+#elif defined(ARCHITECTURE_arm64)
     // EAX[3:0] = 2 = AArch64 host architecture
     Res.eax |= 0b0010;
 #else
@@ -1230,7 +1230,7 @@ CPUIDEmu::CPUIDEmu(const FEXCore::Context::ContextImpl* ctx)
 
   SetupFeatures();
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
   if (SupportsCPUIndexInTPIDRRO) {
     GetCPUID = GetCPUID_TPIDRRO;
   }

FEXCore/Source/Interface/Core/CPUID.h

@@ -159,7 +159,7 @@ private:
 
   struct CPUData {
     const char* ProductName {};
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
     uint32_t MIDR {};
 #endif
     bool IsBig {};

FEXCore/Source/Interface/Core/CodeCache.cpp

@@ -3,11 +3,15 @@
 
 #include <Interface/Context/Context.h>
 #include <Interface/Core/ArchHelpers/Arm64Emitter.h>
+#include <Interface/Core/Dispatcher/Dispatcher.h>
+#include <Interface/Core/JIT/DebugData.h>
 #include <Interface/Core/JIT/Relocations.h>
 #include <Interface/Core/LookupCache.h>
+#include <Interface/Core/OpcodeDispatcher.h>
+#include <Interface/IR/PassManager.h>
 
 #include <FEXCore/Core/Thunks.h>
-#include <FEXCore/HLE/SourcecodeResolver.h>
+#include <FEXCore/HLE/SyscallHandler.h>
 
 #include <FEXHeaderUtils/Filesystem.h>
 
@@ -25,7 +29,6 @@ ExecutableFileInfo::ExecutableFileInfo(fextl::unique_ptr<HLE::SourcecodeMap> Map
   , FileId(FileId)
   , Filename(Filename) {}
 #endif
-ExecutableFileInfo::~ExecutableFileInfo() = default;
 
 fextl::string CodeMap::GetBaseFilename(const ExecutableFileInfo& MainExecutable, bool AddNombSuffix) {
   auto FileId = MainExecutable.FileId;
@@ -227,7 +230,7 @@ uint64_t CodeCache::ComputeCodeMapId(std::string_view Filename, int FD) {
 }
 
 struct CodeCacheHeader {
-  char Magic[4] = {'F', 'X', 'C', 'C'};
+  std::array<char, 4> Magic = ExpectedMagic;
   uint32_t FormatVersion = 1;
   char FEXVersion[8] = {};
   uint32_t NumBlocks;
@@ -236,28 +239,23 @@ struct CodeCacheHeader {
   uint32_t NumRelocations;
   uint64_t SerializedBaseAddress;
   // TODO: Consider including information from LookupCache.BlockLinks
+
+  static constexpr std::array<char, 4> ExpectedMagic = {'F', 'X', 'C', 'C'};
 };
 
-void CodeCache::LoadData(Core::InternalThreadState& Thread, std::byte* MappedCacheFile, const ExecutableFileSectionInfo& GuestRIPLookup) {
-  // TODO
-}
-
 template<typename T>
-static constexpr auto IsOrderedContainer(const T&) -> std::false_type;
-template<typename... T>
-static constexpr auto IsOrderedContainer(const std::map<T...>&) -> std::true_type;
-template<typename... T>
-static constexpr auto IsOrderedContainer(const std::set<T...>&) -> std::true_type;
+concept OrderedContainer = requires { typename T::key_compare; };
 
 bool CodeCache::SaveData(Core::InternalThreadState& Thread, int fd, const ExecutableFileSectionInfo& SourceBinary, uint64_t SerializedBaseAddress) {
   auto CodeBuffer = CTX.GetLatest();
   auto& LookupCache = *Thread.LookupCache->Shared;
-
   auto Relocations = Thread.CPUBackend->TakeRelocations(SourceBinary.FileStartVA);
 
   // Write file header
-  CodeCacheHeader header;
-  memcpy(&header.FEXVersion[0], GIT_SHORT_HASH, strlen(GIT_SHORT_HASH));
+  CodeCacheHeader header {};
+  constexpr std::string_view git_hash = GIT_SHORT_HASH;
+  static_assert(git_hash.size() <= sizeof(header.FEXVersion));
+  std::ranges::copy(git_hash, header.FEXVersion);
   header.NumBlocks = LookupCache.BlockList.size();
   header.NumCodePages = LookupCache.CodePages.size();
   header.CodeBufferSize = CTX.LatestOffset;
@@ -268,7 +266,7 @@ bool CodeCache::SaveData(Core::InternalThreadState& Thread, int fd, const Execut
   // Dump guest<->host block mappings
   {
     // Cache contents must be deterministic, so copy the unordered block list and then sort by key
-    static_assert(!decltype(IsOrderedContainer(LookupCache.BlockList))::value, "Already deterministic; drop temporary container");
+    static_assert(!OrderedContainer<decltype(LookupCache.BlockList)>, "Already deterministic; drop temporary container");
     fextl::vector<std::pair<uint64_t, const GuestToHostMap::BlockEntry*>> BlockList;
     BlockList.reserve(LookupCache.BlockList.size());
     for (auto& [Guest, BlockEntry] : LookupCache.BlockList) {
@@ -317,18 +315,305 @@ bool CodeCache::SaveData(Core::InternalThreadState& Thread, int fd, const Execut
   ::write(fd, CodeBufferData.data(), CodeBufferData.size());
 
   // Dump code pages
-  static_assert(decltype(IsOrderedContainer(LookupCache.CodePages))::value, "Non-deterministic data source");
-  for (auto& [Page, Entrypoints] : LookupCache.CodePages) {
-    static_assert(sizeof(Page) == 8, "Breaking change in code cache data layout");
-    ::write(fd, &Page, sizeof(Page));
+  static_assert(OrderedContainer<decltype(LookupCache.CodePages)>, "Non-deterministic data source");
+  for (const auto& [PageIndex, Entrypoints] : LookupCache.CodePages) {
+    uint64_t PageAddr = (PageIndex << 12) - SourceBinary.FileStartVA;
+    ::write(fd, &PageAddr, sizeof(PageAddr));
     uint64_t NumEntrypoints = Entrypoints.size();
     ::write(fd, &NumEntrypoints, sizeof(NumEntrypoints));
-    ::write(fd, Entrypoints.data(), Entrypoints.size() * sizeof(Entrypoints[0]));
+    for (uint64_t Entrypoint : Entrypoints) {
+      Entrypoint -= SourceBinary.FileStartVA;
+      ::write(fd, &Entrypoint, sizeof(Entrypoint));
+    }
   }
 
   return true;
 }
 
+bool CodeCache::LoadData(Core::InternalThreadState* Thread, std::byte* MappedCacheFile, const ExecutableFileSectionInfo& BinarySection) {
+  if (!EnableCodeCaching) {
+    return true;
+  }
+
+  namespace ranges = std::ranges;
+
+  // Read file header
+  CodeCacheHeader header {};
+  ::memcpy(&header, MappedCacheFile, sizeof(header));
+  MappedCacheFile += sizeof(header);
+
+  LogMan::Msg::IFmt("Cache load: {:5} blocks; base={:#14x}; off={:#9x}-{:#09x}; {:016x} {}", header.NumBlocks, BinarySection.FileStartVA,
+                    BinarySection.BeginVA - BinarySection.FileStartVA, BinarySection.EndVA - BinarySection.FileStartVA,
+                    BinarySection.FileInfo.FileId, BinarySection.FileInfo.Filename);
+
+  if (!ranges::equal(header.Magic, header.ExpectedMagic)) {
+    LogMan::Msg::EFmt("Invalid cache file header");
+    return false;
+  }
+
+  char ExpectedVersion[8] = GIT_SHORT_HASH;
+  ranges::fill(ranges::find(ExpectedVersion, 0), std::end(ExpectedVersion), 0);
+  if (!ranges::equal(header.FEXVersion, ExpectedVersion)) {
+    LogMan::Msg::IFmt("Cache generated from old FEX version {}, current is {}; skipping", fmt::join(header.FEXVersion, ""),
+                      fmt::join(ExpectedVersion, ""));
+    return false;
+  }
+
+  if (header.NumBlocks == 0) {
+    // Valid caches are never empty
+    LogMan::Msg::IFmt("Code cache empty, aborting");
+    return false;
+  }
+
+  // Read guest<->host block mappings
+  using BlockListEntry = decltype(GuestToHostMap::BlockList)::value_type;
+  fextl::vector<BlockListEntry> BlockList(header.NumBlocks);
+  {
+    for (auto& BlockPtr : BlockList) {
+      ::memcpy(&BlockPtr.first, MappedCacheFile, sizeof(BlockPtr.first));
+      MappedCacheFile += sizeof(BlockPtr.first);
+      ::memcpy(&BlockPtr.second.HostCode, MappedCacheFile, sizeof(BlockPtr.second.HostCode));
+      MappedCacheFile += sizeof(BlockPtr.second.HostCode);
+      uint64_t NumGuestPages;
+      ::memcpy(&NumGuestPages, MappedCacheFile, sizeof(NumGuestPages));
+      MappedCacheFile += sizeof(NumGuestPages);
+
+      BlockPtr.second.CodePages.resize(NumGuestPages);
+      ::memcpy(BlockPtr.second.CodePages.data(), MappedCacheFile, std::span {BlockPtr.second.CodePages}.size_bytes());
+      MappedCacheFile += std::span {BlockPtr.second.CodePages}.size_bytes();
+    }
+
+    // Consistency check: VMA regions at the top and end should belong to the same file
+    auto [min_val, max_val] = ranges::minmax_element(BlockList, std::less {}, &decltype(BlockList)::value_type::first);
+    auto MinBound = CTX.SyscallHandler->LookupExecutableFileSection(Thread, min_val->first + BinarySection.FileStartVA);
+    auto MaxBound = CTX.SyscallHandler->LookupExecutableFileSection(Thread, max_val->first + BinarySection.FileStartVA);
+    if (&MinBound->FileInfo != &BinarySection.FileInfo || &MaxBound->FileInfo != &BinarySection.FileInfo) {
+      ERROR_AND_DIE_FMT("Cached blocks offsets {:#x}-{:#x} out of bounds for guest library {} ({:016x} @ {:#x}) while trying to load "
+                        "section {:#x}-{:#x}!",
+                        min_val->first, max_val->first, BinarySection.FileInfo.Filename, BinarySection.FileInfo.FileId,
+                        BinarySection.FileStartVA, BinarySection.BeginVA, BinarySection.EndVA);
+    }
+
+    // Constrain BlockList to the given ExecutableFileSectionInfo
+    LOGMAN_THROW_A_FMT(ranges::is_sorted(BlockList, [](auto& a, auto& b) { return a.first < b.first; }), "Expected sorted block list");
+    auto begin = ranges::lower_bound(BlockList, BinarySection.BeginVA - BinarySection.FileStartVA, std::less {}, &BlockListEntry::first);
+    auto end =
+      ranges::upper_bound(begin, BlockList.end(), BinarySection.EndVA - BinarySection.FileStartVA - 1, std::less {}, &BlockListEntry::first);
+    BlockList.erase(end, BlockList.end());
+    BlockList.erase(BlockList.begin(), begin);
+    if (BlockList.empty()) {
+      // Not an error since there is just no data to load
+      LogMan::Msg::IFmt("No blocks cached in this range, aborting");
+      return true;
+    }
+  }
+
+  // Read relocations
+  fextl::vector<FEXCore::CPU::Relocation> Relocations(header.NumRelocations, FEXCore::CPU::Relocation::Default());
+  ::memcpy(Relocations.data(), MappedCacheFile, Relocations.size() * sizeof(Relocations[0]));
+  MappedCacheFile += Relocations.size() * sizeof(Relocations[0]);
+
+  // Pad to next page in file, which contains CodeBuffer data
+  MappedCacheFile = reinterpret_cast<std::byte*>(AlignUp(reinterpret_cast<uintptr_t>(MappedCacheFile), Utils::FEX_PAGE_SIZE));
+
+  // Prepare CodeBuffer: Page aligned and big enough to hold all cached data
+  auto Lock = std::unique_lock {CTX.CodeBufferWriteMutex};
+  if (Thread) {
+    if (auto Prev = Thread->CPUBackend->CheckCodeBufferUpdate()) {
+      Allocator::VirtualDontNeed(Thread->CallRetStackBase, FEXCore::Core::InternalThreadState::CALLRET_STACK_SIZE);
+      auto lk = Thread->LookupCache->AcquireWriteLock();
+      Thread->LookupCache->ChangeGuestToHostMapping(*Prev, *CTX.GetLatest()->LookupCache, lk);
+    }
+  }
+
+  auto CodeBuffer = CTX.GetLatest();
+  LOGMAN_THROW_A_FMT(header.CodeBufferSize <= CodeBuffer->Size, "CodeBuffer too small to load code cache");
+  LOGMAN_THROW_A_FMT(reinterpret_cast<uintptr_t>(CodeBuffer->Ptr) % 0x1000 == 0, "Expected CodeBuffer base to be page-aligned");
+  const auto Delta = AlignUp(CTX.LatestOffset, 0x1000) - CTX.LatestOffset;
+  CTX.LatestOffset += Delta;
+
+  while (CTX.LatestOffset + header.CodeBufferSize > CodeBuffer->Size - Utils::FEX_PAGE_SIZE) {
+    if (Thread) {
+      CTX.ClearCodeCache(Thread);
+      CodeBuffer = CTX.GetLatest();
+      LogMan::Msg::IFmt("Increased code buffer size to {} MiB for cache load", CodeBuffer->Size / 1024 / 1024);
+    } else {
+      ERROR_AND_DIE_FMT("Cannot extend codebuffer without thread!");
+    }
+  }
+
+  // Read CodeBuffer data from file. Make sure the destination is page-aligned.
+  // TODO: Only load the data needed for the selected section
+  auto CodeBufferRange = std::as_writable_bytes(std::span {CodeBuffer->Ptr, CodeBuffer->Size}).subspan(CTX.LatestOffset, header.CodeBufferSize);
+  ::memcpy(CodeBufferRange.data(), MappedCacheFile, header.CodeBufferSize);
+  MappedCacheFile += header.CodeBufferSize;
+  CTX.LatestOffset += header.CodeBufferSize;
+
+  // Apply FEX relocations
+  auto Ret = ApplyCodeRelocations(BinarySection.FileStartVA, CodeBufferRange, Relocations, false);
+  LOGMAN_THROW_A_FMT(Ret == true, "Failed to apply code cache relocations");
+
+  {
+    auto& LookupCache = *CodeBuffer->LookupCache;
+    auto WriteLock = LookupCache.AcquireWriteLock();
+
+    // Register blocks to LookupCache
+    for (auto& [Guest, Host] : BlockList) {
+      for (auto& CodePage : Host.CodePages) {
+        CodePage += BinarySection.FileStartVA;
+      }
+      auto HostCode = reinterpret_cast<void*>(Host.HostCode + reinterpret_cast<uintptr_t>(CodeBufferRange.data()));
+      LookupCache.AddBlockMapping(Guest + BinarySection.FileStartVA, std::move(Host.CodePages), HostCode, WriteLock);
+    }
+
+    // Register loaded code ranges
+    fextl::vector<uint64_t> Entrypoints;
+    for (uint32_t i = 0; i < header.NumCodePages; ++i) {
+      uint64_t CodePage;
+      memcpy(&CodePage, MappedCacheFile, sizeof(CodePage));
+      CodePage += BinarySection.FileStartVA;
+      MappedCacheFile += sizeof(CodePage);
+
+      uint64_t NumEntrypoints;
+      memcpy(&NumEntrypoints, MappedCacheFile, sizeof(NumEntrypoints));
+      MappedCacheFile += sizeof(NumEntrypoints);
+
+      Entrypoints.resize(NumEntrypoints);
+      memcpy(Entrypoints.data(), MappedCacheFile, NumEntrypoints * sizeof(Entrypoints[0]));
+      MappedCacheFile += NumEntrypoints * sizeof(Entrypoints[0]);
+      for (auto& Entrypoint : Entrypoints) {
+        Entrypoint += BinarySection.FileStartVA;
+      }
+
+      if (LookupCache.AddBlockExecutableRange(Entrypoints, CodePage, FEXCore::Utils::FEX_PAGE_SIZE, WriteLock)) {
+        CTX.SyscallHandler->MarkGuestExecutableRange(Thread, CodePage, FEXCore::Utils::FEX_PAGE_SIZE);
+      }
+    }
+  }
+
+  if (EnableCodeCacheValidation) {
+    fextl::set<uint64_t> GuestBlocks, HostBlocks;
+    for (auto& [Guest, Host] : BlockList) {
+      GuestBlocks.insert(Guest + BinarySection.FileStartVA);
+      HostBlocks.insert(Host.HostCode);
+    }
+
+    Validate(BinarySection, std::move(GuestBlocks), HostBlocks, CodeBufferRange);
+  }
+
+  return true;
+}
+
+void CodeCache::Validate(const ExecutableFileSectionInfo& Section, fextl::set<uint64_t> GuestBlocks, const fextl::set<uint64_t>& HostBlocks,
+                         std::span<std::byte> CachedCode) {
+  LOGMAN_THROW_A_FMT(!HostBlocks.empty(), "Tried to validate without any host blocks");
+  // Skip any cached data before the first host block
+  CachedCode = CachedCode.subspan(*HostBlocks.begin() - sizeof(CPU::CPUBackend::JITCodeHeader));
+
+  if (!ValidationCTX) {
+    ValidationCTX.reset(static_cast<ContextImpl*>(FEXCore::Context::Context::CreateNewContext(CTX.HostFeatures).release()));
+    ValidationCTX->SetSignalDelegator(CTX.SignalDelegation);
+    ValidationCTX->SetSyscallHandler(CTX.SyscallHandler);
+    ValidationCTX->SetThunkHandler(CTX.ThunkHandler);
+    if (!ValidationCTX->InitCore()) {
+      ERROR_AND_DIE_FMT("Failed to create cache load validation context");
+    }
+
+    ValidationThread.reset(ValidationCTX->CreateThread(0, 0, nullptr));
+
+    auto Frame = ValidationThread->CurrentFrame;
+    Frame->State.segment_arrays[FEXCore::Core::CPUState::SEGMENT_ARRAY_INDEX_GDT] = &ValidationGDT[0];
+    Frame->State.segment_arrays[FEXCore::Core::CPUState::SEGMENT_ARRAY_INDEX_LDT] = &ValidationGDT[0];
+    Frame->State.cs_idx = 0;
+    Frame->State.cs_cached = 0;
+
+    if (ValidationCTX->Config.Is64BitMode()) {
+      ValidationGDT[0].L = 1; // L = Long Mode = 64-bit
+      ValidationGDT[0].D = 0; // D = Default Operand Size = Reserved
+    } else {
+      ValidationGDT[0].L = 0; // L = Long Mode = 32-bit
+      ValidationGDT[0].D = 1; // D = Default Operand Size = 32-bit
+    }
+  }
+
+  auto NewCodeBuffer = ValidationCTX->GetLatest();
+
+  std::span<std::byte> CodeBufferRangeRef =
+    std::as_writable_bytes(std::span {NewCodeBuffer->Ptr, NewCodeBuffer->Ptr + NewCodeBuffer->Size}).subspan(0, CachedCode.size_bytes());
+
+  while (!GuestBlocks.empty()) {
+    auto [CompiledBlocks, _, _2, _3, _4] = ValidationCTX->CompileCode(ValidationThread.get(), *GuestBlocks.begin(), 0 /* TODO: Set MaxInst? */);
+    for (auto& Entry : CompiledBlocks.EntryPoints) {
+      GuestBlocks.erase(Entry.first);
+    }
+  }
+
+  // Patch FEX-internal function addresses with values from the main Context to ensure the code blocks are comparable
+  auto NewRelocations = ValidationThread->CPUBackend->TakeRelocations(Section.FileStartVA);
+  NewRelocations.erase(std::remove_if(NewRelocations.begin(), NewRelocations.end(), [](const CPU::Relocation& Reloc) {
+    return Reloc.Header.Type != CPU::RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL && Reloc.Header.Type != CPU::RelocationTypes::RELOC_NAMED_THUNK_MOVE;
+  }));
+  (void)ApplyCodeRelocations(Section.FileStartVA, CodeBufferRangeRef, NewRelocations, false);
+
+  if (ValidationCTX->LatestOffset <= CodeBufferRangeRef.size()) {
+    // Reference compilation produced fewer bytes than our cache, so validation is going to fail.
+    // Make sure we don't output any garbage bytes though.
+    CodeBufferRangeRef = CodeBufferRangeRef.subspan(0, ValidationCTX->LatestOffset);
+  }
+
+  auto [Mismatch, _] = std::mismatch(CodeBufferRangeRef.begin(), CodeBufferRangeRef.end(), CachedCode.begin());
+  if (Mismatch != CodeBufferRangeRef.end()) {
+    // Align down to instruction size
+    auto Idx = AlignDown(std::distance(CodeBufferRangeRef.begin(), Mismatch), 4);
+
+    auto BlockIt = std::prev(HostBlocks.lower_bound(*HostBlocks.begin() + Idx + 1));
+    std::optional<uint64_t> GuestBlockAddr;
+    std::optional<uint64_t> GuestBlockAddrRef;
+    if (BlockIt != HostBlocks.end()) {
+      for (int i : {0, 1}) {
+        std::span Buffer = (i == 0 ? CachedCode : CodeBufferRangeRef);
+
+        // Second instruction is always a constant load for relative offset to the (multi)block start
+        int32_t addr = (*reinterpret_cast<uint32_t*>(&Buffer[*BlockIt - *HostBlocks.begin() + 4]) & 0x3ff'ffe0) << 11;
+        addr >>= 14;
+        auto header = reinterpret_cast<CPU::CPUBackend::JITCodeHeader*>(&Buffer[*BlockIt - *HostBlocks.begin() + 4 + addr]);
+        auto tail = reinterpret_cast<CPU::CPUBackend::JITCodeTail*>(reinterpret_cast<uintptr_t>(header) + header->OffsetToBlockTail);
+        (i == 0 ? GuestBlockAddr : GuestBlockAddrRef) = tail->RIP - Section.FileStartVA;
+        LogMan::Msg::EFmt("Recorded rip {}: {:#x} (offset {:#x})", i, tail->RIP, tail->RIP - Section.FileStartVA);
+
+        if (i == 1) {
+          if (tail->RIP >= Section.BeginVA && tail->RIP < Section.EndVA) {
+            auto [IRView, TotalInstructions, TotalInstructionsLength, StartAddr, Length, _] =
+              ValidationCTX->GenerateIR(ValidationThread.get(), tail->RIP, false, FEXCore::Config::Get_MAXINST());
+            fextl::stringstream ss;
+            FEXCore::IR::Dump(&ss, &*IRView);
+            LogMan::Msg::EFmt("IR:\n{}", ss.str());
+          } else {
+            LogMan::Msg::EFmt("Can't dump IR for out-of-range RIP {:#x}", tail->RIP);
+          }
+        }
+      }
+    }
+
+    fextl::string GuestBlockInfo = "UNKNOWN";
+    if (GuestBlockAddr) {
+      GuestBlockInfo = fextl::fmt::format("{:#x}", GuestBlockAddr.value());
+    }
+    if (GuestBlockAddr != GuestBlockAddrRef) {
+      GuestBlockInfo += " (MISMATCH)";
+    }
+    ERROR_AND_DIE_FMT("Cache validation failed at offset {:#x}: {:02x} <-> {:02x} (at {} <-> {}, guest block {})", Idx,
+                      fmt::join(CachedCode.subspan(Idx, 4), ""), fmt::join(CodeBufferRangeRef.subspan(Idx, 4), ""),
+                      fmt::ptr(CachedCode.data()), fmt::ptr(CodeBufferRangeRef.data()), GuestBlockInfo);
+  }
+
+  // Reset Context state for next validation
+  ValidationThread->LookupCache->ClearCache(ValidationThread->LookupCache->AcquireWriteLock());
+  ValidationCTX->LatestOffset = 0;
+
+  LogMan::Msg::IFmt("\tSuccessfully validated cache");
+}
+
 bool CodeCache::ApplyCodeRelocations(uint64_t GuestEntry, std::span<std::byte> Code,
                                      std::span<const FEXCore::CPU::Relocation> EntryRelocations, bool ForStorage) {
   CPU::Arm64Emitter Emitter(&CTX, Code.data(), Code.size_bytes());
@@ -348,8 +633,9 @@ bool CodeCache::ApplyCodeRelocations(uint64_t GuestEntry, std::span<std::byte> C
       if (Pointer == ~0ULL) {
         return false;
       }
-
-      Emitter.LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(Reloc.NamedThunkMove.RegisterIndex), Pointer, true);
+      // Pointers are required to fit within 48-bit VA space.
+      Emitter.LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(Reloc.NamedThunkMove.RegisterIndex), Pointer,
+                           CPU::Arm64Emitter::PadType::DOPAD, 6);
       break;
     }
     case FEXCore::CPU::RelocationTypes::RELOC_GUEST_RIP_LITERAL: {
@@ -358,7 +644,9 @@ bool CodeCache::ApplyCodeRelocations(uint64_t GuestEntry, std::span<std::byte> C
     }
     case FEXCore::CPU::RelocationTypes::RELOC_GUEST_RIP_MOVE: {
       uint64_t Pointer = Reloc.GuestRIP.GuestRIP + GuestEntry;
-      Emitter.LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(Reloc.GuestRIP.RegisterIndex), Pointer, true);
+      // Pointers are required to fit within 48-bit VA space.
+      Emitter.LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(Reloc.GuestRIP.RegisterIndex), Pointer,
+                           CPU::Arm64Emitter::PadType::DOPAD, 6);
       break;
     }
 

FEXCore/Source/Interface/Core/Core.cpp

@@ -345,7 +345,7 @@ bool ContextImpl::InitCore() {
   // Set up the SignalDelegator config since core is initialized.
   SignalDelegation->SetConfig(Dispatcher->MakeSignalDelegatorConfig());
 
-#if defined(_WIN32) && !defined(_M_ARM_64EC)
+#if defined(_WIN32) && !defined(ARCHITECTURE_arm64ec)
   // WOW64 always needs the interrupt fault check to be enabled.
   Config.NeedsPendingInterruptFaultCheck = true;
 #endif
@@ -363,6 +363,9 @@ void ContextImpl::HandleCallback(FEXCore::Core::InternalThreadState* Thread, uin
 }
 
 void ContextImpl::ExecuteThread(FEXCore::Core::InternalThreadState* Thread) {
+  // Update the thread pointer for Thunk return to the latest.
+  Thread->CurrentFrame->Pointers.ThunkCallbackRet = SignalDelegation->GetThunkCallbackRET();
+
   Dispatcher->ExecuteDispatch(Thread->CurrentFrame);
 
   // If it is the parent thread that died then just leave
@@ -379,7 +382,7 @@ void ContextImpl::InitializeCompiler(FEXCore::Core::InternalThreadState* Thread)
   Thread->CurrentFrame->State.L1Pointer = Thread->LookupCache->GetL1Pointer();
   Thread->CurrentFrame->State.L1Mask = Thread->LookupCache->GetScaledL1PointerMask();
 
-  Thread->CurrentFrame->Pointers.Common.L2Pointer = Thread->LookupCache->GetPagePointer();
+  Thread->CurrentFrame->Pointers.L2Pointer = Thread->LookupCache->GetPagePointer();
 
   Dispatcher->InitThreadPointers(Thread);
 
@@ -655,7 +658,8 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
               LogMan::Msg::EFmt("Invalid or Unknown instruction: {} 0x{:x}", TableInfo->Name ?: "UND", Block.Entry - GuestRIP);
             }
 
-            if (Block.BlockStatus == Frontend::Decoder::DecodedBlockStatus::INVALID_INST) {
+            if (Block.BlockStatus == Frontend::Decoder::DecodedBlockStatus::INVALID_INST ||
+                Block.BlockStatus == Frontend::Decoder::DecodedBlockStatus::BAD_RELOCATION) {
               Thread->OpDispatcher->InvalidOp(DecodedInfo);
             } else {
               Thread->OpDispatcher->NoExecOp(DecodedInfo);
@@ -722,7 +726,7 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
 
 ContextImpl::CompileCodeResult ContextImpl::CompileCode(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestRIP, uint64_t MaxInst) {
   if (SourcecodeResolver && Config.GDBSymbols()) {
-    auto MappedSection = SyscallHandler->LookupExecutableFileSection(*Thread, GuestRIP);
+    auto MappedSection = SyscallHandler->LookupExecutableFileSection(Thread, GuestRIP);
     if (MappedSection) {
       MappedSection->FileInfo.SourcecodeMap =
         SourcecodeResolver->GenerateMap(MappedSection->FileInfo.Filename, CodeMap::GetBaseFilename(MappedSection->FileInfo, false));
@@ -803,7 +807,7 @@ uintptr_t ContextImpl::CompileBlock(FEXCore::Core::CpuStateFrame* Frame, uint64_
   if (Config.BlockJITNaming()) {
     auto FragmentBasePtr = CompiledCode.BlockBegin;
 
-    auto GuestRIPLookup = SyscallHandler->LookupExecutableFileSection(*Thread, GuestRIP);
+    auto GuestRIPLookup = SyscallHandler->LookupExecutableFileSection(Thread, GuestRIP);
 
     if (DebugData->Subblocks.size()) {
       for (auto& Subblock : DebugData->Subblocks) {
@@ -826,7 +830,7 @@ uintptr_t ContextImpl::CompileBlock(FEXCore::Core::CpuStateFrame* Frame, uint64_
   }
 
   if (Config.LibraryJITNaming() || Config.GDBSymbols()) {
-    auto MappedSection = SyscallHandler->LookupExecutableFileSection(*Thread, GuestRIP);
+    auto MappedSection = SyscallHandler->LookupExecutableFileSection(Thread, GuestRIP);
     if (MappedSection) {
       if (Config.LibraryJITNaming()) {
         Symbols.RegisterNamedRegion(Thread->SymbolBuffer.get(), CodePtr, DebugData->HostCodeSize, MappedSection->FileInfo.Filename);
@@ -865,7 +869,7 @@ uintptr_t ContextImpl::CompileBlock(FEXCore::Core::CpuStateFrame* Frame, uint64_
   }
 
   if (CodeMapWriter) {
-    auto Region = SyscallHandler->LookupExecutableFileSection(*Thread, GuestRIP);
+    auto Region = SyscallHandler->LookupExecutableFileSection(Thread, GuestRIP);
     if (Region && Region->FileStartVA != 0) {
       CodeMapWriter->AppendBlock(*Region, GuestRIP);
     }
@@ -967,6 +971,7 @@ void ContextImpl::AddThunkTrampolineIRHandler(uintptr_t Entrypoint, uintptr_t Gu
 
       const auto GPRSize = this->Config.Is64BitMode ? IR::OpSize::i64Bit : IR::OpSize::i32Bit;
 
+      // Thunk entry-points don't get cached, don't need to be padded.
       if (GPRSize == IR::OpSize::i64Bit) {
         IR::Ref R = emit->_StoreRegister(emit->Constant(Entrypoint), GPRSize);
         R->Reg = IR::PhysicalRegister(IR::RegClass::GPRFixed, X86State::REG_R11).Raw;
@@ -1037,6 +1042,5 @@ void ContextImpl::MonoBackpatcherWrite(FEXCore::Core::CpuStateFrame* Frame, uint
 
 void ContextImpl::ConfigureAOTGen(FEXCore::Core::InternalThreadState* Thread, fextl::set<uint64_t>* ExternalBranches, uint64_t SectionMaxAddress) {
   Thread->FrontendDecoder->SetExternalBranches(ExternalBranches);
-  Thread->FrontendDecoder->SetSectionMaxAddress(SectionMaxAddress);
 }
 } // namespace FEXCore::Context

FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp

@@ -96,7 +96,7 @@ void Dispatcher::EmitDispatcher() {
 
   ARMEmitter::BiDirectionalLabel LoopTop {};
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
   (void)b(&LoopTop);
 
   AbsoluteLoopTopAddressEnterECFillSRA = GetCursorAddress<uint64_t>();
@@ -147,7 +147,7 @@ void Dispatcher::EmitDispatcher() {
   // Load in our RIP
   ldr(RipReg, STATE_PTR(CpuStateFrame, State.rip));
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
   // Clobbers TMP1/2
   // Check the EC code bitmap incase we need to exit the JIT to call into native code.
   ARMEmitter::ForwardLabel l_NotECCode;
@@ -159,13 +159,13 @@ void Dispatcher::EmitDispatcher() {
   ldr(TMP1, TMP1, TMP2, ARMEmitter::ExtendedType::LSL_64, 0);
   lsr(ARMEmitter::Size::i64Bit, TMP2, RipReg, 12);
   lsrv(ARMEmitter::Size::i64Bit, TMP1, TMP1, TMP2);
-  tbz(TMP1, 0, &l_NotECCode);
+  (void)tbz(TMP1, 0, &l_NotECCode);
 
   str(REG_CALLRET_SP, STATE_PTR(CpuStateFrame, State.callret_sp));
 
   add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, StaticRegisters[X86State::REG_RSP], 0);
   mov(EC_CALL_CHECKER_PC_REG, RipReg);
-  ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC));
+  ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.ExitFunctionEC));
   br(TMP2);
 
   (void)Bind(&l_NotECCode);
@@ -181,7 +181,7 @@ void Dispatcher::EmitDispatcher() {
   } else {
     // This is the block cache lookup routine
     // It matches what is going on it LookupCache.h::FindBlock
-    ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.L2Pointer));
+    ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.L2Pointer));
 
     // Mask the address by the virtual address size so we can check for aliases
     uint64_t VirtualMemorySize = CTX->Config.VirtualMemSize;
@@ -259,7 +259,7 @@ void Dispatcher::EmitDispatcher() {
     str(TMP2, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
 #endif
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
     ldr(TMP2, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
     LoadConstant(ARMEmitter::Size::i32Bit, TMP1, 1);
     strb(TMP1.W(), TMP2, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
@@ -267,7 +267,7 @@ void Dispatcher::EmitDispatcher() {
 
     Body();
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
     ldr(TMP2, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
     strb(ARMEmitter::WReg::zr, TMP2, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
 #endif
@@ -291,7 +291,7 @@ void Dispatcher::EmitDispatcher() {
       mov(ARMEmitter::XReg::x0, STATE);
       mov(ARMEmitter::XReg::x1, ARMEmitter::XReg::lr);
 
-      ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionLink));
+      ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, Pointers.ExitFunctionLink));
       if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
         GenerateIndirectRuntimeCall<uintptr_t, void*, void*>(ARMEmitter::Reg::r2);
       } else {
@@ -488,7 +488,7 @@ void Dispatcher::EmitDispatcher() {
 
     // Now push the callback return trampoline to the guest stack
     // Guest will be misaligned because calling a thunk won't correct the guest's stack once we call the callback from the host
-    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, CTX->SignalDelegation->GetThunkCallbackRET());
+    ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, Pointers.ThunkCallbackRet));
 
     ldr(ARMEmitter::XReg::x2, STATE_PTR(CpuStateFrame, State.gregs[X86State::REG_RSP]));
     sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::r2, CTX->Config.Is64BitMode ? 16 : 12);
@@ -544,8 +544,8 @@ void Dispatcher::EmitDispatcher() {
     return Address;
   };
 
-  LUDIVHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.AArch64.LUDIV));
-  LDIVHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.AArch64.LDIV));
+  LUDIVHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.LUDIV));
+  LDIVHandlerAddress = EmitLongALUOpHandler(STATE_PTR(CpuStateFrame, Pointers.LDIV));
 
   // Interpreter fallbacks
   {
@@ -1086,27 +1086,25 @@ uint64_t Dispatcher::GenerateABICall(FallbackABI ABI) {
 void Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState* Thread) {
   // Setup dispatcher specific pointers that need to be accessed from JIT code
   {
-    auto& Common = Thread->CurrentFrame->Pointers.Common;
+    auto& Ptrs = Thread->CurrentFrame->Pointers;
 
-    Common.DispatcherLoopTop = AbsoluteLoopTopAddress;
-    Common.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA;
-    Common.DispatcherLoopTopEnterEC = AbsoluteLoopTopAddressEnterEC;
-    Common.DispatcherLoopTopEnterECFillSRA = AbsoluteLoopTopAddressEnterECFillSRA;
-    Common.ExitFunctionLinker = ExitFunctionLinkerAddress;
-    Common.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA;
-    Common.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA;
-    Common.GuestSignal_SIGILL = GuestSignal_SIGILL;
-    Common.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP;
-    Common.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV;
-    Common.SignalReturnHandler = SignalHandlerReturnAddress;
-    Common.SignalReturnHandlerRT = SignalHandlerReturnAddressRT;
-
-    auto& AArch64 = Thread->CurrentFrame->Pointers.AArch64;
-    AArch64.LUDIVHandler = LUDIVHandlerAddress;
-    AArch64.LDIVHandler = LDIVHandlerAddress;
+    Ptrs.DispatcherLoopTop = AbsoluteLoopTopAddress;
+    Ptrs.DispatcherLoopTopFillSRA = AbsoluteLoopTopAddressFillSRA;
+    Ptrs.DispatcherLoopTopEnterEC = AbsoluteLoopTopAddressEnterEC;
+    Ptrs.DispatcherLoopTopEnterECFillSRA = AbsoluteLoopTopAddressEnterECFillSRA;
+    Ptrs.ExitFunctionLinker = ExitFunctionLinkerAddress;
+    Ptrs.ThreadStopHandlerSpillSRA = ThreadStopHandlerAddressSpillSRA;
+    Ptrs.ThreadPauseHandlerSpillSRA = ThreadPauseHandlerAddressSpillSRA;
+    Ptrs.GuestSignal_SIGILL = GuestSignal_SIGILL;
+    Ptrs.GuestSignal_SIGTRAP = GuestSignal_SIGTRAP;
+    Ptrs.GuestSignal_SIGSEGV = GuestSignal_SIGSEGV;
+    Ptrs.SignalReturnHandler = SignalHandlerReturnAddress;
+    Ptrs.SignalReturnHandlerRT = SignalHandlerReturnAddressRT;
+    Ptrs.LUDIVHandler = LUDIVHandlerAddress;
+    Ptrs.LDIVHandler = LDIVHandlerAddress;
 
     // Fill in the fallback handlers
-    InterpreterOps::FillFallbackIndexPointers(Common.FallbackHandlerPointers, &ABIPointers[0]);
+    InterpreterOps::FillFallbackIndexPointers(Ptrs.FallbackHandlerPointers, &ABIPointers[0]);
   }
 }
 

FEXCore/Source/Interface/Core/Frontend.cpp

@@ -132,7 +132,7 @@ std::optional<uint8_t> Decoder::PeekByte(uint8_t Offset) {
   }
 }
 
-uint64_t Decoder::ReadData(uint8_t Size) {
+std::pair<uint64_t, bool> Decoder::ReadData(uint8_t Size) {
   LOGMAN_THROW_A_FMT(Size != 0 && Size <= sizeof(uint64_t), "Unknown data size to read");
 
   uint64_t Res = 0;
@@ -154,7 +154,21 @@ uint64_t Decoder::ReadData(uint8_t Size) {
   SkipBytes(Size);
 #endif
 
-  return Res;
+  if (Relocations) {
+    uint32_t SectionOffset = static_cast<uint32_t>(Address - SectionMinAddress);
+    if (auto It = Relocations->find(SectionOffset); It != Relocations->end()) {
+      if (It->second == GuestRelocationType::Rel32 && Size == 4) {
+        return {static_cast<int64_t>(static_cast<int32_t>(Res) - static_cast<int32_t>(EntryPoint)), true};
+      } else if (It->second == GuestRelocationType::Rel64 && Size == 8) {
+        return {static_cast<int64_t>(Res) - static_cast<int64_t>(EntryPoint), true};
+      } else {
+        HitBadRelocation = true;
+        Res = 0;
+      }
+    }
+  }
+
+  return {Res, false};
 }
 
 void Decoder::DecodeModRM_16(X86Tables::DecodedOperand* Operand, X86Tables::ModRMDecoded ModRM) {
@@ -186,7 +200,9 @@ void Decoder::DecodeModRM_16(X86Tables::DecodedOperand* Operand, X86Tables::ModR
     DisplacementSize = 1;
   }
   if (DisplacementSize) {
-    Literal = ReadData(DisplacementSize);
+    bool IsRelocation = false;
+    std::tie(Literal, IsRelocation) = ReadData(DisplacementSize);
+    LOGMAN_THROW_A_FMT(!IsRelocation, "1/2 byte relocations unsupported");
     if (DisplacementSize == 1) {
       Literal = static_cast<int8_t>(Literal);
     }
@@ -292,7 +308,10 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand* Operand, X86Tables::ModR
     LOGMAN_THROW_A_FMT(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
 
     if (Displacement) {
-      uint64_t Literal = ReadData(Displacement);
+      auto [Literal, IsRelocation] = ReadData(Displacement);
+      if (IsRelocation) {
+        Operand->Type = DecodedOperand::OpType::SIBRelocation;
+      }
       if (Displacement == 1) {
         Literal = static_cast<int8_t>(Literal);
       }
@@ -302,10 +321,9 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand* Operand, X86Tables::ModR
     // Explained in Table 1-14. "Operand Addressing Using ModRM and SIB Bytes"
     if (ModRM.rm == 0b101) {
       // 32bit Displacement
-      const uint32_t Literal = ReadData(4);
-
-      Operand->Type = DecodedOperand::OpType::RIPRelative;
-      Operand->Data.RIPLiteral.Value.u = Literal;
+      auto [Literal, IsRelocation] = ReadData(4);
+      Operand->Type = IsRelocation ? DecodedOperand::OpType::RIPRelativeRelocation : DecodedOperand::OpType::RIPRelative;
+      Operand->Data.RIPLiteral.Value = Literal;
     } else {
       // Register-direct addressing
       Operand->Type = DecodedOperand::OpType::GPRDirect;
@@ -313,12 +331,12 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand* Operand, X86Tables::ModR
     }
   } else {
     uint8_t DisplacementSize = ModRM.mod == 1 ? 1 : 4;
-    uint32_t Literal = ReadData(DisplacementSize);
+    auto [Literal, IsRelocation] = ReadData(DisplacementSize);
     if (DisplacementSize == 1) {
       Literal = static_cast<int8_t>(Literal);
     }
 
-    Operand->Type = DecodedOperand::OpType::GPRIndirect;
+    Operand->Type = IsRelocation ? DecodedOperand::OpType::GPRIndirectRelocation : DecodedOperand::OpType::GPRIndirect;
     Operand->Data.GPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);
     Operand->Data.GPRIndirect.Displacement = Literal;
   }
@@ -614,31 +632,29 @@ bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op,
   if (Bytes != 0) {
     LOGMAN_THROW_A_FMT(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
 
-    DecodeInst->Src[CurrentSrc].Data.Literal.Size = Bytes;
 
-    uint64_t Literal = ReadData(Bytes);
+    auto [Literal, IsRelocation] = ReadData(Bytes);
+    if (IsRelocation) {
+      DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::LiteralRelocation;
+      DecodeInst->Src[CurrentSrc].Data.LiteralRelocation.EntrypointOffset = Literal;
+    } else {
+      DecodeInst->Src[CurrentSrc].Data.Literal.Size = Bytes;
 
-    if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SRC_SEXT) || (DecodeFlags::GetSizeDstFlags(DecodeInst->Flags) == DecodeFlags::SIZE_64BIT &&
-                                                                          Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SRC_SEXT64BIT)) {
-      if (Bytes == 1) {
-        Literal = static_cast<int8_t>(Literal);
-      } else if (Bytes == 2) {
-        Literal = static_cast<int16_t>(Literal);
-      } else {
-        Literal = static_cast<int32_t>(Literal);
+      if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SRC_SEXT) ||
+          (DecodeFlags::GetSizeDstFlags(DecodeInst->Flags) == DecodeFlags::SIZE_64BIT &&
+           Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SRC_SEXT64BIT)) {
+        if (Bytes == 1) {
+          Literal = static_cast<int8_t>(Literal);
+        } else if (Bytes == 2) {
+          Literal = static_cast<int16_t>(Literal);
+        } else {
+          Literal = static_cast<int32_t>(Literal);
+        }
+        DecodeInst->Src[CurrentSrc].Data.Literal.Size = DestSize;
       }
-      DecodeInst->Src[CurrentSrc].Data.Literal.Size = DestSize;
-      DecodeInst->Src[CurrentSrc].Data.Literal.SignExtend = true;
-    }
 
-    DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::Literal;
-    DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal;
-    ++CurrentSrc;
-
-    if (Bytes == 8) [[unlikely]] {
-      DecodeInst->Src[CurrentSrc].Data.Literal.Size = 4;
       DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::Literal;
-      DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal >> 32;
+      DecodeInst->Src[CurrentSrc].Data.Literal.Value = Literal;
     }
 
     Bytes = 0;
@@ -832,6 +848,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
       switch (EscapeOp) {
       case 0x0F:
         [[unlikely]] { // 3DNow!
+          DecodeREXIfValid(-2);
           // 3DNow! Instruction Encoding: 0F 0F [ModRM] [SIB] [Displacement] [Opcode]
           // Decode ModRM
           uint8_t ModRMByte = ReadByte();
@@ -856,6 +873,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
           break;
         }
       case 0x38: { // F38 Table!
+        DecodeREXIfValid(-2);
         constexpr uint16_t PF_38_NONE = 0;
         constexpr uint16_t PF_38_66 = (1U << 0);
         constexpr uint16_t PF_38_F2 = (1U << 1);
@@ -881,11 +899,11 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
           DecodeInst->Flags &= ~DecodeFlags::FLAG_OPERAND_SIZE;
           DecodeFlags::PopOpAddrIf(&DecodeInst->Flags, DecodeFlags::FLAG_OPERAND_SIZE_LAST);
         }
-
         return NormalOpHeader(&FEXCore::X86Tables::H0F38TableOps[LocalOp], LocalOp);
         break;
       }
       case 0x3A: { // F3A Table!
+        DecodeREXIfValid(-2);
         constexpr uint16_t PF_3A_NONE = 0;
         constexpr uint16_t PF_3A_66 = (1 << 0);
         constexpr uint16_t PF_3A_REX = (1 << 1);
@@ -915,6 +933,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
           bool NoOverlay = (FEXCore::X86Tables::SecondBaseOps[EscapeOp].Flags & InstFlags::FLAGS_NO_OVERLAY) != 0;
           bool NoOverlay66 = (FEXCore::X86Tables::SecondBaseOps[EscapeOp].Flags & InstFlags::FLAGS_NO_OVERLAY66) != 0;
 
+          DecodeREXIfValid(-2);
           if (NoOverlay) { // This section of the table ignores prefix extention
             return NormalOpHeader(&FEXCore::X86Tables::SecondBaseOps[EscapeOp], EscapeOp);
           } else if (LastEscapePrefix == 0xF3) { // REP
@@ -994,29 +1013,9 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
         }
 
         if (Info->Type == FEXCore::X86Tables::TYPE_REX_PREFIX) {
-          DecodeInst->Flags |= DecodeFlags::FLAG_REX_PREFIX;
-
-          // Widening displacement
-          if (Op & 0b1000) {
-            DecodeInst->Flags |= DecodeFlags::FLAG_REX_WIDENING;
-            DecodeFlags::PushOpAddr(&DecodeInst->Flags, DecodeFlags::FLAG_WIDENING_SIZE_LAST);
-          }
-
-          // XGPR_B bit set
-          if (Op & 0b0001) {
-            DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_B;
-          }
-
-          // XGPR_X bit set
-          if (Op & 0b0010) {
-            DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_X;
-          }
-
-          // XGPR_R bit set
-          if (Op & 0b0100) {
-            DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_R;
-          }
+          DecodeInst->REXIndex = InstructionSize;
         } else {
+          DecodeREXIfValid();
           return NormalOpHeader(Info, Op);
         }
 
@@ -1032,18 +1031,51 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
   return true;
 }
 
+void Decoder::DecodeREXIfValid(int8_t ExpectedOffset) {
+  LOGMAN_THROW_A_FMT(ExpectedOffset < 0, "Expecting an negative offset for the REX offset!");
+  const int8_t REXIndex = InstructionSize + ExpectedOffset;
+
+  if (DecodeInst->REXIndex != 0 && DecodeInst->REXIndex == REXIndex) {
+    const uint8_t Op = Instruction[REXIndex - 1];
+    DecodeInst->Flags |= DecodeFlags::FLAG_REX_PREFIX;
+
+    // Widening displacement
+    if (Op & 0b1000) {
+      DecodeInst->Flags |= DecodeFlags::FLAG_REX_WIDENING;
+      DecodeFlags::PushOpAddr(&DecodeInst->Flags, DecodeFlags::FLAG_WIDENING_SIZE_LAST);
+    }
+
+    // XGPR_B bit set
+    if (Op & 0b0001) {
+      DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_B;
+    }
+
+    // XGPR_X bit set
+    if (Op & 0b0010) {
+      DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_X;
+    }
+
+    // XGPR_R bit set
+    if (Op & 0b0100) {
+      DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_R;
+    }
+  }
+}
+
 Decoder::DecodedBlockStatus Decoder::DecodeInstruction(uint64_t PC) {
   // Will be set if DecodeInstructionImpl tries to read non-executable memory
   HitNonExecutableRange = false;
+  HitBadRelocation = false;
   bool ErrorDuringDecoding = !DecodeInstructionImpl(PC);
 
-  if (ErrorDuringDecoding || HitNonExecutableRange) [[unlikely]] {
+  if (ErrorDuringDecoding || HitNonExecutableRange || HitBadRelocation) [[unlikely]] {
     // Put an invalid instruction in the stream so the core can raise SIGILL if hit
     // Error while decoding instruction. We don't know the table or instruction size
     DecodeInst->TableInfo = nullptr;
-    auto Result = ErrorDuringDecoding  ? DecodedBlockStatus::INVALID_INST :
-                  DecodeInst->InstSize ? DecodedBlockStatus::PARTIAL_DECODE_INST :
-                                         DecodedBlockStatus::NOEXEC_INST;
+    auto Result = ErrorDuringDecoding   ? DecodedBlockStatus::INVALID_INST :
+                  DecodeInst->InstSize  ? DecodedBlockStatus::PARTIAL_DECODE_INST :
+                  HitNonExecutableRange ? DecodedBlockStatus::NOEXEC_INST :
+                                          DecodedBlockStatus::BAD_RELOCATION;
     DecodeInst->InstSize = 0;
     return Result;
   } else if (!DecodeInst->TableInfo || (DecodeInst->TableInfo->Type == TYPE_INST && !DecodeInst->TableInfo->OpcodeDispatcher.OpDispatch)) {
@@ -1129,9 +1161,9 @@ void Decoder::BranchTargetInMultiblockRange() {
   // Forbid distant branches to have the cost code better match the guest code layout, avoiding massive (range-wise) code
   // blocks in highly fragmented guest code. Such branches are often not-taken branches to garbage in obfuscated code.
   constexpr uint64_t MAX_FORWARD_BRANCH_DIST = FEXCore::Utils::FEX_PAGE_SIZE * 4;
-  bool ValidMultiblockMember = TargetRIP >= SymbolMinAddress && TargetRIP < std::min(InstEnd + MAX_FORWARD_BRANCH_DIST, SymbolMaxAddress);
+  bool ValidMultiblockMember = TargetRIP >= EntryPoint && TargetRIP < std::min(InstEnd + MAX_FORWARD_BRANCH_DIST, SectionMaxAddress);
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
   ValidMultiblockMember = ValidMultiblockMember && !RtlIsEcCode(TargetRIP);
 #endif
 
@@ -1322,19 +1354,23 @@ void Decoder::DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState* Thre
   BlockInfo.Is64BitMode = CSSegment->L == 1;
   LOGMAN_THROW_A_FMT(BlockInfo.Is64BitMode == CTX->Config.Is64BitMode, "Expected operating mode to not change at runtime!");
 
-  // XXX: Load symbol data
-  SymbolAvailable = false;
   EntryPoint = PC;
   BlockInfo.EntryPoints = {PC};
   InstStream = _InstStream;
 
   uint64_t TotalInstructions {};
 
-  // If we don't have symbols available then we become a bit optimistic about multiblock ranges
-  if (!SymbolAvailable) {
-    // If we don't have a symbol available then assume all branches are valid for multiblock
-    SymbolMaxAddress = SectionMaxAddress;
-    SymbolMinAddress = EntryPoint;
+  SectionMinAddress = 0;
+  SectionMaxAddress = ~0ULL;
+  Relocations = nullptr;
+
+  if (CTX->GetCodeCache().IsGeneratingCache || EnableCodeCacheValidation) {
+    // If generating cache, attempt to load section bounds and relocations
+    if (auto SectionInfo = CTX->SyscallHandler->LookupExecutableFileSection(Thread, EntryPoint)) {
+      SectionMinAddress = SectionInfo->FileStartVA;
+      SectionMaxAddress = SectionInfo->EndVA;
+      Relocations = &SectionInfo->FileInfo.Relocations;
+    }
   }
 
   DecodedMinAddress = EntryPoint;
@@ -1447,9 +1483,10 @@ void Decoder::DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState* Thre
           EraseBlock = true;
         } else {
           LogMan::Msg::EFmt("{} instruction in entry block: {:X}",
-                            BlockIt->BlockStatus == DecodedBlockStatus::INVALID_INST ? "Invalid" :
-                            BlockIt->BlockStatus == DecodedBlockStatus::NOEXEC_INST  ? "NoExec" :
-                                                                                       "PartialDecode",
+                            BlockIt->BlockStatus == DecodedBlockStatus::INVALID_INST   ? "Invalid" :
+                            BlockIt->BlockStatus == DecodedBlockStatus::NOEXEC_INST    ? "NoExec" :
+                            BlockIt->BlockStatus == DecodedBlockStatus::BAD_RELOCATION ? "BadRelocation" :
+                                                                                         "PartialDecode",
                             OpAddress);
         }
         break;

FEXCore/Source/Interface/Core/Frontend.h

@@ -4,9 +4,12 @@
 #include "Interface/Core/X86Tables/X86Tables.h"
 #include "Interface/IR/IR.h"
 
+#include <FEXCore/Config/Config.h>
+#include <FEXCore/Core/CodeCache.h>
 #include <FEXCore/Utils/ThreadPoolAllocator.h>
 #include <FEXCore/fextl/set.h>
 #include <FEXCore/fextl/vector.h>
+#include <FEXCore/fextl/robin_map.h>
 
 #include <array>
 #include <cstddef>
@@ -28,6 +31,7 @@ public:
     INVALID_INST,
     NOEXEC_INST,
     PARTIAL_DECODE_INST,
+    BAD_RELOCATION,
   };
 
   // New Frontend decoding
@@ -59,9 +63,6 @@ public:
   uint64_t DecodedMinAddress {};
   uint64_t DecodedMaxAddress {~0ULL};
 
-  void SetSectionMaxAddress(uint64_t v) {
-    SectionMaxAddress = v;
-  }
   void SetExternalBranches(fextl::set<uint64_t>* v) {
     ExternalBranches = v;
   }
@@ -87,6 +88,8 @@ private:
   FEXCore::Context::ContextImpl* CTX;
   const FEXCore::HLE::SyscallOSABI OSABI {};
 
+  FEX_CONFIG_OPT(EnableCodeCacheValidation, ENABLECODECACHEVALIDATION);
+
   bool DecodeInstructionImpl(uint64_t PC);
   DecodedBlockStatus DecodeInstruction(uint64_t PC);
 
@@ -100,7 +103,8 @@ private:
 
   uint8_t ReadByte();
   std::optional<uint8_t> PeekByte(uint8_t Offset);
-  uint64_t ReadData(uint8_t Size);
+  std::pair<uint64_t, bool> ReadData(uint8_t Size);
+
   void SkipBytes(uint8_t Size) {
     InstructionSize += Size;
   }
@@ -108,6 +112,8 @@ private:
   bool NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op, DecodedHeader Options = {});
   bool NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op);
 
+  void DecodeREXIfValid(int8_t ExpectedOffset = -1);
+
   static constexpr size_t DefaultDecodedBufferSize = 0x10000;
   FEXCore::X86Tables::DecodedInst* DecodedBuffer {};
   Utils::PoolBufferWithTimedRetirement<FEXCore::X86Tables::DecodedInst*, 5000, 500> PoolObject;
@@ -117,6 +123,7 @@ private:
   uint64_t ExecutableRangeEnd {};
   bool ExecutableRangeWritable {};
   bool HitNonExecutableRange {};
+  bool HitBadRelocation {};
 
   const uint8_t* InstStream {};
   IR::OpSize GetGPROpSize() const {
@@ -130,13 +137,11 @@ private:
   FEXCore::X86Tables::DecodedInst* DecodeInst;
 
   // This is for multiblock data tracking
-  bool SymbolAvailable {false};
   uint64_t EntryPoint {};
   uint64_t MaxCondBranchForward {};
   uint64_t MaxCondBranchBackwards {~0ULL};
-  uint64_t SymbolMaxAddress {};
-  uint64_t SymbolMinAddress {~0ULL};
   uint64_t SectionMaxAddress {~0ULL};
+  uint64_t SectionMinAddress {};
   uint64_t NextBlockStartAddress {~0ULL};
 
   DecodedBlockInformation BlockInfo;
@@ -145,6 +150,8 @@ private:
   fextl::set<uint64_t> VisitedBlocks;
   fextl::set<uint64_t>* ExternalBranches {nullptr};
 
+  const fextl::robin_map<uint32_t, GuestRelocationType>* Relocations {nullptr};
+
   // ModRM rm decoding
   using DecodeModRMPtr = void (FEXCore::Frontend::Decoder::*)(X86Tables::DecodedOperand* Operand, X86Tables::ModRMDecoded ModRM);
   void DecodeModRM_16(X86Tables::DecodedOperand* Operand, X86Tables::ModRMDecoded ModRM);

FEXCore/Source/Interface/Core/Interpreter/Fallbacks/StringCompareFallbacks.cpp

@@ -2,14 +2,14 @@
 #include "Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h"
 #include "Interface/IR/IR.h"
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 #include <arm_neon.h>
 #endif
 
 #include <cstring>
 
 namespace FEXCore::CPU {
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 FEXCORE_PRESERVE_ALL_ATTR static int32_t GetImplicitLength(FEXCore::VectorRegType data, uint16_t control) {
   const auto is_using_words = (control & 1) != 0;
 

FEXCore/Source/Interface/Core/JIT/ALUOps.cpp

@@ -43,7 +43,15 @@ DEF_BINOP_WITH_CONSTANT(Ror, rorv, ror)
 DEF_OP(Constant) {
   auto Op = IROp->C<IR::IROp_Constant>();
   auto Dst = GetReg(Node);
-  LoadConstant(ARMEmitter::Size::i64Bit, Dst, Op->Constant);
+
+  const auto PadType = [Pad = Op->Pad]() {
+    switch (Pad) {
+    case IR::ConstPad::NoPad: return CPU::Arm64Emitter::PadType::NOPAD;
+    case IR::ConstPad::DoPad: return CPU::Arm64Emitter::PadType::DOPAD;
+    default: return CPU::Arm64Emitter::PadType::AUTOPAD;
+    }
+  }();
+  LoadConstant(ARMEmitter::Size::i64Bit, Dst, Op->Constant, PadType, Op->MaxBytes);
 }
 
 DEF_OP(EntrypointOffset) {
@@ -916,7 +924,7 @@ DEF_OP(Div) {
       mov(EmitSize, TMP2, Lower);
       mov(EmitSize, TMP3, Divisor);
 
-      ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LDIVHandler));
+      ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.LDIVHandler));
 
       str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
       blr(TMP4);
@@ -999,7 +1007,7 @@ DEF_OP(UDiv) {
       mov(EmitSize, TMP2, Lower);
       mov(EmitSize, TMP3, Divisor);
 
-      ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUDIVHandler));
+      ldr(TMP4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.LUDIVHandler));
 
       str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
       blr(TMP4);

FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp

@@ -28,7 +28,8 @@ void Arm64JITCore::InsertNamedThunkRelocation(ARMEmitter::Register Reg, const IR
 
   uint64_t Pointer = reinterpret_cast<uint64_t>(EmitterCTX->ThunkHandler->LookupThunk(Sum));
 
-  LoadConstant(ARMEmitter::Size::i64Bit, Reg, Pointer, false);
+  // Pointers are required to fit within 48-bit VA space.
+  LoadConstant(ARMEmitter::Size::i64Bit, Reg, Pointer, FEXCore::CPU::Arm64Emitter::PadType::AUTOPAD, 6);
   Relocations.emplace_back(MoveABI);
 }
 
@@ -92,7 +93,11 @@ void Arm64JITCore::InsertGuestRIPMove(ARMEmitter::Register Reg, uint64_t Constan
   MoveABI.GuestRIP.GuestRIP = Constant;
   MoveABI.GuestRIP.RegisterIndex = Reg.Idx();
 
-  LoadConstant(ARMEmitter::Size::i64Bit, Reg, Constant, false);
+  // Pointers are required to fit within 48-bit VA space.
+  // TODO: Force 6-byte `MaxSize`, with sign extension to 64-bit. Current code not smart enough to handle negatives.
+  // 48-bit sign extension works because x86-64 guests only receive 47-bit VA space, with 48-bit being reserved for kernel.
+  // Additional quirk, "canonical" 48-bit pointers on x86-64, sign extend the 48-bit as well (Which is why kernel pointers are negative).
+  LoadConstant(ARMEmitter::Size::i64Bit, Reg, Constant, FEXCore::CPU::Arm64Emitter::PadType::AUTOPAD);
   Relocations.emplace_back(MoveABI);
 }
 

FEXCore/Source/Interface/Core/JIT/AtomicOps.cpp

@@ -329,7 +329,7 @@ DEF_OP(TelemetrySetValue) {
   auto Op = IROp->C<IR::IROp_TelemetrySetValue>();
   auto Src = GetReg(Op->Value);
 
-  ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.TelemetryValueAddresses[Op->TelemetryValueIndex]));
+  ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.TelemetryValueAddresses[Op->TelemetryValueIndex]));
 
   // Cortex fuses cmp+cset.
   cmp(ARMEmitter::Size::i32Bit, Src, 0);

FEXCore/Source/Interface/Core/JIT/BranchOps.cpp

@@ -56,12 +56,12 @@ DEF_OP(ExitFunction) {
   uint64_t NewRIP;
 
   if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
     if (NewRIP < EC_CODE_BITMAP_MAX_ADDRESS && RtlIsEcCode(NewRIP)) {
       str(REG_CALLRET_SP, STATE_PTR(CpuStateFrame, State.callret_sp));
       add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, StaticRegisters[X86State::REG_RSP], 0);
-      LoadConstant(ARMEmitter::Size::i64Bit, EC_CALL_CHECKER_PC_REG, NewRIP);
-      ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC));
+      InsertGuestRIPMove(EC_CALL_CHECKER_PC_REG, NewRIP);
+      ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.ExitFunctionEC));
       br(TMP2);
     } else {
 #endif
@@ -150,16 +150,16 @@ DEF_OP(ExitFunction) {
         ARMEmitter::ForwardLabel TFUnset;
         ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
         (void)cbz(ARMEmitter::Size::i32Bit, TMP1, &TFUnset);
-        LoadConstant(ARMEmitter::Size::i64Bit, TMP1, NewRIP);
+        InsertGuestRIPMove(TMP1, NewRIP);
         str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip));
-        ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop));
+        ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.DispatcherLoopTop));
         blr(TMP2);
         (void)Bind(&TFUnset);
       }
 
       EmitLinkedBranch(NewRIP, Op->Hint == IR::BranchHint::Call);
       (void)Bind(&l_CallReturn);
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
     }
 #endif
   } else {
@@ -186,7 +186,7 @@ DEF_OP(ExitFunction) {
     // Note: sub+cbnz used over cmp+br to preserve flags.
     sub(TMP1, TMP1, RipReg.X());
     (void)cbz(ARMEmitter::Size::i64Bit, TMP1, &SkipFullLookup);
-    ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop));
+    ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.DispatcherLoopTop));
     str(RipReg.X(), STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip));
 
     (void)Bind(&SkipFullLookup);
@@ -283,8 +283,8 @@ DEF_OP(Syscall) {
     str(GetReg(Op->Header.Args[i]).X(), ARMEmitter::Reg::rsp, i * 8);
   }
 
-  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerObj));
-  ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.SyscallHandlerFunc));
+  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.SyscallHandlerObj));
+  ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.SyscallHandlerFunc));
   mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, STATE.R());
 
   // SP supporting move
@@ -397,9 +397,10 @@ DEF_OP(ThreadRemoveCodeEntry) {
   // X1: RIP
   mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, STATE.R());
 
-  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, Entry);
+  // TODO: Relocations don't seem to be wired up to this...?
+  LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, Entry, CPU::Arm64Emitter::PadType::AUTOPAD);
 
-  ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadRemoveCodeEntryFromJIT));
+  ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.ThreadRemoveCodeEntryFromJIT));
   if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
     GenerateIndirectRuntimeCall<void, void*, void*>(ARMEmitter::Reg::r2);
   } else {
@@ -424,8 +425,8 @@ DEF_OP(CPUID) {
   // x0 = CPUID Handler
   // x1 = CPUID Function
   // x2 = CPUID Leaf
-  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj));
-  ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDFunction));
+  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.CPUIDObj));
+  ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.CPUIDFunction));
 
   if (!TMP_ABIARGS) {
     mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, TMP2);
@@ -465,8 +466,8 @@ DEF_OP(XGetBV) {
 
   // x0 = CPUID Handler
   // x1 = XCR Function
-  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj));
-  ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.XCRFunction));
+  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.CPUIDObj));
+  ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.XCRFunction));
   if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
     GenerateIndirectRuntimeCall<uint64_t, void*, uint32_t>(ARMEmitter::Reg::r2);
   } else {

FEXCore/Source/Interface/Core/JIT/JIT.cpp

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: MIT
 /*
 $info$
-glossary: Splatter ~ a code generator backend that concaternates configurable macros instead of doing isel
+glossary: Splatter ~ a code generator backend that concatenates configurable macros instead of doing isel
 glossary: IR ~ Intermediate Representation, our high-level opcode representation, loosely modeling arm64
 glossary: SSA ~ Single Static Assignment, a form of representing IR in memory
 glossary: Basic Block ~ A block of instructions with no control flow, terminated by control flow
@@ -133,8 +133,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       const auto Src1 = GetVReg(IROp->Args[0]);
       fmov(VTMP1.S(), Src1.S());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -151,8 +151,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       const auto Src1 = GetVReg(IROp->Args[0]);
       fmov(VTMP1.D(), Src1.D());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -176,8 +176,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
         mov(ARMEmitter::Size::i32Bit, TMP2, Src1);
       }
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -194,8 +194,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       const auto Src1 = GetVReg(IROp->Args[0]);
       mov(VTMP1.Q(), Src1.Q());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -212,8 +212,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       const auto Src1 = GetVReg(IROp->Args[0]);
       mov(VTMP1.Q(), Src1.Q());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -230,8 +230,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       const auto Src1 = GetVReg(IROp->Args[0]);
       fmov(VTMP1.D(), Src1.D());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -254,8 +254,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
 
       fmov(VTMP1.D(), Src1.D());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -276,8 +276,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       fmov(VTMP1.D(), Src1.D());
       fmov(VTMP2.D(), Src2.D());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -294,8 +294,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       const auto Src1 = GetVReg(IROp->Args[0]);
       mov(VTMP1.Q(), Src1.Q());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -312,8 +312,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       const auto Src1 = GetVReg(IROp->Args[0]);
       mov(VTMP1.Q(), Src1.Q());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -330,8 +330,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       const auto Src1 = GetVReg(IROp->Args[0]);
       mov(VTMP1.Q(), Src1.Q());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -351,8 +351,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       mov(VTMP1.Q(), Src1.Q());
       mov(VTMP2.Q(), Src2.Q());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -369,8 +369,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       const auto Src1 = GetVReg(IROp->Args[0]);
       mov(VTMP1.Q(), Src1.Q());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -394,8 +394,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
 
       mov(VTMP1.Q(), Src1.Q());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -416,8 +416,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       mov(VTMP1.Q(), Src1.Q());
       mov(VTMP2.Q(), Src2.Q());
 
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP1);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -434,8 +434,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       // tmp2 (x1/x11): source 2
       // tmp3 (x2/x12): source 3
       const auto Op = IROp->C<IR::IROp_VPCMPESTRX>();
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
 
       stp<ARMEmitter::IndexType::PRE>(TMP1, ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
 
@@ -476,8 +476,8 @@ void Arm64JITCore::Op_Unhandled(const IR::IROp_Header* IROp, IR::Ref Node) {
       mov(VTMP2.Q(), Src2.Q());
       movz(ARMEmitter::Size::i32Bit, TMP1, Control);
 
-      ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
-      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex].Func));
+      ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].ABIHandler));
+      ldr(TMP4, STATE_PTR(CpuStateFrame, Pointers.FallbackHandlerPointers[Info.HandlerIndex].Func));
       blr(TMP2);
 
       ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
@@ -533,7 +533,7 @@ uint64_t Arm64JITCore::ExitFunctionLink(FEXCore::Core::CpuStateFrame* Frame, FEX
   if (TFSet) {
     // If TF is set, the cache must be skipped as different code needs to be generated.
     Frame->State.rip = GuestRip;
-    return Frame->Pointers.Common.DispatcherLoopTop;
+    return Frame->Pointers.DispatcherLoopTop;
   } else {
     {
       // Guard the LookupCache lock with the code invalidation mutex, to avoid issues with forking
@@ -590,7 +590,7 @@ uint64_t Arm64JITCore::ExitFunctionLink(FEXCore::Core::CpuStateFrame* Frame, FEX
   } else {
     // This case is common between calls and jumps as the thunk callsite can be left untouched.
     std::atomic_ref<uint64_t>(Record->HostCode).store(HostCode, std::memory_order::seq_cst);
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
     // Make memory write visible to other threads reading the same location
     asm volatile("dc cvau, %0; dsb ish" : : "r"(Record->HostCode) :);
 #endif
@@ -632,36 +632,32 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::In
     // Set up pointers that the JIT needs to load
 
     // Common
-    auto& Common = ThreadState->CurrentFrame->Pointers.Common;
+    auto& Ptrs = ThreadState->CurrentFrame->Pointers;
 
-    Common.PrintValue = reinterpret_cast<uint64_t>(PrintValue);
-    Common.PrintVectorValue = reinterpret_cast<uint64_t>(PrintVectorValue);
-    Common.ThreadRemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadRemoveCodeEntryFromJit);
-    Common.MonoBackpatcherWrite = reinterpret_cast<uint64_t>(&Context::ContextImpl::MonoBackpatcherWrite);
-    Common.CPUIDObj = reinterpret_cast<uint64_t>(&CTX->CPUID);
+    Ptrs.PrintValue = reinterpret_cast<uint64_t>(PrintValue);
+    Ptrs.PrintVectorValue = reinterpret_cast<uint64_t>(PrintVectorValue);
+    Ptrs.ThreadRemoveCodeEntryFromJIT = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadRemoveCodeEntryFromJit);
+    Ptrs.MonoBackpatcherWrite = reinterpret_cast<uint64_t>(&Context::ContextImpl::MonoBackpatcherWrite);
+    Ptrs.CPUIDObj = reinterpret_cast<uint64_t>(&CTX->CPUID);
 
     {
       FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunFunction);
-      Common.CPUIDFunction = PMF.GetConvertedPointer();
+      Ptrs.CPUIDFunction = PMF.GetConvertedPointer();
     }
 
     {
       FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunXCRFunction);
-      Common.XCRFunction = PMF.GetConvertedPointer();
+      Ptrs.XCRFunction = PMF.GetConvertedPointer();
     }
 
     {
       FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::HLE::SyscallHandler::HandleSyscall);
-      Common.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
-      Common.SyscallHandlerFunc = PMF.GetVTableEntry(CTX->SyscallHandler);
+      Ptrs.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
+      Ptrs.SyscallHandlerFunc = PMF.GetVTableEntry(CTX->SyscallHandler);
     }
-    Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Arm64JITCore::ExitFunctionLink);
-
-    // Platform Specific
-    auto& AArch64 = ThreadState->CurrentFrame->Pointers.AArch64;
-
-    AArch64.LUDIV = reinterpret_cast<uint64_t>(LUDIV);
-    AArch64.LDIV = reinterpret_cast<uint64_t>(LDIV);
+    Ptrs.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Arm64JITCore::ExitFunctionLink);
+    Ptrs.LUDIV = reinterpret_cast<uint64_t>(LUDIV);
+    Ptrs.LDIV = reinterpret_cast<uint64_t>(LDIV);
   }
 
   CurrentCodeBuffer = CodeBuffers.GetLatest();
@@ -760,7 +756,7 @@ void Arm64JITCore::EmitTFCheck() {
 
   LoadConstant(ARMEmitter::Size::i64Bit, TMP1, Constant);
   str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData));
-  ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP));
+  ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.GuestSignal_SIGTRAP));
   br(TMP1);
 
   (void)Bind(&l_TFBlocked);
@@ -778,7 +774,7 @@ void Arm64JITCore::EmitSuspendInterruptCheck() {
          offsetof(FEXCore::Core::InternalThreadState, InterruptFaultPage) - offsetof(FEXCore::Core::InternalThreadState, BaseFrameState));
   }
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
   static constexpr uint16_t SuspendMagic {0xCAFE};
 
   ldr(TMP2.W(), STATE_PTR(CpuStateFrame, SuspendDoorbell));

FEXCore/Source/Interface/Core/JIT/MiscOps.cpp

@@ -78,19 +78,19 @@ DEF_OP(Break) {
 
   switch (Op->Reason.Signal) {
   case Core::FAULT_SIGILL:
-    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGILL));
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.GuestSignal_SIGILL));
     br(TMP1);
     break;
   case Core::FAULT_SIGTRAP:
-    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP));
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.GuestSignal_SIGTRAP));
     br(TMP1);
     break;
   case Core::FAULT_SIGSEGV:
-    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGSEGV));
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.GuestSignal_SIGSEGV));
     br(TMP1);
     break;
   default:
-    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP));
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.GuestSignal_SIGTRAP));
     br(TMP1);
     break;
   }
@@ -189,11 +189,11 @@ DEF_OP(Print) {
 
   if (IsGPR(Op->Value)) {
     mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, GetReg(Op->Value));
-    ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintValue));
+    ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.PrintValue));
   } else {
     fmov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, GetVReg(Op->Value), false);
     fmov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, GetVReg(Op->Value), true);
-    ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.PrintVectorValue));
+    ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.PrintVectorValue));
   }
 
   if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
@@ -241,7 +241,7 @@ DEF_OP(ProcessorID) {
   sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 16);
 
   // Load the getcpu syscall number
-#if defined(_M_X86_64)
+#if defined(ARCHITECTURE_x86_64)
   // Just to ensure the syscall number doesn't change if compiled for an x86_64 host.
   constexpr auto GetCPUSyscallNum = 0xa8;
 #else
@@ -305,20 +305,20 @@ DEF_OP(MonoBackpatcherWrite) {
     mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, TMP4);
   }
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
   ldr(TMP2, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
   LoadConstant(ARMEmitter::Size::i32Bit, TMP1, 1);
   strb(TMP1.W(), TMP2, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
 #endif
 
-  ldr(ARMEmitter::XReg::x4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.MonoBackpatcherWrite));
+  ldr(ARMEmitter::XReg::x4, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.MonoBackpatcherWrite));
   if (!CTX->Config.DisableVixlIndirectCalls) [[unlikely]] {
     GenerateIndirectRuntimeCall<void, void*, uint8_t, uint64_t, uint64_t>(ARMEmitter::Reg::r4);
   } else {
     blr(ARMEmitter::Reg::r4);
   }
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
   ldr(TMP2, ARMEmitter::XReg::x18, TEB_CPU_AREA_OFFSET);
   strb(ARMEmitter::WReg::zr, TMP2, CPU_AREA_IN_SYSCALL_CALLBACK_OFFSET);
 #endif

FEXCore/Source/Interface/Core/JIT/Relocations.h

@@ -74,6 +74,17 @@ struct RelocGuestRIP final {
 };
 
 union Relocation {
+  // Clang 16 Can't default-initialize this union
+  static Relocation Default() {
+#if __clang_major__ < 17
+    Relocation Ret {.Header {}};
+    memset(&Ret, 0, sizeof(Ret));
+    return Ret;
+#else
+    return {};
+#endif
+  }
+
   RelocationHeader Header {};
 
   RelocNamedSymbolLiteral NamedSymbolLiteral;

FEXCore/Source/Interface/Core/JIT/VectorOps.cpp

@@ -977,7 +977,7 @@ DEF_OP(LoadNamedVectorConstant) {
   }
   // Load the pointer.
   auto GenerateMemOperand = [this](IR::OpSize OpSize, uint32_t NamedConstant, ARMEmitter::Register Base) {
-    const auto ConstantOffset = offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.NamedVectorConstants[NamedConstant]);
+    const auto ConstantOffset = offsetof(FEXCore::Core::CpuStateFrame, Pointers.NamedVectorConstants[NamedConstant]);
 
     if (ConstantOffset <= 255 || // Unscaled 9-bit signed
         ((ConstantOffset & (IR::OpSizeToSize(OpSize) - 1)) == 0 &&
@@ -985,13 +985,13 @@ DEF_OP(LoadNamedVectorConstant) {
       return ARMEmitter::ExtendedMemOperand(Base.X(), ARMEmitter::IndexType::OFFSET, ConstantOffset);
     }
 
-    ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.NamedVectorConstantPointers[NamedConstant]));
+    ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.NamedVectorConstantPointers[NamedConstant]));
     return ARMEmitter::ExtendedMemOperand(TMP1, ARMEmitter::IndexType::OFFSET, 0);
   };
 
   if (OpSize == IR::OpSize::i256Bit) {
     // Handle SVE 32-byte variant upfront.
-    ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.NamedVectorConstantPointers[Op->Constant]));
+    ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.NamedVectorConstantPointers[Op->Constant]));
     ld1b<ARMEmitter::SubRegSize::i8Bit>(Dst.Z(), PRED_TMP_32B.Zeroing(), TMP1, 0);
     return;
   }
@@ -1013,7 +1013,7 @@ DEF_OP(LoadNamedVectorIndexedConstant) {
   const auto Dst = GetVReg(Node);
 
   // Load the pointer.
-  ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.Common.IndexedNamedVectorConstantPointers[Op->Constant]));
+  ldr(TMP1, STATE_PTR(CpuStateFrame, Pointers.IndexedNamedVectorConstantPointers[Op->Constant]));
 
   switch (OpSize) {
   case IR::OpSize::i8Bit: ldrb(Dst, TMP1, Op->Index); break;

FEXCore/Source/Interface/Core/LookupCache.h

@@ -141,7 +141,7 @@ struct GuestToHostMap {
     BlockLinks->insert({{GuestDestination, HostLink}, delinker});
   }
 
-  bool AddBlockExecutableRange(const fextl::set<uint64_t>& Addresses, uint64_t Start, uint64_t Length, const LookupCacheWriteLockToken&) {
+  bool AddBlockExecutableRange(const std::ranges::input_range auto& Addresses, uint64_t Start, uint64_t Length, const LookupCacheWriteLockToken&) {
     bool rv = false;
 
     for (auto CurrentPage = Start >> 12, EndPage = (Start + Length - 1) >> 12; CurrentPage <= EndPage; CurrentPage++) {
@@ -407,7 +407,7 @@ private:
         if (!NewPageBacking) {
           // Couldn't allocate, clear L2 and retry
           ClearL2Cache(lk);
-          CacheBlockMapping(Address, Entry, false, lk);
+          CacheBlockMapping(FullAddress, Entry, false, lk);
           return;
         }
         Pointers[Address] = NewPageBacking;

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -1325,35 +1325,12 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs, bool ToSeg) {
 }
 
 void OpDispatchBuilder::MOVOffsetOp(OpcodeArgs) {
-
-  auto GenMemSrcFromOp = [&](size_t StartingSource) -> AddressMode {
-    const uint64_t Lower = Op->Src[StartingSource].Literal();
-    const uint64_t Upper = Op->Src[StartingSource + 1].Literal();
-    const uint64_t Combined = (Upper << 32) | Lower;
-    const auto GPRSize = GetGPROpSize();
-
-    AddressMode A {
-      .Segment = GetSegment(Op->Flags),
-      .Offset = static_cast<int64_t>(Combined),
-      .AddrSize = (Op->Flags & X86Tables::DecodeFlags::FLAG_ADDRESS_SIZE) != 0 ? (GPRSize >> 1) : GPRSize,
-      .NonTSO = false,
-    };
-
-    return A;
-  };
   switch (Op->OP) {
   case 0xA0:
   case 0xA1: {
     // Source is memory(literal)
     // Dest is GPR
-    Ref Src {};
-    if (Op->Src[0].Data.Literal.Size <= 4) {
-      Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.ForceLoad = true});
-    } else {
-      const auto OpSize = OpSizeFromSrc(Op);
-      auto A = GenMemSrcFromOp(0);
-      Src = _LoadMemGPRAutoTSO(OpSize, A, OpSize::i8Bit);
-    }
+    auto Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.ForceLoad = true});
     StoreResultGPR(Op, Op->Dest, Src);
     break;
   }
@@ -1365,13 +1342,7 @@ void OpDispatchBuilder::MOVOffsetOp(OpcodeArgs) {
 
     // This one is a bit special since the destination is a literal
     // So the destination gets stored in Src[1]
-    if (Op->Src[1].Data.Literal.Size <= 4) {
-      StoreResultGPR(Op, Op->Src[1], Src);
-    } else {
-      const auto OpSize = OpSizeFromSrc(Op);
-      auto A = GenMemSrcFromOp(1);
-      _StoreMemGPRAutoTSO(OpSize, A, Src, OpSize::i8Bit);
-    }
+    StoreResultGPR(Op, Op->Src[1], Src);
     break;
   }
   }
@@ -1396,7 +1367,7 @@ void OpDispatchBuilder::CPUIDOp(OpcodeArgs) {
   StoreGPRRegister(X86State::REG_RDX, RDX);
 }
 
-uint32_t OpDispatchBuilder::LoadConstantShift(X86Tables::DecodedOp Op, bool Is1Bit) {
+uint32_t OpDispatchBuilder::GetConstantShift(X86Tables::DecodedOp Op, bool Is1Bit) {
   if (Is1Bit) {
     return 1;
   } else {
@@ -1431,7 +1402,7 @@ void OpDispatchBuilder::SHLOp(OpcodeArgs) {
 void OpDispatchBuilder::SHLImmediateOp(OpcodeArgs, bool SHL1Bit) {
   Ref Dest = LoadSourceGPR(Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = true});
 
-  uint64_t Shift = LoadConstantShift(Op, SHL1Bit);
+  uint64_t Shift = GetConstantShift(Op, SHL1Bit);
   const auto Size = GetSrcBitSize(Op);
 
   Ref Result = _Lshl(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Constant(Shift));
@@ -1454,7 +1425,7 @@ void OpDispatchBuilder::SHRImmediateOp(OpcodeArgs, bool SHR1Bit) {
   const auto Size = GetSrcBitSize(Op);
   auto Dest = LoadSourceGPR(Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = Size >= 32});
 
-  uint64_t Shift = LoadConstantShift(Op, SHR1Bit);
+  uint64_t Shift = GetConstantShift(Op, SHR1Bit);
   auto ALUOp = _Lshr(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Constant(Shift));
 
   CalculateFlags_ShiftRightImmediate(OpSizeFromSrc(Op), ALUOp, Dest, Shift);
@@ -1506,7 +1477,7 @@ void OpDispatchBuilder::SHLDOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::SHLDImmediateOp(OpcodeArgs) {
-  uint64_t Shift = LoadConstantShift(Op, false);
+  uint64_t Shift = GetConstantShift(Op, false);
   const auto Size = GetSrcBitSize(Op);
 
   Ref Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = Size >= 32});
@@ -1574,7 +1545,7 @@ void OpDispatchBuilder::SHRDImmediateOp(OpcodeArgs) {
   Ref Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags);
   Ref Dest = LoadSourceGPR(Op, Op->Dest, Op->Flags);
 
-  uint64_t Shift = LoadConstantShift(Op, false);
+  uint64_t Shift = GetConstantShift(Op, false);
   const auto Size = GetSrcBitSize(Op);
 
   if (Shift != 0) {
@@ -1615,7 +1586,7 @@ void OpDispatchBuilder::ASHROp(OpcodeArgs, bool Immediate, bool SHR1Bit) {
   }
 
   if (Immediate) {
-    uint64_t Shift = LoadConstantShift(Op, SHR1Bit);
+    uint64_t Shift = GetConstantShift(Op, SHR1Bit);
     Ref Result = _Ashr(OpSize, Dest, Constant(Shift));
 
     CalculateFlags_SignShiftRightImmediate(OpSizeFromSrc(Op), Result, Dest, Shift);
@@ -1643,7 +1614,7 @@ void OpDispatchBuilder::RotateOp(OpcodeArgs, bool Left, bool IsImmediate, bool I
 
   ArithRef UnmaskedSrc;
   if (Is1Bit || IsImmediate) {
-    UnmaskedConst = LoadConstantShift(Op, Is1Bit);
+    UnmaskedConst = GetConstantShift(Op, Is1Bit);
     UnmaskedSrc = ARef(UnmaskedConst);
   } else {
     UnmaskedSrc = ARef(LoadSourceGPR(Op, Op->Src[1], Op->Flags, {.AllowUpperGarbage = true}));
@@ -3067,7 +3038,6 @@ void OpDispatchBuilder::SMSWOp(OpcodeArgs) {
                        (0U << 2) | ///< EM - Emulation
                        (1U << 1) | ///< MP - Monitor Coprocessor
                        (1U << 0)); ///< PE - Protection Enabled
-
   const auto OpAddr = X86Tables::DecodeFlags::GetOpAddr(Op->Flags, 0);
   if (Is64BitMode) {
     DstSize = OpAddr == X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST  ? OpSize::i16Bit :
@@ -4131,6 +4101,8 @@ void OpDispatchBuilder::CheckLegacySegmentRead(Ref NewNode, uint32_t SegmentReg)
 
   // Will set the telemetry value if NewNode is != 0
   _TelemetrySetValue(NewNode, TelemIndex);
+  // Telemetry will dirty flags, and user code does not expect LoadSource to clobber flags, fix that up here as this is an edge case.
+  CalculateDeferredFlags();
 #endif
 }
 
@@ -4169,6 +4141,8 @@ void OpDispatchBuilder::CheckLegacySegmentWrite(Ref NewNode, uint32_t SegmentReg
 
   // Will set the telemetry value if NewNode is != 0
   _TelemetrySetValue(NewNode, TelemIndex);
+  // Telemetry will dirty flags, and user code does not expect LoadSource to clobber flags, fix that up here as this is an edge case.
+  CalculateDeferredFlags();
 #endif
 }
 
@@ -4234,18 +4208,26 @@ AddressMode OpDispatchBuilder::DecodeAddress(const X86Tables::DecodedOp& Op, con
   } else if (Operand.IsGPRDirect()) {
     A.Base = LoadGPRRegister(Operand.Data.GPR.GPR, GPRSize);
     A.NonTSO |= IsNonTSOReg(AccessType, Operand.Data.GPR.GPR);
-  } else if (Operand.IsGPRIndirect()) {
+  } else if (Operand.IsGPRIndirect() || Operand.IsGPRIndirectRelocation()) {
     A.Base = LoadGPRRegister(Operand.Data.GPRIndirect.GPR, GPRSize);
-    A.Offset = Operand.Data.GPRIndirect.Displacement;
+    if (Operand.IsGPRIndirectRelocation()) {
+      A.Base = Add(GPRSize, _EntrypointOffset(GPRSize, Operand.Data.GPRIndirect.Displacement), A.Base);
+    } else {
+      A.Offset = static_cast<int32_t>(Operand.Data.GPRIndirect.Displacement);
+    }
     A.NonTSO |= IsNonTSOReg(AccessType, Operand.Data.GPRIndirect.GPR);
-  } else if (Operand.IsRIPRelative()) {
+  } else if (Operand.IsRIPRelative() || Operand.IsRIPRelativeRelocation()) {
     if (Is64BitMode) {
-      A.Base = GetRelocatedPC(Op, Operand.Data.RIPLiteral.Value.s);
+      A.Base = GetRelocatedPC(Op, static_cast<int32_t>(Operand.Data.RIPLiteral.Value));
     } else {
       // 32bit this isn't RIP relative but instead absolute
-      A.Offset = Operand.Data.RIPLiteral.Value.u;
+      if (Operand.IsRIPRelativeRelocation()) {
+        A.Base = _EntrypointOffset(GPRSize, Operand.Data.RIPLiteral.Value);
+      } else {
+        A.Offset = Operand.Data.RIPLiteral.Value;
+      }
     }
-  } else if (Operand.IsSIB()) {
+  } else if (Operand.IsSIB() || Operand.IsSIBRelocation()) {
     const bool IsVSIB = IsLoad && ((Op->Flags & X86Tables::DecodeFlags::FLAG_VSIB_BYTE) != 0);
 
     if (Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) {
@@ -4266,8 +4248,20 @@ AddressMode OpDispatchBuilder::DecodeAddress(const X86Tables::DecodedOp& Op, con
       A.IndexScale = Operand.Data.SIB.Scale;
     }
 
-    A.Offset = Operand.Data.SIB.Offset;
+    if (Operand.IsSIBRelocation()) {
+      auto EPOffset = _EntrypointOffset(GPRSize, Operand.Data.SIB.Offset);
+      if (A.Base) {
+        A.Base = Add(GPRSize, EPOffset, A.Base);
+      } else {
+        A.Base = EPOffset;
+      }
+    } else {
+      A.Offset = static_cast<int32_t>(Operand.Data.SIB.Offset);
+    }
+
     A.NonTSO |= IsNonTSOReg(AccessType, Operand.Data.SIB.Base) || IsNonTSOReg(AccessType, Operand.Data.SIB.Index);
+  } else if (Operand.IsLiteralRelocation()) {
+    A.Base = _EntrypointOffset(GPRSize, Operand.Data.LiteralRelocation.EntrypointOffset);
   } else {
     LOGMAN_MSG_A_FMT("Unknown Src Type: {}\n", Operand.Type);
   }
@@ -4500,20 +4494,6 @@ void OpDispatchBuilder::MOVGPROp(OpcodeArgs, uint32_t SrcIndex) {
   StoreResultGPR(Op, Src, OpSize::i8Bit);
 }
 
-void OpDispatchBuilder::MOVGPRImmediate(OpcodeArgs) {
-  Ref Src {};
-  if (Op->Src[0].Data.Literal.Size <= 4) {
-    Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.Align = OpSize::i8Bit, .AllowUpperGarbage = true});
-  } else {
-    // 8-byte literal is special cased.
-    const uint64_t Lower = Op->Src[0].Literal();
-    const uint64_t Upper = Op->Src[1].Literal();
-    const uint64_t Combined = (Upper << 32) | Lower;
-    Src = _Constant(Combined);
-  }
-  StoreResultGPR(Op, Src, OpSize::i8Bit);
-}
-
 void OpDispatchBuilder::MOVGPRNTOp(OpcodeArgs) {
   Ref Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.Align = OpSize::i8Bit});
   StoreResultGPR(Op, Src, OpSize::i8Bit, MemoryAccessType::STREAM);
@@ -4658,7 +4638,7 @@ void OpDispatchBuilder::INTOp(OpcodeArgs) {
     }
 #endif
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
     // This is used when QueryPerformanceCounter is called on recent Windows versions, it causes CNTVCT to be written into RAX.
     constexpr uint8_t GET_CNTVCT_LITERAL = 0x81;
     if (Literal == GET_CNTVCT_LITERAL) {

FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -319,7 +319,6 @@ public:
 
   void UnhandledOp(OpcodeArgs);
   void MOVGPROp(OpcodeArgs, uint32_t SrcIndex);
-  void MOVGPRImmediate(OpcodeArgs);
   void MOVGPRNTOp(OpcodeArgs);
   void MOVVectorAlignedOp(OpcodeArgs);
   void MOVVectorUnalignedOp(OpcodeArgs);
@@ -373,7 +372,7 @@ public:
   void CMOVOp(OpcodeArgs);
   void CPUIDOp(OpcodeArgs);
   void XGetBVOp(OpcodeArgs);
-  uint32_t LoadConstantShift(X86Tables::DecodedOp Op, bool Is1Bit);
+  uint32_t GetConstantShift(X86Tables::DecodedOp Op, bool Is1Bit);
   void SHLOp(OpcodeArgs);
   void SHLImmediateOp(OpcodeArgs, bool SHL1Bit);
   void SHROp(OpcodeArgs);
@@ -1544,7 +1543,7 @@ private:
   [[nodiscard]]
   static bool IsOperandMem(const X86Tables::DecodedOperand& Operand, bool Load) {
     // Literals are immediates as sources but memory addresses as destinations.
-    return !(Load && Operand.IsLiteral()) && !Operand.IsGPR();
+    return !(Load && (Operand.IsLiteral() || Operand.IsLiteralRelocation())) && !Operand.IsGPR();
   }
 
   [[nodiscard]]

FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp

@@ -52,7 +52,8 @@ OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_LoadSource_WithOpSize(
 OpDispatchBuilder::RefVSIB
 OpDispatchBuilder::AVX128_LoadVSIB(const X86Tables::DecodedOp& Op, const X86Tables::DecodedOperand& Operand, uint32_t Flags, bool NeedsHigh) {
   const bool IsVSIB = (Op->Flags & X86Tables::DecodeFlags::FLAG_VSIB_BYTE) != 0;
-  LOGMAN_THROW_A_FMT(Operand.IsSIB() && IsVSIB, "Trying to load VSIB for something that isn't the correct type!");
+  LOGMAN_THROW_A_FMT((Operand.IsSIB() || Operand.IsSIBRelocation()) && IsVSIB, "Trying to load VSIB for something that isn't the correct "
+                                                                               "type!");
 
   // VSIB is a very special case which has a ton of encoded data.
   // Get it in a format we can reason about.
@@ -64,13 +65,25 @@ OpDispatchBuilder::AVX128_LoadVSIB(const X86Tables::DecodedOp& Op, const X86Tabl
                      "Base must be a GPR.");
   const auto Index_XMM_gpr = Index_gpr - X86State::REG_XMM_0;
 
-  return {
+  OpDispatchBuilder::RefVSIB A {
     .Low = AVX128_LoadXMMRegister(Index_XMM_gpr, false),
     .High = NeedsHigh ? AVX128_LoadXMMRegister(Index_XMM_gpr, true) : Invalid(),
     .BaseAddr = Base_gpr != FEXCore::X86State::REG_INVALID ? LoadGPRRegister(Base_gpr, OpSize::i64Bit, 0, false) : nullptr,
-    .Displacement = Operand.Data.SIB.Offset,
     .Scale = Operand.Data.SIB.Scale,
   };
+
+  if (Operand.IsSIBRelocation()) {
+    auto EPOffset = _EntrypointOffset(OpSize::i64Bit, Operand.Data.SIB.Offset);
+    if (A.BaseAddr) {
+      A.BaseAddr = Add(OpSize::i64Bit, EPOffset, A.BaseAddr);
+    } else {
+      A.BaseAddr = EPOffset;
+    }
+  } else {
+    A.Displacement = static_cast<int32_t>(Operand.Data.SIB.Offset);
+  }
+
+  return A;
 }
 
 void OpDispatchBuilder::AVX128_StoreResult_WithOpSize(FEXCore::X86Tables::DecodedOp Op, const FEXCore::X86Tables::DecodedOperand& Operand,

FEXCore/Source/Interface/Core/OpcodeDispatcher/BaseTables.h

@@ -53,7 +53,7 @@ constexpr inline DispatchTableEntry OpDispatch_BaseOpTable[] = {
   {0xAA, 2, &OpDispatchBuilder::STOSOp},
   {0xAC, 2, &OpDispatchBuilder::LODSOp},
   {0xAE, 2, &OpDispatchBuilder::SCASOp},
-  {0xB0, 16, &OpDispatchBuilder::Bind<&OpDispatchBuilder::MOVGPRImmediate>},
+  {0xB0, 16, &OpDispatchBuilder::Bind<&OpDispatchBuilder::MOVGPROp, 0>},
   {0xC2, 2, &OpDispatchBuilder::RETOp},
   {0xC8, 1, &OpDispatchBuilder::EnterOp},
   {0xC9, 1, &OpDispatchBuilder::LEAVEOp},

FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp

@@ -5017,7 +5017,8 @@ void OpDispatchBuilder::VFMAddSubImpl(OpcodeArgs, bool AddSub, uint8_t Src1Idx,
 
 OpDispatchBuilder::RefVSIB OpDispatchBuilder::LoadVSIB(const X86Tables::DecodedOp& Op, const X86Tables::DecodedOperand& Operand, uint32_t Flags) {
   const bool IsVSIB = (Op->Flags & X86Tables::DecodeFlags::FLAG_VSIB_BYTE) != 0;
-  LOGMAN_THROW_A_FMT(Operand.IsSIB() && IsVSIB, "Trying to load VSIB for something that isn't the correct type!");
+  LOGMAN_THROW_A_FMT((Operand.IsSIB() || Operand.IsSIBRelocation()) && IsVSIB, "Trying to load VSIB for something that isn't the correct "
+                                                                               "type!");
 
   // VSIB is a very special case which has a ton of encoded data.
   // Get it in a format we can reason about.
@@ -5029,12 +5030,24 @@ OpDispatchBuilder::RefVSIB OpDispatchBuilder::LoadVSIB(const X86Tables::DecodedO
                      "Base must be a GPR.");
   const auto Index_XMM_gpr = Index_gpr - X86State::REG_XMM_0;
 
-  return {
+  OpDispatchBuilder::RefVSIB A {
     .Low = LoadXMMRegister(Index_XMM_gpr),
     .BaseAddr = Base_gpr != FEXCore::X86State::REG_INVALID ? LoadGPRRegister(Base_gpr, OpSize::i64Bit, 0, false) : nullptr,
-    .Displacement = Operand.Data.SIB.Offset,
     .Scale = Operand.Data.SIB.Scale,
   };
+
+  if (Operand.IsSIBRelocation()) {
+    auto EPOffset = _EntrypointOffset(OpSize::i64Bit, Operand.Data.SIB.Offset);
+    if (A.BaseAddr) {
+      A.BaseAddr = Add(OpSize::i64Bit, EPOffset, A.BaseAddr);
+    } else {
+      A.BaseAddr = EPOffset;
+    }
+  } else {
+    A.Displacement = static_cast<int32_t>(Operand.Data.SIB.Offset);
+  }
+
+  return A;
 }
 
 template<OpSize AddrElementSize>

FEXCore/Source/Interface/Core/X86Tables/X86Tables.h

@@ -117,9 +117,13 @@ struct DecodedOperand {
     GPR,
     GPRDirect,
     GPRIndirect,
+    GPRIndirectRelocation,
     RIPRelative,
+    RIPRelativeRelocation,
     Literal,
+    LiteralRelocation,
     SIB,
+    SIBRelocation
   };
 
   bool IsNone() const {
@@ -134,20 +138,30 @@ struct DecodedOperand {
   bool IsGPRIndirect() const {
     return Type == OpType::GPRIndirect;
   }
+  bool IsGPRIndirectRelocation() const {
+    return Type == OpType::GPRIndirectRelocation;
+  }
   bool IsRIPRelative() const {
     return Type == OpType::RIPRelative;
   }
+  bool IsRIPRelativeRelocation() const {
+    return Type == OpType::RIPRelativeRelocation;
+  }
   bool IsLiteral() const {
     return Type == OpType::Literal;
   }
+  bool IsLiteralRelocation() const {
+    return Type == OpType::LiteralRelocation;
+  }
   bool IsSIB() const {
     return Type == OpType::SIB;
   }
+  bool IsSIBRelocation() const {
+    return Type == OpType::SIBRelocation;
+  }
+
   uint64_t Literal() const {
     LOGMAN_THROW_A_FMT(IsLiteral(), "Precondition: must be a literal");
-    if (Data.Literal.SignExtend) {
-      return static_cast<int64_t>(static_cast<int32_t>(Data.Literal.Value));
-    }
     return Data.Literal.Value;
   }
 
@@ -159,30 +173,29 @@ struct DecodedOperand {
     } GPR;
 
     struct {
-      int32_t Displacement;
+      int64_t Displacement;
       uint8_t GPR;
-    } GPRIndirect;
+    } GPRIndirect; // Shared with GPRIndirectRelocation
 
     struct {
-      union {
-        int32_t s;
-        uint32_t u;
-      } Value;
-    } RIPLiteral;
+      int64_t Value;
+    } RIPLiteral; // Shared with RIPLiteralRelocation
 
     struct LiteralType {
-      uint32_t Value;
-      uint8_t Size : 7 ;
-      bool SignExtend : 1;
-      auto operator<=>(const LiteralType&) const = default;
+      uint64_t Value;
+      uint8_t Size;
     } Literal;
 
     struct {
-      int32_t Offset;
+      int64_t EntrypointOffset;
+    } LiteralRelocation;
+
+    struct {
+      int64_t Offset;
       uint8_t Scale;
       uint8_t Index; // ~0 invalid
       uint8_t Base; // ~0 invalid
-    } SIB;
+    } SIB; // Shared with SIBRelocation
   };
 
   TypeUnion Data;
@@ -205,6 +218,7 @@ struct DecodedInst {
   uint8_t ModRM;
   uint8_t SIB;
   uint8_t InstSize;
+  int8_t REXIndex;
 };
 
 union ModRMDecoded {

FEXCore/Source/Interface/GDBJIT/GDBJIT.cpp

@@ -42,7 +42,7 @@ void __attribute__((noinline)) __jit_debug_register_code() {
 
 namespace FEXCore {
 
-void GDBJITRegister(FEXCore::ExecutableFileInfo& Entry, uintptr_t VAFileStart, uint64_t GuestRIP, uintptr_t HostEntry,
+void GDBJITRegister(const FEXCore::ExecutableFileInfo& Entry, uintptr_t VAFileStart, uint64_t GuestRIP, uintptr_t HostEntry,
                     FEXCore::Core::DebugData& DebugData) {
   auto map = Entry.SourcecodeMap.get();
 
@@ -113,7 +113,7 @@ void GDBJITRegister(FEXCore::ExecutableFileInfo& Entry, uintptr_t VAFileStart, u
 } // namespace FEXCore
 #else
 namespace FEXCore {
-void GDBJITRegister(FEXCore::ExecutableFileInfo&, uintptr_t, uint64_t, uintptr_t, FEXCore::Core::DebugData&) {
+void GDBJITRegister(const FEXCore::ExecutableFileInfo&, uintptr_t, uint64_t, uintptr_t, FEXCore::Core::DebugData&) {
   ERROR_AND_DIE_FMT("GDBSymbols support not compiled in");
 }
 } // namespace FEXCore

FEXCore/Source/Interface/GDBJIT/GDBJIT.h

@@ -4,5 +4,5 @@
 #include <Interface/Core/JIT/DebugData.h>
 
 namespace FEXCore {
-void GDBJITRegister(FEXCore::ExecutableFileInfo&, uintptr_t VAFileStart, uint64_t GuestRIP, uintptr_t HostEntry, FEXCore::Core::DebugData&);
+void GDBJITRegister(const FEXCore::ExecutableFileInfo&, uintptr_t VAFileStart, uint64_t GuestRIP, uintptr_t HostEntry, FEXCore::Core::DebugData&);
 }

FEXCore/Source/Interface/IR/IR.json

@@ -105,6 +105,11 @@
       "PosInfinity = 2,",
       "TowardsZero = 3, /* Truncate */",
       "Host        = 4,"
+    ],
+    "class ConstPad : uint8_t": [
+      "NoPad = 0,",
+      "DoPad = 1,",
+      "AutoPad = 2,"
     ]
   },
   "Defines": [
@@ -142,6 +147,7 @@
     "MemOffsetType": "MemOffsetType",
     "BreakDefinition": "BreakDefinition",
     "RoundType": "RoundMode",
+    "ConstPad": "ConstPad",
     "FloatCompareOp": "FloatCompareOp",
     "NamedVectorConstant": "FEXCore::IR::NamedVectorConstant",
     "IndexNamedVectorConstant": "FEXCore::IR::IndexNamedVectorConstant",
@@ -930,11 +936,15 @@
         ]
       },
 
-      "GPR = Constant i64:$Constant": {
+      "GPR = Constant i64:$Constant, ConstPad:$Pad{IR::ConstPad::NoPad}, i32:$MaxBytes{0}": {
         "Desc": ["Generates a 64bit constant inside of a GPR",
                  "Unsupported to create a constant in FPR"
                 ],
-        "DestSize": "OpSize::i64Bit"
+        "DestSize": "OpSize::i64Bit",
+        "EmitValidation": [
+          "MaxBytes >= 0 && MaxBytes <= 8 && (MaxBytes & 1) == 0",
+          "MaxBytes == 0 || (Constant >> (MaxBytes * 8)) == 0"
+        ]
       },
 
       "InlineConstant i64:$Constant": {

FEXCore/Source/Interface/IR/IRDumper.cpp

@@ -149,6 +149,17 @@ static void PrintArg(fextl::stringstream* out, const IRListView*, RoundMode Arg)
   }();
 }
 
+static void PrintArg(fextl::stringstream* out, const IRListView*, ConstPad Arg) {
+  *out << [Arg] {
+    switch (Arg) {
+    case ConstPad::NoPad: return "NoPad";
+    case ConstPad::DoPad: return "DoPad";
+    case ConstPad::AutoPad: return "AutoPad";
+    }
+    return "<Unknown ConstPad Type>";
+  }();
+}
+
 static void PrintArg(fextl::stringstream* out, const IRListView*, NamedVectorConstant Arg) {
   *out << [Arg] {
     // clang-format off

FEXCore/Source/Interface/IR/IREmitter.h

@@ -239,22 +239,33 @@ public:
   DEF_ADDSUB(AddWithFlags)
   DEF_ADDSUB(SubWithFlags)
 
-  int64_t Constants[32];
+  struct ConstantData {
+    int64_t Value;
+    ConstPad Pad;
+    int32_t MaxBytes;
+    [[nodiscard]] auto operator<=>(const ConstantData&) const noexcept = default;
+  };
+  ConstantData Constants[32];
   Ref ConstantRefs[32];
   uint32_t NrConstants;
 
-  Ref Constant(int64_t Value) {
+  Ref Constant(int64_t Value, ConstPad Pad = IR::ConstPad::NoPad, int32_t MaxBytes = 0) {
+    const ConstantData Data {
+      .Value = Value,
+      .Pad = Pad,
+      .MaxBytes = MaxBytes,
+    };
     // Search for the constant in the pool.
     for (unsigned i = 0; i < std::min(NrConstants, 32u); ++i) {
-      if (Constants[i] == Value) {
+      if (Constants[i] == Data) {
         return ConstantRefs[i];
       }
     }
 
     // Otherwise, materialize a fresh constant and pool it.
-    Ref R = _Constant(Value);
+    Ref R = _Constant(Value, Pad, MaxBytes);
     unsigned i = (NrConstants++) & 31;
-    Constants[i] = Value;
+    Constants[i] = Data;
     ConstantRefs[i] = R;
     return R;
   }

FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp

@@ -94,8 +94,9 @@ private:
 
     // Remat if we can
     if (Rematerializable(IROp)) {
-      uint64_t Const = IROp->C<IR::IROp_Constant>()->Constant;
-      return IREmit->_Constant(Const);
+      const auto Op = IROp->C<IR::IROp_Constant>();
+      uint64_t Const = Op->Constant;
+      return IREmit->_Constant(Const, Op->Pad, Op->MaxBytes);
     }
 
     // Otherwise fill from stack

FEXCore/Source/Utils/Allocator/64BitAllocator.cpp

@@ -192,7 +192,7 @@ void OSAllocator_64Bit::DetermineVASize() {
 
   UPPER_BOUND = Size;
 
-#if _M_X86_64 // Last page cannot be allocated on x86
+#if ARCHITECTURE_x86_64 // Last page cannot be allocated on x86
   UPPER_BOUND -= FEXCore::Utils::FEX_PAGE_SIZE;
 #endif
 

FEXCore/Source/Utils/AllocatorHooks.cpp

@@ -5,6 +5,7 @@
 
 #include <malloc.h>
 #include <stdlib.h>
+#include <unistd.h>
 
 namespace FEXCore::Allocator {
 

FEXCore/Source/Utils/ArchHelpers/Arm64.cpp

@@ -1923,7 +1923,7 @@ static uint64_t HandleAtomicLoadstoreExclusive(uintptr_t ProgramCounter, uint64_
 [[nodiscard]]
 std::optional<int32_t> HandleUnalignedAccess(FEXCore::Core::InternalThreadState* Thread, UnalignedHandlerType HandleType,
                                              uintptr_t ProgramCounter, uint64_t* GPRs, bool IsJIT) {
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
   constexpr bool is_arm64 = true;
 #else
   constexpr bool is_arm64 = false;

FEXCore/Source/Utils/ArchHelpers/Arm64_stubs.cpp

@@ -5,7 +5,7 @@
 
 namespace FEXCore::ArchHelpers::Arm64 {
 
-#ifndef _M_ARM_64
+#ifndef ARCHITECTURE_arm64
 // These are stub implementations that exist only to allow instantiating the arm64 jit
 // on non arm platforms.
 

FEXCore/Source/Utils/ForcedAssert.cpp

@@ -3,7 +3,7 @@ namespace FEXCore::Assert {
 // This function can not be inlined
 [[noreturn]]
 __attribute__((noinline, naked)) void ForcedAssert() {
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
   asm volatile("ud2");
 #else
   asm volatile("hlt #1");

FEXCore/Source/Utils/LongJump.cpp

@@ -5,7 +5,7 @@
 #include <cstring>
 
 namespace FEXCore::UncheckedLongJump {
-#if defined(_M_ARM_64)
+#if defined(ARCHITECTURE_arm64)
 [[nodiscard]]
 FEX_DEFAULT_VISIBILITY FEX_NAKED uint64_t SetJump(JumpBuf& Buffer) {
   __asm volatile(R"(

FEXCore/Source/Utils/MemberFunctionToPointer.h

@@ -20,13 +20,13 @@ public:
   }
 
   uintptr_t GetConvertedPointer() const {
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
     // Itanium C++ ABI (https://itanium-cxx-abi.github.io/cxx-abi/abi.html#member-function-pointers)
     // Low bit of ptr specifies if this Member function pointer is virtual or not
     // Throw an assert if we were trying to cast a virtual member
     LOGMAN_THROW_A_FMT((PMF.ptr & 1) == 0, "C++ Pointer-To-Member representation didn't have low bit set to 0. Are you trying to cast a "
                                            "virtual member?");
-#elif defined(_M_ARM_64)
+#elif defined(ARCHITECTURE_arm64)
     // C++ ABI for the Arm 64-bit Architecture (IHI 0059E)
     // 4.2.1 Representation of pointer to member function
     // Differs from Itanium specification
@@ -39,14 +39,14 @@ public:
 
   // Gets the vtable entry position of a virtual member function.
   size_t GetVTableOffset() const {
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
     // Itanium C++ ABI (https://itanium-cxx-abi.github.io/cxx-abi/abi.html#member-function-pointers)
     // Low bit of ptr specifies if this Member function pointer is virtual or not
     // Throw an assert if we are not loading a virtual member.
     LOGMAN_THROW_A_FMT((PMF.ptr & 1) == 1, "C++ Pointer-To-Member representation didn't have low bit set to 1. This cast only works for "
                                            "virtual members.");
     return PMF.ptr & ~1ULL;
-#elif defined(_M_ARM_64)
+#elif defined(ARCHITECTURE_arm64)
     // C++ ABI for the Arm 64-bit Architecture (IHI 0059E)
     // 4.2.1 Representation of pointer to member function
     // Differs from Itanium specification

FEXCore/Source/Utils/SpinWaitLock.cpp

@@ -2,7 +2,7 @@
 #include "Utils/SpinWaitLock.h"
 
 namespace FEXCore::Utils::SpinWaitLock {
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 constexpr uint64_t NanosecondsInSecond = 1'000'000'000ULL;
 
 static uint32_t GetCycleCounterFrequency() {

FEXCore/Source/Utils/SpinWaitLock.h

@@ -29,7 +29,7 @@ namespace FEXCore::Utils::SpinWaitLock {
  *
  * On non-ARM platforms it is truly a spin-loop, which is okay for debugging only.
  */
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 
 #define LOADEXCLUSIVE(LoadExclusiveOp, RegSize)                 \
   /* Prime the exclusive monitor with the passed in address. */ \

FEXCore/Source/Utils/WritePriorityMutex.h

@@ -65,6 +65,7 @@ public:
       LOGMAN_THROW_A_FMT((Desired & WRITE_WAITER_COUNT_MASK) != 0, "Overflow in write-waiters!");
     } while (AtomicFutex.compare_exchange_strong(Expected, Desired, std::memory_order_acq_rel, std::memory_order_acquire) == false);
 #else
+    // Increment the number of writers waiting. The following loop will attempt to acquire the write-lock while decrementing the waiter count.
     Expected = AtomicFutex.fetch_add(WRITE_WAITER_INCREMENT);
     Desired = Expected + WRITE_WAITER_INCREMENT;
 #endif
@@ -101,6 +102,15 @@ public:
         LOGMAN_THROW_A_FMT((Desired & WRITE_OWNED_BIT) == WRITE_OWNED_BIT, "Somehow acquired a write-lock without it being set!");
         return;
       }
+
+      // Two paths to get here.
+      // Desired[31] = 1 (WRITE_OWNED_BIT)
+      // OR
+      // Desired[15:0] != 0 (READ_OWNER_COUNT_MASK)
+      // Meaning that there was already a writer that owned the lock, or reads were owning it.
+      // This thread already incremented `WRITE_WAITER_INCREMENT` before this loop.
+      // - Linux waits for the full 32-bits to change (With bitset wakeup).
+      // - Win32 also waits for the full 32-bits to change (with offset addr on the reader side to reduce stampeding).
       FutexWaitForWriteAvailable(Desired);
 
       Expected = AtomicFutex.load(std::memory_order_relaxed);
@@ -145,6 +155,12 @@ public:
         return;
       }
 
+      // Only one path to get here.
+      // Desired[31][29:16] != 0 (Either writer-owned, or writer-waiting)
+      // Desired[30][15:0]  == READ_WAIT_BIT and number of read-owners (draining to zero as write-side is set)
+      // - Linux waits for full 32-bit futex.
+      // - Win32 waits for upper 16-bits to not match (Either zero writer owned, writer-wait is draining, and `READ_WAITER_BIT` changed).
+      // Can get some spurious wake-ups which will `or` the `READ_WAITER_BIT` again, which does nothing.
       FutexWaitForReadAvailable(Desired);
 
       Expected = AtomicFutex.load(std::memory_order_relaxed);
@@ -167,7 +183,12 @@ public:
       }
     } while (AtomicFutex.compare_exchange_strong(Expected, Desired, std::memory_order_acq_rel, std::memory_order_acquire) == false);
 
-    // If success, then `Expected` has old value. Containing `READ_WAITER_BIT` which was just masked off, and also `WRITE_WAITER_COUNT_MASK`.
+    // `Expected` has old value. Containing `READ_WAITER_BIT` which was just masked off, and also `WRITE_WAITER_COUNT_MASK`.
+    //
+    // Two paths here to be careful about dead-locking other waiters:
+    // - If there are any writers waiting, those get priority to wake.
+    // - If there are zero writers waiting, and there are read waiters then make sure to wake them all.
+    // Failure to send wake events can cause readers to "infinitely" hang! (ignoring spurious wake-up).
     if ((Expected & WRITE_WAITER_COUNT_MASK)) {
       // Handle write-write handoff.
       FutexWakeWriter();
@@ -195,6 +216,11 @@ public:
 #endif
 
     // Handle read->write handoff if there are any waiting writers, and no readers left.
+    // Only one path here but still need to be careful to not dead-lock waiting writers.
+    // - If there are waiters /but/ this is not the final unlock_shared, then don't wake writer.
+    //   - Writer would wake and immediately sleep again if we woke on every unlock_shared.
+    // - If there are waiters and this is the final unlock_shared, then wake a /single/ writer.
+    // - We ignore any reader-waiters here as they must wait their turn for writers that are waiting.
     if ((Desired & WRITE_WAITER_COUNT_MASK) && (Desired & READ_OWNER_COUNT_MASK) == 0) {
       FutexWakeWriter();
     }
@@ -291,7 +317,7 @@ private:
   // WFE-read-lock is actually quite likely to succeed.
   // Return: true if the lock was acquired.
   bool Attempt_WFE_WriteLock() {
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
     const auto Begin = FEXCore::Utils::SpinWaitLock::GetCycleCounter();
     auto Now = Begin;
     const auto Duration = FEXCore::Utils::SpinWaitLock::CycleCounterFrequency / CYCLECOUNT_DIVISOR;
@@ -320,7 +346,7 @@ private:
 
   // Return: true if the lock was acquired.
   bool Attempt_WFE_ReadLock() {
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
     // Spin on a WFE for a short-amount of time, waiting for write-owned and writer-count to be zero.
     //  - Attempt to acquire read-lock at that point.
     //  - Don't add read-waiters bit on failure, return false.
@@ -353,14 +379,14 @@ private:
   }
 
   constexpr static uint32_t WRITE_OWNED_BIT = 1U << 31;
-  constexpr static uint32_t READ_WAITER_BIT = 1U << 15;
+  constexpr static uint32_t READ_WAITER_BIT = 1U << 30;
   constexpr static uint32_t WRITE_WAITER_OFFSET = 16;
   constexpr static uint32_t WRITE_WAITER_INCREMENT = 1U << WRITE_WAITER_OFFSET;
   constexpr static uint32_t READ_OWNER_INCREMENT = 1;
 
   // Count masks
-  constexpr static uint32_t WRITE_WAITER_COUNT_MASK = 0x7FFFU << WRITE_WAITER_OFFSET;
-  constexpr static uint32_t READ_OWNER_COUNT_MASK = 0x7FFFU;
+  constexpr static uint32_t WRITE_WAITER_COUNT_MASK = 0x3FFFU << WRITE_WAITER_OFFSET;
+  constexpr static uint32_t READ_OWNER_COUNT_MASK = 0xFFFFU;
 
   // Independent futex bit-set masks.
   // Wait for readers to drain.
@@ -373,9 +399,9 @@ private:
 
   // Layout:
   //    Bits[31]: Write-lock bit.
-  // Bits[30:16]: Write-waiter count.
-  //    Bits[15]: Read-waiter bit.
-  //  Bits[14:0]: Read-owner count.
+  //    Bits[30]: Read-waiter bit.
+  // Bits[29:16]: Write-waiter count.
+  //  Bits[15:0]: Read-owner count.
   uint32_t Futex {};
 };
 } // namespace FEXCore::Utils::WritePriorityMutex

FEXCore/include/FEXCore/Core/CodeCache.h

@@ -7,6 +7,8 @@
 #include <FEXCore/fextl/set.h>
 #include <FEXCore/fextl/string.h>
 #include <FEXCore/fextl/vector.h>
+#include <FEXCore/fextl/robin_map.h>
+#include <FEXCore/HLE/SourcecodeResolver.h>
 
 #include <atomic>
 #include <cstdint>
@@ -26,27 +28,37 @@ namespace HLE {
   struct SourcecodeMap;
 } // namespace HLE
 
+enum class GuestRelocationType : uint32_t { Rel32, Rel64 };
+
 // Generic information associated with an executable file.
 struct ExecutableFileInfo {
-  ~ExecutableFileInfo();
-
 #if __clang_major__ < 16
   // Workaround for broken aggregate-initialization with std::piecewise_construct
   ExecutableFileInfo(fextl::unique_ptr<HLE::SourcecodeMap>, uint64_t, fextl::string);
   ExecutableFileInfo() = default;
 #endif
 
-  fextl::unique_ptr<HLE::SourcecodeMap> SourcecodeMap;
+  // This legacy field must be assignable through const-references
+  mutable fextl::unique_ptr<HLE::SourcecodeMap> SourcecodeMap;
+
   uint64_t FileId = 0;
   fextl::string Filename;
+  fextl::robin_map<uint32_t, GuestRelocationType> Relocations;
 };
 
 // Information associated with a specific section of an executable file
 struct ExecutableFileSectionInfo {
-  ExecutableFileInfo& FileInfo;
+  const ExecutableFileInfo& FileInfo;
 
   // Start address that the file is mapped to.
+  // NOTE: Since executable files may be mapped multiple times, this can depend on the queried section.
   uintptr_t FileStartVA;
+
+  // Start address of the section mapping
+  uintptr_t BeginVA;
+
+  // End address that of the section mapping
+  uintptr_t EndVA;
 };
 
 using CodeMapFileId = uint64_t;
@@ -175,8 +187,9 @@ public:
   /**
    * Loads a code cache from mapped memory and appends it to the current Core state.
    * TODO: Optionally recompiles all contained code blocks at runtime for validation.
+   * Returns false if the provided cache file is invalid, and true otherwise.
    */
-  virtual void LoadData(Core::InternalThreadState&, std::byte* MappedCacheFile, const ExecutableFileSectionInfo&) = 0;
+  virtual bool LoadData(Core::InternalThreadState*, std::byte* MappedCacheFile, const ExecutableFileSectionInfo&) = 0;
 
   /**
    * Bundles the current Core state (CodeBuffer, GuestToHostMapping, ...) to a code cache and writes it to the given file descriptor.

FEXCore/include/FEXCore/Core/CoreState.h

@@ -320,71 +320,51 @@ struct FallbackABIInfo {
 
 struct JITPointers {
 
-  struct {
-    // Process specific
+  // Process specific
+  uint64_t PrintValue {};
+  uint64_t PrintVectorValue {};
+  uint64_t ThreadRemoveCodeEntryFromJIT {};
+  uint64_t CPUIDObj {};
+  uint64_t CPUIDFunction {};
+  uint64_t XCRFunction {};
+  uint64_t SyscallHandlerObj {};
+  uint64_t SyscallHandlerFunc {};
+  uint64_t ExitFunctionLink {};
+  uint64_t MonoBackpatcherWrite {};
+  uint64_t LUDIV {};
+  uint64_t LDIV {};
+  uint64_t ThunkCallbackRet {};
 
-    uint64_t PrintValue {};
-    uint64_t PrintVectorValue {};
-    uint64_t ThreadRemoveCodeEntryFromJIT {};
-    uint64_t CPUIDObj {};
-    uint64_t CPUIDFunction {};
-    uint64_t XCRFunction {};
-    uint64_t SyscallHandlerObj {};
-    uint64_t SyscallHandlerFunc {};
-    uint64_t ExitFunctionLink {};
-    uint64_t MonoBackpatcherWrite {};
+  // Handles returning/calling ARM64EC code from the JIT, expects the target PC in TMP3
+  uint64_t ExitFunctionEC {};
 
-    // Handles returning/calling ARM64EC code from the JIT, expects the target PC in TMP3
-    uint64_t ExitFunctionEC {};
+  FallbackABIInfo FallbackHandlerPointers[FallbackHandlerIndex::OPINDEX_MAX];
+  uint64_t NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX];
+  uint64_t IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_MAX];
+  uint64_t TelemetryValueAddresses[FEXCore::Telemetry::TYPE_LAST];
 
-    FallbackABIInfo FallbackHandlerPointers[FallbackHandlerIndex::OPINDEX_MAX];
-    uint64_t NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX];
-    uint64_t IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_MAX];
-    uint64_t TelemetryValueAddresses[FEXCore::Telemetry::TYPE_LAST];
+  /**
+   * @name Dispatcher pointers
+   * @{ */
+  uint64_t DispatcherLoopTop {};
+  uint64_t DispatcherLoopTopFillSRA {};
+  uint64_t DispatcherLoopTopEnterEC {};
+  uint64_t DispatcherLoopTopEnterECFillSRA {};
+  uint64_t ExitFunctionLinker {};
+  uint64_t ThreadStopHandlerSpillSRA {};
+  uint64_t ThreadPauseHandlerSpillSRA {};
+  uint64_t GuestSignal_SIGILL {};
+  uint64_t GuestSignal_SIGTRAP {};
+  uint64_t GuestSignal_SIGSEGV {};
+  uint64_t SignalReturnHandler {};
+  uint64_t SignalReturnHandlerRT {};
+  uint64_t L2Pointer {};
+  uint64_t LUDIVHandler {};
+  uint64_t LDIVHandler {};
+  /**  @} */
 
-    // Thread Specific
-    /**
-     * @name Dispatcher pointers
-     * @{ */
-    uint64_t DispatcherLoopTop {};
-    uint64_t DispatcherLoopTopFillSRA {};
-    uint64_t DispatcherLoopTopEnterEC {};
-    uint64_t DispatcherLoopTopEnterECFillSRA {};
-    uint64_t ExitFunctionLinker {};
-    uint64_t ThreadStopHandlerSpillSRA {};
-    uint64_t ThreadPauseHandlerSpillSRA {};
-    uint64_t GuestSignal_SIGILL {};
-    uint64_t GuestSignal_SIGTRAP {};
-    uint64_t GuestSignal_SIGSEGV {};
-    uint64_t SignalReturnHandler {};
-    uint64_t SignalReturnHandlerRT {};
-    uint64_t L2Pointer {};
-    /**  @} */
-
-    // Copy of process-wide named vector constants data.
-    alignas(16) uint64_t NamedVectorConstants[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX][2];
-  } Common;
-
-  union {
-    struct {
-      // Process specific
-      uint64_t LUDIV {};
-      uint64_t LDIV {};
-
-      // Thread Specific
-
-      /**
-       * @name Dispatcher pointers
-       * @{ */
-      uint64_t LUDIVHandler {};
-      uint64_t LDIVHandler {};
-      /**  @} */
-    } AArch64;
-
-    struct {
-      // None so far
-    } X86;
-  };
+  // Copy of process-wide named vector constants data.
+  alignas(16) uint64_t NamedVectorConstants[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX][2];
 };
 
 // Each guest JIT frame has one of these
@@ -420,7 +400,7 @@ struct CpuStateFrame {
 
   InternalThreadState* Thread;
 
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
   // Set by the kernel on ARM64EC whenever the JIT should cooperatively suspend running guest code.
   uint32_t SuspendDoorbell {};
 #endif

FEXCore/include/FEXCore/HLE/SyscallHandler.h

@@ -63,7 +63,7 @@ public:
   virtual void MarkOvercommitRange(uint64_t Start, uint64_t Length) {}
   virtual void UnmarkOvercommitRange(uint64_t Start, uint64_t Length) {}
   virtual ExecutableRangeInfo QueryGuestExecutableRange(FEXCore::Core::InternalThreadState* Thread, uint64_t Address) = 0;
-  virtual std::optional<ExecutableFileSectionInfo> LookupExecutableFileSection(Core::InternalThreadState& Thread, uint64_t GuestAddr) = 0;
+  virtual std::optional<ExecutableFileSectionInfo> LookupExecutableFileSection(Core::InternalThreadState* Thread, uint64_t GuestAddr) = 0;
 
   virtual void PreCompile() {}
 

FEXCore/include/FEXCore/Utils/AllocatorHooks.h

@@ -31,7 +31,7 @@ FEX_DEF_NUM_OPS(ProtectOptions)
 inline void* VirtualAlloc(void* Base, size_t Size, bool Execute = false, bool Commit = true) {
   // Allocate top-down to avoid polluting the lower VA space, as even on 64-bit some programs (i.e. LuaJIT) require allocations below 4GB.
   DWORD Flags = (Commit ? MEM_COMMIT : 0) | MEM_RESERVE | MEM_TOP_DOWN;
-#ifdef _M_ARM_64EC
+#ifdef ARCHITECTURE_arm64ec
   MEM_EXTENDED_PARAMETER Parameter {};
   if (Execute) {
     Parameter.Type = MemExtendedParameterAttributeFlags;

FEXCore/include/FEXCore/Utils/LongJump.h

@@ -9,7 +9,7 @@
 // a libc implementation that does not implement std::longjmp.
 namespace FEXCore::UncheckedLongJump {
 // JumpBuf definition needs to be public because the frontend needs to understand it.
-#if defined(_M_ARM_64)
+#if defined(ARCHITECTURE_arm64)
 struct JumpBuf {
   // All the registers that are required by AAPCS64 to save.
   // GPRs

FEXCore/include/FEXCore/Utils/SHMStats.h

@@ -4,12 +4,12 @@
 #include <cstddef>
 #include <cstdint>
 
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
 #include <x86intrin.h>
 #endif
 
 namespace FEXCore::SHMStats {
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 /**
  * @brief Get the raw cycle counter with synchronizing isb.
  *
@@ -79,12 +79,12 @@ template<typename T, size_t FlatOffset = 0>
 class AccumulationBlock final {
 public:
   AccumulationBlock(T* Stat)
-    : Begin {GetCycleCounter()}
+    : Begin {Stat ? GetCycleCounter() : 0}
     , Stat {Stat} {}
 
   ~AccumulationBlock() {
-    const auto Duration = GetCycleCounter() - Begin + FlatOffset;
     if (Stat) {
+      const auto Duration = GetCycleCounter() - Begin + FlatOffset;
       auto ref = std::atomic_ref<T>(*Stat);
       ref.fetch_add(Duration, std::memory_order_relaxed);
     }

FEXCore/include/FEXCore/Utils/SignalScopeGuards.h

@@ -127,7 +127,7 @@ public:
 
   ~DeferredSignalRefCountGuard() {
     if (Thread) {
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
       // Needs to be atomic so that operations can't end up getting reordered around this.
       // Without this, the refcount and the signal access could get reordered.
       auto Result = Thread->CurrentFrame->State.DeferredSignalRefCount.Decrement(1);

FEXCore/unittests/APITests/CMakeLists.txt

@@ -1,6 +1,6 @@
 file(GLOB_RECURSE TESTS CONFIGURE_DEPENDS *.cpp)
 
-set (LIBS fmt::fmt vixl Catch2::Catch2WithMain FEXCore_Base JemallocLibs)
+set(LIBS fmt::fmt vixl Catch2::Catch2WithMain FEXCore_Base JemallocLibs)
 foreach(TEST ${TESTS})
   get_filename_component(TEST_NAME ${TEST} NAME_WLE)
   add_executable(FEXCore_Tests_${TEST_NAME} ${TEST})
@@ -10,8 +10,7 @@ foreach(TEST ${TESTS})
   catch_discover_tests(FEXCore_Tests_${TEST_NAME} TEST_SUFFIX ".${TEST_NAME}.FEXCore_Tests")
 endforeach()
 
-add_custom_target(
-  fexcore_apitests
+add_custom_target(fexcore_apitests
   WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/"
   USES_TERMINAL
   COMMAND "ctest" "--output-on-failure" "--timeout" "302" ${TEST_JOB_FLAG} "-R" "\.*.FEXCore_Tests$$")

FEXCore/unittests/CMakeLists.txt

@@ -1,4 +1,4 @@
-if (NOT MINGW_BUILD)
+if (NOT MINGW)
   add_subdirectory(Emitter/)
   add_subdirectory(APITests/)
 endif()

FEXCore/unittests/Emitter/CMakeLists.txt

@@ -1,6 +1,6 @@
 file(GLOB_RECURSE TESTS CONFIGURE_DEPENDS *.cpp)
 
-set (LIBS fmt::fmt vixl Catch2::Catch2WithMain FEXCore_Base JemallocLibs)
+set(LIBS fmt::fmt vixl Catch2::Catch2WithMain FEXCore_Base JemallocLibs)
 foreach(TEST ${TESTS})
   get_filename_component(TEST_NAME ${TEST} NAME_WLE)
   add_executable(Emitter_${TEST_NAME} ${TEST})
@@ -10,8 +10,7 @@ foreach(TEST ${TESTS})
   catch_discover_tests(Emitter_${TEST_NAME} TEST_SUFFIX ".${TEST_NAME}.Emitter")
 endforeach()
 
-add_custom_target(
-  emitter_tests
+add_custom_target(emitter_tests
   WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/"
   USES_TERMINAL
   COMMAND "ctest" "--output-on-failure" "--timeout" "302" ${TEST_JOB_FLAG} "-R" "\.*.Emitter$$")

FEXHeaderUtils/CMakeLists.txt

@@ -1,8 +1,7 @@
 add_library(FEXHeaderUtils INTERFACE)
 
 # Check for syscall support here
-check_cxx_source_compiles(
-  "
+check_cxx_source_compiles("
   #include <sched.h>
   int main() {
   return ::getcpu(nullptr, nullptr);
@@ -11,10 +10,9 @@ check_cxx_source_compiles(
 if (HAS_SYSCALL_GETCPU)
   message(STATUS "Has getcpu helper")
   target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_GETCPU=1)
-endif ()
+endif()
 
-check_cxx_source_compiles(
-  "
+check_cxx_source_compiles("
   #include <unistd.h>
   int main() {
   return ::gettid();
@@ -23,10 +21,9 @@ check_cxx_source_compiles(
 if (HAS_SYSCALL_GETTID)
   message(STATUS "Has gettid helper")
   target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_GETTID=1)
-endif ()
+endif()
 
-check_cxx_source_compiles(
-  "
+check_cxx_source_compiles("
   #include <signal.h>
   int main() {
   return ::tgkill(0, 0, 0);
@@ -35,10 +32,9 @@ check_cxx_source_compiles(
 if (HAS_SYSCALL_TGKILL)
   message(STATUS "Has tgkill helper")
   target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_TGKILL=1)
-endif ()
+endif()
 
-check_cxx_source_compiles(
-  "
+check_cxx_source_compiles("
   #include <sys/stat.h>
   int main() {
   return ::statx(0, nullptr, 0, 0, nullptr);
@@ -47,10 +43,9 @@ check_cxx_source_compiles(
 if (HAS_SYSCALL_STATX)
   message(STATUS "Has statx helper")
   target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_STATX=1)
-endif ()
+endif()
 
-check_cxx_source_compiles(
-  "
+check_cxx_source_compiles("
   #include <stdio.h>
   int main() {
   return ::renameat2(0, nullptr, 0, nullptr, 0);
@@ -59,6 +54,6 @@ check_cxx_source_compiles(
 if (HAS_SYSCALL_RENAMEAT2)
   message(STATUS "Has renameat2 helper")
   target_compile_definitions(FEXHeaderUtils INTERFACE HAS_SYSCALL_RENAMEAT2=1)
-endif ()
+endif()
 
 target_include_directories(FEXHeaderUtils INTERFACE .)

FEXHeaderUtils/FEXHeaderUtils/Syscalls.h

@@ -86,7 +86,7 @@ inline int32_t statx(int dirfd, const char* pathname, int32_t flags, uint32_t ma
 }
 
 inline int32_t renameat2(int olddirfd, const char* oldpath, int newdirfd, const char* newpath, unsigned int flags) {
-#if defined(HAS_SYSCALL_STATX) && HAS_SYSCALL_STATX
+#if defined(HAS_SYSCALL_RENAMEAT2) && HAS_SYSCALL_RENAMEAT2
   return ::renameat2(olddirfd, oldpath, newdirfd, newpath, flags);
 #else
   return ::syscall(SYS_renameat2, olddirfd, oldpath, newdirfd, newpath, flags);

Scripts/DefinitionExtract.py

@@ -534,7 +534,7 @@ def main():
         "-isystem", "/usr/x86_64-linux-gnu/include/",
         "-O2",
         "--target=x86_64-linux-unknown",
-        "-D_M_X86_64",
+        "-DARCHITECTURE_x86_64",
     ]
 
     # Add all the arguments to the different lists

Scripts/InstallFEX.py

@@ -1,9 +1,15 @@
 #!/usr/bin/python3
 import os
 import subprocess
+import platform
 import sys
 import re
 
+try:
+    from packaging.version import Version as version_check
+except:
+    from pkg_resources import parse_version as version_check
+
 _Arch = None
 def GetArch():
     global _Arch
@@ -337,12 +343,24 @@ def ExitWithStatus(Status):
     subprocess.call(["sudo", "-K"])
     sys.exit(Status)
 
+def GetKernelVersion():
+    # eg: `6.14.4-061404-generic`
+    return platform.uname().release.split("-")[0]
+
+def IsSupportedKernel():
+    return version_check(GetKernelVersion()) >= version_check("5.15")
+
 def main():
     # Only run on supported arch
     if not IsSupportedArch():
         print ( "{} is not a supported architecture".format(GetArch()))
         ExitWithStatus(-1)
 
+    # Only run on a new enough kernel
+    if not IsSupportedKernel():
+        print ( "Kernel {} is too old. FEX needs 5.15 minimum".format(GetKernelVersion()))
+        ExitWithStatus(-1)
+
     if not IsSupportedDistro():
         Distro = GetDistro()
         print ( "'{} {}' is not a supported distro".format(Distro[0], Distro[1]))

Scripts/StructPackVerifier.py

@@ -669,14 +669,14 @@ def main():
         "-isystem", "/usr/x86_64-linux-gnu/include",
         "-O2",
         "--target=x86_64-linux-unknown",
-        "-D_M_X86_64",
+        "-DARCHITECTURE_x86_64",
     ]
 
     args_aarch64 = [
         "-isystem", "/usr/aarch64-linux-gnu/include",
         "-O2",
         "--target=aarch64-linux-unknown",
-        "-D_M_ARM_64",
+        "-DARCHITECTURE_arm64",
     ]
 
     args_x86_win32 = [

Source/CMakeLists.txt

@@ -6,6 +6,6 @@ add_compile_options($<$<COMPILE_LANGUAGE:CXX>:-fno-strict-aliasing>)
 add_subdirectory(Common/)
 add_subdirectory(Tools/)
 
-if (MINGW_BUILD)
+if (MINGW)
   add_subdirectory(Windows/)
 endif()

Source/Common/AsyncNet.h

@@ -72,7 +72,7 @@ struct tcp_socket {
    */
   size_t write_some(const mutable_buffer& Buffers, error& ec) {
     auto iov = (iovec*)alloca(sizeof(mutable_buffer) * Buffers.count_chunks());
-    size_t NumIovs = 0;
+    decltype(msghdr::msg_iovlen) NumIovs = 0;
     for (auto Buffer = &Buffers; Buffer; Buffer = Buffer->Next) {
       iov[NumIovs].iov_base = Buffer->Data.data();
       iov[NumIovs].iov_len = Buffer->Data.size_bytes();
@@ -120,7 +120,7 @@ struct tcp_socket {
 private:
   static size_t read_some_from_fd(const mutable_buffer& Buffers, error& ec, int FD) {
     auto iov = (iovec*)alloca(sizeof(mutable_buffer) * Buffers.count_chunks());
-    size_t NumIovs = 0;
+    decltype(msghdr::msg_iovlen) NumIovs = 0;
     for (auto Buffer = &Buffers; Buffer; Buffer = Buffer->Next) {
       iov[NumIovs].iov_base = Buffer->Data.data();
       iov[NumIovs].iov_len = Buffer->Data.size_bytes();

Source/Common/CMakeLists.txt

@@ -8,11 +8,10 @@ set(SRCS
   HostFeatures.cpp
   JSONPool.cpp
   SHMStats.cpp
-  VolatileMetadata.cpp
-  )
+  VolatileMetadata.cpp)
 
-if (NOT MINGW_BUILD)
-  list (APPEND SRCS
+if (NOT MINGW)
+  list(APPEND SRCS
     FEXServerClient.cpp
     FileFormatCheck.cpp)
 endif()
@@ -24,5 +23,4 @@ target_include_directories(${NAME} PRIVATE ${CMAKE_BINARY_DIR}/generated)
 set_target_properties(${NAME} PROPERTIES
   C_VISIBILITY_PRESET hidden
   CXX_VISIBILITY_PRESET hidden
-  VISIBILITY_INLINES_HIDDEN TRUE
-)
+  VISIBILITY_INLINES_HIDDEN TRUE)

Source/Common/Config.cpp

@@ -622,6 +622,7 @@ fextl::string GetCacheDirectory() {
     return CacheOverride;
   }
 
+#ifndef _WIN32
 #ifdef FEX_STEAM_SUPPORT
   const char* SteamDataPath = getenv("STEAM_COMPAT_SHADER_PATH");
   if (SteamDataPath) {
@@ -632,6 +633,10 @@ fextl::string GetCacheDirectory() {
   const char* HomeDir = GetHomeDirectory();
   const char* CacheXDG = getenv("XDG_CACHE_HOME");
   return (CacheXDG ? fextl::string {CacheXDG} : (fextl::string {HomeDir} + "/.cache")) + "/fex-emu/";
+#else
+  const char* PrefixAppData = getenv("LOCALAPPDATA");
+  return PrefixAppData ? (fextl::string {PrefixAppData} + "\\fex-emu\\") : fextl::string {".\\"};
+#endif
 }
 
 fextl::string GetConfigFileLocation(bool Global, const PortableInformation& PortableInfo) {

Source/Common/FEXServerClient.cpp

@@ -405,6 +405,29 @@ int RequestPIDFD(int ServerSocket) {
   return RequestPIDFDPacket(ServerSocket, PacketType::TYPE_GET_PID_FD);
 }
 
+void PopulateCodeCache(int ServerSocket, int ProgramFD, bool HasMultiblock) {
+  fasio::error ec;
+  fasio::tcp_socket Socket {ServerSocket};
+
+  // Send request
+  FEXServerRequestPacket Req {
+    .Header {.Type = HasMultiblock ? PacketType::TYPE_POPULATE_CODE_CACHE : PacketType::TYPE_POPULATE_CODE_CACHE_NO_MULTIBLOCK}};
+
+  fasio::mutable_buffer WriteBuffer {std::as_writable_bytes(std::span {&Req, 1})};
+  WriteBuffer.FD = &ProgramFD;
+  write(Socket, WriteBuffer, ec);
+  if (ec != fasio::error::success) {
+    return;
+  }
+
+  // Wait for success response to ensure FEXServer completed any pending cache generation.
+  // The cache loading code handles missing caches gracefully, so we don't
+  // actually care about the result here.
+  FEXServerResultPacket Res {};
+  fasio::mutable_buffer ResBuffer {std::as_writable_bytes(std::span {&Res, 1})};
+  read(Socket, ResBuffer, ec);
+}
+
 int RequestCodeMapFD(int ServerSocket, int ProgramFD, bool HasMultiblock) {
   fasio::tcp_socket Socket {ServerSocket};
   FEXServerRequestPacket Req {

Source/Common/FEXServerClient.h

@@ -19,6 +19,8 @@ enum class PacketType {
   TYPE_GET_LOG_FD,
   TYPE_GET_ROOTFS_PATH,
   TYPE_GET_PID_FD,
+  TYPE_POPULATE_CODE_CACHE,
+  TYPE_POPULATE_CODE_CACHE_NO_MULTIBLOCK,
   TYPE_QUERY_CODE_MAP,
   TYPE_QUERY_CODE_MAP_NO_MULTIBLOCK,
 
@@ -122,6 +124,16 @@ fextl::string RequestRootFSPath(int ServerSocket);
  */
 int RequestPIDFD(int ServerSocket);
 
+/**
+ * @brief Request FEXServer to populate the disk cache for the given executable
+ *        and any libraries referenced in its code map
+ *
+ * @param ServerSocket - Socket to the server
+ * @param ProgramFD - FD for program binary
+ * @param HasMultiblock - true if multiblock is enabled (used for selecting code maps)
+ */
+void PopulateCodeCache(int ServerSocket, int ProgramFD, bool HasMultiblock);
+
 /**
  * @brief Request FEXServer to create a new code map for disk cache population
  *

Source/Common/HostFeatures.cpp

@@ -10,7 +10,7 @@
 #include <range/v3/view/split.hpp>
 #include <range/v3/view/transform.hpp>
 
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
 #include "Common/X86Features.h"
 #endif
 
@@ -19,7 +19,7 @@ namespace FEX {
 void FillMIDRInformationViaLinux(FEXCore::HostFeatures* Features) {
   auto Cores = FEX::CPUInfo::CalculateNumberOfCPUs();
   Features->CPUMIDRs.resize(Cores);
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
   for (size_t i = 0; i < Cores; ++i) {
     std::error_code ec {};
     fextl::string MIDRPath = fextl::fmt::format("/sys/devices/system/cpu/cpu{}/regs/identification/midr_el1", i);
@@ -38,7 +38,7 @@ void FillMIDRInformationViaLinux(FEXCore::HostFeatures* Features) {
 #endif
 }
 
-#if defined(_M_ARM_64) && !defined(VIXL_SIMULATOR)
+#if defined(ARCHITECTURE_arm64) && !defined(VIXL_SIMULATOR)
 __attribute__((naked)) static uint64_t ReadSVEVectorLengthInBits() {
   ///< Can't use rdvl instruction directly because compilers will complain that sve/sme is required.
   __asm(R"(
@@ -54,7 +54,7 @@ static int ReadSVEVectorLengthInBits() {
 }
 #endif
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 #define GetSysReg(name, reg)                         \
   static uint64_t Get_##name() {                     \
     uint64_t Result {};                              \
@@ -446,7 +446,7 @@ void FEX::CPUFeatures::FillFeatureFlags() {
   }
 }
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 static uint32_t GetFPCR() {
   uint64_t Result {};
   __asm("mrs %[Res], FPCR" : [Res] "=r"(Result));
@@ -550,7 +550,7 @@ static void HandleErrata(FEXCore::HostFeatures* HostFeatures, uint64_t MIDR) {
   const uint32_t MIDR_Implementer = GetMIDRImplementer(MIDR);
   const uint32_t MIDR_PartNum = GetMIDRPartNum(MIDR);
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
   if (MIDR_Implementer == Implementer_QCOM && MIDR_PartNum == PartNum_Oryon1) {
     // Work around an errata in Qualcomm's Oryon.
     // While this CPU implements the RAND extension:
@@ -646,7 +646,7 @@ void FetchHostFeatures(FEX::CPUFeatures& Features, FEXCore::HostFeatures& HostFe
     WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
   }
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
   // Test if this CPU supports float exception trapping by attempting to enable
   // On unsupported these bits are architecturally defined as RAZ/WI
   constexpr uint32_t ExceptionEnableTraps = (1U << 8) |  // Invalid Operation float exception trap enable
@@ -696,7 +696,7 @@ void FetchHostFeatures(FEX::CPUFeatures& Features, FEXCore::HostFeatures& HostFe
     HostFeatures.DCacheLineSize = HostFeatures.ICacheLineSize = 64;
   }
 
-#if defined(_M_X86_64) && !defined(VIXL_SIMULATOR)
+#if defined(ARCHITECTURE_x86_64) && !defined(VIXL_SIMULATOR)
   FEX::X86::Features Feature {};
   HostFeatures.SupportsAES = Feature.Feat_aes;
   HostFeatures.SupportsCRC = Feature.Feat_crc;
@@ -725,7 +725,7 @@ FEXCore::HostFeatures FetchHostFeatures() {
   if (!CPUFeatureRegisters().empty()) {
     Features = GetCPUFeaturesFromConfig(CPUFeatureRegisters());
   } else {
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
     Features = CPUFeaturesAll {};
 
     // Vixl simulator doesn't support AFP.
@@ -739,7 +739,7 @@ FEXCore::HostFeatures FetchHostFeatures() {
 
   uint64_t CTR = 0;
   uint64_t MIDR = 0;
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
   // We need to get the CPU's cache line size
   // We expect sane targets that have correct cacheline sizes across clusters
   __asm volatile("mrs %[ctr], ctr_el0" : [ctr] "=r"(CTR));

Source/Common/SHMStats.h

@@ -12,7 +12,7 @@ namespace FEXCore::Core {
 struct InternalThreadState;
 }
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 static inline void store_memory_barrier() {
   asm volatile("dmb ishst;" ::: "memory");
 }

Source/Common/X86Features.h

@@ -1,7 +1,7 @@
 #pragma once
 #include <cstdint>
 
-#ifdef _M_X86_64
+#ifdef ARCHITECTURE_x86_64
 #include <cpuid.h>
 
 namespace FEX::X86 {

Source/Steam/CMakeLists.txt

@@ -1,28 +1,20 @@
-add_executable(FEXCompatTool
-  CompatTool.cpp)
+set(LIBS FEXCore Common CommonTools JemallocLibs)
 
-target_link_libraries(FEXCompatTool
-  PRIVATE
-  FEXCore Common CommonTools JemallocLibs)
+add_executable(FEXCompatTool CompatTool.cpp)
 
-install(TARGETS FEXCompatTool
-  RUNTIME
-    DESTINATION /
-    COMPONENT Runtime
-)
+target_link_libraries(FEXCompatTool PRIVATE ${LIBS})
 
-add_executable(FEXServerManager
-  ServerManager.cpp)
+install(TARGETS FEXCompatTool RUNTIME
+  DESTINATION /
+  COMPONENT Runtime)
 
-target_link_libraries(FEXServerManager
-  PRIVATE
-  FEXCore Common CommonTools JemallocLibs)
+add_executable(FEXServerManager ServerManager.cpp)
 
-install(TARGETS FEXServerManager
-  RUNTIME
-    DESTINATION bin
-    COMPONENT Runtime
-)
+target_link_libraries(FEXServerManager PRIVATE ${LIBS})
+
+install(TARGETS FEXServerManager RUNTIME
+  DESTINATION bin
+  COMPONENT Runtime)
 
 # Description json gets installed into root of depot
 install(FILES emulator.json
@@ -31,3 +23,6 @@ install(FILES emulator.json
 install(FILES ConfigTemplate.json
   DESTINATION /
   COMPONENT Runtime)
+install(FILES toolmanifest.vdf
+  DESTINATION /
+  COMPONENT Runtime)

Source/Steam/ServerManager.cpp

@@ -3,6 +3,7 @@
 #include "Common/FEXServerClient.h"
 
 #include <cstdio>
+#include <errno.h>
 #include <unistd.h>
 #include <poll.h>
 
@@ -17,14 +18,14 @@ void AssertHandler(const char* Message) {
   return MsgHandler(LogMan::ASSERT, Message);
 }
 
-void SignalPVToContinue() {
+void SignalPVToContinue(int* original_stdout) {
   // Tell pressure-vessel that the startup was a success.
   const auto ReadyMsg = "READY=1\n";
-  write(STDOUT_FILENO, ReadyMsg, strlen(ReadyMsg));
+  write(*original_stdout, ReadyMsg, strlen(ReadyMsg));
 
   // pressure-vessel is waiting for EOF on STDOUT from this process to ensure it can run FEX processes.
-  // dup2 atomically replaces stdout with a copy of stderr to achieve this.
-  dup2(STDERR_FILENO, STDOUT_FILENO);
+  close(*original_stdout);
+  *original_stdout = -1;
 }
 
 struct PipesType {
@@ -48,6 +49,21 @@ int main(int argc, const char** argv, char** const envp) {
   // Reload the meta layer
   FEXCore::Config::ReloadMetaLayer();
 
+  // Move the ready-indicator pipe from stdout to some other fd,
+  // and mark it so the FEXServer won't inherit it. Otherwise the FEXServer
+  // will hold it open, preventing pressure-vessel from detecting that
+  // we are ready.
+  int original_stdout = fcntl(STDOUT_FILENO, F_DUPFD_CLOEXEC, /* minimum fd = */ 3);
+  if (original_stdout < 0) {
+    perror("F_DUPFD_CLOEXEC");
+    return 126;
+  }
+  // Replace stdout with a copy of our original stderr.
+  if (dup2(STDERR_FILENO, STDOUT_FILENO) != STDOUT_FILENO) {
+    perror("dup2");
+    return 126;
+  }
+
   auto pipes = get_pipe();
 
   // Set the write side to close on exec.
@@ -62,7 +78,7 @@ int main(int argc, const char** argv, char** const envp) {
   }
 
   // FEXServer is now running. Tell PV to continue.
-  SignalPVToContinue();
+  SignalPVToContinue(&original_stdout);
 
   // Don't need the read pipe anymore.
   close(pipes.read_pipe);
@@ -72,21 +88,20 @@ int main(int argc, const char** argv, char** const envp) {
   close(ServerFD);
   ServerFD = -1;
 
-  // stdin will be a pipe, so wait until that FD is closed.
+  // Do a blocking read, discarding any written data and wait for EOF.
   while (true) {
-    pollfd p {
-      .fd = STDIN_FILENO,
-      .events = POLLRDHUP,
-      .revents = 0,
-    };
-
-    int events = poll(&p, 1, -1);
-    if (events == -1 && errno == EINTR) {
-      continue;
-    }
-
-    if (events > 0 && (p.revents & (POLLRDHUP | POLLERR | POLLHUP | POLLNVAL))) {
-      // Error or pressure-vessel hung-up.
+    char buf[4096];
+    auto read_len = ::read(STDIN_FILENO, buf, sizeof(buf));
+    if (read_len < 0) {
+      if (errno == EINTR || errno == EAGAIN) {
+        // Interrupted, try again.
+        continue;
+      } else {
+        // Error on read.
+        break;
+      }
+    } else if (read_len == 0) {
+      // EOF
       break;
     }
   }

Source/Steam/toolmanifest.vdf

@@ -0,0 +1,8 @@
+"manifest"
+{
+  "commandline" "/FEXCompatTool %verb%"
+  "filter_exclusive_priority" "2"
+  "version" "2"
+  "use_tool_subprocess_reaper" "1"
+  "compatmanager_layer_name" "fex"
+}

Source/Tools/CMakeLists.txt

@@ -1,6 +1,6 @@
 add_subdirectory(CommonTools)
 
-if (NOT MINGW_BUILD)
+if (NOT MINGW)
   if (BUILD_FEXCONFIG)
     find_package(Qt6 COMPONENTS Qml Quick Widgets QUIET)
     if (NOT Qt6_FOUND)

Source/Tools/CodeSizeValidation/CMakeLists.txt

@@ -1,14 +1,6 @@
 list(APPEND LIBS FEXCore Common CommonTools JemallocLibs)
 
-set (SRCS Main.cpp)
-add_executable(CodeSizeValidation ${SRCS})
-target_include_directories(CodeSizeValidation
-  PRIVATE
-    ${CMAKE_CURRENT_SOURCE_DIR}/Source/
-    ${CMAKE_BINARY_DIR}/generated
-)
-target_link_libraries(CodeSizeValidation
-  PRIVATE
-    ${LIBS}
-    ${PTHREAD_LIB}
-)
+add_executable(CodeSizeValidation Main.cpp)
+target_include_directories(CodeSizeValidation PRIVATE ${CMAKE_BINARY_DIR}/generated)
+
+target_link_libraries(CodeSizeValidation PRIVATE ${LIBS} ${PTHREAD_LIB})

Source/Tools/CodeSizeValidation/Main.cpp

@@ -449,7 +449,7 @@ public:
 
   // These are no-ops implementations of the SyscallHandler API
   std::optional<FEXCore::ExecutableFileSectionInfo>
-  LookupExecutableFileSection(FEXCore::Core::InternalThreadState& Thread, uint64_t GuestAddr) override {
+  LookupExecutableFileSection(FEXCore::Core::InternalThreadState* Thread, uint64_t GuestAddr) override {
     return std::nullopt;
   }
 

Source/Tools/CommonTools/CMakeLists.txt

@@ -1,14 +1,9 @@
-set(NAME CommonTools)
-set(SRCS
-  DummyHandlers.cpp
-  )
+set(SRCS DummyHandlers.cpp)
 
-if (NOT MINGW_BUILD)
-  list(APPEND SRCS
-  Linux/Utils/ELFContainer.cpp
-  )
+if (NOT MINGW)
+  list(APPEND SRCS Linux/Utils/ELFContainer.cpp)
 endif()
 
-add_library(${NAME} STATIC ${SRCS})
-target_link_libraries(${NAME} FEXCore_Base FEXHeaderUtils)
-target_include_directories(${NAME} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
+add_library(CommonTools STATIC ${SRCS})
+target_link_libraries(CommonTools FEXCore_Base FEXHeaderUtils)
+target_include_directories(CommonTools PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})

Source/Tools/CommonTools/DummyHandlers.h

@@ -17,7 +17,7 @@ public:
   }
 
   // These are no-ops implementations of the SyscallHandler API
-  std::optional<FEXCore::ExecutableFileSectionInfo> LookupExecutableFileSection(FEXCore::Core::InternalThreadState&, uint64_t) override {
+  std::optional<FEXCore::ExecutableFileSectionInfo> LookupExecutableFileSection(FEXCore::Core::InternalThreadState*, uint64_t) override {
     return std::nullopt;
   }
 

Source/Tools/FEXBash/CMakeLists.txt

@@ -1,24 +1,9 @@
 add_executable(FEXBash FEXBash.cpp)
-target_include_directories(FEXBash PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/Source/)
 
-target_link_libraries(FEXBash
-  PRIVATE
-    FEXCore
-    Common
-    JemallocLibs
-)
+target_link_libraries(FEXBash PRIVATE FEXCore Common JemallocLibs)
 
-if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
-  target_link_options(FEXBash
-    PRIVATE
-      "LINKER:--gc-sections"
-      "LINKER:--strip-all"
-      "LINKER:--as-needed"
-  )
-endif()
+LinkerGC(FEXBash)
 
-install(TARGETS FEXBash
-  RUNTIME
-    DESTINATION bin
-    COMPONENT Runtime
-)
+install(TARGETS FEXBash RUNTIME
+  DESTINATION bin
+  COMPONENT Runtime)

Source/Tools/FEXConfig/CMakeLists.txt

@@ -2,7 +2,7 @@ set(CMAKE_AUTOMOC ON)
 
 add_executable(FEXConfig)
 target_sources(FEXConfig PRIVATE Main.cpp Main.h)
-target_include_directories(FEXConfig PRIVATE ${CMAKE_SOURCE_DIR}/Source/)
+
 target_link_libraries(FEXConfig PRIVATE Common JemallocDummy)
 if (Qt6_FOUND)
   qt_add_resources(QT_RESOURCES qml6.qrc)
@@ -13,16 +13,8 @@ else()
 endif()
 target_sources(FEXConfig PRIVATE ${QT_RESOURCES})
 
-if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
-  target_link_options(FEXConfig
-    PRIVATE
-      "LINKER:--gc-sections"
-      "LINKER:--strip-all"
-      "LINKER:--as-needed"
-  )
-endif()
+LinkerGC(FEXConfig)
 
-install(TARGETS FEXConfig
-  RUNTIME
+install(TARGETS FEXConfig RUNTIME
   DESTINATION bin
   COMPONENT Runtime)

Source/Tools/FEXConfig/main.qml

@@ -448,12 +448,12 @@ ApplicationWindow {
                             id: loggingComboBox
                             property string configValue: ConfigModel.has("OutputLog", refreshCache) ? ConfigModel.getString("OutputLog", refreshCache) : ""
 
-                            currentIndex: configValue === "" ? -1 : configValue == "server" ? 0 : configValue == "stderr" ? 1 : configValue == "stdout" ? 2 : 3
+                            currentIndex: configValue === "" ? -1 : configValue == "server" ? 0 : configValue == "stderr" ? 1 : 2
 
                             onActivated: {
                                 configDirty = true
-                                var configNames = [ "server", "stderr", "stdout" ]
-                                if (currentIndex != -1 && currentIndex < 3) {
+                                var configNames = [ "server", "stderr" ]
+                                if (currentIndex != -1 && currentIndex < 2) {
                                     ConfigModel.setString("OutputLog", configNames[currentIndex])
                                 } else {
                                     // Set by text field below
@@ -463,13 +463,12 @@ ApplicationWindow {
                             model: ListModel {
                                 ListElement { text: "FEXServer" }
                                 ListElement { text: "stderr" }
-                                ListElement { text: "stdout" }
                                 ListElement { text: qsTr("File...") }
                             }
                         }
 
                         ConfigTextFieldForPath {
-                            visible: loggingComboBox.currentIndex === 3
+                            visible: loggingComboBox.currentIndex === 2
                             config: "OutputLog"
                         }
                     }

Source/Tools/FEXGDBReader/CMakeLists.txt

@@ -1,15 +1,10 @@
-set(NAME FEXGDBReader)
-set(SRCS FEXGDBReader.cpp)
+add_library(FEXGDBReader SHARED FEXGDBReader.cpp)
 
-add_library(${NAME} SHARED ${SRCS})
-
-install(TARGETS ${NAME}
-  RUNTIME
+install(TARGETS FEXGDBReader RUNTIME
   LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}/gdb
   COMPONENT Development)
 
-target_include_directories(${NAME} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/Source/)
-target_include_directories(${NAME} PRIVATE ${CMAKE_BINARY_DIR}/generated)
+target_include_directories(FEXGDBReader PRIVATE ${CMAKE_BINARY_DIR}/generated)
 
 # We don't actually link, but this is a nice way to get the include dirs
-target_link_libraries(${NAME} PRIVATE Common)
+target_link_libraries(FEXGDBReader PRIVATE Common)

Source/Tools/FEXGetConfig/CMakeLists.txt

@@ -1,25 +1,13 @@
-set(NAME FEXGetConfig)
-set(SRCS Main.cpp)
-
-add_executable(${NAME} ${SRCS})
+add_executable(FEXGetConfig Main.cpp)
 
 list(APPEND LIBS Common JemallocDummy)
 
-if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
-  target_link_options(${NAME}
-    PRIVATE
-      "LINKER:--gc-sections"
-      "LINKER:--strip-all"
-      "LINKER:--as-needed"
-  )
-endif()
+LinkerGC(FEXGetConfig)
 
-install(TARGETS ${NAME}
-  RUNTIME
+install(TARGETS FEXGetConfig RUNTIME
   DESTINATION bin
   COMPONENT Runtime)
 
-target_link_libraries(${NAME} PRIVATE ${LIBS})
+target_link_libraries(FEXGetConfig PRIVATE ${LIBS})
 
-target_include_directories(${NAME} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/Source/)
-target_include_directories(${NAME} PRIVATE ${CMAKE_BINARY_DIR}/generated)
+target_include_directories(FEXGetConfig PRIVATE ${CMAKE_BINARY_DIR}/generated)

Source/Tools/FEXGetConfig/Main.cpp

@@ -22,7 +22,7 @@ struct TSOEmulationFacts {
   bool LRCPC1 {}, LRCPC2 {}, LRCPC3 {};
 };
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
 bool CheckForHardwareTSO() {
   // Check to see if this is supported.
   auto Result = prctl(PR_GET_MEM_MODEL, 0, 0, 0, 0);
@@ -113,7 +113,7 @@ int main(int argc, char** argv, char** envp) {
 
   Parser.add_option("--tso-emulation-info").action("store_true").help("Print how FEX is emulating the x86-TSO memory model.");
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
   Parser.add_option("--identification-reg-info").action("store_true").help("Print identification registers");
 #endif
 
@@ -235,7 +235,7 @@ int main(int argc, char** argv, char** envp) {
     fprintf(stdout, "\t64-Byte strict split-lock emulation:  %s\n", StrictInProcessSplitLocks() ? "In-process mutex" : "Tearing");
   }
 
-#ifdef _M_ARM_64
+#ifdef ARCHITECTURE_arm64
   if (Options.is_set_by_user("identification_reg_info")) {
     auto Features = FEX::GetCPUFeaturesFromIDRegisters();
     fextl::string features {};

Source/Tools/FEXInterpreter/CMakeLists.txt

@@ -1,6 +1,7 @@
-list(APPEND LIBS FEXCore Common JemallocLibs)
+list(APPEND LIBS FEXCore Common JemallocLibs LinuxEmulation
+  CommonTools ${PTHREAD_LIB} fmt::fmt)
 
-set (DEFINES)
+set(DEFINES)
 if (ENABLE_VIXL_SIMULATOR)
   list(APPEND DEFINES -DVIXL_SIMULATOR=1)
 endif()
@@ -16,38 +17,19 @@ set_target_properties(FEX PROPERTIES
   ENABLE_EXPORTS 1
   C_VISIBILITY_PRESET hidden
   CXX_VISIBILITY_PRESET hidden
-  VISIBILITY_INLINES_HIDDEN TRUE
-)
+  VISIBILITY_INLINES_HIDDEN TRUE)
+
+target_include_directories(FEX PRIVATE ${CMAKE_BINARY_DIR}/generated)
+
+target_link_libraries(FEX PRIVATE ${LIBS})
 
-target_include_directories(FEX
-  PRIVATE
-    ${CMAKE_CURRENT_SOURCE_DIR}/
-    ${CMAKE_BINARY_DIR}/generated
-)
-target_link_libraries(FEX
-  PRIVATE
-    ${LIBS}
-    LinuxEmulation
-    CommonTools
-    ${PTHREAD_LIB}
-    fmt::fmt
-)
 target_compile_options(FEX PRIVATE ${FEX_TUNE_COMPILE_FLAGS})
 
-if (CMAKE_BUILD_TYPE MATCHES "RELEASE")
-  target_link_options(FEX
-    PRIVATE
-      "LINKER:--gc-sections"
-      "LINKER:--strip-all"
-      "LINKER:--as-needed"
-  )
-endif()
+LinkerGC(FEX)
 
-install(TARGETS FEX
-  RUNTIME
+install(TARGETS FEX RUNTIME
     DESTINATION bin
-    COMPONENT Runtime
-)
+    COMPONENT Runtime)
 
 # Create a copy of FEX with legacy names until phased out.
 install(PROGRAMS ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/FEX
@@ -55,19 +37,18 @@ install(PROGRAMS ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/FEX
   DESTINATION bin
   COMPONENT LegacyRuntime)
 
-if (_M_ARM_64)
+if (ARCHITECTURE_arm64)
   if (NOT USE_LEGACY_BINFMTMISC)
     # Just restart the systemd service
     add_custom_target(binfmt_misc
       echo "Restarting systemd service now."
-      COMMAND "service" "systemd-binfmt" "restart"
-    )
+      COMMAND "service" "systemd-binfmt" "restart")
   else()
     # Check for conflicting binfmt before installing
-    set (CONFLICTING_BINFMTS_32
+    set(CONFLICTING_BINFMTS_32
       ${CMAKE_INSTALL_PREFIX}/share/binfmts/qemu-i386
       ${CMAKE_INSTALL_PREFIX}/share/binfmts/box86)
-    set (CONFLICTING_BINFMTS_64
+    set(CONFLICTING_BINFMTS_64
       ${CMAKE_INSTALL_PREFIX}/share/binfmts/qemu-x86_64
       ${CMAKE_INSTALL_PREFIX}/share/binfmts/box64)
 
@@ -80,14 +61,12 @@ if (_M_ARM_64)
         COMMAND "update-binfmts" "--importdir=${CMAKE_INSTALL_PREFIX}/share/binfmts/" "--import" "FEX-x86"
         COMMAND "update-binfmts" "--importdir=${CMAKE_INSTALL_PREFIX}/share/binfmts/" "--import" "FEX-x86_64"
         COMMAND ${CMAKE_COMMAND} -E
-        echo "FEX binfmt_misc installed"
-      )
+        echo "FEX binfmt_misc installed")
 
       if(TARGET uninstall)
         add_custom_target(uninstall_binfmt_misc
           COMMAND update-binfmts --unimport FEX-x86 || (exit 0)
-          COMMAND update-binfmts --unimport FEX-x86_64 || (exit 0)
-        )
+          COMMAND update-binfmts --unimport FEX-x86_64 || (exit 0))
 
         add_dependencies(uninstall uninstall_binfmt_misc)
       endif()
@@ -109,16 +88,14 @@ if (_M_ARM_64)
           echo
           ':FEX-x86_64:M:0:\\x7fELF\\x02\\x01\\x01\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x02\\x00\\x3e\\x00:\\xff\\xff\\xff\\xff\\xff\\xfe\\xfe\\x00\\x00\\x00\\x00\\xff\\xff\\xff\\xff\\xff\\xfe\\xff\\xff\\xff:${CMAKE_INSTALL_PREFIX}/bin/FEX:POCF' > /proc/sys/fs/binfmt_misc/register
         COMMAND ${CMAKE_COMMAND} -E
-          echo "binfmt_misc FEX installed"
-        )
+          echo "binfmt_misc FEX installed")
 
       if(TARGET uninstall)
         add_custom_target(uninstall_binfmt_misc
           COMMAND ${CMAKE_COMMAND} -E
             echo -1 > /proc/sys/fs/binfmt_misc/FEX-x86 || (exit 0)
           COMMAND ${CMAKE_COMMAND} -E
-            echo -1 > /proc/sys/fs/binfmt_misc/FEX-x86_64 || (exit 0)
-        )
+            echo -1 > /proc/sys/fs/binfmt_misc/FEX-x86_64 || (exit 0))
 
         add_dependencies(uninstall uninstall_binfmt_misc)
       endif()