Docs: Update for release FEX-2308

ARMEmitter: Add missing atomic aliases

.github/workflows/ccpp.yml

@@ -14,6 +14,7 @@ env:
   CC: clang
   CXX: clang++
   FEX_FORCE32BITALLOCATOR: 1
+  FEX_ENABLEAVX: 1
 
 jobs:
   build:
@@ -24,7 +25,7 @@ jobs:
       fail-fast: false
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Set runner label
       run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
@@ -171,6 +172,17 @@ jobs:
       working-directory: ${{runner.workspace}}/build
       run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_APITests.log || true
 
+    - name: FEXCore APITest tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target fexcore_apitests
+
+    - name: FEXCore APITest Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_FEXCoreAPITests.log || true
+
     - name: ARMEmitter tests
       working-directory: ${{runner.workspace}}/build
       shell: bash
@@ -240,13 +252,20 @@ jobs:
       # ASM tests get quite close to 10MB
       run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
 
+    - name: Remove old SHM regions
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: cmake --build . --config $BUILD_TYPE --target remove_old_shm_regions
+
     - name: Set runner name
       if: ${{ always() }}
       run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
 
     - name: Upload results
       if: ${{ always() }}
-      uses: 'actions/upload-artifact@v2'
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
       with:
         name: Results-${{ env.runner_name }}
         path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log

.github/workflows/glibc_fault.yml

@@ -0,0 +1,208 @@
+name: GLIBC fault test
+# This workflow file is the same as the `Build + Test` with some key differences
+# - Runs on any x86 and ARM64 runner
+# - Disables the glibc jemalloc compile option
+# - Enables the glibc allocator fault option
+# - Disables gvisor tests to reduce stress on CI machines (tmp/shm tests overwhelm them)
+# - Disables thunk tests since they are incompatible with glibc fault allocator
+# - Disables ARMEmitter tests (We don't want to fault test vixl's disassembler)
+
+on:
+  push:
+    branches:
+      - main
+  pull_request:
+    branches:
+      - main
+
+env:
+  # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)
+  BUILD_TYPE: Release
+  CC: clang
+  CXX: clang++
+  FEX_FORCE32BITALLOCATOR: 1
+  FEX_ENABLEAVX: 1
+
+jobs:
+  build:
+    runs-on: ${{ matrix.arch }}
+    strategy:
+      matrix:
+        # Run on an x86 device and any ARM runner.
+        arch: [[self-hosted, x64], [self-hosted, ARM64]]
+      fail-fast: false
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
+    - name: Set rootfs paths
+      run: |
+        echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+
+    - name: Update RootFS cache
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      run: $GITHUB_WORKSPACE/Scripts/CI_FetchRootFS.py
+
+    - name : submodule checkout
+      # Need to update submodules
+      run: |
+        git submodule sync --recursive
+        git submodule update --init --depth 1
+
+    - name: Clean Build Environment
+      run: rm -Rf ${{runner.workspace}}/build
+
+    - name: Create Build Environment
+      # Some projects don't allow in-source building, so create a separate build directory
+      # We'll use this as our working directory for all subsequent commands
+      run: cmake -E make_directory ${{runner.workspace}}/build
+
+    - name: Configure CMake
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Note the current convention is to use the -S and -B options here to specify source
+      # and build directories, but this is only available with CMake 3.13 and higher.
+      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=True -DBUILD_FEX_LINUX_TESTS=True -DENABLE_GLIBC_ALLOCATOR_HOOK_FAULT=True -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+
+    - name: Build
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the build.  You can specify a specific target with "--target <NAME>"
+      run: cmake --build . --config $BUILD_TYPE
+
+    - name: Install
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target install
+
+    - name: ASM Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target asm_tests
+
+    - name: ASM Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM.log || true
+
+    - name: IR Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the unit tests
+      run: cmake --build . --config $BUILD_TYPE --target ir_tests
+
+    - name: IR Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
+
+    - name: Posix Tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the posixtest
+      run: cmake --build . --config $BUILD_TYPE --target posix_tests
+
+    - name: Posix Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_Posix.log || true
+
+    - name: gcc target tests 64
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the gvisor tests
+      run: cmake --build . --config $BUILD_TYPE --target gcc_target_tests_64
+
+    - name: GCC64 Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC64.log || true
+
+    - name: gcc target tests 32
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the gvisor tests
+      run: cmake --build . --config $BUILD_TYPE --target gcc_target_tests_32
+
+    - name: GCC32 Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_GCC32.log || true
+
+    - name: APITest tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target api_tests
+
+    - name: APITest Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_APITests.log || true
+
+    - name: FEXCore APITest tests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target fexcore_apitests
+
+    - name: FEXCore APITest Test Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_FEXCoreAPITests.log || true
+
+    - name: FEXLinuxTests
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      run: cmake --build . --config $BUILD_TYPE --target fex_linux_tests_all
+
+    - name: FEXLinuxTests Results move
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_FEXLinuxTests.log || true
+
+    - name: Truncate test results
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Cap out the log files at 20M in case something crash spins and dumps fault text
+      # ASM tests get quite close to 10MB
+      run: truncate --size=<20M ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log || true
+
+    - name: Remove old SHM regions
+      if: ${{ always() }}
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      run: cmake --build . --config $BUILD_TYPE --target remove_old_shm_regions
+
+    - name: Set runner name
+      if: ${{ always() }}
+      run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
+
+    - name: Upload results
+      if: ${{ always() }}
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
+      with:
+        name: Results-${{ env.runner_name }}
+        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
+        retention-days: 3
+

.github/workflows/mingw_build.yml

@@ -0,0 +1,96 @@
+name: Mingw build
+
+on:
+  push:
+    branches:
+      - main
+  pull_request:
+    branches:
+      - main
+
+env:
+  BUILD_TYPE: Debug
+  FEX_ENABLEAVX: 1
+
+jobs:
+  build:
+    runs-on: ${{ matrix.arch }}
+    strategy:
+      matrix:
+        arch: [[self-hosted, x64, mingw], [self-hosted, ARM64, mingw]]
+      fail-fast: false
+
+    steps:
+    - uses: actions/checkout@v3
+
+    - name: Set runner label
+      run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
+
+    - name: Set CC x86
+      if: matrix.arch[1] == 'x64'
+      run: |
+        echo "CC=$HOME/llvm-mingw/build/bin/x86_64-w64-mingw32-clang" >> $GITHUB_ENV
+        echo "CXX=$HOME/llvm-mingw/build/bin/x86_64-w64-mingw32-clang++" >> $GITHUB_ENV
+
+    - name: Set CC Arm64
+      if: matrix.arch[1] == 'ARM64'
+      run: |
+        echo "CC=$HOME/llvm-mingw/build/bin/aarch64-w64-mingw32-clang" >> $GITHUB_ENV
+        echo "CXX=$HOME/llvm-mingw/build/bin/aarch64-w64-mingw32-clang++" >> $GITHUB_ENV
+
+    - name: Set rootfs paths
+      run: |
+        echo "FEX_ROOTFS_MOUNT=/mnt/AutoNFS/rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS_PATH=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "FEX_ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+        echo "ROOTFS=$HOME/Rootfs/" >> $GITHUB_ENV
+
+    - name: Update RootFS cache
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      run: $GITHUB_WORKSPACE/Scripts/CI_FetchRootFS.py
+
+    - name : submodule checkout
+      # Need to update submodules
+      run: |
+        git submodule sync --recursive
+        git submodule update --init --depth 1
+
+    - name: Clean Build Environment
+      run: rm -Rf ${{runner.workspace}}/build
+
+    - name: Create Build Environment
+      # Some projects don't allow in-source building, so create a separate build directory
+      # We'll use this as our working directory for all subsequent commands
+      run: cmake -E make_directory ${{runner.workspace}}/build
+
+    - name: Configure CMake
+      # Use a bash shell so we can use the same syntax for environment variable
+      # access regardless of the host operating system
+      shell: bash
+      working-directory: ${{runner.workspace}}/build
+      # Note the current convention is to use the -S and -B options here to specify source
+      # and build directories, but this is only available with CMake 3.13 and higher.
+      # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
+      run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -G Ninja -DENABLE_LTO=False -DENABLE_ASSERTIONS=True -DENABLE_X86_HOST_DEBUG=True -DENABLE_INTERPRETER=False -DBUILD_TESTS=False -DENABLE_JEMALLOC=False -DENABLE_JEMALLOC_GLIBC_ALLOC=False -DCMAKE_INSTALL_PREFIX=${{runner.workspace}}/build/install
+
+    - name: Build
+      working-directory: ${{runner.workspace}}/build
+      shell: bash
+      # Execute the build.  You can specify a specific target with "--target <NAME>"
+      run: cmake --build . --config $BUILD_TYPE
+
+    - name: Set runner name
+      if: ${{ always() }}
+      run: echo "runner_name=$(hostname)" >> $GITHUB_ENV
+
+    - name: Upload results
+      if: ${{ always() }}
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
+      with:
+        name: Results-${{ env.runner_name }}
+        path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log
+        retention-days: 3
+

.github/workflows/vixl_simulator.yml

@@ -13,6 +13,7 @@ env:
   BUILD_TYPE: Release
   CC: clang
   CXX: clang++
+  FEX_ENABLEAVX: 1
 
 jobs:
   build:
@@ -24,7 +25,7 @@ jobs:
       fail-fast: false
 
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
 
     - name: Set runner label
       run: echo "runner_label=${{ matrix.arch[1] }}" >> $GITHUB_ENV
@@ -110,7 +111,8 @@ jobs:
 
     - name: Upload results
       if: ${{ always() }}
-      uses: 'actions/upload-artifact@v2'
+      uses: 'actions/upload-artifact@v3'
+      timeout-minutes: 1
       with:
         name: Results-${{ env.runner_name }}
         path: ${{runner.workspace}}/build/Testing/Temporary/LastTest_*.log

.gitmodules

@@ -3,7 +3,7 @@
 	path = External/vixl
 	url = https://github.com/FEX-Emu/vixl.git
 [submodule "External/cpp-optparse"]
-	path = External/cpp-optparse
+	path = Source/Common/cpp-optparse
 	url = https://github.com/Sonicadvance1/cpp-optparse
 [submodule "External/imgui"]
 	path = External/imgui
@@ -48,8 +48,11 @@
 [submodule "External/robin-map"]
 	shallow = true
 	path = External/robin-map
-	url = https://github.com/Tessil/robin-map.git
+	url = https://github.com/FEX-Emu/robin-map.git
 [submodule "External/Vulkan-Headers"]
 	shallow = true
 	path = External/Vulkan-Headers
 	url = https://github.com/KhronosGroup/Vulkan-Headers.git
+[submodule "External/jemalloc_glibc"]
+	path = External/jemalloc_glibc
+	url = https://github.com/FEX-Emu/jemalloc.git

CMakeFiles/version_to_variables.cmake

@@ -0,0 +1,30 @@
+# Extracts a version from the passed in version string in the form of "<Major>.<Minor>.<Patch>".
+# If a part of the version is missing then it gets set as zero.
+# Version variables returned in:
+# ${Package}_VERSION_MAJOR
+# ${Package}_VERSION_MINOR
+# ${Package}_VERSION_PATCH
+function(version_to_variables VERSION _Package)
+  string(REPLACE "." ";" VERSION_LIST "${VERSION}")
+  list (LENGTH VERSION_LIST VERSION_LEN)
+  if (${VERSION_LEN} GREATER 0)
+    list(GET VERSION_LIST 0 VERSION_MAJOR)
+    set(${_Package}_VERSION_MAJOR ${VERSION_MAJOR} PARENT_SCOPE)
+  else()
+    set(${_Package}_VERSION_MAJOR 0 PARENT_SCOPE)
+  endif()
+
+  if (${VERSION_LEN} GREATER 1)
+    list(GET VERSION_LIST 1 VERSION_MINOR)
+    set(${_Package}_VERSION_MINOR ${VERSION_MINOR} PARENT_SCOPE)
+  else()
+    set(${_Package}_VERSION_MINOR 0 PARENT_SCOPE)
+  endif()
+
+  if (${VERSION_LEN} GREATER 2)
+    list(GET VERSION_LIST 2 VERSION_PATCH)
+    set(${_Package}_VERSION_PATCH ${VERSION_PATCH} PARENT_SCOPE)
+  else()
+    set(${_Package}_VERSION_PATCH 0 PARENT_SCOPE)
+  endif()
+endfunction()

CMakeLists.txt

@@ -7,21 +7,21 @@ CHECK_INCLUDE_FILES ("gdb/jit-reader.h" HAVE_GDB_JIT_READER_H)
 option(BUILD_TESTS "Build unit tests to ensure sanity" TRUE)
 option(BUILD_FEX_LINUX_TESTS "Build FEXLinuxTests, requires x86 compiler" FALSE)
 option(BUILD_THUNKS "Build thunks" FALSE)
+option(BUILD_FEXCONFIG "Build FEXConfig, requires SDL2 and X11" TRUE)
 option(ENABLE_CLANG_THUNKS "Build thunks with clang" FALSE)
 option(ENABLE_CLANG_FORMAT "Run clang format over the source" FALSE)
 option(ENABLE_IWYU "Enables include what you use program" FALSE)
 option(ENABLE_LTO "Enable LTO with compilation" TRUE)
 option(ENABLE_XRAY "Enable building with LLVM X-Ray" FALSE)
-option(ENABLE_LLD "Enable linking with lld" FALSE)
-option(ENABLE_MOLD "Enable linking with mold" FALSE)
+set(USE_LINKER "" CACHE STRING "Allow overriding the linker path directly")
 option(ENABLE_ASAN "Enables Clang ASAN" FALSE)
 option(ENABLE_TSAN "Enables Clang TSAN" FALSE)
 option(ENABLE_ASSERTIONS "Enables assertions in build" FALSE)
 option(ENABLE_GDB_SYMBOLS "Enables GDBSymbols integration support" ${HAVE_GDB_JIT_READER_H})
-option(ENABLE_VISUAL_DEBUGGER "Enables the visual debugger for compiling" FALSE)
 option(ENABLE_STRICT_WERROR "Enables stricter -Werror for CI" FALSE)
 option(ENABLE_WERROR "Enables -Werror" FALSE)
 option(ENABLE_JEMALLOC "Enables jemalloc allocator" TRUE)
+option(ENABLE_JEMALLOC_GLIBC_ALLOC "Enables jemalloc glibc allocator" TRUE)
 option(ENABLE_OFFLINE_TELEMETRY "Enables FEX offline telemetry" TRUE)
 option(ENABLE_COMPILE_TIME_TRACE "Enables time trace compile option" FALSE)
 option(ENABLE_LIBCXX "Enables LLVM libc++" FALSE)
@@ -33,11 +33,19 @@ option(ENABLE_VIXL_DISASSEMBLER "Enables debug disassembler output with VIXL" FA
 option(COMPILE_VIXL_DISASSEMBLER "Compiles the vixl disassembler in to vixl" FALSE)
 option(ENABLE_FEXCORE_PROFILER "Enables use of the FEXCore timeline profiling capabilities" FALSE)
 set (FEXCORE_PROFILER_BACKEND "gpuvis" CACHE STRING "Set which backend you want to use for the FEXCore profiler")
+option(ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT "Enables glibc memory allocation hooking with fault for CI testing")
 
 set (X86_32_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/toolchain_x86_32.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting i686")
 set (X86_64_TOOLCHAIN_FILE "${CMAKE_CURRENT_SOURCE_DIR}/toolchain_x86_64.cmake" CACHE FILEPATH "Toolchain file for the (cross-)compiler targeting x86_64")
 set (DATA_DIRECTORY "${CMAKE_INSTALL_PREFIX}/share/fex-emu" CACHE PATH "global data directory")
 
+string(FIND ${CMAKE_BASE_NAME} mingw CONTAINS_MINGW)
+if (NOT CONTAINS_MINGW EQUAL -1)
+  message (STATUS "Mingw build")
+  set (MINGW_BUILD TRUE)
+  set (ENABLE_JEMALLOC FALSE)
+endif()
+
 if (ENABLE_FEXCORE_PROFILER)
   add_definitions(-DENABLE_FEXCORE_PROFILER=1)
   string(TOUPPER "${FEXCORE_PROFILER_BACKEND}" FEXCORE_PROFILER_BACKEND)
@@ -49,6 +57,14 @@ if (ENABLE_FEXCORE_PROFILER)
   endif()
 endif()
 
+if (ENABLE_JEMALLOC_GLIBC_ALLOC AND ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
+  message(FATAL_ERROR "Can't have both glibc fault allocator and jemalloc glibc allocator enabled at the same time")
+endif()
+
+if (ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
+  add_definitions(-DGLIBC_ALLOCATOR_FAULT=1)
+endif()
+
 # uninstall target
 if(NOT TARGET uninstall)
   configure_file(
@@ -140,13 +156,9 @@ endif()
 
 set (PTHREAD_LIB pthread)
 
-if (ENABLE_LLD AND ENABLE_MOLD)
-  message (FATAL_ERROR "Cannot enable both lld and mold")
-elseif (ENABLE_LLD)
-  set (LD_OVERRIDE "-fuse-ld=lld")
-  add_link_options(${LD_OVERRIDE})
-elseif (ENABLE_MOLD)
-  add_link_options("-fuse-ld=mold")
+if (USE_LINKER)
+  message(STATUS "Overriding linker to: ${USE_LINKER}")
+  add_link_options("-fuse-ld=${USE_LINKER}")
 endif()
 
 if (ENABLE_LIBCXX)
@@ -163,8 +175,13 @@ endif()
 if(DEFINED ENV{TERMUX_VERSION} OR ENABLE_TERMUX_BUILD)
   add_definitions(-DTERMUX_BUILD=1)
   set(TERMUX_BUILD 1)
+
   # Termux doesn't support Jemalloc due to bad interactions between emutls, jemalloc, and scudo
   set(ENABLE_JEMALLOC FALSE)
+
+  # Termux builds can't rely on X11 packages
+  # SDL2 isn't even compiled with GL support so our GUIs wouldn't even work
+  set(BUILD_FEXCONFIG FALSE)
 endif()
 
 if (ENABLE_ASAN)
@@ -178,7 +195,22 @@ if (ENABLE_TSAN)
   link_libraries(-fno-omit-frame-pointer -fsanitize=thread)
 endif()
 
+if (ENABLE_JEMALLOC_GLIBC_ALLOC)
+  # The glibc jemalloc subproject which hooks the glibc allocator.
+  # Required for thunks to work.
+  # All host native libraries will use this allocator, while *most* other FEX internal allocations will use the other jemalloc allocator.
+  add_definitions(-DENABLE_JEMALLOC_GLIBC=1)
+  add_subdirectory(External/jemalloc_glibc/)
+else()
+  message (STATUS
+    " jemalloc glibc allocator disabled!\n"
+    " This is not a recommended configuration!\n"
+    " This will very explicitly break thunk execution!\n"
+    " Use at your own risk!")
+endif()
+
 if (ENABLE_JEMALLOC)
+  # The jemalloc subproject that all FEXCore fextl objects allocate through.
   add_definitions(-DENABLE_JEMALLOC=1)
   add_subdirectory(External/jemalloc/)
   include_directories(External/jemalloc/pregen/include/)
@@ -230,9 +262,8 @@ if (BUILD_TESTS)
   include(Catch)
 endif()
 
-add_subdirectory(External/cpp-optparse/)
-include_directories(External/cpp-optparse/)
-
+# Disable fmt install
+set(FMT_INSTALL OFF)
 add_subdirectory(External/fmt/)
 
 add_subdirectory(External/imgui/)

Data/ThunksDB.json

@@ -6,10 +6,10 @@
         "X11"
       ],
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGL.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGL.so.1",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGL.so.1.2.0",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGL.so.1.7.0"
+        "@PREFIX_LIB@/libGL.so",
+        "@PREFIX_LIB@/libGL.so.1",
+        "@PREFIX_LIB@/libGL.so.1.2.0",
+        "@PREFIX_LIB@/libGL.so.1.7.0"
       ]
     },
     "GLESv2": {
@@ -18,17 +18,17 @@
         "X11"
       ],
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGLESv2.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGLESv2.so.2",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libGLESv2.so.2.0.0"
+        "@PREFIX_LIB@/libGLESv2.so",
+        "@PREFIX_LIB@/libGLESv2.so.2",
+        "@PREFIX_LIB@/libGLESv2.so.2.0.0"
       ]
     },
     "X11": {
       "Library": "libX11-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libX11.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libX11.so.6",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libX11.so.6.4.0"
+        "@PREFIX_LIB@/libX11.so",
+        "@PREFIX_LIB@/libX11.so.6",
+        "@PREFIX_LIB@/libX11.so.6.4.0"
       ]
     },
     "Vulkan": {
@@ -37,8 +37,8 @@
         "xcb"
       ],
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libvulkan.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libvulkan.so.1",
+        "@PREFIX_LIB@/libvulkan.so",
+        "@PREFIX_LIB@/libvulkan.so.1",
         "@HOME@/.local/share/Steam/ubuntu12_32/steam-runtime/pinned_libs_64/libvulkan.so.1"
       ],
       "Comment": [
@@ -46,131 +46,142 @@
       ]
     },
     "xcb": {
+      "Depends": [
+        "X11"
+      ],
       "Library": "libxcb-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb.so.1",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb.so.1.1.0"
+        "@PREFIX_LIB@/libxcb.so",
+        "@PREFIX_LIB@/libxcb.so.1",
+        "@PREFIX_LIB@/libxcb.so.1.1.0"
       ]
     },
     "xcb-dri2": {
       "Library": "libxcb-dri2-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri2.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri2.so.0",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri2.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-dri2.so",
+        "@PREFIX_LIB@/libxcb-dri2.so.0",
+        "@PREFIX_LIB@/libxcb-dri2.so.0.0.0"
       ]
     },
     "xcb-dri3": {
       "Library": "libxcb-dri3-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri3.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri3.so.0",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-dri3.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-dri3.so",
+        "@PREFIX_LIB@/libxcb-dri3.so.0",
+        "@PREFIX_LIB@/libxcb-dri3.so.0.0.0"
       ]
     },
     "xcb-xfixes": {
       "Library": "libxcb-xfixes-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-xfixes.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-xfixes.so.0",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-xfixes.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-xfixes.so",
+        "@PREFIX_LIB@/libxcb-xfixes.so.0",
+        "@PREFIX_LIB@/libxcb-xfixes.so.0.0.0"
       ]
     },
     "xcb-shm": {
       "Library": "libxcb-shm-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-shm.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-shm.so.0",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-shm.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-shm.so",
+        "@PREFIX_LIB@/libxcb-shm.so.0",
+        "@PREFIX_LIB@/libxcb-shm.so.0.0.0"
       ]
     },
     "xcb-sync": {
       "Library": "libxcb-sync-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-sync.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-sync.so.1",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-sync.so.1.0.0"
+        "@PREFIX_LIB@/libxcb-sync.so",
+        "@PREFIX_LIB@/libxcb-sync.so.1",
+        "@PREFIX_LIB@/libxcb-sync.so.1.0.0"
       ]
     },
     "xcb-randr": {
       "Library": "libxcb-randr-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-randr.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-randr.so.0",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-randr.so.0.1.0"
+        "@PREFIX_LIB@/libxcb-randr.so",
+        "@PREFIX_LIB@/libxcb-randr.so.0",
+        "@PREFIX_LIB@/libxcb-randr.so.0.1.0"
       ]
     },
     "xcb-present": {
       "Library": "libxcb-present-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-present.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-present.so.0",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-present.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-present.so",
+        "@PREFIX_LIB@/libxcb-present.so.0",
+        "@PREFIX_LIB@/libxcb-present.so.0.0.0"
       ]
     },
     "xcb-glx": {
       "Library": "libxcb-glx-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-glx.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-glx.so.0",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxcb-glx.so.0.0.0"
+        "@PREFIX_LIB@/libxcb-glx.so",
+        "@PREFIX_LIB@/libxcb-glx.so.0",
+        "@PREFIX_LIB@/libxcb-glx.so.0.0.0"
       ]
     },
     "xshmfence": {
       "Library": "libxshmfence-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxshmfence.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxshmfence.so.1",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libxshmfence.so.1.0.0"
+        "@PREFIX_LIB@/libxshmfence.so",
+        "@PREFIX_LIB@/libxshmfence.so.1",
+        "@PREFIX_LIB@/libxshmfence.so.1.0.0"
       ]
     },
     "drm": {
       "Library": "libdrm-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libdrm.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libdrm.so.2",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libdrm.so.2.4.0"
+        "@PREFIX_LIB@/libdrm.so",
+        "@PREFIX_LIB@/libdrm.so.2",
+        "@PREFIX_LIB@/libdrm.so.2.4.0"
       ]
     },
     "asound": {
       "Library": "libasound-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libasound.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libasound.so.2",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libasound.so.2.0.0"
+        "@PREFIX_LIB@/libasound.so",
+        "@PREFIX_LIB@/libasound.so.2",
+        "@PREFIX_LIB@/libasound.so.2.0.0"
       ]
     },
     "Xrender": {
       "Library": "libXrender-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXrender.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXrender.so.1",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXrender.so.1.3.0"
+        "@PREFIX_LIB@/libXrender.so",
+        "@PREFIX_LIB@/libXrender.so.1",
+        "@PREFIX_LIB@/libXrender.so.1.3.0"
       ]
     },
     "Xext": {
       "Library": "libXext-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXext.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXext.so.6",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXext.so.6.4.0"
+        "@PREFIX_LIB@/libXext.so",
+        "@PREFIX_LIB@/libXext.so.6",
+        "@PREFIX_LIB@/libXext.so.6.4.0"
       ]
     },
     "Xfixes": {
       "Library": "libXfixes-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXfixes.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXfixes.so.3",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libXfixes.so.3.1.0"
+        "@PREFIX_LIB@/libXfixes.so",
+        "@PREFIX_LIB@/libXfixes.so.3",
+        "@PREFIX_LIB@/libXfixes.so.3.1.0"
       ]
     },
     "OpenCL": {
       "Library" : "libOpenCL-guest.so",
       "Overlay": [
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libOpenCL.so",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libOpenCL.so.1",
-        "@PREFIX_LIB@/@PREFIX_ARCH@-linux-gnu/libOpenCL.so.1.0.0"
+        "@PREFIX_LIB@/libOpenCL.so",
+        "@PREFIX_LIB@/libOpenCL.so.1",
+        "@PREFIX_LIB@/libOpenCL.so.1.0.0"
+      ]
+    },
+    "WaylandClient": {
+      "Library" : "libwayland-client-guest.so",
+      "Overlay": [
+        "@PREFIX_LIB@/libwayland-client.so",
+        "@PREFIX_LIB@/libwayland-client.so.0",
+        "@PREFIX_LIB@/libwayland-client.so.0.20.0"
       ]
     },
     "":{}

External/FEXCore/CMakeLists.txt

@@ -77,6 +77,7 @@ configure_file(
 
 include_directories(${CMAKE_BINARY_DIR}/generated)
 
+add_compile_options(-fno-exceptions)
 add_subdirectory(Source/)
 
 install (DIRECTORY include/FEXCore ${CMAKE_BINARY_DIR}/include/FEXCore

External/FEXCore/Scripts/config_generator.py

@@ -22,12 +22,14 @@ def print_header():
 #define OPT_UINT64(group, enum, json, default) OPT_BASE(uint64_t, group, enum, json, default)
 #endif
 #ifndef OPT_STR
-#define OPT_STR(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#define OPT_STR(group, enum, json, default) OPT_BASE(fextl::string, group, enum, json, default)
 #endif
 #ifndef OPT_STRARRAY
-#define OPT_STRARRAY(group, enum, json, default) OPT_BASE(std::string, group, enum, json, default)
+#define OPT_STRARRAY(group, enum, json, default) OPT_BASE(fextl::string, group, enum, json, default)
+#endif
+#ifndef OPT_STRENUM
+#define OPT_STRENUM(group, enum, json, default) OPT_BASE(uint64_t, group, enum, json, default)
 #endif
-
 '''
     output_file.write(header)
 
@@ -40,6 +42,7 @@ def print_tail():
 #undef OPT_UINT64
 #undef OPT_STR
 #undef OPT_STRARRAY
+#undef OPT_STRENUM
 '''
     output_file.write(tail)
 
@@ -127,12 +130,13 @@ def print_man_options(options):
                 short = op_vals["ShortArg"]
 
             default = op_vals["Default"]
+            value_type = op_vals["Type"]
 
             # Textual default rather than enum based
             if ("TextDefault" in op_vals):
                 default = op_vals["TextDefault"]
 
-            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+            if (value_type == "str" or value_type == "strarray" or value_type == "strenum"):
                 # Wrap the string argument in quotes
                 default = "'" + default + "'"
             print_man_option(
@@ -141,6 +145,12 @@ def print_man_options(options):
                 op_vals["Desc"],
                 default
             )
+            if (value_type == "strenum"):
+                Enums = op_vals["Enums"]
+                output_man.write("\\fBAvailable Options:\\fR\n")
+                for enum_op_key, enum_op_vals in Enums.items():
+                    output_man.write("{}, ".format(enum_op_vals))
+                output_man.write("\n")
 
     output_man.write(".El\n")
 
@@ -150,12 +160,13 @@ def print_man_environment(options):
     for op_group, group_vals in options.items():
         for op_key, op_vals in group_vals.items():
             default = op_vals["Default"]
+            value_type = op_vals["Type"]
 
             # Textual default rather than enum based
             if ("TextDefault" in op_vals):
                 default = op_vals["TextDefault"]
 
-            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+            if (value_type == "str" or value_type == "strarray" or value_type == "strenum"):
                 # Wrap the string argument in quotes
                 default = "'" + default + "'"
             print_man_env_option(
@@ -165,6 +176,13 @@ def print_man_environment(options):
                 False
             )
 
+            if (value_type == "strenum"):
+                Enums = op_vals["Enums"]
+                output_man.write("\\fBAvailable Options:\\fR\n")
+                for enum_op_key, enum_op_vals in Enums.items():
+                    output_man.write("{}, ".format(enum_op_vals))
+                output_man.write("\n")
+
     print_man_environment_tail()
     output_man.write(".El\n")
 
@@ -334,7 +352,7 @@ def print_argloader_options(options):
         for op_key, op_vals in group_vals.items():
             default = op_vals["Default"]
 
-            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray"):
+            if (op_vals["Type"] == "str" or op_vals["Type"] == "strarray" or op_vals["Type"] == "strenum"):
                 # Wrap the string argument in quotes
                 default = "\"" + default + "\""
 
@@ -371,15 +389,21 @@ def print_parse_argloader_options(options):
 
             value_type = op_vals["Type"]
             NeedsString = False
-            conversion_func = "std::to_string"
+            conversion_func = "fextl::fmt::format(\"{}\", "
             if ("ArgumentHandler" in op_vals):
                 NeedsString = True
-                conversion_func = "FEXCore::Config::Handler::{0}".format(op_vals["ArgumentHandler"])
+                conversion_func = "FEXCore::Config::Handler::{0}(".format(op_vals["ArgumentHandler"])
             if (value_type == "str"):
                 NeedsString = True
-                conversion_func = ""
+                conversion_func = "("
+            if (value_type == "bool"):
+                # boolean values need a decimal specifier. Otherwise fmt prints strings.
+                conversion_func = "fextl::fmt::format(\"{:d}\", "
 
-            if (value_type == "strarray"):
+            if (value_type == "strenum"):
+                output_argloader.write("\tfextl::string UserValue = Options[\"{0}\"];\n".format(op_key))
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{}, FEXCore::Config::EnumParser(FEXCore::Config::{}_EnumPairs, UserValue));\n".format(op_key.upper(), op_key, op_key))
+            elif (value_type == "strarray"):
                 # these need a bit more help
                 output_argloader.write("\tauto Array = Options.all(\"{0}\");\n".format(op_key))
                 output_argloader.write("\tfor (auto iter = Array.begin(); iter != Array.end(); ++iter) {\n")
@@ -387,11 +411,11 @@ def print_parse_argloader_options(options):
                 output_argloader.write("\t}\n")
             else:
                 if (NeedsString):
-                    output_argloader.write("\tstd::string UserValue = Options[\"{0}\"];\n".format(op_key))
+                    output_argloader.write("\tfextl::string UserValue = Options[\"{0}\"];\n".format(op_key))
                 else:
                     output_argloader.write("\t{0} UserValue = Options.get(\"{1}\");\n".format(value_type, op_key))
 
-                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, {1}(UserValue));\n".format(op_key.upper(), conversion_func))
+                output_argloader.write("\tSet(FEXCore::Config::ConfigOption::CONFIG_{0}, {1}UserValue));\n".format(op_key.upper(), conversion_func))
             output_argloader.write("}\n")
 
     output_argloader.write("#endif\n")
@@ -404,6 +428,12 @@ def print_parse_envloader_options(options):
 
     for op_group, group_vals in options.items():
         for op_key, op_vals in group_vals.items():
+            value_type = op_vals["Type"]
+            if (value_type == "strenum"):
+                output_argloader.write("else if (Key == \"FEX_{0}\") {{\n".format(op_key.upper()))
+                output_argloader.write("Value = FEXCore::Config::EnumParser(FEXCore::Config::{}_EnumPairs, Value);\n".format(op_key, op_key))
+                output_argloader.write("}\n")
+
             if ("ArgumentHandler" in op_vals):
                 conversion_func = "FEXCore::Config::Handler::{0}".format(op_vals["ArgumentHandler"])
                 output_argloader.write("else if (Key == \"FEX_{0}\") {{\n".format(op_key.upper()))
@@ -411,6 +441,41 @@ def print_parse_envloader_options(options):
                 output_argloader.write("}\n")
     output_argloader.write("#endif\n")
 
+def print_parse_enum_options(options):
+    output_argloader.write("#ifdef ENUMDEFINES\n")
+    output_argloader.write("#undef ENUMDEFINES\n")
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            if (op_vals["Type"] == "strenum"):
+                output_argloader.write("enum {} : uint64_t {{\n".format(op_key))
+                Enums = op_vals["Enums"]
+                i = 0
+                # Always have an OFF.
+                output_argloader.write("\tOFF = 0,\n")
+                for enum_op_key, enum_op_vals in Enums.items():
+                    output_argloader.write("\t{} = 1ULL << {},\n".format(enum_op_key.upper(), i))
+                    i += 1
+
+                output_argloader.write("};\n")
+
+    for op_group, group_vals in options.items():
+        for op_key, op_vals in group_vals.items():
+            if (op_vals["Type"] == "strenum"):
+                Enums = op_vals["Enums"]
+
+                output_argloader.write("using {}ConfigPair = std::pair<std::string_view, FEXCore::Config::{}>;\n".format(op_key, op_key))
+                output_argloader.write("constexpr static std::array<{}ConfigPair, {}> {}_EnumPairs = {{{{\n".format(op_key, len(Enums) + 1, op_key))
+                i = 0
+                # Always have an OFF.
+                output_argloader.write("\t{{ \"off\", FEXCore::Config::{}::OFF }},\n".format(op_key))
+                for enum_op_key, enum_op_vals in Enums.items():
+                    output_argloader.write("\t{{ \"{}\", FEXCore::Config::{}::{} }},\n".format(enum_op_vals, op_key, enum_op_key.upper()))
+                    i += 1
+
+                output_argloader.write("}};\n")
+
+    output_argloader.write("#endif\n")
+
 def check_for_duplicate_options(options):
     short_map = []
     long_map = []
@@ -489,4 +554,7 @@ print_parse_argloader_options(options);
 # Generate environment loader code
 print_parse_envloader_options(options);
 
+# Generate enum variable options
+print_parse_enum_options(options);
+
 output_argloader.close()

External/FEXCore/Scripts/json_ir_generator.py

@@ -251,11 +251,8 @@ def parse_ops(ops):
 
 # Print out enum values
 def print_enums():
-    if len(IROps) > 255:
-        ExitError("We have more than uint8_t ops. We have {}. Time to upgrade to uint16_t".format(len(IROps)))
-
     output_file.write("#ifdef IROP_ENUM\n")
-    output_file.write("enum IROps : uint8_t {\n")
+    output_file.write("enum IROps : uint16_t {\n")
 
     for op in IROps:
         output_file.write("\tOP_{},\n" .format(op.Name.upper()))
@@ -291,6 +288,7 @@ def print_ir_structs(defines):
     output_file.write("\tOrderedNodeWrapper Args[0];\n")
 
     output_file.write("};\n\n");
+    output_file.write("static_assert(sizeof(IROp_Header) == sizeof(uint32_t), \"IROp_Header should be 32-bits in size\");\n\n");
 
     # Now the user defined types
     output_file.write("// User defined IR Op structs\n")
@@ -677,7 +675,7 @@ def print_ir_allocator_helpers():
                 output_file.write("\t\t#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED\n")
 
                 for Validation in op.EmitValidation:
-                    output_file.write("\t\tassert({});\n".format(Validation))
+                    output_file.write("\tLOGMAN_THROW_A_FMT({}, \"\");\n".format(Validation))
                 output_file.write("\t\t#endif\n")
 
             output_file.write("\t\treturn Op;\n")

External/FEXCore/Source/CMakeLists.txt

@@ -1,13 +1,19 @@
-set (MAN_DIR ${CMAKE_INSTALL_PREFIX}/share/man CACHE PATH "MAN_DIR")
+set (MAN_DIR share/man CACHE PATH "MAN_DIR")
 
 set (FEXCORE_BASE_SRCS
-  Common/Paths.cpp
   Interface/Config/Config.cpp
+  Utils/Allocator.cpp
+  Utils/CPUInfo.cpp
   Utils/FileLoading.cpp
   Utils/ForcedAssert.cpp
   Utils/LogManager.cpp
   )
 
+if (NOT MINGW_BUILD)
+  list(APPEND FEXCORE_BASE_SRCS
+    Utils/Allocator/64BitAllocator.cpp)
+endif()
+
 set (SRCS
   Common/JitSymbols.cpp
   Common/SoftFloat-3e/extF80_add.c
@@ -99,12 +105,11 @@ set (SRCS
   Interface/Core/X86Tables.cpp
   Interface/Core/X86DebugInfo.cpp
   Interface/Core/X86HelperGen.cpp
-  Interface/Core/ArchHelpers/Arm64_stubs.cpp
   Interface/Core/ArchHelpers/Arm64Emitter.cpp
   Interface/Core/Dispatcher/Dispatcher.cpp
   Interface/Core/Dispatcher/X86Dispatcher.cpp
   Interface/Core/Dispatcher/Arm64Dispatcher.cpp
-  Interface/Core/Interpreter/InterpreterFallbacks.cpp
+  Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp
   Interface/Core/X86Tables/BaseTables.cpp
   Interface/Core/X86Tables/DDDTables.cpp
   Interface/Core/X86Tables/EVEXTables.cpp
@@ -137,14 +142,23 @@ set (SRCS
   Interface/IR/Passes/DeadStoreElimination.cpp
   Interface/IR/Passes/RegisterAllocationPass.cpp
   Interface/IR/Passes/SyscallOptimization.cpp
-  Utils/Allocator.cpp
-  Utils/Allocator/64BitAllocator.cpp
   Utils/NetStream.cpp
   Utils/Telemetry.cpp
   Utils/Threads.cpp
   Utils/Profiler.cpp
   )
 
+if (_M_ARM_64)
+  list(APPEND SRCS Utils/ArchHelpers/Arm64.cpp)
+else()
+  list(APPEND SRCS Utils/ArchHelpers/Arm64_stubs.cpp)
+endif()
+
+if (ENABLE_GLIBC_ALLOCATOR_HOOK_FAULT)
+  list(APPEND FEXCORE_BASE_SRCS
+    Utils/AllocatorOverride.cpp)
+endif()
+
 if (ENABLE_INTERPRETER)
   list(APPEND SRCS
     Interface/Core/Interpreter/InterpreterCore.cpp
@@ -162,11 +176,6 @@ if (ENABLE_INTERPRETER)
     Interface/Core/Interpreter/VectorOps.cpp)
 endif()
 
-if(_M_ARM_64)
-  list(APPEND SRCS
-    Interface/Core/ArchHelpers/Arm64.cpp)
-endif()
-
 set(DEFINES -DTHREAD_LOCAL=_Thread_local)
 
 if (_M_X86_64)
@@ -222,11 +231,22 @@ if (ENABLE_JIT_ARM64)
     )
 endif()
 
-set (LIBS fmt::fmt vixl dl xxhash tiny-json FEXHeaderUtils)
+set (LIBS fmt::fmt vixl xxhash FEXHeaderUtils)
+
+if (NOT MINGW_BUILD)
+  list (APPEND LIBS dl)
+else()
+  list (APPEND LIBS synchronization)
+endif()
+
 if (ENABLE_JEMALLOC)
   list (APPEND LIBS FEX_jemalloc)
 endif()
 
+if (ENABLE_JEMALLOC_GLIBC_ALLOC)
+  list (APPEND LIBS FEX_jemalloc_glibc)
+endif()
+
 # Generate config
 configure_file(
   ${CMAKE_CURRENT_SOURCE_DIR}/Interface/Config/Config.json.in
@@ -331,7 +351,7 @@ function(AddDefaultOptionsToTarget Name)
   target_include_directories(${Name} PUBLIC "${CMAKE_BINARY_DIR}/include/")
 
   target_compile_definitions(${Name} PRIVATE ${DEFINES})
-  add_dependencies(${Name} CONFIG_INC)
+  add_dependencies(${Name} CONFIG_INC IR_INC)
 
   target_compile_options(${Name}
     PRIVATE
@@ -373,7 +393,6 @@ AddDefaultOptionsToTarget(FEXCore_Base)
 
 function(AddObject Name Type)
   add_library(${Name} ${Type} ${SRCS})
-  add_dependencies(${Name} IR_INC)
 
   target_link_libraries(${Name} FEXCore_Base)
   AddDefaultOptionsToTarget(${Name})
@@ -385,6 +404,16 @@ function(AddLibrary Name Type)
   add_library(${Name} ${Type} $<TARGET_OBJECTS:${PROJECT_NAME}_object>)
   target_link_libraries(${Name} FEXCore_Base)
   set_target_properties(${Name} PROPERTIES OUTPUT_NAME FEXCore)
+  if (MINGW_BUILD)
+    # Mingw build isn't building a linux shared library, so it can't have a SONAME.
+    set_target_properties(${Name} PROPERTIES NO_SONAME ON)
+    # Change the suffixes otherwise cmake continues using .a and .so
+    if (${Type} STREQUAL SHARED)
+      set_target_properties(${Name} PROPERTIES SUFFIX ".dll")
+    elseif(${Type} STREQUAL STATIC)
+      set_target_properties(${Name} PROPERTIES SUFFIX ".lib")
+    endif()
+  endif()
 
   AddDefaultOptionsToTarget(${Name})
 endfunction()
@@ -393,10 +422,12 @@ AddObject(${PROJECT_NAME}_object OBJECT)
 AddLibrary(${PROJECT_NAME} STATIC)
 AddLibrary(${PROJECT_NAME}_shared SHARED)
 
-install(TARGETS ${PROJECT_NAME} ${PROJECT_NAME}_shared
-  LIBRARY
-    DESTINATION lib
-    COMPONENT Libraries
-  ARCHIVE
-    DESTINATION lib
-    COMPONENT Libraries)
+if (NOT MINGW_BUILD)
+  install(TARGETS ${PROJECT_NAME} ${PROJECT_NAME}_shared
+    LIBRARY
+      DESTINATION lib
+      COMPONENT Libraries
+    ARCHIVE
+      DESTINATION lib
+      COMPONENT Libraries)
+endif()

External/FEXCore/Source/Common/JitSymbols.cpp

@@ -1,11 +1,10 @@
+#include <FEXCore/fextl/fmt.h>
+
 #include "Common/JitSymbols.h"
 
 #include <fcntl.h>
-#include <string>
 #include <unistd.h>
 
-#include <fmt/format.h>
-
 namespace FEXCore {
   JITSymbols::JITSymbols() {
   }
@@ -18,8 +17,12 @@ namespace FEXCore {
 
   void JITSymbols::InitFile() {
     // We can't use FILE here since we must be robust against forking processes closing our FD from under us.
-    const auto PerfMap = fmt::format("/tmp/perf-{}.map", getpid());
-
+#ifdef __ANDROID__
+    // Android simpleperf looks in /data/local/tmp instead of /tmp
+    const auto PerfMap = fextl::fmt::format("/data/local/tmp/perf-{}.map", getpid());
+#else
+    const auto PerfMap = fextl::fmt::format("/tmp/perf-{}.map", getpid());
+#endif
     fd = open(PerfMap.c_str(), O_CREAT | O_TRUNC | O_WRONLY | O_APPEND, 0644);
   }
 
@@ -28,7 +31,7 @@ namespace FEXCore {
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fmt::format("{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
+    const auto Buffer = fextl::fmt::format("{} {:x} JIT_0x{:x}_{}\n", HostAddr, CodeSize, GuestAddr, HostAddr);
     auto Result = write(fd, Buffer.c_str(), Buffer.size());
     if (Result == -1 && errno == EBADF) {
       fd = -1;
@@ -40,7 +43,7 @@ namespace FEXCore {
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fmt::format("{} {:x} {}_{}\n", HostAddr, CodeSize, Name, HostAddr);
+    const auto Buffer = fextl::fmt::format("{} {:x} {}_{}\n", HostAddr, CodeSize, Name, HostAddr);
     auto Result = write(fd, Buffer.c_str(), Buffer.size());
     if (Result == -1 && errno == EBADF) {
       fd = -1;
@@ -52,7 +55,7 @@ namespace FEXCore {
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fmt::format("{} {:x} {}+0x{:x} ({})\n", HostAddr, CodeSize, Name, Offset, HostAddr);
+    const auto Buffer = fextl::fmt::format("{} {:x} {}+0x{:x} ({})\n", HostAddr, CodeSize, Name, Offset, HostAddr);
     auto Result = write(fd, Buffer.c_str(), Buffer.size());
     if (Result == -1 && errno == EBADF) {
       fd = -1;
@@ -64,7 +67,7 @@ namespace FEXCore {
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fmt::format("{} {:x} {}\n", HostAddr, CodeSize, Name);
+    const auto Buffer = fextl::fmt::format("{} {:x} {}\n", HostAddr, CodeSize, Name);
     auto Result = write(fd, Buffer.c_str(), Buffer.size());
     if (Result == -1 && errno == EBADF) {
       fd = -1;
@@ -76,7 +79,7 @@ namespace FEXCore {
 
     // Linux perf format is very straightforward
     // `<HostPtr> <Size> <Name>\n`
-    const auto Buffer = fmt::format("{} {:x} FEXJIT\n", HostAddr, CodeSize);
+    const auto Buffer = fextl::fmt::format("{} {:x} FEXJIT\n", HostAddr, CodeSize);
     auto Result = write(fd, Buffer.c_str(), Buffer.size());
     if (Result == -1 && errno == EBADF) {
       fd = -1;

External/FEXCore/Source/Common/Paths.cpp

@@ -1,91 +0,0 @@
-#include "Common/Paths.h"
-#include <FEXCore/Utils/LogManager.h>
-
-#include <cstdlib>
-#include <filesystem>
-#include <memory>
-#include <pwd.h>
-#include <system_error>
-#include <unistd.h>
-
-namespace FEXCore::Paths {
-  std::unique_ptr<std::string> CachePath;
-  std::unique_ptr<std::string> EntryCache;
-
-  char const* FindUserHomeThroughUID() {
-    auto passwd = getpwuid(geteuid());
-    if (passwd) {
-      return passwd->pw_dir;
-    }
-    return nullptr;
-  }
-
-  const char *GetHomeDirectory() {
-    char const *HomeDir = getenv("HOME");
-
-    // Try to get home directory from uid
-    if (!HomeDir) {
-      HomeDir = FindUserHomeThroughUID();
-    }
-
-    // try the PWD
-    if (!HomeDir) {
-      HomeDir = getenv("PWD");
-    }
-
-    // Still doesn't exit? You get local
-    if (!HomeDir) {
-      HomeDir = ".";
-    }
-
-    return HomeDir;
-  }
-
-  void InitializePaths() {
-    CachePath = std::make_unique<std::string>();
-    EntryCache = std::make_unique<std::string>();
-
-    char const *HomeDir = getenv("HOME");
-
-    if (!HomeDir) {
-      HomeDir = getenv("PWD");
-    }
-
-    if (!HomeDir) {
-      HomeDir = ".";
-    }
-
-    char *XDGDataDir = getenv("XDG_DATA_DIR");
-    if (XDGDataDir) {
-      *CachePath = XDGDataDir;
-    }
-    else {
-      if (HomeDir) {
-        *CachePath = HomeDir;
-      }
-    }
-
-    *CachePath += "/.fex-emu/";
-    *EntryCache = *CachePath + "/EntryCache/";
-
-    std::error_code ec{};
-    // Ensure the folder structure is created for our Data
-    if (!std::filesystem::exists(*EntryCache, ec) &&
-        !std::filesystem::create_directories(*EntryCache, ec)) {
-      LogMan::Msg::DFmt("Couldn't create EntryCache directory: '{}'", *EntryCache);
-    }
-  }
-
-  void ShutdownPaths() {
-    CachePath.reset();
-    EntryCache.reset();
-  }
-
-  std::string GetCachePath() {
-    return *CachePath;
-  }
-
-  std::string GetEntryCachePath() {
-    return *EntryCache;
-  }
-}

External/FEXCore/Source/Common/Paths.h

@@ -1,12 +0,0 @@
-#pragma once
-#include <string>
-
-namespace FEXCore::Paths {
-  void InitializePaths();
-  void ShutdownPaths();
-
-  const char *GetHomeDirectory();
-
-  std::string GetCachePath();
-  std::string GetEntryCachePath();
-}

External/FEXCore/Source/Common/SoftFloat.h

@@ -2,19 +2,19 @@
 
 #include <FEXCore/Utils/BitUtils.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/fextl/sstream.h>
+#include <FEXCore/fextl/string.h>
 
 #include <cmath>
 #include <cstring>
 #include <stdint.h>
-#include <string>
-#include <sstream>
 
 extern "C" {
 #include "SoftFloat-3e/platform.h"
 #include "SoftFloat-3e/softfloat.h"
 }
 
-struct X80SoftFloat {
+struct FEX_PACKED X80SoftFloat {
 #ifdef _M_X86_64
 // Define this to push some operations to x87
 // Only useful to see if precision loss is killing something
@@ -32,22 +32,28 @@ struct X80SoftFloat {
 #else
 #error No 128bit float for this target!
 #endif
-  struct __attribute__((packed)) {
-    uint64_t Significand : 64;
-    uint16_t Exponent    : 15;
-    unsigned Sign        : 1;
-  };
+
+#ifndef _WIN32
+#define LIBRARY_PRECISION BIGFLOAT
+#else
+// Mingw Win32 libraries don't have `__float128` helpers. Needs to use a lower precision.
+#define LIBRARY_PRECISION double
+#endif
+
+  uint64_t Significand : 64;
+  uint16_t Exponent    : 15;
+  uint16_t Sign        : 1;
 
   X80SoftFloat() { memset(this, 0, sizeof(*this)); }
-  X80SoftFloat(unsigned _Sign, uint16_t _Exponent, uint64_t _Significand)
+  X80SoftFloat(uint16_t _Sign, uint16_t _Exponent, uint64_t _Significand)
     : Significand {_Significand}
     , Exponent {_Exponent}
     , Sign {_Sign}
     {
   }
 
-  std::string str() const {
-    std::ostringstream string;
+  fextl::string str() const {
+    fextl::ostringstream string;
     string << std::hex << Sign;
     string << "_" << Exponent;
     string << "_" << (Significand >> 63);
@@ -262,7 +268,7 @@ struct X80SoftFloat {
     return Result;
 #else
     X80SoftFloat Int = FRNDINT(rhs, softfloat_round_minMag);
-    BIGFLOAT Src2_d = Int;
+    LIBRARY_PRECISION Src2_d = Int;
     Src2_d = exp2l(Src2_d);
     X80SoftFloat Src2_X80 = Src2_d;
     X80SoftFloat Result = extF80_mul(lhs, Src2_X80);
@@ -286,8 +292,8 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src1_d = lhs;
-    BIGFLOAT Result = exp2l(Src1_d);
+    LIBRARY_PRECISION Src1_d = lhs;
+    LIBRARY_PRECISION Result = exp2l(Src1_d);
     Result -= 1.0;
     return Result;
 #endif
@@ -311,9 +317,9 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src1_d = lhs;
-    BIGFLOAT Src2_d = rhs;
-    BIGFLOAT Tmp = Src2_d * log2l(Src1_d);
+    LIBRARY_PRECISION Src1_d = lhs;
+    LIBRARY_PRECISION Src2_d = rhs;
+    LIBRARY_PRECISION Tmp = Src2_d * log2l(Src1_d);
     return Tmp;
 #endif
   }
@@ -336,9 +342,9 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src1_d = lhs;
-    BIGFLOAT Src2_d = rhs;
-    BIGFLOAT Tmp = atan2l(Src1_d, Src2_d);
+    LIBRARY_PRECISION Src1_d = lhs;
+    LIBRARY_PRECISION Src2_d = rhs;
+    LIBRARY_PRECISION Tmp = atan2l(Src1_d, Src2_d);
     return Tmp;
 #endif
   }
@@ -360,7 +366,7 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs;
     Src_d = tanl(Src_d);
     return Src_d;
 #endif
@@ -382,7 +388,7 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs;
     Src_d = sinl(Src_d);
     return Src_d;
 #endif
@@ -404,7 +410,7 @@ struct X80SoftFloat {
 
     return Result;
 #else
-    BIGFLOAT Src_d = lhs;
+    LIBRARY_PRECISION Src_d = lhs;
     Src_d = cosl(Src_d);
     return Src_d;
 #endif
@@ -439,6 +445,7 @@ struct X80SoftFloat {
     return FEXCore::BitCast<double>(Result);
   }
 
+#ifndef _WIN32
   operator BIGFLOAT() const {
 #if BIGFLOATSIZE == 16
     const float128_t Result = extF80_to_f128(*this);
@@ -449,6 +456,7 @@ struct X80SoftFloat {
     return result;
 #endif
   }
+#endif
 
   operator int16_t() const {
     auto rv = extF80_to_i32(*this, softfloat_roundingMode, false);
@@ -517,6 +525,7 @@ struct X80SoftFloat {
     *this = f64_to_extF80(FEXCore::BitCast<float64_t>(rhs));
   }
 
+#ifndef _WIN32
   X80SoftFloat(BIGFLOAT rhs) {
 #if BIGFLOATSIZE == 16
     *this = f128_to_extF80(FEXCore::BitCast<float128_t>(rhs));
@@ -524,6 +533,7 @@ struct X80SoftFloat {
     *this = FEXCore::BitCast<long double>(rhs);
 #endif
   }
+#endif
 
   X80SoftFloat(const int16_t rhs) {
     *this = i32_to_extF80(rhs);
@@ -562,4 +572,9 @@ private:
   static constexpr uint32_t ExponentBias = 16383;
 };
 
+#ifndef _WIN32
 static_assert(sizeof(X80SoftFloat) == 10, "tword must be 10bytes in size");
+#else
+// Padding on this extends to 16-bytes rather than 10-bytes on WIN32.
+static_assert(sizeof(X80SoftFloat) == 16, "tword must be 16bytes in size");
+#endif

External/FEXCore/Source/Common/StringConv.h

@@ -1,48 +1,49 @@
 #pragma once
+#include <FEXCore/fextl/string.h>
+
 #include <cstdint>
-#include <string>
 #include <string_view>
 #include <optional>
 
 namespace FEXCore::StrConv {
   [[maybe_unused]] static bool Conv(std::string_view Value, bool *Result) {
-    *Result = std::stoi(std::string(Value), nullptr, 0);
+    *Result = std::strtoull(Value.data(), nullptr, 0);
     return true;
   }
 
   [[maybe_unused]] static bool Conv(std::string_view Value, uint8_t *Result) {
-    *Result = std::stoi(std::string(Value), nullptr, 0);
+    *Result = std::strtoul(Value.data(), nullptr, 0);
     return true;
   }
 
   [[maybe_unused]] static bool Conv(std::string_view Value, uint16_t *Result) {
-    *Result = std::stoi(std::string(Value), nullptr, 0);
+    *Result = std::strtoul(Value.data(), nullptr, 0);
     return true;
   }
 
   [[maybe_unused]] static bool Conv(std::string_view Value, uint32_t *Result) {
-    *Result = std::stoi(std::string(Value), nullptr, 0);
+    *Result = std::strtoul(Value.data(), nullptr, 0);
     return true;
   }
 
   [[maybe_unused]] static bool Conv(std::string_view Value, int32_t *Result) {
-    *Result = std::stoi(std::string(Value), nullptr, 0);
+    *Result = std::strtol(Value.data(), nullptr, 0);
     return true;
   }
 
   [[maybe_unused]] static bool Conv(std::string_view Value, uint64_t *Result) {
-    *Result = std::stoull(std::string(Value), nullptr, 0);
-    return true;
-  }
-  [[maybe_unused]] static bool Conv(std::string_view Value, std::string *Result) {
-    *Result = Value;
+    *Result = std::strtoull(Value.data(), nullptr, 0);
     return true;
   }
   template <typename T,
     typename = std::enable_if<std::is_enum<T>::value, T>>
   [[maybe_unused]] static bool Conv(std::string_view Value, T *Result) {
-    *Result = static_cast<T>(std::stoull(std::string(Value), nullptr, 0));
+    *Result = static_cast<T>(std::stoull(Value.data(), nullptr, 0));
     return true;
   }
 
+  [[maybe_unused]] static bool Conv(std::string_view Value, fextl::string *Result) {
+    *Result = Value;
+    return true;
+  }
 }

External/FEXCore/Source/Common/StringUtils.h

@@ -1,11 +1,11 @@
 #pragma once
-#include <string>
+#include <FEXCore/fextl/string.h>
 
 namespace FEXCore::StringUtils {
   // Trim the left side of the string of whitespace and new lines
-  [[maybe_unused]] static std::string LeftTrim(std::string String, std::string TrimTokens = " \t\n\r") {
-    size_t pos = std::string::npos;
-    if ((pos = String.find_first_not_of(TrimTokens)) != std::string::npos) {
+  [[maybe_unused]] static fextl::string LeftTrim(fextl::string String, std::string_view TrimTokens = " \t\n\r") {
+    size_t pos = fextl::string::npos;
+    if ((pos = String.find_first_not_of(TrimTokens)) != fextl::string::npos) {
       String.erase(0, pos);
     }
 
@@ -13,9 +13,9 @@ namespace FEXCore::StringUtils {
   }
 
   // Trim the right side of the string of whitespace and new lines
-  [[maybe_unused]] static std::string RightTrim(std::string String, std::string TrimTokens = " \t\n\r") {
-    size_t pos = std::string::npos;
-    if ((pos = String.find_last_not_of(TrimTokens)) != std::string::npos) {
+  [[maybe_unused]] static fextl::string RightTrim(fextl::string String, std::string_view TrimTokens = " \t\n\r") {
+    size_t pos = fextl::string::npos;
+    if ((pos = String.find_last_not_of(TrimTokens)) != fextl::string::npos) {
       String.erase(String.begin() + pos + 1, String.end());
     }
 
@@ -23,7 +23,8 @@ namespace FEXCore::StringUtils {
   }
 
   // Trim both the left and right of the string of whitespace and new lines
-  [[maybe_unused]] static std::string Trim(std::string String, std::string TrimTokens = " \t\n\r") {
-    return RightTrim(LeftTrim(String, TrimTokens), TrimTokens);
+  [[maybe_unused]] static fextl::string Trim(fextl::string String, std::string_view TrimTokens = " \t\n\r") {
+    return RightTrim(LeftTrim(std::move(String), TrimTokens), TrimTokens);
   }
+
 }

External/FEXCore/Source/Interface/Config/Config.cpp

@@ -1,33 +1,31 @@
 #include "Common/StringConv.h"
 #include "Common/StringUtils.h"
-#include "Common/Paths.h"
-#include "Utils/FileLoading.h"
+#include "FEXCore/Utils/EnumUtils.h"
 
 #include <FEXCore/Config/Config.h>
+#include <FEXCore/Utils/Allocator.h>
+#include <FEXCore/Utils/CPUInfo.h>
+#include <FEXCore/Utils/FileLoading.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/fextl/fmt.h>
+#include <FEXCore/fextl/list.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/unordered_map.h>
+#include <FEXCore/fextl/vector.h>
+#include <FEXHeaderUtils/Filesystem.h>
 
 #include <array>
-#include <assert.h>
 #include <cstdlib>
-#include <filesystem>
-#include <fstream>
 #include <functional>
-#include <map>
-#include <memory>
-#include <list>
 #include <optional>
 #include <stddef.h>
 #include <stdint.h>
-#include <string>
 #include <string_view>
-#include <sys/sysinfo.h>
 #include <system_error>
 #include <type_traits>
-#include <unordered_map>
 #include <utility>
-#include <vector>
-
-#include <tiny-json.h>
 
 namespace FEXCore::Context {
   class Context;
@@ -39,176 +37,79 @@ namespace DefaultValues {
 #define OPT_BASE(type, group, enum, json, default) const P(type) P(enum) = P(default);
 #define OPT_STR(group, enum, json, default) const std::string_view P(enum) = P(default);
 #define OPT_STRARRAY(group, enum, json, default) OPT_STR(group, enum, json, default)
+#define OPT_STRENUM(group, enum, json, default) const uint64_t P(enum) = FEXCore::ToUnderlying(P(default));
 #include <FEXCore/Config/ConfigValues.inl>
 }
 
-namespace JSON {
-  struct JsonAllocator {
-    jsonPool_t PoolObject;
-    std::unique_ptr<std::list<json_t>> json_objects;
+  enum Paths {
+    PATH_DATA_DIR = 0,
+    PATH_CONFIG_DIR_LOCAL,
+    PATH_CONFIG_DIR_GLOBAL,
+    PATH_CONFIG_FILE_LOCAL,
+    PATH_CONFIG_FILE_GLOBAL,
+    PATH_LAST,
   };
-  static_assert(offsetof(JsonAllocator, PoolObject) == 0, "This needs to be at offset zero");
+  static std::array<fextl::string, Paths::PATH_LAST> Paths;
 
-  json_t* PoolInit(jsonPool_t* Pool) {
-    JsonAllocator* alloc = reinterpret_cast<JsonAllocator*>(Pool);
-    alloc->json_objects = std::make_unique<std::list<json_t>>();
-    return &*alloc->json_objects->emplace(alloc->json_objects->end());
+  void SetDataDirectory(const std::string_view Path) {
+    Paths[PATH_DATA_DIR] = Path;
   }
 
-  json_t* PoolAlloc(jsonPool_t* Pool) {
-    JsonAllocator* alloc = reinterpret_cast<JsonAllocator*>(Pool);
-    return &*alloc->json_objects->emplace(alloc->json_objects->end());
+  void SetConfigDirectory(const std::string_view Path, bool Global) {
+    Paths[PATH_CONFIG_DIR_LOCAL + Global] = Path;
   }
 
-  static void LoadJSonConfig(const std::string &Config, std::function<void(const char *Name, const char *ConfigSring)> Func) {
-    std::vector<char> Data;
-    if (!FEXCore::FileLoading::LoadFile(Data, Config)) {
-      return;
-    }
-
-    JsonAllocator Pool {
-      .PoolObject = {
-        .init = PoolInit,
-        .alloc = PoolAlloc,
-      },
-    };
-
-    json_t const *json = json_createWithPool(&Data.at(0), &Pool.PoolObject);
-    if (!json) {
-      LogMan::Msg::EFmt("Couldn't create json");
-      return;
-    }
-
-    json_t const* ConfigList = json_getProperty(json, "Config");
-
-    if (!ConfigList) {
-      // This is a non-error if the configuration file exists but no Config section
-      return;
-    }
-
-    for (json_t const* ConfigItem = json_getChild(ConfigList);
-      ConfigItem != nullptr;
-      ConfigItem = json_getSibling(ConfigItem)) {
-      const char* ConfigName = json_getName(ConfigItem);
-      const char* ConfigString = json_getValue(ConfigItem);
-
-      if (!ConfigName) {
-        LogMan::Msg::EFmt("Couldn't get config name");
-        return;
-      }
-
-      if (!ConfigString) {
-        LogMan::Msg::EFmt("Couldn't get ConfigString for '{}'", ConfigName);
-        return;
-      }
-
-      Func(ConfigName, ConfigString);
-    }
-  }
-}
-
-  std::string GetDataDirectory() {
-    std::string DataDir{};
-
-    char const *HomeDir = Paths::GetHomeDirectory();
-    char const *DataXDG = getenv("XDG_DATA_HOME");
-    char const *DataOverride = getenv("FEX_APP_DATA_LOCATION");
-    if (DataOverride) {
-      // Data override will override the complete directory
-      DataDir = DataOverride;
-    }
-    else {
-      DataDir = DataXDG ?: HomeDir;
-      DataDir += "/.fex-emu/";
-    }
-    return DataDir;
+  void SetConfigFileLocation(const std::string_view Path, bool Global) {
+    Paths[PATH_CONFIG_FILE_LOCAL + Global] = Path;
   }
 
-  std::string GetConfigDirectory(bool Global) {
-    std::string ConfigDir;
-    if (Global) {
-      ConfigDir = GLOBAL_DATA_DIRECTORY;
-    }
-    else {
-      char const *HomeDir = Paths::GetHomeDirectory();
-      char const *ConfigXDG = getenv("XDG_CONFIG_HOME");
-      char const *ConfigOverride = getenv("FEX_APP_CONFIG_LOCATION");
-      if (ConfigOverride) {
-        // Config override completely overrides the config directory
-        ConfigDir = ConfigOverride;
-      }
-      else {
-        ConfigDir = ConfigXDG ? ConfigXDG : HomeDir;
-        ConfigDir += "/.fex-emu/";
-      }
-
-      // Ensure the folder structure is created for our configuration
-      std::error_code ec{};
-      if (!std::filesystem::exists(ConfigDir, ec) &&
-          !std::filesystem::create_directories(ConfigDir, ec)) {
-        // Let's go local in this case
-        return "./";
-      }
-    }
-
-    return ConfigDir;
+  fextl::string const& GetDataDirectory() {
+    return Paths[PATH_DATA_DIR];
   }
 
-  std::string GetConfigFileLocation(bool Global) {
-    std::string ConfigFile{};
-    if (Global) {
-      ConfigFile = GetConfigDirectory(true) + "Config.json";
-    }
-    else {
-      const char *AppConfig = getenv("FEX_APP_CONFIG");
-      if (AppConfig) {
-        // App config environment variable overwrites only the config file
-        ConfigFile = AppConfig;
-      }
-      else {
-        ConfigFile = GetConfigDirectory(false) + "Config.json";
-      }
-    }
-    return ConfigFile;
+  fextl::string const& GetConfigDirectory(bool Global) {
+    return Paths[PATH_CONFIG_DIR_LOCAL + Global];
   }
 
-  std::string GetApplicationConfig(const std::string &Filename, bool Global) {
-    std::string ConfigFile = GetConfigDirectory(Global);
+  fextl::string const& GetConfigFileLocation(bool Global) {
+    return Paths[PATH_CONFIG_FILE_LOCAL + Global];
+  }
+
+  fextl::string GetApplicationConfig(const std::string_view Program, bool Global) {
+    fextl::string ConfigFile = GetConfigDirectory(Global);
 
-    std::error_code ec{};
     if (!Global &&
-        !std::filesystem::exists(ConfigFile, ec) &&
-        !std::filesystem::create_directories(ConfigFile, ec)) {
+        !FHU::Filesystem::Exists(ConfigFile) &&
+        !FHU::Filesystem::CreateDirectories(ConfigFile)) {
       LogMan::Msg::DFmt("Couldn't create config directory: '{}'", ConfigFile);
       // Let's go local in this case
-      return "./" + Filename + ".json";
+      return fextl::fmt::format("./{}.json", Program);
     }
 
     ConfigFile += "AppConfig/";
 
     // Attempt to create the local folder if it doesn't exist
     if (!Global &&
-        !std::filesystem::exists(ConfigFile, ec) &&
-        !std::filesystem::create_directories(ConfigFile, ec)) {
+        !FHU::Filesystem::Exists(ConfigFile) &&
+        !FHU::Filesystem::CreateDirectories(ConfigFile)) {
       // Let's go local in this case
-      return "./" + Filename + ".json";
+      return fextl::fmt::format("./{}.json", Program);
     }
 
-    ConfigFile += Filename + ".json";
-    return ConfigFile;
+    return fextl::fmt::format("{}{}.json", ConfigFile, Program);
   }
 
   void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, uint64_t Config) {
   }
 
-  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, std::string const &Config) {
+  void SetConfig(FEXCore::Context::Context *CTX, ConfigOption Option, fextl::string const &Config) {
   }
 
   uint64_t GetConfig(FEXCore::Context::Context *CTX, ConfigOption Option) {
     return 0;
   }
 
-  static std::map<FEXCore::Config::LayerType, std::unique_ptr<FEXCore::Config::Layer>> ConfigLayers;
+  static fextl::map<FEXCore::Config::LayerType, fextl::unique_ptr<FEXCore::Config::Layer>> ConfigLayers;
   static FEXCore::Config::Layer *Meta{};
 
   constexpr std::array<FEXCore::Config::LayerType, 9> LoadOrder = {
@@ -268,17 +169,17 @@ namespace JSON {
     }
 
     // If an environment variable exists in both current meta and in the incoming layer then the meta layer value is overwritten
-    std::unordered_map<std::string, std::string> LookupMap;
+    fextl::unordered_map<fextl::string, fextl::string> LookupMap;
     const auto AddToMap = [&LookupMap](FEXCore::Config::LayerValue const &Value) {
       for (const auto &EnvVar : Value) {
         const auto ItEq = EnvVar.find_first_of('=');
-        if (ItEq == std::string::npos) {
+        if (ItEq == fextl::string::npos) {
           // Broken environment variable
           // Skip
           continue;
         }
-        auto Key = std::string(EnvVar.begin(), EnvVar.begin() + ItEq);
-        auto Value = std::string(EnvVar.begin() + ItEq + 1, EnvVar.end());
+        auto Key = fextl::string(EnvVar.begin(), EnvVar.begin() + ItEq);
+        auto Value = fextl::string(EnvVar.begin() + ItEq + 1, EnvVar.end());
 
         // Add the key to the map, overwriting whatever previous value was there
         LookupMap.insert_or_assign(std::move(Key), std::move(Value));
@@ -311,7 +212,7 @@ namespace JSON {
   }
 
   void Initialize() {
-    AddLayer(std::make_unique<MetaLayer>(FEXCore::Config::LayerType::LAYER_TOP));
+    AddLayer(fextl::make_unique<MetaLayer>(FEXCore::Config::LayerType::LAYER_TOP));
     Meta = ConfigLayers.begin()->second.get();
   }
 
@@ -329,16 +230,15 @@ namespace JSON {
     }
   }
 
-  std::string ExpandPath(std::string const &ContainerPrefix, std::string PathName) {
+  fextl::string ExpandPath(fextl::string const &ContainerPrefix, fextl::string PathName) {
     if (PathName.empty()) {
       return {};
     }
 
-    std::filesystem::path Path{PathName};
 
     // Expand home if it exists
-    if (Path.is_relative()) {
-      std::string Home = getenv("HOME") ?: "";
+    if (FHU::Filesystem::IsRelative(PathName)) {
+      fextl::string Home = getenv("HOME") ?: "";
       // Home expansion only works if it is the first character
       // This matches bash behaviour
       if (PathName.at(0) == '~') {
@@ -347,12 +247,15 @@ namespace JSON {
       }
 
       // Expand relative path to absolute
-      Path = std::filesystem::absolute(Path);
+      char ExistsTempPath[PATH_MAX];
+      char *RealPath = FHU::Filesystem::Absolute(PathName.c_str(), ExistsTempPath);
+      if (RealPath) {
+        PathName = RealPath;
+      }
 
       // Only return if it exists
-      std::error_code ec{};
-      if (std::filesystem::exists(Path, ec)) {
-        return Path;
+      if (FHU::Filesystem::Exists(PathName)) {
+        return PathName;
       }
     }
     else {
@@ -368,9 +271,9 @@ namespace JSON {
       // HostThunks: $CMAKE_INSTALL_PREFIX/lib/fex-emu/HostThunks/
       // GuestThunks: $CMAKE_INSTALL_PREFIX/share/fex-emu/GuestThunks/
       if (!ContainerPrefix.empty() && !PathName.empty()) {
-        if (!std::filesystem::exists(PathName)) {
+        if (!FHU::Filesystem::Exists(PathName)) {
           auto ContainerPath = ContainerPrefix + PathName;
-          if (std::filesystem::exists(ContainerPath)) {
+          if (FHU::Filesystem::Exists(ContainerPath)) {
             return ContainerPath;
           }
         }
@@ -379,15 +282,15 @@ namespace JSON {
     return {};
   }
 
+  constexpr char ContainerManager[] = "/run/host/container-manager";
 
-  std::string FindContainer() {
+  fextl::string FindContainer() {
     // We only support pressure-vessel at the moment
-    const static std::string ContainerManager = "/run/host/container-manager";
-    if (std::filesystem::exists(ContainerManager)) {
-      std::vector<char> Manager{};
+    if (FHU::Filesystem::Exists(ContainerManager)) {
+      fextl::vector<char> Manager{};
       if (FEXCore::FileLoading::LoadFile(Manager, ContainerManager)) {
         // Trim the whitespace, may contain a newline
-        std::string ManagerStr = Manager.data();
+        fextl::string ManagerStr = Manager.data();
         ManagerStr = FEXCore::StringUtils::Trim(ManagerStr);
         return ManagerStr;
       }
@@ -395,14 +298,13 @@ namespace JSON {
     return {};
   }
 
-  std::string FindContainerPrefix() {
+  fextl::string FindContainerPrefix() {
     // We only support pressure-vessel at the moment
-    const static std::string ContainerManager = "/run/host/container-manager";
-    if (std::filesystem::exists(ContainerManager)) {
-      std::vector<char> Manager{};
+    if (FHU::Filesystem::Exists(ContainerManager)) {
+      fextl::vector<char> Manager{};
       if (FEXCore::FileLoading::LoadFile(Manager, ContainerManager)) {
         // Trim the whitespace, may contain a newline
-        std::string ManagerStr = Manager.data();
+        fextl::string ManagerStr = Manager.data();
         ManagerStr = FEXCore::StringUtils::Trim(ManagerStr);
         if (strncmp(ManagerStr.data(), "pressure-vessel", Manager.size()) == 0) {
           // We are running inside of pressure vessel
@@ -424,7 +326,7 @@ namespace JSON {
       FEX_CONFIG_OPT(Cores, THREADS);
       if (Cores == 0) {
         // When the number of emulated CPU cores is zero then auto detect
-        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THREADS, std::to_string(get_nprocs_conf()));
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THREADS, fextl::fmt::format("{}", FEXCore::CPUInfo::CalculateNumberOfCPUs()));
       }
     }
 
@@ -443,7 +345,7 @@ namespace JSON {
 #endif
       if (Core > MaxCoreNumber || Core < MinCoreNumber) {
         // Sanitize the core option by setting the core to the JIT if invalid
-        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_CORE, std::to_string(FEXCore::Config::CONFIG_IRJIT));
+        FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_CORE, fextl::fmt::format("{}", static_cast<uint32_t>(FEXCore::Config::CONFIG_IRJIT)));
       }
     }
 
@@ -457,8 +359,8 @@ namespace JSON {
       }
     }
 
-    std::string ContainerPrefix { FindContainerPrefix() };
-    auto ExpandPathIfExists = [&ContainerPrefix](FEXCore::Config::ConfigOption Config, std::string PathName) {
+    fextl::string ContainerPrefix { FindContainerPrefix() };
+    auto ExpandPathIfExists = [&ContainerPrefix](FEXCore::Config::ConfigOption Config, fextl::string PathName) {
       auto NewPath = ExpandPath(ContainerPrefix, PathName);
       if (!NewPath.empty()) {
         FEXCore::Config::EraseSet(Config, NewPath);
@@ -467,16 +369,15 @@ namespace JSON {
 
     if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_ROOTFS)) {
       FEX_CONFIG_OPT(PathName, ROOTFS);
-      auto ExpandedString = ExpandPath(ContainerPrefix, PathName());
+      auto ExpandedString = ExpandPath(ContainerPrefix,PathName());
       if (!ExpandedString.empty()) {
         // Adjust the path if it ended up being relative
         FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, ExpandedString);
       }
       else if (!PathName().empty()) {
         // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
-        std::string NamedRootFS = GetDataDirectory() + "RootFS/" + PathName();
-        std::error_code ec{};
-        if (std::filesystem::exists(NamedRootFS, ec)) {
+        fextl::string NamedRootFS = GetDataDirectory() + "RootFS/" + PathName();
+        if (FHU::Filesystem::Exists(NamedRootFS)) {
           FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_ROOTFS, NamedRootFS);
         }
       }
@@ -498,9 +399,8 @@ namespace JSON {
       }
       else if (!PathName().empty()) {
         // If the filesystem doesn't exist then let's see if it exists in the fex-emu folder
-        std::string NamedConfig = GetDataDirectory() + "ThunkConfigs/" + PathName();
-        std::error_code ec{};
-        if (std::filesystem::exists(NamedConfig, ec)) {
+        fextl::string NamedConfig = GetDataDirectory() + "ThunkConfigs/" + PathName();
+        if (FHU::Filesystem::Exists(NamedConfig)) {
           FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THUNKCONFIG, NamedConfig);
         }
       }
@@ -514,11 +414,11 @@ namespace JSON {
 
     if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_SINGLESTEP)) {
       // Single stepping also enforces single instruction size blocks
-      Set(FEXCore::Config::ConfigOption::CONFIG_MAXINST, std::to_string(1u));
+      Set(FEXCore::Config::ConfigOption::CONFIG_MAXINST, "1");
     }
   }
 
-  void AddLayer(std::unique_ptr<FEXCore::Config::Layer> _Layer) {
+  void AddLayer(fextl::unique_ptr<FEXCore::Config::Layer> _Layer) {
     ConfigLayers.emplace(_Layer->GetLayerType(), std::move(_Layer));
   }
 
@@ -530,7 +430,7 @@ namespace JSON {
     return Meta->All(Option);
   }
 
-  std::optional<std::string*> Get(ConfigOption Option) {
+  std::optional<fextl::string*> Get(ConfigOption Option) {
     return Meta->Get(Option);
   }
 
@@ -552,7 +452,7 @@ namespace JSON {
     auto Value = FEXCore::Config::Get(Option);
 
     if (!FEXCore::StrConv::Conv(**Value, &Result)) {
-      assert(0 && "Attempted to convert invalid value");
+      LOGMAN_MSG_A_FMT("Attempted to convert invalid value");
     }
     return Result;
   }
@@ -571,7 +471,7 @@ namespace JSON {
   }
 
   template<>
-  std::string Value<std::string>::GetIfExists(FEXCore::Config::ConfigOption Option, std::string Default) {
+  fextl::string Value<fextl::string>::GetIfExists(FEXCore::Config::ConfigOption Option, fextl::string Default) {
     auto Value = FEXCore::Config::Get(Option);
     if (Value) {
       return **Value;
@@ -582,13 +482,13 @@ namespace JSON {
   }
 
   template<>
-  std::string Value<std::string>::GetIfExists(FEXCore::Config::ConfigOption Option, std::string_view Default) {
+  fextl::string Value<fextl::string>::GetIfExists(FEXCore::Config::ConfigOption Option, std::string_view Default) {
     auto Value = FEXCore::Config::Get(Option);
     if (Value) {
       return **Value;
     }
     else {
-      return std::string(Default);
+      return fextl::string(Default);
     }
   }
 
@@ -603,167 +503,19 @@ namespace JSON {
   template uint64_t Value<uint64_t>::GetIfExists(FEXCore::Config::ConfigOption Option, uint64_t Default);
 
   // Constructor
-  template Value<std::string>::Value(FEXCore::Config::ConfigOption _Option, std::string Default);
+  template Value<fextl::string>::Value(FEXCore::Config::ConfigOption _Option, fextl::string Default);
   template Value<bool>::Value(FEXCore::Config::ConfigOption _Option, bool Default);
   template Value<uint8_t>::Value(FEXCore::Config::ConfigOption _Option, uint8_t Default);
   template Value<uint64_t>::Value(FEXCore::Config::ConfigOption _Option, uint64_t Default);
 
   template<typename T>
-  void Value<T>::GetListIfExists(FEXCore::Config::ConfigOption Option, std::list<std::string> *List) {
+  void Value<T>::GetListIfExists(FEXCore::Config::ConfigOption Option, fextl::list<fextl::string> *List) {
     auto Value = FEXCore::Config::All(Option);
     List->clear();
     if (Value) {
       *List = **Value;
     }
   }
-  template void Value<std::string>::GetListIfExists(FEXCore::Config::ConfigOption Option, std::list<std::string> *List);
-
-  // Application loaders
-  class MainLoader final : public FEXCore::Config::OptionMapper {
-  public:
-    explicit MainLoader(FEXCore::Config::LayerType Type);
-    explicit MainLoader(std::string ConfigFile);
-    void Load() override;
-
-  private:
-    std::string Config;
-  };
-
-  class AppLoader final : public FEXCore::Config::OptionMapper {
-  public:
-    explicit AppLoader(const std::string& Filename, FEXCore::Config::LayerType Type);
-    void Load();
-
-  private:
-    std::string Config;
-  };
-
-  class EnvLoader final : public FEXCore::Config::Layer {
-  public:
-    explicit EnvLoader(char *const _envp[]);
-    void Load() override;
-
-  private:
-    char *const *envp;
-  };
-
-  static const std::map<std::string, FEXCore::Config::ConfigOption, std::less<>> ConfigLookup = {{
-#define OPT_BASE(type, group, enum, json, default) {#json, FEXCore::Config::ConfigOption::CONFIG_##enum},
-#include <FEXCore/Config/ConfigValues.inl>
-  }};
-  static const std::vector<std::pair<const char*, FEXCore::Config::ConfigOption>> EnvConfigLookup = {{
-#define OPT_BASE(type, group, enum, json, default) {"FEX_" #enum, FEXCore::Config::ConfigOption::CONFIG_##enum},
-#include <FEXCore/Config/ConfigValues.inl>
-  }};
-
-  OptionMapper::OptionMapper(FEXCore::Config::LayerType Layer)
-    : FEXCore::Config::Layer(Layer) {
-  }
-
-  void OptionMapper::MapNameToOption(const char *ConfigName, const char *ConfigString) {
-    auto it = ConfigLookup.find(ConfigName);
-    if (it != ConfigLookup.end()) {
-      Set(it->second, ConfigString);
-    }
-  }
-
-  MainLoader::MainLoader(FEXCore::Config::LayerType Type)
-    : FEXCore::Config::OptionMapper(Type)
-    , Config{FEXCore::Config::GetConfigFileLocation(Type == FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN)} {
-  }
-
-  MainLoader::MainLoader(std::string ConfigFile)
-    : FEXCore::Config::OptionMapper(FEXCore::Config::LayerType::LAYER_MAIN)
-    , Config{std::move(ConfigFile)} {
-  }
-
-  void MainLoader::Load() {
-    JSON::LoadJSonConfig(Config, [this](const char *Name, const char *ConfigString) {
-      MapNameToOption(Name, ConfigString);
-    });
-  }
-
-  AppLoader::AppLoader(const std::string& Filename, FEXCore::Config::LayerType Type)
-    : FEXCore::Config::OptionMapper(Type) {
-    const bool Global = Type == FEXCore::Config::LayerType::LAYER_GLOBAL_STEAM_APP ||
-                        Type == FEXCore::Config::LayerType::LAYER_GLOBAL_APP;
-    Config = FEXCore::Config::GetApplicationConfig(Filename, Global);
-
-    // Immediately load so we can reload the meta layer
-    Load();
-  }
-
-  void AppLoader::Load() {
-    JSON::LoadJSonConfig(Config, [this](const char *Name, const char *ConfigString) {
-      MapNameToOption(Name, ConfigString);
-    });
-  }
-
-  EnvLoader::EnvLoader(char *const _envp[])
-    : FEXCore::Config::Layer(FEXCore::Config::LayerType::LAYER_ENVIRONMENT)
-    , envp {_envp} {
-  }
-
-  void EnvLoader::Load() {
-    std::unordered_map<std::string_view, std::string_view> EnvMap;
-
-    for(const char *const *pvar=envp; pvar && *pvar; pvar++) {
-      std::string_view Var(*pvar);
-      size_t pos = Var.rfind('=');
-      if (std::string::npos == pos)
-        continue;
-
-      std::string_view Key = Var.substr(0,pos);
-      std::string_view Value {Var.substr(pos+1)};
-
-#define ENVLOADER
-#include <FEXCore/Config/ConfigOptions.inl>
-
-      EnvMap[Key]=Value;
-    }
-
-    std::function GetVar = [=](const std::string_view id)  -> std::optional<std::string_view> {
-      if (EnvMap.find(id) != EnvMap.end())
-        return EnvMap.at(id);
-
-      // If envp[] was empty, search using std::getenv()
-      const char* vs = std::getenv(id.data());
-      if (vs) {
-        return vs;
-      }
-      else {
-        return std::nullopt;
-      }
-    };
-
-    std::optional<std::string_view> Value;
-
-    for (auto &it : EnvConfigLookup) {
-      if ((Value = GetVar(it.first)).has_value()) {
-        Set(it.second, std::string(*Value));
-      }
-    }
-  }
-
-  std::unique_ptr<FEXCore::Config::Layer> CreateGlobalMainLayer() {
-    return std::make_unique<FEXCore::Config::MainLoader>(FEXCore::Config::LayerType::LAYER_GLOBAL_MAIN);
-  }
-
-  std::unique_ptr<FEXCore::Config::Layer> CreateMainLayer(std::string const *File) {
-    if (File) {
-      return std::make_unique<FEXCore::Config::MainLoader>(*File);
-    }
-    else {
-      return std::make_unique<FEXCore::Config::MainLoader>(FEXCore::Config::LayerType::LAYER_MAIN);
-    }
-  }
-
-  std::unique_ptr<FEXCore::Config::Layer> CreateAppLayer(const std::string& Filename, FEXCore::Config::LayerType Type) {
-    return std::make_unique<FEXCore::Config::AppLoader>(Filename, Type);
-  }
-
-  std::unique_ptr<FEXCore::Config::Layer> CreateEnvironmentLayer(char *const _envp[]) {
-    return std::make_unique<FEXCore::Config::EnvLoader>(_envp);
-  }
+  template void Value<fextl::string>::GetListIfExists(FEXCore::Config::ConfigOption Option, fextl::list<fextl::string> *List);
 }
 

External/FEXCore/Source/Interface/Config/Config.json.in

@@ -53,7 +53,7 @@
       },
       "EnableAVX": {
         "Type": "bool",
-        "Default": "true",
+        "Default": "false",
         "Desc": [
           "Determines whether or not we use the expanded register file for AVX or not"
         ]
@@ -251,6 +251,20 @@
           "Set this in an application configuration for injecting in to only specific applications.",
           "\tNote: If x86/x86_64 libSegFault.so isn't installed then this option won't work."
         ]
+      },
+      "Disassemble": {
+        "Type": "strenum",
+        "Default": "FEXCore::Config::Disassemble::OFF",
+        "Enums": {
+          "DISPATCHER": "dispatcher",
+          "BLOCKS": "blocks"
+        },
+        "Desc": [
+          "Allows controlling of the vixl disassembler.",
+          "\toff: No disassembly will be output",
+          "\tdispatcher: Will enable disassembly of the JIT dispatcher loop",
+          "\tblocks: Will enable disassembly of the translated instruction code blocks"
+        ]
       }
     },
     "Logging": {

External/FEXCore/Source/Interface/Context/Context.cpp

@@ -1,6 +1,4 @@
-#include "Common/Paths.h"
 #include "Interface/Context/Context.h"
-#include "Interface/Core/Core.h"
 #include "Interface/Core/OpcodeDispatcher.h"
 #include "Interface/Core/X86Tables/X86Tables.h"
 
@@ -19,32 +17,18 @@ namespace FEXCore::HLE {
 
 namespace FEXCore::Context {
   void InitializeStaticTables(OperatingMode Mode) {
-    FEXCore::Paths::InitializePaths();
     X86Tables::InitializeInfoTables(Mode);
     IR::InstallOpcodeHandlers(Mode);
   }
 
-  void ShutdownStaticTables() {
-    FEXCore::Paths::ShutdownPaths();
-  }
-
-  FEXCore::Context::Context *FEXCore::Context::Context::CreateNewContext() {
-    return new FEXCore::Context::ContextImpl{};
-  }
-
-  void FEXCore::Context::Context::DestroyContext(FEXCore::Context::Context *CTX) {
-    CTX->DestroyContext();
-    delete CTX;
+  fextl::unique_ptr<FEXCore::Context::Context> FEXCore::Context::Context::CreateNewContext() {
+    return fextl::make_unique<FEXCore::Context::ContextImpl>();
   }
 
   bool FEXCore::Context::ContextImpl::InitializeContext() {
-    return FEXCore::CPU::CreateCPUCore(this);
-  }
-
-  void FEXCore::Context::ContextImpl::DestroyContext() {
-    if (ParentThread) {
-      DestroyThread(ParentThread);
-    }
+    // This should be used for generating things that are shared between threads
+    CPUID.Init(this);
+    return true;
   }
 
   void FEXCore::Context::ContextImpl::SetExitHandler(ExitHandler handler) {
@@ -83,10 +67,6 @@ namespace FEXCore::Context {
     CustomCPUFactory = std::move(Factory);
   }
 
-  bool FEXCore::Context::ContextImpl::AddVirtualMemoryMapping([[maybe_unused]] uint64_t VirtualAddress, [[maybe_unused]] uint64_t PhysicalAddress, [[maybe_unused]] uint64_t Size) {
-    return false;
-  }
-
   HostFeatures FEXCore::Context::ContextImpl::GetHostFeatures() const {
     return HostFeatures;
   }
@@ -104,41 +84,11 @@ namespace FEXCore::Context {
     return CPUID.RunFunction(Function, Leaf);
   }
 
+  FEXCore::CPUID::XCRResults FEXCore::Context::ContextImpl::RunXCRFunction(uint32_t Function) {
+    return CPUID.RunXCRFunction(Function);
+  }
+
   FEXCore::CPUID::FunctionResults FEXCore::Context::ContextImpl::RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) {
     return CPUID.RunFunctionName(Function, Leaf, CPU);
   }
-  void SetVDSOSigReturn(FEXCore::Context::Context *CTX, const VDSOSigReturn &Pointers) {
-    CTX->SetVDSOSigReturn(Pointers);
-  }
-
-namespace Debug {
-  //void CompileRIP(FEXCore::Context::Context *CTX, uint64_t RIP) {
-  //  CTX->CompileRIP(CTX->ParentThread, RIP);
-  //}
-  //uint64_t GetThreadCount(FEXCore::Context::Context *CTX) {
-  //  return CTX->GetThreadCount();
-  //}
-
-  //FEXCore::Core::RuntimeStats *GetRuntimeStatsForThread(FEXCore::Context::Context *CTX, uint64_t Thread) {
-  //  return CTX->GetRuntimeStatsForThread(Thread);
-  //}
-
-  //bool GetDebugDataForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::Core::DebugData *Data) {
-  //  return CTX->GetDebugDataForRIP(RIP, Data);
-  //}
-
-  //bool FindHostCodeForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, uint8_t **Code) {
-  //  return CTX->FindHostCodeForRIP(RIP, Code);
-  //}
-
-  // XXX:
-  // bool FindIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList **ir) {
-  //   return CTX->FindIRForRIP(RIP, ir);
-  // }
-
-  // void SetIRForRIP(FEXCore::Context::Context *CTX, uint64_t RIP, FEXCore::IR::IntrusiveIRList *const ir) {
-  //   CTX->SetIRForRIP(RIP, ir);
-  // }
-}
-
 }

External/FEXCore/Source/Interface/Context/Context.h

@@ -1,7 +1,6 @@
 #pragma once
 
 #include "Common/JitSymbols.h"
-#include "FEXHeaderUtils/ScopedSignalMask.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/X86HelperGen.h"
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
@@ -14,24 +13,25 @@
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/CompilerDefs.h>
+#include <FEXCore/Utils/DeferredSignalMutex.h>
 #include <FEXCore/Utils/Event.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/set.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/unordered_map.h>
+#include <FEXCore/fextl/vector.h>
 #include <FEXHeaderUtils/Syscalls.h>
 #include <stdint.h>
 
-
 #include <atomic>
 #include <condition_variable>
 #include <functional>
 #include <istream>
-#include <map>
 #include <memory>
 #include <mutex>
 #include <shared_mutex>
 #include <stddef.h>
-#include <string>
-#include <unordered_map>
 #include <queue>
-#include <vector>
 
 namespace FEXCore {
 class CodeLoader;
@@ -75,8 +75,6 @@ namespace FEXCore::Context {
       // Context base class implementation.
       bool InitializeContext() override;
 
-      void DestroyContext() override;
-
       FEXCore::Core::InternalThreadState* InitCore(uint64_t InitialRIP, uint64_t StackPointer) override;
 
       void SetExitHandler(ExitHandler handler) override;
@@ -102,15 +100,11 @@ namespace FEXCore::Context {
 
       void SetCustomCPUBackendFactory(CustomCPUFactoryType Factory) override;
 
-      bool AddVirtualMemoryMapping(uint64_t VirtualAddress, uint64_t PhysicalAddress, uint64_t Size) override;
-
       HostFeatures GetHostFeatures() const override;
 
       void HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) override;
 
-      void RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required) override;
-      [[noreturn]] void HandleSignalHandlerReturn(bool RT) override ;
-      void RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required) override;
+      uint64_t RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState *Thread, uint64_t HostPC) override;
 
       /**
        * @brief Used to create FEX thread objects in preparation for creating a true OS thread. Does set a TID or PID.
@@ -158,40 +152,46 @@ namespace FEXCore::Context {
        * @param Thread The internal FEX thread state object
        */
       void DestroyThread(FEXCore::Core::InternalThreadState *Thread) override;
-      void CleanupAfterFork(FEXCore::Core::InternalThreadState *Thread) override;
+
+#ifndef _WIN32
+      void LockBeforeFork(FEXCore::Core::InternalThreadState *Thread) override;
+      void UnlockAfterFork(FEXCore::Core::InternalThreadState *Thread, bool Child) override;
+#endif
       void SetSignalDelegator(FEXCore::SignalDelegator *SignalDelegation) override;
       void SetSyscallHandler(FEXCore::HLE::SyscallHandler *Handler) override;
+
       FEXCore::CPUID::FunctionResults RunCPUIDFunction(uint32_t Function, uint32_t Leaf) override;
+      FEXCore::CPUID::XCRResults RunXCRFunction(uint32_t Function) override;
       FEXCore::CPUID::FunctionResults RunCPUIDFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) override;
 
-      FEXCore::IR::AOTIRCacheEntry *LoadAOTIRCacheEntry(const std::string& Name) override;
+      FEXCore::IR::AOTIRCacheEntry *LoadAOTIRCacheEntry(const fextl::string& Name) override;
       void UnloadAOTIRCacheEntry(FEXCore::IR::AOTIRCacheEntry *Entry) override;
 
-      void SetAOTIRLoader(std::function<int(const std::string&)> CacheReader) override {
-        IRCaptureCache.SetAOTIRLoader(CacheReader);
+      void SetAOTIRLoader(AOTIRLoaderCBFn CacheReader) override {
+        IRCaptureCache.SetAOTIRLoader(std::move(CacheReader));
       }
-      void SetAOTIRWriter(std::function<std::unique_ptr<std::ofstream>(const std::string&)> CacheWriter) override {
-        IRCaptureCache.SetAOTIRWriter(CacheWriter);
+      void SetAOTIRWriter(AOTIRWriterCBFn CacheWriter) override {
+        IRCaptureCache.SetAOTIRWriter(std::move(CacheWriter));
       }
-      void SetAOTIRRenamer(std::function<void(const std::string&)> CacheRenamer) override {
-        IRCaptureCache.SetAOTIRRenamer(CacheRenamer);
+      void SetAOTIRRenamer(AOTIRRenamerCBFn CacheRenamer) override {
+        IRCaptureCache.SetAOTIRRenamer(std::move(CacheRenamer));
       }
 
       void FinalizeAOTIRCache() override {
         IRCaptureCache.FinalizeAOTIRCache();
       }
-      void WriteFilesWithCode(std::function<void(const std::string& fileid, const std::string& filename)> Writer) override {
+      void WriteFilesWithCode(AOTIRCodeFileWriterFn Writer) override {
         IRCaptureCache.WriteFilesWithCode(Writer);
       }
-      void InvalidateGuestCodeRange(uint64_t Start, uint64_t Length) override;
-      void InvalidateGuestCodeRange(uint64_t Start, uint64_t Length, std::function<void(uint64_t start, uint64_t Length)> callback) override;
+      void InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length) override;
+      void InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length, CodeRangeInvalidationFn callback) override;
       void MarkMemoryShared() override;
 
-      void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, std::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) override;
+      void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, fextl::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) override;
       // returns false if a handler was already registered
-      CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator = nullptr, void *Data = nullptr) override;
+      CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void *Creator = nullptr, void *Data = nullptr) override;
 
-      void AppendThunkDefinitions(std::vector<FEXCore::IR::ThunkDefinition> const& Definitions) override;
+      void AppendThunkDefinitions(fextl::vector<FEXCore::IR::ThunkDefinition> const& Definitions) override;
 
     public:
     friend class FEXCore::HLE::SyscallHandler;
@@ -239,14 +239,13 @@ namespace FEXCore::Context {
       FEX_CONFIG_OPT(ParanoidTSO, PARANOIDTSO);
       FEX_CONFIG_OPT(CacheObjectCodeCompilation, CACHEOBJECTCODECOMPILATION);
       FEX_CONFIG_OPT(x87ReducedPrecision, X87REDUCEDPRECISION);
-      FEX_CONFIG_OPT(EnableAVX, ENABLEAVX);
     } Config;
 
     FEXCore::HostFeatures HostFeatures;
 
     std::mutex ThreadCreationMutex;
     FEXCore::Core::InternalThreadState* ParentThread{};
-    std::vector<FEXCore::Core::InternalThreadState*> Threads;
+    fextl::vector<FEXCore::Core::InternalThreadState*> Threads;
     std::atomic_bool CoreShuttingDown{false};
     bool NeedToCheckXID{true};
 
@@ -257,24 +256,23 @@ namespace FEXCore::Context {
     Event PauseWait;
     bool Running{};
 
-    std::shared_mutex CodeInvalidationMutex;
+    FEXCore::ForkableSharedMutex CodeInvalidationMutex;
 
     FEXCore::CPUIDEmu CPUID;
     FEXCore::HLE::SyscallHandler *SyscallHandler{};
     FEXCore::HLE::SourcecodeResolver *SourcecodeResolver{};
-    std::unique_ptr<FEXCore::ThunkHandler> ThunkHandler;
-    std::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
+    fextl::unique_ptr<FEXCore::ThunkHandler> ThunkHandler;
+    fextl::unique_ptr<FEXCore::CPU::Dispatcher> Dispatcher;
 
     CustomCPUFactoryType CustomCPUFactory;
     FEXCore::Context::ExitHandler CustomExitHandler;
 
 #ifdef BLOCKSTATS
-    std::unique_ptr<FEXCore::BlockSamplingData> BlockData;
+    fextl::unique_ptr<FEXCore::BlockSamplingData> BlockData;
 #endif
 
     SignalDelegator *SignalDelegation{};
     X86GeneratedCode X86CodeGen;
-    VDSOSigReturn VDSOPointers{};
 
     ContextImpl();
     ~ContextImpl();
@@ -294,7 +292,8 @@ namespace FEXCore::Context {
 
     template<auto Fn>
     static uint64_t ThreadExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame, uint64_t *record) {
-      FHU::ScopedSignalMaskWithSharedLock lk(static_cast<ContextImpl*>(Frame->Thread->CTX)->CodeInvalidationMutex);
+      auto Thread = Frame->Thread;
+      ScopedDeferredSignalWithForkableSharedLock lk(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);
 
       return Fn(Frame, record);
     }
@@ -305,20 +304,13 @@ namespace FEXCore::Context {
       auto Thread = Frame->Thread;
 
       LogMan::Throw::AFmt(Thread->ThreadManager.GetTID() == FHU::Syscalls::gettid(), "Must be called from owning thread {}, not {}", Thread->ThreadManager.GetTID(), FHU::Syscalls::gettid());
-
-      FHU::ScopedSignalMaskWithUniqueLock lk(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex);
+      ScopedDeferredSignalWithForkableUniqueLock lk(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);
 
       ThreadRemoveCodeEntry(Thread, GuestRIP);
     }
 
     void RemoveCustomIREntrypoint(uintptr_t Entrypoint);
 
-    // Debugger interface
-    uint64_t GetThreadCount() const;
-    FEXCore::Core::RuntimeStats *GetRuntimeStatsForThread(uint64_t Thread);
-    bool GetDebugDataForRIP(uint64_t RIP, FEXCore::Core::DebugData *Data);
-    bool FindHostCodeForRIP(uint64_t RIP, uint8_t **Code);
-
     struct GenerateIRResult {
       FEXCore::IR::IRListView* IRList;
       FEXCore::IR::RegisterAllocationData::UniquePtr RAData;
@@ -354,31 +346,57 @@ namespace FEXCore::Context {
 
     void CopyMemoryMapping(FEXCore::Core::InternalThreadState *ParentThread, FEXCore::Core::InternalThreadState *ChildThread);
 
-    std::vector<FEXCore::Core::InternalThreadState*>* GetThreads() { return &Threads; }
+    fextl::vector<FEXCore::Core::InternalThreadState*>* GetThreads() { return &Threads; }
 
     uint8_t GetGPRSize() const { return Config.Is64BitMode ? 8 : 4; }
 
     FEXCore::JITSymbols Symbols;
 
-    void SetVDSOSigReturn(const VDSOSigReturn &Pointers) override {
-      VDSOPointers = Pointers;
-      if (VDSOPointers.VDSO_kernel_sigreturn == nullptr) {
-        VDSOPointers.VDSO_kernel_sigreturn = reinterpret_cast<void*>(X86CodeGen.sigreturn_32);
+    void GetVDSOSigReturn(VDSOSigReturn *VDSOPointers) override {
+      if (VDSOPointers->VDSO_kernel_sigreturn == nullptr) {
+        VDSOPointers->VDSO_kernel_sigreturn = reinterpret_cast<void*>(X86CodeGen.sigreturn_32);
       }
 
-      if (VDSOPointers.VDSO_kernel_rt_sigreturn == nullptr) {
-        VDSOPointers.VDSO_kernel_rt_sigreturn = reinterpret_cast<void*>(X86CodeGen.rt_sigreturn_32);
+      if (VDSOPointers->VDSO_kernel_rt_sigreturn == nullptr) {
+        VDSOPointers->VDSO_kernel_rt_sigreturn = reinterpret_cast<void*>(X86CodeGen.rt_sigreturn_32);
       }
     }
 
-    FEXCore::Utils::PooledAllocatorMMap OpDispatcherAllocator;
-    FEXCore::Utils::PooledAllocatorMMap FrontendAllocator;
+    void IncrementIdleRefCount() override {
+      ++IdleWaitRefCount;
+    }
 
-    bool IsTSOEnabled() { return (IsMemoryShared || !Config.TSOAutoMigration) && Config.TSOEnabled; }
+    FEXCore::Utils::PooledAllocatorVirtual OpDispatcherAllocator;
+    FEXCore::Utils::PooledAllocatorVirtual FrontendAllocator;
+
+    // If Atomic-based TSO emulation is enabled or not.
+    bool IsAtomicTSOEnabled() const { return AtomicTSOEmulationEnabled; }
+
+    void SetHardwareTSOSupport(bool HardwareTSOSupported) override {
+      SupportsHardwareTSO = HardwareTSOSupported;
+      UpdateAtomicTSOEmulationConfig();
+    }
+
+    void EnableExitOnHLT() override { ExitOnHLT = true; }
+
+    bool ExitOnHLTEnabled() const { return ExitOnHLT; }
+
+    FEXCore::CPU::CPUBackendFeatures BackendFeatures;
 
   protected:
     void ClearCodeCache(FEXCore::Core::InternalThreadState *Thread);
 
+    void UpdateAtomicTSOEmulationConfig() {
+      if (SupportsHardwareTSO) {
+        // If the hardware supports TSO then we don't need to emulate it through atomics.
+        AtomicTSOEmulationEnabled = false;
+      }
+      else {
+        // Atomic TSO emulation only enabled if the config option is enabled.
+        AtomicTSOEmulationEnabled = (IsMemoryShared || !Config.TSOAutoMigration) && Config.TSOEnabled;
+      }
+    }
+
   private:
     /**
      * @brief Does some final thread initialization
@@ -406,18 +424,20 @@ namespace FEXCore::Context {
 
     // Entry Cache
     std::mutex ExitMutex;
-    std::unique_ptr<GdbServer> DebugServer;
+    fextl::unique_ptr<GdbServer> DebugServer;
 
     IR::AOTIRCaptureCache IRCaptureCache;
-    std::unique_ptr<FEXCore::CodeSerialize::CodeObjectSerializeService> CodeObjectCacheService;
+    fextl::unique_ptr<FEXCore::CodeSerialize::CodeObjectSerializeService> CodeObjectCacheService;
 
     bool StartPaused = false;
     bool IsMemoryShared = false;
+    bool SupportsHardwareTSO = false;
+    bool AtomicTSOEmulationEnabled = true;
+    bool ExitOnHLT = false;
     FEX_CONFIG_OPT(AppFilename, APP_FILENAME);
 
     std::shared_mutex CustomIRMutex;
-    std::unordered_map<uint64_t, std::tuple<std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)>, void *, void *>> CustomIRHandlers;
-    FEXCore::CPU::CPUBackendFeatures BackendFeatures;
+    fextl::unordered_map<uint64_t, std::tuple<CustomIREntrypointHandler, void *, void *>> CustomIRHandlers;
     FEXCore::CPU::DispatcherConfig DispatcherConfig;
   };
 

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp

@@ -1,4 +1,5 @@
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
+#include "FEXCore/Utils/AllocatorHooks.h"
 #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Context/Context.h"
@@ -19,18 +20,162 @@
 #include <utility>
 
 namespace FEXCore::CPU {
+// Register x18 is unused in the current configuration.
+// This is due to it being a platform register on wine platforms.
+// TODO: Allow x18 register allocation in the future to gain one more register.
+
+namespace x64 {
+  // All but x19 and x29 are caller saved
+  constexpr std::array<FEXCore::ARMEmitter::Register, 16> SRA = {
+    FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5,
+    FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7,
+    FEXCore::ARMEmitter::Reg::r8, FEXCore::ARMEmitter::Reg::r9,
+    FEXCore::ARMEmitter::Reg::r10, FEXCore::ARMEmitter::Reg::r11,
+    FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r13,
+    FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15,
+    FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17,
+    FEXCore::ARMEmitter::Reg::r19, FEXCore::ARMEmitter::Reg::r29
+  };
+
+  constexpr std::array<FEXCore::ARMEmitter::Register, 9> RA = {
+    // All these callee saved
+    FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21,
+    FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23,
+    FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25,
+    FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27,
+    FEXCore::ARMEmitter::Reg::r30,
+  };
+
+  constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 4> RAPair = {{
+    {FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21},
+    {FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23},
+    {FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25},
+    {FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27},
+  }};
+
+  // All are caller saved
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 16> SRAFPR = {
+    FEXCore::ARMEmitter::VReg::v16, FEXCore::ARMEmitter::VReg::v17,
+    FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19,
+    FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21,
+    FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23,
+    FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25,
+    FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27,
+    FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29,
+    FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31
+  };
+
+  //  v8..v15 = (lower 64bits) Callee saved
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 12> RAFPR = {
+    // v0 ~ v3 are used as temps.
+    // FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1,
+    // FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
+
+    FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
+    FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
+    FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9,
+    FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11,
+    FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
+    FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+  };
+}
+
+namespace x32 {
+  // All but x19 and x29 are caller saved
+  constexpr std::array<FEXCore::ARMEmitter::Register, 8> SRA = {
+    FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5,
+    FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7,
+    FEXCore::ARMEmitter::Reg::r8, FEXCore::ARMEmitter::Reg::r9,
+    FEXCore::ARMEmitter::Reg::r10, FEXCore::ARMEmitter::Reg::r11,
+  };
+
+  constexpr std::array<FEXCore::ARMEmitter::Register, 17> RA = {
+    // All these callee saved
+    FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21,
+    FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23,
+    FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25,
+    FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27,
+
+    // Registers only available on 32-bit
+    // All these are caller saved (except for r19).
+    FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r13,
+    FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15,
+    FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17,
+    FEXCore::ARMEmitter::Reg::r29, FEXCore::ARMEmitter::Reg::r30,
+
+    FEXCore::ARMEmitter::Reg::r19,
+  };
+
+  constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 8> RAPair = {{
+    {FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21},
+    {FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23},
+    {FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25},
+    {FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27},
+
+    {FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r13},
+    {FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r15},
+    {FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r17},
+    {FEXCore::ARMEmitter::Reg::r29, FEXCore::ARMEmitter::Reg::r30},
+  }};
+
+  // All are caller saved
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 8> SRAFPR = {
+    FEXCore::ARMEmitter::VReg::v16, FEXCore::ARMEmitter::VReg::v17,
+    FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19,
+    FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21,
+    FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23,
+  };
+
+  //  v8..v15 = (lower 64bits) Callee saved
+  constexpr std::array<FEXCore::ARMEmitter::VRegister, 20> RAFPR = {
+    // v0 ~ v3 are used as temps.
+    // FEXCore::ARMEmitter::VReg::v0, FEXCore::ARMEmitter::VReg::v1,
+    // FEXCore::ARMEmitter::VReg::v2, FEXCore::ARMEmitter::VReg::v3,
+
+    FEXCore::ARMEmitter::VReg::v4, FEXCore::ARMEmitter::VReg::v5,
+    FEXCore::ARMEmitter::VReg::v6, FEXCore::ARMEmitter::VReg::v7,
+    FEXCore::ARMEmitter::VReg::v8, FEXCore::ARMEmitter::VReg::v9,
+    FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11,
+    FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13,
+    FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15,
+
+    FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25,
+    FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27,
+    FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29,
+    FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31
+  };
+}
 
 // We want vixl to not allocate a default buffer. Jit and dispatcher will manually create one.
 Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl *ctx, size_t size)
-  : Emitter(size ? (uint8_t*)FEXCore::Allocator::mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0) : nullptr, size)
+  : Emitter(size ? (uint8_t*)FEXCore::Allocator::VirtualAlloc(size, true) : nullptr, size)
   , EmitterCTX {ctx} {
   CPU.SetUp();
+
+  // Number of register available is dependent on what operating mode the proccess is in.
+  if (EmitterCTX->Config.Is64BitMode()) {
+    StaticRegisters = x64::SRA;
+    GeneralRegisters = x64::RA;
+    GeneralPairRegisters = x64::RAPair;
+    StaticFPRegisters = x64::SRAFPR;
+    GeneralFPRegisters = x64::RAFPR;
+  }
+  else {
+    ConfiguredDynamicRegisterBase = std::span(x32::RA.begin() + 8, 8);
+
+    StaticRegisters = x32::SRA;
+    GeneralRegisters = x32::RA;
+    GeneralPairRegisters = x32::RAPair;
+
+    StaticFPRegisters = x32::SRAFPR;
+    GeneralFPRegisters = x32::RAFPR;
+  }
 }
 
 Arm64Emitter::~Arm64Emitter() {
   auto BufferSize = GetBufferSize();
   if (BufferSize) {
-    FEXCore::Allocator::munmap(GetBufferBase(), BufferSize);
+    FEXCore::Allocator::VirtualFree(GetBufferBase(), BufferSize);
   }
 }
 
@@ -47,6 +192,23 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
     return;
   }
 
+  if ((Constant >> 32) == 0) {
+    // If the upper 32-bits is all zero, we can now switch to a 32-bit move.
+    s = ARMEmitter::Size::i32Bit;
+    Is64Bit = false;
+    Segments = 2;
+  }
+
+  // If this can be loaded with a mov bitmask.
+  const auto IsImm = vixl::aarch64::Assembler::IsImmLogical(Constant, RegSizeInBits(s));
+  if (IsImm) {
+    orr(s, Reg, ARMEmitter::Reg::zr, Constant);
+    if (NOPPad) {
+      nop(); nop(); nop();
+    }
+    return;
+  }
+
   int NumMoves = 1;
   int RequiredMoveSegments{};
 
@@ -112,7 +274,11 @@ void Arm64Emitter::LoadConstant(ARMEmitter::Size s, ARMEmitter::Register Reg, ui
 void Arm64Emitter::PushCalleeSavedRegisters() {
   // We need to save pairs of registers
   // We save r19-r30
-  const std::array<std::pair<ARMEmitter::XRegister, ARMEmitter::XRegister>, 6> CalleeSaved = {{
+  const fextl::vector<std::pair<ARMEmitter::XRegister, ARMEmitter::XRegister>> CalleeSaved = {{
+#ifdef _WIN32
+    // Platform register, Just save it twice to make logic easy.
+    {ARMEmitter::XReg::x18, ARMEmitter::XReg::x18},
+#endif
     {ARMEmitter::XReg::x19, ARMEmitter::XReg::x20},
     {ARMEmitter::XReg::x21, ARMEmitter::XReg::x22},
     {ARMEmitter::XReg::x23, ARMEmitter::XReg::x24},
@@ -176,13 +342,17 @@ void Arm64Emitter::PopCalleeSavedRegisters() {
         32);
   }
 
-  const std::array<std::pair<ARMEmitter::XRegister, ARMEmitter::XRegister>, 6> CalleeSaved = {{
+  const fextl::vector<std::pair<ARMEmitter::XRegister, ARMEmitter::XRegister>> CalleeSaved = {{
     {ARMEmitter::XReg::x29, ARMEmitter::XReg::x30},
     {ARMEmitter::XReg::x27, ARMEmitter::XReg::x28},
     {ARMEmitter::XReg::x25, ARMEmitter::XReg::x26},
     {ARMEmitter::XReg::x23, ARMEmitter::XReg::x24},
     {ARMEmitter::XReg::x21, ARMEmitter::XReg::x22},
     {ARMEmitter::XReg::x19, ARMEmitter::XReg::x20},
+#ifdef _WIN32
+    // Platform register.
+    {ARMEmitter::XReg::x18, ARMEmitter::XReg::zr},
+#endif
   }};
 
   for (auto &RegPair : CalleeSaved) {
@@ -190,14 +360,14 @@ void Arm64Emitter::PopCalleeSavedRegisters() {
   }
 }
 
-void Arm64Emitter::SpillStaticRegs(bool FPRs, uint32_t GPRSpillMask, uint32_t FPRSpillMask) {
+void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FPRs, uint32_t GPRSpillMask, uint32_t FPRSpillMask) {
   if (!StaticRegisterAllocation()) {
     return;
   }
 
-  for (size_t i = 0; i < SRA64.size(); i+=2) {
-    auto Reg1 = SRA64[i];
-    auto Reg2 = SRA64[i+1];
+  for (size_t i = 0; i < StaticRegisters.size(); i+=2) {
+    auto Reg1 = StaticRegisters[i];
+    auto Reg2 = StaticRegisters[i+1];
     if (((1U << Reg1.Idx()) & GPRSpillMask) &&
         ((1U << Reg2.Idx()) & GPRSpillMask)) {
       stp<ARMEmitter::IndexType::OFFSET>(Reg1.X(), Reg2.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i]));
@@ -212,8 +382,8 @@ void Arm64Emitter::SpillStaticRegs(bool FPRs, uint32_t GPRSpillMask, uint32_t FP
 
   if (FPRs) {
     if (EmitterCTX->HostFeatures.SupportsAVX) {
-      for (size_t i = 0; i < SRAFPR.size(); i++) {
-        const auto Reg = SRAFPR[i];
+      for (size_t i = 0; i < StaticFPRegisters.size(); i++) {
+        const auto Reg = StaticFPRegisters[i];
 
         if (((1U << Reg.Idx()) & FPRSpillMask) != 0) {
           mov(ARMEmitter::Size::i64Bit, TMP4.R(), offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
@@ -223,22 +393,20 @@ void Arm64Emitter::SpillStaticRegs(bool FPRs, uint32_t GPRSpillMask, uint32_t FP
     } else {
       if (GPRSpillMask && FPRSpillMask == ~0U) {
         // Optimize the common case where we can spill four registers per instruction
-        auto TmpReg = SRA64[FindFirstSetBit(GPRSpillMask)];
-
         // Load the sse offset in to the temporary register
         add(ARMEmitter::Size::i64Bit, TmpReg, STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[0][0]));
-        for (size_t i = 0; i < SRAFPR.size(); i += 4) {
-          const auto Reg1 = SRAFPR[i];
-          const auto Reg2 = SRAFPR[i + 1];
-          const auto Reg3 = SRAFPR[i + 2];
-          const auto Reg4 = SRAFPR[i + 3];
+        for (size_t i = 0; i < StaticFPRegisters.size(); i += 4) {
+          const auto Reg1 = StaticFPRegisters[i];
+          const auto Reg2 = StaticFPRegisters[i + 1];
+          const auto Reg3 = StaticFPRegisters[i + 2];
+          const auto Reg4 = StaticFPRegisters[i + 3];
           st1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), TmpReg, 64);
         }
       }
       else {
-        for (size_t i = 0; i < SRAFPR.size(); i += 2) {
-          const auto Reg1 = SRAFPR[i];
-          const auto Reg2 = SRAFPR[i + 1];
+        for (size_t i = 0; i < StaticFPRegisters.size(); i += 2) {
+          const auto Reg1 = StaticFPRegisters[i];
+          const auto Reg2 = StaticFPRegisters[i + 1];
 
           if (((1U << Reg1.Idx()) & FPRSpillMask) &&
               ((1U << Reg2.Idx()) & FPRSpillMask)) {
@@ -270,8 +438,8 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
       ptrue<ARMEmitter::SubRegSize::i8Bit>(PRED_TMP_16B, ARMEmitter::PredicatePattern::SVE_VL16);
       ptrue<ARMEmitter::SubRegSize::i8Bit>(PRED_TMP_32B, ARMEmitter::PredicatePattern::SVE_VL32);
 
-      for (size_t i = 0; i < SRAFPR.size(); i++) {
-        const auto Reg = SRAFPR[i];
+      for (size_t i = 0; i < StaticFPRegisters.size(); i++) {
+        const auto Reg = StaticFPRegisters[i];
         if (((1U << Reg.Idx()) & FPRFillMask) != 0) {
           mov(ARMEmitter::Size::i64Bit, TMP4.R(), offsetof(Core::CpuStateFrame, State.xmm.avx.data[i][0]));
           ld1b<ARMEmitter::SubRegSize::i8Bit>(Reg.Z(), PRED_TMP_32B.Zeroing(), STATE.R(), TMP4.R());
@@ -281,22 +449,22 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
       if (GPRFillMask && FPRFillMask == ~0U) {
         // Optimize the common case where we can fill four registers per instruction.
         // Use one of the filling static registers before we fill it.
-        auto TmpReg = SRA64[FindFirstSetBit(GPRFillMask)];
+        auto TmpReg = StaticRegisters[FindFirstSetBit(GPRFillMask)];
 
         // Load the sse offset in to the temporary register
         add(ARMEmitter::Size::i64Bit, TmpReg, STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[0][0]));
-        for (size_t i = 0; i < SRAFPR.size(); i += 4) {
-          const auto Reg1 = SRAFPR[i];
-          const auto Reg2 = SRAFPR[i + 1];
-          const auto Reg3 = SRAFPR[i + 2];
-          const auto Reg4 = SRAFPR[i + 3];
+        for (size_t i = 0; i < StaticFPRegisters.size(); i += 4) {
+          const auto Reg1 = StaticFPRegisters[i];
+          const auto Reg2 = StaticFPRegisters[i + 1];
+          const auto Reg3 = StaticFPRegisters[i + 2];
+          const auto Reg4 = StaticFPRegisters[i + 3];
           ld1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), TmpReg, 64);
         }
       }
       else {
-        for (size_t i = 0; i < SRAFPR.size(); i += 2) {
-          const auto Reg1 = SRAFPR[i];
-          const auto Reg2 = SRAFPR[i + 1];
+        for (size_t i = 0; i < StaticFPRegisters.size(); i += 2) {
+          const auto Reg1 = StaticFPRegisters[i];
+          const auto Reg2 = StaticFPRegisters[i + 1];
 
           if (((1U << Reg1.Idx()) & FPRFillMask) &&
               ((1U << Reg2.Idx()) & FPRFillMask)) {
@@ -313,9 +481,9 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
     }
   }
 
-  for (size_t i = 0; i < SRA64.size(); i+=2) {
-    auto Reg1 = SRA64[i];
-    auto Reg2 = SRA64[i+1];
+  for (size_t i = 0; i < StaticRegisters.size(); i+=2) {
+    auto Reg1 = StaticRegisters[i];
+    auto Reg2 = StaticRegisters[i+1];
     if (((1U << Reg1.Idx()) & GPRFillMask) &&
         ((1U << Reg2.Idx()) & GPRFillMask)) {
       ldp<ARMEmitter::IndexType::OFFSET>(Reg1.X(), Reg2.X(), STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.gregs[i]));
@@ -331,10 +499,10 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
 
 void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
   const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
-  const auto GPRSize = 1 * Core::CPUState::GPR_REG_SIZE;
+  const auto GPRSize = (ConfiguredDynamicRegisterBase.size() + 1) * Core::CPUState::GPR_REG_SIZE;
   const auto FPRRegSize = CanUseSVE ? Core::CPUState::XMM_AVX_REG_SIZE
                                     : Core::CPUState::XMM_SSE_REG_SIZE;
-  const auto FPRSize = RAFPR.size() * FPRRegSize;
+  const auto FPRSize = GeneralFPRegisters.size() * FPRRegSize;
   const uint64_t SPOffset = AlignUp(GPRSize + FPRSize, 16);
 
   sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, SPOffset);
@@ -343,25 +511,31 @@ void Arm64Emitter::PushDynamicRegsAndLR(FEXCore::ARMEmitter::Register TmpReg) {
   add(ARMEmitter::Size::i64Bit, TmpReg, ARMEmitter::Reg::rsp, 0);
 
   if (CanUseSVE) {
-    for (size_t i = 0; i < RAFPR.size(); i += 4) {
-      const auto Reg1 = RAFPR[i];
-      const auto Reg2 = RAFPR[i + 1];
-      const auto Reg3 = RAFPR[i + 2];
-      const auto Reg4 = RAFPR[i + 3];
+    for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
+      const auto Reg1 = GeneralFPRegisters[i];
+      const auto Reg2 = GeneralFPRegisters[i + 1];
+      const auto Reg3 = GeneralFPRegisters[i + 2];
+      const auto Reg4 = GeneralFPRegisters[i + 3];
       st4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B, TmpReg, 0);
       add(ARMEmitter::Size::i64Bit, TmpReg, TmpReg, 32 * 4);
     }
   } else {
-    static_assert(RAFPR.size() % 4 == 0, "Needs to have multiple of 4 FPRs for RA");
-    for (size_t i = 0; i < RAFPR.size(); i += 4) {
-      const auto Reg1 = RAFPR[i];
-      const auto Reg2 = RAFPR[i + 1];
-      const auto Reg3 = RAFPR[i + 2];
-      const auto Reg4 = RAFPR[i + 3];
+    LOGMAN_THROW_A_FMT(GeneralFPRegisters.size() % 4 == 0, "Needs to have multiple of 4 FPRs for RA");
+    for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
+      const auto Reg1 = GeneralFPRegisters[i];
+      const auto Reg2 = GeneralFPRegisters[i + 1];
+      const auto Reg3 = GeneralFPRegisters[i + 2];
+      const auto Reg4 = GeneralFPRegisters[i + 3];
       st1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), TmpReg, 64);
     }
   }
 
+  for (size_t i = 0; i < ConfiguredDynamicRegisterBase.size(); i += 2) {
+    const auto Reg1 = ConfiguredDynamicRegisterBase[i];
+    const auto Reg2 = ConfiguredDynamicRegisterBase[i + 1];
+    stp<ARMEmitter::IndexType::POST>(Reg1.X(), Reg2.X(), TmpReg, 16);
+  }
+
   str(ARMEmitter::XReg::lr, TmpReg, 0);
 }
 
@@ -369,24 +543,30 @@ void Arm64Emitter::PopDynamicRegsAndLR() {
   const auto CanUseSVE = EmitterCTX->HostFeatures.SupportsAVX;
 
   if (CanUseSVE) {
-    for (size_t i = 0; i < RAFPR.size(); i += 4) {
-      const auto Reg1 = RAFPR[i];
-      const auto Reg2 = RAFPR[i + 1];
-      const auto Reg3 = RAFPR[i + 2];
-      const auto Reg4 = RAFPR[i + 3];
+    for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
+      const auto Reg1 = GeneralFPRegisters[i];
+      const auto Reg2 = GeneralFPRegisters[i + 1];
+      const auto Reg3 = GeneralFPRegisters[i + 2];
+      const auto Reg4 = GeneralFPRegisters[i + 3];
       ld4b(Reg1.Z(), Reg2.Z(), Reg3.Z(), Reg4.Z(), PRED_TMP_32B.Zeroing(), ARMEmitter::Reg::rsp);
       add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 32 * 4);
     }
   } else {
-    for (size_t i = 0; i < RAFPR.size(); i += 4) {
-      const auto Reg1 = RAFPR[i];
-      const auto Reg2 = RAFPR[i + 1];
-      const auto Reg3 = RAFPR[i + 2];
-      const auto Reg4 = RAFPR[i + 3];
+    for (size_t i = 0; i < GeneralFPRegisters.size(); i += 4) {
+      const auto Reg1 = GeneralFPRegisters[i];
+      const auto Reg2 = GeneralFPRegisters[i + 1];
+      const auto Reg3 = GeneralFPRegisters[i + 2];
+      const auto Reg4 = GeneralFPRegisters[i + 3];
       ld1<ARMEmitter::SubRegSize::i64Bit>(Reg1.Q(), Reg2.Q(), Reg3.Q(), Reg4.Q(), ARMEmitter::Reg::rsp, 64);
     }
   }
 
+  for (size_t i = 0; i < ConfiguredDynamicRegisterBase.size(); i += 2) {
+    const auto Reg1 = ConfiguredDynamicRegisterBase[i];
+    const auto Reg2 = ConfiguredDynamicRegisterBase[i + 1];
+    ldp<ARMEmitter::IndexType::POST>(Reg1.X(), Reg2.X(), ARMEmitter::Reg::rsp, 16);
+  }
+
   ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
 }
 

External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h

@@ -26,39 +26,9 @@
 #include <cstddef>
 #include <cstdint>
 #include <utility>
+#include <span>
 
 namespace FEXCore::CPU {
-// All but x29 are caller saved
-constexpr std::array<FEXCore::ARMEmitter::Register, 16> SRA64 = {
-  FEXCore::ARMEmitter::Reg::r4, FEXCore::ARMEmitter::Reg::r5, FEXCore::ARMEmitter::Reg::r6, FEXCore::ARMEmitter::Reg::r7, FEXCore::ARMEmitter::Reg::r8, FEXCore::ARMEmitter::Reg::r9, FEXCore::ARMEmitter::Reg::r10, FEXCore::ARMEmitter::Reg::r11,
-  FEXCore::ARMEmitter::Reg::r12, FEXCore::ARMEmitter::Reg::r18, FEXCore::ARMEmitter::Reg::r17, FEXCore::ARMEmitter::Reg::r16, FEXCore::ARMEmitter::Reg::r15, FEXCore::ARMEmitter::Reg::r14, FEXCore::ARMEmitter::Reg::r13, FEXCore::ARMEmitter::Reg::r29
-};
-
-// All are callee saved
-constexpr std::array<FEXCore::ARMEmitter::Register, 9> RA64 = {
-  FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21, FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23, FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25, FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27,
-  FEXCore::ARMEmitter::Reg::r19
-};
-
-constexpr std::array<std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>, 4>  RA64Pair = {{
-  {FEXCore::ARMEmitter::Reg::r20, FEXCore::ARMEmitter::Reg::r21},
-  {FEXCore::ARMEmitter::Reg::r22, FEXCore::ARMEmitter::Reg::r23},
-  {FEXCore::ARMEmitter::Reg::r24, FEXCore::ARMEmitter::Reg::r25},
-  {FEXCore::ARMEmitter::Reg::r26, FEXCore::ARMEmitter::Reg::r27},
-}};
-
-// All are caller saved
-constexpr std::array<FEXCore::ARMEmitter::VRegister, 16> SRAFPR = {
-  FEXCore::ARMEmitter::VReg::v16, FEXCore::ARMEmitter::VReg::v17, FEXCore::ARMEmitter::VReg::v18, FEXCore::ARMEmitter::VReg::v19, FEXCore::ARMEmitter::VReg::v20, FEXCore::ARMEmitter::VReg::v21, FEXCore::ARMEmitter::VReg::v22, FEXCore::ARMEmitter::VReg::v23,
-  FEXCore::ARMEmitter::VReg::v24, FEXCore::ARMEmitter::VReg::v25, FEXCore::ARMEmitter::VReg::v26, FEXCore::ARMEmitter::VReg::v27, FEXCore::ARMEmitter::VReg::v28, FEXCore::ARMEmitter::VReg::v29, FEXCore::ARMEmitter::VReg::v30, FEXCore::ARMEmitter::VReg::v31
-};
-
-//  v8..v15 = (lower 64bits) Callee saved
-constexpr std::array<FEXCore::ARMEmitter::VRegister, 12> RAFPR = {
-/*FEXCore::ARMEmitter::VReg::v0,  FEXCore::ARMEmitter::VReg::v1,  FEXCore::ARMEmitter::VReg::v2,  FEXCore::ARMEmitter::VReg::v3,*/FEXCore::ARMEmitter::VReg::v4,  FEXCore::ARMEmitter::VReg::v5,  FEXCore::ARMEmitter::VReg::v6,  FEXCore::ARMEmitter::VReg::v7,  // FEXCore::ARMEmitter::VReg::v0 ~ FEXCore::ARMEmitter::VReg::v3 are used as temps
-  FEXCore::ARMEmitter::VReg::v8,  FEXCore::ARMEmitter::VReg::v9,  FEXCore::ARMEmitter::VReg::v10, FEXCore::ARMEmitter::VReg::v11, FEXCore::ARMEmitter::VReg::v12, FEXCore::ARMEmitter::VReg::v13, FEXCore::ARMEmitter::VReg::v14, FEXCore::ARMEmitter::VReg::v15
-};
-
 // Contains the address to the currently available CPU state
 constexpr auto STATE = FEXCore::ARMEmitter::XReg::x28;
 
@@ -90,16 +60,40 @@ protected:
 
   FEXCore::Context::ContextImpl *EmitterCTX;
   vixl::aarch64::CPU CPU;
+
+  std::span<const FEXCore::ARMEmitter::Register> ConfiguredDynamicRegisterBase{};
+  std::span<const FEXCore::ARMEmitter::Register> StaticRegisters{};
+  std::span<const FEXCore::ARMEmitter::Register> GeneralRegisters{};
+  std::span<const std::pair<FEXCore::ARMEmitter::Register, FEXCore::ARMEmitter::Register>> GeneralPairRegisters{};
+  std::span<const FEXCore::ARMEmitter::VRegister> StaticFPRegisters{};
+  std::span<const FEXCore::ARMEmitter::VRegister> GeneralFPRegisters{};
+
+  /**
+   * @name Register Allocation
+   * @{ */
+  constexpr static uint32_t RegisterClasses = 6;
+
+  constexpr static uint64_t GPRBase = (0ULL << 32);
+  constexpr static uint64_t FPRBase = (1ULL << 32);
+  constexpr static uint64_t GPRPairBase = (2ULL << 32);
+
+  /**  @} */
+
+  constexpr static uint8_t RA_32 = 0;
+  constexpr static uint8_t RA_64 = 1;
+  constexpr static uint8_t RA_FPR = 2;
+
   void LoadConstant(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register Reg, uint64_t Constant, bool NOPPad = false);
 
 
   // NOTE: These functions WILL clobber the register TMP4 if AVX support is enabled
   //       and FPRs are being spilled or filled. If only GPRs are spilled/filled, then
   //       TMP4 is left alone.
-  void SpillStaticRegs(bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
+  void SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FPRs = true, uint32_t GPRSpillMask = ~0U, uint32_t FPRSpillMask = ~0U);
   void FillStaticRegs(bool FPRs = true, uint32_t GPRFillMask = ~0U, uint32_t FPRFillMask = ~0U);
 
-  static constexpr uint32_t CALLER_GPR_MASK = 0b0011'1111'1111'1111'1111;
+  // Register 0-18 + 29 + 30 are caller saved
+  static constexpr uint32_t CALLER_GPR_MASK = 0b0110'0000'0000'0111'1111'1111'1111'1111U;
 
   // This isn't technically true because the lower 64-bits of v8..v15 are callee saved
   // We can't guarantee only the lower 64bits are used so flush everything
@@ -181,6 +175,7 @@ protected:
 #endif
 #ifdef VIXL_DISASSEMBLER
   vixl::aarch64::PrintDisassembler Disasm {stderr};
+  FEX_CONFIG_OPT(Disassemble, DISASSEMBLE);
 #endif
   FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
 };

External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ALUOps.inl

@@ -129,7 +129,9 @@ public:
     constexpr uint32_t Op = 0b0011'0001'0 << 23;
     DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
   }
-
+  void cmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
+    adds(s, FEXCore::ARMEmitter::Reg::zr, rn, Imm, LSL12);
+  }
   void sub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t Imm, bool LSL12 = false) {
     constexpr uint32_t Op = 0b0101'0001'0 << 23;
     DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
@@ -145,6 +147,27 @@ public:
     DataProcessing_AddSub_Imm(Op, s, rd, rn, Imm, LSL12);
   }
 
+  // Min/max immediate
+  void smax(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, int64_t Imm) {
+    LOGMAN_THROW_A_FMT(Imm >= -128 && Imm <= 127, "{} Immediate too large", __func__);
+    MinMaxImmediate(0b0000, s, rd, rn, Imm);
+  }
+
+  void umax(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) {
+    LOGMAN_THROW_A_FMT(Imm <= 255, "{} Immediate too large", __func__);
+    MinMaxImmediate(0b0001, s, rd, rn, Imm);
+  }
+
+  void smin(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, int64_t Imm) {
+    LOGMAN_THROW_A_FMT(Imm >= -128 && Imm <= 127, "{} Immediate too large", __func__);
+    MinMaxImmediate(0b0010, s, rd, rn, Imm);
+  }
+
+  void umin(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) {
+    LOGMAN_THROW_A_FMT(Imm <= 255, "{} Immediate too large", __func__);
+    MinMaxImmediate(0b0011, s, rd, rn, Imm);
+  }
+
   // Logical immediate
   void and_(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) {
     uint32_t n, immr, imms;
@@ -198,6 +221,10 @@ public:
     eor(s, rd, rn, n, immr, imms);
   }
 
+  void tst(ARMEmitter::Size s, Register rn, uint64_t imm) {
+    ands(s, Reg::zr, rn, imm);
+  }
+
   // Move wide immediate
   void movn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset = 0) {
     LOGMAN_THROW_A_FMT((Imm & 0xFFFF0000U) == 0, "Upper bits of move wide not valid");
@@ -265,6 +292,9 @@ public:
     LOGMAN_THROW_A_FMT((lsb + width) <= RegSizeInBits(s), "Tried to sbfx a region larger than the register");
     sbfm(s, rd, rn, lsb, lsb + width - 1);
   }
+  void sbfiz(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) {
+    xbfiz_helper(true, s, rd, rn, lsb, width);
+  }
   void asr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t shift) {
     LOGMAN_THROW_A_FMT(shift <= RegSizeInBits(s), "Tried to asr a region larger than the register");
     sbfm(s, rd, rn, shift, RegSizeInBits(s) - 1);
@@ -285,6 +315,10 @@ public:
     DataProcessing_Logical_Imm(Op, s, rd, rn, s == ARMEmitter::Size::i64Bit, immr, imms);
   }
 
+  void ubfiz(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) {
+    xbfiz_helper(false, s, rd, rn, lsb, width);
+  }
+
   void lsl(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t shift) {
     const auto RegSize = RegSizeInBits(s);
     LOGMAN_THROW_A_FMT(shift < RegSize, "Tried to lsl a region larger than the register");
@@ -303,10 +337,23 @@ public:
 
   void bfi(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t lsb, uint32_t width) {
     const auto RegSize = RegSizeInBits(s);
-    LOGMAN_THROW_A_FMT(width > 0, "bfi needs width > 0");
-    LOGMAN_THROW_A_FMT((lsb + width) <= RegSize, "Tried to bfi a region larger than the register");
+    LOGMAN_THROW_A_FMT(width > 0, "bfc/bfi needs width > 0");
+    LOGMAN_THROW_A_FMT((lsb + width) <= RegSize, "Tried to bfc/bfi a region larger than the register");
     bfm(s, rd, rn, (RegSize - lsb) & (RegSize - 1), width - 1);
   }
+  void bfc(ARMEmitter::Size s, Register rd, uint32_t lsb, uint32_t width) {
+    bfi(s, rd, Reg::zr, lsb, width);
+  }
+  void bfxil(ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) {
+    [[maybe_unused]] const auto reg_size_bits = RegSizeInBits(s);
+    const auto lsb_p_width = lsb + width;
+
+    LOGMAN_THROW_A_FMT(width >= 1, "bfxil needs width >= 1");
+    LOGMAN_THROW_A_FMT(lsb_p_width <= reg_size_bits, "bfxil lsb + width ({}) must be <= {}. lsb={}, width={}",
+                       lsb_p_width, reg_size_bits, lsb, width);
+
+    bfm(s, rd, rn, lsb, lsb_p_width - 1);
+  }
 
   // Extract
   void extr(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, uint32_t Imm) {
@@ -381,6 +428,26 @@ public:
                         (0b0101'10U << 10);
     DataProcessing_2Source(Op, ARMEmitter::Size::i32Bit, rd, rn, rm);
   }
+  void smax(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0110'00U << 10);
+    DataProcessing_2Source(Op, s, rd, rn, rm);
+  }
+  void umax(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0110'01U << 10);
+    DataProcessing_2Source(Op, s, rd, rn, rm);
+  }
+  void smin(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0110'10U << 10);
+    DataProcessing_2Source(Op, s, rd, rn, rm);
+  }
+  void umin(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm) {
+    constexpr uint32_t Op = (0b001'1010'110U << 21) |
+                        (0b0110'11U << 10);
+    DataProcessing_2Source(Op, s, rd, rn, rm);
+  }
   void subp(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm) {
     constexpr uint32_t Op = (0b001'1010'110U << 21) |
                         (0b0000'00U << 10);
@@ -467,7 +534,24 @@ public:
                         (s == ARMEmitter::Size::i64Bit ? (1U << 10) : 0);
     DataProcessing_1Source(Op, s, rd, rn);
   }
-
+  void ctz(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    constexpr uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0001'10U << 10);
+    DataProcessing_1Source(Op, s, rd, rn);
+  }
+  void cnt(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    constexpr uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0001'11U << 10);
+    DataProcessing_1Source(Op, s, rd, rn);
+  }
+  void abs(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn) {
+    constexpr uint32_t Op = (0b101'1010'110U << 21) |
+                        (0b0'0000U << 16) |
+                        (0b0010'00U << 10);
+    DataProcessing_1Source(Op, s, rd, rn);
+  }
 
   // TODO: PAUTH
 
@@ -506,6 +590,9 @@ public:
     constexpr uint32_t Op = 0b010'1010'000U << 21;
     DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
   }
+  void tst(ARMEmitter::Size s, Register rn, Register rm, ShiftType shift = ShiftType::LSL, uint32_t amt = 0) {
+    ands(s, Reg::zr, rn, rm, shift, amt);
+  }
 
   void orn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
     constexpr uint32_t Op = 0b010'1010'001U << 21;
@@ -527,6 +614,9 @@ public:
   void adds(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
     adds(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
   }
+  void cmn(FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    adds(ARMEmitter::Size::i64Bit, FEXCore::ARMEmitter::XReg::zr, rn.R(), rm.R(), Shift, amt);
+  }
   void sub(FEXCore::ARMEmitter::XRegister rd, FEXCore::ARMEmitter::XRegister rn, FEXCore::ARMEmitter::XRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
     sub(ARMEmitter::Size::i64Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
   }
@@ -549,6 +639,9 @@ public:
   void adds(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
     adds(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
   }
+  void cmn(FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    adds(ARMEmitter::Size::i32Bit, FEXCore::ARMEmitter::WReg::zr, rn.R(), rm.R(), Shift, amt);
+  }
   void sub(FEXCore::ARMEmitter::WRegister rd, FEXCore::ARMEmitter::WRegister rn, FEXCore::ARMEmitter::WRegister rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
     sub(ARMEmitter::Size::i32Bit, rd.R(), rn.R(), rm.R(), Shift, amt);
   }
@@ -575,6 +668,9 @@ public:
     constexpr uint32_t Op = 0b010'1011'000U << 21;
     DataProcessing_Shifted_Reg(Op, s, rd, rn, rm, Shift, amt);
   }
+  void cmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
+    adds(s, FEXCore::ARMEmitter::Reg::zr, rn, rm, Shift, amt);
+  }
   void sub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift = FEXCore::ARMEmitter::ShiftType::LSL, uint32_t amt = 0) {
     LOGMAN_THROW_AA_FMT(Shift != FEXCore::ARMEmitter::ShiftType::ROR, "Doesn't support ROR");
     constexpr uint32_t Op = 0b100'1011'000U << 21;
@@ -606,6 +702,9 @@ public:
     constexpr uint32_t Op = 0b010'1011'001U << 21;
     DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift);
   }
+  void cmn(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) {
+    adds(s, FEXCore::ARMEmitter::Reg::zr, rn, rm, Option, Shift);
+  }
   void sub(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ExtendedType Option, uint32_t Shift = 0) {
     constexpr uint32_t Op = 0b100'1011'001U << 21;
     DataProcessing_Extended_Reg(Op, s, rd, rn, rm, Option, Shift);
@@ -636,6 +735,12 @@ public:
     constexpr uint32_t Op = 0b0111'1010'000U << 21;
     DataProcessing_Extended_Reg(Op, s, rd, rn, rm, FEXCore::ARMEmitter::ExtendedType::UXTB, 0);
   }
+  void ngc(ARMEmitter::Size s, Register rd, Register rm) {
+    sbc(s, rd, Reg::zr, rm);
+  }
+  void ngcs(ARMEmitter::Size s, Register rd, Register rm) {
+    sbcs(s, rd, Reg::zr, rm);
+  }
 
   // Rotate right into flags
   void rmif(XRegister rn, uint32_t shift, uint32_t mask) {
@@ -703,6 +808,18 @@ public:
     constexpr uint32_t Op = 0b0001'1010'100 << 21;
     ConditionalCompare(Op, 1, 0b01, s, rd, rn, rm, Cond);
   }
+  void cneg(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Condition Cond) {
+    csneg(s, rd, rn, rn, InvertCondition(Cond));
+  }
+  void cinc(ARMEmitter::Size s, Register rd, Register rn, Condition cond) {
+    csinc(s, rd, rn, rn, InvertCondition(cond));
+  }
+  void cinv(ARMEmitter::Size s, Register rd, Register rn, Condition cond) {
+    csinv(s, rd, rn, rn, InvertCondition(cond));
+  }
+  void csetm(ARMEmitter::Size s, Register rd, Condition cond) {
+    csinv(s, rd, Reg::zr, Reg::zr, InvertCondition(cond));
+  }
 
   // Data processing - 3 source
   void madd(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::Register ra) {
@@ -757,6 +874,13 @@ public:
   }
 
 private:
+  static constexpr Condition InvertCondition(Condition cond) {
+    // These behave as always, so it makes no sense to allow inverting these.
+    LOGMAN_THROW_AA_FMT(cond != Condition::CC_AL && cond != Condition::CC_NV,
+                        "Cannot invert CC_AL or CC_NV");
+    return static_cast<Condition>(FEXCore::ToUnderlying(cond) ^ 1);
+  }
+
   void and_(FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint32_t n, uint32_t immr, uint32_t imms) {
     constexpr uint32_t Op = 0b001'0010'00 << 22;
     DataProcessing_Logical_Imm(Op, s, rd, rn, n, immr, imms);
@@ -819,6 +943,21 @@ private:
     dc32(Instr);
   }
 
+  // Min/max immediate
+  void MinMaxImmediate(uint32_t opc, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, uint64_t Imm) {
+    const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
+
+    uint32_t Instr = 0b1'0001'11U << 22;
+
+    Instr |= SF;
+    Instr |= opc << 18;
+    Instr |= (Imm & 0xFF) << 10;
+    Instr |= Encode_rn(rn);
+    Instr |= Encode_rd(rd);
+
+    dc32(Instr);
+  }
+
   // Move Wide
   void DataProcessing_MoveWide(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, uint32_t Imm, uint32_t Offset) {
     const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
@@ -849,6 +988,24 @@ private:
     dc32(Instr);
   }
 
+  void xbfiz_helper(bool is_signed, ARMEmitter::Size s, Register rd, Register rn, uint32_t lsb, uint32_t width) {
+    [[maybe_unused]] const auto lsb_p_width = lsb + width;
+    const auto reg_size_bits = RegSizeInBits(s);
+
+    LOGMAN_THROW_AA_FMT(lsb_p_width <= reg_size_bits, "lsb + width ({}) must be <= {}. lsb={}, width={}",
+                        lsb_p_width, reg_size_bits, lsb, width);
+    LOGMAN_THROW_AA_FMT(width >= 1, "xbfiz width must be >= 1");
+
+    const auto immr = (reg_size_bits - lsb) & (reg_size_bits - 1);
+    const auto imms = width - 1;
+
+    if (is_signed) {
+      sbfm(s, rd, rn, immr, imms);
+    } else {
+      ubfm(s, rd, rn, immr, imms);
+    }
+  }
+
   void DataProcessing_Extract(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, uint32_t Imm) {
     const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
 
@@ -899,6 +1056,9 @@ private:
   // AddSub - shifted register
   void DataProcessing_Shifted_Reg(uint32_t Op, FEXCore::ARMEmitter::Size s, FEXCore::ARMEmitter::Register rd, FEXCore::ARMEmitter::Register rn, FEXCore::ARMEmitter::Register rm, FEXCore::ARMEmitter::ShiftType Shift, uint32_t amt) {
     LOGMAN_THROW_AA_FMT((amt & ~0b11'1111U) == 0, "Shift amount too large");
+    if (s == FEXCore::ARMEmitter::Size::i32Bit) {
+      LOGMAN_THROW_AA_FMT(amt < 32, "Shift amount for 32-bit must be below 32");
+    }
 
     const uint32_t SF = s == FEXCore::ARMEmitter::Size::i64Bit ? (1U << 31) : 0;
 

External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/ASIMDOps.inl

@@ -1893,433 +1893,351 @@ public:
   // TODO: Double check narrowing op size limits.
   // TODO: Don't enforce DRegister/QRegister for Q check
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void saddl(SubRegSize size, T rd, T rn, T rm) {
+  void saddl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0000, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0000, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void saddl2(SubRegSize size, T rd, T rn, T rm) {
+  void saddl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0000, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0000, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void saddw(SubRegSize size, T rd, T rn, T rm) {
+  void saddw(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0001, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0001, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void saddw2(SubRegSize size, T rd, T rn, T rm) {
+  void saddw2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0001, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0001, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void ssubl(SubRegSize size, T rd, T rn, T rm) {
+  void ssubl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0010, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0010, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void ssubl2(SubRegSize size, T rd, T rn, T rm) {
+  void ssubl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0010, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0010, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void ssubw(SubRegSize size, T rd, T rn, T rm) {
+  void ssubw(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0011, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0011, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void ssubw2(SubRegSize size, T rd, T rn, T rm) {
+  void ssubw2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0011, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0011, ConvertedSize, rd, rn, rm);
   }
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void addhn(SubRegSize size, T rd, T rn, T rm) {
+  void addhn(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
-    ASIMD3Different<T>(Op, 0, 0b0100, size, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0100, size, rd, rn, rm);
   }
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void addhn2(SubRegSize size, T rd, T rn, T rm) {
+  void addhn2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
-    ASIMD3Different<T>(Op, 0, 0b0100, size, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0100, size, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void sabal(SubRegSize size, T rd, T rn, T rm) {
+  void sabal(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0101, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0101, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void sabal2(SubRegSize size, T rd, T rn, T rm) {
+  void sabal2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0101, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0101, ConvertedSize, rd, rn, rm);
   }
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void subhn(SubRegSize size, T rd, T rn, T rm) {
+  void subhn(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
-    ASIMD3Different<T>(Op, 0, 0b0110, size, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0110, size, rd, rn, rm);
   }
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void subhn2(SubRegSize size, T rd, T rn, T rm) {
+  void subhn2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i64Bit, "No 64-bit dest support.");
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
-    ASIMD3Different<T>(Op, 0, 0b0110, size, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0110, size, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void sabdl(SubRegSize size, T rd, T rn, T rm) {
+  void sabdl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0111, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0111, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void sabdl2(SubRegSize size, T rd, T rn, T rm) {
+  void sabdl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b0111, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b0111, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void smlal(SubRegSize size, T rd, T rn, T rm) {
+  void smlal(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1000, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1000, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void smlal2(SubRegSize size, T rd, T rn, T rm) {
+  void smlal2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1000, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1000, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void sqdmlal(SubRegSize size, T rd, T rn, T rm) {
+  void sqdmlal(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1001, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1001, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void sqdmlal2(SubRegSize size, T rd, T rn, T rm) {
+  void sqdmlal2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1001, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1001, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void smlsl(SubRegSize size, T rd, T rn, T rm) {
+  void smlsl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1010, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1010, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void smlsl2(SubRegSize size, T rd, T rn, T rm) {
+  void smlsl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1010, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1010, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void sqdmlsl(SubRegSize size, T rd, T rn, T rm) {
+  void sqdmlsl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1011, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1011, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void sqdmlsl2(SubRegSize size, T rd, T rn, T rm) {
+  void sqdmlsl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1011, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1011, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void smull(SubRegSize size, T rd, T rn, T rm) {
+  void smull(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1100, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1100, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void smull2(SubRegSize size, T rd, T rn, T rm) {
+  void smull2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1100, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1100, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void sqdmull(SubRegSize size, T rd, T rn, T rm) {
+  void sqdmull(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1101, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1101, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void sqdmull2(SubRegSize size, T rd, T rn, T rm) {
+  void sqdmull2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i16Bit, "No 8/16-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 0, 0b1101, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1101, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void pmull(SubRegSize size, T rd, T rn, T rm) {
+  void pmull(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size == SubRegSize::i16Bit || size == SubRegSize::i128Bit, "Only 16-bit and 128-bit destination supported");
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
-    ASIMD3Different<T>(Op, 0, 0b1110, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1110, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void pmull2(SubRegSize size, T rd, T rn, T rm) {
+  void pmull2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size == SubRegSize::i16Bit || size == SubRegSize::i128Bit, "Only 16-bit and 128-bit destination supported");
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
-    ASIMD3Different<T>(Op, 0, 0b1110, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 0, 0b1110, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void uaddl(SubRegSize size, T rd, T rn, T rm) {
+  void uaddl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b0000, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b0000, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void uaddl2(SubRegSize size, T rd, T rn, T rm) {
+  void uaddl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b0000, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b0000, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void uaddw(SubRegSize size, T rd, T rn, T rm) {
+  void uaddw(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b0001, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b0001, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void uaddw2(SubRegSize size, T rd, T rn, T rm) {
+  void uaddw2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b0001, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b0001, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void usubl(SubRegSize size, T rd, T rn, T rm) {
+  void usubl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b0010, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b0010, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void usubl2(SubRegSize size, T rd, T rn, T rm) {
+  void usubl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b0010, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b0010, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void usubw(SubRegSize size, T rd, T rn, T rm) {
+  void usubw(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b0011, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b0011, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void usubw2(SubRegSize size, T rd, T rn, T rm) {
+  void usubw2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b0011, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b0011, ConvertedSize, rd, rn, rm);
   }
   // XXX: RADDHN/2
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void uabal(SubRegSize size, T rd, T rn, T rm) {
+  void uabal(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b0101, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b0101, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void uabal2(SubRegSize size, T rd, T rn, T rm) {
+  void uabal2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b0101, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b0101, ConvertedSize, rd, rn, rm);
   }
   // XXX: RSUBHN/2
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void uabdl(SubRegSize size, T rd, T rn, T rm) {
+  void uabdl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
@@ -2328,9 +2246,7 @@ public:
     ASIMD3Different(Op, 1, 0b0111, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void uabdl2(SubRegSize size, T rd, T rn, T rm) {
+  void uabdl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
@@ -2339,70 +2255,58 @@ public:
     ASIMD3Different(Op, 1, 0b0111, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void umlal(SubRegSize size, T rd, T rn, T rm) {
+  void umlal(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b1000, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b1000, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void umlal2(SubRegSize size, T rd, T rn, T rm) {
+  void umlal2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b1000, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b1000, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void umlsl(SubRegSize size, T rd, T rn, T rm) {
+  void umlsl(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b1010, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b1010, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void umlsl2(SubRegSize size, T rd, T rn, T rm) {
+  void umlsl2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b1010, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b1010, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<DRegister, T>)
-  void umull(SubRegSize size, T rd, T rn, T rm) {
+  void umull(SubRegSize size, DRegister rd, DRegister rn, DRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b1100, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b1100, ConvertedSize, rd, rn, rm);
   }
   ///< Size is dest size
-  template<typename T>
-  requires(std::is_same_v<QRegister, T>)
-  void umull2(SubRegSize size, T rd, T rn, T rm) {
+  void umull2(SubRegSize size, QRegister rd, QRegister rn, QRegister rm) {
     LOGMAN_THROW_AA_FMT(size != SubRegSize::i8Bit, "No 8-bit dest support.");
 
     constexpr uint32_t Op = 0b0000'1110'0010'0000'0000'00 << 10;
     const auto ConvertedSize = SubRegSize{FEXCore::ToUnderlying(size) - 1};
 
-    ASIMD3Different<T>(Op, 1, 0b1100, ConvertedSize, rd, rn, rm);
+    ASIMD3Different(Op, 1, 0b1100, ConvertedSize, rd, rn, rm);
   }
 
   // Advanced SIMD three same

External/FEXCore/Source/Interface/Core/ArchHelpers/CodeEmitter/Emitter.h

@@ -6,13 +6,14 @@
 #include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/Utils/MathUtils.h>
+#include <FEXCore/fextl/vector.h>
 
 #include <aarch64/assembler-aarch64.h>
 
 #include <cstdint>
 #include <utility>
 #include <type_traits>
-#include <vector>
 
 /*
  * Welcome to FEX-Emu's custom AArch64 emitter.
@@ -62,20 +63,9 @@ namespace FEXCore::ARMEmitter {
   };
 
   // This allows us to get the `Size` enum in bits.
-  template<Size size>
-  constexpr size_t RegSizeInBits() {
-    constexpr size_t RegSize[] = {
-      32, 64, 128,
-    };
-    return RegSize[FEXCore::ToUnderlying(size)];
-  }
-
-  [[maybe_unused]]
-  static inline size_t RegSizeInBits(Size size) {
-    constexpr size_t RegSize[] = {
-      32, 64, 128,
-    };
-    return RegSize[FEXCore::ToUnderlying(size)];
+  [[nodiscard]]
+  constexpr size_t RegSizeInBits(Size size) {
+    return size_t{32} << FEXCore::ToUnderlying(size);
   }
 
   /* This `SubRegSize` enum is used for most ASIMD operations.
@@ -90,14 +80,9 @@ namespace FEXCore::ARMEmitter {
   };
 
   // This allows us to get the `SubRegSize` in bits.
-  template<SubRegSize size>
-  constexpr size_t SubRegSizeInBits() {
-    return (1 << FEXCore::ToUnderlying(size)) * 8;
-  }
-
-  [[maybe_unused]]
-  static inline size_t SubRegSizeInBits(SubRegSize size) {
-    return (1 << FEXCore::ToUnderlying(size)) * 8;
+  [[nodiscard]]
+  constexpr size_t SubRegSizeInBits(SubRegSize size) {
+    return size_t{8} << FEXCore::ToUnderlying(size);
   }
 
   /* This `ScalarRegSize` enum is used for most scalar float
@@ -117,14 +102,9 @@ namespace FEXCore::ARMEmitter {
   };
 
   // This allows us to get the `ScalarRegSize` in bits.
-  template<ScalarRegSize size>
-  constexpr size_t ScalarRegSizeInBits() {
-    return (1 << FEXCore::ToUnderlying(size)) * 8;
-  }
-
-  [[maybe_unused]]
-  static inline size_t ScalarRegSizeInBits(ScalarRegSize size) {
-    return (1 << FEXCore::ToUnderlying(size)) * 8;
+  [[nodiscard]]
+  constexpr size_t ScalarRegSizeInBits(ScalarRegSize size) {
+    return size_t{8} << FEXCore::ToUnderlying(size);
   }
 
   /* This `VectorRegSizePair` union allows us to have an overlapping type
@@ -140,12 +120,12 @@ namespace FEXCore::ARMEmitter {
   };
 
   // This allows us to create a `VectorRegSizePair` union.
-  [[maybe_unused]]
-  static inline VectorRegSizePair ToVectorSizePair(SubRegSize size) {
+  [[nodiscard]]
+  constexpr VectorRegSizePair ToVectorSizePair(SubRegSize size) {
     return VectorRegSizePair {.Vector = size};
   }
-  [[maybe_unused]]
-  static inline VectorRegSizePair ToVectorSizePair(ScalarRegSize size) {
+  [[nodiscard]]
+  constexpr VectorRegSizePair ToVectorSizePair(ScalarRegSize size) {
     return VectorRegSizePair {.Scalar = size};
   }
 
@@ -228,58 +208,94 @@ namespace FEXCore::ARMEmitter {
    */
   class SVEMemOperand final {
     public:
+      // Used for scalar + vector variants to determine
+      // extension behavior on the index values.
+      enum class ModType : uint8_t {
+        MOD_UXTW,
+        MOD_SXTW,
+        MOD_LSL,
+        MOD_NONE,
+      };
+
+      enum class Type {
+        ScalarPlusScalar,
+        ScalarPlusImm,
+        ScalarPlusVector,
+        VectorPlusImm,
+      };
+
       SVEMemOperand(XRegister rn, XRegister rm = XReg::zr)
         : rn {rn}
+        , MemType{Type::ScalarPlusScalar}
         , MetaType {
           .ScalarScalarType {
-            .Header = { .MemType = TYPE_SCALAR_SCALAR },
             .rm = rm,
           }
         } {}
       SVEMemOperand(XRegister rn, int32_t imm = 0)
         : rn {rn}
+        , MemType{Type::ScalarPlusImm}
         , MetaType {
           .ScalarImmType {
-            .Header = { .MemType = TYPE_SCALAR_IMM },
+            .Imm = imm,
+          }
+        } {}
+      SVEMemOperand(XRegister rn, ZRegister zm, ModType mod = ModType::MOD_NONE, uint8_t scale = 0)
+        : rn{rn}
+        , MemType{Type::ScalarPlusVector}
+        , MetaType {
+          .ScalarVectorType {
+            .zm = zm,
+            .mod = mod,
+            .scale = scale,
+          }
+        } {}
+      SVEMemOperand(ZRegister zn, uint32_t imm)
+        : rn{Register{zn.Idx()}}
+        , MemType{Type::VectorPlusImm}
+        , MetaType {
+          .VectorImmType{
             .Imm = imm,
           }
         } {}
 
-      Register rn;
-      enum Type {
-        TYPE_SCALAR_SCALAR,
-        TYPE_SCALAR_IMM,
-        TYPE_SCALAR_VECTOR,
-        TYPE_VECTOR_IMM,
-      };
-      struct HeaderStruct {
-        Type MemType;
-      };
+      [[nodiscard]] bool IsScalarPlusScalar() const {
+        return MemType == Type::ScalarPlusScalar;
+      }
+      [[nodiscard]] bool IsScalarPlusImm() const {
+        return MemType == Type::ScalarPlusImm;
+      }
+      [[nodiscard]] bool IsScalarPlusVector() const {
+        return MemType == Type::ScalarPlusVector;
+      }
+      [[nodiscard]] bool IsVectorPlusImm() const {
+        return MemType == Type::VectorPlusImm;
+      }
 
-      union {
-        HeaderStruct Header;
+      union Data {
         struct {
-          HeaderStruct Header;
           Register rm;
         } ScalarScalarType;
 
         struct {
-          HeaderStruct Header;
           int32_t Imm;
         } ScalarImmType;
 
         struct {
-          HeaderStruct Header;
           ZRegister zm;
-          // TODO: Implement support for modifier
+          ModType mod;
+          uint8_t scale;
         } ScalarVectorType;
 
         struct {
-          HeaderStruct Header;
           // rn will be a ZRegister
-          int32_t Imm;
+          uint32_t Imm;
         } VectorImmType;
-      } MetaType;
+      };
+
+      Register rn;
+      Type MemType;
+      Data MetaType;
   };
 
   /* This `ExtendedMemOperand` class is used for the helper load-store instructions.
@@ -496,6 +512,20 @@ namespace FEXCore::ARMEmitter {
     SVE_ALL   = 0b11111,
   };
 
+  // Used with SVE FP immediate arithmetic instructions
+  enum class SVEFAddSubImm : uint32_t {
+    _0_5,
+    _1_0,
+  };
+  enum class SVEFMulImm : uint32_t {
+    _0_5,
+    _2_0,
+  };
+  enum class SVEFMaxMinImm : uint32_t {
+    _0_0,
+    _1_0,
+  };
+
   /* This `BackwardLabel` struct used for retaining a location for PC-Relative instructions.
    * This is specifically a label for a target that is logically `below` an instruction that uses it.
    * Which means that a branch would jump backwards.
@@ -524,7 +554,7 @@ namespace FEXCore::ARMEmitter {
       uint8_t *Location{};
       InstType Type;
     };
-    std::vector<Instructions> Insts{};
+    fextl::vector<Instructions> Insts{};
   };
 
   /* This `BiDirectionalLabel` struct used for retaining a location for PC-Relative instructions.

External/FEXCore/Source/Interface/Core/CPUBackend.cpp

@@ -1,3 +1,4 @@
+#include "FEXCore/Utils/AllocatorHooks.h"
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include <FEXCore/Core/CPUBackend.h>
@@ -57,7 +58,7 @@ auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
   CodeBuffer Buffer;
   Buffer.Size = Size;
   Buffer.Ptr = static_cast<uint8_t *>(
-      FEXCore::Allocator::mmap(nullptr, Buffer.Size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+      FEXCore::Allocator::VirtualAlloc(Buffer.Size, true));
   LOGMAN_THROW_AA_FMT(!!Buffer.Ptr, "Couldn't allocate code buffer");
 
   if (static_cast<Context::ContextImpl*>(ThreadState->CTX)->Config.GlobalJITNaming()) {
@@ -67,7 +68,7 @@ auto CPUBackend::AllocateNewCodeBuffer(size_t Size) -> CodeBuffer {
 }
 
 void CPUBackend::FreeCodeBuffer(CodeBuffer Buffer) {
-  FEXCore::Allocator::munmap(Buffer.Ptr, Buffer.Size);
+  FEXCore::Allocator::VirtualFree(Buffer.Ptr, Buffer.Size);
 }
 
 bool CPUBackend::IsAddressInCodeBuffer(uintptr_t Address) const {

External/FEXCore/Source/Interface/Core/CPUID.cpp

@@ -8,18 +8,20 @@ $end_info$
 #include "Common/StringConv.h"
 #include "Interface/Context/Context.h"
 #include "Interface/Core/CPUID.h"
-#include "Utils/FileLoading.h"
 
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CPUID.h>
 #include <FEXCore/Core/HostFeatures.h>
+#include <FEXCore/Utils/CPUInfo.h>
+#include <FEXCore/Utils/FileLoading.h>
+#include <FEXCore/fextl/string.h>
 #include <FEXHeaderUtils/Syscalls.h>
 
 #include "git_version.h"
 
 #include <cstring>
 #ifdef _M_X86_64
-#include <cpuid.h>
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #endif
 
 namespace FEXCore {
@@ -74,20 +76,6 @@ static uint32_t GetCPUID() {
   return CPU;
 }
 
-static uint32_t CalculateNumberOfCPUs() {
-  size_t CPUs = 1;
-
-  while(std::filesystem::exists("/sys/devices/system/cpu/cpu" + std::to_string(CPUs))) {
-    CPUs++;
-  }
-
-  return CPUs;
-}
-
-// TODO: Replace usages with CTX->HostFeatures.EnableAVX
-//       when AVX implementations are further along.
-constexpr uint32_t SUPPORTS_AVX = 0;
-
 #ifdef CPUID_AMD
 constexpr uint32_t FAMILY_IDENTIFIER =
   0 |          // Stepping
@@ -115,13 +103,13 @@ static uint32_t GetCycleCounterFrequency() {
 }
 
 void CPUIDEmu::SetupHostHybridFlag() {
-  size_t CPUs = CalculateNumberOfCPUs();
+  size_t CPUs = FEXCore::CPUInfo::CalculateNumberOfCPUs();
   PerCPUData.resize(CPUs);
 
   uint64_t MIDR{};
   for (size_t i = 0; i < CPUs; ++i) {
     std::error_code ec{};
-    std::string MIDRPath = fmt::format("/sys/devices/system/cpu/cpu{}/regs/identification/midr_el1", i);
+    fextl::string MIDRPath = fextl::fmt::format("/sys/devices/system/cpu/cpu{}/regs/identification/midr_el1", i);
 
     std::array<char, 18> Data;
     // Needs to be a fixed size since depending on kernel it will try to read a full page of data and fail
@@ -217,8 +205,8 @@ void CPUIDEmu::SetupHostHybridFlag() {
 
   if (Hybrid) {
     // Walk the MIDRs and calculate big little designs
-    std::vector<const CPUMIDR*> BigCores;
-    std::vector<const CPUMIDR*> LittleCores;
+    fextl::vector<const CPUMIDR*> BigCores;
+    fextl::vector<const CPUMIDR*> LittleCores;
 
     // Separate CPU cores out to big or little selected
     for (size_t i = 0; i < CPUs; ++i) {
@@ -354,28 +342,28 @@ void CPUIDEmu::SetupHostHybridFlag() {
 
 #else
 static uint32_t GetCycleCounterFrequency() {
-  uint32_t eax, ebx, ecx, edx;
-  __cpuid(0, eax, ebx, ecx, edx);
-  if (eax >= 0x15) {
-    __cpuid(0x15, eax, ebx, ecx, edx);
+  uint32_t data[4];
+  Xbyak::util::Cpu::getCpuid(0, data);
+  if (data[0] >= 0x15) {
+    Xbyak::util::Cpu::getCpuid(0x15, data);
 
-    if (eax && ebx && ecx) {
-      return ecx * ebx / eax;
+    if (data[0] && data[1] && data[2]) {
+      return data[2] * data[1] / data[0];
     }
   }
   return 0;
 }
 
 void CPUIDEmu::SetupHostHybridFlag() {
-  uint32_t eax, ebx, ecx, edx;
-  __cpuid(0, eax, ebx, ecx, edx);
-  if (eax >= 0x7) {
-    __cpuid(0x7, eax, ebx, ecx, edx);
+  uint32_t data[4];
+  Xbyak::util::Cpu::getCpuid(0, data);
+  if (data[0] >= 0x7) {
+    Xbyak::util::Cpu::getCpuid(0x7, data);
     // Bit 15 of edx claims hybrid CPU
-    Hybrid = (edx & (1U << 15)) != 0;
+    Hybrid = (data[3] & (1U << 15)) != 0;
   }
 
-  size_t CPUs = CalculateNumberOfCPUs();
+  size_t CPUs = FEXCore::CPUInfo::CalculateNumberOfCPUs();
   PerCPUData.resize(CPUs);
   for (size_t i = 0; i < CPUs; ++i) {
     PerCPUData[i].IsBig = true;
@@ -407,8 +395,6 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0h(uint32_t Leaf) {
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
   FEXCore::CPUID::FunctionResults Res{};
   uint32_t CoreCount = Cores();
-  // XXX: Enable once the rest of the SSE4.2 instructions are emulated
-  uint32_t SupportsSSE42 = CTX->HostFeatures.SupportsCRC && false ? 1 : 0;
 
   // Hypervisor bit is normally set but some applications have issues with it.
   uint32_t Hypervisor = HideHypervisorBit() ? 0 : 1;
@@ -441,15 +427,15 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) {
     (0 << 17) | // Process-context identifiers
     (0 << 18) | // Prefetching from memory mapped device
     (1 << 19) | // SSE4.1
-    (SupportsSSE42 << 20) | // SSE4.2
+    (CTX->HostFeatures.SupportsCRC << 20) | // SSE4.2
     (0 << 21) | // X2APIC
     (1 << 22) | // MOVBE
     (1 << 23) | // POPCNT
     (0 << 24) | // APIC TSC-Deadline
     (CTX->HostFeatures.SupportsAES << 25) | // AES
-    (0 << 26) | // XSAVE
-    (0 << 27) | // OSXSAVE
-    (SUPPORTS_AVX << 28) | // AVX
+    (SupportsAVX() << 26) | // XSAVE
+    (SupportsAVX() << 27) | // OSXSAVE
+    (SupportsAVX() << 28) | // AVX
     (0 << 29) | // F16C
     (CTX->HostFeatures.SupportsRAND << 30) | // RDRAND
     (Hypervisor << 31);
@@ -638,12 +624,12 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) {
       (1 <<  0) | // FS/GS support
       (0 <<  1) | // TSC adjust MSR
       (0 <<  2) | // SGX
-      (1 <<  3) | // BMI1
+      (SupportsAVX() << 3) | // BMI1
       (0 <<  4) | // Intel Hardware Lock Elison
       (0 <<  5) | // AVX2 support
       (1 <<  6) | // FPU data pointer updated only on exception
       (1 <<  7) | // SMEP support
-      (1 <<  8) | // BMI2
+      (SupportsAVX() << 8) | // BMI2
       (0 <<  9) | // Enhanced REP MOVSB/STOSB
       (1 << 10) | // INVPCID for system software control of process-context
       (0 << 11) | // Restricted transactional memory
@@ -707,7 +693,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) {
       (0 <<  1) | // Reserved
       (0 <<  2) | // AVX512_4VNNIW
       (0 <<  3) | // AVX512_4FMAPS
-      (0 <<  4) | // Fast Short Rep Mov
+      (1 <<  4) | // Fast Short Rep Mov
       (0 <<  5) | // Reserved
       (0 <<  6) | // Reserved
       (0 <<  7) | // Reserved
@@ -744,13 +730,13 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0Dh(uint32_t Leaf) {
   // Leaf 0
   FEXCore::CPUID::FunctionResults Res{};
 
-  uint32_t XFeatureSupportedSizeMax = SUPPORTS_AVX ? 0x0000'0340 : 0x0000'0240; // XFeatureEnabledSizeMax: Legacy Header + FPU/SSE + AVX
+  uint32_t XFeatureSupportedSizeMax = SupportsAVX() ? 0x0000'0340 : 0x0000'0240; // XFeatureEnabledSizeMax: Legacy Header + FPU/SSE + AVX
   if (Leaf == 0) {
     // XFeatureSupportedMask[31:0]
     Res.eax =
       (1 << 0) |            // X87 support
       (1 << 1) |            // 128-bit SSE support
-      (SUPPORTS_AVX << 2) | // 256-bit AVX support
+      (SupportsAVX() << 2) | // 256-bit AVX support
       (0b00 << 3) |         // MPX State
       (0b000 << 5) |        // AVX-512 state
       (0 << 8) |            // "Used for IA32_XSS" ... Used for what?
@@ -784,8 +770,8 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0Dh(uint32_t Leaf) {
     Res.edx = 0;
   }
   else if (Leaf == 2) {
-    Res.eax = SUPPORTS_AVX ? 0x0000'0100 : 0; // YmmSaveStateSize
-    Res.ebx = SUPPORTS_AVX ? 0x0000'0240 : 0; // YmmSaveStateOffset
+    Res.eax = SupportsAVX() ? 0x0000'0100 : 0; // YmmSaveStateSize
+    Res.ebx = SupportsAVX() ? 0x0000'0240 : 0; // YmmSaveStateOffset
 
     // Reserved
     Res.ecx = 0;
@@ -880,6 +866,13 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0000h(uint32_t Leaf) {
 
 // Extended processor and feature bits
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h(uint32_t Leaf) {
+
+  // RDTSCP is disabled on WIN32/Wine because there is no sane way to query processor ID.
+#ifndef _WIN32
+  constexpr uint32_t SUPPORTS_RDTSCP = 0;
+#else
+  constexpr uint32_t SUPPORTS_RDTSCP = 1;
+#endif
   FEXCore::CPUID::FunctionResults Res{};
 
   Res.eax = FAMILY_IDENTIFIER;
@@ -946,7 +939,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0001h(uint32_t Leaf) {
     (1 << 24) | // FXSAVE/FXRSTOR
     (1 << 25) | // FXSAVE/FXRSTOR Optimizations
     (0 << 26) | // 1 gigabit pages
-    (1 << 27) | // RDTSCP
+    (SUPPORTS_RDTSCP << 27) | // RDTSCP
     (0 << 28) | // Reserved
     (1 << 29) | // Long Mode
     (1 << 30) | // 3DNow! Extensions
@@ -977,14 +970,14 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0004h(uint32_t Leaf) {
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0002h(uint32_t Leaf, uint32_t CPU) {
   FEXCore::CPUID::FunctionResults Res{};
   memset(&Res, ' ', sizeof(FEXCore::CPUID::FunctionResults));
-  memcpy(&Res, &ProcessorBrand[0], std::min(16L, DESCRIBE_STR_SIZE));
+  memcpy(&Res, &ProcessorBrand[0], std::min(ssize_t{16L}, DESCRIBE_STR_SIZE));
   return Res;
 }
 
 FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0003h(uint32_t Leaf, uint32_t CPU) {
   FEXCore::CPUID::FunctionResults Res{};
   memset(&Res, ' ', sizeof(FEXCore::CPUID::FunctionResults));
-  memcpy(&Res, &ProcessorBrand[16], std::max(0L, DESCRIBE_STR_SIZE - 16));
+  memcpy(&Res, &ProcessorBrand[16], std::max(ssize_t{0L}, DESCRIBE_STR_SIZE - 16));
   return Res;
 }
 
@@ -1213,11 +1206,26 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_Reserved(uint32_t Leaf) {
   return Res;
 }
 
+FEXCore::CPUID::XCRResults CPUIDEmu::XCRFunction_0h() {
+  // This just returns XCR0
+  FEXCore::CPUID::XCRResults Res{
+    .eax = static_cast<uint32_t>(XCR0),
+    .edx = static_cast<uint32_t>(XCR0 >> 32),
+  };
+
+  return Res;
+}
+
 void CPUIDEmu::Init(FEXCore::Context::ContextImpl *ctx) {
   CTX = ctx;
 
   // Setup some state tracking
   SetupHostHybridFlag();
+
+  // TODO: Enable once AVX is supported.
+  if (false && CTX->HostFeatures.SupportsAVX) {
+    XCR0 |= XCR0_AVX;
+  }
 }
 }
 

External/FEXCore/Source/Interface/Core/CPUID.h

@@ -1,12 +1,12 @@
 #pragma once
 
+#include <FEXCore/Core/CPUID.h>
+#include <FEXCore/Config/Config.h>
+#include <FEXCore/fextl/vector.h>
+
 #include <cstdint>
 #include <unordered_map>
 #include <utility>
-#include <vector>
-
-#include <FEXCore/Core/CPUID.h>
-#include <FEXCore/Config/Config.h>
 
 namespace FEXCore {
 namespace Context {
@@ -63,13 +63,52 @@ public:
       return Function_8000_0004h(Leaf, CPU % PerCPUData.size());
   }
 
+  FEXCore::CPUID::XCRResults RunXCRFunction(uint32_t Function) {
+    if (Function >= 1) {
+      // XCR function 1 is not yet supported.
+      return {};
+    }
+
+    return XCRFunction_0h();
+  }
+
 private:
   FEXCore::Context::ContextImpl *CTX;
   bool Hybrid{};
   FEX_CONFIG_OPT(Cores, THREADS);
   FEX_CONFIG_OPT(HideHypervisorBit, HIDEHYPERVISORBIT);
 
+  // XFEATURE_ENABLED_MASK
+  // Mask that configures what features are enabled on the CPU.
+  // Affects XSAVE and XRSTOR when modified.
+  // Bit layout is as follows.
+  // [0]     - x87 enabled
+  // [1]     - SSE enabled
+  // [2]     - YMM enabled (256-bit SSE)
+  // [8:3]   - Reserved. MBZ.
+  // [9]     - MPK
+  // [10]    - Reserved. MBZ.
+  // [11]    - CET_U
+  // [12]    - CET_S
+  // [61:13] - Reserved. MBZ.
+  // [62]    - LWP (Lightweight profiling)
+  // [63]    - Reserved for XCR bit vector expansion. MBZ.
+  // Always enable x87 and SSE by default.
+  constexpr static uint64_t XCR0_X87 = 1ULL << 0;
+  constexpr static uint64_t XCR0_SSE = 1ULL << 1;
+  constexpr static uint64_t XCR0_AVX = 1ULL << 2;
+
+  uint64_t XCR0 {
+    XCR0_X87 |
+    XCR0_SSE
+  };
+
+  uint32_t SupportsAVX() const {
+    return (XCR0 & XCR0_AVX) ? 1 : 0;
+  }
+
   using FunctionHandler = FEXCore::CPUID::FunctionResults (CPUIDEmu::*)(uint32_t Leaf);
+
   struct CPUData {
     const char *ProductName{};
 #ifdef _M_ARM_64
@@ -77,7 +116,7 @@ private:
 #endif
     bool IsBig{};
   };
-  std::vector<CPUData> PerCPUData{};
+  fextl::vector<CPUData> PerCPUData{};
 
   // Functions
   FEXCore::CPUID::FunctionResults Function_0h(uint32_t Leaf);
@@ -109,6 +148,8 @@ private:
   FEXCore::CPUID::FunctionResults Function_8000_001Dh(uint32_t Leaf);
   FEXCore::CPUID::FunctionResults Function_Reserved(uint32_t Leaf);
 
+  FEXCore::CPUID::XCRResults XCRFunction_0h();
+
   void SetupHostHybridFlag();
   static constexpr std::array<FunctionHandler, 27> Primary = {
     // 0: Highest function parameter and ID

External/FEXCore/Source/Interface/Core/Core.cpp

@@ -8,9 +8,9 @@ $end_info$
 */
 
 #include <cstdint>
+#include "FEXCore/Utils/DeferredSignalMutex.h"
 #include "Interface/Context/Context.h"
 #include "Interface/Core/LookupCache.h"
-#include "Interface/Core/Core.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/Frontend.h"
 #include "Interface/Core/GdbServer.h"
@@ -19,10 +19,13 @@ $end_info$
 #include "Interface/Core/Interpreter/InterpreterCore.h"
 #include "Interface/Core/JIT/JITCore.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/Core/X86Tables/X86Tables.h"
 #include "Interface/HLE/Thunks/Thunks.h"
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 #include "Interface/IR/Passes.h"
 #include "Interface/IR/PassManager.h"
+#include "Utils/Allocator.h"
+#include "Utils/Allocator/HostAllocator.h"
 
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CodeLoader.h>
@@ -32,7 +35,6 @@ $end_info$
 #include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/InternalThreadState.h>
-#include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/HLE/SourcecodeResolver.h>
 #include <FEXCore/HLE/Linux/ThreadManagement.h>
@@ -42,9 +44,15 @@ $end_info$
 #include <FEXCore/IR/RegisterAllocationData.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/Event.h>
+#include <FEXCore/Utils/File.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Threads.h>
 #include <FEXCore/Utils/Profiler.h>
+#include <FEXCore/fextl/fmt.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/set.h>
+#include <FEXCore/fextl/sstream.h>
+#include <FEXCore/fextl/vector.h>
 #include <FEXHeaderUtils/Syscalls.h>
 #include <FEXHeaderUtils/TodoDefines.h>
 
@@ -53,46 +61,26 @@ $end_info$
 #include <atomic>
 #include <chrono>
 #include <condition_variable>
-#include <filesystem>
+#include <fcntl.h>
 #include <functional>
-#include <fstream>
-#include <map>
-#include <memory>
 #include <mutex>
 #include <queue>
-#include <set>
 #include <shared_mutex>
 #include <signal.h>
 #include <stdio.h>
-#include <string.h>
-#include <string>
 #include <string_view>
-#include <sys/mman.h>
 #include <sys/stat.h>
-#include <sys/syscall.h>
 #include <type_traits>
 #include <unistd.h>
 #include <unordered_map>
 #include <utility>
-#include <vector>
 #include <xxhash.h>
 
-
-namespace FEXCore::CPU {
-  bool CreateCPUCore(Context::ContextImpl *CTX) {
-    // This should be used for generating things that are shared between threads
-    CTX->CPUID.Init(CTX);
-    return true;
-  }
-}
-
 namespace FEXCore::Core {
 struct ThreadLocalData {
   FEXCore::Core::InternalThreadState* Thread;
 };
 
-thread_local ThreadLocalData ThreadData{};
-
 constexpr std::array<std::string_view const, 22> FlagNames = {
   "CF",
   "",
@@ -153,12 +141,8 @@ namespace FEXCore::Context {
     BlockData = std::make_unique<FEXCore::BlockSamplingData>();
 #endif
     if (Config.CacheObjectCodeCompilation() != FEXCore::Config::ConfigObjectCodeHandler::CONFIG_NONE) {
-      CodeObjectCacheService = std::make_unique<FEXCore::CodeSerialize::CodeObjectSerializeService>(this);
+      CodeObjectCacheService = fextl::make_unique<FEXCore::CodeSerialize::CodeObjectSerializeService>(this);
     }
-    if (!Config.EnableAVX) {
-      HostFeatures.SupportsAVX = false;
-    }
-
     if (!Config.Is64BitMode()) {
       // When operating in 32-bit mode, the virtual memory we care about is only the lower 32-bits.
       Config.VirtualMemSize = 1ULL << 32;
@@ -170,9 +154,16 @@ namespace FEXCore::Context {
       // Only initialize symbols file if enabled. Ensures we don't pollute /tmp with empty files.
       Symbols.InitFile();
     }
+
+    // Track atomic TSO emulation configuration.
+    UpdateAtomicTSOEmulationConfig();
   }
 
   ContextImpl::~ContextImpl() {
+    if (ParentThread) {
+      DestroyThread(ParentThread);
+    }
+
     {
       if (CodeObjectCacheService) {
         CodeObjectCacheService->Shutdown();
@@ -191,27 +182,43 @@ namespace FEXCore::Context {
     }
   }
 
-  static FEXCore::Core::CPUState CreateDefaultCPUState() {
-    FEXCore::Core::CPUState NewThreadState{};
+  uint64_t ContextImpl::RestoreRIPFromHostPC(FEXCore::Core::InternalThreadState *Thread, uint64_t HostPC) {
+    const auto Frame = Thread->CurrentFrame;
+    const uint64_t BlockBegin = Frame->State.InlineJITBlockHeader;
+    auto InlineHeader = reinterpret_cast<const CPU::CPUBackend::JITCodeHeader *>(BlockBegin);
 
-    // Initialize default CPU state
-    NewThreadState.rip = ~0ULL;
-    for (auto& greg : NewThreadState.gregs) {
-      greg = 0;
+    if (InlineHeader) {
+      auto InlineTail = reinterpret_cast<const CPU::CPUBackend::JITCodeTail *>(Frame->State.InlineJITBlockHeader + InlineHeader->OffsetToBlockTail);
+      auto RIPEntries = reinterpret_cast<const CPU::CPUBackend::JITRIPReconstructEntries *>(Frame->State.InlineJITBlockHeader + InlineHeader->OffsetToBlockTail + InlineTail->OffsetToRIPEntries);
+
+      // Check if the host PC is currently within a code block.
+      // If it is then RIP can be reconstructed from the beginning of the code block.
+      // This is currently as close as FEX can get RIP reconstructions.
+      if (HostPC >= reinterpret_cast<uint64_t>(BlockBegin) &&
+          HostPC < reinterpret_cast<uint64_t>(BlockBegin + InlineTail->Size)) {
+
+        // Reconstruct RIP from JIT entries for this block.
+        uint64_t StartingHostPC = BlockBegin;
+        uint64_t StartingGuestRIP = InlineTail->RIP;
+
+        for (uint32_t i = 0; i < InlineTail->NumberOfRIPEntries; ++i) {
+          const auto &RIPEntry = RIPEntries[i];
+          if (HostPC >= (StartingHostPC + RIPEntry.HostPCOffset)) {
+            // We are beyond this entry, keep going forward.
+            StartingHostPC += RIPEntry.HostPCOffset;
+            StartingGuestRIP += RIPEntry.GuestRIPOffset;
+          }
+          else {
+            // Passed where the Host PC is at. Break now.
+            break;
+          }
+        }
+        return StartingGuestRIP;
+      }
     }
 
-    for (auto& xmm : NewThreadState.xmm.avx.data) {
-      xmm[0] = 0xDEADBEEFULL;
-      xmm[1] = 0xBAD0DAD1ULL;
-      xmm[2] = 0xDEADCAFEULL;
-      xmm[3] = 0xBAD2CAD3ULL;
-    }
-    memset(NewThreadState.flags, 0, Core::CPUState::NUM_EFLAG_BITS);
-    NewThreadState.flags[1] = 1;
-    NewThreadState.flags[9] = 1;
-    NewThreadState.FCW = 0x37F;
-    NewThreadState.FTW = 0xFFFF;
-    return NewThreadState;
+    // Fallback to what is stored in the RIP currently.
+    return Frame->State.rip;
   }
 
   FEXCore::Core::InternalThreadState* ContextImpl::InitCore(uint64_t InitialRIP, uint64_t StackPointer) {
@@ -219,16 +226,13 @@ namespace FEXCore::Context {
     switch (Config.Core) {
 #ifdef INTERPRETER_ENABLED
     case FEXCore::Config::CONFIG_INTERPRETER:
-      FEXCore::CPU::InitializeInterpreterSignalHandlers(this);
       BackendFeatures = FEXCore::CPU::GetInterpreterBackendFeatures();
       break;
 #endif
     case FEXCore::Config::CONFIG_IRJIT:
 #if (_M_X86_64 && JIT_X86_64)
-      FEXCore::CPU::InitializeX86JITSignalHandlers(this);
       BackendFeatures = FEXCore::CPU::GetX86JITBackendFeatures();
 #elif (_M_ARM_64 && JIT_ARM64) || defined(VIXL_SIMULATOR)
-      FEXCore::CPU::InitializeArm64JITSignalHandlers(this);
       BackendFeatures = FEXCore::CPU::GetArm64JITBackendFeatures();
 #else
       ERROR_AND_DIE_FMT("FEXCore has been compiled without a viable JIT core");
@@ -252,24 +256,37 @@ namespace FEXCore::Context {
     ERROR_AND_DIE_FMT("FEXCore has been compiled with an unknown target");
 #endif
 
-    // Initialize common signal handlers
+    // Set up the SignalDelegator config since core is initialized.
+    FEXCore::SignalDelegator::SignalDelegatorConfig SignalConfig {
+      .StaticRegisterAllocation = DispatcherConfig.StaticRegisterAllocation,
+      .SupportsAVX = HostFeatures.SupportsAVX,
 
-    auto PauseHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-      return static_cast<ContextImpl*>(Thread->CTX)->Dispatcher->HandleSignalPause(Thread, Signal, info, ucontext);
+      .DispatcherBegin = Dispatcher->Start,
+      .DispatcherEnd = Dispatcher->End,
+
+      .AbsoluteLoopTopAddressFillSRA = Dispatcher->AbsoluteLoopTopAddressFillSRA,
+      .SignalHandlerReturnAddress = Dispatcher->SignalHandlerReturnAddress,
+      .SignalHandlerReturnAddressRT = Dispatcher->SignalHandlerReturnAddressRT,
+
+      .PauseReturnInstruction = Dispatcher->PauseReturnInstruction,
+      .ThreadPauseHandlerAddressSpillSRA = Dispatcher->ThreadPauseHandlerAddressSpillSRA,
+      .ThreadPauseHandlerAddress = Dispatcher->ThreadPauseHandlerAddress,
+
+      // Stop handlers.
+      .ThreadStopHandlerAddressSpillSRA = Dispatcher->ThreadStopHandlerAddressSpillSRA,
+      .ThreadStopHandlerAddress = Dispatcher->ThreadStopHandlerAddress,
+
+      // SRA information.
+      .SRAGPRCount = Dispatcher->GetSRAGPRCount(),
+      .SRAFPRCount = Dispatcher->GetSRAFPRCount(),
     };
 
-    SignalDelegation->RegisterHostSignalHandler(SignalDelegator::SIGNAL_FOR_PAUSE, PauseHandler, true);
+    Dispatcher->GetSRAGPRMapping(SignalConfig.SRAGPRMapping);
+    Dispatcher->GetSRAFPRMapping(SignalConfig.SRAFPRMapping);
 
-    auto GuestSignalHandler = [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack) -> bool {
-      return static_cast<ContextImpl*>(Thread->CTX)->Dispatcher->HandleGuestSignal(Thread, Signal, info, ucontext, GuestAction, GuestStack);
-    };
+    // Give this configuration to the SignalDelegator.
+    SignalDelegation->SetConfig(SignalConfig);
 
-    for (uint32_t Signal = 0; Signal <= SignalDelegator::MAX_SIGNALS; ++Signal) {
-      SignalDelegation->RegisterHostSignalHandlerForGuest(Signal, GuestSignalHandler);
-    }
-
-    // Initialize GDBServer after the signal handlers are installed
-    // It may install its own handlers that need to be executed AFTER the CPU cores
     if (Config.GdbServer) {
       StartGdbServer();
     }
@@ -277,12 +294,13 @@ namespace FEXCore::Context {
       StopGdbServer();
     }
 
-    ThunkHandler.reset(FEXCore::ThunkHandler::Create());
+#ifndef _WIN32
+    ThunkHandler = FEXCore::ThunkHandler::Create();
+#endif
 
     using namespace FEXCore::Core;
 
-    FEXCore::Core::CPUState NewThreadState = CreateDefaultCPUState();
-    FEXCore::Core::InternalThreadState *Thread = CreateThread(&NewThreadState, 0);
+    FEXCore::Core::InternalThreadState *Thread = CreateThread(nullptr, 0);
 
     // We are the parent thread
     ParentThread = Thread;
@@ -296,43 +314,24 @@ namespace FEXCore::Context {
   }
 
   void ContextImpl::StartGdbServer() {
+#ifndef _WIN32
     if (!DebugServer) {
-      DebugServer = std::make_unique<GdbServer>(this);
+      DebugServer = fextl::make_unique<GdbServer>(this);
       StartPaused = true;
     }
+#endif
   }
 
   void ContextImpl::StopGdbServer() {
+#ifndef _WIN32
     DebugServer.reset();
+#endif
   }
 
   void ContextImpl::HandleCallback(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) {
     static_cast<ContextImpl*>(Thread->CTX)->Dispatcher->ExecuteJITCallback(Thread->CurrentFrame, RIP);
   }
 
-  void ContextImpl::HandleSignalHandlerReturn(bool RT) {
-    using SignalHandlerReturnFunc = void(*)();
-
-    SignalHandlerReturnFunc SignalHandlerReturn{};
-    if (RT) {
-      SignalHandlerReturn = reinterpret_cast<SignalHandlerReturnFunc>(Dispatcher->SignalHandlerReturnAddressRT);
-    }
-    else {
-      SignalHandlerReturn = reinterpret_cast<SignalHandlerReturnFunc>(Dispatcher->SignalHandlerReturnAddress);
-    }
-
-    SignalHandlerReturn();
-    FEX_UNREACHABLE;
-  }
-
-  void ContextImpl::RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required) {
-      SignalDelegation->RegisterHostSignalHandler(Signal, Func, Required);
-  }
-
-  void ContextImpl::RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required) {
-    SignalDelegation->RegisterFrontendHostSignalHandler(Signal, Func, Required);
-  }
-
   void ContextImpl::WaitForIdle() {
     std::unique_lock<std::mutex> lk(IdleWaitMutex);
     IdleWaitCV.wait(lk, [this] {
@@ -365,11 +364,7 @@ namespace FEXCore::Context {
     // Tell all the threads that they should pause
     std::lock_guard<std::mutex> lk(ThreadCreationMutex);
     for (auto &Thread : Threads) {
-      Thread->SignalReason.store(FEXCore::Core::SignalEvent::Pause);
-      if (Thread->RunningEvents.Running.load()) {
-        // Only attempt to stop this thread if it is running
-        FHU::Syscalls::tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
-      }
+      SignalDelegation->SignalThread(Thread, FEXCore::Core::SignalEvent::Pause);
     }
   }
 
@@ -470,15 +465,13 @@ namespace FEXCore::Context {
 
   void ContextImpl::StopThread(FEXCore::Core::InternalThreadState *Thread) {
     if (Thread->RunningEvents.Running.exchange(false)) {
-      Thread->SignalReason.store(FEXCore::Core::SignalEvent::Stop);
-      FHU::Syscalls::tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
+      SignalDelegation->SignalThread(Thread, FEXCore::Core::SignalEvent::Stop);
     }
   }
 
   void ContextImpl::SignalThread(FEXCore::Core::InternalThreadState *Thread, FEXCore::Core::SignalEvent Event) {
     if (Thread->RunningEvents.Running.load()) {
-      Thread->SignalReason.store(Event);
-      FHU::Syscalls::tgkill(Thread->ThreadManager.PID, Thread->ThreadManager.TID, SignalDelegator::SIGNAL_FOR_PAUSE);
+      SignalDelegation->SignalThread(Thread, Event);
     }
   }
 
@@ -550,7 +543,9 @@ namespace FEXCore::Context {
     Thread->ThreadManager.TID = FHU::Syscalls::gettid();
     Thread->ThreadManager.PID = ::getpid();
     SignalDelegation->RegisterTLSState(Thread);
-    ThunkHandler->RegisterTLSState(Thread);
+    if (ThunkHandler) {
+      ThunkHandler->RegisterTLSState(Thread);
+    }
   }
 
   void ContextImpl::RunThread(FEXCore::Core::InternalThreadState *Thread) {
@@ -559,11 +554,11 @@ namespace FEXCore::Context {
   }
 
   void ContextImpl::InitializeCompiler(FEXCore::Core::InternalThreadState* Thread) {
-    Thread->OpDispatcher = std::make_unique<FEXCore::IR::OpDispatchBuilder>(this);
+    Thread->OpDispatcher = fextl::make_unique<FEXCore::IR::OpDispatchBuilder>(this);
     Thread->OpDispatcher->SetMultiblock(Config.Multiblock);
-    Thread->LookupCache = std::make_unique<FEXCore::LookupCache>(this);
-    Thread->FrontendDecoder = std::make_unique<FEXCore::Frontend::Decoder>(this);
-    Thread->PassManager = std::make_unique<FEXCore::IR::PassManager>();
+    Thread->LookupCache = fextl::make_unique<FEXCore::LookupCache>(this);
+    Thread->FrontendDecoder = fextl::make_unique<FEXCore::Frontend::Decoder>(this);
+    Thread->PassManager = fextl::make_unique<FEXCore::IR::PassManager>();
     Thread->PassManager->RegisterExitHandler([this]() {
         Stop(false /* Ignore current thread */);
     });
@@ -614,7 +609,9 @@ namespace FEXCore::Context {
     FEXCore::Core::InternalThreadState *Thread = new FEXCore::Core::InternalThreadState{};
 
     // Copy over the new thread state to the new object
-    memcpy(Thread->CurrentFrame, NewThreadState, sizeof(FEXCore::Core::CPUState));
+    if (NewThreadState) {
+      memcpy(Thread->CurrentFrame, NewThreadState, sizeof(FEXCore::Core::CPUState));
+    }
     Thread->CurrentFrame->Thread = Thread;
 
     // Set up the thread manager state
@@ -623,6 +620,9 @@ namespace FEXCore::Context {
     InitializeCompiler(Thread);
     InitializeThreadData(Thread);
 
+    Thread->CurrentFrame->State.DeferredSignalRefCount.Store(0);
+    Thread->CurrentFrame->State.DeferredSignalFaultAddress = reinterpret_cast<Core::NonAtomicRefCounter<uint64_t>*>(FEXCore::Allocator::VirtualAlloc(4096));
+
     // Insert after the Thread object has been fully initialized
     {
       std::lock_guard lk(ThreadCreationMutex);
@@ -648,10 +648,23 @@ namespace FEXCore::Context {
       // To be able to delete a thread from itself, we need to detached the std::thread object
       Thread->ExecutionThread->detach();
     }
+
+    FEXCore::Allocator::VirtualFree(reinterpret_cast<void*>(Thread->CurrentFrame->State.DeferredSignalFaultAddress), 4096);
     delete Thread;
   }
 
-  void ContextImpl::CleanupAfterFork(FEXCore::Core::InternalThreadState *LiveThread) {
+#ifndef _WIN32
+  void ContextImpl::UnlockAfterFork(FEXCore::Core::InternalThreadState *LiveThread, bool Child) {
+    Allocator::UnlockAfterFork(LiveThread, Child);
+
+    if (Child) {
+      CodeInvalidationMutex.StealAndDropActiveLocks();
+    }
+    else {
+      CodeInvalidationMutex.unlock();
+      return;
+    }
+
     // This function is called after fork
     // We need to cleanup some of the thread data that is dead
     for (auto &DeadThread : Threads) {
@@ -690,6 +703,12 @@ namespace FEXCore::Context {
     FEXCore::Threads::Thread::CleanupAfterFork();
   }
 
+  void ContextImpl::LockBeforeFork(FEXCore::Core::InternalThreadState *Thread) {
+    CodeInvalidationMutex.lock();
+    Allocator::LockBeforeFork(Thread);
+  }
+#endif
+
   void ContextImpl::AddBlockMapping(FEXCore::Core::InternalThreadState *Thread, uint64_t Address, void *Ptr) {
     Thread->LookupCache->AddBlockMapping(Address, Ptr);
   }
@@ -710,49 +729,46 @@ namespace FEXCore::Context {
   }
 
   static void IRDumper(FEXCore::Core::InternalThreadState *Thread, IR::IREmitter *IREmitter, uint64_t GuestRIP, IR::RegisterAllocationData* RA) {
-    FILE* f = nullptr;
-    bool CloseAfter = false;
+    FEXCore::File::File FD;
     const auto DumpIRStr = static_cast<ContextImpl*>(Thread->CTX)->Config.DumpIR();
 
     // DumpIRStr might be no if not dumping but ShouldDump is set in OpDisp
     if (DumpIRStr =="stderr" || DumpIRStr =="no") {
-      f = stderr;
+      FD = FEXCore::File::File::GetStdERR();
     }
     else if (DumpIRStr =="stdout") {
-      f = stdout;
+      FD = FEXCore::File::File::GetStdOUT();
     }
     else {
-      const auto fileName = fmt::format("{}/{:x}{}", DumpIRStr, GuestRIP, RA ? "-post.ir" : "-pre.ir");
-      f = fopen(fileName.c_str(), "w");
-      CloseAfter = true;
+      const auto fileName = fextl::fmt::format("{}/{:x}{}", DumpIRStr, GuestRIP, RA ? "-post.ir" : "-pre.ir");
+      FD = FEXCore::File::File(fileName.c_str(),
+        FEXCore::File::FileModes::WRITE |
+        FEXCore::File::FileModes::CREATE |
+        FEXCore::File::FileModes::TRUNCATE);
     }
 
-    if (f) {
-      std::stringstream out;
+    if (FD.IsValid()) {
+      fextl::stringstream out;
       auto NewIR = IREmitter->ViewIR();
       FEXCore::IR::Dump(&out, &NewIR, RA);
-      fmt::print(f,"IR-{} 0x{:x}:\n{}\n@@@@@\n", RA ? "post" : "pre", GuestRIP, out.str());
-
-      if (CloseAfter) {
-        fclose(f);
-      }
+      fextl::fmt::print(FD, "IR-{} 0x{:x}:\n{}\n@@@@@\n", RA ? "post" : "pre", GuestRIP, out.str());
     }
   };
 
   static void ValidateIR(ContextImpl *ctx, IR::IREmitter *IREmitter) {
     // Convert to text, Parse, Convert to text again and make sure the texts match
-    std::stringstream out;
+    fextl::stringstream out;
     static auto compaction = IR::CreateIRCompaction(ctx->OpDispatcherAllocator);
     compaction->Run(IREmitter);
     auto NewIR = IREmitter->ViewIR();
     Dump(&out, &NewIR, nullptr);
     out.seekg(0);
     FEXCore::Utils::PooledAllocatorMalloc Allocator;
-    auto reparsed = IR::Parse(Allocator, &out);
+    auto reparsed = IR::Parse(Allocator, out);
     if (reparsed == nullptr) {
       LOGMAN_MSG_A_FMT("Failed to parse IR\n");
     } else {
-      std::stringstream out2;
+      fextl::stringstream out2;
       auto NewIR2 = reparsed->ViewIR();
       Dump(&out2, &NewIR2, nullptr);
       if (out.str() != out2.str()) {
@@ -790,7 +806,7 @@ namespace FEXCore::Context {
 
       Thread->FrontendDecoder->DecodeInstructionsAtEntry(GuestCode, GuestRIP, [Thread](uint64_t BlockEntry, uint64_t Start, uint64_t Length) {
         if (Thread->LookupCache->AddBlockExecutableRange(BlockEntry, Start, Length)) {
-          static_cast<ContextImpl*>(Thread->CTX)->SyscallHandler->MarkGuestExecutableRange(Start, Length);
+          static_cast<ContextImpl*>(Thread->CTX)->SyscallHandler->MarkGuestExecutableRange(Thread, Start, Length);
         }
       });
 
@@ -820,7 +836,7 @@ namespace FEXCore::Context {
           DecodedInfo = &Block.DecodedInstructions[i];
           bool IsLocked = DecodedInfo->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_LOCK;
 
-          if (ExtendedDebugInfo) {
+          if (ExtendedDebugInfo || Thread->OpDispatcher->CanHaveSideEffects(TableInfo, DecodedInfo)) {
             Thread->OpDispatcher->_GuestOpcode(Block.Entry + BlockInstructionsLength - GuestRIP);
           }
 
@@ -847,14 +863,14 @@ namespace FEXCore::Context {
 
           if (TableInfo && TableInfo->OpcodeDispatcher) {
             auto Fn = TableInfo->OpcodeDispatcher;
-            Thread->OpDispatcher->HandledLock = false;
+            Thread->OpDispatcher->ResetHandledLock();
             Thread->OpDispatcher->ResetDecodeFailure();
             std::invoke(Fn, Thread->OpDispatcher, DecodedInfo);
             if (Thread->OpDispatcher->HadDecodeFailure()) {
               HadDispatchError = true;
             }
             else {
-              if (Thread->OpDispatcher->HandledLock != IsLocked) {
+              if (Thread->OpDispatcher->HasHandledLock() != IsLocked) {
                 HadDispatchError = true;
                 LogMan::Msg::EFmt("Missing LOCK HANDLER at 0x{:x}{{'{}'}}", Block.Entry + BlockInstructionsLength, TableInfo->Name ?: "UND");
               }
@@ -864,6 +880,9 @@ namespace FEXCore::Context {
             }
           }
           else {
+            if (TableInfo) {
+              LogMan::Msg::EFmt("Invalid or Unknown instruction: {} 0x{:x}", TableInfo->Name ?: "UND", Block.Entry - GuestRIP);
+            }
             // Invalid instruction
             Thread->OpDispatcher->InvalidOp(DecodedInfo);
             Thread->OpDispatcher->_ExitFunction(Thread->OpDispatcher->_EntrypointOffset(Block.Entry - GuestRIP, GPRSize));
@@ -901,7 +920,7 @@ namespace FEXCore::Context {
 
     IR::IREmitter *IREmitter = Thread->OpDispatcher.get();
 
-    auto ShouldDump = static_cast<ContextImpl*>(Thread->CTX)->Config.DumpIR() != "no" || Thread->OpDispatcher->ShouldDump;
+    auto ShouldDump = static_cast<ContextImpl*>(Thread->CTX)->Config.DumpIR() != "no" || Thread->OpDispatcher->ShouldDumpIR();
     // Debug
     {
       if (ShouldDump) {
@@ -966,7 +985,7 @@ namespace FEXCore::Context {
     }
 
     if (SourcecodeResolver && Config.GDBSymbols()) {
-      auto AOTIRCacheEntry = SyscallHandler->LookupAOTIRCacheEntry(GuestRIP);
+      auto AOTIRCacheEntry = SyscallHandler->LookupAOTIRCacheEntry(Thread, GuestRIP);
       if (AOTIRCacheEntry.Entry && !AOTIRCacheEntry.Entry->ContainsCode) {
         AOTIRCacheEntry.Entry->SourcecodeMap =
             SourcecodeResolver->GenerateMap(AOTIRCacheEntry.Entry->Filename, AOTIRCacheEntry.Entry->FileId);
@@ -975,7 +994,7 @@ namespace FEXCore::Context {
 
     // AOT IR bookkeeping and cache
     {
-      auto [IRCopy, RACopy, DebugDataCopy, _StartAddr, _Length, _GeneratedIR] = IRCaptureCache.PreGenerateIRFetch(GuestRIP, IRList);
+      auto [IRCopy, RACopy, DebugDataCopy, _StartAddr, _Length, _GeneratedIR] = IRCaptureCache.PreGenerateIRFetch(Thread, GuestRIP, IRList);
       if (_GeneratedIR) {
         // Setup pointers to internal structures
         IRList = IRCopy;
@@ -998,9 +1017,6 @@ namespace FEXCore::Context {
       StartAddr = _StartAddr;
       Length = _Length;
 
-      // Increment stats
-      Thread->Stats.BlocksCompiled.fetch_add(1);
-
       // These blocks aren't already in the cache
       GeneratedIR = true;
     }
@@ -1039,7 +1055,7 @@ namespace FEXCore::Context {
     auto Thread = Frame->Thread;
 
     // Invalidate might take a unique lock on this, to guarantee that during invalidation no code gets compiled
-    std::shared_lock lk(CodeInvalidationMutex);
+    ScopedDeferredSignalWithForkableSharedLock lk(CodeInvalidationMutex, Thread);
 
     // Is the code in the cache?
     // The backends only check L1 and L2, not L3
@@ -1071,7 +1087,7 @@ namespace FEXCore::Context {
       auto FragmentBasePtr = reinterpret_cast<uint8_t *>(CodePtr);
 
       if (DebugData) {
-        auto GuestRIPLookup = SyscallHandler->LookupAOTIRCacheEntry(GuestRIP);
+        auto GuestRIPLookup = SyscallHandler->LookupAOTIRCacheEntry(Thread, GuestRIP);
 
         if (DebugData->Subblocks.size()) {
           for (auto& Subblock: DebugData->Subblocks) {
@@ -1096,7 +1112,7 @@ namespace FEXCore::Context {
     if (CodeObjectCacheService &&
         Config.CacheObjectCodeCompilation == FEXCore::Config::ConfigObjectCodeHandler::CONFIG_READWRITE &&
         DebugData) {
-      CodeObjectCacheService->AsyncAddSerializationJob(std::make_unique<CodeSerialize::AsyncJobHandler::SerializationJobData>(
+      CodeObjectCacheService->AsyncAddSerializationJob(fextl::make_unique<CodeSerialize::AsyncJobHandler::SerializationJobData>(
         CodeSerialize::AsyncJobHandler::SerializationJobData {
           .GuestRIP = GuestRIP,
           .GuestCodeLength = Length,
@@ -1135,10 +1151,12 @@ namespace FEXCore::Context {
   }
 
   void ContextImpl::ExecutionThread(FEXCore::Core::InternalThreadState *Thread) {
-    Core::ThreadData.Thread = Thread;
     Thread->ExitReason = FEXCore::Context::ExitReason::EXIT_WAITING;
 
     InitializeThreadTLSData(Thread);
+#ifndef _WIN32
+    Alloc::OSAllocator::RegisterTLSData(Thread);
+#endif
 
     ++IdleWaitRefCount;
 
@@ -1183,6 +1201,9 @@ namespace FEXCore::Context {
     --IdleWaitRefCount;
     IdleWaitCV.notify_all();
 
+#ifndef _WIN32
+    Alloc::OSAllocator::UninstallTLSData(Thread);
+#endif
     SignalDelegation->UninstallTLSState(Thread);
 
     // If the parent thread is waiting to join, then we can't destroy our thread object
@@ -1213,14 +1234,20 @@ namespace FEXCore::Context {
     }
   }
 
-  void ContextImpl::InvalidateGuestCodeRange(uint64_t Start, uint64_t Length) {
-    FHU::ScopedSignalMaskWithUniqueLock CodeInvalidationLock(CodeInvalidationMutex);
+  void ContextImpl::InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length) {
+    // Potential deferred since Thread might not be valid.
+    // Thread object isn't valid very early in frontend's initialization.
+    // To be more optimal the frontend should provide this code with a valid Thread object earlier.
+    ScopedPotentialDeferredSignalWithForkableUniqueLock lk(CodeInvalidationMutex, Thread);
 
     InvalidateGuestCodeRangeInternal(this, Start, Length);
   }
 
-  void ContextImpl::InvalidateGuestCodeRange(uint64_t Start, uint64_t Length, std::function<void(uint64_t start, uint64_t Length)> CallAfter) {
-    FHU::ScopedSignalMaskWithUniqueLock CodeInvalidationLock(CodeInvalidationMutex);
+  void ContextImpl::InvalidateGuestCodeRange(FEXCore::Core::InternalThreadState *Thread, uint64_t Start, uint64_t Length, CodeRangeInvalidationFn CallAfter) {
+    // Potential deferred since Thread might not be valid.
+    // Thread object isn't valid very early in frontend's initialization.
+    // To be more optimal the frontend should provide this code with a valid Thread object earlier.
+    ScopedPotentialDeferredSignalWithForkableUniqueLock lk(CodeInvalidationMutex, Thread);
 
     InvalidateGuestCodeRangeInternal(this, Start, Length);
     CallAfter(Start, Length);
@@ -1229,6 +1256,7 @@ namespace FEXCore::Context {
   void ContextImpl::MarkMemoryShared() {
     if (!IsMemoryShared) {
       IsMemoryShared = true;
+      UpdateAtomicTSOEmulationConfig();
 
       if (Config.TSOAutoMigration) {
         std::lock_guard<std::mutex> lkThreads(ThreadCreationMutex);
@@ -1247,7 +1275,7 @@ namespace FEXCore::Context {
   }
 
   void ContextImpl::ThreadAddBlockLink(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestDestination, uintptr_t HostLink, const std::function<void()> &delinker) {
-    std::shared_lock lk(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex);
+    ScopedDeferredSignalWithForkableSharedLock lk(static_cast<ContextImpl*>(Thread->CTX)->CodeInvalidationMutex, Thread);
 
     Thread->LookupCache->AddBlockLink(GuestDestination, HostLink, delinker);
   }
@@ -1261,7 +1289,7 @@ namespace FEXCore::Context {
     Thread->LookupCache->Erase(GuestRIP);
   }
 
-  CustomIRResult ContextImpl::AddCustomIREntrypoint(uintptr_t Entrypoint, std::function<void(uintptr_t Entrypoint, FEXCore::IR::IREmitter *)> Handler, void *Creator, void *Data) {
+  CustomIRResult ContextImpl::AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void *Creator, void *Data) {
     LOGMAN_THROW_A_FMT(Config.Is64BitMode || !(Entrypoint >> 32), "64-bit Entrypoint in 32-bit mode {:x}", Entrypoint);
 
     std::unique_lock lk(CustomIRMutex);
@@ -1282,63 +1310,18 @@ namespace FEXCore::Context {
 
     std::scoped_lock lk(CustomIRMutex);
 
-    InvalidateGuestCodeRange(Entrypoint, 1, [this](uint64_t Entrypoint, uint64_t) {
+    InvalidateGuestCodeRange(nullptr, Entrypoint, 1, [this](uint64_t Entrypoint, uint64_t) {
       CustomIRHandlers.erase(Entrypoint);
     });
   }
 
-  // Debug interface
-  void Context::CompileRIP(FEXCore::Core::InternalThreadState *Thread, uint64_t RIP) {
-    uint64_t RIPBackup = Thread->CurrentFrame->State.rip;
-    Thread->CurrentFrame->State.rip = RIP;
-
-    auto CTX = static_cast<ContextImpl*>(Thread->CTX);
-
-    // Erase the RIP from all the storage backings if it exists
-    CTX->ThreadRemoveCodeEntry(Thread, RIP);
-
-    // We don't care if compilation passes or not
-    CTX->CompileBlock(Thread->CurrentFrame, RIP);
-
-    Thread->CurrentFrame->State.rip = RIPBackup;
-  }
-
-  uint64_t ContextImpl::GetThreadCount() const {
-    return Threads.size();
-  }
-
-  FEXCore::Core::RuntimeStats *ContextImpl::GetRuntimeStatsForThread(uint64_t Thread) {
-    return &Threads[Thread]->Stats;
-  }
-
-  bool ContextImpl::GetDebugDataForRIP(uint64_t RIP, FEXCore::Core::DebugData *Data) {
-    std::lock_guard<std::recursive_mutex> lk(ParentThread->LookupCache->WriteLock);
-    auto it = ParentThread->DebugStore.find(RIP);
-    if (it == ParentThread->DebugStore.end()) {
-      return false;
-    }
-
-    memcpy(Data, it->second.DebugData.get(), sizeof(FEXCore::Core::DebugData));
-    return true;
-  }
-
-  bool ContextImpl::FindHostCodeForRIP(uint64_t RIP, uint8_t **Code) {
-    uintptr_t HostCode = ParentThread->LookupCache->FindBlock(RIP);
-    if (!HostCode) {
-      return false;
-    }
-
-    *Code = reinterpret_cast<uint8_t*>(HostCode);
-    return true;
-  }
-
   uint64_t HandleSyscall(FEXCore::HLE::SyscallHandler *Handler, FEXCore::Core::CpuStateFrame *Frame, FEXCore::HLE::SyscallArguments *Args) {
     uint64_t Result{};
     Result = Handler->HandleSyscall(Frame, Args);
     return Result;
   }
 
-  IR::AOTIRCacheEntry *ContextImpl::LoadAOTIRCacheEntry(const std::string &filename) {
+  IR::AOTIRCacheEntry *ContextImpl::LoadAOTIRCacheEntry(const fextl::string &filename) {
     auto rv = IRCaptureCache.LoadAOTIRCacheEntry(filename);
     if (DebugServer) {
       DebugServer->AlertLibrariesChanged();
@@ -1353,11 +1336,13 @@ namespace FEXCore::Context {
     }
   }
 
-  void ContextImpl::AppendThunkDefinitions(std::vector<FEXCore::IR::ThunkDefinition> const& Definitions) {
-    ThunkHandler->AppendThunkDefinitions(Definitions);
+  void ContextImpl::AppendThunkDefinitions(fextl::vector<FEXCore::IR::ThunkDefinition> const& Definitions) {
+    if (ThunkHandler) {
+      ThunkHandler->AppendThunkDefinitions(Definitions);
+    }
   }
 
-  void ContextImpl::ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, std::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) {
+  void ContextImpl::ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, fextl::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) {
     Thread->FrontendDecoder->SetExternalBranches(ExternalBranches);
     Thread->FrontendDecoder->SetSectionMaxAddress(SectionMaxAddress);
   }

External/FEXCore/Source/Interface/Core/Core.h

@@ -1,23 +0,0 @@
-#pragma once
-
-namespace FEXCore {
-  class CodeLoader;
-}
-
-namespace FEXCore::Context {
-  class ContextImpl;
-}
-
-namespace FEXCore::CPU {
-
-  /**
-   * @brief Create the CPU core backend for the context passed in
-   *
-   * @param CTX
-   *
-   * @return true if core was able to be create
-   */
-  bool CreateCPUCore(FEXCore::Context::ContextImpl *CTX);
-
-  bool LoadCode(FEXCore::Context::ContextImpl *CTX, FEXCore::CodeLoader *Loader);
-}

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp

@@ -1,7 +1,6 @@
 #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/LookupCache.h"
 
-#include "Interface/Core/ArchHelpers/MContext.h"
 #include "Interface/Core/Dispatcher/Arm64Dispatcher.h"
 #include "Interface/Core/Interpreter/InterpreterClass.h"
 
@@ -12,6 +11,7 @@
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/X86Enums.h>
 #include <FEXCore/Debug/InternalThreadState.h>
+#include <FEXCore/fextl/memory.h>
 #include <FEXHeaderUtils/Syscalls.h>
 
 #include <array>
@@ -28,7 +28,6 @@
 #include <code-buffer-vixl.h>
 #include <platform-vixl.h>
 
-#include <sys/syscall.h>
 #include <unistd.h>
 
 namespace FEXCore::CPU {
@@ -130,13 +129,6 @@ void Arm64Dispatcher::EmitDispatcher() {
     and_(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, RipReg.R(), ARMEmitter::Reg::r3);
   }
 
-#ifdef VIXL_SIMULATOR
-  // VIXL simulator can't run syscalls.
-  constexpr bool SignalSafeCompile = false;
-#else
-  constexpr bool SignalSafeCompile = true;
-#endif
-
   ARMEmitter::ForwardLabel NoBlock;
 
   {
@@ -184,7 +176,7 @@ void Arm64Dispatcher::EmitDispatcher() {
   {
     ThreadStopHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
     ThreadStopHandlerAddress = GetCursorAddress<uint64_t>();
 
@@ -198,26 +190,11 @@ void Arm64Dispatcher::EmitDispatcher() {
   {
     ExitFunctionLinkerAddress = GetCursorAddress<uint64_t>();
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
-    if (SignalSafeCompile) {
-      // When compiling code, mask all signals to reduce the chance of reentrant allocations
-      // Args:
-      // X0: SETMASK
-      // X1: Pointer to mask value (uint64_t)
-      // X2: Pointer to old mask value (uint64_t)
-      // X3: Size of mask, sizeof(uint64_t)
-      // X8: Syscall
-
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, ~0ULL);
-      stp<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, ARMEmitter::Reg::rsp, -16);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, SIG_SETMASK);
-      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, ARMEmitter::Reg::rsp, 0);
-      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::rsp, 0);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, 8);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r8, SYS_rt_sigprocmask);
-      svc(0);
-    }
+    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
+    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
 
     mov(ARMEmitter::XReg::x0, STATE);
     mov(ARMEmitter::XReg::x1, ARMEmitter::XReg::lr);
@@ -229,26 +206,17 @@ void Arm64Dispatcher::EmitDispatcher() {
     blr(ARMEmitter::Reg::r2);
 #endif
 
-    if (SignalSafeCompile) {
-      // Now restore the signal mask
-      // Living in the same location
-
-      mov(ARMEmitter::XReg::x4, ARMEmitter::XReg::x0);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, SIG_SETMASK);
-      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, ARMEmitter::Reg::rsp, 0);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, 0);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, 8);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r8, SYS_rt_sigprocmask);
-      svc(0);
-
-      // Bring stack back
-      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 16);
-      mov(ARMEmitter::XReg::x0, ARMEmitter::XReg::x4);
-    }
-
     if (config.StaticRegisterAllocation)
       FillStaticRegs();
 
+    ldr(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    subs(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x1, ARMEmitter::XReg::x1, 1);
+    str(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+
+    // Trigger segfault if any deferred signals are pending
+    ldr(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
+    str(ARMEmitter::XReg::zr, ARMEmitter::XReg::x1, 0);
+
     br(ARMEmitter::Reg::r0);
   }
 
@@ -257,29 +225,11 @@ void Arm64Dispatcher::EmitDispatcher() {
     Bind(&NoBlock);
 
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
-    if (SignalSafeCompile) {
-      // When compiling code, mask all signals to reduce the chance of reentrant allocations
-      // Args:
-      // X0: SETMASK
-      // X1: Pointer to mask value (uint64_t)
-      // X2: Pointer to old mask value (uint64_t)
-      // X3: Size of mask, sizeof(uint64_t)
-      // X8: Syscall
-
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, ~0ULL);
-      stp<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::x0, ARMEmitter::XReg::x2, ARMEmitter::Reg::rsp, -16);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, SIG_SETMASK);
-      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, ARMEmitter::Reg::rsp, 0);
-      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, ARMEmitter::Reg::rsp, 0);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, 8);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r8, SYS_rt_sigprocmask);
-      svc(0);
-
-      // Reload x2 to bring back RIP
-      ldr(ARMEmitter::XReg::x2, ARMEmitter::Reg::rsp, 8);
-    }
+    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    add(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
+    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
 
     ldr(ARMEmitter::XReg::x0, &l_CTX);
     mov(ARMEmitter::XReg::x1, STATE);
@@ -292,23 +242,17 @@ void Arm64Dispatcher::EmitDispatcher() {
     blr(ARMEmitter::Reg::r3); // { CTX, Frame, RIP}
 #endif
 
-    if (SignalSafeCompile) {
-      // Now restore the signal mask
-      // Living in the same location
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, SIG_SETMASK);
-      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, ARMEmitter::Reg::rsp, 0);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r2, 0);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r3, 8);
-      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r8, SYS_rt_sigprocmask);
-      svc(0);
-
-      // Bring stack back
-      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, 16);
-    }
-
     if (config.StaticRegisterAllocation)
       FillStaticRegs();
 
+    ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+    subs(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::x0, ARMEmitter::XReg::x0, 1);
+    str(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount));
+
+    // Trigger segfault if any deferred signals are pending
+    ldr(TMP1, STATE, offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress));
+    str(ARMEmitter::XReg::zr, TMP1, 0);
+
     b(&LoopTop);
   }
 
@@ -334,7 +278,7 @@ void Arm64Dispatcher::EmitDispatcher() {
     GuestSignal_SIGILL = GetCursorAddress<uint64_t>();
 
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
     hlt(0);
   }
@@ -345,7 +289,7 @@ void Arm64Dispatcher::EmitDispatcher() {
     GuestSignal_SIGTRAP  = GetCursorAddress<uint64_t>();
 
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
     brk(0);
   }
@@ -356,20 +300,28 @@ void Arm64Dispatcher::EmitDispatcher() {
     GuestSignal_SIGSEGV = GetCursorAddress<uint64_t>();
 
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
     // hlt/udf = SIGILL
     // brk = SIGTRAP
     // ??? = SIGSEGV
     // Force a SIGSEGV by loading zero
-    LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, 0);
-    ldr(ARMEmitter::XReg::x1, ARMEmitter::Reg::r1);
+    if (CTX->ExitOnHLTEnabled()) {
+      ldr(ARMEmitter::XReg::x0, STATE_PTR(CpuStateFrame, ReturningStackLocation));
+      add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::r0, 0);
+      PopCalleeSavedRegisters();
+      ret();
+    }
+    else {
+      LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, 0);
+      ldr(ARMEmitter::XReg::x1, ARMEmitter::Reg::r1);
+    }
   }
 
   {
     ThreadPauseHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
     if (config.StaticRegisterAllocation)
-      SpillStaticRegs();
+      SpillStaticRegs(TMP1);
 
     ThreadPauseHandlerAddress = GetCursorAddress<uint64_t>();
     // We are pausing, this means the frontend should be waiting for this thread to idle
@@ -446,7 +398,7 @@ void Arm64Dispatcher::EmitDispatcher() {
     LUDIVHandlerAddress = GetCursorAddress<uint64_t>();
 
     PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
-    SpillStaticRegs();
+    SpillStaticRegs(ARMEmitter::Reg::r3);
 
     ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LUDIV));
 #ifdef VIXL_SIMULATOR
@@ -468,7 +420,7 @@ void Arm64Dispatcher::EmitDispatcher() {
     LDIVHandlerAddress = GetCursorAddress<uint64_t>();
 
     PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
-    SpillStaticRegs();
+    SpillStaticRegs(ARMEmitter::Reg::r3);
 
     ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LDIV));
 #ifdef VIXL_SIMULATOR
@@ -490,7 +442,7 @@ void Arm64Dispatcher::EmitDispatcher() {
     LUREMHandlerAddress = GetCursorAddress<uint64_t>();
 
     PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
-    SpillStaticRegs();
+    SpillStaticRegs(ARMEmitter::Reg::r3);
 
     ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LUREM));
 #ifdef VIXL_SIMULATOR
@@ -512,7 +464,7 @@ void Arm64Dispatcher::EmitDispatcher() {
     LREMHandlerAddress = GetCursorAddress<uint64_t>();
 
     PushDynamicRegsAndLR(ARMEmitter::Reg::r3);
-    SpillStaticRegs();
+    SpillStaticRegs(ARMEmitter::Reg::r3);
 
     ldr(ARMEmitter::XReg::x3, STATE_PTR(CpuStateFrame, Pointers.AArch64.LREM));
 
@@ -543,7 +495,7 @@ void Arm64Dispatcher::EmitDispatcher() {
   ClearICache(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
 
   if (CTX->Config.BlockJITNaming()) {
-    std::string Name = "Dispatch_" + std::to_string(FHU::Syscalls::gettid());
+    fextl::string Name = fextl::fmt::format("Dispatch_{}", FHU::Syscalls::gettid());
     CTX->Symbols.Register(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr), Name);
   }
   if (CTX->Config.GlobalJITNaming()) {
@@ -551,8 +503,10 @@ void Arm64Dispatcher::EmitDispatcher() {
   }
 
 #ifdef VIXL_DISASSEMBLER
-  const auto DisasmEnd = GetCursorAddress<const vixl::aarch64::Instruction*>();
-  Disasm.DisassembleBuffer(DisasmBegin, DisasmEnd);
+  if (Disassemble() & FEXCore::Config::Disassemble::DISPATCHER) {
+    const auto DisasmEnd = GetCursorAddress<const vixl::aarch64::Instruction*>();
+    Disasm.DisassembleBuffer(DisasmBegin, DisasmEnd);
+  }
 #endif
 }
 
@@ -626,28 +580,6 @@ size_t Arm64Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) {
   return UsedBytes;
 }
 
-void Arm64Dispatcher::SpillSRA(FEXCore::Core::InternalThreadState *Thread, void *ucontext, uint32_t IgnoreMask) {
-  for (size_t i = 0; i < SRA64.size(); i++) {
-    if (IgnoreMask & (1U << SRA64[i].Idx())) {
-      // Skip this one, it's already spilled
-      continue;
-    }
-    Thread->CurrentFrame->State.gregs[i] = ArchHelpers::Context::GetArmReg(ucontext, SRA64[i].Idx());
-  }
-
-  if (EmitterCTX->HostFeatures.SupportsAVX) {
-    for (size_t i = 0; i < SRAFPR.size(); i++) {
-      auto FPR = ArchHelpers::Context::GetArmFPR(ucontext, SRAFPR[i].Idx());
-      memcpy(&Thread->CurrentFrame->State.xmm.avx.data[i][0], &FPR, sizeof(__uint128_t));
-    }
-  } else {
-    for (size_t i = 0; i < SRAFPR.size(); i++) {
-      auto FPR = ArchHelpers::Context::GetArmFPR(ucontext, SRAFPR[i].Idx());
-      memcpy(&Thread->CurrentFrame->State.xmm.sse.data[i][0], &FPR, sizeof(__uint128_t));
-    }
-  }
-}
-
 void Arm64Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) {
   // Setup dispatcher specific pointers that need to be accessed from JIT code
   {
@@ -672,8 +604,8 @@ void Arm64Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thr
   }
 }
 
-std::unique_ptr<Dispatcher> Dispatcher::CreateArm64(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config) {
-  return std::make_unique<Arm64Dispatcher>(CTX, Config);
+fextl::unique_ptr<Dispatcher> Dispatcher::CreateArm64(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config) {
+  return fextl::make_unique<Arm64Dispatcher>(CTX, Config);
 }
 
 }

External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.h

@@ -30,8 +30,25 @@ class Arm64Dispatcher final : public Dispatcher, public Arm64Emitter {
 
   void EmitDispatcher();
 
-  protected:
-    void SpillSRA(FEXCore::Core::InternalThreadState *Thread, void *ucontext, uint32_t IgnoreMask) override;
+  uint16_t GetSRAGPRCount() const override {
+    return StaticRegisters.size();
+  }
+
+  uint16_t GetSRAFPRCount() const override {
+    return StaticFPRegisters.size();
+  }
+
+  void GetSRAGPRMapping(uint8_t Mapping[16]) const override {
+    for (size_t i = 0; i < StaticRegisters.size(); ++i) {
+      Mapping[i] = StaticRegisters[i].Idx();
+    }
+  }
+
+  void GetSRAFPRMapping(uint8_t Mapping[16]) const override {
+    for (size_t i = 0; i < StaticFPRegisters.size(); ++i) {
+      Mapping[i] = StaticFPRegisters[i].Idx();
+    }
+  }
 
   private:
     // Long division helpers

External/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.h

@@ -1,14 +1,13 @@
 #pragma once
 
 #include <FEXCore/Core/CPUBackend.h>
-#include "Interface/Core/ArchHelpers/MContext.h"
+#include <FEXCore/fextl/memory.h>
 
 #include <cstdint>
 #include <signal.h>
 #include <stddef.h>
 #include <stack>
 #include <tuple>
-#include <vector>
 
 namespace FEXCore {
 struct GuestSigAction;
@@ -57,14 +56,6 @@ public:
   uint64_t Start{};
   uint64_t End{};
 
-  bool HandleGuestSignal(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext, GuestSigAction *GuestAction, stack_t *GuestStack);
-  bool HandleSIGILL(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext);
-  bool HandleSignalPause(FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext);
-
-  bool IsAddressInDispatcher(uint64_t Address) const {
-    return Address >= Start && Address < End;
-  }
-
   virtual void InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) = 0;
 
   // These are across all arches for now
@@ -74,8 +65,8 @@ public:
   virtual size_t GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) = 0;
   virtual size_t GenerateInterpreterTrampoline(uint8_t *CodeBuffer) = 0;
 
-  static std::unique_ptr<Dispatcher> CreateX86(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config);
-  static std::unique_ptr<Dispatcher> CreateArm64(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config);
+  static fextl::unique_ptr<Dispatcher> CreateX86(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config);
+  static fextl::unique_ptr<Dispatcher> CreateArm64(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config);
 
   virtual void ExecuteDispatch(FEXCore::Core::CpuStateFrame *Frame) {
     DispatchPtr(Frame);
@@ -85,80 +76,28 @@ public:
     CallbackPtr(Frame, RIP);
   }
 
+  virtual uint16_t GetSRAGPRCount() const {
+    return 0U;
+  }
+
+  virtual uint16_t GetSRAFPRCount() const {
+    return 0U;
+  }
+
+  virtual void GetSRAGPRMapping(uint8_t Mapping[16]) const {
+  }
+
+  virtual void GetSRAFPRMapping(uint8_t Mapping[16]) const {
+  }
+
+  const DispatcherConfig& GetConfig() const { return config; }
+
 protected:
   Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &Config)
     : CTX {ctx}
     , config {Config}
     {}
 
-  uint64_t ReconstructRIPFromContext(FEXCore::Core::CpuStateFrame *Frame, void *ucontext) const;
-  void RestoreFrame_x64(ArchHelpers::Context::ContextBackup* Context, FEXCore::Core::CpuStateFrame *Frame, void *ucontext);
-  void RestoreFrame_ia32(ArchHelpers::Context::ContextBackup* Context, FEXCore::Core::CpuStateFrame *Frame, void *ucontext);
-  void RestoreRTFrame_ia32(ArchHelpers::Context::ContextBackup* Context, FEXCore::Core::CpuStateFrame *Frame, void *ucontext);
-
-  ///< Setup the signal frame for x64.
-  uint64_t SetupFrame_x64(FEXCore::Core::InternalThreadState *Thread, ArchHelpers::Context::ContextBackup* ContextBackup, FEXCore::Core::CpuStateFrame *Frame,
-    int Signal, siginfo_t *HostSigInfo, void *ucontext,
-    GuestSigAction *GuestAction, stack_t *GuestStack,
-    uint64_t NewGuestSP, const uint32_t eflags);
-
-  ///< Setup the signal frame for a 32-bit signal without SA_SIGINFO.
-  uint64_t SetupFrame_ia32(ArchHelpers::Context::ContextBackup* ContextBackup, FEXCore::Core::CpuStateFrame *Frame,
-    int Signal, siginfo_t *HostSigInfo, void *ucontext,
-    GuestSigAction *GuestAction, stack_t *GuestStack,
-    uint64_t NewGuestSP, const uint32_t eflags);
-
-  ///< Setup the signal frame for a 32-bit signal with SA_SIGINFO.
-  uint64_t SetupRTFrame_ia32(ArchHelpers::Context::ContextBackup* ContextBackup, FEXCore::Core::CpuStateFrame *Frame,
-    int Signal, siginfo_t *HostSigInfo, void *ucontext,
-    GuestSigAction *GuestAction, stack_t *GuestStack,
-    uint64_t NewGuestSP, const uint32_t eflags);
-
-  ArchHelpers::Context::ContextBackup* StoreThreadState(FEXCore::Core::InternalThreadState *Thread, int Signal, void *ucontext);
-  enum class RestoreType {
-    TYPE_REALTIME, ///< Signal restore type is from a `realtime` signal.
-    TYPE_NONREALTIME, ///< Signal restore type is from a `non-realtime` signal.
-    TYPE_PAUSE, ///< Signal restore type is from a GDB pause event.
-  };
-
-  /*
-   * Signal frames on 32-bit architecture needs to match exactly how the kernel generates the frame.
-   * This is because large parts of the signal frame definition is part of the UAPI.
-   * This means that when FEX sets up the signal frame, it needs to match the UAPI stack setup.
-   *
-   * The two signal stack frame types below describe the two different 32-bit frame types.
-   */
-
-  // The 32-bit non-realtime signal frame.
-  // This frame type is used when the guest signal is used without the `SA_SIGINFO` flag.
-  struct SigFrame_i32 {
-    uint32_t pretcode; ///< sigreturn return branch point.
-    int32_t Signal; ///< The signal hit.
-    FEXCore::x86::sigcontext sc; ///< The signal context.
-    x86::_libc_fpstate fpstate_unused; ///< Unused fpstate. Retained for backwards compatibility.
-    uint32_t extramask[1]; ///< Upper 32-bits of the signal mask. Lower 32-bits is in the sigcontext.
-    char retcode[8]; ///< Unused but needs to be filled. GDB seemingly uses as a debug marker.
-    ///< FP state now follows after this.
-  };
-
-  // The 32-bit realtime signal frame.
-  // This frame type is used when the guest signal is used with the `SA_SIGINFO` flag.
-  struct RTSigFrame_i32 {
-    uint32_t pretcode; ///< sigreturn return branch point.
-    int32_t Signal; ///< The signal hit.
-    uint32_t pinfo; ///< Pointer to siginfo_t
-    uint32_t puc; ///< Pointer to ucontext_t
-    FEXCore::x86::siginfo_t info;
-    FEXCore::x86::ucontext_t uc;
-    char retcode[8]; ///< Unused but needs to be filled. GDB seemingly uses as a debug marker.
-    ///< FP state now follows after this.
-  };
-
-  void RestoreThreadState(FEXCore::Core::InternalThreadState *Thread, void *ucontext, RestoreType Type);
-  std::stack<uint64_t, std::vector<uint64_t>> SignalFrames;
-
-  virtual void SpillSRA(FEXCore::Core::InternalThreadState *Thread, void *ucontext, uint32_t IgnoreMask) {}
-
   FEXCore::Context::ContextImpl *CTX;
   DispatcherConfig config;
 

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.cpp

@@ -1,3 +1,4 @@
+#include "FEXCore/Utils/AllocatorHooks.h"
 #include "Interface/Core/LookupCache.h"
 
 #include "Interface/Core/Dispatcher/X86Dispatcher.h"
@@ -11,14 +12,14 @@
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/Allocator.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
 #include <FEXHeaderUtils/Syscalls.h>
 
 #include <cmath>
 #include <memory>
 #include <stddef.h>
 #include <stdint.h>
-#include <sys/mman.h>
-#include <xbyak/xbyak.h>
 
 #define STATE_PTR(STATE_TYPE, FIELD) \
   [STATE + offsetof(FEXCore::Core::STATE_TYPE, FIELD)]
@@ -30,7 +31,7 @@ static constexpr size_t MAX_DISPATCHER_CODE_SIZE = 4096;
 X86Dispatcher::X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const DispatcherConfig &config)
   : Dispatcher(ctx, config)
   , Xbyak::CodeGenerator(MAX_DISPATCHER_CODE_SIZE,
-      FEXCore::Allocator::mmap(nullptr, MAX_DISPATCHER_CODE_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0),
+      FEXCore::Allocator::VirtualAlloc(MAX_DISPATCHER_CODE_SIZE, true),
       nullptr) {
 
   LOGMAN_THROW_AA_FMT(!config.StaticRegisterAllocation, "X86 dispatcher does not support SRA");
@@ -169,36 +170,11 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const Dispatche
     ret();
   }
 
-  constexpr bool SignalSafeCompile = true;
   // Block creation
   {
     L(NoBlock);
 
-    if (SignalSafeCompile) {
-      // When compiling code, mask all signals to reduce the chance of reentrant allocations
-      // RDI: SETMASK
-      // RSI: Pointer to mask value (uint64_t)
-      // RDX: Pointer to old mask value (uint64_t)
-      // R10: Size of mask, sizeof(uint64_t)
-      // RAX: Syscall
-
-      // Backup rdx
-      mov(r9, rdx);
-
-      mov(rdi, ~0ULL);
-      sub(rsp, 16);
-      mov(qword [rsp], rdi);
-      mov(qword [rsp + 8], rdi);
-
-      mov(rdi, SIG_SETMASK);
-      mov(rsi, rsp);
-      mov(rdx, rsp);
-      mov(r10, 8);
-      mov(rax, SYS_rt_sigprocmask);
-      syscall();
-
-      mov(rdx, r9);
-    }
+    inc(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
 
     // {rdi, rsi, rdx}
     mov(rdi, reinterpret_cast<uint64_t>(CTX));
@@ -207,24 +183,15 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const Dispatche
 
     call(rax);
 
-    if (SignalSafeCompile) {
-      // Now restore the signal mask
-      // Living in the same location
-      // Backup rdx
-      mov(r9, rdx);
+    dec(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
 
-      mov(rdi, SIG_SETMASK);
-      mov(rsi, rsp);
-      mov(rdx, 0); // Don't care about result
-      mov(r10, 8);
-      mov(rax, SYS_rt_sigprocmask);
-      syscall();
+    Label AfterStore;
+    // Skip the deferred fault address if the refcount isn't zero
+    jne(AfterStore);
+    mov(rax, qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress)]);
+    mov(rax, qword [rax]);
 
-      // Bring stack back
-      add(rsp, 16);
-
-      mov(rdx, r9);
-    }
+    L(AfterStore);
 
     // rdx already contains RIP here
     jmp(LoopTop);
@@ -232,31 +199,7 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const Dispatche
 
   {
     ExitFunctionLinkerAddress = getCurr<uint64_t>();
-    if (SignalSafeCompile) {
-      // When compiling code, mask all signals to reduce the chance of reentrant allocations
-      // RDI: SETMASK
-      // RSI: Pointer to mask value (uint64_t)
-      // RDX: Pointer to old mask value (uint64_t)
-      // R10: Size of mask, sizeof(uint64_t)
-      // RAX: Syscall
-
-      // Backup rax
-      mov(r9, rax);
-
-      mov(rdi, ~0ULL);
-      sub(rsp, 16);
-      mov(qword [rsp], rdi);
-      mov(qword [rsp + 8], rdi);
-
-      mov(rdi, SIG_SETMASK);
-      mov(rsi, rsp);
-      mov(rdx, rsp);
-      mov(r10, 8);
-      mov(rax, SYS_rt_sigprocmask);
-      syscall();
-
-      mov(rax, r9);
-    }
+    inc(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
 
     // {rdi, rsi}
     mov(rdi, STATE);
@@ -264,27 +207,17 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const Dispatche
 
     call(qword STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionLink));
 
-    if (SignalSafeCompile) {
-      // Now restore the signal mask
-      // Living in the same location
-      // Backup rax
-      mov(r9, rax);
+    dec(qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalRefCount)]);
 
-      mov(rdi, SIG_SETMASK);
-      mov(rsi, rsp);
-      mov(rdx, 0); // Don't care about result
-      mov(r10, 8);
-      mov(rax, SYS_rt_sigprocmask);
-      syscall();
+    Label AfterStore;
+    // Skip the deferred fault address if the refcount isn't zero
+    jne(AfterStore);
+    mov(rbx, qword [STATE + offsetof(FEXCore::Core::CPUState, DeferredSignalFaultAddress)]);
+    mov(qword [rbx], rbx);
 
-      // Bring stack back
-      add(rsp, 16);
+    L(AfterStore);
 
-      jmp(r9);
-    }
-    else {
-      jmp(rax);
-    }
+    jmp(rax);
   }
 
   {
@@ -407,7 +340,7 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const Dispatche
   End = Start + getSize();
 
   if (CTX->Config.BlockJITNaming()) {
-    std::string Name = "Dispatch_" + std::to_string(FHU::Syscalls::gettid());
+    fextl::string Name = fextl::fmt::format("Dispatch_{}", FHU::Syscalls::gettid());
     CTX->Symbols.Register(reinterpret_cast<void*>(Start), End-Start, Name);
   }
   if (CTX->Config.GlobalJITNaming()) {
@@ -416,15 +349,13 @@ X86Dispatcher::X86Dispatcher(FEXCore::Context::ContextImpl *ctx, const Dispatche
 
 }
 
-// Used by GenerateGDBPauseCheck, GenerateInterpreterTrampoline
-static thread_local Xbyak::CodeGenerator emit(1, &emit); // actual emit target set with setNewBuffer
-
 size_t X86Dispatcher::GenerateGDBPauseCheck(uint8_t *CodeBuffer, uint64_t GuestRIP) {
   using namespace Xbyak;
   using namespace Xbyak::util;
 
+  Xbyak::CodeGenerator emit(1, &emit); // actual emit target set with setNewBuffer
   emit.setNewBuffer(CodeBuffer, MaxGDBPauseCheckSize);
-  
+
   Label RunBlock;
 
   // If we have a gdb server running then run in a less efficient mode that checks if we need to exit
@@ -457,10 +388,11 @@ size_t X86Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) {
   using namespace Xbyak;
   using namespace Xbyak::util;
 
+  Xbyak::CodeGenerator emit(1, &emit); // actual emit target set with setNewBuffer
   emit.setNewBuffer(CodeBuffer, MaxInterpreterTrampolineSize);
 
   Label InlineIRData;
-  
+
   emit.mov(rdi, STATE);
   emit.lea(rsi, ptr[rip + InlineIRData]);
   emit.call(qword STATE_PTR(CpuStateFrame, Pointers.Interpreter.FragmentExecuter));
@@ -475,7 +407,7 @@ size_t X86Dispatcher::GenerateInterpreterTrampoline(uint8_t *CodeBuffer) {
 }
 
 X86Dispatcher::~X86Dispatcher() {
-  FEXCore::Allocator::munmap(top_, MAX_DISPATCHER_CODE_SIZE);
+  FEXCore::Allocator::VirtualFree(top_, MAX_DISPATCHER_CODE_SIZE);
 }
 
 void X86Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Thread) {
@@ -499,8 +431,8 @@ void X86Dispatcher::InitThreadPointers(FEXCore::Core::InternalThreadState *Threa
   }
 }
 
-std::unique_ptr<Dispatcher> Dispatcher::CreateX86(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config) {
-  return std::make_unique<X86Dispatcher>(CTX, Config);
+fextl::unique_ptr<Dispatcher> Dispatcher::CreateX86(FEXCore::Context::ContextImpl *CTX, const DispatcherConfig &Config) {
+  return fextl::make_unique<X86Dispatcher>(CTX, Config);
 }
 
 }

External/FEXCore/Source/Interface/Core/Dispatcher/X86Dispatcher.h

@@ -1,9 +1,24 @@
 #pragma once
 
+#include <FEXCore/fextl/list.h>
+#include <FEXCore/fextl/unordered_map.h>
+#include <FEXCore/fextl/unordered_set.h>
+
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 
 #define XBYAK64
+#define XBYAK_CUSTOM_ALLOC
+#define XBYAK_CUSTOM_MALLOC FEXCore::Allocator::malloc
+#define XBYAK_CUSTOM_FREE FEXCore::Allocator::free
+#define XBYAK_CUSTOM_SETS
+#define XBYAK_STD_UNORDERED_SET fextl::unordered_set
+#define XBYAK_STD_UNORDERED_MAP fextl::unordered_map
+#define XBYAK_STD_UNORDERED_MULTIMAP fextl::unordered_multimap
+#define XBYAK_STD_LIST fextl::list
+#define XBYAK_NO_EXCEPTION
+
 #include <xbyak/xbyak.h>
+#include <xbyak/xbyak_util.h>
 
 namespace FEXCore::Core {
   struct InternalThreadState;

External/FEXCore/Source/Interface/Core/Frontend.cpp

@@ -7,22 +7,20 @@ $end_info$
 
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Frontend.h"
+#include "Interface/Core/X86Tables/X86Tables.h"
 
 #include <array>
-#include <assert.h>
 #include <algorithm>
 #include <cstring>
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
 #include <FEXCore/Utils/Telemetry.h>
+#include <FEXCore/fextl/set.h>
 #include <FEXHeaderUtils/TypeDefines.h>
-#include <set>
-#include <sys/mman.h>
 
 namespace FEXCore::Frontend {
 #include "Interface/Core/VSyscall/VSyscall.inc"
@@ -240,8 +238,19 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     Operand->Data.SIB.Scale = 1 << SIB.scale;
 
     // The invalid encoding types are described at Table 1-12. "promoted nsigned is always non-zero"
-    Operand->Data.SIB.Index = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X ? 1 : 0, SIB.index, false, false, false, false, 0b100);
-    Operand->Data.SIB.Base  = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
+    {
+      // If we have a VSIB byte (as opposed to SIB), then the index register is a vector.
+      const bool IsIndexVector = (DecodeInst->TableInfo->Flags & InstFlags::FLAGS_VEX_VSIB) != 0;
+      if (IsIndexVector) {
+        DecodeInst->Flags |= X86Tables::DecodeFlags::FLAG_VSIB_BYTE;
+      }
+
+      const uint8_t IndexREX = (DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_X) != 0 ? 1 : 0;
+      const uint8_t BaseREX = (DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B) != 0 ? 1 : 0;
+
+      Operand->Data.SIB.Index = MapModRMToReg(IndexREX, SIB.index, false, false, IsIndexVector, false, 0b100);
+      Operand->Data.SIB.Base  = MapModRMToReg(BaseREX, SIB.base, false, false, false, false, ModRM.mod == 0 ? 0b101 : 16);
+    }
 
     LOGMAN_THROW_AA_FMT(Displacement <= 4, "Number of bytes should be <= 4 for literal src");
 
@@ -304,18 +313,19 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
                                        (Options.w && CTX->Config.Is64BitMode);
   const bool HasNarrowingDisplacement = (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST) != 0;
 
-  bool HasXMMSrc = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_GPR) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_SRC);
-  bool HasXMMDst = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_GPR) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_DST);
-  bool HasMMSrc = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_GPR) &&
-    HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_SRC);
-  bool HasMMDst = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_XMM_FLAGS) &&
-    !HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_GPR) &&
-    HAS_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_MMX_DST);
+  const bool HasXMMFlags = (Info->Flags & InstFlags::FLAGS_XMM_FLAGS) != 0;
+  bool HasXMMSrc = HasXMMFlags &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_SRC_GPR) &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_SRC);
+  bool HasXMMDst = HasXMMFlags &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_DST_GPR) &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_DST);
+  bool HasMMSrc = HasXMMFlags &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_SRC_GPR) &&
+    HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_SRC);
+  bool HasMMDst = HasXMMFlags &&
+    !HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_DST_GPR) &&
+    HAS_XMM_SUBFLAG(Info->Flags, InstFlags::FLAGS_SF_MMX_DST);
 
   // Is ModRM present via explicit instruction encoded or REX?
   const bool HasMODRM = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM);
@@ -502,7 +512,12 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op,
   if ((Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_VEX_1ST_SRC) != 0) {
     DecodeInst->Src[CurrentSrc].Type = DecodedOperand::OpType::GPR;
     DecodeInst->Src[CurrentSrc].Data.GPR.HighBits = false;
-    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = MapVEXToReg(Options.vvvv, HasXMMSrc);
+
+    // If we have XMM flags at all, then SRC 1 cannot be a GPR. The only case where
+    // this is possible is with BMI1 and BMI2 instructions (which are all GPR-based
+    // and don't use XMM flags)
+    DecodeInst->Src[CurrentSrc].Data.GPR.GPR = MapVEXToReg(Options.vvvv, HasXMMFlags);
+
     ++CurrentSrc;
   }
 
@@ -666,9 +681,6 @@ bool Decoder::NormalOpHeader(FEXCore::X86Tables::X86InstInfo const *Info, uint16
     DecodeInst->ModRM = ModRMByte;
     DecodeInst->DecodedModRM = true;
 
-    FEXCore::X86Tables::ModRMDecoded ModRM;
-    ModRM.Hex = DecodeInst->ModRM;
-
     uint16_t X87Op = ((Op - 0xD8) << 8) | ModRMByte;
     return NormalOp(&X87Ops[X87Op], X87Op);
   }
@@ -952,7 +964,7 @@ bool Decoder::DecodeInstruction(uint64_t PC) {
   }
 
   if (DecodeInst->Dest.IsGPR()) {
-    assert(DecodeInst->Dest.Data.GPR.GPR != FEXCore::X86State::REG_INVALID);
+    LOGMAN_THROW_A_FMT(DecodeInst->Dest.Data.GPR.GPR != FEXCore::X86State::REG_INVALID, "Destination GPR was invalid");
   }
 
   return true;
@@ -1010,15 +1022,13 @@ void Decoder::BranchTargetInMultiblockRange() {
 
       // If we are conditional then a target can be the instruction past the conditional instruction
       uint64_t FallthroughRIP = DecodeInst->PC + DecodeInst->InstSize;
-      if (HasBlocks.find(FallthroughRIP) == HasBlocks.end() &&
-          BlocksToDecode.find(FallthroughRIP) == BlocksToDecode.end()) {
-        BlocksToDecode.emplace(FallthroughRIP);
+      if (!HasBlocks.contains(FallthroughRIP)) {
+        BlocksToDecode.insert(FallthroughRIP);
       }
     }
 
-    if (HasBlocks.find(TargetRIP) == HasBlocks.end() &&
-        BlocksToDecode.find(TargetRIP) == BlocksToDecode.end()) {
-      BlocksToDecode.emplace(TargetRIP);
+    if (!HasBlocks.contains(TargetRIP)) {
+      BlocksToDecode.insert(TargetRIP);
     }
   } else {
     if (ExternalBranches) {
@@ -1108,7 +1118,7 @@ void Decoder::DecodeInstructionsAtEntry(uint8_t const* _InstStream, uint64_t PC,
 
   uint64_t CurrentCodePage = PC & FHU::FEX_PAGE_MASK;
 
-  std::set<uint64_t> CodePages = { CurrentCodePage };
+  fextl::set<uint64_t> CodePages = { CurrentCodePage };
 
   AddContainedCodePage(PC, CurrentCodePage, FHU::FEX_PAGE_SIZE);
 

External/FEXCore/Source/Interface/Core/Frontend.h

@@ -1,14 +1,15 @@
 #pragma once
 
-#include <FEXCore/Debug/X86Tables.h>
+#include "Interface/Core/X86Tables/X86Tables.h"
+
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/Utils/Telemetry.h>
+#include <FEXCore/fextl/set.h>
+#include <FEXCore/fextl/vector.h>
 
 #include <array>
 #include <cstdint>
-#include <set>
 #include <stddef.h>
-#include <vector>
 
 namespace FEXCore::Context {
 class ContextImpl;
@@ -29,7 +30,7 @@ public:
   ~Decoder();
   void DecodeInstructionsAtEntry(uint8_t const* InstStream, uint64_t PC, std::function<void(uint64_t BlockEntry, uint64_t Start, uint64_t Length)> AddContainedCodePage);
 
-  std::vector<DecodedBlocks> const *GetDecodedBlocks() const {
+  fextl::vector<DecodedBlocks> const *GetDecodedBlocks() const {
     return &Blocks;
   }
 
@@ -37,7 +38,7 @@ public:
   uint64_t DecodedMaxAddress {~0ULL};
 
   void SetSectionMaxAddress(uint64_t v) { SectionMaxAddress = v; }
-  void SetExternalBranches(std::set<uint64_t> *v) { ExternalBranches = v; }
+  void SetExternalBranches(fextl::set<uint64_t> *v) { ExternalBranches = v; }
 
   void DelayedDisownBuffer() {
     PoolObject.DelayedDisownBuffer();
@@ -89,10 +90,10 @@ private:
   uint64_t SymbolMinAddress {~0ULL};
   uint64_t SectionMaxAddress {~0ULL};
 
-  std::vector<DecodedBlocks> Blocks;
-  std::set<uint64_t> BlocksToDecode;
-  std::set<uint64_t> HasBlocks;
-  std::set<uint64_t> *ExternalBranches {nullptr};
+  fextl::vector<DecodedBlocks> Blocks;
+  fextl::set<uint64_t> BlocksToDecode;
+  fextl::set<uint64_t> HasBlocks;
+  fextl::set<uint64_t> *ExternalBranches {nullptr};
 
   // ModRM rm decoding
   using DecodeModRMPtr = void (FEXCore::Frontend::Decoder::*)(X86Tables::DecodedOperand *Operand, X86Tables::ModRMDecoded ModRM);

External/FEXCore/Source/Interface/Core/GdbServer.cpp

@@ -8,11 +8,8 @@ $end_info$
 #include <cstdlib>
 #include <cstdio>
 #include <iomanip>
-#include <sstream>
-#include <string>
 #include <memory>
 #include <optional>
-#include <vector>
 #include "Common/SoftFloat.h"
 #include "Common/StringUtils.h"
 #include "Interface/Context/Context.h"
@@ -27,39 +24,45 @@ $end_info$
 #include <FEXCore/HLE/Linux/ThreadManagement.h>
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/Utils/CompilerDefs.h>
+#include <FEXCore/Utils/FileLoading.h>
 #include <FEXCore/Utils/NetStream.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Threads.h>
+#include <FEXCore/fextl/fmt.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/sstream.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/vector.h>
 
 #include <atomic>
 #include <cstring>
+#ifndef _WIN32
 #include <elf.h>
+#include <netdb.h>
+#include <sys/socket.h>
+#endif
 #include <errno.h>
 #include <fcntl.h>
-#include <fstream>
 #include <fmt/format.h>
-#include <netdb.h>
 #include <signal.h>
 #include <stddef.h>
 #include <string_view>
-#include <sys/socket.h>
 #include <sys/stat.h>
 #include <unistd.h>
 #include <utility>
-#include <vector>
 
 #include "GdbServer.h"
 
 namespace FEXCore
 {
-
+#ifndef _WIN32
 void GdbServer::Break(int signal) {
   std::lock_guard lk(sendMutex);
   if (!CommsStream) {
     return;
   }
 
-  const auto str = fmt::format("S{:02x}", signal);
+  const fextl::string str = fextl::fmt::format("S{:02x}", signal);
   SendPacket(*CommsStream, str);
 }
 
@@ -101,7 +104,7 @@ GdbServer::GdbServer(FEXCore::Context::ContextImpl *ctx) : CTX(ctx) {
   StartThread();
 }
 
-static int calculateChecksum(const std::string &packet) {
+static int calculateChecksum(const fextl::string &packet) {
   unsigned char checksum = 0;
   for (const char &c : packet) {
     checksum += c;
@@ -109,8 +112,8 @@ static int calculateChecksum(const std::string &packet) {
   return checksum;
 }
 
-static std::string hexstring(std::istringstream &ss, int delm) {
-  std::string ret;
+static fextl::string hexstring(fextl::istringstream &ss, int delm) {
+  fextl::string ret;
 
   char hexString[3] = {0, 0, 0};
   while (ss.peek() != delm) {
@@ -125,8 +128,8 @@ static std::string hexstring(std::istringstream &ss, int delm) {
   return ret;
 }
 
-static std::string encodeHex(const unsigned char *data, size_t length) {
-  std::ostringstream ss;
+static fextl::string encodeHex(const unsigned char *data, size_t length) {
+  fextl::ostringstream ss;
 
   for (size_t i=0; i < length; i++) {
     ss << std::setfill('0') << std::setw(2) << std::hex << int(data[i]);
@@ -134,26 +137,19 @@ static std::string encodeHex(const unsigned char *data, size_t length) {
   return ss.str();
 }
 
-static std::string getThreadName(uint32_t ThreadID) {
-  const auto ThreadFile = fmt::format("/proc/{}/task/{}/comm", getpid(), ThreadID);
-  std::fstream fs(ThreadFile, std::fstream::in | std::fstream::binary);
-
-  if (fs.is_open()) {
-    std::string ThreadName;
-    fs >> ThreadName;
-    fs.close();
-    return ThreadName;
-  }
-
-  return "<No Name>";
+static fextl::string getThreadName(uint32_t ThreadID) {
+  const auto ThreadFile = fextl::fmt::format("/proc/{}/task/{}/comm", getpid(), ThreadID);
+  fextl::string ThreadName {"<No Name>"};
+  FEXCore::FileLoading::LoadFile(ThreadName, ThreadFile);
+  return ThreadName;
 }
 
 // Packet parser
 // Takes a serial stream and reads a single packet
 // Un-escapes chars, checks the checksum and request a retransmit if it fails.
 // Once the checksum is validated, it acknowledges and returns the packet in a string
-std::string GdbServer::ReadPacket(std::iostream &stream) {
-  std::string packet{};
+fextl::string GdbServer::ReadPacket(std::iostream &stream) {
+  fextl::string packet{};
 
   // The GDB "Remote Serial Protocal" was originally 7bit clean for use on serial ports.
   // Binary data is useally hex encoded. However some later extentions just put
@@ -172,7 +168,7 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
           LogMan::Msg::EFmt("Dropping unexpected data: \"{}\"", packet);
 
         // clear any existing data, must have been a mistake.
-        packet = std::string();
+        packet = fextl::string();
         break;
       case '}': // escape char
       {
@@ -203,8 +199,8 @@ std::string GdbServer::ReadPacket(std::iostream &stream) {
   return "";
 }
 
-static std::string escapePacket(const std::string& packet) {
-  std::ostringstream ss;
+static fextl::string escapePacket(const fextl::string& packet) {
+  fextl::ostringstream ss;
 
   for(const auto &c : packet) {
     switch (c) {
@@ -225,9 +221,9 @@ static std::string escapePacket(const std::string& packet) {
   return ss.str();
 }
 
-void GdbServer::SendPacket(std::ostream &stream, const std::string& packet) {
+void GdbServer::SendPacket(std::ostream &stream, const fextl::string& packet) {
   const auto escaped = escapePacket(packet);
-  const auto str = fmt::format("${}#{:02x}", escaped, calculateChecksum(escaped));
+  const auto str = fextl::fmt::format("${}#{:02x}", escaped, calculateChecksum(escaped));
 
   stream << str << std::flush;
 }
@@ -263,7 +259,7 @@ struct FEX_PACKED GDBContextDefinition {
   uint32_t mxcsr;
 };
 
-std::string GdbServer::readRegs() {
+fextl::string GdbServer::readRegs() {
   GDBContextDefinition GDB{};
   FEXCore::Core::CPUState state{};
 
@@ -311,11 +307,11 @@ std::string GdbServer::readRegs() {
   return encodeHex((unsigned char *)&GDB, sizeof(GDBContextDefinition));
 }
 
-GdbServer::HandledPacketType GdbServer::readReg(const std::string& packet) {
-	size_t addr;
-	auto ss = std::istringstream(packet);
-	ss.get(); // Drop first letter
-	ss >> std::hex >> addr;
+GdbServer::HandledPacketType GdbServer::readReg(const fextl::string& packet) {
+  size_t addr;
+  auto ss = fextl::istringstream(packet);
+  ss.get(); // Drop first letter
+  ss >> std::hex >> addr;
 
   FEXCore::Core::CPUState state{};
 
@@ -395,8 +391,8 @@ GdbServer::HandledPacketType GdbServer::readReg(const std::string& packet) {
   return {"E00", HandledPacketType::TYPE_ACK};
 }
 
-std::string buildTargetXML() {
-  std::ostringstream xml;
+fextl::string buildTargetXML() {
+  fextl::ostringstream xml;
 
   xml << "<?xml version='1.0'?>\n";
   xml << "<!DOCTYPE target SYSTEM 'gdb-target.dtd'>\n";
@@ -448,7 +444,7 @@ std::string buildTargetXML() {
 
       // x87 stack
       for (int i=0; i < 8; i++) {
-          reg("st" + std::to_string(i), "i387_ext", 80);
+        reg(fextl::fmt::format("st{}", i), "i387_ext", 80);
       }
 
       // x87 control
@@ -484,7 +480,7 @@ std::string buildTargetXML() {
 
       // SSE regs
       for (size_t i = 0; i < Core::CPUState::NUM_XMMS; i++) {
-          reg("xmm" + std::to_string(i), "vec128", 128);
+          reg(fextl::fmt::format("xmm{}", i), "vec128", 128);
       }
 
       reg("mxcsr", "int", 32);
@@ -520,8 +516,8 @@ std::string buildTargetXML() {
   return xml.str();
 }
 
-std::string buildOSData() {
-  std::ostringstream xml;
+fextl::string buildOSData() {
+  fextl::ostringstream xml;
 
   xml << "<?xml version='1.0'?>\n";
 
@@ -541,24 +537,27 @@ void GdbServer::buildLibraryMap() {
     return;
   }
 
-  std::ostringstream xml;
+  fextl::ostringstream xml;
 
-  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
-  std::string Line;
+  fextl::string MapsFile;
+  FEXCore::FileLoading::LoadFile(MapsFile, "/proc/self/maps");
+  fextl::istringstream MapsStream(MapsFile);
+
+  fextl::string Line;
 
   struct FileData {
     uint64_t Begin;
   };
 
-  std::map<std::string, std::vector<FileData>> SegmentMaps;
+  fextl::map<fextl::string, fextl::vector<FileData>> SegmentMaps;
 
   // 7ff5dd6d2000-7ff5dd6d3000 rw-p 0000a000 103:0b 1881447                   /usr/lib/x86_64-linux-gnu/libnss_compat.so.2
-  std::string const &RuntimeExecutable = Filename();
-  while (std::getline(fs, Line)) {
-    auto ss = std::istringstream(Line);
-    std::string Tmp;
-    std::string Begin;
-    std::string Name;
+  fextl::string const &RuntimeExecutable = Filename();
+  while (std::getline(MapsStream, Line)) {
+    auto ss = fextl::istringstream(Line);
+    fextl::string Tmp;
+    fextl::string Begin;
+    fextl::string Name;
     std::getline(ss, Begin, '-');
     std::getline(ss, Tmp, ' '); // End
     std::getline(ss, Tmp, ' '); // Perm
@@ -609,18 +608,18 @@ void GdbServer::buildLibraryMap() {
   LibraryMapChanged = false;
 }
 
-GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
-  std::string object;
-  std::string rw;
-  std::string annex;
+GdbServer::HandledPacketType GdbServer::handleXfer(const fextl::string &packet) {
+  fextl::string object;
+  fextl::string rw;
+  fextl::string annex;
   int annex_pid;
   int offset;
   int length;
 
   // Parse Xfer message
   {
-    auto ss = std::istringstream(packet);
-    std::string expectXfer;
+    auto ss = fextl::istringstream(packet);
+    fextl::string expectXfer;
     char expectComma;
 
     std::getline(ss, expectXfer, ':');
@@ -631,7 +630,7 @@ GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
       annex_pid = getpid();
     }
     else {
-      auto ss_pid = std::istringstream(annex);
+      auto ss_pid = fextl::istringstream(annex);
       ss_pid >> std::hex >> annex_pid;
     }
     ss >> std::hex >> offset;
@@ -644,7 +643,7 @@ GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
   }
 
   // Lambda to correctly encode any reply
-  auto encode = [&](std::string data) -> std::string {
+  auto encode = [&](fextl::string data) -> fextl::string {
     if (offset == data.size())
       return "l";
     if (offset >= data.size())
@@ -674,7 +673,7 @@ GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
       auto Threads = CTX->GetThreads();
 
       ThreadString.clear();
-      std::ostringstream ss;
+      fextl::ostringstream ss;
       ss << "<?xml version=\"1.0\"?>\n";
       ss << "<threads>\n";
       for (auto &Thread : *Threads) {
@@ -710,7 +709,7 @@ GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
     auto CodeLoader = CTX->SyscallHandler->GetCodeLoader();
     uint64_t auxv_ptr, auxv_size;
     CodeLoader->GetAuxv(auxv_ptr, auxv_size);
-    std::string data;
+    fextl::string data;
     if (CTX->Config.Is64BitMode) {
       data.resize(auxv_size);
       memcpy(data.data(), reinterpret_cast<void*>(auxv_ptr), data.size());
@@ -736,11 +735,14 @@ GdbServer::HandledPacketType GdbServer::handleXfer(const std::string &packet) {
 
 static size_t CheckMemMapping(uint64_t Address, size_t Size) {
   uint64_t AddressEnd = Address + Size;
-  std::fstream fs("/proc/self/maps", std::fstream::in | std::fstream::binary);
-  std::string Line;
+  fextl::string MapsFile;
+  FEXCore::FileLoading::LoadFile(MapsFile, "/proc/self/maps");
+  fextl::istringstream MapsStream(MapsFile);
 
-  while (std::getline(fs, Line)) {
-    if (fs.eof()) break;
+  fextl::string Line;
+
+  while (std::getline(MapsStream, Line)) {
+    if (MapsStream.eof()) break;
     uint64_t Begin, End;
     char r,w,x,p;
     if (sscanf(Line.c_str(), "%lx-%lx %c%c%c%c", &Begin, &End, &r, &w, &x, &p) == 6) {
@@ -761,17 +763,17 @@ static size_t CheckMemMapping(uint64_t Address, size_t Size) {
 GdbServer::HandledPacketType GdbServer::handleProgramOffsets() {
   auto CodeLoader = CTX->SyscallHandler->GetCodeLoader();
   uint64_t BaseOffset = CodeLoader->GetBaseOffset();
-  auto str = fmt::format("Text={:x};Data={:x};Bss={:x}", BaseOffset, BaseOffset, BaseOffset);
+  fextl::string str = fextl::fmt::format("Text={:x};Data={:x};Bss={:x}", BaseOffset, BaseOffset, BaseOffset);
   return {std::move(str), HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::handleMemory(const std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleMemory(const fextl::string &packet) {
   bool write;
   size_t addr;
   size_t length;
-  std::string data;
+  fextl::string data;
 
-  auto ss = std::istringstream(packet);
+  auto ss = fextl::istringstream(packet);
   write = ss.get() == 'M';
   ss >> std::hex >> addr;
   ss.get(); // discard comma
@@ -806,22 +808,22 @@ GdbServer::HandledPacketType GdbServer::handleMemory(const std::string &packet)
 }
 
 
-GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleQuery(const fextl::string &packet) {
   const auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
-  const auto MatchStr = [](const std::string &Str, const char *str) -> bool { return Str.rfind(str, 0) == 0; };
+  const auto MatchStr = [](const fextl::string &Str, const char *str) -> bool { return Str.rfind(str, 0) == 0; };
 
-  const auto split = [](const std::string &Str, char deliminator) -> std::vector<std::string> {
-    std::vector<std::string> Elements;
-    std::istringstream Input(Str);
-    for (std::string line;
+  const auto split = [](const fextl::string &Str, char deliminator) -> fextl::vector<fextl::string> {
+    fextl::vector<fextl::string> Elements;
+    fextl::istringstream Input(Str);
+    for (fextl::string line;
          std::getline(Input, line);
          Elements.emplace_back(line));
     return Elements;
   };
 
   if (match("QNonStop:")) {
-    auto ss = std::istringstream(packet);
-    ss.seekg(std::string("QNonStop:").size());
+    auto ss = fextl::istringstream(packet);
+    ss.seekg(fextl::string("QNonStop:").size());
     ss.get(); // discard colon
     ss >> NonStopMode;
     return {"OK", HandledPacketType::TYPE_ACK};
@@ -832,7 +834,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
 
     // For feature documentation
     // https://sourceware.org/gdb/current/onlinedocs/gdb/General-Query-Packets.html#qSupported
-    std::string SupportedFeatures{};
+    fextl::string SupportedFeatures{};
 
     // Required features
     SupportedFeatures += "PacketSize=32768;";
@@ -901,7 +903,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
   if (match("qfThreadInfo")) {
     auto Threads = CTX->GetThreads();
 
-    std::ostringstream ss;
+    fextl::ostringstream ss;
     ss << "m";
     for (size_t i = 0; i < Threads->size(); ++i) {
       auto Thread = Threads->at(i);
@@ -916,8 +918,8 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
     return {"l", HandledPacketType::TYPE_ACK};
   }
   if (match("qThreadExtraInfo")) {
-    auto ss = std::istringstream(packet);
-    ss.seekg(std::string("qThreadExtraInfo").size());
+    auto ss = fextl::istringstream(packet);
+    ss.seekg(fextl::string("qThreadExtraInfo").size());
     ss.get(); // discard comma
     uint32_t ThreadID;
     ss >> std::hex >> ThreadID;
@@ -926,7 +928,7 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
   }
   if (match("qC")) {
     // Returns the current Thread ID
-    std::ostringstream ss;
+    fextl::ostringstream ss;
     ss << "m" <<  std::hex << CTX->ParentThread->ThreadManager.TID;
     return {ss.str(), HandledPacketType::TYPE_ACK};
   }
@@ -935,10 +937,10 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
     return {"OK", HandledPacketType::TYPE_ACK};
   }
   if (match("qSymbol")) {
-    auto ss = std::istringstream(packet);
-    ss.seekg(std::string("qSymbol").size());
+    auto ss = fextl::istringstream(packet);
+    ss.seekg(fextl::string("qSymbol").size());
     ss.get(); // discard colon
-    std::string Symbol_Val, Symbol_name;
+    fextl::string Symbol_Val, Symbol_name;
     std::getline(ss, Symbol_Val, ':');
     std::getline(ss, Symbol_name, ':');
 
@@ -955,13 +957,13 @@ GdbServer::HandledPacketType GdbServer::handleQuery(const std::string &packet) {
     std::fill(PassSignals.begin(), PassSignals.end(), false);
 
     // eg: QPassSignals:e;10;14;17;1a;1b;1c;21;24;25;2c;4c;97;
-    auto ss = std::istringstream(packet);
-    ss.seekg(std::string("QPassSignals").size());
+    auto ss = fextl::istringstream(packet);
+    ss.seekg(fextl::string("QPassSignals").size());
     ss.get(); // discard colon
 
     // We now have a semi-colon deliminated list of signals to pass to the guest process
-    for (std::string tmp; std::getline(ss, tmp, ';'); ) {
-      uint32_t Signal = std::stoi(tmp, nullptr, 16);
+    for (fextl::string tmp; std::getline(ss, tmp, ';'); ) {
+      uint32_t Signal = std::stoi(tmp.c_str(), nullptr, 16);
       if (Signal < SignalDelegator::MAX_SIGNALS) {
         PassSignals[Signal] = true;
       }
@@ -984,7 +986,7 @@ GdbServer::HandledPacketType GdbServer::ThreadAction(char action, uint32_t tid)
     case 's': {
       CTX->Step();
       SendPacketPair({"OK", HandledPacketType::TYPE_ACK});
-      auto str = fmt::format("T05thread:{:02x};", getpid());
+      fextl::string str = fextl::fmt::format("T05thread:{:02x};", getpid());
       if (LibraryMapChanged) {
         // If libraries have changed then let gdb know
         str += "library:1;";
@@ -1002,26 +1004,26 @@ GdbServer::HandledPacketType GdbServer::ThreadAction(char action, uint32_t tid)
   }
 }
 
-GdbServer::HandledPacketType GdbServer::handleV(const std::string& packet) {
-  const auto match = [&](const std::string& str) -> std::optional<std::istringstream> {
+GdbServer::HandledPacketType GdbServer::handleV(const fextl::string& packet) {
+  const auto match = [&](const fextl::string& str) -> std::optional<fextl::istringstream> {
     if (packet.rfind(str, 0) == 0) {
-      auto ss = std::istringstream(packet);
+      auto ss = fextl::istringstream(packet);
       ss.seekg(str.size());
       return ss;
     }
     return std::nullopt;
   };
 
-  const auto F       = [](int result) { return fmt::format("F{:x}", result); };
-  const auto F_error = [] { return fmt::format("F-1,{:x}", errno); };
-  const auto F_data  = [](int result, const std::string& data) {
+  const auto F       = [](int result) -> fextl::string { return fextl::fmt::format("F{:x}", result); };
+  const auto F_error = []() -> fextl::string { return fextl::fmt::format("F-1,{:x}", errno); };
+  const auto F_data  = [](int result, const fextl::string& data) -> fextl::string {
     // Binary encoded data is raw appended to the end
-    return fmt::format("F{:#x};", result) + data;
+    return fextl::fmt::format("F{:#x};", result) + data;
   };
 
-  std::optional<std::istringstream> ss;
+  std::optional<fextl::istringstream> ss;
   if((ss = match("vFile:open:"))) {
-    std::string filename;
+    fextl::string filename;
     int flags;
     int mode;
 
@@ -1053,7 +1055,7 @@ GdbServer::HandledPacketType GdbServer::handleV(const std::string& packet) {
     ss->get(); // discard comma
     *ss >> std::hex >> offset;
 
-    std::string data(count, '\0');
+    fextl::string data(count, '\0');
     if (lseek(fd, offset, SEEK_SET) < 0) {
       return {F_error(), HandledPacketType::TYPE_ACK};
     }
@@ -1093,14 +1095,14 @@ GdbServer::HandledPacketType GdbServer::handleV(const std::string& packet) {
   return {"", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::handleThreadOp(const std::string &packet) {
+GdbServer::HandledPacketType GdbServer::handleThreadOp(const fextl::string &packet) {
   const auto match = [&](const char *str) -> bool { return packet.rfind(str, 0) == 0; };
 
   if (match("Hc")) {
     // Sets thread to this ID for stepping
     // This is deprecated and vCont should be used instead
-    auto ss = std::istringstream(packet);
-    ss.seekg(std::string("Hc").size());
+    auto ss = fextl::istringstream(packet);
+    ss.seekg(fextl::string("Hc").size());
     ss >> std::hex >> CurrentDebuggingThread;
 
     CTX->Pause();
@@ -1109,7 +1111,7 @@ GdbServer::HandledPacketType GdbServer::handleThreadOp(const std::string &packet
 
   if (match("Hg")) {
     // Sets thread for "other" operations
-    auto ss = std::istringstream(packet);
+    auto ss = fextl::istringstream(packet);
     ss.seekg(std::string_view("Hg").size());
     ss >> std::hex >> CurrentDebuggingThread;
 
@@ -1121,8 +1123,8 @@ GdbServer::HandledPacketType GdbServer::handleThreadOp(const std::string &packet
   return {"", HandledPacketType::TYPE_UNKNOWN};
 }
 
-GdbServer::HandledPacketType GdbServer::handleBreakpoint(const std::string &packet) {
-  auto ss = std::istringstream(packet);
+GdbServer::HandledPacketType GdbServer::handleBreakpoint(const fextl::string &packet) {
+  auto ss = fextl::istringstream(packet);
 
   // Don't do anything with set breakpoints yet
   [[maybe_unused]] bool Set{};
@@ -1138,13 +1140,13 @@ GdbServer::HandledPacketType GdbServer::handleBreakpoint(const std::string &pack
   return {"OK", HandledPacketType::TYPE_ACK};
 }
 
-GdbServer::HandledPacketType GdbServer::ProcessPacket(const std::string &packet) {
+GdbServer::HandledPacketType GdbServer::ProcessPacket(const fextl::string &packet) {
   switch (packet[0]) {
     case '?': {
       // Indicates the reason that the thread has stopped
       // Behaviour changes if the target is in non-stop mode
       // Binja doesn't support S response here
-      auto str = fmt::format("T00thread:{:x};", getpid());
+      fextl::string str = fextl::fmt::format("T00thread:{:x};", getpid());
       return {std::move(str), HandledPacketType::TYPE_ACK};
     }
     case 'c':
@@ -1225,7 +1227,7 @@ void GdbServer::GdbServerLoop() {
     while ((c = CommsStream->get()) >= 0 ) {
         switch (c) {
         case '$': {
-            std::string packet = ReadPacket(*CommsStream);
+            auto packet = ReadPacket(*CommsStream);
             response = ProcessPacket(packet);
             SendPacketPair(response);
             if (response.TypeResponse == HandledPacketType::TYPE_UNKNOWN) {
@@ -1245,7 +1247,7 @@ void GdbServer::GdbServerLoop() {
             break;
         case '\x03': { // ASCII EOT
             CTX->Pause();
-            auto str = fmt::format("T02thread:{:02x};", getpid());
+            fextl::string str = fextl::fmt::format("T02thread:{:02x};", getpid());
             if (LibraryMapChanged) {
               // If libraries have changed then let gdb know
               str += "library:1;";
@@ -1279,7 +1281,8 @@ void GdbServer::StartThread() {
 }
 
 void GdbServer::OpenListenSocket() {
-  // open socket
+  // getaddrinfo allocates memory that can't be removed.
+  FEXCore::Allocator::YesIKnowImNotSupposedToUseTheGlibcAllocator glibc;
   struct addrinfo hints, *res;
 
   memset(&hints, 0, sizeof(hints));
@@ -1308,9 +1311,11 @@ void GdbServer::OpenListenSocket() {
   }
 
   listen(ListenSocket, 1);
+
+  freeaddrinfo(res);
 }
 
-std::unique_ptr<std::iostream> GdbServer::OpenSocket() {
+fextl::unique_ptr<std::iostream> GdbServer::OpenSocket() {
   // Block until a connection arrives
   struct sockaddr_storage their_addr{};
   socklen_t addr_size{};
@@ -1318,7 +1323,8 @@ std::unique_ptr<std::iostream> GdbServer::OpenSocket() {
   LogMan::Msg::IFmt("GdbServer, waiting for connection on localhost:8086");
   int new_fd = accept(ListenSocket, (struct sockaddr *)&their_addr, &addr_size);
 
-  return std::make_unique<FEXCore::Utils::NetStream>(new_fd);
+  return fextl::make_unique<FEXCore::Utils::NetStream>(new_fd);
 }
 
+#endif
 } // namespace FEXCore

External/FEXCore/Source/Interface/Core/GdbServer.h

@@ -8,13 +8,14 @@ $end_info$
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/Threads.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
 
 #include <atomic>
 #include <istream>
 #include <memory>
 #include <mutex>
 #include <stdint.h>
-#include <string>
 
 namespace FEXCore {
 
@@ -37,10 +38,10 @@ private:
     void Break(int signal);
 
     void OpenListenSocket();
-    std::unique_ptr<std::iostream> OpenSocket();
+    fextl::unique_ptr<std::iostream> OpenSocket();
     void StartThread();
-    std::string ReadPacket(std::iostream &stream);
-    void SendPacket(std::ostream &stream, const std::string& packet);
+    fextl::string ReadPacket(std::iostream &stream);
+    void SendPacket(std::ostream &stream, const fextl::string& packet);
 
     void SendACK(std::ostream &stream, bool NACK);
 
@@ -48,7 +49,7 @@ private:
     void WaitForThreadWakeup();
 
     struct HandledPacketType {
-      std::string Response{};
+      fextl::string Response{};
       enum ResponseType {
         TYPE_NONE,
         TYPE_UNKNOWN,
@@ -61,32 +62,32 @@ private:
     };
 
     void SendPacketPair(const HandledPacketType& packetPair);
-    HandledPacketType ProcessPacket(const std::string &packet);
-    HandledPacketType handleQuery(const std::string &packet);
-    HandledPacketType handleXfer(const std::string &packet);
-    HandledPacketType handleMemory(const std::string &packet);
-    HandledPacketType handleV(const std::string& packet);
-    HandledPacketType handleThreadOp(const std::string &packet);
-    HandledPacketType handleBreakpoint(const std::string &packet);
+    HandledPacketType ProcessPacket(const fextl::string &packet);
+    HandledPacketType handleQuery(const fextl::string &packet);
+    HandledPacketType handleXfer(const fextl::string &packet);
+    HandledPacketType handleMemory(const fextl::string &packet);
+    HandledPacketType handleV(const fextl::string& packet);
+    HandledPacketType handleThreadOp(const fextl::string &packet);
+    HandledPacketType handleBreakpoint(const fextl::string &packet);
     HandledPacketType handleProgramOffsets();
 
     HandledPacketType ThreadAction(char action, uint32_t tid);
 
-    std::string readRegs();
-    HandledPacketType readReg(const std::string& packet);
+    fextl::string readRegs();
+    HandledPacketType readReg(const fextl::string& packet);
 
     FEXCore::Context::ContextImpl *CTX;
-    std::unique_ptr<FEXCore::Threads::Thread> gdbServerThread;
-    std::unique_ptr<std::iostream> CommsStream;
+    fextl::unique_ptr<FEXCore::Threads::Thread> gdbServerThread;
+    fextl::unique_ptr<std::iostream> CommsStream;
     std::mutex sendMutex;
     bool SettingNoAckMode{false};
     bool NoAckMode{false};
     bool NonStopMode{false};
-    std::string ThreadString{};
-    std::string OSDataString{};
+    fextl::string ThreadString{};
+    fextl::string OSDataString{};
     void buildLibraryMap();
     std::atomic<bool> LibraryMapChanged = true;
-    std::string LibraryMapString{};
+    fextl::string LibraryMapString{};
 
     // Used to keep track of which signals to pass to the guest
     std::array<bool, SignalDelegator::MAX_SIGNALS + 1> PassSignals{};

External/FEXCore/Source/Interface/Core/HostFeatures.cpp

@@ -9,7 +9,7 @@
 #endif
 
 #ifdef _M_X86_64
-#include <xbyak/xbyak_util.h>
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #endif
 
 namespace FEXCore {
@@ -17,12 +17,12 @@ namespace FEXCore {
 // Data Zero Prohibited flag
 // 0b0 = ZVA/GVA/GZVA permitted
 // 0b1 = ZVA/GVA/GZVA prohibited
-constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
+[[maybe_unused]] constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
 // Log2 of the blocksize in 32-bit words
-constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
+[[maybe_unused]] constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
 
 #ifdef _M_ARM_64
-static uint32_t GetDCZID() {
+[[maybe_unused]] static uint32_t GetDCZID() {
   uint64_t Result{};
   __asm("mrs %[Res], DCZID_EL0"
       : [Res] "=r" (Result));
@@ -54,7 +54,12 @@ HostFeatures::HostFeatures() {
 #ifdef VIXL_SIMULATOR
   auto Features = vixl::CPUFeatures::All();
 #else
+#ifndef _WIN32
   auto Features = vixl::CPUFeatures::InferFromOS();
+#else
+  // Need to use ID registers in WINE.
+  auto Features = vixl::CPUFeatures::InferFromIDRegisters();
+#endif
 #endif
   SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
   SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
@@ -66,6 +71,7 @@ HostFeatures::HostFeatures() {
   SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
   SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
   SupportsPMULL_128Bit = Features.Has(vixl::CPUFeatures::Feature::kPmull1Q);
+  SupportsCSSC = Features.Has(vixl::CPUFeatures::Feature::kCSSC);
 
   Supports3DNow = true;
   SupportsSSE4A = true;
@@ -133,13 +139,14 @@ HostFeatures::HostFeatures() {
   SupportsPMULL_128Bit = Features.has(Xbyak::util::Cpu::tPCLMULQDQ);
 
   // xbyak doesn't know how to check for CLZero
-  uint32_t eax, ebx, ecx, edx;
   // First ensure we support a new enough extended CPUID function range
-  __cpuid(0x8000'0000, eax, ebx, ecx, edx);
-  if (eax >= 0x8000'0008U) {
+
+  uint32_t data[4];
+  Xbyak::util::Cpu::getCpuid(0x8000'0000, data);
+  if (data[0] >= 0x8000'0008U) {
     // CLZero defined in 8000_00008_EBX[bit 0]
-    __cpuid(0x8000'0008, eax, ebx, ecx, edx);
-    SupportsCLZERO = ebx & 1;
+    Xbyak::util::Cpu::getCpuid(0x8000'0008, data);
+    SupportsCLZERO = data[1] & 1;
   }
 
   SupportsFlushInputsToZero = true;
@@ -160,5 +167,11 @@ HostFeatures::HostFeatures() {
     SupportsCLZERO = DCZID_Bytes == CPUIDEmu::CACHELINE_SIZE;
   }
 #endif
+
+  // Disable AVX if the configuration explicitly has disabled it.
+  FEX_CONFIG_OPT(EnableAVX, ENABLEAVX);
+  if (!EnableAVX) {
+    SupportsAVX = false;
+  }
 }
 }

External/FEXCore/Source/Interface/Core/Interpreter/ALUOps.cpp

@@ -113,6 +113,22 @@ DEF_OP(Neg) {
   }
 }
 
+DEF_OP(Abs) {
+  auto Op = IROp->C<IR::IROp_Abs>();
+  const uint8_t OpSize = IROp->Size;
+
+  const int64_t Src = *GetSrc<int64_t*>(Data->SSAData, Op->Src);
+  switch (OpSize) {
+    case 4:
+      GD = std::abs(static_cast<int32_t>(Src));
+      break;
+    case 8:
+      GD = std::abs(static_cast<int64_t>(Src));
+      break;
+    default: LOGMAN_MSG_A_FMT("Unknown Abs Size: {}\n", OpSize); break;
+  }
+}
+
 DEF_OP(Mul) {
   auto Op = IROp->C<IR::IROp_Mul>();
   const uint8_t OpSize = IROp->Size;
@@ -869,12 +885,8 @@ DEF_OP(Select) {
   auto Op = IROp->C<IR::IROp_Select>();
   const uint8_t OpSize = IROp->Size;
 
-  const uint64_t Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp1);
-  const uint64_t Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp2);
-
   uint64_t ArgTrue;
   uint64_t ArgFalse;
-
   if (OpSize == 4) {
     ArgTrue = *GetSrc<uint32_t*>(Data->SSAData, Op->TrueVal);
     ArgFalse = *GetSrc<uint32_t*>(Data->SSAData, Op->FalseVal);
@@ -885,10 +897,25 @@ DEF_OP(Select) {
 
   bool CompResult;
 
-  if (Op->CompareSize == 4)
+  if (Op->CompareSize == 4) {
+    const auto Src1 = *GetSrc<uint32_t*>(Data->SSAData, Op->Cmp1);
+    const auto Src2 = *GetSrc<uint32_t*>(Data->SSAData, Op->Cmp2);
     CompResult = IsConditionTrue<uint32_t, int32_t, float>(Op->Cond.Val, Src1, Src2);
-  else
+  }
+  else if (Op->CompareSize == 8) {
+    const auto Src1 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp1);
+    const auto Src2 = *GetSrc<uint64_t*>(Data->SSAData, Op->Cmp2);
     CompResult = IsConditionTrue<uint64_t, int64_t, double>(Op->Cond.Val, Src1, Src2);
+  }
+  else if (Op->CompareSize == 16) {
+    const auto Src1 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Cmp1);
+    const auto Src2 = *GetSrc<__uint128_t*>(Data->SSAData, Op->Cmp2);
+    CompResult = IsConditionTrue<__uint128_t, __int128_t, double>(Op->Cond.Val, Src1, Src2);
+  }
+  else {
+    LOGMAN_MSG_A_FMT("Unknown select size: {}", Op->CompareSize);
+    FEX_UNREACHABLE;
+  }
 
   GD = CompResult ? ArgTrue : ArgFalse;
 }

External/FEXCore/Source/Interface/Core/Interpreter/BranchOps.cpp

@@ -143,6 +143,15 @@ DEF_OP(CPUID) {
   memcpy(DstPtr, &Results, sizeof(uint32_t) * 4);
 }
 
+DEF_OP(XGETBV) {
+  auto Op = IROp->C<IR::IROp_XGetBV>();
+  uint32_t *DstPtr = GetDest<uint32_t*>(Data->SSAData, Node);
+  const uint32_t Function = *GetSrc<uint32_t*>(Data->SSAData, Op->Function);
+
+  auto Results = Data->State->CTX->RunXCRFunction(Function);
+  memcpy(DstPtr, &Results, sizeof(uint32_t) * 2);
+}
+
 #undef DEF_OP
 
 } // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/ConversionOps.cpp

@@ -211,7 +211,7 @@ DEF_OP(Vector_FToF) {
       // Little bit tricky here
       // Sometimes is used to convert from a 128bit vector register
       // in to a 64bit vector register with different sized elements
-      // eg: %ssa5 i32v2 = Vector_FToF %ssa4 i128, #0x8
+      // eg: %5 i32v2 = Vector_FToF %4 i128, #0x8
       uint8_t Elements = OpSize == 8 ? 2 : OpSize / Op->SrcElementSize;
       DO_VECTOR_1SRC_2TYPE_OP_NOSIZE(float, double, Func, 0, 0)
       break;

External/FEXCore/Source/Interface/Core/Interpreter/F80Ops.cpp

@@ -8,7 +8,7 @@ $end_info$
 #include "Interface/Core/Interpreter/InterpreterOps.h"
 #include "Interface/Core/Interpreter/InterpreterDefines.h"
 
-#include "F80Ops.h"
+#include "Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h"
 
 #include <cstdint>
 
@@ -417,7 +417,6 @@ DEF_OP(F64SCALE) {
   memcpy(GDP, &Tmp, sizeof(double));
 }
 
-
 #undef DEF_OP
 
 } // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h

@@ -4,12 +4,9 @@
 
 #include <FEXCore/IR/IR.h>
 
+#include "Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h"
+
 namespace FEXCore::CPU {
-template<IR::IROps Op>
-struct OpHandlers {
-
-};
-
 template<>
 struct OpHandlers<IR::OP_F80CVTTO> {
   static X80SoftFloat handle4(float src) {
@@ -395,5 +392,4 @@ struct OpHandlers<IR::OP_F80LOADFCW> {
   }
 };
 
-
-}
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h

@@ -0,0 +1,75 @@
+#pragma once
+
+#include <cstdint>
+
+namespace FEXCore::IR {
+enum IROps : uint16_t;
+}
+
+namespace FEXCore::CPU {
+
+// Base template for fallback handling.
+//
+// Registering and hooking up fallback is currently like so:
+//
+// 1. Go to InterpreterFallbacks.cpp and create a template specialization of
+//    the GetFallbackInfo member function.
+//
+//    This member function should reasonably define what the fallback you're
+//    going to create will take as parameters and return as a result. For example:
+//
+//    template<>
+//    FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(double), Core::FallbackHandlerIndex Index) {
+//      return {FABI_F80_F64, (void*)fn, Index};
+//    }
+//
+//    Defines info about a fallback that takes a double as an argument and
+//    returns a X80SoftFloat instance.
+//
+//    You will also want to define a new FallbackHandlerIndex enum member and use it
+//    to set up the new info handler into the Info array in FillFallbackIndexPointers.
+//
+// 1.1. (potentially optional). Define a new ABI element in the FallbackAPI enum.
+//      This ABI enum value will be used to tell the JITs how to handle the fallback
+//      properly. These enum values specify the return type followed by its argument types.
+//
+//      So, FABI_I64_F80_F80, for example indicates that the function will behave like a
+//      function as if were defined as:
+//
+//      uint64_t fn(X80SoftFloat, X80SoftFloat)
+//
+// 1.2. (potentially optional). If you needed to define a new enum ABI type like in 1.1, then
+//      you need to add the handling for it in the JITs, which can be found in the respective
+//      JIT's JIT.cpp file in a function called Op_Unhandled
+//
+//      You need to add a new case to the ABI switch statement using the new ABI type
+//      and do the necessary moving of data from register-allocated JIT parameters
+//      into that platform's registers that respects the calling convention. After this is
+//      done, most of the necessary background boilerplate is finished.
+//
+// 2. Now, make a specialization of this class with a member function named 'handle()'
+//    that takes the same parameters as the ones described in the fallback info function
+//    specialization.
+//
+//    For example, if you have the fallback info from the example in step 1, it would be:
+//
+//    template <>
+//    struct OpHandlers<IR::CoolNewIROpcode> {
+//      static X80SoftFloat handle(double src) {
+//        return ...;
+//      }
+//    };
+//
+// 3. Fill out the behavior of the OpHandler specialization to perform what you would like
+//    the fallback to do.
+//
+// 4. Add an implementation of the IR op to the Interpreter that passes through to the
+//    OpHandler implementation.
+//
+// 5. Done.
+//
+template <IR::IROps Op>
+struct OpHandlers {
+};
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp

@@ -1,6 +1,8 @@
-#include "FEXCore/Core/CoreState.h"
+#include <FEXCore/Core/CoreState.h>
+
 #include "Interface/Core/Interpreter/InterpreterOps.h"
-#include "Interface/Core/Interpreter/F80Ops.h"
+#include "Interface/Core/Interpreter/Fallbacks/F80Fallbacks.h"
+#include "Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h"
 
 #include <cstddef>
 #include <cstdint>
@@ -87,6 +89,16 @@ FallbackInfo GetFallbackInfo(X80SoftFloat(*fn)(X80SoftFloat, X80SoftFloat), FEXC
   return {FABI_F80_F80_F80, (void*)fn, HandlerIndex};
 }
 
+template<>
+FallbackInfo GetFallbackInfo(uint32_t(*fn)(uint64_t, uint64_t, __uint128_t, __uint128_t, uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_I32_I64_I64_I128_I128_I16, (void*)fn, HandlerIndex};
+}
+
+template<>
+FallbackInfo GetFallbackInfo(uint32_t(*fn)(__uint128_t, __uint128_t, uint16_t), FEXCore::Core::FallbackHandlerIndex HandlerIndex) {
+  return {FABI_I32_I128_I128_I16, (void*)fn, HandlerIndex};
+}
+
 void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) {
   Info[Core::OPINDEX_F80LOADFCW] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80LOADFCW>::handle, Core::OPINDEX_F80LOADFCW).fn);
   Info[Core::OPINDEX_F80CVTTO_4] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F80CVTTO>::handle4, Core::OPINDEX_F80CVTTO_4).fn);
@@ -144,6 +156,9 @@ void InterpreterOps::FillFallbackIndexPointers(uint64_t *Info) {
   Info[Core::OPINDEX_F64FPREM1] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64FPREM1>::handle, Core::OPINDEX_F64FPREM1).fn);
   Info[Core::OPINDEX_F64SCALE] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_F64SCALE>::handle, Core::OPINDEX_F64SCALE).fn);
 
+  // SSE4.2 string instructions
+  Info[Core::OPINDEX_VPCMPESTRX] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX).fn);
+  Info[Core::OPINDEX_VPCMPISTRX] = reinterpret_cast<uint64_t>(GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX).fn);
 }
 
 bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInfo *Info) {
@@ -302,6 +317,14 @@ bool InterpreterOps::GetFallbackHandler(IR::IROp_Header const *IROp, FallbackInf
     COMMON_F64_OP(FPREM)
     COMMON_F64_OP(SCALE)
 
+    // SSE4.2 Fallbacks
+    case IR::OP_VPCMPESTRX:
+      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPESTRX>::handle, Core::OPINDEX_VPCMPESTRX);
+      return true;
+    case IR::OP_VPCMPISTRX:
+      *Info = GetFallbackInfo(&FEXCore::CPU::OpHandlers<IR::OP_VPCMPISTRX>::handle, Core::OPINDEX_VPCMPISTRX);
+      return true;
+
     default:
       break;
   }

External/FEXCore/Source/Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h

@@ -0,0 +1,408 @@
+#pragma once
+
+#include <algorithm>
+#include <cstddef>
+#include <cstdint>
+#include <cstdlib>
+#include <cstring>
+
+#include <FEXCore/IR/IR.h>
+
+#include "Interface/Core/Interpreter/Fallbacks/FallbackOpHandler.h"
+
+namespace FEXCore::CPU {
+
+template<>
+struct OpHandlers<IR::OP_VPCMPESTRX> {
+  enum class AggregationOp {
+    EqualAny     = 0b00,
+    Ranges       = 0b01,
+    EqualEach    = 0b10,
+    EqualOrdered = 0b11,
+  };
+
+  enum class SourceData {
+    U8,
+    U16,
+    S8,
+    S16,
+  };
+
+  enum class Polarity {
+    Positive,
+    Negative,
+    PositiveMasked,
+    NegativeMasked,
+  };
+
+  static uint32_t handle(uint64_t RAX, uint64_t RDX, __uint128_t lhs, __uint128_t rhs, uint16_t control) {
+    // Subtract by 1 in order to make validity limits 0-based
+    const auto valid_lhs = GetExplicitLength(RAX, control) - 1;
+    const auto valid_rhs = GetExplicitLength(RDX, control) - 1;
+
+    return MainBody(lhs, valid_lhs, rhs, valid_rhs, control);
+  }
+
+  // Main PCMPXSTRX algorithm body. Allows for reuse with both implicit and explicit length variants.
+  static uint32_t MainBody(const __uint128_t& lhs, int valid_lhs, const __uint128_t& rhs, int valid_rhs, uint16_t control) {
+    const uint32_t aggregation = PerformAggregation(lhs, valid_lhs, rhs, valid_rhs, control);
+    const int32_t upper_limit = (16 >> (control & 1)) - 1;
+
+    // Bits are arranged as:
+    // Bit #:   3    2    1    0
+    //         [OF | CF | SF | ZF]
+    uint32_t flags = 0;
+    flags |= (valid_rhs < upper_limit) ? 0b01 : 0b00;
+    flags |= (valid_lhs < upper_limit) ? 0b10 : 0b00;
+
+    const uint32_t result = HandlePolarity(aggregation, control, upper_limit, valid_rhs);
+    if (result != 0) {
+      flags |= 0b0100;
+    }
+    if ((result & 1) != 0) {
+      flags |= 0b1000;
+    }
+
+    // We tack the flags on top of the result to avoid needing to handle
+    // multiple return values in the JITs.
+    return result | (flags << 16);
+  }
+
+  static int32_t GetExplicitLength(uint64_t reg, uint16_t control) {
+    // Bit 8 controls whether or not the reg value is 64-bit or 32-bit.
+    int64_t value = 0;
+    if (((control >> 8) & 1) != 0) {
+      value = static_cast<int64_t>(reg);
+    } else {
+      // We need a sign extend in this case.
+      value = static_cast<int32_t>(reg);
+    }
+
+    // If control[0] is set, then we're dealing with words instead of bytes
+    const int64_t limit = (control & 1) != 0 ? 8 : 16;
+
+    // Length needs to saturate to 16 (if bytes) or 8 (if words)
+    // when the length value is greater than 16 (if bytes)/8 (if words)
+    // or if the length value is less than -16 (if bytes)/-8 (if words).
+    if (value < -limit || value > limit) {
+      return limit;
+    }
+
+    return std::abs(static_cast<int>(value));
+  }
+
+  static int32_t GetElement(const __uint128_t& vec, int32_t index, uint16_t control) {
+    const auto* vec_ptr = reinterpret_cast<const uint8_t*>(&vec);
+
+    // Control bits [1:0] define the data type being dealt with.
+    switch (static_cast<SourceData>(control & 0b11)) {
+    case SourceData::U8:
+      return static_cast<int32_t>(vec_ptr[index]);
+    case SourceData::U16: {
+      uint16_t value{};
+      std::memcpy(&value, vec_ptr + (sizeof(uint16_t) * static_cast<size_t>(index)), sizeof(value));
+      return value;
+    }
+    case SourceData::S8:
+      return static_cast<int8_t>(vec_ptr[index]);
+    case SourceData::S16:
+    default: {
+      int16_t value{};
+      std::memcpy(&value, vec_ptr + (sizeof(int16_t) * static_cast<size_t>(index)), sizeof(value));
+      return value;
+    }
+    }
+  }
+
+  static uint32_t PerformAggregation(const __uint128_t& lhs, int32_t valid_lhs,
+                                     const __uint128_t& rhs, int32_t valid_rhs,
+                                     uint16_t control) {
+    switch (static_cast<AggregationOp>((control >> 2) & 0b11)) {
+    case AggregationOp::EqualAny:
+      return HandleEqualAny(lhs, valid_lhs, rhs, valid_rhs, control);
+    case AggregationOp::Ranges:
+      return HandleRanges(lhs, valid_lhs, rhs, valid_rhs, control);
+    case AggregationOp::EqualEach:
+      return HandleEqualEach(lhs, valid_lhs, rhs, valid_rhs, control);
+    case AggregationOp::EqualOrdered:
+    default:
+      return HandleEqualOrdered(lhs, valid_lhs, rhs, valid_rhs, control);
+    }
+  }
+
+  static uint32_t HandlePolarity(uint32_t value, uint16_t control, int upper_limit, int valid_rhs) {
+    switch (static_cast<Polarity>((control >> 4) & 0b11)) {
+      case Polarity::Negative:
+        return value ^ ((2U << upper_limit) - 1);
+      case Polarity::NegativeMasked:
+        return value ^ ((1U << (valid_rhs + 1)) - 1);
+      case Polarity::Positive:
+      case Polarity::PositiveMasked:
+      default:
+        // Both positive masking and positive polarity are documented
+        // as both being equivalent to "IntRes2 = IntRes1", where IntRes1
+        // is our 'value' parameter, so we don't need to do anything in
+        // these cases except return the same value.
+        return value;
+    }
+  }
+
+  // Finds characters from an overall character set.
+  //
+  // Scans through RHS trying to find any characters contained in LHS.
+  // Think of this as a sort of vectorized version of strspn (kind of).
+  //
+  // e.g. Assume operating on two character vectors as unsigned words
+  //
+  //         0  1  2  3  4  5  6  7
+  // LHS -> [a, b, c, d, e, f, g, n]
+  // RHS -> [z, k, v, c, d, o, p, n]
+  //
+  // With both explicit lengths for each string being 8 (the max length for words),
+  // this would result in an intermediate result like:
+  //
+  //            0b1001'1000
+  //              │  │ │
+  // 'n' match ───┘  │ │
+  //                 │ │
+  // 'd' match ──────┘ │
+  //                   │
+  // 'c' match ────────┘
+  //
+  static uint32_t HandleEqualAny(const __uint128_t& lhs, int32_t valid_lhs,
+                                 const __uint128_t& rhs, int32_t valid_rhs,
+                                 uint16_t control) {
+    uint32_t result = 0;
+
+    for (int j = valid_rhs; j >= 0; j--) {
+      result <<= 1;
+
+      const int rhs_value = GetElement(rhs, j, control);
+      for (int i = valid_lhs; i >= 0; i--) {
+        const int lhs_value = GetElement(lhs, i, control);
+        result |= static_cast<uint32_t>(rhs_value == lhs_value);
+      }
+    }
+
+    return result;
+  }
+
+  // Determines if a character falls within a limited range
+  //
+  // Scans through rhs using a range denoted by two elements
+  // in lhs and determines if the respective character in rhs
+  // falls within its range.
+  //
+  // i.e.
+  //      lhs_upper_bound >= rhs_value && lhs_lower_bound <= rhs_value
+  //
+  // e.g. Assume operating on two character vectors as unsigned words
+  //
+  //         0  1  2  3  4  5  6  7
+  // LHS -> [a, z, A, Z, 0, 0, 0, 0]
+  // RHS -> [z, k, ., C, M, ;, \, ']
+  //
+  // With LHS's length being 4 and RHS's lenth being 8,
+  // this would result in an intermediate result like:
+  //
+  //                          0b0001'1011
+  //                               │ │ ││
+  // 'z' >= 'M' && 'a' <= 'M' ─────┘ │ ││
+  //                                 │ ││
+  // 'z' >= 'C' && 'a' <= 'C' ───────┘ ││
+  //                                   ││
+  // 'Z' >= 'k' && 'A' <= 'k' ─────────┘│
+  //                                    │
+  // 'Z' >= 'z' && 'A' <= 'z' ──────────┘
+  //
+  static uint32_t HandleRanges(const __uint128_t& lhs, int32_t valid_lhs,
+                               const __uint128_t& rhs, int32_t valid_rhs,
+                               uint16_t control) {
+    uint32_t result = 0;
+
+    for (int j = valid_rhs; j >= 0; j--) {
+      result <<= 1;
+
+      const int element = GetElement(rhs, j, control);
+      for (int i = (valid_lhs - 1) | 1; i >= 0; i -= 2) {
+        const int upper_bound = GetElement(lhs, i - 0, control);
+        const int lower_bound = GetElement(lhs, i - 1, control);
+
+        const bool ge = upper_bound >= element;
+        const bool le = lower_bound <= element;
+
+        result |= static_cast<uint32_t>(ge && le);
+      }
+    }
+
+    return result;
+  }
+
+  // Determines if each character is equal to one another (string compare)
+  //
+  // Essentially the PCMPXSTRX variant of memcmp/strcmp. Sets the bit of the
+  // resulting mask if both elements are equal to one another. Otherwise
+  // sets it to false.
+  //
+  // e.g. Assume operating on two character vectors as unsigned words
+  //
+  //         0  1  2  3  4  5  6  7
+  // LHS -> [a, b, c, d, e, f, g, n]
+  // RHS -> [a, b, c, d, e, f, e, x]
+  //
+  // With both explicit lengths for each string being 8 (the max length for words),
+  // this would result in an intermediate result like:
+  //
+  //            0b0011'1111
+  //                ││ ││││
+  // 'f' == 'f' ────┘│ ││││
+  //                 │ ││││
+  // 'e' == 'e' ─────┘ ││││
+  //                   ││││
+  // 'd' == 'd' ───────┘│││
+  //                    │││
+  // 'c' == 'c' ────────┘││
+  //                     ││
+  // 'b' == 'b' ─────────┘│
+  //                      │
+  // 'a' == 'a' ──────────┘
+  //
+  static uint32_t HandleEqualEach(const __uint128_t& lhs, int32_t valid_lhs,
+                                  const __uint128_t& rhs, int32_t valid_rhs,
+                                  uint16_t control) {
+    const auto upper_limit = (16 >> (control & 1)) - 1;
+    const auto max_valid = std::max(valid_lhs, valid_rhs);
+    const auto min_valid = std::min(valid_lhs, valid_rhs);
+
+    // All values past the end of string must be forced to true.
+    // (See 4.1.6 Valid/Invalid Override of Comparisons in the Intel Software Development Manual)
+    // So we can calculate this part of the mask ahead of time and set all those to-be bits to true
+    // and then progressively shift them into place over the course of execution.
+    uint32_t result = (1U << (upper_limit - max_valid)) - 1;
+    result <<= (max_valid - min_valid);
+
+    for (int i = min_valid; i >= 0; i--) {
+      const int lhs_element = GetElement(lhs, i, control);
+      const int rhs_element = GetElement(rhs, i, control);
+
+      result <<= 1;
+      result |= static_cast<uint32_t>(lhs_element == rhs_element);
+    }
+
+    return result;
+  }
+
+  // Determines if a substring exists within an overall string
+  //
+  // Somewhat equivalent to the behavior of strstr.
+  //
+  // Sets the corresponding index in the result where a substring is found.
+  //
+  // e.g. Assume operating on two character vectors as unsigned words
+  //
+  //         0  1  2  3  4  5  6  7
+  // LHS -> [b, a, x, z, y, v, o, m]
+  // RHS -> [b, a, d, b, a, n, k, s]
+  //
+  // With the length of LHS being 2 and the length of RHS being 8, we have a composition like:
+  //
+  //      Substring to look for
+  //       ┌──┴──┐
+  // LHS -> [b, a, x, z, y, v, o, m]
+  // RHS -> [b, a, d, b, a, n, k, s]
+  //       └───────────┬────────────┘
+  //         Entire string to search
+  //
+  // And we end up with a result like:
+  //
+  //            0b0000'1001
+  //                   │  │
+  // At index 3 ───────┘  │
+  //                      │
+  // At index 0 ──────────┘
+  //
+  static uint32_t HandleEqualOrdered(const __uint128_t& lhs, int32_t valid_lhs,
+                                     const __uint128_t& rhs, int32_t valid_rhs,
+                                     uint16_t control) {
+    const auto upper_limit = (16 >> (control & 1)) - 1;
+
+    // Edge case!
+    // If we have *no* valid characters in our inner string, then
+    // we need to return the intermediate result as
+    // 0xFF (if operating on words) or 0xFFFF (if operating on bytes)
+    if (valid_lhs == -1) {
+      return (2U << upper_limit) - 1;
+    }
+
+    uint32_t result = 0;
+    const int initial = valid_rhs == upper_limit ? valid_rhs
+                                                 : valid_rhs - valid_lhs;
+    for (int j = initial; j >= 0; j--) {
+      result <<= 1;
+
+      uint32_t value = 1;
+      const int start = std::min(valid_rhs - j, valid_lhs);
+      for (int i = start; i >= 0; i--) {
+        const int lhs_value = GetElement(lhs, i + 0, control);
+        const int rhs_value = GetElement(rhs, i + j, control);
+
+        value &= static_cast<uint32_t>(lhs_value == rhs_value);
+      }
+
+      result |= value;
+    }
+
+    return result;
+  }
+};
+
+template<>
+struct OpHandlers<IR::OP_VPCMPISTRX> {
+  // Essentially the same in terms of behavior with VPCMPESTRX instructions,
+  // with the only difference being that the length of the string is encoded
+  // as part of the data vectors passed in.
+  //
+  // i.e. Length is determined by the presence of a NUL (all-zero) character
+  //      within the data.
+  //
+  //      If no NUL character exists, then the length of the strings are assumed
+  //      to be the max length possible for the given character size specified
+  //      in the control flags (16 characters for 8-bit, and 8 characters for 16-bit).
+  //
+  static uint32_t handle(__uint128_t lhs, __uint128_t rhs, uint16_t control) {
+    // Subtract by 1 in order to make validity limits 0-based
+    const auto valid_lhs = GetImplicitLength(lhs, control) - 1;
+    const auto valid_rhs = GetImplicitLength(rhs, control) - 1;
+
+    return OpHandlers<IR::OP_VPCMPESTRX>::MainBody(lhs, valid_lhs, rhs, valid_rhs, control);
+  }
+
+  static int32_t GetImplicitLength(const __uint128_t& data, uint16_t control) {
+    const auto* data_u8 = reinterpret_cast<const uint8_t*>(&data);
+    const auto is_using_words = (control & 1) != 0;
+
+    int32_t length = 0;
+
+    if (is_using_words) {
+      const auto get_word = [data_u8](int32_t index) {
+        const auto* src = data_u8 + (index * sizeof(uint16_t));
+
+        uint16_t element{};
+        std::memcpy(&element, src, sizeof(uint16_t));
+        return element;
+      };
+
+      while (length < 8 && get_word(length) != 0) {
+        length++;
+      }
+    } else {
+      while (length < 16 && data_u8[length] != 0) {
+        length++;
+      }
+    }
+
+    return length;
+  }
+};
+
+} // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterClass.h

@@ -6,25 +6,22 @@
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/vector.h>
 
 namespace FEXCore::CPU {
 class Dispatcher;
 class X86DispatchGenerator;
 class Arm64DispatchGenerator;
 
-#define DESTMAP_AS_MAP 0
-#if DESTMAP_AS_MAP
-using DestMapType = std::unordered_map<uint32_t, uint32_t>;
-#else
-using DestMapType = std::vector<uint32_t>;
-#endif
+using DestMapType = fextl::vector<uint32_t>;
 
 class InterpreterCore final : public CPUBackend {
 public:
   explicit InterpreterCore(Dispatcher *Dispatch,
                            FEXCore::Core::InternalThreadState *Thread);
 
-  [[nodiscard]] std::string GetName() override { return "Interpreter"; }
+  [[nodiscard]] fextl::string GetName() override { return "Interpreter"; }
 
   [[nodiscard]] CPUBackend::CompiledCode CompileCode(uint64_t Entry,
                                   FEXCore::IR::IRListView const *IR,
@@ -36,7 +33,7 @@ public:
   [[nodiscard]] bool NeedsOpDispatch() override { return true; }
 
   static void InitializeSignalHandlers(FEXCore::Context::ContextImpl *CTX);
-  
+
   void ClearCache() override;
 
 private:

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.cpp

@@ -1,17 +1,14 @@
 #include "Interface/Context/Context.h"
 
-#include "Interface/Core/ArchHelpers/Arm64.h"
-#include "Interface/Core/ArchHelpers/MContext.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
 #include "Interface/Core/Interpreter/InterpreterClass.h"
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/MathUtils.h>
+#include <FEXCore/fextl/memory.h>
 
-#include <memory>
 #include <signal.h>
 #include <stdint.h>
 #include <utility>
@@ -49,18 +46,6 @@ InterpreterCore::InterpreterCore(Dispatcher *Dispatcher, FEXCore::Core::Internal
   ClearCache();
 }
 
-void InterpreterCore::InitializeSignalHandlers(FEXCore::Context::ContextImpl *CTX) {
-  CTX->SignalDelegation->RegisterHostSignalHandler(SIGILL, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-    return reinterpret_cast<Context::ContextImpl*>(Thread->CTX)->Dispatcher->HandleSIGILL(Thread, Signal, info, ucontext);
-  }, true);
-
-#ifdef _M_ARM_64
-  CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-    return FEXCore::ArchHelpers::Arm64::HandleSIGBUS(true, Signal, info, ucontext);
-  }, true);
-#endif
-}
-
 CPUBackend::CompiledCode InterpreterCore::CompileCode(uint64_t Entry, [[maybe_unused]] FEXCore::IR::IRListView const *IR, [[maybe_unused]] FEXCore::Core::DebugData *DebugData, FEXCore::IR::RegisterAllocationData *RAData, bool GDBEnabled) {
 
   const auto IRSize = AlignUp(IR->GetInlineSize(), 16);
@@ -103,12 +88,8 @@ void InterpreterCore::ClearCache() {
   BufferUsed = 0;
 }
 
-std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  return std::make_unique<InterpreterCore>(ctx->Dispatcher.get(), Thread);
-}
-
-void InitializeInterpreterSignalHandlers(FEXCore::Context::ContextImpl *CTX) {
-  InterpreterCore::InitializeSignalHandlers(CTX);
+fextl::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  return fextl::make_unique<InterpreterCore>(ctx->Dispatcher.get(), Thread);
 }
 
 CPUBackendFeatures GetInterpreterBackendFeatures() {

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterCore.h

@@ -1,6 +1,7 @@
 #pragma once
 
-#include <memory>
+#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/fextl/memory.h>
 
 namespace FEXCore::Context {
 class ContextImpl;
@@ -14,7 +15,7 @@ namespace FEXCore::CPU {
 class CPUBackend;
 struct DispatcherConfig;
 
-[[nodiscard]] std::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::ContextImpl *ctx,
+[[nodiscard]] fextl::unique_ptr<CPUBackend> CreateInterpreterCore(FEXCore::Context::ContextImpl *ctx,
                                                                 FEXCore::Core::InternalThreadState *Thread);
 void InitializeInterpreterSignalHandlers(FEXCore::Context::ContextImpl *CTX);
 CPUBackendFeatures GetInterpreterBackendFeatures();

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp

@@ -2,11 +2,6 @@
 #include "Interface/Core/CPUID.h"
 #include "InterpreterDefines.h"
 #include "InterpreterOps.h"
-#include "F80Ops.h"
-
-#ifdef _M_ARM_64
-#include "Interface/Core/ArchHelpers/Arm64.h"
-#endif
 
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Core/CoreState.h>
@@ -57,6 +52,7 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(ADD,                    Add);
   REGISTER_OP(SUB,                    Sub);
   REGISTER_OP(NEG,                    Neg);
+  REGISTER_OP(ABS,                    Abs);
   REGISTER_OP(MUL,                    Mul);
   REGISTER_OP(UMUL,                   UMul);
   REGISTER_OP(DIV,                    Div);
@@ -123,6 +119,7 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(VALIDATECODE,           ValidateCode);
   REGISTER_OP(THREADREMOVECODEENTRY,        ThreadRemoveCodeEntry);
   REGISTER_OP(CPUID,                  CPUID);
+  REGISTER_OP(XGETBV,                 XGETBV);
 
   // Conversion ops
   REGISTER_OP(VINSGPR,                VInsGPR);
@@ -154,7 +151,10 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(STOREMEM,               StoreMem);
   REGISTER_OP(LOADMEMTSO,             LoadMem);
   REGISTER_OP(STOREMEMTSO,            StoreMem);
+  REGISTER_OP(VLOADVECTORMASKED,      VLoadVectorMasked);
+  REGISTER_OP(VSTOREVECTORMASKED,     VStoreVectorMasked);
   REGISTER_OP(MEMSET,                 MemSet);
+  REGISTER_OP(MEMCPY,                 MemCpy);
   REGISTER_OP(CACHELINECLEAR,         CacheLineClear);
   REGISTER_OP(CACHELINECLEAN,         CacheLineClean);
   REGISTER_OP(CACHELINEZERO,          CacheLineZero);
@@ -267,8 +267,11 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(VUMULL2,                VUMull2);
   REGISTER_OP(VSMULL2,                VSMull2);
   REGISTER_OP(VUABDL,                 VUABDL);
+  REGISTER_OP(VUABDL2,                VUABDL2);
   REGISTER_OP(VTBL1,                  VTBL1);
   REGISTER_OP(VREV64,                 VRev64);
+  REGISTER_OP(VPCMPESTRX,             VPCMPESTRX);
+  REGISTER_OP(VPCMPISTRX,             VPCMPISTRX);
 
   // Encryption ops
   REGISTER_OP(VAESIMC,                AESImc);

External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h

@@ -36,6 +36,8 @@ namespace FEXCore::CPU {
     FABI_I64_F80_F80,
     FABI_F80_F80,
     FABI_F80_F80_F80,
+    FABI_I32_I64_I64_I128_I128_I16,
+    FABI_I32_I128_I128_I16,
   };
 
   struct FallbackInfo {
@@ -83,6 +85,7 @@ namespace FEXCore::CPU {
   DEF_OP(Add);
   DEF_OP(Sub);
   DEF_OP(Neg);
+  DEF_OP(Abs);
   DEF_OP(Mul);
   DEF_OP(UMul);
   DEF_OP(Div);
@@ -152,6 +155,7 @@ namespace FEXCore::CPU {
   DEF_OP(ValidateCode);
   DEF_OP(ThreadRemoveCodeEntry);
   DEF_OP(CPUID);
+  DEF_OP(XGETBV);
 
   ///< Conversion ops
   DEF_OP(VInsGPR);
@@ -181,7 +185,10 @@ namespace FEXCore::CPU {
   DEF_OP(StoreFlag);
   DEF_OP(LoadMem);
   DEF_OP(StoreMem);
+  DEF_OP(VLoadVectorMasked);
+  DEF_OP(VStoreVectorMasked);
   DEF_OP(MemSet);
+  DEF_OP(MemCpy);
   DEF_OP(CacheLineClear);
   DEF_OP(CacheLineClean);
   DEF_OP(CacheLineZero);
@@ -286,8 +293,11 @@ namespace FEXCore::CPU {
   DEF_OP(VUMull2);
   DEF_OP(VSMull2);
   DEF_OP(VUABDL);
+  DEF_OP(VUABDL2);
   DEF_OP(VTBL1);
   DEF_OP(VRev64);
+  DEF_OP(VPCMPESTRX);
+  DEF_OP(VPCMPISTRX);
 
   ///< Encryption ops
   DEF_OP(AESImc);
@@ -340,6 +350,15 @@ namespace FEXCore::CPU {
   template<typename unsigned_type, typename signed_type, typename float_type>
   [[nodiscard]] static bool IsConditionTrue(uint8_t Cond, uint64_t Src1, uint64_t Src2) {
     bool CompResult = false;
+    if constexpr (sizeof(unsigned_type) == 16) {
+      LOGMAN_THROW_A_FMT(Cond != FEXCore::IR::COND_FLU &&
+        Cond != FEXCore::IR::COND_FGE &&
+        Cond != FEXCore::IR::COND_FLEU &&
+        Cond != FEXCore::IR::COND_FGT &&
+        Cond != FEXCore::IR::COND_FU &&
+        Cond != FEXCore::IR::COND_FNU, "Unsupported comparison for 128-bit floats");
+    }
+
     switch (Cond) {
       case FEXCore::IR::COND_EQ:
         CompResult = static_cast<unsigned_type>(Src1) == static_cast<unsigned_type>(Src2);

External/FEXCore/Source/Interface/Core/Interpreter/MemoryOps.cpp

@@ -190,19 +190,31 @@ DEF_OP(LoadFlag) {
   uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
   ContextPtr += offsetof(FEXCore::Core::CPUState, flags[0]);
   ContextPtr += Op->Flag;
-  uint8_t const *MemData = reinterpret_cast<uint8_t const*>(ContextPtr);
-  GD = *MemData;
+
+  if (Op->Flag == 24 /* NZCV */) {
+    uint32_t const *MemData = reinterpret_cast<uint32_t const*>(ContextPtr);
+    GD = *MemData;
+  } else {
+    uint8_t const *MemData = reinterpret_cast<uint8_t const*>(ContextPtr);
+    GD = *MemData;
+  }
 }
 
 DEF_OP(StoreFlag) {
   auto Op = IROp->C<IR::IROp_StoreFlag>();
-  uint8_t Arg = *GetSrc<uint8_t*>(Data->SSAData, Op->Value);
+  uint32_t Arg = *GetSrc<uint32_t*>(Data->SSAData, Op->Value);
 
   uintptr_t ContextPtr = reinterpret_cast<uintptr_t>(Data->State->CurrentFrame);
   ContextPtr += offsetof(FEXCore::Core::CPUState, flags[0]);
   ContextPtr += Op->Flag;
-  uint8_t *MemData = reinterpret_cast<uint8_t*>(ContextPtr);
-  *MemData = Arg;
+
+  if (Op->Flag == 24 /* NZCV */) {
+    uint32_t *MemData = reinterpret_cast<uint32_t*>(ContextPtr);
+    *MemData = Arg;
+  } else {
+    uint8_t *MemData = reinterpret_cast<uint8_t*>(ContextPtr);
+    *MemData = Arg;
+  }
 }
 
 DEF_OP(LoadMem) {
@@ -288,11 +300,134 @@ DEF_OP(StoreMem) {
   }
 }
 
+DEF_OP(VLoadVectorMasked) {
+  const auto Op = IROp->C<IR::IROp_VLoadVectorMasked>();
+  const auto OpSize = IROp->Size;
+
+  const auto ElementSize = IROp->ElementSize;
+  const auto NumElements = OpSize / ElementSize;
+
+  const auto *MemData = *GetSrc<uint8_t const**>(Data->SSAData, Op->Addr);
+  const auto *Mask = GetSrc<uint8_t const*>(Data->SSAData, Op->Mask);
+
+  const auto SetElements = [NumElements]<typename T>(void* Dst, const T* MaskValues, const T* MemoryData) {
+    const auto SignBit = 1ULL << ((sizeof(T) * 8) - 1);
+    for (size_t i = 0; i < NumElements; i++) {
+      if ((MaskValues[i] & SignBit) != 0) {
+        std::memcpy(static_cast<uint8_t*>(Dst) + (i * sizeof(T)), MemoryData + i, sizeof(T));
+      }
+    }
+  };
+
+  if (!Op->Offset.IsInvalid()) {
+    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
+
+    switch(Op->OffsetType.Val) {
+      case IR::MEM_OFFSET_SXTX.Val: MemData +=  Offset; break;
+      case IR::MEM_OFFSET_UXTW.Val: MemData += (uint32_t)Offset; break;
+      case IR::MEM_OFFSET_SXTW.Val: MemData += (int32_t)Offset; break;
+    }
+  }
+
+  memset(GDP, 0, Core::CPUState::XMM_AVX_REG_SIZE);
+  switch (ElementSize) {
+    case 1: {
+      SetElements(GDP, Mask, MemData);
+      return;
+    }
+    case 2: {
+      SetElements(GDP,
+                  reinterpret_cast<const uint16_t*>(Mask),
+                  reinterpret_cast<const uint16_t*>(MemData));
+      return;
+    }
+    case 4: {
+      SetElements(GDP,
+                  reinterpret_cast<const uint32_t*>(Mask),
+                  reinterpret_cast<const uint32_t*>(MemData));
+      return;
+    }
+    case 8: {
+      SetElements(GDP,
+                  reinterpret_cast<const uint64_t*>(Mask),
+                  reinterpret_cast<const uint64_t*>(MemData));
+      return;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled VLoadVectorMasked element size: {}", ElementSize);
+      return;
+  }
+}
+
+DEF_OP(VStoreVectorMasked) {
+  const auto Op = IROp->C<IR::IROp_VStoreVectorMasked>();
+  const auto OpSize = IROp->Size;
+
+  const auto ElementSize = IROp->ElementSize;
+  const auto NumElements = OpSize / ElementSize;
+
+  auto *Dst = *GetSrc<uint8_t**>(Data->SSAData, Op->Addr);
+  const auto *RegData = GetSrc<uint8_t const*>(Data->SSAData, Op->Data);
+  const auto *Mask = GetSrc<uint8_t const*>(Data->SSAData, Op->Mask);
+
+  const auto SetElements = [NumElements]<typename T>(void* Dst, const T* MaskValues, const T* DataVals) {
+    const auto SignBit = 1ULL << ((sizeof(T) * 8) - 1);
+    for (size_t i = 0; i < NumElements; i++) {
+      if ((MaskValues[i] & SignBit) != 0) {
+        std::memcpy(static_cast<uint8_t*>(Dst) + (i * sizeof(T)), DataVals + i, sizeof(T));
+      }
+    }
+  };
+
+  if (!Op->Offset.IsInvalid()) {
+    auto Offset = *GetSrc<uintptr_t const*>(Data->SSAData, Op->Offset) * Op->OffsetScale;
+
+    switch(Op->OffsetType.Val) {
+      case IR::MEM_OFFSET_SXTX.Val: Dst +=  Offset; break;
+      case IR::MEM_OFFSET_UXTW.Val: Dst += (uint32_t)Offset; break;
+      case IR::MEM_OFFSET_SXTW.Val: Dst += (int32_t)Offset; break;
+    }
+  }
+
+  switch (ElementSize) {
+    case 1: {
+      SetElements(Dst, Mask, RegData);
+      return;
+    }
+    case 2: {
+      SetElements(Dst,
+                  reinterpret_cast<const uint16_t*>(Mask),
+                  reinterpret_cast<const uint16_t*>(RegData));
+      return;
+    }
+    case 4: {
+      SetElements(Dst,
+                  reinterpret_cast<const uint32_t*>(Mask),
+                  reinterpret_cast<const uint32_t*>(RegData));
+      return;
+    }
+    case 8: {
+      SetElements(Dst,
+                  reinterpret_cast<const uint64_t*>(Mask),
+                  reinterpret_cast<const uint64_t*>(RegData));
+      return;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled VStoreVectorMasked element size: {}", ElementSize);
+      return;
+  }
+}
+
 DEF_OP(MemSet) {
   const auto Op = IROp->C<IR::IROp_MemSet>();
   const int32_t Size = Op->Size;
 
   char *MemData = *GetSrc<char **>(Data->SSAData, Op->Addr);
+  uint64_t MemPrefix{};
+  if (!Op->Prefix.IsInvalid()) {
+    MemPrefix = *GetSrc<uint64_t*>(Data->SSAData, Op->Prefix);
+  }
+
   const auto Value = *GetSrc<uint64_t*>(Data->SSAData, Op->Value);
   const auto Length = *GetSrc<uint64_t*>(Data->SSAData, Op->Length);
   const auto Direction = *GetSrc<uint8_t*>(Data->SSAData, Op->Direction);
@@ -313,16 +448,16 @@ DEF_OP(MemSet) {
     if (Op->IsAtomic) {
       switch (Size) {
         case 1:
-          MemSetElements(reinterpret_cast<std::atomic<uint8_t>*>(MemData), Value, Length);
+          MemSetElements(reinterpret_cast<std::atomic<uint8_t>*>(MemData + MemPrefix), Value, Length);
           break;
         case 2:
-          MemSetElements(reinterpret_cast<std::atomic<uint16_t>*>(MemData), Value, Length);
+          MemSetElements(reinterpret_cast<std::atomic<uint16_t>*>(MemData + MemPrefix), Value, Length);
           break;
         case 4:
-          MemSetElements(reinterpret_cast<std::atomic<uint32_t>*>(MemData), Value, Length);
+          MemSetElements(reinterpret_cast<std::atomic<uint32_t>*>(MemData + MemPrefix), Value, Length);
           break;
         case 8:
-          MemSetElements(reinterpret_cast<std::atomic<uint64_t>*>(MemData), Value, Length);
+          MemSetElements(reinterpret_cast<std::atomic<uint64_t>*>(MemData + MemPrefix), Value, Length);
           break;
         default:
           LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
@@ -332,16 +467,16 @@ DEF_OP(MemSet) {
     else {
       switch (Size) {
         case 1:
-          MemSetElements(reinterpret_cast<uint8_t*>(MemData), Value, Length);
+          MemSetElements(reinterpret_cast<uint8_t*>(MemData + MemPrefix), Value, Length);
           break;
         case 2:
-          MemSetElements(reinterpret_cast<uint16_t*>(MemData), Value, Length);
+          MemSetElements(reinterpret_cast<uint16_t*>(MemData + MemPrefix), Value, Length);
           break;
         case 4:
-          MemSetElements(reinterpret_cast<uint32_t*>(MemData), Value, Length);
+          MemSetElements(reinterpret_cast<uint32_t*>(MemData + MemPrefix), Value, Length);
           break;
         case 8:
-          MemSetElements(reinterpret_cast<uint64_t*>(MemData), Value, Length);
+          MemSetElements(reinterpret_cast<uint64_t*>(MemData + MemPrefix), Value, Length);
           break;
         default:
           LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
@@ -354,16 +489,16 @@ DEF_OP(MemSet) {
     if (Op->IsAtomic) {
       switch (Size) {
         case 1:
-          MemSetElementsInverse(reinterpret_cast<std::atomic<uint8_t>*>(MemData), Value, Length);
+          MemSetElementsInverse(reinterpret_cast<std::atomic<uint8_t>*>(MemData + MemPrefix), Value, Length);
           break;
         case 2:
-          MemSetElementsInverse(reinterpret_cast<std::atomic<uint16_t>*>(MemData), Value, Length);
+          MemSetElementsInverse(reinterpret_cast<std::atomic<uint16_t>*>(MemData + MemPrefix), Value, Length);
           break;
         case 4:
-          MemSetElementsInverse(reinterpret_cast<std::atomic<uint32_t>*>(MemData), Value, Length);
+          MemSetElementsInverse(reinterpret_cast<std::atomic<uint32_t>*>(MemData + MemPrefix), Value, Length);
           break;
         case 8:
-          MemSetElementsInverse(reinterpret_cast<std::atomic<uint64_t>*>(MemData), Value, Length);
+          MemSetElementsInverse(reinterpret_cast<std::atomic<uint64_t>*>(MemData + MemPrefix), Value, Length);
           break;
         default:
           LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
@@ -373,16 +508,16 @@ DEF_OP(MemSet) {
     else {
       switch (Size) {
         case 1:
-          MemSetElementsInverse(reinterpret_cast<uint8_t*>(MemData), Value, Length);
+          MemSetElementsInverse(reinterpret_cast<uint8_t*>(MemData + MemPrefix), Value, Length);
           break;
         case 2:
-          MemSetElementsInverse(reinterpret_cast<uint16_t*>(MemData), Value, Length);
+          MemSetElementsInverse(reinterpret_cast<uint16_t*>(MemData + MemPrefix), Value, Length);
           break;
         case 4:
-          MemSetElementsInverse(reinterpret_cast<uint32_t*>(MemData), Value, Length);
+          MemSetElementsInverse(reinterpret_cast<uint32_t*>(MemData + MemPrefix), Value, Length);
           break;
         case 8:
-          MemSetElementsInverse(reinterpret_cast<uint64_t*>(MemData), Value, Length);
+          MemSetElementsInverse(reinterpret_cast<uint64_t*>(MemData + MemPrefix), Value, Length);
           break;
         default:
           LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
@@ -393,6 +528,138 @@ DEF_OP(MemSet) {
   }
 }
 
+DEF_OP(MemCpy) {
+  const auto Op = IROp->C<IR::IROp_MemCpy>();
+  const int32_t Size = Op->Size;
+
+  uint64_t *DstPtr = GetDest<uint64_t*>(Data->SSAData, Node);
+
+  char *MemDataDest = *GetSrc<char **>(Data->SSAData, Op->AddrDest);
+  char *MemDataSrc = *GetSrc<char **>(Data->SSAData, Op->AddrSrc);
+
+  uint64_t DestPrefix{};
+  uint64_t SrcPrefix{};
+  if (!Op->PrefixDest.IsInvalid()) {
+    DestPrefix = *GetSrc<uint64_t*>(Data->SSAData, Op->PrefixDest);
+
+  }
+  if (!Op->PrefixSrc.IsInvalid()) {
+    SrcPrefix = *GetSrc<uint64_t*>(Data->SSAData, Op->PrefixSrc);
+  }
+
+  const auto Length = *GetSrc<uint64_t*>(Data->SSAData, Op->Length);
+  const auto Direction = *GetSrc<uint8_t*>(Data->SSAData, Op->Direction);
+
+  auto MemSetElementsAtomic = [](auto* MemDst, auto* MemSrc, size_t Length) {
+    for (size_t i = 0; i < Length; ++i) {
+      MemDst[i].store(MemSrc[i].load());
+    }
+  };
+
+  auto MemSetElementsAtomicInverse = [](auto* MemDst, auto* MemSrc, size_t Length) {
+    for (size_t i = 0; i < Length; ++i) {
+      MemDst[-i].store(MemSrc[-i].load());
+    }
+  };
+
+  auto MemSetElements = [](auto* MemDst, auto* MemSrc, size_t Length) {
+    for (size_t i = 0; i < Length; ++i) {
+      MemDst[i] = MemSrc[i];
+    }
+  };
+
+  auto MemSetElementsInverse = [](auto* MemDst, auto* MemSrc, size_t Length) {
+    for (size_t i = 0; i < Length; ++i) {
+      MemDst[-i] = MemSrc[-i];
+    }
+  };
+
+  if (Direction == 0) { // Forward
+    if (Op->IsAtomic) {
+      switch (Size) {
+        case 1:
+          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint8_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint8_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 2:
+          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint16_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint16_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 4:
+          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint32_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint32_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 8:
+          MemSetElementsAtomic(reinterpret_cast<std::atomic<uint64_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint64_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    else {
+      switch (Size) {
+        case 1:
+          MemSetElements(reinterpret_cast<uint8_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint8_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 2:
+          MemSetElements(reinterpret_cast<uint16_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint16_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 4:
+          MemSetElements(reinterpret_cast<uint32_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint32_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 8:
+          MemSetElements(reinterpret_cast<uint64_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint64_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    DstPtr[0] = reinterpret_cast<uint64_t>(MemDataDest + (Length * Size));
+    DstPtr[1] = reinterpret_cast<uint64_t>(MemDataSrc + (Length * Size));
+  }
+  else { // Backward
+    if (Op->IsAtomic) {
+      switch (Size) {
+        case 1:
+          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint8_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint8_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 2:
+          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint16_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint16_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 4:
+          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint32_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint32_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 8:
+          MemSetElementsAtomicInverse(reinterpret_cast<std::atomic<uint64_t>*>(MemDataDest + DestPrefix), reinterpret_cast<std::atomic<uint64_t>*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    else {
+      switch (Size) {
+        case 1:
+          MemSetElementsInverse(reinterpret_cast<uint8_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint8_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 2:
+          MemSetElementsInverse(reinterpret_cast<uint16_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint16_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 4:
+          MemSetElementsInverse(reinterpret_cast<uint32_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint32_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        case 8:
+          MemSetElementsInverse(reinterpret_cast<uint64_t*>(MemDataDest + DestPrefix), reinterpret_cast<uint64_t*>(MemDataSrc + SrcPrefix), Length);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+    DstPtr[0] = reinterpret_cast<uint64_t>(MemDataDest - (Length * Size));
+    DstPtr[1] = reinterpret_cast<uint64_t>(MemDataSrc - (Length * Size));
+  }
+}
+
 DEF_OP(CacheLineClear) {
   auto Op = IROp->C<IR::IROp_CacheLineClear>();
 

External/FEXCore/Source/Interface/Core/Interpreter/VectorOps.cpp

@@ -8,6 +8,8 @@ $end_info$
 #include "Interface/Core/Interpreter/InterpreterOps.h"
 #include "Interface/Core/Interpreter/InterpreterDefines.h"
 
+#include "Interface/Core/Interpreter/Fallbacks/VectorFallbacks.h"
+
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Utils/BitUtils.h>
 
@@ -2225,6 +2227,33 @@ DEF_OP(VUABDL) {
   memcpy(GDP, Tmp, OpSize);
 }
 
+DEF_OP(VUABDL2) {
+  const auto Op = IROp->C<IR::IROp_VUABDL2>();
+  const uint8_t OpSize = IROp->Size;
+
+  void *Src1 = GetSrc<void*>(Data->SSAData, Op->Vector1);
+  void *Src2 = GetSrc<void*>(Data->SSAData, Op->Vector2);
+
+  uint8_t Tmp[Core::CPUState::XMM_AVX_REG_SIZE];
+
+  const uint8_t ElementSize = Op->Header.ElementSize;
+  const uint8_t Elements = OpSize / ElementSize;
+
+  const auto Func8 = [](auto a, auto b) { return std::abs((int16_t)a - (int16_t)b); };
+  const auto Func16 = [](auto a, auto b) { return std::abs((int32_t)a - (int32_t)b); };
+  const auto Func32 = [](auto a, auto b) { return std::abs((int64_t)a - (int64_t)b); };
+
+  switch (ElementSize) {
+    DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(2, uint16_t, uint8_t, Func8)
+    DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(4, uint32_t, uint16_t, Func16)
+    DO_VECTOR_2SRC_2TYPE_OP_TOP_SRC(8, uint64_t, uint32_t, Func32)
+    default:
+      LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
+      break;
+  }
+  memcpy(GDP, Tmp, OpSize);
+}
+
 DEF_OP(VTBL1) {
   const auto Op = IROp->C<IR::IROp_VTBL1>();
   const uint8_t OpSize = IROp->Size;
@@ -2276,6 +2305,34 @@ DEF_OP(VRev64) {
   memcpy(GDP, Tmp, OpSize);
 }
 
+DEF_OP(VPCMPESTRX) {
+  const auto Op = IROp->C<IR::IROp_VPCMPESTRX>();
+  const auto Control = Op->Control;
+
+  const auto RAX = *GetSrc<uint64_t*>(Data->SSAData, Op->RAX);
+  const auto RDX = *GetSrc<uint64_t*>(Data->SSAData, Op->RDX);
+  const auto LHS = *GetSrc<__uint128_t*>(Data->SSAData, Op->LHS);
+  const auto RHS = *GetSrc<__uint128_t*>(Data->SSAData, Op->RHS);
+
+  const auto Result = OpHandlers<IR::OP_VPCMPESTRX>::handle(RAX, RDX, LHS, RHS, Control);
+
+  memset(GDP, 0, sizeof(uint64_t));
+  memcpy(GDP, &Result, sizeof(Result));
+}
+
+DEF_OP(VPCMPISTRX) {
+  const auto Op = IROp->C<IR::IROp_VPCMPISTRX>();
+
+  const auto LHS = *GetSrc<__uint128_t*>(Data->SSAData, Op->LHS);
+  const auto RHS = *GetSrc<__uint128_t*>(Data->SSAData, Op->RHS);
+  const auto Control = Op->Control;
+
+  const auto Result = OpHandlers<IR::OP_VPCMPISTRX>::handle(LHS, RHS, Control);
+
+  memset(GDP, 0, sizeof(uint64_t));
+  memcpy(GDP, &Result, sizeof(Result));
+}
+
 #undef DEF_OP
 
 } // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp

@@ -4,6 +4,7 @@ tags: backend|arm64
 $end_info$
 */
 
+#include "Interface/Context/Context.h"
 #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
@@ -83,6 +84,21 @@ DEF_OP(Add) {
   }
 }
 
+DEF_OP(TestNZ) {
+  auto Op = IROp->C<IR::IROp_TestNZ>();
+  const uint8_t OpSize = Op->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == 4 || OpSize == 8, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  const auto Dst = GetReg(Node);
+  const auto Src = GetReg(Op->Src1.ID());
+  tst(EmitSize, Src, Src);
+
+  // TODO: Optimize this out
+  mrs(Dst, ARMEmitter::SystemRegister::NZCV);
+}
+
 DEF_OP(Sub) {
   auto Op = IROp->C<IR::IROp_Sub>();
   const uint8_t OpSize = IROp->Size;
@@ -108,6 +124,26 @@ DEF_OP(Neg) {
   neg(EmitSize, GetReg(Node), GetReg(Op->Src.ID()));
 }
 
+DEF_OP(Abs) {
+  auto Op = IROp->C<IR::IROp_Abs>();
+  const uint8_t OpSize = IROp->Size;
+
+  LOGMAN_THROW_AA_FMT(OpSize == 4 || OpSize == 8, "Unsupported {} size: {}", __func__, OpSize);
+  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  const auto Dst = GetReg(Node);
+  auto Src = GetReg(Op->Src.ID());
+
+  if (CTX->HostFeatures.SupportsCSSC) {
+    // On CSSC supporting processors, this turns in to one instruction and doesn't modify flags.
+    abs(EmitSize, Dst, Src);
+  }
+  else {
+    cmp(EmitSize, Src, 0);
+    cneg(EmitSize, Dst, Src, ARMEmitter::Condition::CC_MI);
+  }
+}
+
 DEF_OP(Mul) {
   auto Op = IROp->C<IR::IROp_Mul>();
   const uint8_t OpSize = IROp->Size;
@@ -310,6 +346,40 @@ DEF_OP(Or) {
   }
 }
 
+DEF_OP(Orlshl) {
+  auto Op = IROp->C<IR::IROp_Orlshl>();
+  const uint8_t OpSize = IROp->Size;
+  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  const auto Dst = GetReg(Node);
+  const auto Src1 = GetReg(Op->Src1.ID());
+
+  uint64_t Const;
+  if (IsInlineConstant(Op->Src2, &Const)) {
+    orr(EmitSize, Dst, Src1, Const << Op->BitShift);
+  } else {
+    const auto Src2 = GetReg(Op->Src2.ID());
+    orr(EmitSize, Dst, Src1, Src2, ARMEmitter::ShiftType::LSL, Op->BitShift);
+  }
+}
+
+DEF_OP(Orlshr) {
+  auto Op = IROp->C<IR::IROp_Orlshr>();
+  const uint8_t OpSize = IROp->Size;
+  const auto EmitSize = OpSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
+
+  const auto Dst = GetReg(Node);
+  const auto Src1 = GetReg(Op->Src1.ID());
+
+  uint64_t Const;
+  if (IsInlineConstant(Op->Src2, &Const)) {
+    orr(EmitSize, Dst, Src1, Const >> Op->BitShift);
+  } else {
+    const auto Src2 = GetReg(Op->Src2.ID());
+    orr(EmitSize, Dst, Src1, Src2, ARMEmitter::ShiftType::LSR, Op->BitShift);
+  }
+}
+
 DEF_OP(And) {
   auto Op = IROp->C<IR::IROp_And>();
   const uint8_t OpSize = IROp->Size;
@@ -477,9 +547,9 @@ DEF_OP(PDep) {
   const auto IndexReg      = TMP4.R();
   const auto ZeroReg       = ARMEmitter::Reg::zr;
 
-  const auto InputReg = SRA64[0];
-  const auto MaskReg  = SRA64[1];
-  const auto DestReg  = SRA64[2];
+  const auto InputReg = StaticRegisters[0];
+  const auto MaskReg  = StaticRegisters[1];
+  const auto DestReg  = StaticRegisters[2];
 
   const auto SpillCode = 1U << InputReg.Idx() |
                          1U << MaskReg.Idx() |
@@ -494,7 +564,7 @@ DEF_OP(PDep) {
   // We sadly need to spill regs for this for the time being
   // TODO: Remove when scratch registers can be allocated
   //       explicitly.
-  SpillStaticRegs(false, SpillCode);
+  SpillStaticRegs(TMP1, false, SpillCode);
 
 
   mov(EmitSize, InputReg, Input);
@@ -558,7 +628,7 @@ DEF_OP(PExt) {
   // We sadly need to spill a reg for this for the time being
   // TODO: Remove when scratch registers can be allocated
   //       explicitly.
-  SpillStaticRegs(false, 1U << Mask.Idx());
+  SpillStaticRegs(TMP2, false, 1U << Mask.Idx());
   mov(EmitSize, Mask, ZeroReg);
 
   // Main loop
@@ -633,7 +703,10 @@ DEF_OP(LDiv) {
         mov(EmitSize, ARMEmitter::Reg::r2, Divisor);
 
         ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LDIVHandler));
+
+        str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
         blr(ARMEmitter::Reg::r3);
+        ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
 
         // Move result to its destination register
         mov(EmitSize, Dst, ARMEmitter::Reg::r0);
@@ -697,7 +770,11 @@ DEF_OP(LUDiv) {
         mov(EmitSize, ARMEmitter::Reg::r2, Divisor);
 
         ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUDIVHandler));
+
+        str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
         blr(ARMEmitter::Reg::r3);
+        ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
+
         // Move result to its destination register
         mov(EmitSize, Dst, ARMEmitter::Reg::r0);
 
@@ -768,7 +845,11 @@ DEF_OP(LRem) {
         mov(EmitSize, ARMEmitter::Reg::r2, Divisor);
 
         ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LREMHandler));
+
+        str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
         blr(ARMEmitter::Reg::r3);
+        ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
+
         // Move result to its destination register
         mov(EmitSize, Dst, ARMEmitter::Reg::r0);
 
@@ -833,7 +914,11 @@ DEF_OP(LURem) {
         mov(EmitSize, ARMEmitter::Reg::r2, Divisor);
 
         ldr(ARMEmitter::XReg::x3, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.AArch64.LUREMHandler));
+
+        str<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, -16);
         blr(ARMEmitter::Reg::r3);
+        ldr<ARMEmitter::IndexType::POST>(ARMEmitter::XReg::lr, ARMEmitter::Reg::rsp, 16);
+
         // Move result to its destination register
         mov(EmitSize, Dst, ARMEmitter::Reg::r0);
 
@@ -1020,14 +1105,22 @@ DEF_OP(Bfi) {
   const auto SrcDst = GetReg(Op->Dest.ID());
   const auto Src = GetReg(Op->Src.ID());
 
-  mov(EmitSize, TMP1, SrcDst);
-  bfi(EmitSize, TMP1, Src, Op->lsb, Op->Width);
-
-  if (OpSize == 8) {
-    mov(EmitSize, Dst, TMP1.R());
+  if (Dst == SrcDst) {
+    // If Dst and SrcDst match then this turns in to a simple BFI instruction.
+    bfi(EmitSize, Dst, Src, Op->lsb, Op->Width);
   }
   else {
-    ubfx(EmitSize, Dst, TMP1, 0, OpSize * 8);
+    // Destination didn't match the dst source register.
+    // TODO: Inefficient until FEX can have RA constraints here.
+    mov(EmitSize, TMP1, SrcDst);
+    bfi(EmitSize, TMP1, Src, Op->lsb, Op->Width);
+
+    if (OpSize == 8) {
+      mov(EmitSize, Dst, TMP1.R());
+    }
+    else {
+      ubfx(EmitSize, Dst, TMP1, 0, OpSize * 8);
+    }
   }
 }
 
@@ -1085,6 +1178,7 @@ DEF_OP(Select) {
   const auto CompareEmitSize = Op->CompareSize == 8 ? ARMEmitter::Size::i64Bit : ARMEmitter::Size::i32Bit;
 
   uint64_t Const;
+  auto cc = MapSelectCC(Op->Cond);
 
   if (IsGPR(Op->Cmp1.ID())) {
     const auto Src1 = GetReg(Op->Cmp1.ID());
@@ -1095,7 +1189,14 @@ DEF_OP(Select) {
       const auto Src2 = GetReg(Op->Cmp2.ID());
       cmp(CompareEmitSize, Src1, Src2);
     }
-  } else if (IsFPR(Op->Cmp1.ID())) {
+  }
+  else if (IsGPRPair(Op->Cmp1.ID())) {
+    const auto Src1 = GetRegPair(Op->Cmp1.ID());
+    const auto Src2 = GetRegPair(Op->Cmp2.ID());
+    cmp(EmitSize, Src1.first, Src2.first);
+    ccmp(EmitSize, Src1.second, Src2.second, ARMEmitter::StatusFlags::None, cc);
+  }
+  else if (IsFPR(Op->Cmp1.ID())) {
     const auto Src1 = GetVReg(Op->Cmp1.ID());
     const auto Src2 = GetVReg(Op->Cmp2.ID());
     fcmp(Op->CompareSize == 8 ? ARMEmitter::ScalarRegSize::i64Bit : ARMEmitter::ScalarRegSize::i32Bit, Src1, Src2);
@@ -1103,8 +1204,6 @@ DEF_OP(Select) {
     LOGMAN_MSG_A_FMT("Select: Expected GPR or FPR");
   }
 
-  auto cc = MapSelectCC(Op->Cond);
-
   uint64_t const_true, const_false;
   bool is_const_true = IsInlineConstant(Op->TrueVal, &const_true);
   bool is_const_false = IsInlineConstant(Op->FalseVal, &const_false);

External/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp

@@ -22,7 +22,7 @@ namespace FEXCore::CPU {
 
 DEF_OP(CallbackReturn) {
   // spill back to CTX
-  SpillStaticRegs();
+  SpillStaticRegs(TMP1);
 
   // First we must reset the stack
   ResetStack();
@@ -175,7 +175,7 @@ DEF_OP(Syscall) {
     FPRSpillMask = CALLER_FPR_MASK;
   }
 
-  SpillStaticRegs(true, GPRSpillMask, FPRSpillMask);
+  SpillStaticRegs(TMP1, true, GPRSpillMask, FPRSpillMask);
 
   // Now that we are spilled, store in the state that we are in a syscall
   // Still without overwriting registers that matter
@@ -216,8 +216,11 @@ DEF_OP(Syscall) {
 
     PopDynamicRegsAndLR();
 
-    // Move result to its destination register
-    mov(ARMEmitter::Size::i64Bit, GetReg(Node), ARMEmitter::Reg::r0);
+    if ((Flags & FEXCore::IR::SyscallFlags::NORETURNEDRESULT) != FEXCore::IR::SyscallFlags::NORETURNEDRESULT) {
+      // Move result to its destination register.
+      // Only if `NORETURNEDRESULT` wasn't set, otherwise we might overwrite the CPUState refilled with `FillStaticRegs`
+      mov(ARMEmitter::Size::i64Bit, GetReg(Node), ARMEmitter::Reg::r0);
+    }
   }
 }
 
@@ -257,7 +260,7 @@ DEF_OP(InlineSyscall) {
   // Ordering is incredibly important here
   // We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all
   // Only spill the registers that intersect with our usage
-  SpillStaticRegs(false, SpillMask);
+  SpillStaticRegs(TMP1, false, SpillMask);
 
   // Now that we are spilled, store in the state that we are in a syscall
   // Still without overwriting registers that matter
@@ -325,7 +328,7 @@ DEF_OP(Thunk) {
   // X0: CTX
   // X1: Args (from guest stack)
 
-  SpillStaticRegs(); // spill to ctx before ra64 spill
+  SpillStaticRegs(TMP1); // spill to ctx before ra64 spill
 
   PushDynamicRegsAndLR(TMP1);
 
@@ -400,12 +403,12 @@ DEF_OP(ThreadRemoveCodeEntry) {
   // X1: RIP
 
   PushDynamicRegsAndLR(TMP1);
+  SpillStaticRegs(TMP1);
 
   mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, STATE.R());
   LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r1, Entry);
 
   ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.ThreadRemoveCodeEntryFromJIT));
-  SpillStaticRegs();
 #ifdef VIXL_SIMULATOR
   GenerateIndirectRuntimeCall<void, void*, void*>(ARMEmitter::Reg::r2);
 #else
@@ -421,7 +424,7 @@ DEF_OP(CPUID) {
   auto Op = IROp->C<IR::IROp_CPUID>();
 
   PushDynamicRegsAndLR(TMP1);
-  SpillStaticRegs();
+  SpillStaticRegs(TMP1);
 
   // x0 = CPUID Handler
   // x1 = CPUID Function
@@ -447,6 +450,34 @@ DEF_OP(CPUID) {
   mov(ARMEmitter::Size::i64Bit, Dst.second, ARMEmitter::Reg::r1);
 }
 
+DEF_OP(XGETBV) {
+  auto Op = IROp->C<IR::IROp_XGetBV>();
+
+  PushDynamicRegsAndLR(TMP1);
+  SpillStaticRegs(TMP1);
+
+  // x0 = CPUID Handler
+  // x1 = XCR Function
+  ldr(ARMEmitter::XReg::x0, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj));
+  ldr(ARMEmitter::XReg::x2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.XCRFunction));
+  mov(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r1, GetReg(Op->Function.ID()));
+#ifdef VIXL_SIMULATOR
+  GenerateIndirectRuntimeCall<uint64_t, void*, uint32_t>(ARMEmitter::Reg::r2);
+#else
+  blr(ARMEmitter::Reg::r2);
+#endif
+
+  FillStaticRegs();
+
+  PopDynamicRegsAndLR();
+
+  // Results are in x0
+  // Results want to be in a i32v2 vector
+  auto Dst = GetRegPair(Node);
+  mov(ARMEmitter::Size::i32Bit, Dst.first,  ARMEmitter::Reg::r0);
+  lsr(ARMEmitter::Size::i64Bit, Dst.second, ARMEmitter::Reg::r0, 32);
+}
+
 #undef DEF_OP
 }
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp

@@ -14,8 +14,6 @@ $end_info$
 #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/LookupCache.h"
 
-#include "Interface/Core/ArchHelpers/Arm64.h"
-#include "Interface/Core/ArchHelpers/MContext.h"
 #include "Interface/Core/Dispatcher/Arm64Dispatcher.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "Interface/Core/InternalThreadState.h"
@@ -25,7 +23,6 @@ $end_info$
 #include "Utils/MemberFunctionToPointer.h"
 
 #include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Core/UContext.h>
 #include <FEXCore/Utils/Allocator.h>
 #include <FEXCore/Utils/CompilerDefs.h>
 #include <FEXCore/Utils/EnumUtils.h>
@@ -33,7 +30,6 @@ $end_info$
 
 #include "Interface/Core/Interpreter/InterpreterOps.h"
 
-#include <sys/mman.h>
 #include <stdio.h>
 #include <unistd.h>
 #include <string.h>
@@ -87,7 +83,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
   } else {
     switch(Info.ABI) {
       case FABI_VOID_U16:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -107,7 +103,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F80_F32:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
         const auto Src1 = GetVReg(IROp->Args[0].ID());
@@ -131,7 +127,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F80_F64:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -157,7 +153,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
 
       case FABI_F80_I16:
       case FABI_F80_I32: {
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -187,7 +183,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F32_F80:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -213,7 +209,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F64_F80:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -239,7 +235,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F64_F64: {
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -263,7 +259,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_F64_F64_F64: {
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -289,7 +285,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       break;
 
       case FABI_I16_F80:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -314,7 +310,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       }
       break;
       case FABI_I32_F80:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -339,7 +335,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       }
       break;
       case FABI_I64_F80:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -364,7 +360,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       }
       break;
       case FABI_I64_F80_F80:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -392,7 +388,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       }
       break;
       case FABI_F80_F80:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -419,7 +415,7 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
       }
       break;
       case FABI_F80_F80_F80:{
-        SpillStaticRegs();
+        SpillStaticRegs(TMP1);
 
         PushDynamicRegsAndLR(TMP1);
 
@@ -449,6 +445,75 @@ void Arm64JITCore::Op_Unhandled(IR::IROp_Header const *IROp, IR::NodeID Node) {
         ins(ARMEmitter::SubRegSize::i16Bit, Dst, 4, ARMEmitter::Reg::r1);
       }
       break;
+      case FABI_I32_I64_I64_I128_I128_I16: {
+        SpillStaticRegs(TMP1);
+        PushDynamicRegsAndLR(TMP1);
+
+        const auto Op = IROp->C<IR::IROp_VPCMPESTRX>();
+        const auto Control = Op->Control;
+
+        const auto Src1 = GetVReg(Op->LHS.ID());
+        const auto Src2 = GetVReg(Op->RHS.ID());
+        const auto SrcRAX = GetReg(Op->RAX.ID());
+        const auto SrcRDX = GetReg(Op->RDX.ID());
+
+        mov(ARMEmitter::XReg::x0, SrcRAX.X());
+        mov(ARMEmitter::XReg::x1, SrcRDX.X());
+
+        umov<ARMEmitter::SubRegSize::i64Bit>(ARMEmitter::Reg::r2, Src1, 0);
+        umov<ARMEmitter::SubRegSize::i64Bit>(ARMEmitter::Reg::r3, Src1, 1);
+
+        umov<ARMEmitter::SubRegSize::i64Bit>(ARMEmitter::Reg::r4, Src2, 0);
+        umov<ARMEmitter::SubRegSize::i64Bit>(ARMEmitter::Reg::r5, Src2, 1);
+
+        movz(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r6, Control);
+
+        ldr(ARMEmitter::XReg::x7, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
+#ifdef VIXL_SIMULATOR
+        GenerateIndirectRuntimeCall<uint32_t, uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, uint16_t>(ARMEmitter::Reg::r7);
+#else
+        blr(ARMEmitter::Reg::r7);
+#endif
+
+        PopDynamicRegsAndLR();
+        FillStaticRegs();
+
+        const auto Dst = GetReg(Node);
+        mov(Dst.W(), ARMEmitter::WReg::w0);
+        break;
+      }
+      case FABI_I32_I128_I128_I16: {
+        SpillStaticRegs(TMP1);
+        PushDynamicRegsAndLR(TMP1);
+
+        const auto Op = IROp->C<IR::IROp_VPCMPISTRX>();
+
+        const auto Src1 = GetVReg(Op->LHS.ID());
+        const auto Src2 = GetVReg(Op->RHS.ID());
+        const auto Control = Op->Control;
+
+        umov<ARMEmitter::SubRegSize::i64Bit>(ARMEmitter::Reg::r0, Src1, 0);
+        umov<ARMEmitter::SubRegSize::i64Bit>(ARMEmitter::Reg::r1, Src1, 1);
+
+        umov<ARMEmitter::SubRegSize::i64Bit>(ARMEmitter::Reg::r2, Src2, 0);
+        umov<ARMEmitter::SubRegSize::i64Bit>(ARMEmitter::Reg::r3, Src2, 1);
+
+        movz(ARMEmitter::Size::i32Bit, ARMEmitter::Reg::r4, Control);
+
+        ldr(ARMEmitter::XReg::x5, STATE_PTR(CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex]));
+#ifdef VIXL_SIMULATOR
+        GenerateIndirectRuntimeCall<uint32_t, uint64_t, uint64_t, uint64_t, uint64_t, uint16_t>(ARMEmitter::Reg::r5);
+#else
+        blr(ARMEmitter::Reg::r5);
+#endif
+
+        PopDynamicRegsAndLR();
+        FillStaticRegs();
+
+        const auto Dst = GetReg(Node);
+        mov(Dst.W(), ARMEmitter::WReg::w0);
+        break;
+      }
       case FABI_UNKNOWN:
       default:
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
@@ -484,7 +549,7 @@ static uint64_t Arm64JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Fram
     FEXCore::ARMEmitter::Emitter::ClearICache((void*)branch, 24);
 
     // Add de-linking handler
-    Context::ContextImpl::ThreadAddBlockLink(Thread, GuestRip, (uintptr_t)record, [branch, LinkerAddress]{
+    Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [branch, LinkerAddress]{
       FEXCore::ARMEmitter::Emitter emit((uint8_t*)(branch), 24);
       FEXCore::ARMEmitter::ForwardLabel l_BranchHost;
       emit.ldr(FEXCore::ARMEmitter::XReg::x0, &l_BranchHost);
@@ -498,7 +563,7 @@ static uint64_t Arm64JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Fram
     record[0] = HostCode;
 
     // Add de-linking handler
-    Context::ContextImpl::ThreadAddBlockLink(Thread, GuestRip, (uintptr_t)record, [record, LinkerAddress]{
+    Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [record, LinkerAddress]{
       record[0] = LinkerAddress;
     });
   }
@@ -517,20 +582,16 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::In
 
   RAPass = Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA");
 
-  uint32_t NumUsedGPRs = NumGPRs;
-  uint32_t NumUsedGPRPairs = NumGPRPairs;
-  uint32_t UsedRegisterCount = RegisterCount;
+  RAPass->AllocateRegisterSet(RegisterClasses);
 
-  RAPass->AllocateRegisterSet(UsedRegisterCount, RegisterClasses);
-
-  RAPass->AddRegisters(FEXCore::IR::GPRClass, NumUsedGPRs);
-  RAPass->AddRegisters(FEXCore::IR::GPRFixedClass, SRA64.size());
-  RAPass->AddRegisters(FEXCore::IR::FPRClass, NumFPRs);
-  RAPass->AddRegisters(FEXCore::IR::FPRFixedClass, SRAFPR.size()  );
-  RAPass->AddRegisters(FEXCore::IR::GPRPairClass, NumUsedGPRPairs);
+  RAPass->AddRegisters(FEXCore::IR::GPRClass, GeneralRegisters.size());
+  RAPass->AddRegisters(FEXCore::IR::GPRFixedClass, StaticRegisters.size());
+  RAPass->AddRegisters(FEXCore::IR::FPRClass, GeneralFPRegisters.size());
+  RAPass->AddRegisters(FEXCore::IR::FPRFixedClass, StaticFPRegisters.size());
+  RAPass->AddRegisters(FEXCore::IR::GPRPairClass, GeneralPairRegisters.size());
   RAPass->AddRegisters(FEXCore::IR::ComplexClass, 1);
 
-  for (uint32_t i = 0; i < NumUsedGPRPairs; ++i) {
+  for (uint32_t i = 0; i < GeneralPairRegisters.size(); ++i) {
     RAPass->AddRegisterConflict(FEXCore::IR::GPRClass, i * 2,     FEXCore::IR::GPRPairClass, i);
     RAPass->AddRegisterConflict(FEXCore::IR::GPRClass, i * 2 + 1, FEXCore::IR::GPRPairClass, i);
   }
@@ -551,6 +612,11 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::In
       Common.CPUIDFunction = PMF.GetConvertedPointer();
     }
 
+    {
+      FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunXCRFunction);
+      Common.XCRFunction = PMF.GetConvertedPointer();
+    }
+
     Common.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
     Common.SyscallHandlerFunc = reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall);
     Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadExitFunctionLink<Arm64JITCore_ExitFunctionLink>);
@@ -570,23 +636,25 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::In
 
   // Must be done after Dispatcher init
   ClearCache();
-}
 
-void Arm64JITCore::InitializeSignalHandlers(FEXCore::Context::ContextImpl *CTX) {
-  CTX->SignalDelegation->RegisterHostSignalHandler(SIGILL, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-    return reinterpret_cast<Context::ContextImpl*>(Thread->CTX)->Dispatcher->HandleSIGILL(Thread, Signal, info, ucontext);
-  }, true);
+  // Setup dynamic dispatch.
+  if (CTX->Dispatcher->GetConfig().StaticRegisterAllocation) {
+    RT_LoadRegister = &Arm64JITCore::Op_LoadRegisterSRA;
+    RT_StoreRegister = &Arm64JITCore::Op_StoreRegisterSRA;
+  }
+  else {
+    RT_LoadRegister = &Arm64JITCore::Op_LoadRegister;
+    RT_StoreRegister = &Arm64JITCore::Op_StoreRegister;
+  }
 
-#ifdef _M_ARM_64
-  CTX->SignalDelegation->RegisterHostSignalHandler(SIGBUS, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-    if (!Thread->CPUBackend->IsAddressInCodeBuffer(ArchHelpers::Context::GetPc(ucontext))) {
-      // Wasn't a sigbus in JIT code
-      return false;
-    }
-
-    return FEXCore::ArchHelpers::Arm64::HandleSIGBUS(static_cast<Context::ContextImpl*>(Thread->CTX)->Config.ParanoidTSO(), Signal, info, ucontext);
-  }, true);
-#endif
+  if (ParanoidTSO()) {
+    RT_LoadMemTSO = &Arm64JITCore::Op_ParanoidLoadMemTSO;
+    RT_StoreMemTSO = &Arm64JITCore::Op_ParanoidStoreMemTSO;
+  }
+  else {
+    RT_LoadMemTSO = &Arm64JITCore::Op_LoadMemTSO;
+    RT_StoreMemTSO = &Arm64JITCore::Op_StoreMemTSO;
+  }
 }
 
 void Arm64JITCore::EmitDetectionString() {
@@ -656,6 +724,12 @@ bool Arm64JITCore::IsGPR(IR::NodeID Node) const {
   return Class == IR::GPRClass || Class == IR::GPRFixedClass;
 }
 
+bool Arm64JITCore::IsGPRPair(IR::NodeID Node) const {
+  auto Class = GetRegClass(Node);
+
+  return Class == IR::GPRPairClass;
+}
+
 CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
                                 FEXCore::IR::IRListView const *IR,
                                 FEXCore::Core::DebugData *DebugData,
@@ -767,6 +841,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
     for (auto [CodeNode, IROp] : IR->GetCode(BlockNode)) {
       const auto ID = IR->GetID(CodeNode);
       switch (IROp->Op) {
+#define REGISTER_OP_RT(op, x) case FEXCore::IR::IROps::OP_##op: std::invoke(RT_##x, this, IROp, ID); break
 #define REGISTER_OP(op, x) case FEXCore::IR::IROps::OP_##op: Op_##x(IROp, ID); break
         // ALU ops
         REGISTER_OP(TRUNCELEMENTPAIR,  TruncElementPair);
@@ -776,8 +851,10 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
         REGISTER_OP(INLINEENTRYPOINTOFFSET,  InlineEntrypointOffset);
         REGISTER_OP(CYCLECOUNTER,      CycleCounter);
         REGISTER_OP(ADD,               Add);
+        REGISTER_OP(TESTNZ,            TestNZ);
         REGISTER_OP(SUB,               Sub);
         REGISTER_OP(NEG,               Neg);
+        REGISTER_OP(ABS,               Abs);
         REGISTER_OP(MUL,               Mul);
         REGISTER_OP(UMUL,              UMul);
         REGISTER_OP(DIV,               Div);
@@ -787,6 +864,8 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
         REGISTER_OP(MULH,              MulH);
         REGISTER_OP(UMULH,             UMulH);
         REGISTER_OP(OR,                Or);
+        REGISTER_OP(ORLSHL,            Orlshl);
+        REGISTER_OP(ORLSHR,            Orlshr);
         REGISTER_OP(AND,               And);
         REGISTER_OP(ANDN,              Andn);
         REGISTER_OP(XOR,               Xor);
@@ -844,6 +923,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
         REGISTER_OP(VALIDATECODE,      ValidateCode);
         REGISTER_OP(THREADREMOVECODEENTRY,   ThreadRemoveCodeEntry);
         REGISTER_OP(CPUID,             CPUID);
+        REGISTER_OP(XGETBV,            XGETBV);
 
         // Conversion ops
         REGISTER_OP(VINSGPR,         VInsGPR);
@@ -873,8 +953,8 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
         // Memory ops
         REGISTER_OP(LOADCONTEXT,         LoadContext);
         REGISTER_OP(STORECONTEXT,        StoreContext);
-        REGISTER_OP(LOADREGISTER,        LoadRegister);
-        REGISTER_OP(STOREREGISTER,       StoreRegister);
+        REGISTER_OP_RT(LOADREGISTER,     LoadRegister);
+        REGISTER_OP_RT(STOREREGISTER,    StoreRegister);
         REGISTER_OP(LOADCONTEXTINDEXED,  LoadContextIndexed);
         REGISTER_OP(STORECONTEXTINDEXED, StoreContextIndexed);
         REGISTER_OP(SPILLREGISTER,       SpillRegister);
@@ -883,24 +963,13 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
         REGISTER_OP(STOREFLAG,           StoreFlag);
         REGISTER_OP(LOADMEM,             LoadMem);
         REGISTER_OP(STOREMEM,            StoreMem);
-        case FEXCore::IR::IROps::OP_LOADMEMTSO:
-          if (ParanoidTSO()) {
-            Op_ParanoidLoadMemTSO(IROp, ID);
-          }
-          else {
-            Op_LoadMemTSO(IROp, ID);
-          }
-          break;
-        case FEXCore::IR::IROps::OP_STOREMEMTSO:
-          if (ParanoidTSO()) {
-            Op_ParanoidStoreMemTSO(IROp, ID);
-          }
-          else {
-            Op_StoreMemTSO(IROp, ID);
-          }
-          break;
+        REGISTER_OP_RT(LOADMEMTSO,       LoadMemTSO);
+        REGISTER_OP_RT(STOREMEMTSO,      StoreMemTSO);
+        REGISTER_OP(VLOADVECTORMASKED,   VLoadVectorMasked);
+        REGISTER_OP(VSTOREVECTORMASKED,  VStoreVectorMasked);
 
         REGISTER_OP(MEMSET,              MemSet);
+        REGISTER_OP(MEMCPY,              MemCpy);
         REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
         REGISTER_OP(CACHELINECLEAN,      CacheLineClean);
         REGISTER_OP(CACHELINEZERO,       CacheLineZero);
@@ -1013,6 +1082,7 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
         REGISTER_OP(VUMULL2,           VUMull2);
         REGISTER_OP(VSMULL2,           VSMull2);
         REGISTER_OP(VUABDL,            VUABDL);
+        REGISTER_OP(VUABDL2,           VUABDL2);
         REGISTER_OP(VTBL1,             VTBL1);
         REGISTER_OP(VREV64,            VRev64);
 #undef REGISTER_OP
@@ -1038,28 +1108,54 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry,
   }
   PendingTargetLabel = nullptr;
 
+  // CodeSize not including the tail data.
+  const uint64_t CodeOnlySize = GetCursorAddress<uint8_t *>() - CodeData.BlockBegin;
+
   // Add the JitCodeTail
   auto JITBlockTailLocation = GetCursorAddress<uint8_t *>();
   auto JITBlockTail = GetCursorAddress<JITCodeTail*>();
   CursorIncrement(sizeof(JITCodeTail));
 
+  auto JITRIPEntriesLocation = GetCursorAddress<uint8_t *>();
+  auto JITRIPEntries = GetCursorAddress<JITRIPReconstructEntries*>();
+
+  CursorIncrement(sizeof(JITRIPReconstructEntries) * DebugData->GuestOpcodes.size());
+
   // Put the block's RIP entry in the tail.
   // This will be used for RIP reconstruction in the future.
   // TODO: This needs to be a data RIP relocation once code caching works.
   //   Current relocation code doesn't support this feature yet.
   JITBlockTail->RIP = Entry;
 
+  {
+    // Store the RIP entries.
+    JITBlockTail->NumberOfRIPEntries = DebugData->GuestOpcodes.size();
+    JITBlockTail->OffsetToRIPEntries = JITRIPEntriesLocation - JITBlockTailLocation;
+    uintptr_t CurrentRIPOffset = 0;
+    uint64_t CurrentPCOffset = 0;
+    for (size_t i = 0; i < DebugData->GuestOpcodes.size(); i++) {
+      const auto &GuestOpcode = DebugData->GuestOpcodes[i];
+      auto &RIPEntry = JITRIPEntries[i];
+      RIPEntry.HostPCOffset = GuestOpcode.HostEntryOffset - CurrentPCOffset;
+      RIPEntry.GuestRIPOffset = GuestOpcode.GuestEntryOffset - CurrentRIPOffset;
+      CurrentPCOffset = GuestOpcode.HostEntryOffset;
+      CurrentRIPOffset = GuestOpcode.GuestEntryOffset;
+    }
+  }
+
   CodeHeader->OffsetToBlockTail = JITBlockTailLocation - CodeData.BlockBegin;
 
   CodeData.Size = GetCursorAddress<uint8_t *>() - CodeData.BlockBegin;
 
   JITBlockTail->Size = CodeData.Size;
 
-  ClearICache(CodeData.BlockBegin, CodeData.Size);
+  ClearICache(CodeData.BlockBegin, CodeOnlySize);
 
 #ifdef VIXL_DISASSEMBLER
-  const auto DisasmEnd = GetCursorAddress<const vixl::aarch64::Instruction*>();
-  Disasm.DisassembleBuffer(DisasmBegin, DisasmEnd);
+  if (Disassemble() & FEXCore::Config::Disassemble::BLOCKS) {
+    const auto DisasmEnd = reinterpret_cast<const vixl::aarch64::Instruction*>(JITBlockTailLocation);
+    Disasm.DisassembleBuffer(DisasmBegin, DisasmEnd);
+  }
 #endif
 
   if (DebugData) {
@@ -1088,17 +1184,15 @@ void Arm64JITCore::ResetStack() {
   }
 }
 
-std::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  return std::make_unique<Arm64JITCore>(ctx, Thread);
-}
-
-void InitializeArm64JITSignalHandlers(FEXCore::Context::ContextImpl *CTX) {
-  Arm64JITCore::InitializeSignalHandlers(CTX);
+fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  return fextl::make_unique<Arm64JITCore>(ctx, Thread);
 }
 
 CPUBackendFeatures GetArm64JITBackendFeatures() {
   return CPUBackendFeatures {
-    .SupportsStaticRegisterAllocation = true
+    .SupportsStaticRegisterAllocation = true,
+    .SupportsShiftedBitwise = true,
+    .SupportsFlags = true,
   };
 }
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h

@@ -6,7 +6,6 @@ $end_info$
 
 #pragma once
 
-#include <FEXCore/IR/RegisterAllocationData.h>
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
 #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
@@ -14,15 +13,18 @@ $end_info$
 #include <aarch64/assembler-aarch64.h>
 #include <aarch64/disasm-aarch64.h>
 
+#include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
+#include <FEXCore/IR/RegisterAllocationData.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/vector.h>
 
 #include <array>
 #include <cstdint>
-#include <map>
 #include <utility>
-#include <vector>
 
 namespace FEXCore::Core {
   struct InternalThreadState;
@@ -35,7 +37,7 @@ public:
                         FEXCore::Core::InternalThreadState *Thread);
   ~Arm64JITCore() override;
 
-  [[nodiscard]] std::string GetName() override { return "JIT"; }
+  [[nodiscard]] fextl::string GetName() override { return "JIT"; }
 
   [[nodiscard]] CPUBackend::CompiledCode CompileCode(uint64_t Entry,
                                   FEXCore::IR::IRListView const *IR,
@@ -48,8 +50,6 @@ public:
 
   void ClearCache() override;
 
-  static void InitializeSignalHandlers(FEXCore::Context::ContextImpl *CTX);
-
   void ClearRelocations() override { Relocations.clear(); }
 
 private:
@@ -62,28 +62,7 @@ private:
   uint64_t Entry;
   CPUBackend::CompiledCode CodeData{};
 
-  std::map<IR::NodeID, ARMEmitter::BiDirectionalLabel> JumpTargets;
-
-  /**
-   * @name Register Allocation
-   * @{ */
-  constexpr static uint32_t NumGPRs = RA64.size();
-  constexpr static uint32_t NumFPRs = RAFPR.size();
-  constexpr static uint32_t NumGPRPairs = RA64Pair.size();
-  constexpr static uint32_t NumCalleeGPRs = 10;
-  constexpr static uint32_t NumCalleeGPRPairs = 5;
-  constexpr static uint32_t RegisterCount = NumGPRs + NumFPRs + NumGPRPairs;
-  constexpr static uint32_t RegisterClasses = 6;
-
-  constexpr static uint64_t GPRBase = (0ULL << 32);
-  constexpr static uint64_t FPRBase = (1ULL << 32);
-  constexpr static uint64_t GPRPairBase = (2ULL << 32);
-
-  /**  @} */
-
-  constexpr static uint8_t RA_32 = 0;
-  constexpr static uint8_t RA_64 = 1;
-  constexpr static uint8_t RA_FPR = 2;
+  fextl::map<IR::NodeID, ARMEmitter::BiDirectionalLabel> JumpTargets;
 
   [[nodiscard]] FEXCore::ARMEmitter::Register GetReg(IR::NodeID Node) const {
     const auto Reg = GetPhys(Node);
@@ -91,9 +70,9 @@ private:
     LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRFixedClass.Val || Reg.Class == IR::GPRClass.Val, "Unexpected Class: {}", Reg.Class);
 
     if (Reg.Class == IR::GPRFixedClass.Val) {
-      return SRA64[Reg.Reg];
+      return StaticRegisters[Reg.Reg];
     } else if (Reg.Class == IR::GPRClass.Val) {
-      return RA64[Reg.Reg];
+      return GeneralRegisters[Reg.Reg];
     }
 
     FEX_UNREACHABLE;
@@ -105,9 +84,9 @@ private:
     LOGMAN_THROW_AA_FMT(Reg.Class == IR::FPRFixedClass.Val || Reg.Class == IR::FPRClass.Val, "Unexpected Class: {}", Reg.Class);
 
     if (Reg.Class == IR::FPRFixedClass.Val) {
-      return SRAFPR[Reg.Reg];
+      return StaticFPRegisters[Reg.Reg];
     } else if (Reg.Class == IR::FPRClass.Val) {
-      return RAFPR[Reg.Reg];
+      return GeneralFPRegisters[Reg.Reg];
     }
 
     FEX_UNREACHABLE;
@@ -118,7 +97,7 @@ private:
 
     LOGMAN_THROW_AA_FMT(Reg.Class == IR::GPRPairClass.Val, "Unexpected Class: {}", Reg.Class);
 
-    return RA64Pair[Reg.Reg];
+    return GeneralPairRegisters[Reg.Reg];
   }
 
   [[nodiscard]] FEXCore::IR::RegisterClassType GetRegClass(IR::NodeID Node) const;
@@ -133,6 +112,7 @@ private:
 
   [[nodiscard]] bool IsFPR(IR::NodeID Node) const;
   [[nodiscard]] bool IsGPR(IR::NodeID Node) const;
+  [[nodiscard]] bool IsGPRPair(IR::NodeID Node) const;
 
   [[nodiscard]] FEXCore::ARMEmitter::ExtendedMemOperand GenerateMemOperand(uint8_t AccessSize,
                                               FEXCore::ARMEmitter::Register Base,
@@ -223,7 +203,7 @@ private:
      */
     void PlaceNamedSymbolLiteral(NamedSymbolLiteralPair &Lit);
 
-    std::vector<FEXCore::CPU::Relocation> Relocations;
+    fextl::vector<FEXCore::CPU::Relocation> Relocations;
 
     ///< Relocation code loading
     bool ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uint64_t CursorEntry, size_t NumRelocations, const char* EntryRelocations);
@@ -231,6 +211,16 @@ private:
   /**  @} */
 
   uint32_t SpillSlots{};
+  using OpType = void (Arm64JITCore::*)(IR::IROp_Header const *IROp, IR::NodeID Node);
+
+  // Runtime selection;
+  // Load and store register style.
+  OpType RT_LoadRegister;
+  OpType RT_StoreRegister;
+  // Load and store TSO memory style
+  OpType RT_LoadMemTSO;
+  OpType RT_StoreMemTSO;
+
 #define DEF_OP(x) void Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
 
   ///< Unhandled handler
@@ -247,8 +237,10 @@ private:
   DEF_OP(InlineEntrypointOffset);
   DEF_OP(CycleCounter);
   DEF_OP(Add);
+  DEF_OP(TestNZ);
   DEF_OP(Sub);
   DEF_OP(Neg);
+  DEF_OP(Abs);
   DEF_OP(Mul);
   DEF_OP(UMul);
   DEF_OP(Div);
@@ -258,6 +250,8 @@ private:
   DEF_OP(MulH);
   DEF_OP(UMulH);
   DEF_OP(Or);
+  DEF_OP(Orlshl);
+  DEF_OP(Orlshr);
   DEF_OP(And);
   DEF_OP(Andn);
   DEF_OP(Xor);
@@ -318,6 +312,7 @@ private:
   DEF_OP(ValidateCode);
   DEF_OP(ThreadRemoveCodeEntry);
   DEF_OP(CPUID);
+  DEF_OP(XGETBV);
 
   ///< Conversion ops
   DEF_OP(VInsGPR);
@@ -339,6 +334,8 @@ private:
   DEF_OP(StoreContext);
   DEF_OP(LoadRegister);
   DEF_OP(StoreRegister);
+  DEF_OP(LoadRegisterSRA);
+  DEF_OP(StoreRegisterSRA);
   DEF_OP(LoadContextIndexed);
   DEF_OP(StoreContextIndexed);
   DEF_OP(SpillRegister);
@@ -349,7 +346,10 @@ private:
   DEF_OP(StoreMem);
   DEF_OP(LoadMemTSO);
   DEF_OP(StoreMemTSO);
+  DEF_OP(VLoadVectorMasked);
+  DEF_OP(VStoreVectorMasked);
   DEF_OP(MemSet);
+  DEF_OP(MemCpy);
   DEF_OP(ParanoidLoadMemTSO);
   DEF_OP(ParanoidStoreMemTSO);
   DEF_OP(CacheLineClear);
@@ -457,6 +457,7 @@ private:
   DEF_OP(VUMull2);
   DEF_OP(VSMull2);
   DEF_OP(VUABDL);
+  DEF_OP(VUABDL2);
   DEF_OP(VTBL1);
   DEF_OP(VRev64);
 

External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp

@@ -10,6 +10,7 @@ $end_info$
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include <FEXCore/Utils/CompilerDefs.h>
+#include <FEXCore/Utils/MathUtils.h>
 
 namespace FEXCore::CPU {
 #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
@@ -128,13 +129,177 @@ DEF_OP(LoadRegister) {
   const auto Op = IROp->C<IR::IROp_LoadRegister>();
   const auto OpSize = IROp->Size;
 
+  if (Op->Class == IR::GPRClass) {
+    [[maybe_unused]] const auto regId = (Op->Offset / Core::CPUState::GPR_REG_SIZE) - 1;
+    const auto regOffs = Op->Offset & 7;
+
+    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "out of range regId");
+
+    switch (OpSize) {
+      case 1:
+        LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        ldrb(GetReg(Node), STATE, Op->Offset);
+        break;
+
+      case 2:
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
+        ldrh(GetReg(Node), STATE, Op->Offset);
+        break;
+
+      case 4:
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
+        ldr(GetReg(Node).W(), STATE, Op->Offset);
+        break;
+
+      case 8:
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
+        ldr(GetReg(Node).X(), STATE, Op->Offset);
+        break;
+
+      default:
+        LOGMAN_MSG_A_FMT("Unhandled LoadRegister GPR size: {}", OpSize);
+        break;
+    }
+  }
+  else if (Op->Class == IR::FPRClass) {
+    const auto regSize = HostSupportsSVE ? Core::CPUState::XMM_AVX_REG_SIZE
+                                         : Core::CPUState::XMM_SSE_REG_SIZE;
+    [[maybe_unused]] const auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.xmm.avx.data[0][0])) / regSize;
+
+    LOGMAN_THROW_A_FMT(HostSupportsSVE, "Unsupported code path!");
+    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "out of range regId");
+
+    const auto host = GetVReg(Node);
+
+    const auto regOffs = Op->Offset & 15;
+
+    switch (OpSize) {
+      case 1: {
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs: {}", regOffs);
+        ldrb(host, STATE, Op->Offset);
+        break;
+      }
+      case 2: {
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs: {}", regOffs);
+        ldrh(host, STATE, Op->Offset);
+        break;
+      }
+      case 4: {
+        LOGMAN_THROW_AA_FMT((regOffs & 3) == 0, "unexpected regOffs: {}", regOffs);
+        ldr(host.S(), STATE, Op->Offset);
+        break;
+      }
+
+      case 8: {
+        LOGMAN_THROW_AA_FMT((regOffs & 7) == 0, "unexpected regOffs: {}", regOffs);
+        ldr(host.D(), STATE, Op->Offset);
+        break;
+      }
+
+      case 16: {
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs: {}", regOffs);
+        ldr(host.Q(), STATE, Op->Offset);
+        break;
+      }
+    }
+  } else {
+    LOGMAN_THROW_AA_FMT(false, "Unhandled Op->Class {}", Op->Class);
+  }
+}
+
+DEF_OP(StoreRegister) {
+  const auto Op = IROp->C<IR::IROp_StoreRegister>();
+  const auto OpSize = IROp->Size;
+
+  if (Op->Class == IR::GPRClass) {
+    [[maybe_unused]] const auto regId = (Op->Offset / Core::CPUState::GPR_REG_SIZE) - 1;
+    const auto regOffs = Op->Offset & 7;
+
+    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "out of range regId");
+
+    const auto Src = GetReg(Op->Value.ID());
+
+    switch (OpSize) {
+      case 1:
+        LOGMAN_THROW_AA_FMT(regOffs == 0 || regOffs == 1, "unexpected regOffs");
+        strb(Src, STATE, Op->Offset);
+        break;
+
+      case 2:
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
+        strh(Src, STATE, Op->Offset);
+        break;
+
+      case 4:
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
+        str(Src.W(), STATE, Op->Offset);
+        break;
+      case 8:
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs");
+        str(Src.X(), STATE, Op->Offset);
+        break;
+
+      default:
+        LOGMAN_MSG_A_FMT("Unhandled StoreRegister GPR size: {}", OpSize);
+        break;
+    }
+  } else if (Op->Class == IR::FPRClass) {
+    const auto regSize = HostSupportsSVE ? Core::CPUState::XMM_AVX_REG_SIZE
+                                         : Core::CPUState::XMM_SSE_REG_SIZE;
+    [[maybe_unused]] const auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.xmm.avx.data[0][0])) / regSize;
+
+    LOGMAN_THROW_A_FMT(HostSupportsSVE, "Unsupported code path!");
+    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "regId out of range");
+
+    const auto host = GetVReg(Op->Value.ID());
+
+    const auto regOffs = Op->Offset & 15;
+
+    switch (OpSize) {
+      case 1:
+        strb(host, STATE, Op->Offset);
+        break;
+
+      case 2:
+        LOGMAN_THROW_AA_FMT((regOffs & 1) == 0, "unexpected regOffs: {}", regOffs);
+        strh(host, STATE, Op->Offset);
+        break;
+
+      case 4:
+        LOGMAN_THROW_AA_FMT((regOffs & 3) == 0, "unexpected regOffs: {}", regOffs);
+        str(host.S(), STATE, Op->Offset);
+        break;
+
+      case 8:
+        LOGMAN_THROW_AA_FMT((regOffs & 7) == 0, "unexpected regOffs: {}", regOffs);
+        str(host.D(), STATE, Op->Offset);
+        break;
+
+      case 16:
+        LOGMAN_THROW_AA_FMT(regOffs == 0, "unexpected regOffs: {}", regOffs);
+        str(host.Q(), STATE, Op->Offset);
+        break;
+
+      default:
+        LOGMAN_MSG_A_FMT("Unhandled StoreRegister FPR size: {}", OpSize);
+        break;
+    }
+  } else {
+    LOGMAN_THROW_AA_FMT(false, "Unhandled Op->Class {}", Op->Class);
+  }
+}
+
+DEF_OP(LoadRegisterSRA) {
+  const auto Op = IROp->C<IR::IROp_LoadRegister>();
+  const auto OpSize = IROp->Size;
+
   if (Op->Class == IR::GPRClass) {
     const auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.gregs[0])) / Core::CPUState::GPR_REG_SIZE;
     const auto regOffs = Op->Offset & 7;
 
-    LOGMAN_THROW_A_FMT(regId < SRA64.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "out of range regId");
 
-    const auto reg = SRA64[regId];
+    const auto reg = StaticRegisters[regId];
 
     switch (OpSize) {
       case 1:
@@ -170,9 +335,9 @@ DEF_OP(LoadRegister) {
                                          : Core::CPUState::XMM_SSE_REG_SIZE;
     const auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.xmm.avx.data[0][0])) / regSize;
 
-    LOGMAN_THROW_A_FMT(regId < SRAFPR.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "out of range regId");
 
-    const auto guest = SRAFPR[regId];
+    const auto guest = StaticFPRegisters[regId];
     const auto host = GetVReg(Node);
 
     if (HostSupportsSVE) {
@@ -312,7 +477,7 @@ DEF_OP(LoadRegister) {
   }
 }
 
-DEF_OP(StoreRegister) {
+DEF_OP(StoreRegisterSRA) {
   const auto Op = IROp->C<IR::IROp_StoreRegister>();
   const auto OpSize = IROp->Size;
 
@@ -320,9 +485,9 @@ DEF_OP(StoreRegister) {
     const auto regId = (Op->Offset / Core::CPUState::GPR_REG_SIZE) - 1;
     const auto regOffs = Op->Offset & 7;
 
-    LOGMAN_THROW_A_FMT(regId < SRA64.size(), "out of range regId");
+    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "out of range regId");
 
-    const auto reg = SRA64[regId];
+    const auto reg = StaticRegisters[regId];
     const auto Src = GetReg(Op->Value.ID());
 
     switch (OpSize) {
@@ -356,9 +521,9 @@ DEF_OP(StoreRegister) {
                                          : Core::CPUState::XMM_SSE_REG_SIZE;
     const auto regId = (Op->Offset - offsetof(Core::CpuStateFrame, State.xmm.avx.data[0][0])) / regSize;
 
-    LOGMAN_THROW_A_FMT(regId < SRAFPR.size(), "regId out of range");
+    LOGMAN_THROW_A_FMT(regId < StaticFPRegisters.size(), "regId out of range");
 
-    const auto guest = SRAFPR[regId];
+    const auto guest = StaticFPRegisters[regId];
     const auto host = GetVReg(Op->Value.ID());
 
     if (HostSupportsSVE) {
@@ -500,7 +665,6 @@ DEF_OP(StoreRegister) {
   }
 }
 
-
 DEF_OP(LoadContextIndexed) {
   const auto Op = IROp->C<IR::IROp_LoadContextIndexed>();
   const auto OpSize = IROp->Size;
@@ -513,10 +677,7 @@ DEF_OP(LoadContextIndexed) {
     case 2:
     case 4:
     case 8: {
-      LoadConstant(ARMEmitter::Size::i64Bit, TMP1, Op->Stride);
-      mul(ARMEmitter::Size::i64Bit, TMP1, Index, TMP1);
-      add(ARMEmitter::Size::i64Bit, TMP1, STATE, TMP1.R());
-
+      add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, FEXCore::ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride));
       const auto Dst = GetReg(Node);
       switch (OpSize) {
       case 1:
@@ -553,10 +714,7 @@ DEF_OP(LoadContextIndexed) {
     case 8:
     case 16:
     case 32: {
-      LoadConstant(ARMEmitter::Size::i64Bit, TMP1, Op->Stride);
-      mul(ARMEmitter::Size::i64Bit, TMP1, Index, TMP1);
-      add(ARMEmitter::Size::i64Bit, TMP1, STATE, TMP1.R());
-
+      add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, FEXCore::ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride));
       const auto Dst = GetVReg(Node);
 
       switch (OpSize) {
@@ -611,9 +769,7 @@ DEF_OP(StoreContextIndexed) {
     case 2:
     case 4:
     case 8: {
-      LoadConstant(ARMEmitter::Size::i64Bit, TMP1, Op->Stride);
-      mul(ARMEmitter::Size::i64Bit, TMP1, Index, TMP1);
-      add(ARMEmitter::Size::i64Bit, TMP1, STATE, TMP1.R());
+      add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, FEXCore::ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride));
 
       switch (OpSize) {
       case 1:
@@ -652,9 +808,7 @@ DEF_OP(StoreContextIndexed) {
     case 8:
     case 16:
     case 32: {
-      LoadConstant(ARMEmitter::Size::i64Bit, TMP1, Op->Stride);
-      mul(ARMEmitter::Size::i64Bit, TMP1, Index, TMP1);
-      add(ARMEmitter::Size::i64Bit, TMP1, STATE, TMP1.R());
+      add(ARMEmitter::Size::i64Bit, TMP1, STATE, Index, FEXCore::ARMEmitter::ShiftType::LSL, FEXCore::ilog2(Op->Stride));
 
       switch (OpSize) {
       case 1:
@@ -897,12 +1051,20 @@ DEF_OP(FillRegister) {
 DEF_OP(LoadFlag) {
   auto Op = IROp->C<IR::IROp_LoadFlag>();
   auto Dst = GetReg(Node);
-  ldrb(Dst, STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag);
+
+  if (Op->Flag == 24 /* NZCV */)
+    ldr(Dst.W(), STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag);
+  else
+    ldrb(Dst, STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag);
 }
 
 DEF_OP(StoreFlag) {
   auto Op = IROp->C<IR::IROp_StoreFlag>();
-  strb(GetReg(Op->Value.ID()), STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag);
+
+  if (Op->Flag == 24 /* NZCV */)
+    str(GetReg(Op->Value.ID()).W(), STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag);
+  else
+    strb(GetReg(Op->Value.ID()), STATE, offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag);
 }
 
 FEXCore::ARMEmitter::ExtendedMemOperand Arm64JITCore::GenerateMemOperand(uint8_t AccessSize,
@@ -922,9 +1084,9 @@ FEXCore::ARMEmitter::ExtendedMemOperand Arm64JITCore::GenerateMemOperand(uint8_t
     } else {
       auto RegOffset = GetReg(Offset.ID());
       switch(OffsetType.Val) {
-        case IR::MEM_OFFSET_SXTX.Val: return ARMEmitter::ExtendedMemOperand(Base.X(), RegOffset.X(), ARMEmitter::ExtendedType::SXTX, (int)std::log2(OffsetScale) );
-        case IR::MEM_OFFSET_UXTW.Val: return ARMEmitter::ExtendedMemOperand(Base.X(), RegOffset.X(), ARMEmitter::ExtendedType::UXTW, (int)std::log2(OffsetScale) );
-        case IR::MEM_OFFSET_SXTW.Val: return ARMEmitter::ExtendedMemOperand(Base.X(), RegOffset.X(), ARMEmitter::ExtendedType::SXTW, (int)std::log2(OffsetScale) );
+        case IR::MEM_OFFSET_SXTX.Val: return ARMEmitter::ExtendedMemOperand(Base.X(), RegOffset.X(), ARMEmitter::ExtendedType::SXTX, FEXCore::ilog2(OffsetScale) );
+        case IR::MEM_OFFSET_UXTW.Val: return ARMEmitter::ExtendedMemOperand(Base.X(), RegOffset.X(), ARMEmitter::ExtendedType::UXTW, FEXCore::ilog2(OffsetScale) );
+        case IR::MEM_OFFSET_SXTW.Val: return ARMEmitter::ExtendedMemOperand(Base.X(), RegOffset.X(), ARMEmitter::ExtendedType::SXTW, FEXCore::ilog2(OffsetScale) );
         default: LOGMAN_MSG_A_FMT("Unhandled GenerateMemOperand OffsetType: {}", OffsetType.Val); break;
       }
     }
@@ -1077,8 +1239,6 @@ DEF_OP(LoadMemTSO) {
       ldapurb(Dst, MemReg, Offset);
     }
     else {
-      // Aligned
-      nop();
       switch (OpSize) {
         case 2:
           ldapurh(Dst, MemReg, Offset);
@@ -1093,19 +1253,17 @@ DEF_OP(LoadMemTSO) {
           LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", OpSize);
           break;
       }
+      // Half-barrier once back-patched.
       nop();
     }
   }
   else if (CTX->HostFeatures.SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
-
     const auto Dst = GetReg(Node);
     if (OpSize == 1) {
       // 8bit load is always aligned to natural alignment
       ldaprb(Dst.W(), MemReg);
     }
     else {
-      // Aligned
-      nop();
       switch (OpSize) {
         case 2:
           ldaprh(Dst.W(), MemReg);
@@ -1120,6 +1278,7 @@ DEF_OP(LoadMemTSO) {
           LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", OpSize);
           break;
       }
+      // Half-barrier once back-patched.
       nop();
     }
   }
@@ -1130,8 +1289,6 @@ DEF_OP(LoadMemTSO) {
       ldarb(Dst, MemReg);
     }
     else {
-      // Aligned
-      nop();
       switch (OpSize) {
         case 2:
           ldarh(Dst, MemReg);
@@ -1146,11 +1303,11 @@ DEF_OP(LoadMemTSO) {
           LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", OpSize);
           break;
       }
+      // Half-barrier once back-patched.
       nop();
     }
   }
   else {
-    dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
     const auto Dst = GetVReg(Node);
     const auto MemSrc = GenerateMemOperand(OpSize, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
     switch (OpSize) {
@@ -1178,7 +1335,108 @@ DEF_OP(LoadMemTSO) {
         LOGMAN_MSG_A_FMT("Unhandled LoadMemTSO size: {}", OpSize);
         break;
     }
-    dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
+    // Half-barrier.
+    dmb(FEXCore::ARMEmitter::BarrierScope::ISHLD);
+  }
+}
+
+DEF_OP(VLoadVectorMasked) {
+  LOGMAN_THROW_A_FMT(HostSupportsSVE, "Need SVE support in order to use VLoadVectorMasked");
+
+  const auto Op = IROp->C<IR::IROp_VLoadVectorMasked>();
+  const auto OpSize = IROp->Size;
+
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto ElementSize = IROp->ElementSize;
+
+  const auto CMPPredicate = ARMEmitter::PReg::p0;
+  const auto GoverningPredicate = Is256Bit ? PRED_TMP_32B : PRED_TMP_16B;
+
+  const auto Dst = GetVReg(Node);
+  const auto MaskReg = GetVReg(Op->Mask.ID());
+  const auto MemReg = GetReg(Op->Addr.ID());
+  const auto MemSrc = GenerateSVEMemOperand(OpSize, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
+
+  LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8, "Invalid size");
+  const auto SubRegSize =
+    ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i8Bit;
+
+  // Check if the sign bit is set for the given element size.
+  cmplt(SubRegSize, CMPPredicate, GoverningPredicate.Zeroing(), MaskReg.Z(), 0);
+
+  switch (ElementSize) {
+    case 1: {
+      ld1b<ARMEmitter::SubRegSize::i8Bit>(Dst.Z(), CMPPredicate.Zeroing(), MemSrc);
+      break;
+    }
+    case 2: {
+      ld1h<ARMEmitter::SubRegSize::i16Bit>(Dst.Z(), CMPPredicate.Zeroing(), MemSrc);
+      break;
+    }
+    case 4: {
+      ld1w<ARMEmitter::SubRegSize::i32Bit>(Dst.Z(), CMPPredicate.Zeroing(), MemSrc);
+      break;
+    }
+    case 8: {
+      ld1d(Dst.Z(), CMPPredicate.Zeroing(), MemSrc);
+      break;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled VLoadVectorMasked size: {}", ElementSize);
+      break;
+  }
+}
+
+DEF_OP(VStoreVectorMasked) {
+  LOGMAN_THROW_A_FMT(HostSupportsSVE, "Need SVE support in order to use VStoreVectorMasked");
+
+  const auto Op = IROp->C<IR::IROp_VStoreVectorMasked>();
+  const auto OpSize = IROp->Size;
+
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto ElementSize = IROp->ElementSize;
+
+  const auto CMPPredicate = ARMEmitter::PReg::p0;
+  const auto GoverningPredicate = Is256Bit ? PRED_TMP_32B : PRED_TMP_16B;
+
+  const auto RegData = GetVReg(Op->Data.ID());
+  const auto MaskReg = GetVReg(Op->Mask.ID());
+  const auto MemReg = GetReg(Op->Addr.ID());
+  const auto MemDst = GenerateSVEMemOperand(OpSize, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
+
+  LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8, "Invalid size");
+  const auto SubRegSize =
+    ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i8Bit;
+
+  // Check if the sign bit is set for the given element size.
+  cmplt(SubRegSize, CMPPredicate, GoverningPredicate.Zeroing(), MaskReg.Z(), 0);
+
+  switch (ElementSize) {
+    case 1: {
+      st1b<ARMEmitter::SubRegSize::i8Bit>(RegData.Z(), CMPPredicate.Zeroing(), MemDst);
+      break;
+    }
+    case 2: {
+      st1h<ARMEmitter::SubRegSize::i16Bit>(RegData.Z(), CMPPredicate.Zeroing(), MemDst);
+      break;
+    }
+    case 4: {
+      st1w<ARMEmitter::SubRegSize::i32Bit>(RegData.Z(), CMPPredicate.Zeroing(), MemDst);
+      break;
+    }
+    case 8: {
+      st1d(RegData.Z(), CMPPredicate.Zeroing(), MemDst);
+      break;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled VStoreVectorMasked size: {}", ElementSize);
+      break;
   }
 }
 
@@ -1263,6 +1521,7 @@ DEF_OP(StoreMemTSO) {
       stlurb(Src, MemReg, Offset);
     }
     else {
+      // Half-barrier once back-patched.
       nop();
       switch (OpSize) {
         case 2:
@@ -1278,7 +1537,6 @@ DEF_OP(StoreMemTSO) {
           LOGMAN_MSG_A_FMT("Unhandled StoreMemTSO size: {}", OpSize);
           break;
       }
-      nop();
     }
   }
   else if (Op->Class == FEXCore::IR::GPRClass) {
@@ -1289,6 +1547,7 @@ DEF_OP(StoreMemTSO) {
       stlrb(Src, MemReg);
     }
     else {
+      // Half-barrier once back-patched.
       nop();
       switch (OpSize) {
         case 2:
@@ -1304,10 +1563,10 @@ DEF_OP(StoreMemTSO) {
           LOGMAN_MSG_A_FMT("Unhandled StoreMemTSO size: {}", OpSize);
           break;
       }
-      nop();
     }
   }
   else {
+    // Half-Barrier.
     dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
     const auto Src = GetVReg(Op->Value.ID());
     const auto MemSrc = GenerateMemOperand(OpSize, MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
@@ -1336,7 +1595,6 @@ DEF_OP(StoreMemTSO) {
         LOGMAN_MSG_A_FMT("Unhandled StoreMemTSO size: {}", OpSize);
         break;
     }
-    dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
   }
 }
 
@@ -1503,30 +1761,335 @@ DEF_OP(MemSet) {
   // Destination already set to the final pointer.
 }
 
+DEF_OP(MemCpy) {
+  // TODO: A future looking task would be to support this with ARM's MOPS instructions.
+  // The 8-bit non-atomic path directly matches ARM's CPYP/CPYM/CPYE instruction,
+  //
+  // Assuming non-atomicity and non-faulting behaviour, this can accelerate this implementation.
+  const auto Op = IROp->C<IR::IROp_MemCpy>();
+
+  const int32_t Size = Op->Size;
+  const auto MemRegDest = GetReg(Op->AddrDest.ID());
+  const auto MemRegSrc = GetReg(Op->AddrSrc.ID());
+
+  const auto Length = GetReg(Op->Length.ID());
+  const auto Direction = GetReg(Op->Direction.ID());
+
+  auto Dst = GetRegPair(Node);
+  // If Direction == 0 then:
+  //   MemRegDest is incremented (by size)
+  //   MemRegSrc is incremented (by size)
+  // else:
+  //   MemRegDest is decremented (by size)
+  //   MemRegSrc is decremented (by size)
+  //
+  // Counter is decremented regardless.
+
+  ARMEmitter::ForwardLabel BackwardImpl{};
+  ARMEmitter::ForwardLabel Done{};
+
+  mov(TMP1, Length.X());
+  if (Op->PrefixDest.IsInvalid()) {
+    mov(TMP2, MemRegDest.X());
+  }
+  else {
+    const auto Prefix = GetReg(Op->PrefixDest.ID());
+    add(TMP2, Prefix.X(), MemRegDest.X());
+  }
+
+  if (Op->PrefixSrc.IsInvalid()) {
+    mov(TMP3, MemRegSrc.X());
+  }
+  else {
+    const auto Prefix = GetReg(Op->PrefixSrc.ID());
+    add(TMP3, Prefix.X(), MemRegSrc.X());
+  }
+
+  // TMP1 = Length
+  // TMP2 = Dest
+  // TMP3 = Src
+  // TMP4 = load+store temp value
+
+  // Backward or forwards implementation depends on flag
+  cbnz(ARMEmitter::Size::i64Bit, Direction, &BackwardImpl);
+
+  auto MemCpy = [this](uint32_t OpSize, int32_t Size) {
+    switch (OpSize) {
+      case 1:
+        ldrb<ARMEmitter::IndexType::POST>(TMP4.W(), TMP3, Size);
+        strb<ARMEmitter::IndexType::POST>(TMP4.W(), TMP2, Size);
+        break;
+      case 2:
+        ldrh<ARMEmitter::IndexType::POST>(TMP4.W(), TMP3, Size);
+        strh<ARMEmitter::IndexType::POST>(TMP4.W(), TMP2, Size);
+        break;
+      case 4:
+        ldr<ARMEmitter::IndexType::POST>(TMP4.W(), TMP3, Size);
+        str<ARMEmitter::IndexType::POST>(TMP4.W(), TMP2, Size);
+        break;
+      case 8:
+        ldr<ARMEmitter::IndexType::POST>(TMP4, TMP3, Size);
+        str<ARMEmitter::IndexType::POST>(TMP4, TMP2, Size);
+        break;
+      default:
+        LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+        break;
+    }
+  };
+
+  auto MemCpyTSO = [this](uint32_t OpSize, int32_t Size) {
+    if (CTX->HostFeatures.SupportsRCPC) {
+      if (OpSize == 1) {
+        // 8bit load is always aligned to natural alignment
+        ldaprb(TMP4.W(), TMP3);
+        stlrb(TMP4.W(), TMP2);
+      }
+      else {
+        nop();
+        switch (OpSize) {
+          case 2:
+            ldaprh(TMP4.W(), TMP3);
+            break;
+          case 4:
+            ldapr(TMP4.W(), TMP3);
+            break;
+          case 8:
+            ldapr(TMP4, TMP3);
+            break;
+          default:
+            LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+            break;
+        }
+        nop();
+
+        nop();
+        switch (OpSize) {
+          case 2:
+            stlrh(TMP4.W(), TMP2);
+            break;
+          case 4:
+            stlr(TMP4.W(), TMP2);
+            break;
+          case 8:
+            stlr(TMP4, TMP2);
+            break;
+          default:
+            LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+            break;
+        }
+        nop();
+      }
+    }
+    else {
+      if (OpSize == 1) {
+        // 8bit load is always aligned to natural alignment
+        ldarb(TMP4.W(), TMP3);
+        stlrb(TMP4.W(), TMP2);
+      }
+      else {
+        nop();
+        switch (OpSize) {
+          case 2:
+            ldarh(TMP4.W(), TMP3);
+            break;
+          case 4:
+            ldar(TMP4.W(), TMP3);
+            break;
+          case 8:
+            ldar(TMP4, TMP3);
+            break;
+          default:
+            LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+            break;
+        }
+        nop();
+
+        nop();
+        switch (OpSize) {
+          case 2:
+            stlrh(TMP4.W(), TMP2);
+            break;
+          case 4:
+            stlr(TMP4.W(), TMP2);
+            break;
+          case 8:
+            stlr(TMP4, TMP2);
+            break;
+          default:
+            LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+            break;
+        }
+        nop();
+      }
+    }
+
+    if (Size >= 0) {
+      add(ARMEmitter::Size::i64Bit, TMP2, TMP2, OpSize);
+      add(ARMEmitter::Size::i64Bit, TMP3, TMP3, OpSize);
+    }
+    else {
+      sub(ARMEmitter::Size::i64Bit, TMP2, TMP2, OpSize);
+      sub(ARMEmitter::Size::i64Bit, TMP3, TMP3, OpSize);
+    }
+  };
+
+  // Emit forward direction memset then backward direction memset.
+  for (int32_t Direction :  { 1, -1 }) {
+    const int32_t OpSize = Size;
+    const int32_t SizeDirection = Size * Direction;
+
+    ARMEmitter::BackwardLabel AgainInternal{};
+    ARMEmitter::ForwardLabel DoneInternal{};
+
+    // Early exit if zero count.
+    cbz(ARMEmitter::Size::i64Bit, TMP1, &DoneInternal);
+
+    Bind(&AgainInternal);
+    if (Op->IsAtomic) {
+      MemCpyTSO(OpSize, SizeDirection);
+    }
+    else {
+      MemCpy(OpSize, SizeDirection);
+    }
+    sub(ARMEmitter::Size::i64Bit, TMP1, TMP1, 1);
+    cbnz(ARMEmitter::Size::i64Bit, TMP1, &AgainInternal);
+
+    Bind(&DoneInternal);
+
+    // Needs to use temporaries just in case of overwrite
+    mov(TMP1, MemRegDest.X());
+    mov(TMP2, MemRegSrc.X());
+    mov(TMP3, Length.X());
+
+    if (SizeDirection >= 0) {
+      switch (OpSize) {
+        case 1:
+          add(Dst.first.X(), TMP1, TMP3);
+          add(Dst.second.X(), TMP2, TMP3);
+          break;
+        case 2:
+          add(Dst.first.X(), TMP1, TMP3, ARMEmitter::ShiftType::LSL, 1);
+          add(Dst.second.X(), TMP2, TMP3, ARMEmitter::ShiftType::LSL, 1);
+          break;
+        case 4:
+          add(Dst.first.X(), TMP1, TMP3, ARMEmitter::ShiftType::LSL, 2);
+          add(Dst.second.X(), TMP2, TMP3, ARMEmitter::ShiftType::LSL, 2);
+          break;
+        case 8:
+          add(Dst.first.X(), TMP1, TMP3, ARMEmitter::ShiftType::LSL, 3);
+          add(Dst.second.X(), TMP2, TMP3, ARMEmitter::ShiftType::LSL, 3);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, OpSize);
+          break;
+      }
+    }
+    else {
+      switch (OpSize) {
+        case 1:
+          sub(Dst.first.X(), TMP1, TMP3);
+          sub(Dst.second.X(), TMP2, TMP3);
+          break;
+        case 2:
+          sub(Dst.first.X(), TMP1, TMP3, ARMEmitter::ShiftType::LSL, 1);
+          sub(Dst.second.X(), TMP2, TMP3, ARMEmitter::ShiftType::LSL, 1);
+          break;
+        case 4:
+          sub(Dst.first.X(), TMP1, TMP3, ARMEmitter::ShiftType::LSL, 2);
+          sub(Dst.second.X(), TMP2, TMP3, ARMEmitter::ShiftType::LSL, 2);
+          break;
+        case 8:
+          sub(Dst.first.X(), TMP1, TMP3, ARMEmitter::ShiftType::LSL, 3);
+          sub(Dst.second.X(), TMP2, TMP3, ARMEmitter::ShiftType::LSL, 3);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, OpSize);
+          break;
+      }
+    }
+
+    if (Direction == 1) {
+      b(&Done);
+      Bind(&BackwardImpl);
+    }
+  }
+
+  Bind(&Done);
+  // Destination already set to the final pointer.
+}
+
 DEF_OP(ParanoidLoadMemTSO) {
   const auto Op = IROp->C<IR::IROp_LoadMemTSO>();
   const auto OpSize = IROp->Size;
 
-  const auto Addr = GetReg(Op->Addr.ID());
+  const auto MemReg = GetReg(Op->Addr.ID());
 
-  if (!Op->Offset.IsInvalid()) {
-    LOGMAN_MSG_A_FMT("ParanoidLoadMemTSO: No offset allowed");
+  if (CTX->HostFeatures.SupportsTSOImm9 && Op->Class == FEXCore::IR::GPRClass) {
+    const auto Dst = GetReg(Node);
+    uint64_t Offset = 0;
+    if (!Op->Offset.IsInvalid()) {
+      (void)IsInlineConstant(Op->Offset, &Offset);
+    }
+
+    if (OpSize == 1) {
+      // 8bit load is always aligned to natural alignment
+      const auto Dst = GetReg(Node);
+      ldapurb(Dst, MemReg, Offset);
+    }
+    else {
+      switch (OpSize) {
+        case 2:
+          ldapurh(Dst, MemReg, Offset);
+          break;
+        case 4:
+          ldapur(Dst.W(), MemReg, Offset);
+          break;
+        case 8:
+          ldapur(Dst.X(), MemReg, Offset);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", OpSize);
+          break;
+      }
+    }
   }
-
-  if (Op->Class == FEXCore::IR::GPRClass) {
+  else if (CTX->HostFeatures.SupportsRCPC && Op->Class == FEXCore::IR::GPRClass) {
+    const auto Dst = GetReg(Node);
+    if (OpSize == 1) {
+      // 8bit load is always aligned to natural alignment
+      ldaprb(Dst.W(), MemReg);
+    }
+    else {
+      switch (OpSize) {
+        case 2:
+          ldaprh(Dst.W(), MemReg);
+          break;
+        case 4:
+          ldapr(Dst.W(), MemReg);
+          break;
+        case 8:
+          ldapr(Dst.X(), MemReg);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", OpSize);
+          break;
+      }
+    }
+  }
+  else if (Op->Class == FEXCore::IR::GPRClass) {
     const auto Dst = GetReg(Node);
     switch (OpSize) {
       case 1:
-        ldarb(Dst, Addr);
+        ldarb(Dst, MemReg);
         break;
       case 2:
-        ldarh(Dst, Addr);
+        ldarh(Dst, MemReg);
         break;
       case 4:
-        ldar(Dst.W(), Addr);
+        ldar(Dst.W(), MemReg);
         break;
       case 8:
-        ldar(Dst.X(), Addr);
+        ldar(Dst.X(), MemReg);
         break;
       default:
         LOGMAN_MSG_A_FMT("Unhandled ParanoidLoadMemTSO size: {}", OpSize);
@@ -1537,31 +2100,30 @@ DEF_OP(ParanoidLoadMemTSO) {
     const auto Dst = GetVReg(Node);
     switch (OpSize) {
       case 1:
-        ldarb(TMP1, Addr);
-        ins(ARMEmitter::SubRegSize::i8Bit, Dst, 0, TMP1);
+        ldarb(TMP1, MemReg);
+        fmov(ARMEmitter::Size::i32Bit, Dst.S(), TMP1.W());
         break;
       case 2:
-        ldarh(TMP1, Addr);
-        ins(ARMEmitter::SubRegSize::i16Bit, Dst, 0, TMP1);
+        ldarh(TMP1, MemReg);
+        fmov(ARMEmitter::Size::i32Bit, Dst.S(), TMP1.W());
         break;
       case 4:
-        ldar(TMP1.W(), Addr);
-        ins(ARMEmitter::SubRegSize::i32Bit, Dst, 0, TMP1);
+        ldar(TMP1.W(), MemReg);
+        fmov(ARMEmitter::Size::i32Bit, Dst.S(), TMP1.W());
         break;
       case 8:
-        ldar(TMP1, Addr);
-        ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, TMP1);
+        ldar(TMP1, MemReg);
+        fmov(ARMEmitter::Size::i64Bit, Dst.D(), TMP1);
         break;
       case 16:
-        nop();
-        ldaxp(ARMEmitter::Size::i64Bit, TMP1, TMP2, Addr);
+        ldaxp(ARMEmitter::Size::i64Bit, TMP1, TMP2, MemReg);
         clrex();
         ins(ARMEmitter::SubRegSize::i64Bit, Dst, 0, TMP1);
         ins(ARMEmitter::SubRegSize::i64Bit, Dst, 1, TMP2);
         break;
       case 32:
         dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
-        ld1b<ARMEmitter::SubRegSize::i8Bit>(Dst.Z(), PRED_TMP_32B.Zeroing(), Addr);
+        ld1b<ARMEmitter::SubRegSize::i8Bit>(Dst.Z(), PRED_TMP_32B.Zeroing(), MemReg);
         dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
         break;
       default:
@@ -1575,26 +2137,50 @@ DEF_OP(ParanoidStoreMemTSO) {
   const auto Op = IROp->C<IR::IROp_StoreMemTSO>();
   const auto OpSize = IROp->Size;
 
-  const auto Addr = GetReg(Op->Addr.ID());
+  const auto MemReg = GetReg(Op->Addr.ID());
 
-  if (!Op->Offset.IsInvalid()) {
-    LOGMAN_MSG_A_FMT("ParanoidStoreMemTSO: No offset allowed");
+  if (CTX->HostFeatures.SupportsTSOImm9 && Op->Class == FEXCore::IR::GPRClass) {
+    const auto Src = GetReg(Op->Value.ID());
+    uint64_t Offset = 0;
+    if (!Op->Offset.IsInvalid()) {
+      (void)IsInlineConstant(Op->Offset, &Offset);
+    }
+
+    if (OpSize == 1) {
+      // 8bit load is always aligned to natural alignment
+      stlurb(Src, MemReg, Offset);
+    }
+    else {
+      switch (OpSize) {
+        case 2:
+          stlurh(Src, MemReg, Offset);
+          break;
+        case 4:
+          stlur(Src.W(), MemReg, Offset);
+          break;
+        case 8:
+          stlur(Src.X(), MemReg, Offset);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", OpSize);
+          break;
+      }
+    }
   }
-
-  if (Op->Class == FEXCore::IR::GPRClass) {
+  else if (Op->Class == FEXCore::IR::GPRClass) {
     const auto Src = GetReg(Op->Value.ID());
     switch (OpSize) {
       case 1:
-        stlrb(Src, Addr);
+        stlrb(Src, MemReg);
         break;
       case 2:
-        stlrh(Src, Addr);
+        stlrh(Src, MemReg);
         break;
       case 4:
-        stlr(Src.W(), Addr);
+        stlr(Src.W(), MemReg);
         break;
       case 8:
-        stlr(Src.X(), Addr);
+        stlr(Src.X(), MemReg);
         break;
       default:
         LOGMAN_MSG_A_FMT("Unhandled ParanoidStoreMemTSO size: {}", OpSize);
@@ -1607,19 +2193,19 @@ DEF_OP(ParanoidStoreMemTSO) {
     switch (OpSize) {
       case 1:
         umov<ARMEmitter::SubRegSize::i8Bit>(TMP1, Src, 0);
-        stlrb(TMP1, Addr);
+        stlrb(TMP1, MemReg);
         break;
       case 2:
         umov<ARMEmitter::SubRegSize::i16Bit>(TMP1, Src, 0);
-        stlrh(TMP1, Addr);
+        stlrh(TMP1, MemReg);
         break;
       case 4:
         umov<ARMEmitter::SubRegSize::i32Bit>(TMP1, Src, 0);
-        stlr(TMP1.W(), Addr);
+        stlr(TMP1.W(), MemReg);
         break;
       case 8:
         umov<ARMEmitter::SubRegSize::i64Bit>(TMP1, Src, 0);
-        stlr(TMP1, Addr);
+        stlr(TMP1, MemReg);
         break;
       case 16: {
         // Move vector to GPRs
@@ -1629,14 +2215,14 @@ DEF_OP(ParanoidStoreMemTSO) {
         Bind(&B);
 
         // ldaxp must not have both the destination registers be the same
-        ldaxp(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::zr, TMP3, Addr); // <- Can hit SIGBUS. Overwritten with DMB
-        stlxp(ARMEmitter::Size::i64Bit, TMP3, TMP1, TMP2, Addr); // <- Can also hit SIGBUS
+        ldaxp(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::zr, TMP3, MemReg); // <- Can hit SIGBUS. Overwritten with DMB
+        stlxp(ARMEmitter::Size::i64Bit, TMP3, TMP1, TMP2, MemReg); // <- Can also hit SIGBUS
         cbnz(ARMEmitter::Size::i64Bit, TMP3, &B); // < Overwritten with DMB
         break;
       }
       case 32: {
         dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
-        st1b<ARMEmitter::SubRegSize::i8Bit>(Src.Z(), PRED_TMP_32B, Addr, 0);
+        st1b<ARMEmitter::SubRegSize::i8Bit>(Src.Z(), PRED_TMP_32B, MemReg, 0);
         dmb(FEXCore::ARMEmitter::BarrierScope::ISH);
         break;
       }

External/FEXCore/Source/Interface/Core/JIT/Arm64/MiscOps.cpp

@@ -4,11 +4,16 @@ tags: backend|arm64
 $end_info$
 */
 
+#ifndef _WIN32
 #include <syscall.h>
+#endif
+
 #include "Interface/Core/ArchHelpers/CodeEmitter/Emitter.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 #include "FEXCore/Debug/InternalThreadState.h"
 
+#include <FEXCore/Core/SignalDelegator.h>
+
 namespace FEXCore::CPU {
 #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
 
@@ -55,15 +60,15 @@ DEF_OP(Break) {
   str(ARMEmitter::XReg::x1, STATE, offsetof(FEXCore::Core::CpuStateFrame, SynchronousFaultData));
 
   switch (Op->Reason.Signal) {
-  case SIGILL:
+  case Core::FAULT_SIGILL:
     ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGILL));
     br(TMP1);
     break;
-  case SIGTRAP:
+  case Core::FAULT_SIGTRAP:
     ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGTRAP));
     br(TMP1);
     break;
-  case SIGSEGV:
+  case Core::FAULT_SIGSEGV:
     ldr(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.GuestSignal_SIGSEGV));
     br(TMP1);
     break;
@@ -139,7 +144,7 @@ DEF_OP(Print) {
   auto Op = IROp->C<IR::IROp_Print>();
 
   PushDynamicRegsAndLR(TMP1);
-  SpillStaticRegs();
+  SpillStaticRegs(TMP1);
 
   if (IsGPR(Op->Value.ID())) {
     mov(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::r0, GetReg(Op->Value.ID()));
@@ -157,6 +162,7 @@ DEF_OP(Print) {
   PopDynamicRegsAndLR();
 }
 
+#ifndef _WIN32
 DEF_OP(ProcessorID) {
   // We always need to spill x8 since we can't know if it is live at this SSA location
   uint32_t SpillMask = 1U << 8;
@@ -164,7 +170,7 @@ DEF_OP(ProcessorID) {
   // Ordering is incredibly important here
   // We must spill any overlapping registers first THEN claim we are in a syscall without invalidating state at all
   // Only spill the registers that intersect with our usage
-  SpillStaticRegs(false, SpillMask);
+  SpillStaticRegs(TMP1, false, SpillMask);
 
   // Now that we are spilled, store in the state that we are in a syscall
   // Still without overwriting registers that matter
@@ -207,6 +213,11 @@ DEF_OP(ProcessorID) {
   // Node is in w1
   orr(ARMEmitter::Size::i64Bit, GetReg(Node), ARMEmitter::Reg::r0, ARMEmitter::Reg::r1, ARMEmitter::ShiftType::LSL, 12);
 }
+#else
+DEF_OP(ProcessorID) {
+  ERROR_AND_DIE_FMT("Unsupported");
+}
+#endif
 
 DEF_OP(RDRAND) {
   auto Op = IROp->C<IR::IROp_RDRAND>();

External/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp

@@ -8,6 +8,8 @@ $end_info$
 #include "Interface/Core/ArchHelpers/CodeEmitter/Registers.h"
 #include "Interface/Core/JIT/Arm64/JITClass.h"
 
+#include <FEXCore/Utils/MathUtils.h>
+
 namespace FEXCore::CPU {
 #define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const *IROp, IR::NodeID Node)
 DEF_OP(VectorZero) {
@@ -361,7 +363,6 @@ DEF_OP(VAddP) {
     const auto Pred = PRED_TMP_32B.Merging();
 
     // SVE ADDP is a destructive operation, so we need a temporary
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
     movprfx(VTMP1.Z(), VectorLower.Z());
 
     // Unlike Adv. SIMD's version of ADDP, which acts like it concats the
@@ -609,7 +610,6 @@ DEF_OP(VFAddP) {
     const auto Pred = PRED_TMP_32B.Merging();
 
     // SVE FADDP is a destructive operation, so we need a temporary
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
     movprfx(VTMP1.Z(), VectorLower.Z());
 
     // Unlike Adv. SIMD's version of FADDP, which acts like it concats the
@@ -1533,17 +1533,13 @@ DEF_OP(VCMPEQ) {
     const auto Mask = PRED_TMP_32B.Zeroing();
     const auto ComparePred = ARMEmitter::PReg::p0;
 
-    // Ensure no junk is in the temp (important for ensuring
-    // non-equal entries remain as zero during the final bitwise OR).
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
-
     // General idea is to compare for equality, not the equal vals
     // from one of the registers, then or both together to make the
     // relevant equal entries all 1s.
     cmpeq(SubRegSize.Vector, ComparePred, Mask, Vector1.Z(), Vector2.Z());
     not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector1.Z());
-    orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector1.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector1.Z());
+    orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
   } else {
     if (IsScalar) {
       cmeq(SubRegSize.Scalar, Dst, Vector1, Vector2);
@@ -1617,17 +1613,13 @@ DEF_OP(VCMPGT) {
     const auto Mask = PRED_TMP_32B.Zeroing();
     const auto ComparePred = ARMEmitter::PReg::p0;
 
-    // Ensure no junk is in the temp (important for ensuring
-    // non greater-than values remain as zero).
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
-
     // General idea is to compare for greater-than, bitwise NOT
     // the valid values, then ORR the NOTed values with the original
     // values to form entries that are all 1s.
     cmpgt(SubRegSize.Vector, ComparePred, Mask, Vector1.Z(), Vector2.Z());
     not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector1.Z());
-    orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector1.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector1.Z());
+    orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
   } else {
     if (IsScalar) {
       cmgt(SubRegSize.Scalar, Dst, Vector1, Vector2);
@@ -1735,12 +1727,10 @@ DEF_OP(VFCMPEQ) {
     const auto Mask = PRED_TMP_32B.Zeroing();
     const auto ComparePred = ARMEmitter::PReg::p0;
 
-    // Ensure we have no junk in the temporary.
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
     fcmeq(SubRegSize.Vector, ComparePred, Mask, Vector1.Z(), Vector2.Z());
     not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector1.Z());
-    orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector1.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector1.Z());
+    orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
   } else {
     if (IsScalar) {
       switch (ElementSize) {
@@ -1784,12 +1774,10 @@ DEF_OP(VFCMPNEQ) {
     const auto Mask = PRED_TMP_32B.Zeroing();
     const auto ComparePred = ARMEmitter::PReg::p0;
 
-    // Ensure we have no junk in the temporary.
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
     fcmne(SubRegSize.Vector, ComparePred, Mask, Vector1.Z(), Vector2.Z());
     not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector1.Z());
-    orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector1.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector1.Z());
+    orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
   } else {
     if (IsScalar) {
       switch (ElementSize) {
@@ -1835,12 +1823,10 @@ DEF_OP(VFCMPLT) {
     const auto Mask = PRED_TMP_32B.Zeroing();
     const auto ComparePred = ARMEmitter::PReg::p0;
 
-    // Ensure we have no junk in the temporary.
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
     fcmgt(SubRegSize.Vector, ComparePred, Mask, Vector2.Z(), Vector1.Z());
     not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector2.Z());
-    orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector2.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector2.Z());
+    orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
   } else {
     if (IsScalar) {
       switch (ElementSize) {
@@ -1884,12 +1870,10 @@ DEF_OP(VFCMPGT) {
     const auto Mask = PRED_TMP_32B.Zeroing();
     const auto ComparePred = ARMEmitter::PReg::p0;
 
-    // Ensure there's no junk in the temporary.
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
     fcmgt(SubRegSize.Vector, ComparePred, Mask, Vector1.Z(), Vector2.Z());
     not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector1.Z());
-    orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector1.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector1.Z());
+    orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
   } else {
     if (IsScalar) {
       switch (ElementSize) {
@@ -1933,12 +1917,10 @@ DEF_OP(VFCMPLE) {
     const auto Mask = PRED_TMP_32B.Zeroing();
     const auto ComparePred = ARMEmitter::PReg::p0;
 
-    // Ensure there's no junk in the temporary.
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
     fcmge(SubRegSize.Vector, ComparePred, Mask, Vector2.Z(), Vector1.Z());
     not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector2.Z());
-    orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector2.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector2.Z());
+    orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
   } else {
     if (IsScalar) {
       switch (ElementSize) {
@@ -1983,17 +1965,14 @@ DEF_OP(VFCMPORD) {
     const auto Mask = PRED_TMP_32B.Zeroing();
     const auto ComparePred = ARMEmitter::PReg::p0;
 
-    // Ensure there's no junk in the temporary.
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
-
     // The idea is like comparing for unordered, but we just
     // invert the predicate from the comparison to instead
     // select all ordered elements in the vector.
     fcmuo(SubRegSize.Vector, ComparePred, Mask, Vector1.Z(), Vector2.Z());
     not_(ComparePred, Mask, ComparePred);
     not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector1.Z());
-    orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector1.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector1.Z());
+    orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
   } else {
     if (IsScalar) {
       switch (ElementSize) {
@@ -2044,13 +2023,10 @@ DEF_OP(VFCMPUNO) {
     const auto Mask = PRED_TMP_32B.Zeroing();
     const auto ComparePred = ARMEmitter::PReg::p0;
 
-    // Ensure there's no junk in the temporary.
-    eor(VTMP1.Z(), VTMP1.Z(), VTMP1.Z());
-
     fcmuo(SubRegSize.Vector, ComparePred, Mask, Vector1.Z(), Vector2.Z());
     not_(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), Vector1.Z());
-    orr(SubRegSize.Vector, VTMP1.Z(), ComparePred.Merging(), VTMP1.Z(), Vector1.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    movprfx(SubRegSize.Vector, Dst.Z(), ComparePred.Zeroing(), Vector1.Z());
+    orr(SubRegSize.Vector, Dst.Z(), ComparePred.Merging(), Dst.Z(), VTMP1.Z());
   } else {
     if (IsScalar) {
       switch (ElementSize) {
@@ -2082,11 +2058,94 @@ DEF_OP(VFCMPUNO) {
 }
 
 DEF_OP(VUShl) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
+  const auto Op = IROp->C<IR::IROp_VUShl>();
+  const auto OpSize = IROp->Size;
+
+  const auto ElementSize = IROp->ElementSize;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto MaxShift = ElementSize * 8;
+
+  const auto Dst = GetVReg(Node);
+  const auto ShiftVector = GetVReg(Op->ShiftVector.ID());
+  const auto Vector = GetVReg(Op->Vector.ID());
+
+  LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8, "Invalid size");
+  const auto SubRegSize =
+    ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i8Bit;
+
+  if (HostSupportsSVE && Is256Bit) {
+    const auto Mask = PRED_TMP_32B.Merging();
+
+    dup_imm(SubRegSize, VTMP2.Z(), MaxShift);
+    umin(SubRegSize, VTMP2.Z(), Mask, VTMP2.Z(), ShiftVector.Z());
+
+    movprfx(Dst.Z(), Vector.Z());
+    lsl(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP2.Z());
+  } else {
+    if (ElementSize < 8) {
+      movi(SubRegSize, VTMP1.Q(), MaxShift);
+      umin(SubRegSize, VTMP1.Q(), VTMP1.Q(), ShiftVector.Q());
+    } else {
+      LoadConstant(ARMEmitter::Size::i64Bit, TMP1, MaxShift);
+      dup(SubRegSize, VTMP1.Q(), TMP1.R());
+
+      // UMIN is silly on Adv.SIMD and doesn't have a variant that handles 64-bit elements
+      cmhi(SubRegSize, VTMP2.Q(), ShiftVector.Q(), VTMP1.Q());
+      bif(VTMP1.Q(), ShiftVector.Q(), VTMP2.Q());
+    }
+
+    ushl(SubRegSize, Dst.Q(), Vector.Q(), VTMP1.Q());
+  }
 }
 
 DEF_OP(VUShr) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
+  const auto Op = IROp->C<IR::IROp_VUShr>();
+  const auto OpSize = IROp->Size;
+
+  const auto ElementSize = IROp->ElementSize;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto MaxShift = ElementSize * 8;
+
+  const auto Dst = GetVReg(Node);
+  const auto ShiftVector = GetVReg(Op->ShiftVector.ID());
+  const auto Vector = GetVReg(Op->Vector.ID());
+
+  LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8, "Invalid size");
+  const auto SubRegSize =
+    ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i8Bit;
+
+  if (HostSupportsSVE && Is256Bit) {
+    const auto Mask = PRED_TMP_32B.Merging();
+
+    dup_imm(SubRegSize, VTMP2.Z(), MaxShift);
+    umin(SubRegSize, VTMP2.Z(), Mask, VTMP2.Z(), ShiftVector.Z());
+
+    movprfx(Dst.Z(), Vector.Z());
+    lsr(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP2.Z());
+  } else {
+    if (ElementSize < 8) {
+      movi(SubRegSize, VTMP1.Q(), MaxShift);
+      umin(SubRegSize, VTMP1.Q(), VTMP1.Q(), ShiftVector.Q());
+    } else {
+      LoadConstant(ARMEmitter::Size::i64Bit, TMP1, MaxShift);
+      dup(SubRegSize, VTMP1.Q(), TMP1.R());
+
+      // UMIN is silly on Adv.SIMD and doesn't have a variant that handles 64-bit elements
+      cmhi(SubRegSize, VTMP2.Q(), ShiftVector.Q(), VTMP1.Q());
+      bif(VTMP1.Q(), ShiftVector.Q(), VTMP2.Q());
+    }
+
+    // Need to invert shift values to perform a right shift with USHL
+    // (USHR only has an immediate variant).
+    neg(SubRegSize, VTMP1.Q(), VTMP1.Q());
+    ushl(SubRegSize, Dst.Q(), Vector.Q(), VTMP1.Q());
+  }
 }
 
 DEF_OP(VSShr) {
@@ -2111,17 +2170,23 @@ DEF_OP(VSShr) {
   if (HostSupportsSVE && Is256Bit) {
     const auto Mask = PRED_TMP_32B.Merging();
 
-    dup_imm(SubRegSize, VTMP2.Z(), MaxShift);
-    umin(SubRegSize, VTMP2.Z(), Mask, VTMP2.Z(), ShiftVector.Z());
+    dup_imm(SubRegSize, VTMP1.Z(), MaxShift);
+    umin(SubRegSize, VTMP1.Z(), Mask, VTMP1.Z(), ShiftVector.Z());
 
-    movprfx(VTMP1.Z(), Vector.Z());
-    asr(SubRegSize, VTMP1.Z(), Mask, VTMP1.Z(), VTMP2.Z());
-    mov(Dst.Z(), VTMP1.Z());
+    movprfx(Dst.Z(), Vector.Z());
+    asr(SubRegSize, Dst.Z(), Mask, Dst.Z(), VTMP1.Z());
   } else {
-    LOGMAN_THROW_AA_FMT(ElementSize != 8, "Adv. SIMD UMIN doesn't handle 64-bit values");
+    if (ElementSize < 8) {
+      movi(SubRegSize, VTMP1.Q(), MaxShift);
+      umin(SubRegSize, VTMP1.Q(), VTMP1.Q(), ShiftVector.Q());
+    } else {
+      LoadConstant(ARMEmitter::Size::i64Bit, TMP1, MaxShift);
+      dup(SubRegSize, VTMP1.Q(), TMP1.R());
 
-    movi(SubRegSize, VTMP1.Q(), MaxShift);
-    umin(SubRegSize, VTMP1.Q(), VTMP1.Q(), ShiftVector.Q());
+      // UMIN is silly on Adv.SIMD and doesn't have a variant that handles 64-bit elements
+      cmhi(SubRegSize, VTMP2.Q(), ShiftVector.Q(), VTMP1.Q());
+      bif(VTMP1.Q(), ShiftVector.Q(), VTMP2.Q());
+    }
 
     // Need to invert shift values to perform a right shift with SSHL
     // (SSHR only has an immediate variant).
@@ -2230,40 +2295,47 @@ DEF_OP(VInsElement) {
   const auto OpSize = IROp->Size;
   const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
 
-  const auto ElementSize = Op->Header.ElementSize;
+  const uint32_t ElementSize = Op->Header.ElementSize;
 
-  const auto DestIdx = Op->DestIdx;
-  const auto SrcIdx = Op->SrcIdx;
+  const uint32_t DestIdx = Op->DestIdx;
+  const uint32_t SrcIdx = Op->SrcIdx;
 
   const auto Dst = GetVReg(Node);
   const auto SrcVector = GetVReg(Op->SrcVector.ID());
   auto Reg = GetVReg(Op->DestVector.ID());
 
   if (HostSupportsSVE && Is256Bit) {
+    LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8 || ElementSize == 16, "Invalid size");
+    const auto SubRegSize =
+      ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
+      ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
+      ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+      ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i128Bit;
+
     // We're going to use this to create our predicate register literal.
     // On an SVE 256-bit capable system, the predicate register will be
     // 32-bit in size. We want to set up only the element corresponding
     // to the destination index, since we're going to copy over the equivalent
     // indexed element from the source vector.
-    auto Data = [ElementSize, DestIdx]() -> uint32_t {
+    const auto Data = [ElementSize, DestIdx]() -> uint32_t {
+      const auto Log2ElementSize = FEXCore::ilog2(ElementSize);
+
+      [[maybe_unused]] const auto MaxIndex = (32U >> Log2ElementSize) - 1;
+      LOGMAN_THROW_AA_FMT(DestIdx <= MaxIndex, "DestIdx ({}) out of range. Must be within [0, {}]",
+                          DestIdx, MaxIndex);
+
+      const auto ShiftAmount = DestIdx << Log2ElementSize;
+
       switch (ElementSize) {
         case 1:
-          LOGMAN_THROW_AA_FMT(DestIdx <= 31, "DestIdx out of range: {}", DestIdx);
-          return 1U << DestIdx;
         case 2:
-          LOGMAN_THROW_AA_FMT(DestIdx <= 15, "DestIdx out of range: {}", DestIdx);
-          return 1U << (DestIdx * 2);
         case 4:
-          LOGMAN_THROW_AA_FMT(DestIdx <= 7, "DestIdx out of range: {}", DestIdx);
-          return 1U << (DestIdx * 4);
         case 8:
-          LOGMAN_THROW_AA_FMT(DestIdx <= 3, "DestIdx out of range: {}", DestIdx);
-          return 1U << (DestIdx * 8);
+          return 1U << ShiftAmount;
         case 16:
-          LOGMAN_THROW_AA_FMT(DestIdx <= 1, "DestIdx out of range: {}", DestIdx);
           // Predicates can't be subdivided into the Q format, so we can just set up
           // the predicate to select the two adjacent doublewords.
-          return 0x101U << (DestIdx * 16);
+          return 0x101U << ShiftAmount;
         default:
           FEX_UNREACHABLE;
           return UINT32_MAX;
@@ -2276,13 +2348,6 @@ DEF_OP(VInsElement) {
     adr(TMP1, &DataLocation);
     ldr(Predicate, TMP1);
 
-    LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8 || ElementSize == 16, "Invalid size");
-    const auto SubRegSize =
-      ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
-      ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
-      ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
-      ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i128Bit;
-
     // Broadcast our source value across a temporary,
     // then combine with the destination.
     dup(SubRegSize, VTMP2.Z(), SrcVector.Z(), SrcIdx);
@@ -2302,11 +2367,6 @@ DEF_OP(VInsElement) {
     Bind(&PastConstant);
   }
   else {
-    if (Dst.Idx() != Reg.Idx()) {
-      mov(VTMP1.Q(), Reg.Q());
-      Reg = VTMP1;
-    }
-
     LOGMAN_THROW_AA_FMT(ElementSize == 1 || ElementSize == 2 || ElementSize == 4 || ElementSize == 8, "Invalid size");
     const auto SubRegSize =
       ElementSize == 1 ? ARMEmitter::SubRegSize::i8Bit :
@@ -2314,6 +2374,11 @@ DEF_OP(VInsElement) {
       ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
       ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i8Bit;
 
+    if (Dst.Idx() != Reg.Idx()) {
+      mov(VTMP1.Q(), Reg.Q());
+      Reg = VTMP1;
+    }
+
     ins(SubRegSize, Reg.Q(), DestIdx, SrcVector.Q(), SrcIdx);
 
     if (Dst.Idx() != Reg.Idx()) {
@@ -2962,6 +3027,37 @@ DEF_OP(VUABDL) {
   }
 }
 
+DEF_OP(VUABDL2) {
+  const auto Op = IROp->C<IR::IROp_VUABDL2>();
+  const auto OpSize = IROp->Size;
+
+  const auto ElementSize = Op->Header.ElementSize;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto Dst = GetVReg(Node);
+  const auto Vector1 = GetVReg(Op->Vector1.ID());
+  const auto Vector2 = GetVReg(Op->Vector2.ID());
+
+  LOGMAN_THROW_AA_FMT(ElementSize == 2 || ElementSize == 4 || ElementSize == 8, "Invalid size");
+  const auto SubRegSize =
+    ElementSize == 2 ? ARMEmitter::SubRegSize::i16Bit :
+    ElementSize == 4 ? ARMEmitter::SubRegSize::i32Bit :
+    ElementSize == 8 ? ARMEmitter::SubRegSize::i64Bit : ARMEmitter::SubRegSize::i8Bit;
+
+  if (HostSupportsSVE && Is256Bit) {
+    // To mimic the behavior of AdvSIMD UABDL, we need to get the
+    // absolute difference of the even elements (UADBLB), get the
+    // absolute difference of the odd elemenets (UABDLT), then
+    // interleave the results in both vectors together.
+
+    uabdlb(SubRegSize, VTMP1.Z(), Vector1.Z(), Vector2.Z());
+    uabdlt(SubRegSize, VTMP2.Z(), Vector1.Z(), Vector2.Z());
+    zip2(SubRegSize, Dst.Z(), VTMP1.Z(), VTMP2.Z());
+  } else {
+    uabdl2(SubRegSize, Dst.Q(), Vector1.Q(), Vector2.Q());
+  }
+}
+
 DEF_OP(VTBL1) {
   const auto Op = IROp->C<IR::IROp_VTBL1>();
   const auto OpSize = IROp->Size;

External/FEXCore/Source/Interface/Core/JIT/JITCore.h

@@ -1,6 +1,7 @@
 #pragma once
 
-#include <memory>
+#include <FEXCore/Core/CPUBackend.h>
+#include <FEXCore/fextl/memory.h>
 
 namespace FEXCore::Context {
 class ContextImpl;
@@ -13,14 +14,12 @@ struct InternalThreadState;
 namespace FEXCore::CPU {
 class CPUBackend;
 
-[[nodiscard]] std::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::ContextImpl *ctx,
+[[nodiscard]] fextl::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::ContextImpl *ctx,
                                                            FEXCore::Core::InternalThreadState *Thread);
-void InitializeX86JITSignalHandlers(FEXCore::Context::ContextImpl *CTX);
 CPUBackendFeatures GetX86JITBackendFeatures();
 
-[[nodiscard]] std::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl *ctx,
+[[nodiscard]] fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl *ctx,
                                                              FEXCore::Core::InternalThreadState *Thread);
-void InitializeArm64JITSignalHandlers(FEXCore::Context::ContextImpl *CTX);
 CPUBackendFeatures GetArm64JITBackendFeatures();
 
 } // namespace FEXCore::CPU

External/FEXCore/Source/Interface/Core/JIT/x86_64/ALUOps.cpp

@@ -5,6 +5,7 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/LogManager.h>
@@ -12,7 +13,6 @@ $end_info$
 #include <array>
 #include <stdint.h>
 #include <utility>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 
@@ -161,6 +161,30 @@ DEF_OP(Neg) {
   neg(Dst);
 }
 
+DEF_OP(Abs) {
+  auto Op = IROp->C<IR::IROp_Abs>();
+  const uint8_t OpSize = IROp->Size;
+
+  Xbyak::Reg Src;
+  Xbyak::Reg Dst;
+  switch (OpSize) {
+  case 4:
+    Src = GetSrc<RA_32>(Op->Src.ID());
+    Dst = GetDst<RA_32>(Node);
+    break;
+  case 8:
+    Src = GetSrc<RA_64>(Op->Src.ID());
+    Dst = GetDst<RA_64>(Node);
+    break;
+  default:  LOGMAN_MSG_A_FMT("Unhandled Abs size: {}", OpSize);
+    break;
+  }
+  mov(Dst, Src);
+  mov(TMP1, Src);
+  neg(Dst);
+  cmovs(Dst, TMP1);
+}
+
 DEF_OP(Mul) {
   auto Op = IROp->C<IR::IROp_Mul>();
   const uint8_t OpSize = IROp->Size;
@@ -1116,7 +1140,28 @@ DEF_OP(Select) {
     } else {
       cmp(GRCMP(Op->Cmp1.ID()), GRCMP(Op->Cmp2.ID()));
     }
-  } else if (IsFPR(Op->Cmp1.ID())) {
+  }
+  else if (IsGPRPair(Op->Cmp1.ID())) {
+    if (Op->CompareSize == 4) {
+      const auto Src1 = GetSrcPair<RA_32>(Op->Cmp1.ID());
+      const auto Src2 = GetSrcPair<RA_32>(Op->Cmp2.ID());
+      mov (TMP1.cvt32(), Src1.first);
+      mov (TMP2.cvt32(), Src1.second);
+      xor_(TMP1.cvt32(), Src2.first);
+      xor_(TMP2.cvt32(), Src2.second);
+      or_(TMP1.cvt32(), TMP2.cvt32());
+    }
+    else {
+      const auto Src1 = GetSrcPair<RA_64>(Op->Cmp1.ID());
+      const auto Src2 = GetSrcPair<RA_64>(Op->Cmp2.ID());
+      mov (TMP1, Src1.first);
+      mov (TMP2, Src1.second);
+      xor_(TMP1, Src2.first);
+      xor_(TMP2, Src2.second);
+      or_(TMP1, TMP2);
+    }
+  }
+  else if (IsFPR(Op->Cmp1.ID())) {
     if (Op->CompareSize  == 4)
       ucomiss(GetSrc(Op->Cmp1.ID()), GetSrc(Op->Cmp2.ID()));
     else
@@ -1298,6 +1343,7 @@ void X86JITCore::RegisterALUHandlers() {
   REGISTER_OP(ADD,               Add);
   REGISTER_OP(SUB,               Sub);
   REGISTER_OP(NEG,               Neg);
+  REGISTER_OP(ABS,               Abs);
   REGISTER_OP(MUL,               Mul);
   REGISTER_OP(UMUL,              UMul);
   REGISTER_OP(DIV,               Div);

External/FEXCore/Source/Interface/Core/JIT/x86_64/AtomicOps.cpp

@@ -5,6 +5,7 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/LogManager.h>
@@ -12,7 +13,6 @@ $end_info$
 #include <array>
 #include <stdint.h>
 #include <utility>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 #define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

External/FEXCore/Source/Interface/Core/JIT/x86_64/BranchOps.cpp

@@ -7,6 +7,7 @@ $end_info$
 #include "Interface/Context/Context.h"
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "Interface/HLE/Thunks/Thunks.h"
@@ -25,7 +26,6 @@ $end_info$
 #include <stdint.h>
 #include <unordered_map>
 #include <utility>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 #define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
@@ -146,6 +146,7 @@ DEF_OP(Syscall) {
   auto Op = IROp->C<IR::IROp_Syscall>();
   // XXX: This is very terrible, but I don't care for right now
 
+  FEXCore::IR::SyscallFlags Flags = Op->Flags;
   auto NumPush = RA64.size();
 
   for (auto &Reg : RA64)
@@ -186,7 +187,11 @@ DEF_OP(Syscall) {
   for (uint32_t i = RA64.size(); i > 0; --i)
     pop(RA64[i - 1]);
 
-  mov (GetDst<RA_64>(Node), rax);
+  if ((Flags & FEXCore::IR::SyscallFlags::NORETURNEDRESULT) != FEXCore::IR::SyscallFlags::NORETURNEDRESULT) {
+    // Move result to its destination register.
+    // Only if `NORETURNEDRESULT` wasn't set, otherwise we might overwrite the CPUState refilled with `FillStaticRegs`
+    mov (GetDst<RA_64>(Node), rax);
+  }
 }
 
 DEF_OP(Thunk) {
@@ -302,6 +307,42 @@ DEF_OP(CPUID) {
   mov(Dst.second, rdx);
 }
 
+DEF_OP(XGETBV) {
+  auto Op = IROp->C<IR::IROp_XGetBV>();
+
+  for (auto &Reg : RA64)
+    push(Reg);
+
+  // CPUID ABI
+  // this: rdi
+  // Function: rsi
+  //
+  // Result: RAX, RDX. 4xi32
+
+  // rsi can be in the source registers, so copy argument to edx first
+  mov (esi, GetSrc<RA_32>(Op->Function.ID()));
+  mov (rdi, qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.CPUIDObj)]);
+
+  auto NumPush = RA64.size();
+
+  if (NumPush & 1)
+    sub(rsp, 8); // Align
+
+  // {rdi, rsi, rdx}
+  call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.XCRFunction)]);
+
+  if (NumPush & 1)
+    add(rsp, 8); // Align
+
+  for (uint32_t i = RA64.size(); i > 0; --i)
+    pop(RA64[i - 1]);
+
+  auto Dst = GetSrcPair<RA_64>(Node);
+  mov(Dst.first.cvt32(), eax);
+  mov(Dst.second, rax);
+  shr(Dst.second, 32);
+}
+
 #undef DEF_OP
 void X86JITCore::RegisterBranchHandlers() {
 #define REGISTER_OP(op, x) OpHandlers[FEXCore::IR::IROps::OP_##op] = &X86JITCore::Op_##x
@@ -314,6 +355,7 @@ void X86JITCore::RegisterBranchHandlers() {
   REGISTER_OP(VALIDATECODE,      ValidateCode);
   REGISTER_OP(THREADREMOVECODEENTRY,   ThreadRemoveCodeEntry);
   REGISTER_OP(CPUID,             CPUID);
+  REGISTER_OP(XGETBV,            XGETBV);
 #undef REGISTER_OP
 }
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/ConversionOps.cpp

@@ -5,13 +5,12 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/LogManager.h>
 
 #include <array>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 

External/FEXCore/Source/Interface/Core/JIT/x86_64/EncryptionOps.cpp

@@ -5,12 +5,11 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include <FEXCore/IR/IR.h>
 
 #include <array>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 #define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)

External/FEXCore/Source/Interface/Core/JIT/x86_64/FlagOps.cpp

@@ -5,12 +5,12 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 
 #include <FEXCore/IR/IR.h>
 
 #include <array>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 

External/FEXCore/Source/Interface/Core/JIT/x86_64/JIT.cpp

@@ -19,7 +19,6 @@ $end_info$
 
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/Core/CoreState.h>
-#include <FEXCore/Core/SignalDelegator.h>
 #include <FEXCore/Debug/InternalThreadState.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
@@ -28,6 +27,7 @@ $end_info$
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/Utils/Profiler.h>
+#include <FEXCore/fextl/sstream.h>
 
 #include <algorithm>
 #include <array>
@@ -35,12 +35,9 @@ $end_info$
 #include <stddef.h>
 #include <stdint.h>
 #include <signal.h>
-#include <sys/mman.h>
 #include <tuple>
 #include <unordered_map>
 #include <utility>
-#include <vector>
-#include <xbyak/xbyak.h>
 
 // #define DEBUG_RA 1
 // #define DEBUG_CYCLES
@@ -307,6 +304,63 @@ void X86JITCore::Op_Unhandled(IR::IROp_Header *IROp, IR::NodeID Node) {
       }
       break;
 
+      case FABI_I32_I64_I64_I128_I128_I16: {
+        PushRegs();
+
+        const auto Op = IROp->C<IR::IROp_VPCMPESTRX>();
+        const auto Control = Op->Control;
+
+        const auto LHS = GetSrc(Op->LHS.ID());
+        const auto RHS = GetSrc(Op->RHS.ID());
+        const auto SrcRAX = GetSrc<RA_64>(Op->RAX.ID());
+        const auto SrcRDX = GetSrc<RA_64>(Op->RDX.ID());
+
+        mov(rdi, SrcRAX);
+        mov(rsi, SrcRDX);
+
+        movq(rdx, LHS);
+        pextrq(rcx, LHS, 1);
+
+        movq(r8, RHS);
+        pextrq(r9, RHS, 1);
+
+        sub(rsp, 16);
+        mov(dword [rsp], Control);
+
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
+
+        add(rsp, 16);
+        PopRegs();
+
+        mov(GetDst<RA_32>(Node), rax);
+        break;
+      }
+
+      case FABI_I32_I128_I128_I16: {
+        PushRegs();
+
+        const auto Op = IROp->C<IR::IROp_VPCMPISTRX>();
+
+        const auto LHS = GetSrc(Op->LHS.ID());
+        const auto RHS = GetSrc(Op->RHS.ID());
+        const auto Control = Op->Control;
+
+        movq(rdi, LHS);
+        pextrq(rsi, LHS, 1);
+
+        movq(rdx, RHS);
+        pextrq(rcx, RHS, 1);
+
+        mov(r8, Control);
+
+        call(qword [STATE + offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.FallbackHandlerPointers[Info.HandlerIndex])]);
+
+        PopRegs();
+
+        mov(GetDst<RA_32>(Node), rax);
+        break;
+      }
+
       case FABI_UNKNOWN:
       default:
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
@@ -330,7 +384,7 @@ static uint64_t X86JITCore_ExitFunctionLink(FEXCore::Core::CpuStateFrame *Frame,
   }
 
   auto LinkerAddress = Frame->Pointers.Common.ExitFunctionLinker;
-  Context::ContextImpl::ThreadAddBlockLink(Thread, GuestRip, (uintptr_t)record, [record, LinkerAddress]{
+  Thread->LookupCache->AddBlockLink(GuestRip, (uintptr_t)record, [record, LinkerAddress]{
     // undo the link
     record[0] = LinkerAddress;
   });
@@ -349,7 +403,7 @@ X86JITCore::X86JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::Intern
 
   RAPass = Thread->PassManager->GetPass<IR::RegisterAllocationPass>("RA");
 
-  RAPass->AllocateRegisterSet(RegisterCount, RegisterClasses);
+  RAPass->AllocateRegisterSet(RegisterClasses);
   RAPass->AddRegisters(FEXCore::IR::GPRClass, NumGPRs);
   RAPass->AddRegisters(FEXCore::IR::FPRClass, NumXMMs);
   RAPass->AddRegisters(FEXCore::IR::GPRPairClass, NumGPRPairs);
@@ -387,6 +441,11 @@ X86JITCore::X86JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::Intern
       Common.CPUIDFunction = PMF.GetConvertedPointer();
     }
 
+    {
+      FEXCore::Utils::MemberFunctionToPointerCast PMF(&FEXCore::CPUIDEmu::RunXCRFunction);
+      Common.XCRFunction = PMF.GetConvertedPointer();
+    }
+
     Common.SyscallHandlerObj = reinterpret_cast<uint64_t>(CTX->SyscallHandler);
     Common.SyscallHandlerFunc = reinterpret_cast<uint64_t>(FEXCore::Context::HandleSyscall);
     Common.ExitFunctionLink = reinterpret_cast<uintptr_t>(&Context::ContextImpl::ThreadExitFunctionLink<X86JITCore_ExitFunctionLink>);
@@ -399,12 +458,6 @@ X86JITCore::X86JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::Intern
   ClearCache();
 }
 
-void X86JITCore::InitializeSignalHandlers(FEXCore::Context::ContextImpl *CTX) {
-  CTX->SignalDelegation->RegisterHostSignalHandler(SIGILL, [](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) -> bool {
-    return static_cast<Context::ContextImpl*>(Thread->CTX)->Dispatcher->HandleSIGILL(Thread, Signal, info, ucontext);
-  }, true);
-}
-
 X86JITCore::~X86JITCore() {
 
 }
@@ -431,11 +484,15 @@ IR::PhysicalRegister X86JITCore::GetPhys(IR::NodeID Node) const {
 }
 
 bool X86JITCore::IsFPR(IR::NodeID Node) const {
-  return RAData->GetNodeRegister(Node).Class == IR::FPRClass.Val;
+  return RAData->GetNodeRegister(Node).Class == IR::FPRClass;
 }
 
 bool X86JITCore::IsGPR(IR::NodeID Node) const {
-  return RAData->GetNodeRegister(Node).Class == IR::GPRClass.Val;
+  return RAData->GetNodeRegister(Node).Class == IR::GPRClass;
+}
+
+bool X86JITCore::IsGPRPair(IR::NodeID Node) const {
+  return RAData->GetNodeRegister(Node).Class == IR::GPRPairClass;
 }
 
 template<uint8_t RAType>
@@ -706,7 +763,7 @@ CPUBackend::CompiledCode X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]
       if (IROp->Op != IR::OP_BEGINBLOCK &&
           IROp->Op != IR::OP_CONDJUMP &&
           IROp->Op != IR::OP_JUMP) {
-        std::stringstream Inst;
+        fextl::stringstream Inst;
         auto Name = FEXCore::IR::GetName(IROp->Op);
 
         if (IROp->HasDest) {
@@ -764,12 +821,33 @@ CPUBackend::CompiledCode X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]
   auto JITBlockTail = getCurr<JITCodeTail*>();
   setSize(getSize() + sizeof(JITCodeTail));
 
+  auto JITRIPEntriesLocation = getCurr<uint8_t *>();
+  auto JITRIPEntries = getCurr<JITRIPReconstructEntries*>();
+
+  setSize(getSize() + sizeof(JITRIPReconstructEntries) * DebugData->GuestOpcodes.size());
+
   // Put the block's RIP entry in the tail.
   // This will be used for RIP reconstruction in the future.
   // TODO: This needs to be a data RIP relocation once code caching works.
   //   Current relocation code doesn't support this feature yet.
   JITBlockTail->RIP = Entry;
 
+  {
+    // Store the RIP entries.
+    JITBlockTail->NumberOfRIPEntries = DebugData->GuestOpcodes.size();
+    JITBlockTail->OffsetToRIPEntries = JITRIPEntriesLocation - JITBlockTailLocation;
+    uintptr_t CurrentRIPOffset = 0;
+    uint64_t CurrentPCOffset = 0;
+    for (size_t i = 0; i < DebugData->GuestOpcodes.size(); i++) {
+      const auto &GuestOpcode = DebugData->GuestOpcodes[i];
+      auto &RIPEntry = JITRIPEntries[i];
+      RIPEntry.HostPCOffset = GuestOpcode.HostEntryOffset - CurrentPCOffset;
+      RIPEntry.GuestRIPOffset = GuestOpcode.GuestEntryOffset - CurrentRIPOffset;
+      CurrentPCOffset = GuestOpcode.HostEntryOffset;
+      CurrentRIPOffset = GuestOpcode.GuestEntryOffset;
+    }
+  }
+
   CodeHeader->OffsetToBlockTail = JITBlockTailLocation - CodeData.BlockBegin;
 
   CodeData.Size = getCurr<uint8_t*>() - CodeData.BlockBegin;
@@ -788,16 +866,12 @@ CPUBackend::CompiledCode X86JITCore::CompileCode(uint64_t Entry, [[maybe_unused]
   return CodeData;
 }
 
-std::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread) {
-  return std::make_unique<X86JITCore>(ctx, Thread);
+fextl::unique_ptr<CPUBackend> CreateX86JITCore(FEXCore::Context::ContextImpl *ctx, FEXCore::Core::InternalThreadState *Thread) {
+  return fextl::make_unique<X86JITCore>(ctx, Thread);
 }
 
 CPUBackendFeatures GetX86JITBackendFeatures() {
   return CPUBackendFeatures { };
 }
 
-void InitializeX86JITSignalHandlers(FEXCore::Context::ContextImpl *CTX) {
-  X86JITCore::InitializeSignalHandlers(CTX);
-}
-
 }

External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h

@@ -9,18 +9,20 @@ $end_info$
 #include <FEXCore/IR/RegisterAllocationData.h>
 #include "Interface/Core/BlockSamplingData.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include "Interface/Core/ObjectCache/Relocations.h"
 
-#define XBYAK64
-#include <xbyak/xbyak.h>
-#include <xbyak/xbyak_util.h>
-
 using namespace Xbyak;
 
+#include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/CPUBackend.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/Utils/MathUtils.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/unordered_map.h>
+#include <FEXCore/fextl/vector.h>
+
 #include "Interface/IR/Passes/RegisterAllocationPass.h"
 
 #include <tuple>
@@ -55,7 +57,7 @@ public:
                       FEXCore::Core::InternalThreadState *Thread);
   ~X86JITCore() override;
 
-  [[nodiscard]] std::string GetName() override { return "JIT"; }
+  [[nodiscard]] fextl::string GetName() override { return "JIT"; }
 
   [[nodiscard]] CPUBackend::CompiledCode CompileCode(uint64_t Entry,
                                   FEXCore::IR::IRListView const *IR,
@@ -68,8 +70,6 @@ public:
 
   void ClearCache() override;
 
-  static void InitializeSignalHandlers(FEXCore::Context::ContextImpl *CTX);
-
   void ClearRelocations() override { Relocations.clear(); }
 
 private:
@@ -123,7 +123,7 @@ private:
 
     void PlaceNamedSymbolLiteral(NamedSymbolLiteralPair &Lit);
 
-    std::vector<FEXCore::CPU::Relocation> Relocations;
+    fextl::vector<FEXCore::CPU::Relocation> Relocations;
 
     ///< Relocation code loading
     bool ApplyRelocations(uint64_t GuestEntry, uint64_t CodeEntry, uint64_t CursorEntry, size_t NumRelocations, const char* EntryRelocations);
@@ -140,7 +140,7 @@ private:
   uint64_t Entry;
   CPUBackend::CompiledCode CodeData{};
 
-  std::unordered_map<IR::NodeID, Label> JumpTargets;
+  fextl::unordered_map<IR::NodeID, Label> JumpTargets;
   Xbyak::util::Cpu Features{};
 
   bool MemoryDebug = false;
@@ -151,7 +151,6 @@ private:
   constexpr static uint32_t NumGPRs = RA64.size(); // 4 is the minimum required for GPR ops
   constexpr static uint32_t NumXMMs = RAXMM.size();
   constexpr static uint32_t NumGPRPairs = RA64Pair.size();
-  constexpr static uint32_t RegisterCount = NumGPRs + NumXMMs + NumGPRPairs;
   constexpr static uint32_t RegisterClasses = 6;
 
   constexpr static uint64_t GPRBase = (0ULL << 32);
@@ -170,6 +169,7 @@ private:
 
   [[nodiscard]] bool IsFPR(IR::NodeID Node) const;
   [[nodiscard]] bool IsGPR(IR::NodeID Node) const;
+  [[nodiscard]] bool IsGPRPair(IR::NodeID Node) const;
 
   template<uint8_t RAType>
   [[nodiscard]] Xbyak::Reg GetSrc(IR::NodeID Node) const;
@@ -246,6 +246,7 @@ private:
   DEF_OP(Add);
   DEF_OP(Sub);
   DEF_OP(Neg);
+  DEF_OP(Abs);
   DEF_OP(Mul);
   DEF_OP(UMul);
   DEF_OP(Div);
@@ -314,6 +315,7 @@ private:
   DEF_OP(ValidateCode);
   DEF_OP(ThreadRemoveCodeEntry);
   DEF_OP(CPUID);
+  DEF_OP(XGETBV);
 
   ///< Conversion ops
   DEF_OP(VInsGPR);
@@ -344,7 +346,10 @@ private:
   DEF_OP(StoreFlag);
   DEF_OP(LoadMem);
   DEF_OP(StoreMem);
+  DEF_OP(VLoadVectorMasked);
+  DEF_OP(VStoreVectorMasked);
   DEF_OP(MemSet);
+  DEF_OP(MemCpy);
   DEF_OP(CacheLineClear);
   DEF_OP(CacheLineClean);
   DEF_OP(CacheLineZero);
@@ -450,6 +455,7 @@ private:
   DEF_OP(VUMull2);
   DEF_OP(VSMull2);
   DEF_OP(VUABDL);
+  DEF_OP(VUABDL2);
   DEF_OP(VTBL1);
   DEF_OP(VRev64);
 

External/FEXCore/Source/Interface/Core/JIT/x86_64/MemoryOps.cpp

@@ -6,7 +6,7 @@ $end_info$
 
 #include "Interface/Core/CPUID.h"
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/LogManager.h>
@@ -14,7 +14,6 @@ $end_info$
 #include <array>
 #include <stddef.h>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 
@@ -602,14 +601,22 @@ DEF_OP(LoadFlag) {
   auto Op = IROp->C<IR::IROp_LoadFlag>();
 
   auto Dst = GetDst<RA_64>(Node);
-  movzx(Dst, byte [STATE + (offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag)]);
+
+  if (Op->Flag == 24 /* NZCV */)
+    mov(Dst.cvt32(), dword [STATE + (offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag)]);
+  else
+    movzx(Dst, byte [STATE + (offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag)]);
 }
 
 DEF_OP(StoreFlag) {
   auto Op = IROp->C<IR::IROp_StoreFlag>();
 
   mov (rax, GetSrc<RA_64>(Op->Value.ID()));
-  mov(byte [STATE + (offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag)], al);
+
+  if (Op->Flag == 24 /* NZCV */)
+    mov(dword [STATE + (offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag)], eax);
+  else
+    mov(byte [STATE + (offsetof(FEXCore::Core::CPUState, flags[0]) + Op->Flag)], al);
 }
 
 Xbyak::RegExp X86JITCore::GenerateModRM(Xbyak::Reg Base, IR::OrderedNodeWrapper Offset, IR::MemOffsetType OffsetType, uint8_t OffsetScale) const {
@@ -766,6 +773,77 @@ DEF_OP(StoreMem) {
   }
 }
 
+DEF_OP(VLoadVectorMasked) {
+  const auto Op = IROp->C<IR::IROp_VLoadVectorMasked>();
+  const auto OpSize = IROp->Size;
+
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto ElementSize = IROp->ElementSize;
+
+  const auto Dst = GetDst(Node);
+  const auto Mask = GetSrc(Op->Mask.ID());
+
+  const Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
+  const auto MemPtr = GenerateModRM(MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
+
+  switch (ElementSize) {
+    case 4: {
+      if (Is256Bit) {
+        vmaskmovps(ToYMM(Dst), ToYMM(Mask), yword [MemPtr]);
+      } else {
+        vmaskmovps(Dst, Mask, xword [MemPtr]);
+      }
+      return;
+    }
+    case 8: {
+      if (Is256Bit) {
+        vmaskmovpd(ToYMM(Dst), ToYMM(Mask), yword [MemPtr]);
+      } else {
+        vmaskmovpd(Dst, Mask, xword [MemPtr]);
+      }
+      return;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled VLoadVectorMasked element size: {}", ElementSize);
+      return;
+  }
+}
+DEF_OP(VStoreVectorMasked) {
+  const auto Op = IROp->C<IR::IROp_VStoreVectorMasked>();
+  const auto OpSize = IROp->Size;
+
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+  const auto ElementSize = IROp->ElementSize;
+
+  const auto Data = GetDst(Op->Data.ID());
+  const auto Mask = GetSrc(Op->Mask.ID());
+
+  const Xbyak::Reg MemReg = GetSrc<RA_64>(Op->Addr.ID());
+  const auto MemPtr = GenerateModRM(MemReg, Op->Offset, Op->OffsetType, Op->OffsetScale);
+
+  switch (ElementSize) {
+    case 4: {
+      if (Is256Bit) {
+        vmaskmovps(yword [MemPtr], ToYMM(Mask), ToYMM(Data));
+      } else {
+        vmaskmovps(xword [MemPtr], Mask, Data);
+      }
+      return;
+    }
+    case 8: {
+      if (Is256Bit) {
+        vmaskmovpd(yword [MemPtr], ToYMM(Mask), ToYMM(Data));
+      } else {
+        vmaskmovpd(xword [MemPtr], Mask, Data);
+      }
+      return;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unhandled VStoreVectorMasked element size: {}", ElementSize);
+      return;
+  }
+}
+
 DEF_OP(MemSet) {
   const auto Op = IROp->C<IR::IROp_MemSet>();
 
@@ -791,6 +869,10 @@ DEF_OP(MemSet) {
   mov(rcx, Length);
   mov(rdi, MemReg);
 
+  if (!Op->Prefix.IsInvalid()) {
+    add(rdi, GetSrc<RA_64>(Op->Prefix.ID()));
+  }
+
   {
     mov(TMP3, Length);
     auto CalculateDest = [&]() {
@@ -854,6 +936,139 @@ DEF_OP(MemSet) {
   cld();
 }
 
+DEF_OP(MemCpy) {
+  const auto Op = IROp->C<IR::IROp_MemCpy>();
+
+  const int32_t Size = Op->Size;
+  const auto MemRegDest = GetSrc<RA_64>(Op->AddrDest.ID());
+  const auto MemRegSrc = GetSrc<RA_64>(Op->AddrSrc.ID());
+
+  const auto Length = GetSrc<RA_64>(Op->Length.ID());
+  const auto Direction = GetSrc<RA_64>(Op->Direction.ID());
+
+  // If Direction == 0 then:
+  //   MemRegDest is incremented (by size)
+  //   MemRegSrc is incremented (by size)
+  // else:
+  //   MemRegDest is decremented (by size)
+  //   MemRegSrc is decremented (by size)
+  //
+  // Counter is decremented regardless.
+
+  // TMP1 = Length
+  // TMP2 = Dest
+  // TMP3 = Src
+  // TMP4 = Temp value
+  mov(TMP1, Length);
+  mov(TMP2, MemRegDest);
+  mov(TMP3, MemRegSrc);
+  if (!Op->PrefixDest.IsInvalid()) {
+    add(TMP2, GetSrc<RA_64>(Op->PrefixDest.ID()));
+  }
+  if (!Op->PrefixSrc.IsInvalid()) {
+    add(TMP3, GetSrc<RA_64>(Op->PrefixSrc.ID()));
+  }
+
+  auto Dst = GetSrcPair<RA_64>(Node);
+  Label Done;
+  Label BackwardImpl;
+  cmp(Direction, 0);
+  jne(BackwardImpl);
+
+  // Emit forward direction memcpy then backward direction memcpy.
+  for (int32_t Direction :  { 1, -1 }) {
+    Label DoneInternal;
+    Label AgainInternal;
+
+    L(AgainInternal);
+    cmp(TMP1, 0);
+    je(DoneInternal);
+
+    {
+      switch (Size) {
+        case 1:
+          movzx(TMP4, byte [TMP3]);
+          mov(byte [TMP2], TMP4.cvt8());
+          break;
+        case 2:
+          movzx(TMP4, word [TMP3]);
+          mov(word [TMP2], TMP4.cvt16());
+          break;
+        case 4:
+          mov(TMP4.cvt32(), dword [TMP3]);
+          mov(dword [TMP2], TMP4.cvt32());
+          break;
+        case 8:
+          mov(TMP4, qword [TMP3]);
+          mov(qword [TMP2], TMP4);
+          break;
+        default:
+          LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+          break;
+      }
+    }
+
+    if (Direction == 1) {
+      // Incrementing pointers
+      add(TMP2, Size);
+      add(TMP3, Size);
+    }
+    else {
+      // Decrementing pointers
+      sub(TMP2, Size);
+      sub(TMP3, Size);
+    }
+
+    // Decrement counter by one
+    sub(TMP1, 1);
+
+    jmp(AgainInternal);
+    L(DoneInternal);
+
+    // Pointer math using source pointers and length.
+    mov(TMP3, Length);
+    switch (Size) {
+      case 1:
+        break;
+      case 2:
+        shl(TMP3, 1);
+        break;
+      case 4:
+        shl(TMP3, 2);
+        break;
+      case 8:
+        shl(TMP3, 3);
+        break;
+      default:
+        LOGMAN_MSG_A_FMT("Unhandled {} size: {}", __func__, Size);
+        break;
+    }
+
+    // Needs to use temporaries just in case of overwrite
+    mov(TMP1, MemRegDest);
+    mov(TMP2, MemRegSrc);
+
+    mov(Dst.first, TMP1);
+    mov(Dst.second, TMP2);
+
+    if (Direction == 1) {
+      // Incrementing pointers
+      add(Dst.first, TMP3);
+      add(Dst.second, TMP3);
+
+      jmp(Done);
+      L(BackwardImpl);
+    }
+    else {
+      // Decrementing pointers
+      sub(Dst.first, TMP3);
+      sub(Dst.second, TMP3);
+    }
+  }
+
+  L(Done);
+}
+
 DEF_OP(CacheLineClear) {
   auto Op = IROp->C<IR::IROp_CacheLineClear>();
 
@@ -908,7 +1123,10 @@ void X86JITCore::RegisterMemoryHandlers() {
   REGISTER_OP(STOREMEM,            StoreMem);
   REGISTER_OP(LOADMEMTSO,          LoadMem);
   REGISTER_OP(STOREMEMTSO,         StoreMem);
+  REGISTER_OP(VLOADVECTORMASKED,   VLoadVectorMasked);
+  REGISTER_OP(VSTOREVECTORMASKED,  VStoreVectorMasked);
   REGISTER_OP(MEMSET,              MemSet);
+  REGISTER_OP(MEMCPY,              MemCpy);
   REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
   REGISTER_OP(CACHELINECLEAN,      CacheLineClean);
   REGISTER_OP(CACHELINEZERO,       CacheLineZero);

External/FEXCore/Source/Interface/Core/JIT/x86_64/MiscOps.cpp

@@ -6,6 +6,7 @@ $end_info$
 
 #include "Interface/Context/Context.h"
 #include "Interface/Core/Dispatcher/Dispatcher.h"
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include "Interface/Core/JIT/x86_64/JITClass.h"
 #include "FEXCore/Debug/InternalThreadState.h"
 
@@ -16,7 +17,6 @@ $end_info$
 #include <array>
 #include <stddef.h>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 #define DEF_OP(x) void X86JITCore::Op_##x(IR::IROp_Header *IROp, IR::NodeID Node)
@@ -43,6 +43,7 @@ DEF_OP(Fence) {
   }
 }
 
+#ifndef _WIN32
 DEF_OP(Break) {
   auto Op = IROp->C<IR::IROp_Break>();
 
@@ -79,6 +80,11 @@ DEF_OP(Break) {
     break;
   }
 }
+#else
+DEF_OP(Break) {
+  ERROR_AND_DIE_FMT("Unsupported");
+}
+#endif
 
 DEF_OP(GetRoundingMode) {
   auto Dst = GetDst<RA_32>(Node);

External/FEXCore/Source/Interface/Core/JIT/x86_64/MoveOps.cpp

@@ -5,7 +5,7 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/IR/IR.h>
 

External/FEXCore/Source/Interface/Core/JIT/x86_64/VectorOps.cpp

@@ -5,14 +5,13 @@ $end_info$
 */
 
 #include "Interface/Core/JIT/x86_64/JITClass.h"
-
+#include "Interface/Core/Dispatcher/X86Dispatcher.h"
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/Utils/LogManager.h>
 
 #include <array>
 #include <stddef.h>
 #include <stdint.h>
-#include <xbyak/xbyak.h>
 
 namespace FEXCore::CPU {
 
@@ -2726,11 +2725,71 @@ DEF_OP(VFCMPUNO) {
 }
 
 DEF_OP(VUShl) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
+  const auto Op = IROp->C<IR::IROp_VUShl>();
+  const auto OpSize = IROp->Size;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto ElementSize = IROp->ElementSize;
+  LOGMAN_THROW_AA_FMT(ElementSize == 4 || ElementSize == 8,
+                      "VUShl only supports 32-bit and 64-bit elements");
+
+  const auto Dst = GetDst(Node);
+  const auto ShiftVector = GetSrc(Op->ShiftVector.ID());
+  const auto Vector = GetSrc(Op->Vector.ID());
+
+  switch (ElementSize) {
+  case 4:
+    if (Is256Bit) {
+      vpsllvd(ToYMM(Dst), ToYMM(Vector), ToYMM(ShiftVector));
+    } else {
+      vpsllvd(Dst, Vector, ShiftVector);
+    }
+    return;
+  case 8:
+    if (Is256Bit) {
+      vpsllvq(ToYMM(Dst), ToYMM(Vector), ToYMM(ShiftVector));
+    } else {
+      vpsllvq(Dst, Vector, ShiftVector);
+    }
+    return;
+  default:
+    LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
+    return;
+  }
 }
 
 DEF_OP(VUShr) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
+  const auto Op = IROp->C<IR::IROp_VUShr>();
+  const auto OpSize = IROp->Size;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto ElementSize = IROp->ElementSize;
+  LOGMAN_THROW_AA_FMT(ElementSize == 4 || ElementSize == 8,
+                      "VUShr only supports 32-bit and 64-bit elements");
+
+  const auto Dst = GetDst(Node);
+  const auto ShiftVector = GetSrc(Op->ShiftVector.ID());
+  const auto Vector = GetSrc(Op->Vector.ID());
+
+  switch (ElementSize) {
+  case 4:
+    if (Is256Bit) {
+      vpsrlvd(ToYMM(Dst), ToYMM(Vector), ToYMM(ShiftVector));
+    } else {
+      vpsrlvd(Dst, Vector, ShiftVector);
+    }
+    return;
+  case 8:
+    if (Is256Bit) {
+      vpsrlvq(ToYMM(Dst), ToYMM(Vector), ToYMM(ShiftVector));
+    } else {
+      vpsrlvq(Dst, Vector, ShiftVector);
+    }
+    return;
+  default:
+    LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
+    return;
+  }
 }
 
 DEF_OP(VSShr) {
@@ -4308,6 +4367,93 @@ DEF_OP(VUABDL) {
   }
 }
 
+DEF_OP(VUABDL2) {
+  const auto Op = IROp->C<IR::IROp_VUABDL2>();
+  const auto OpSize = IROp->Size;
+
+  const auto ElementSize = Op->Header.ElementSize;
+  const auto Is256Bit = OpSize == Core::CPUState::XMM_AVX_REG_SIZE;
+
+  const auto Dst = GetDst(Node);
+  const auto Vector1 = GetSrc(Op->Vector1.ID());
+  const auto Vector2 = GetSrc(Op->Vector2.ID());
+
+  switch (ElementSize) {
+    case 2: {
+      vpxor(xmm15, xmm15, xmm15);
+      vpxor(xmm14, xmm14, xmm14);
+
+      if (Is256Bit) {
+        vextracti128(xmm15, ToYMM(Vector1), 1);
+        vextracti128(xmm14, ToYMM(Vector2), 1);
+
+        vpxor(xmm12, xmm12, xmm12);
+        vpxor(xmm13, xmm13, xmm13);
+        vpxor(Dst, Dst, Dst);
+
+        // Bottom half
+        vpunpcklbw(xmm13, xmm15, xmm13);
+        vpunpcklbw(xmm12, xmm14, xmm12);
+
+        // Top half
+        vpunpckhbw(xmm15, xmm15, Dst);
+        vpunpckhbw(xmm14, xmm14, Dst);
+
+        // Reinsert
+        vinserti128(ymm13, ymm13, xmm15, 1);
+        vinserti128(ymm12, ymm12, xmm14, 1);
+
+        vpsubw(ToYMM(Dst), ymm12, ymm13);
+        vpabsw(ToYMM(Dst), ToYMM(Dst));
+      } else {
+        vpunpckhbw(xmm15, Vector1, xmm15);
+        vpunpckhbw(xmm14, Vector2, xmm14);
+        vpsubw(Dst, xmm14, xmm15);
+        vpabsw(Dst, Dst);
+      }
+      break;
+    }
+    case 4: {
+      vpxor(xmm15, xmm15, xmm15);
+      vpxor(xmm14, xmm14, xmm14);
+
+      if (Is256Bit) {
+        vextracti128(xmm15, ToYMM(Vector1), 1);
+        vextracti128(xmm14, ToYMM(Vector2), 1);
+
+        vpxor(xmm12, xmm12, xmm12);
+        vpxor(xmm13, xmm13, xmm13);
+        vpxor(Dst, Dst, Dst);
+
+        // Bottom half
+        vpunpcklwd(xmm13, xmm15, xmm13);
+        vpunpcklwd(xmm12, xmm14, xmm12);
+
+        // Top half
+        vpunpckhwd(xmm15, xmm15, Dst);
+        vpunpckhwd(xmm14, xmm14, Dst);
+
+        // Reinsert
+        vinserti128(ymm13, ymm13, xmm15, 1);
+        vinserti128(ymm12, ymm12, xmm14, 1);
+
+        vpsubd(ToYMM(Dst), ymm12, ymm13);
+        vpabsd(ToYMM(Dst), ToYMM(Dst));
+      } else {
+        vpunpckhwd(xmm15, Vector1, xmm15);
+        vpunpckhwd(xmm14, Vector2, xmm14);
+        vpsubd(Dst, xmm14, xmm15);
+        vpabsd(Dst, Dst);
+      }
+      break;
+    }
+    default:
+      LOGMAN_MSG_A_FMT("Unknown Element Size: {}", ElementSize);
+      break;
+  }
+}
+
+
 DEF_OP(VTBL1) {
   const auto Op = IROp->C<IR::IROp_VTBL1>();
   const auto OpSize = IROp->Size;
@@ -4550,6 +4696,7 @@ void X86JITCore::RegisterVectorHandlers() {
   REGISTER_OP(VUMULL2,           VUMull2);
   REGISTER_OP(VSMULL2,           VSMull2);
   REGISTER_OP(VUABDL,            VUABDL);
+  REGISTER_OP(VUABDL2,           VUABDL2);
   REGISTER_OP(VTBL1,             VTBL1);
   REGISTER_OP(VREV64,            VRev64);
 #undef REGISTER_OP

External/FEXCore/Source/Interface/Core/LookupCache.cpp

@@ -11,15 +11,15 @@ $end_info$
 #include "Interface/Context/Context.h"
 #include "Interface/Core/LookupCache.h"
 
-#include <sys/mman.h>
-
 namespace FEXCore {
 LookupCache::LookupCache(FEXCore::Context::ContextImpl *CTX)
-  : ctx {CTX} {
+  : BlockLinks_mbr { fextl::pmr::get_default_resource() }
+  , ctx {CTX} {
 
   TotalCacheSize = ctx->Config.VirtualMemSize / 4096 * 8 + CODE_SIZE + L1_SIZE;
+  BlockLinks_pma = fextl::make_unique<std::pmr::polymorphic_allocator<std::byte>>(&BlockLinks_mbr);
   // Setup our PMR map.
-  BlockLinks = BlockLinks_pma.new_object<BlockLinksMapType>();
+  BlockLinks = BlockLinks_pma->new_object<BlockLinksMapType>();
 
   // Block cache ends up looking like this
   // PageMemoryMap[VirtualMemoryRegion >> 12]
@@ -33,7 +33,7 @@ LookupCache::LookupCache(FEXCore::Context::ContextImpl *CTX)
   // Allocate a region of memory that we can use to back our block pointers
   // We need one pointer per page of virtual memory
   // At 64GB of virtual memory this will allocate 128MB of virtual memory space
-  PagePointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::mmap(nullptr, TotalCacheSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
+  PagePointer = reinterpret_cast<uintptr_t>(FEXCore::Allocator::VirtualAlloc(TotalCacheSize));
 
   // Allocate our memory backing our pages
   // We need 32KB per guest page (One pointer per byte)
@@ -52,7 +52,7 @@ LookupCache::LookupCache(FEXCore::Context::ContextImpl *CTX)
 
 LookupCache::~LookupCache() {
   const size_t TotalCacheSize = ctx->Config.VirtualMemSize / 4096 * 8 + CODE_SIZE + L1_SIZE;
-  FEXCore::Allocator::munmap(reinterpret_cast<void*>(PagePointer), TotalCacheSize);
+  FEXCore::Allocator::VirtualFree(reinterpret_cast<void*>(PagePointer), TotalCacheSize);
 
   // No need to free BlockLinks map.
   // These will get freed when their memory allocators are deallocated.
@@ -62,7 +62,7 @@ void LookupCache::ClearL2Cache() {
   std::lock_guard<std::recursive_mutex> lk(WriteLock);
   // Clear out the page memory
   // PagePointer and PageMemory are sequential with each other. Clear both at once.
-  madvise(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8 + CODE_SIZE, MADV_DONTNEED);
+  FEXCore::Allocator::VirtualDontNeed(reinterpret_cast<void*>(PagePointer), ctx->Config.VirtualMemSize / 4096 * 8 + CODE_SIZE);
   AllocateOffset = 0;
 }
 
@@ -70,11 +70,9 @@ void LookupCache::ClearCache() {
   std::lock_guard<std::recursive_mutex> lk(WriteLock);
 
   // Clear L1 and L2 by clearing the full cache.
-  madvise(reinterpret_cast<void*>(PagePointer), TotalCacheSize, MADV_DONTNEED);
-  // Clear the BlockLinks allocator which frees the BlockLinks map implicitly.
-  BlockLinks_mbr.release();
+  FEXCore::Allocator::VirtualDontNeed(reinterpret_cast<void*>(PagePointer), TotalCacheSize);
   // Allocate a new pointer from the BlockLinks pma again.
-  BlockLinks = BlockLinks_pma.new_object<BlockLinksMapType>();
+  BlockLinks = BlockLinks_pma->new_object<BlockLinksMapType>();
   // All code is gone, clear the block list
   BlockList.clear();
 }

External/FEXCore/Source/Interface/Core/LookupCache.h

@@ -1,22 +1,22 @@
 #pragma once
 #include "Interface/Context/Context.h"
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/memory_resource.h>
+#include <FEXCore/fextl/robin_map.h>
+#include <FEXCore/fextl/vector.h>
+#include <FEXCore/fextl/memory_resource.h>
 
 #include <cstdint>
 #include <functional>
-#include <map>
-#include <memory_resource>
 #include <stddef.h>
 #include <utility>
-#include <vector>
 #include <mutex>
-#include <tsl/robin_map.h>
 
 namespace FEXCore {
 
 class LookupCache {
 public:
-
   struct LookupCacheEntry {
     uintptr_t HostCode;
     uintptr_t GuestCode;
@@ -67,7 +67,7 @@ public:
     return 0;
   }
 
-  std::map<uint64_t, std::vector<uint64_t>> CodePages;
+  fextl::map<uint64_t, fextl::vector<uint64_t>> CodePages;
 
   // Appends Block {Address} to CodePages [Start, Start + Length)
   // Returns true if new pages are marked as containing code
@@ -168,8 +168,6 @@ public:
 
 private:
   void CacheBlockMapping(uint64_t Address, uintptr_t HostCode) {
-    std::lock_guard<std::recursive_mutex> lk(WriteLock);
-
     // Do L1
     auto &L1Entry = reinterpret_cast<LookupCacheEntry*>(L1Pointer)[Address & L1_ENTRIES_MASK];
     L1Entry.GuestCode = Address;
@@ -245,10 +243,10 @@ private:
   // This makes `BlockLinks` look like a raw pointer that could memory leak, but since it is backed by the MBR, it won't.
   std::pmr::monotonic_buffer_resource BlockLinks_mbr;
   using BlockLinksMapType = std::pmr::map<BlockLinkTag, std::function<void()>>;
-  std::pmr::polymorphic_allocator<std::byte> BlockLinks_pma {&BlockLinks_mbr};
+  fextl::unique_ptr<std::pmr::polymorphic_allocator<std::byte>> BlockLinks_pma;
   BlockLinksMapType *BlockLinks;
 
-  tsl::robin_map<uint64_t, uint64_t> BlockList;
+  fextl::robin_map<uint64_t, uint64_t> BlockList;
 
   size_t TotalCacheSize;
 

External/FEXCore/Source/Interface/Core/ObjectCache/CodeObjectSerializationConfig.h

@@ -1,12 +1,16 @@
 #pragma once
 
+#include <FEXCore/Utils/CompilerDefs.h>
+
 #include <cstdint>
 
 namespace FEXCore::CodeSerialize {
   // If any of the config options mismatch on load then the cache won't be used
   // Any of these will result in codegen changes
-  struct CodeObjectSerializationConfig {
-		// Cookie in the header of the file, isn't part of the config hash
+  struct
+  FEX_PACKED
+  CodeObjectSerializationConfig {
+    // Cookie in the header of the file, isn't part of the config hash
     uint64_t Cookie{};
 
     // Instructions per block configuration
@@ -16,41 +20,45 @@ namespace FEXCore::CodeSerialize {
     unsigned Arch : 4;
 
     // Multiblock enabled
-    bool MultiBlock : 1;
+    unsigned MultiBlock : 1;
+
+    // Hardware TSO enabled
+    unsigned HardwareTSOEnabled : 1;
 
     // TSO enabled
-    bool TSOEnabled : 1;
+    unsigned TSOEnabled : 1;
 
     // ABI local flag unsafe optimization
-    bool ABILocalFlags : 1;
+    unsigned ABILocalFlags : 1;
 
     // ABI no PF unsafe optimization
-    bool ABINoPF : 1;
+    unsigned ABINoPF : 1;
 
     // Static register allocation enabled
-    bool SRA : 1;
+    unsigned SRA : 1;
 
     // Paranoid TSO mode enabled
-    bool ParanoidTSO : 1;
+    unsigned ParanoidTSO : 1;
 
     // Guest code execution mode (We don't support live mode switch)
-    bool Is64BitMode : 1;
+    unsigned Is64BitMode : 1;
 
     // SMC checks style
     unsigned SMCChecks : 2;
 
     // x87 reduced precision
-    bool x87ReducedPrecision : 1;
+    unsigned x87ReducedPrecision : 1;
 
     // Padding to remove uninitialized data warning from asan
     // Shows remaining amount of bits available for config
-    unsigned _Pad : 18;
+    unsigned _Pad : 17;
 
     bool operator==(CodeObjectSerializationConfig const &other) const {
       return Cookie == other.Cookie &&
         MaxInstPerBlock == other.MaxInstPerBlock &&
         Arch == other.Arch &&
         MultiBlock == other.MultiBlock &&
+        HardwareTSOEnabled == other.HardwareTSOEnabled &&
         TSOEnabled == other.TSOEnabled &&
         ABILocalFlags == other.ABILocalFlags &&
         ABINoPF == other.ABINoPF &&
@@ -67,6 +75,7 @@ namespace FEXCore::CodeSerialize {
       Hash <<= 32; Hash |= other.MaxInstPerBlock;
       Hash <<= 1;  Hash |= other.Arch;
       Hash <<= 1;  Hash |= other.MultiBlock;
+      Hash <<= 1;  Hash |= other.HardwareTSOEnabled;
       Hash <<= 1;  Hash |= other.TSOEnabled;
       Hash <<= 1;  Hash |= other.ABILocalFlags;
       Hash <<= 1;  Hash |= other.ABINoPF;
@@ -79,6 +88,6 @@ namespace FEXCore::CodeSerialize {
     }
   };
 
-	static_assert(sizeof(CodeObjectSerializationConfig) == 16, "Size changed");
+  static_assert(sizeof(CodeObjectSerializationConfig) == 16, "Size changed");
   static_assert((sizeof(CodeObjectSerializationConfig) - sizeof(uint64_t)) == 8, "Config size exceeded 64its. Need to change how the hash is generated!");
 }

External/FEXCore/Source/Interface/Core/ObjectCache/JobHandling.cpp

@@ -2,25 +2,24 @@
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
 
 #include <FEXCore/Config/Config.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXHeaderUtils/Filesystem.h>
 
 #include <fcntl.h>
-#include <filesystem>
-#include <memory>
-#include <string>
-#include <sys/uio.h>
-#include <sys/mman.h>
 #include <xxhash.h>
 
 namespace FEXCore::CodeSerialize {
-  void AsyncJobHandler::AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const std::string &filename) {
+  void AsyncJobHandler::AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const fextl::string &filename) {
+#ifndef _WIN32
     // This function adds a named region *JOB* to our named region handler
     // This needs to be as fast as possible to keep out of the way of the JIT
 
-    auto BaseFilename = std::filesystem::path(filename).filename().string();
+    const fextl::string BaseFilename = FHU::Filesystem::GetFilename(filename);
 
     if (!BaseFilename.empty()) {
       // Create a new entry that once set up will be put in to our section object map
-      auto Entry = std::make_unique<CodeRegionEntry>(
+      auto Entry = fextl::make_unique<CodeRegionEntry>(
         Base,
         Size,
         Offset,
@@ -77,12 +76,14 @@ namespace FEXCore::CodeSerialize {
       // Tell the async thread that it has work to do
       CodeObjectCacheService->NotifyWork();
     }
+#endif
   }
 
   void AsyncJobHandler::AsyncRemoveNamedRegionJob(uintptr_t Base, uintptr_t Size) {
+#ifndef _WIN32
     // Removing a named region through the job system
     // We need to find the entry that we are deleting first
-    std::unique_ptr<CodeRegionEntry> EntryPointer;
+    fextl::unique_ptr<CodeRegionEntry> EntryPointer;
     {
       std::unique_lock lk {CodeObjectCacheService->GetEntryMapMutex()};
 
@@ -119,9 +120,10 @@ namespace FEXCore::CodeSerialize {
       // Tell the async thread that it has work to do
       CodeObjectCacheService->NotifyWork();
     }
+#endif
   }
 
-  void AsyncJobHandler::AsyncAddSerializationJob(std::unique_ptr<SerializationJobData> Data) {
+  void AsyncJobHandler::AsyncAddSerializationJob(fextl::unique_ptr<SerializationJobData> Data) {
     // XXX: Actually add serialization job
   }
 }

External/FEXCore/Source/Interface/Core/ObjectCache/NamedRegionObjectHandler.cpp

@@ -1,7 +1,9 @@
 #include "Interface/Context/Context.h"
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
 
-#include <FEXCore/Config/Config.h>
+
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/string.h>
 
 namespace FEXCore::CodeSerialize {
   NamedRegionObjectHandler::NamedRegionObjectHandler(FEXCore::Context::ContextImpl *ctx) {
@@ -23,14 +25,14 @@ namespace FEXCore::CodeSerialize {
     DefaultSerializationConfig.x87ReducedPrecision = ctx->Config.x87ReducedPrecision;
   }
 
-  void NamedRegionObjectHandler::AddNamedRegionObject(CodeRegionMapType::iterator Entry, const std::string &base_filename, const std::string &filename, bool Executable) {
+  void NamedRegionObjectHandler::AddNamedRegionObject(CodeRegionMapType::iterator Entry, const fextl::string &base_filename, const fextl::string &filename, bool Executable) {
     // XXX: Add named region objects
 
     // XXX: Until entry loading is complete just claim it is loaded
     Entry->second->NamedJobRefCountMutex.unlock();
   }
 
-  void NamedRegionObjectHandler::RemoveNamedRegionObject(uintptr_t Base, uintptr_t Size, std::unique_ptr<CodeRegionEntry> Entry) {
+  void NamedRegionObjectHandler::RemoveNamedRegionObject(uintptr_t Base, uintptr_t Size, fextl::unique_ptr<CodeRegionEntry> Entry) {
     // XXX: Remove named region objects
 
     // XXX: Until entry loading is complete just claim it is loaded
@@ -40,7 +42,7 @@ namespace FEXCore::CodeSerialize {
   void NamedRegionObjectHandler::HandleNamedRegionObjectJobs() {
     // Walk through all of our jobs sequentially until the work queue is empty
     while (NamedWorkQueueJobs.load()) {
-      std::unique_ptr<AsyncJobHandler::NamedRegionWorkItem> WorkItem;
+      fextl::unique_ptr<AsyncJobHandler::NamedRegionWorkItem> WorkItem;
 
       {
         // Lock the work queue mutex for a short moment and grab an item from the list

External/FEXCore/Source/Interface/Core/ObjectCache/ObjectCacheService.cpp

@@ -1,8 +1,8 @@
 #include "Interface/Core/ObjectCache/ObjectCacheService.h"
 
 #include <FEXCore/Config/Config.h>
-
-#include <memory>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/Utils/Threads.h>
 
 namespace {
   static void* ThreadHandler(void *Arg) {
@@ -38,13 +38,13 @@ namespace FEXCore::CodeSerialize {
 
   void CodeObjectSerializeService::Initialize() {
     // Add a canary so we don't crash on empty map iterator handling
-    auto it = AddressToEntryMap.insert_or_assign(~0ULL, std::make_unique<CodeRegionEntry>());
-		UnrelocatedAddressToEntryMap.insert_or_assign(~0ULL, it.first->second.get());
+    auto it = AddressToEntryMap.insert_or_assign(~0ULL, fextl::make_unique<CodeRegionEntry>());
+    UnrelocatedAddressToEntryMap.insert_or_assign(~0ULL, it.first->second.get());
 
-		uint64_t OldMask = FEXCore::Threads::SetSignalMask(~0ULL);
-		WorkerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
+    uint64_t OldMask = FEXCore::Threads::SetSignalMask(~0ULL);
+    WorkerThread = FEXCore::Threads::Thread::Create(ThreadHandler, this);
     FEXCore::Threads::SetSignalMask(OldMask);
-	}
+  }
 
   void CodeObjectSerializeService::DoCodeRegionClosure(uint64_t Base, CodeRegionEntry *it) {
     if (Base == ~0ULL) {
@@ -61,8 +61,7 @@ namespace FEXCore::CodeSerialize {
 
   void CodeObjectSerializeService::ExecutionThread() {
     // Set our thread name so we can see its relation
-    char ThreadName[16] = "ObjectCodeSeri\0";
-    pthread_setname_np(pthread_self(), ThreadName);
+    FEXCore::Threads::SetThreadName("ObjectCodeSeri\0");
     while (WorkerThreadShuttingDown.load() != true) {
       // Wait for work
       WorkAvailable.Wait();
@@ -81,5 +80,5 @@ namespace FEXCore::CodeSerialize {
     // Safely clear our maps now
     AddressToEntryMap.clear();
     UnrelocatedAddressToEntryMap.clear();
-	}
+  }
 }

External/FEXCore/Source/Interface/Core/ObjectCache/ObjectCacheService.h

@@ -6,13 +6,14 @@
 
 #include <FEXCore/Utils/Event.h>
 #include <FEXCore/Utils/Threads.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/memory.h>
+#include <FEXCore/fextl/queue.h>
+#include <FEXCore/fextl/robin_map.h>
+#include <FEXCore/fextl/string.h>
+#include <FEXCore/fextl/vector.h>
 
-#include <map>
-#include <memory>
 #include <shared_mutex>
-#include <string>
-#include <vector>
-#include <tsl/robin_map.h>
 
 namespace FEXCore::CodeSerialize {
   // XXX: Does this need to be signal safe?
@@ -66,13 +67,13 @@ namespace FEXCore::CodeSerialize {
       uint64_t Offset{};
 
       // Filename of the object
-      std::string Filename{};
+      fextl::string Filename{};
 
       CodeObjectSerializationHeader EntryHeader{};
     /**  @} */
 
     // The filename of the object cache for this entry
-    std::string ObjectEntrySourceFilename{};
+    fextl::string ObjectEntrySourceFilename{};
 
     // In the case of file corruption that we can detect, we can disable serialization early for an entry
     // We should be resiliant to corruption but things happen
@@ -105,12 +106,12 @@ namespace FEXCore::CodeSerialize {
         char *CodeData{};
         size_t FileSize{};
 
-        std::vector<CodeObjectFileSection> FileCodeSections;
+        fextl::vector<CodeObjectFileSection> FileCodeSections;
       /**  @} */
 
       // This per section map takes the most time to load and needs to be quick
       // This is the map of all code segments for this entry
-      tsl::robin_map<uint64_t, CodeObjectFileSection*> SectionLookupMap{};
+      fextl::robin_map<uint64_t, CodeObjectFileSection*> SectionLookupMap{};
     /**  @} */
 
     // Default initialization
@@ -120,7 +121,7 @@ namespace FEXCore::CodeSerialize {
     CodeRegionEntry(uint64_t Base,
       uint64_t Size,
       uint64_t Offset,
-      std::string const &Filename,
+      fextl::string const &Filename,
       CodeObjectSerializationHeader const &DefaultHeader)
       : Base {Base}
       , Size {Size}
@@ -131,8 +132,8 @@ namespace FEXCore::CodeSerialize {
   };
 
   // Map type must use an interator that isn't invalidation on erase/insert
-  using CodeRegionMapType = std::map<uint64_t, std::unique_ptr<CodeRegionEntry>>;
-  using CodeRegionPtrMapType = std::map<uint64_t, CodeRegionEntry*>;
+  using CodeRegionMapType = fextl::map<uint64_t, fextl::unique_ptr<CodeRegionEntry>>;
+  using CodeRegionPtrMapType = fextl::map<uint64_t, CodeRegionEntry*>;
 
   class NamedRegionObjectHandler;
   class CodeObjectSerializeService;
@@ -160,7 +161,7 @@ namespace FEXCore::CodeSerialize {
 
         // These are the reolocations for this serialization job
         // Relatively small number of entries most of the time
-        std::vector<FEXCore::CPU::Relocation> Relocations;
+        fextl::vector<FEXCore::CPU::Relocation> Relocations;
 
         /**
          * @name Objects filled in from the Code Object Serialization service when a job is added
@@ -186,9 +187,9 @@ namespace FEXCore::CodeSerialize {
       /**
        * @name Async job submission functions
        * @{ */
-        void AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const std::string &filename);
+        void AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const fextl::string &filename);
         void AsyncRemoveNamedRegionJob(uintptr_t Base, uintptr_t Size);
-        void AsyncAddSerializationJob(std::unique_ptr<SerializationJobData> Data);
+        void AsyncAddSerializationJob(fextl::unique_ptr<SerializationJobData> Data);
       /**  @} */
 
       /**
@@ -219,22 +220,22 @@ namespace FEXCore::CodeSerialize {
 
         class WorkItemAddNamedRegion : public NamedRegionWorkItem {
           public:
-            WorkItemAddNamedRegion(const std::string &base, const std::string &filename, bool executable, CodeRegionMapType::iterator entry)
+            WorkItemAddNamedRegion(const fextl::string &base, const fextl::string &filename, bool executable, CodeRegionMapType::iterator entry)
               : NamedRegionWorkItem {NamedRegionJobType::JOB_ADD_NAMED_REGION}
               , BaseFilename {base}
               , Filename {filename}
               , Executable {executable}
               , Entry {entry}
               {}
-            const std::string BaseFilename;
-            const std::string Filename;
+            const fextl::string BaseFilename;
+            const fextl::string Filename;
             bool Executable;
             CodeRegionMapType::iterator Entry;
         };
 
         class WorkItemRemoveNamedRegion : public NamedRegionWorkItem {
           public:
-            WorkItemRemoveNamedRegion(uint64_t base, uint64_t size, std::unique_ptr<CodeRegionEntry> entry)
+            WorkItemRemoveNamedRegion(uint64_t base, uint64_t size, fextl::unique_ptr<CodeRegionEntry> entry)
               : NamedRegionWorkItem {NamedRegionJobType::JOB_REMOVE_NAMED_REGION}
               , Base {base}
               , Size {size}
@@ -242,7 +243,7 @@ namespace FEXCore::CodeSerialize {
 
             uint64_t Base;
             uint64_t Size;
-            std::unique_ptr<CodeRegionEntry> Entry;
+            fextl::unique_ptr<CodeRegionEntry> Entry;
         };
       /**  @} */
 
@@ -281,9 +282,9 @@ namespace FEXCore::CodeSerialize {
        *
        * This adds the job that will do the loading of file resources and data tracking.
        */
-      void AsyncAddNamedRegionWorkItem(const std::string &base, const std::string &filename, bool executable, CodeRegionMapType::iterator entry) {
+      void AsyncAddNamedRegionWorkItem(const fextl::string &base, const fextl::string &filename, bool executable, CodeRegionMapType::iterator entry) {
         std::unique_lock lk {NamedWorkQueueMutex};
-        WorkQueue.emplace(std::make_unique<AsyncJobHandler::WorkItemAddNamedRegion> (
+        WorkQueue.emplace(fextl::make_unique<AsyncJobHandler::WorkItemAddNamedRegion> (
           base,
           filename,
           executable,
@@ -292,9 +293,9 @@ namespace FEXCore::CodeSerialize {
         ++NamedWorkQueueJobs;
       }
 
-      void AsyncRemoveNamedRegionWorkItem(uint64_t Base, uint64_t Size, std::unique_ptr<CodeRegionEntry> Entry) {
+      void AsyncRemoveNamedRegionWorkItem(uint64_t Base, uint64_t Size, fextl::unique_ptr<CodeRegionEntry> Entry) {
         std::unique_lock lk {NamedWorkQueueMutex};
-        WorkQueue.emplace(std::make_unique<AsyncJobHandler::WorkItemRemoveNamedRegion> (
+        WorkQueue.emplace(fextl::make_unique<AsyncJobHandler::WorkItemRemoveNamedRegion> (
           Base,
           Size,
           std::move(Entry)
@@ -321,13 +322,13 @@ namespace FEXCore::CodeSerialize {
       // The job queue itself
       // Jobs get consumed as a FIFO
       // Jobs always get appended to the end
-      std::queue<std::unique_ptr<AsyncJobHandler::NamedRegionWorkItem>> WorkQueue{};
+      fextl::queue<fextl::unique_ptr<AsyncJobHandler::NamedRegionWorkItem>> WorkQueue{};
 
       /**
        * @name Named Region object handling
        * @{ */
-        void AddNamedRegionObject(CodeRegionMapType::iterator Entry, const std::string &base_filename, const std::string &filename, bool Executable);
-        void RemoveNamedRegionObject(uintptr_t Base, uintptr_t Size, std::unique_ptr<CodeRegionEntry> Entry);
+        void AddNamedRegionObject(CodeRegionMapType::iterator Entry, const fextl::string &base_filename, const fextl::string &filename, bool Executable);
+        void RemoveNamedRegionObject(uintptr_t Base, uintptr_t Size, fextl::unique_ptr<CodeRegionEntry> Entry);
       /**  @} */
   };
 
@@ -365,7 +366,7 @@ namespace FEXCore::CodeSerialize {
          * @param Offset - The offset from the file
          * @param filename - The filename itself
          */
-        void AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const std::string &filename) {
+        void AsyncAddNamedRegionJob(uintptr_t Base, uintptr_t Size, uintptr_t Offset, const fextl::string &filename) {
           AsyncHandler.AsyncAddNamedRegionJob(Base, Size, Offset, filename);
         }
 
@@ -385,7 +386,7 @@ namespace FEXCore::CodeSerialize {
          *
          * @param Data - A fully filled out struct containing all the code serialization
          */
-        void AsyncAddSerializationJob(std::unique_ptr<AsyncJobHandler::SerializationJobData> Data) {
+        void AsyncAddSerializationJob(fextl::unique_ptr<AsyncJobHandler::SerializationJobData> Data) {
           AsyncHandler.AsyncAddSerializationJob(std::move(Data));
         }
       /**  @} */
@@ -443,7 +444,7 @@ namespace FEXCore::CodeSerialize {
       FEXCore::Context::ContextImpl *CTX;
 
       Event WorkAvailable{};
-      std::unique_ptr<FEXCore::Threads::Thread> WorkerThread;
+      fextl::unique_ptr<FEXCore::Threads::Thread> WorkerThread;
       std::atomic_bool WorkerThreadShuttingDown {false};
       AsyncJobHandler AsyncHandler;
       NamedRegionObjectHandler NamedRegionHandler;

External/FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -1,24 +1,24 @@
 #pragma once
 
 #include "Interface/Core/Frontend.h"
+#include "Interface/Core/X86Tables/X86Tables.h"
 #include "Interface/Context/Context.h"
 
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Core/Context.h>
 #include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/IR/IntrusiveIRList.h>
 #include <FEXCore/IR/IR.h>
 #include <FEXCore/IR/IREmitter.h>
 
 #include <FEXCore/Utils/LogManager.h>
+#include <FEXCore/fextl/map.h>
+#include <FEXCore/fextl/vector.h>
 
 #include <cstdint>
 #include <fmt/format.h>
-#include <map>
 #include <stddef.h>
 #include <utility>
-#include <vector>
 
 namespace FEXCore::IR {
 class Pass;
@@ -28,13 +28,6 @@ class OpDispatchBuilder final : public IREmitter {
 friend class FEXCore::IR::Pass;
 friend class FEXCore::IR::PassManager;
 
-enum class SelectionFlag {
-  Nothing,  // must rely on x86 flags
-  CMP,      // flags were set by a CMP between flagsOpDest/flagsOpDestSigned and flagsOpSrc/flagsOpSrcSigned with flagsOpSize size
-  AND,      // flags were set by an AND/TEST, flagsOpDest contains the resulting value of flagsOpSize size
-  FCMP,     // flags were set by a ucomis* / comis*
-};
-
 public:
   enum class FlagsGenerationType : uint8_t {
     TYPE_NONE,
@@ -49,6 +42,7 @@ public:
     TYPE_LSHLI,
     TYPE_LSHR,
     TYPE_LSHRI,
+    TYPE_LSHRDI,
     TYPE_ASHR,
     TYPE_ASHRI,
     TYPE_ROR,
@@ -68,25 +62,6 @@ public:
     TYPE_RDRAND,
   };
 
-  SelectionFlag flagsOp{};
-  uint8_t flagsOpSize{};
-  OrderedNode* flagsOpDest{};
-  OrderedNode* flagsOpSrc{};
-  OrderedNode* flagsOpDestSigned{};
-  OrderedNode* flagsOpSrcSigned{};
-
-  FEXCore::Context::ContextImpl *CTX{};
-
-  // Used during new op bringup
-  bool ShouldDump {false};
-
-  struct JumpTargetInfo {
-    OrderedNode* BlockEntry;
-    bool HaveEmitted;
-  };
-
-  std::map<uint64_t, JumpTargetInfo> JumpTargets;
-
   OrderedNode* GetNewJumpBlock(uint64_t RIP) {
     auto it = JumpTargets.find(RIP);
     LOGMAN_THROW_A_FMT(it != JumpTargets.end(), "Couldn't find block generated for 0x{:x}", RIP);
@@ -108,6 +83,10 @@ public:
 
   void StartNewBlock() {
     flagsOp = SelectionFlag::Nothing;
+
+    // If we loaded flags but didn't change them, invalidate the cached copy and move on.
+    // Changes get stored out by CalculateDeferredFlags.
+    CachedNZCV = nullptr;
   }
 
   bool FinishOp(uint64_t NextRIP, bool LastOp) {
@@ -149,6 +128,31 @@ public:
     return false;
   }
 
+  static bool CanHaveSideEffects(FEXCore::X86Tables::X86InstInfo const* TableInfo, FEXCore::X86Tables::DecodedOp Op) {
+    if (TableInfo && TableInfo->Flags & X86Tables::InstFlags::FLAGS_DEBUG_MEM_ACCESS) {
+      // If it is marked as having memory access then always say it has a side-effect.
+      // Not always true but better to be safe.
+      return true;
+    }
+
+    auto CanHaveSideEffects = false;
+
+    auto HasPotentialMemoryAccess = [](X86Tables::DecodedOperand const &Operand) -> bool {
+      if (Operand.IsNone()) {
+        return false;
+      }
+
+      // This isn't guaranteed that all of these types will access memory, but be safe.
+      return Operand.IsGPRDirect() || Operand.IsGPRIndirect() || Operand.IsRIPRelative() || Operand.IsSIB();
+    };
+
+    CanHaveSideEffects |= HasPotentialMemoryAccess(Op->Dest);
+    CanHaveSideEffects |= HasPotentialMemoryAccess(Op->Src[0]);
+    CanHaveSideEffects |= HasPotentialMemoryAccess(Op->Src[1]);
+    CanHaveSideEffects |= HasPotentialMemoryAccess(Op->Src[2]);
+    return CanHaveSideEffects;
+  }
+
   OpDispatchBuilder(FEXCore::Context::ContextImpl *ctx);
   OpDispatchBuilder(FEXCore::Utils::IntrusivePooledAllocator &Allocator);
 
@@ -157,7 +161,13 @@ public:
   bool HadDecodeFailure() const { return DecodeFailure; }
   bool NeedsBlockEnder() const { return NeedsBlockEnd; }
 
-  void BeginFunction(uint64_t RIP, std::vector<FEXCore::Frontend::Decoder::DecodedBlocks> const *Blocks);
+  void ResetHandledLock() { HandledLock = false; }
+  bool HasHandledLock() const { return HandledLock; }
+
+  void SetDumpIR(bool DumpIR) { ShouldDump = DumpIR; }
+  bool ShouldDumpIR() const { return ShouldDump; }
+
+  void BeginFunction(uint64_t RIP, fextl::vector<FEXCore::Frontend::Decoder::DecodedBlocks> const *Blocks);
   void Finalize();
 
   // Dispatch builder functions
@@ -181,7 +191,7 @@ public:
   void SecondaryALUOp(OpcodeArgs);
   template<uint32_t SrcIndex>
   void ADCOp(OpcodeArgs);
-  template<uint32_t SrcIndex>
+  template<uint32_t SrcIndex, bool SetFlags>
   void SBBOp(OpcodeArgs);
   void PUSHOp(OpcodeArgs);
   void PUSHREGOp(OpcodeArgs);
@@ -219,6 +229,7 @@ public:
   void MOVOffsetOp(OpcodeArgs);
   void CMOVOp(OpcodeArgs);
   void CPUIDOp(OpcodeArgs);
+  void XGetBVOp(OpcodeArgs);
   template<bool SHL1Bit>
   void SHLOp(OpcodeArgs);
   void SHLImmediateOp(OpcodeArgs);
@@ -355,7 +366,7 @@ public:
   void Vector_CVT_Int_To_Float(OpcodeArgs);
   template<size_t DstElementSize, size_t SrcElementSize>
   void Scalar_CVT_Float_To_Float(OpcodeArgs);
-  template<size_t DstElementSize, size_t SrcElementSize>
+  template<size_t DstElementSize, size_t SrcElementSize, bool IsAVX>
   void Vector_CVT_Float_To_Float(OpcodeArgs);
   template<size_t SrcElementSize, bool Narrow, bool HostRoundingMode>
   void Vector_CVT_Float_To_Int(OpcodeArgs);
@@ -415,12 +426,18 @@ public:
   template <size_t ElementSize, bool Scalar>
   void AVXVectorRound(OpcodeArgs);
 
+  template <size_t DstElementSize, size_t SrcElementSize>
+  void AVXScalar_CVT_Float_To_Float(OpcodeArgs);
+
   template <size_t SrcElementSize, bool Narrow, bool HostRoundingMode>
   void AVXVector_CVT_Float_To_Int(OpcodeArgs);
 
   template <size_t SrcElementSize, bool Widen>
   void AVXVector_CVT_Int_To_Float(OpcodeArgs);
 
+  template <size_t DstElementSize>
+  void AVXCVTGPR_To_FPR(OpcodeArgs);
+
   template <size_t ElementSize, bool Scalar>
   void AVXVFCMPOp(OpcodeArgs);
 
@@ -456,6 +473,9 @@ public:
   void VINSERTOp(OpcodeArgs);
   void VINSERTPSOp(OpcodeArgs);
 
+  template <size_t ElementSize, bool IsStore>
+  void VMASKMOVOp(OpcodeArgs);
+
   void VMOVAPS_VMOVAPD_Op(OpcodeArgs);
   void VMOVUPS_VMOVUPD_Op(OpcodeArgs);
 
@@ -471,6 +491,8 @@ public:
 
   void VMOVVectorNTOp(OpcodeArgs);
 
+  void VMPSADBWOp(OpcodeArgs);
+
   template <size_t ElementSize>
   void VPACKSSOp(OpcodeArgs);
 
@@ -479,6 +501,11 @@ public:
 
   void VPALIGNROp(OpcodeArgs);
 
+  void VPCMPESTRIOp(OpcodeArgs);
+  void VPCMPESTRMOp(OpcodeArgs);
+  void VPCMPISTRIOp(OpcodeArgs);
+  void VPCMPISTRMOp(OpcodeArgs);
+
   void VPERM2Op(OpcodeArgs);
   void VPERMDOp(OpcodeArgs);
   void VPERMQOp(OpcodeArgs);
@@ -496,8 +523,16 @@ public:
   void VPHSUBOp(OpcodeArgs);
   void VPHSUBSWOp(OpcodeArgs);
 
+  void VPINSRBOp(OpcodeArgs);
+  void VPINSRDQOp(OpcodeArgs);
+  void VPINSRWOp(OpcodeArgs);
+
+  void VPMADDUBSWOp(OpcodeArgs);
   void VPMADDWDOp(OpcodeArgs);
 
+  template <bool IsStore>
+  void VPMASKMOVOp(OpcodeArgs);
+
   void VPMULHRSWOp(OpcodeArgs);
 
   template <bool Signed>
@@ -506,6 +541,8 @@ public:
   template <size_t ElementSize, bool Signed>
   void VPMULLOp(OpcodeArgs);
 
+  void VPSADBWOp(OpcodeArgs);
+
   void VPSHUFBOp(OpcodeArgs);
 
   template <size_t ElementSize, bool Low>
@@ -516,6 +553,7 @@ public:
   void VPSLLDQOp(OpcodeArgs);
   template <size_t ElementSize>
   void VPSLLIOp(OpcodeArgs);
+  void VPSLLVOp(OpcodeArgs);
 
   template <size_t ElementSize>
   void VPSRAOp(OpcodeArgs);
@@ -524,6 +562,7 @@ public:
   void VPSRAIOp(OpcodeArgs);
 
   void VPSRAVDOp(OpcodeArgs);
+  void VPSRLVOp(OpcodeArgs);
 
   template <size_t ElementSize>
   void VPSRLDOp(OpcodeArgs);
@@ -541,6 +580,9 @@ public:
   template <size_t ElementSize>
   void VSHUFOp(OpcodeArgs);
 
+  template <size_t ElementSize>
+  void VTESTPOp(OpcodeArgs);
+
   void VZEROOp(OpcodeArgs);
 
   // X87 Ops
@@ -667,6 +709,8 @@ public:
   void FXSaveOp(OpcodeArgs);
   void FXRStoreOp(OpcodeArgs);
 
+  void XSaveOp(OpcodeArgs);
+
   void PAlignrOp(OpcodeArgs);
   template<size_t ElementSize>
   void UCOMISxOp(OpcodeArgs);
@@ -716,11 +760,9 @@ public:
   void PHADDS(OpcodeArgs);
   void PHSUBS(OpcodeArgs);
 
-  template<uint8_t FenceType>
-  void FenceOp(OpcodeArgs);
-
   void CLWB(OpcodeArgs);
   void CLFLUSHOPT(OpcodeArgs);
+  void LoadFenceOrXRSTOR(OpcodeArgs);
   void MemFenceOrXSAVEOPT(OpcodeArgs);
   void StoreFenceOrCLFlush(OpcodeArgs);
   void CLZeroOp(OpcodeArgs);
@@ -770,16 +812,54 @@ public:
   void InvalidOp(OpcodeArgs);
 
   void SetPackedRFLAG(bool Lower8, OrderedNode *Src);
-  OrderedNode *GetPackedRFLAG(bool Lower8);
+  OrderedNode *GetPackedRFLAG(uint32_t FlagsMask = ~0U);
 
   void SetMultiblock(bool _Multiblock) { Multiblock = _Multiblock; }
 
-  bool HandledLock = false;
 private:
+  enum class SelectionFlag {
+    Nothing,  // must rely on x86 flags
+    CMP,      // flags were set by a CMP between flagsOpDest/flagsOpDestSigned and flagsOpSrc/flagsOpSrcSigned with flagsOpSize size
+    AND,      // flags were set by an AND/TEST, flagsOpDest contains the resulting value of flagsOpSize size
+    FCMP,     // flags were set by a ucomis* / comis*
+  };
+
+  struct JumpTargetInfo {
+    OrderedNode* BlockEntry;
+    bool HaveEmitted;
+  };
+
+  FEXCore::Context::ContextImpl *CTX{};
+
+  SelectionFlag flagsOp{};
+  uint8_t flagsOpSize{};
+  OrderedNode* flagsOpDest{};
+  OrderedNode* flagsOpSrc{};
+  OrderedNode* flagsOpDestSigned{};
+  OrderedNode* flagsOpSrcSigned{};
+
+  static bool IsNZCV(unsigned BitOffset) {
+    switch (BitOffset) {
+      case FEXCore::X86State::RFLAG_CF_LOC:
+      case FEXCore::X86State::RFLAG_ZF_LOC:
+      case FEXCore::X86State::RFLAG_SF_LOC:
+      case FEXCore::X86State::RFLAG_OF_LOC:
+        return true;
+
+      default:
+        return false;
+    }
+  }
+
+  OrderedNode* CachedNZCV = {};
+  uint32_t PossiblySetNZCVBits = 0;
+
+  fextl::map<uint64_t, JumpTargetInfo> JumpTargets;
+  bool HandledLock{false};
   bool DecodeFailure{false};
   bool NeedsBlockEnd{false};
-  FEXCore::IR::IROp_IRHeader *Current_Header{};
-  OrderedNode *Current_HeaderNode{};
+  // Used during new op bringup
+  bool ShouldDump{false};
 
   void ALUOpImpl(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::IR::IROps AtomicFetchOp, bool RequiresMask);
 
@@ -795,9 +875,15 @@ private:
   template <size_t ElementSize>
   void AVXVectorVariableBlend(OpcodeArgs);
 
+  void AVXVariableShiftImpl(OpcodeArgs, IROps IROp);
+
   OrderedNode* AESKeyGenAssistImpl(OpcodeArgs);
   OrderedNode* AESIMCImpl(OpcodeArgs);
 
+  OrderedNode* CVTGPR_To_FPRImpl(OpcodeArgs, size_t DstElementSize,
+                                 const X86Tables::DecodedOperand& Src1Op,
+                                 const X86Tables::DecodedOperand& Src2Op);
+
   OrderedNode* DPPOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1,
                          const X86Tables::DecodedOperand& Src2,
                          const X86Tables::DecodedOperand& Imm, size_t ElementSize);
@@ -813,6 +899,10 @@ private:
                               const X86Tables::DecodedOperand& Src2,
                               const X86Tables::DecodedOperand& Imm);
 
+  OrderedNode* MPSADBWOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1Op,
+                             const X86Tables::DecodedOperand& Src2Op,
+                             const X86Tables::DecodedOperand& ImmOp);
+
   OrderedNode* PACKSSOpImpl(OpcodeArgs, size_t ElementSize,
                             OrderedNode *Src1, OrderedNode *Src2);
 
@@ -823,6 +913,8 @@ private:
                              const X86Tables::DecodedOperand& Src2,
                              const X86Tables::DecodedOperand& Imm);
 
+  void PCMPXSTRXOpImpl(OpcodeArgs, bool IsExplicit, bool IsMask);
+
   OrderedNode* PHADDSOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1,
                             const X86Tables::DecodedOperand& Src2);
 
@@ -834,9 +926,17 @@ private:
   OrderedNode* PHSUBSOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1Op,
                             const X86Tables::DecodedOperand& Src2Op);
 
+  OrderedNode* PINSROpImpl(OpcodeArgs, size_t ElementSize,
+                           const X86Tables::DecodedOperand& Src1Op,
+                           const X86Tables::DecodedOperand& Src2Op,
+                           const X86Tables::DecodedOperand& Imm);
+
   OrderedNode* PMADDWDOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1,
                              const X86Tables::DecodedOperand& Src2);
 
+  OrderedNode* PMADDUBSWOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1Op,
+                               const X86Tables::DecodedOperand& Src2Op);
+
   OrderedNode* PMULHRSWOpImpl(OpcodeArgs, OrderedNode *Src1, OrderedNode *Src2);
 
   OrderedNode* PMULHWOpImpl(OpcodeArgs, bool Signed,
@@ -845,6 +945,9 @@ private:
   OrderedNode* PMULLOpImpl(OpcodeArgs, size_t ElementSize, bool Signed,
                            OrderedNode *Src1, OrderedNode *Src2);
 
+  OrderedNode* PSADBWOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1Op,
+                            const X86Tables::DecodedOperand& Src2Op);
+
   OrderedNode* PSHUFBOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1,
                             const X86Tables::DecodedOperand& Src2);
 
@@ -868,11 +971,17 @@ private:
                           const X86Tables::DecodedOperand& Src2,
                           const X86Tables::DecodedOperand& Imm);
 
+  void VMASKMOVOpImpl(OpcodeArgs, size_t ElementSize, size_t DataSize, bool IsStore,
+                      const X86Tables::DecodedOperand& MaskOp,
+                      const X86Tables::DecodedOperand& DataOp);
+
   void VMOVScalarOpImpl(OpcodeArgs, size_t ElementSize);
 
   OrderedNode* VFCMPOpImpl(OpcodeArgs, size_t ElementSize, bool Scalar,
                            OrderedNode *Src1, OrderedNode *Src2, uint8_t CompType);
 
+  void VTESTOpImpl(OpcodeArgs, size_t ElementSize);
+
   void VectorALUOpImpl(OpcodeArgs, IROps IROp, size_t ElementSize);
   void VectorALUROpImpl(OpcodeArgs, IROps IROp, size_t ElementSize);
   void VectorScalarALUOpImpl(OpcodeArgs, IROps IROp, size_t ElementSize);
@@ -882,10 +991,33 @@ private:
   OrderedNode* VectorRoundImpl(OpcodeArgs, size_t ElementSize,
                                OrderedNode *Src, uint64_t Mode);
 
+  OrderedNode* Scalar_CVT_Float_To_FloatImpl(OpcodeArgs, size_t DstElementSize, size_t SrcElementSize,
+                                             const X86Tables::DecodedOperand& Src1Op,
+                                             const X86Tables::DecodedOperand& Src2Op);
+
+  void Vector_CVT_Float_To_FloatImpl(OpcodeArgs, size_t DstElementSize, size_t SrcElementSize, bool IsAVX);
+
   OrderedNode* Vector_CVT_Float_To_IntImpl(OpcodeArgs, size_t SrcElementSize, bool Narrow, bool HostRoundingMode);
 
   OrderedNode* Vector_CVT_Int_To_FloatImpl(OpcodeArgs, size_t SrcElementSize, bool Widen);
 
+  void XSaveOpImpl(OpcodeArgs);
+  void SaveX87State(OpcodeArgs, OrderedNode *MemBase);
+  void SaveSSEState(OrderedNode *MemBase);
+  void SaveMXCSRState(OrderedNode *MemBase);
+  void SaveAVXState(OrderedNode *MemBase);
+
+  void XRstorOpImpl(OpcodeArgs);
+  void RestoreX87State(OrderedNode *MemBase);
+  void RestoreSSEState(OrderedNode *MemBase);
+  void RestoreMXCSRState(OrderedNode *MXCSR);
+  void RestoreAVXState(OrderedNode *MemBase);
+  void DefaultX87State(OpcodeArgs);
+  void DefaultSSEState();
+  void DefaultAVXState();
+
+  OrderedNode *GetMXCSR();
+
   #undef OpcodeArgs
 
   OrderedNode *AppendSegmentOffset(OrderedNode *Value, uint32_t Flags, uint32_t DefaultPrefix = 0, bool Override = false);
@@ -929,19 +1061,123 @@ private:
   [[nodiscard]] uint32_t GetDstBitSize(X86Tables::DecodedOp Op) const;
   [[nodiscard]] uint32_t GetSrcBitSize(X86Tables::DecodedOp Op) const;
 
+  static inline constexpr unsigned IndexNZCV(unsigned BitOffset) {
+    switch (BitOffset) {
+      case FEXCore::X86State::RFLAG_OF_LOC: return 28;
+      case FEXCore::X86State::RFLAG_CF_LOC: return 29;
+      case FEXCore::X86State::RFLAG_ZF_LOC: return 30;
+      case FEXCore::X86State::RFLAG_SF_LOC: return 31;
+      default: FEX_UNREACHABLE;
+    }
+  }
+
+  OrderedNode *GetNZCV() {
+    if (!CachedNZCV) {
+      CachedNZCV = _LoadFlag(FEXCore::X86State::RFLAG_NZCV_LOC);
+
+      // We don't know what's set
+      PossiblySetNZCVBits = ~0;
+    }
+
+    return CachedNZCV;
+  }
+
+  void SetNZCV(OrderedNode *Value) {
+    CachedNZCV = Value;
+  }
+
+  void ZeroNZCV() {
+    CachedNZCV = _Constant(0);
+    PossiblySetNZCVBits = 0;
+  }
+
+  void ZeroCV() {
+    // Get old NZCV before we mess with PossiblySetNZCVBits
+    auto OldNZCV = GetNZCV();
+
+    // Mask out the NZ bits, clearing CV. Even if the code sets CV after, this can end up faster
+    // moves by allowing orlshl to be used instead of bfi.
+    PossiblySetNZCVBits = (1u << IndexNZCV(FEXCore::X86State::RFLAG_SF_LOC)) |
+                          (1u << IndexNZCV(FEXCore::X86State::RFLAG_ZF_LOC));
+    SetNZCV(_And(OldNZCV, _Constant(PossiblySetNZCVBits)));
+  }
+
+  void SetN_ZeroZCV(unsigned SrcSize, OrderedNode *Res) {
+    static_assert(IndexNZCV(FEXCore::X86State::RFLAG_SF_LOC) == 31);
+
+    unsigned NBit = 31;
+    unsigned SignBit = (SrcSize * 8) - 1;
+
+    OrderedNode *Shifted;
+
+    // Shift the sign bit into the N bit
+    if (SignBit > NBit)
+      Shifted = _Ashr(Res, _Constant(SignBit - NBit));
+    else if (SignBit < NBit)
+      Shifted = _Lshl(Res, _Constant(NBit - SignBit));
+    else
+      Shifted = Res;
+
+    // Mask off just the N bit, which now equals the sign bit
+    CachedNZCV = _And(Shifted, _Constant(1u << NBit));
+    PossiblySetNZCVBits = (1u << NBit);
+  }
+
+  void SetNZ_ZeroCV(unsigned SrcSize, OrderedNode *Res) {
+    // The TestNZ opcode does this operation natively for 32-bit or 64-bit.
+    // Otherwise we can implement the functionality ourselves with some bit math.
+    if (CTX->BackendFeatures.SupportsFlags && SrcSize >= 4) {
+      CachedNZCV = _TestNZ(SrcSize, Res);
+      PossiblySetNZCVBits = (1u << 31) | (1u << 30);
+    } else {
+      // N
+      SetN_ZeroZCV(SrcSize, Res);
+
+      // Z
+      auto Zero = _Constant(0);
+      auto One = _Constant(1);
+      auto SelectOp = _Select(FEXCore::IR::COND_EQ, Res, Zero, One, Zero);
+      SetRFLAG<FEXCore::X86State::RFLAG_ZF_LOC>(SelectOp);
+    }
+  }
+
+  OrderedNode *InsertNZCV(OrderedNode *NZCV, unsigned BitOffset, OrderedNode *Value) {
+    unsigned Bit = IndexNZCV(BitOffset);
+
+    uint32_t SetBits = PossiblySetNZCVBits;
+    PossiblySetNZCVBits |= (1u << Bit);
+
+    if (SetBits == 0)
+      return _Lshl(Value, _Constant(Bit));
+    else if (CTX->BackendFeatures.SupportsShiftedBitwise && (SetBits & (1u << Bit)) == 0)
+      return _Orlshl(NZCV, Value, Bit);
+    else
+      return _Bfi(4, 1, Bit, NZCV, Value);
+  }
+
   template<unsigned BitOffset>
   void SetRFLAG(OrderedNode *Value) {
-    flagsOp = SelectionFlag::Nothing;
-    _StoreFlag(_Bfe(1, 0, Value), BitOffset);
+    SetRFLAG(Value, BitOffset);
   }
 
   void SetRFLAG(OrderedNode *Value, unsigned BitOffset) {
     flagsOp = SelectionFlag::Nothing;
-    _StoreFlag(_Bfe(1, 0, Value), BitOffset);
+
+    if (IsNZCV(BitOffset))
+      SetNZCV(InsertNZCV(GetNZCV(), BitOffset, Value));
+    else
+      _StoreFlag(Value, BitOffset);
   }
 
   OrderedNode *GetRFLAG(unsigned BitOffset) {
-    return _LoadFlag(BitOffset);
+    if (IsNZCV(BitOffset)) {
+      if (!CachedNZCV || (PossiblySetNZCVBits & (1u << IndexNZCV(BitOffset))))
+        return _Bfe(1, 1, IndexNZCV(BitOffset), GetNZCV());
+      else
+        return _Constant(0);
+    } else {
+      return _LoadFlag(BitOffset);
+    }
   }
 
   OrderedNode *SelectCC(uint8_t OP, OrderedNode *TrueValue, OrderedNode *FalseValue);
@@ -1046,34 +1282,41 @@ private:
   /**
    * @name These functions are used by the deferred flag handling while it is calculating and storing flags in to RFLAGs.
    * @{ */
-  void CalculcateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
-  void CalculcateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
-  void CalculcateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
-  void CalculcateFlags_ADD(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
-  void CalculcateFlags_MUL(uint8_t SrcSize, OrderedNode *Res, OrderedNode *High);
-  void CalculcateFlags_UMUL(OrderedNode *High);
-  void CalculcateFlags_Logical(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void CalculcateFlags_ShiftLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void CalculcateFlags_ShiftLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void CalculcateFlags_ShiftRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void CalculcateFlags_ShiftRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void CalculcateFlags_SignShiftRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void CalculcateFlags_SignShiftRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void CalculcateFlags_RotateRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void CalculcateFlags_RotateLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void CalculcateFlags_RotateRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void CalculcateFlags_RotateLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
-  void CalculcateFlags_FCMP(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
-  void CalculcateFlags_BEXTR(OrderedNode *Src);
-  void CalculcateFlags_BLSI(uint8_t SrcSize, OrderedNode *Src);
-  void CalculcateFlags_BLSMSK(OrderedNode *Src);
-  void CalculcateFlags_BLSR(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src);
-  void CalculcateFlags_POPCOUNT(OrderedNode *Src);
-  void CalculcateFlags_BZHI(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src);
-  void CalculcateFlags_TZCNT(OrderedNode *Src);
-  void CalculcateFlags_LZCNT(uint8_t SrcSize, OrderedNode *Src);
-  void CalculcateFlags_BITSELECT(OrderedNode *Src);
-  void CalculcateFlags_RDRAND(OrderedNode *Src);
+  OrderedNode *LoadPF();
+  void CalculatePFUncheckedABI(OrderedNode *Res, OrderedNode *condition = nullptr);
+  void CalculatePF(OrderedNode *Res, OrderedNode *condition = nullptr);
+
+  void CalculateOF_Add(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculateFlags_ADC(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
+  void CalculateFlags_SBB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, OrderedNode *CF);
+  void CalculateFlags_SUB(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
+  void CalculateFlags_ADD(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2, bool UpdateCF = true);
+  void CalculateFlags_MUL(uint8_t SrcSize, OrderedNode *Res, OrderedNode *High);
+  void CalculateFlags_UMUL(OrderedNode *High);
+  void CalculateFlags_Logical(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculateFlags_ShiftLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculateFlags_ShiftLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculateFlags_ShiftRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculateFlags_ShiftRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculateFlags_ShiftRightDoubleImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculateFlags_ShiftRightImmediateCommon(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculateFlags_SignShiftRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculateFlags_SignShiftRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculateFlags_RotateRight(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculateFlags_RotateLeft(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculateFlags_RotateRightImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculateFlags_RotateLeftImmediate(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift);
+  void CalculateFlags_FCMP(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2);
+  void CalculateFlags_BEXTR(OrderedNode *Src);
+  void CalculateFlags_BLSI(uint8_t SrcSize, OrderedNode *Src);
+  void CalculateFlags_BLSMSK(OrderedNode *Src);
+  void CalculateFlags_BLSR(uint8_t SrcSize, OrderedNode *Res, OrderedNode *Src);
+  void CalculateFlags_POPCOUNT(OrderedNode *Src);
+  void CalculateFlags_BZHI(uint8_t SrcSize, OrderedNode *Result, OrderedNode *Src);
+  void CalculateFlags_TZCNT(OrderedNode *Src);
+  void CalculateFlags_LZCNT(uint8_t SrcSize, OrderedNode *Src);
+  void CalculateFlags_BITSELECT(OrderedNode *Src);
+  void CalculateFlags_RDRAND(OrderedNode *Src);
   /**  @} */
 
   /**
@@ -1286,6 +1529,23 @@ private:
     };
   }
 
+  void GenerateFlags_ShiftRightDoubleImmediate(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, uint64_t Shift) {
+    // No flags changed if shift is zero.
+    if (Shift == 0) return;
+
+    CurrentDeferredFlags = DeferredFlagData {
+      .Type = FlagsGenerationType::TYPE_LSHRDI,
+      .SrcSize = GetSrcSize(Op),
+      .Res = Res,
+      .Sources = {
+        .OneSrcImmediate = {
+          .Src1 = Src1,
+          .Imm = Shift,
+        },
+      },
+    };
+  }
+
   void GenerateFlags_RotateRight(FEXCore::X86Tables::DecodedOp Op, OrderedNode *Res, OrderedNode *Src1, OrderedNode *Src2) {
     // Doesn't set all the flags, needs to calculate.
     CalculateDeferredFlags();
@@ -1484,21 +1744,21 @@ private:
     return !Op->Dest.IsGPR();
   }
 
-  void CreateJumpBlocks(std::vector<FEXCore::Frontend::Decoder::DecodedBlocks> const *Blocks);
+  void CreateJumpBlocks(fextl::vector<FEXCore::Frontend::Decoder::DecodedBlocks> const *Blocks);
   bool BlockSetRIP {false};
 
   bool Multiblock{};
   uint64_t Entry;
 
   OrderedNode* _StoreMemAutoTSO(FEXCore::IR::RegisterClassType Class, uint8_t Size, OrderedNode *Addr, OrderedNode *Value, uint8_t Align = 1) {
-    if (CTX->IsTSOEnabled())
+    if (CTX->IsAtomicTSOEnabled())
       return _StoreMemTSO(Class, Size, Value, Addr, Invalid(), Align, MEM_OFFSET_SXTX, 1);
     else
       return _StoreMem(Class, Size, Value, Addr, Invalid(), Align, MEM_OFFSET_SXTX, 1);
   }
 
   OrderedNode* _LoadMemAutoTSO(FEXCore::IR::RegisterClassType Class, uint8_t Size, OrderedNode *ssa0, uint8_t Align = 1) {
-    if (CTX->IsTSOEnabled())
+    if (CTX->IsAtomicTSOEnabled())
       return _LoadMemTSO(Class, Size, ssa0, Invalid(), Align, MEM_OFFSET_SXTX, 1);
     else
       return _LoadMem(Class, Size, ssa0, Invalid(), Align, MEM_OFFSET_SXTX, 1);

External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp

@@ -5,7 +5,8 @@ desc: Handles x86/64 Crypto instructions to IR
 $end_info$
 */
 
-#include <FEXCore/Debug/X86Tables.h>
+#include "Interface/Core/X86Tables/X86Tables.h"
+
 #include <FEXCore/IR/IREmitter.h>
 #include <FEXCore/Utils/LogManager.h>
 #include "Interface/Core/OpcodeDispatcher.h"
@@ -77,7 +78,7 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
   using FnType = OrderedNode* (*)(OpDispatchBuilder&, OrderedNode*, OrderedNode*, OrderedNode*);
 
   const auto f0 = [](OpDispatchBuilder &Self, OrderedNode *B, OrderedNode *C, OrderedNode *D) -> OrderedNode* {
-    return Self._Xor(Self._And(B, C), Self._And(Self._Not(B), D));
+    return Self._Xor(Self._And(B, C), Self._Andn(D, B));
   };
   const auto f1 = [](OpDispatchBuilder &Self, OrderedNode *B, OrderedNode *C, OrderedNode *D) -> OrderedNode* {
     return Self._Xor(Self._Xor(B, C), D);
@@ -204,7 +205,7 @@ void OpDispatchBuilder::SHA256MSG2Op(OpcodeArgs) {
 
 void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) {
   const auto Ch = [this](OrderedNode *E, OrderedNode *F, OrderedNode *G) -> OrderedNode* {
-    return _Xor(_And(E, F), _And(_Not(E), G));
+    return _Xor(_And(E, F), _Andn(G, E));
   };
   const auto Major = [this](OrderedNode *A, OrderedNode *B, OrderedNode *C) -> OrderedNode* {
     return _Xor(_Xor(_And(A, B), _And(A, C)), _And(B, C));

External/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp

@@ -6,10 +6,10 @@ $end_info$
 */
 
 #include "Interface/Core/OpcodeDispatcher.h"
+#include "Interface/Core/X86Tables/X86Tables.h"
 
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/IR/IREmitter.h>
@@ -171,12 +171,14 @@ void OpDispatchBuilder::FILD(OpcodeArgs) {
   auto zero = _Constant(0);
 
   // Sign extend to 64bits
-  if (read_width != 8)
+  if (read_width != 8) {
     data = _Sext(read_width * 8, data);
+  }
 
   // Extract sign and make interger absolute
   auto sign = _Select(COND_SLT, data, zero, _Constant(0x8000), zero);
-  auto absolute =  _Select(COND_SLT, data, zero, _Sub(zero, data), data);
+
+  auto absolute = _Abs(data);
 
   // left justify the absolute interger
   auto shift = _Sub(_Constant(63), _FindMSB(absolute));
@@ -621,18 +623,19 @@ void OpDispatchBuilder::FXTRACT(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::FNINIT(OpcodeArgs) {
+  auto Zero = _Constant(0);
   // Init FCW to 0x037F
   auto NewFCW = _Constant(16, 0x037F);
   _F80LoadFCW(NewFCW);
   _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
 
   // Init FSW to 0
-  SetX87Top(_Constant(0));
+  SetX87Top(Zero);
 
-  SetRFLAG<FEXCore::X86State::X87FLAG_C0_LOC>(_Constant(0));
-  SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(_Constant(0));
-  SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(_Constant(0));
-  SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(_Constant(0));
+  SetRFLAG<FEXCore::X86State::X87FLAG_C0_LOC>(Zero);
+  SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(Zero);
+  SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(Zero);
+  SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(Zero);
 
   // Tags all get set to 0b11
   _StoreContext(2, GPRClass, _Constant(0xFFFF), offsetof(FEXCore::Core::CPUState, FTW));
@@ -1278,7 +1281,7 @@ void OpDispatchBuilder::X87FXAM(OpcodeArgs) {
   OrderedNode *Result = _VExtractToGPR(16, 8, a, 1);
 
   // Extract the sign bit
-  Result = _Lshr(Result, _Constant(15));
+  Result = _Bfe(1, 15, Result);
   SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(Result);
 
   // Claim this is a normal number
@@ -1354,28 +1357,24 @@ void OpDispatchBuilder::X87FCMOV(OpcodeArgs) {
   break;
   }
 
-  auto MaskConst = _Constant(FLAGMask);
+  auto RFLAG = GetPackedRFLAG(FLAGMask);
 
-  auto RFLAG = GetPackedRFLAG(false);
-
-  auto AndOp = _And(RFLAG, MaskConst);
   switch (Type) {
     case COMPARE_ZERO: {
       SrcCond = _Select(FEXCore::IR::COND_EQ,
-      AndOp, ZeroConst, OneConst, ZeroConst);
+      RFLAG, ZeroConst, OneConst, ZeroConst);
       break;
     }
     case COMPARE_NOTZERO: {
       SrcCond = _Select(FEXCore::IR::COND_EQ,
-      AndOp, ZeroConst, ZeroConst, OneConst);
+      RFLAG, ZeroConst, ZeroConst, OneConst);
       break;
     }
   }
 
   SrcCond = _Sbfe(1, 0, SrcCond);
 
-  OrderedNode *VecCond = _VCastFromGPR(16, 8, SrcCond);
-  VecCond = _VInsGPR(16, 8, 1, VecCond, SrcCond);
+  OrderedNode *VecCond = _VDupFromGPR(16, 8, SrcCond);
 
   auto top = GetX87Top();
   OrderedNode* arg;

External/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp

@@ -6,10 +6,10 @@ $end_info$
 */
 
 #include "Interface/Core/OpcodeDispatcher.h"
+#include "Interface/Core/X86Tables/X86Tables.h"
 
 #include <FEXCore/Core/CoreState.h>
 #include <FEXCore/Core/X86Enums.h>
-#include <FEXCore/Debug/X86Tables.h>
 #include <FEXCore/Utils/EnumUtils.h>
 #include <FEXCore/Utils/LogManager.h>
 #include <FEXCore/IR/IREmitter.h>
@@ -50,12 +50,12 @@ void OpDispatchBuilder::FNINITF64(OpcodeArgs) {
   _StoreContext(2, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW));
 
   // Init FSW to 0
-  SetX87Top(_Constant(0));
+  SetX87Top(Zero);
 
-  SetRFLAG<FEXCore::X86State::X87FLAG_C0_LOC>(_Constant(0));
-  SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(_Constant(0));
-  SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(_Constant(0));
-  SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(_Constant(0));
+  SetRFLAG<FEXCore::X86State::X87FLAG_C0_LOC>(Zero);
+  SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(Zero);
+  SetRFLAG<FEXCore::X86State::X87FLAG_C2_LOC>(Zero);
+  SetRFLAG<FEXCore::X86State::X87FLAG_C3_LOC>(Zero);
 
   // Tags all get set to 0b11
   _StoreContext(2, GPRClass, _Constant(0xFFFF), offsetof(FEXCore::Core::CPUState, FTW));
@@ -1119,7 +1119,7 @@ void OpDispatchBuilder::X87FXAMF64(OpcodeArgs) {
   OrderedNode *Result = _VExtractToGPR(8, 8, a, 0);
 
   // Extract the sign bit
-  Result = _Lshr(Result, _Constant(63));
+  Result = _Bfe(1, 63, Result);
   SetRFLAG<FEXCore::X86State::X87FLAG_C1_LOC>(Result);
 
   // Claim this is a normal number

External/FEXCore/Source/Interface/Core/SignalDelegator.cpp

@@ -6,93 +6,18 @@
 #include <signal.h>
 
 namespace FEXCore {
-  struct ThreadState {
-    FEXCore::Core::InternalThreadState *Thread{};
-  };
-
-  thread_local ThreadState ThreadData{};
-
-  static bool IsSynchronous(int Signal) {
-    switch (Signal) {
-    case SIGBUS:
-    case SIGFPE:
-    case SIGILL:
-    case SIGSEGV:
-    case SIGTRAP:
-      return true;
-    default: break;
-    };
-    return false;
-  }
-
-  /**
-   * @brief Masks signals from the signal mask
-   *
-   * @param how Argument to sigmask. SIG_{BLOCK, SETMASK, UNBLOCK}
-   * @param Signal Which signal to set or -1 to sweep through them all
-   */
-  static void MaskSignals(int how, int Signal = -1) {
-    // If we have a helper thread, we need to mask a significant amount of signals so the an errant thread doesn't receive a signal that it shouldn't
-    sigset_t SignalSet{};
-    sigemptyset(&SignalSet);
-
-    if (Signal == -1) {
-      for (int i = 0; i <= SignalDelegator::MAX_SIGNALS; ++i) {
-        // If it is a synchronous signal then don't ignore it
-        if (IsSynchronous(i)) {
-          continue;
-        }
-
-        // Add this signal to the ignore list
-        sigaddset(&SignalSet, i);
-      }
-    }
-    else {
-      sigaddset(&SignalSet, Signal);
-    }
-
-    // Be warned, a thread will inherit the signal mask if created from this thread
-    int Result = pthread_sigmask(how, &SignalSet, nullptr);
-    if (Result != 0) {
-      LogMan::Msg::EFmt("Couldn't register thread to mask signals");
-    }
-  }
-
-  void SignalDelegator::MaskThreadSignals() {
-    MaskSignals(SIG_BLOCK);
-  }
-
-  FEXCore::Core::InternalThreadState *SignalDelegator::GetTLSThread() {
-    return ThreadData.Thread;
-  }
-
-  void SignalDelegator::RegisterTLSState(FEXCore::Core::InternalThreadState *Thread) {
-    ThreadData.Thread = Thread;
-    RegisterFrontendTLSState(Thread);
-  }
-
-  void SignalDelegator::UninstallTLSState(FEXCore::Core::InternalThreadState *Thread) {
-    UninstallFrontendTLSState(Thread);
-    ThreadData.Thread = nullptr;
-  }
-
   void SignalDelegator::RegisterHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required) {
     SetHostSignalHandler(Signal, Func, Required);
     FrontendRegisterHostSignalHandler(Signal, Func, Required);
   }
 
-  void SignalDelegator::RegisterFrontendHostSignalHandler(int Signal, HostSignalDelegatorFunction Func, bool Required) {
-    SetFrontendHostSignalHandler(Signal, Func, Required);
-    FrontendRegisterFrontendHostSignalHandler(Signal, Func, Required);
-  }
-
   void SignalDelegator::HandleSignal(int Signal, void *Info, void *UContext) {
     // Let the host take first stab at handling the signal
     auto Thread = GetTLSThread();
     HostSignalHandler &Handler = HostHandlers[Signal];
 
     if (!Thread) {
-      LogMan::Msg::EFmt("[{}] Thread has received a signal and hasn't registered itself with the delegate! Programming error!", FHU::Syscalls::gettid());
+      LogMan::Msg::AFmt("[{}] Thread has received a signal and hasn't registered itself with the delegate! Programming error!", FHU::Syscalls::gettid());
     }
     else {
       for (auto &Handler : Handler.Handlers) {

External/FEXCore/Source/Interface/Core/X86DebugInfo.cpp

@@ -1,8 +1,9 @@
 #ifndef NDEBUG
-#include <FEXCore/Debug/X86Tables.h>
+
+#include "Interface/Core/X86Tables/X86Tables.h"
+
 #include <FEXCore/Utils/LogManager.h>
 #include <tuple>
-#include <vector>
 
 namespace FEXCore::X86Tables::X86InstDebugInfo {
 void InstallDebugInfo() {

External/FEXCore/Source/Interface/Core/X86HelperGen.cpp

@@ -6,6 +6,7 @@ $end_info$
 */
 
 #include "Interface/Core/X86HelperGen.h"
+#include "FEXCore/Utils/AllocatorHooks.h"
 
 #include <FEXCore/Config/Config.h>
 #include <FEXCore/Utils/Allocator.h>
@@ -13,13 +14,15 @@ $end_info$
 
 #include <cstdint>
 #include <cstring>
-#include <vector>
-#include <sys/mman.h>
 
 namespace FEXCore {
 constexpr size_t CODE_SIZE = 0x1000;
 
 X86GeneratedCode::X86GeneratedCode() {
+#ifdef _WIN32
+  // No need to allocate anything in this config.
+#else
+
   // Allocate a page for our emulated guest
   CodePtr = AllocateGuestCodeSpace(CODE_SIZE);
 
@@ -55,18 +58,22 @@ X86GeneratedCode::X86GeneratedCode() {
   memcpy(reinterpret_cast<void*>(rt_sigreturn_32), &rt_sigreturn_32_code.at(0), rt_sigreturn_32_code.size());
 
   mprotect(CodePtr, CODE_SIZE, PROT_READ);
+#endif
 }
 
 X86GeneratedCode::~X86GeneratedCode() {
-  FEXCore::Allocator::munmap(CodePtr, CODE_SIZE);
+#ifndef _WIN32
+  FEXCore::Allocator::VirtualFree(CodePtr, CODE_SIZE);
+#endif
 }
 
 void* X86GeneratedCode::AllocateGuestCodeSpace(size_t Size) {
+#ifndef _WIN32
   FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
 
   if (Is64BitMode()) {
     // 64bit mode can have its sigret handler anywhere
-    return FEXCore::Allocator::mmap(nullptr, Size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+    return FEXCore::Allocator::VirtualAlloc(Size);
   }
 
   // First 64bit page
@@ -95,6 +102,9 @@ void* X86GeneratedCode::AllocateGuestCodeSpace(size_t Size) {
   // Can't do anything about this
   // Here's hoping the application doesn't use signals
   return MAP_FAILED;
+#else
+  return nullptr;
+#endif
 }
 
 }

External/FEXCore/Source/Interface/Core/X86Tables.cpp

@@ -5,8 +5,9 @@ tags: frontend|x86-tables
 $end_info$
 */
 
+#include "Interface/Core/X86Tables/X86Tables.h"
+
 #include <FEXCore/Core/Context.h>
-#include <FEXCore/Debug/X86Tables.h>
 
 namespace FEXCore::X86Tables {
 

External/FEXCore/Source/Interface/Core/X86Tables/BaseTables.cpp

@@ -7,7 +7,6 @@ $end_info$
 #include "Interface/Core/X86Tables/X86Tables.h"
 
 #include <FEXCore/Core/Context.h>
-#include <FEXCore/Debug/X86Tables.h>
 
 #include <iterator>
 
@@ -147,10 +146,10 @@ void InitializeBaseTables(Context::OperatingMode Mode) {
     {0x9E, 1, X86InstInfo{"SAHF",   TYPE_INST, FLAGS_NONE,                              0, nullptr}},
     {0x9F, 1, X86InstInfo{"LAHF",   TYPE_INST, FLAGS_NONE,                              0, nullptr}},
 
-    {0xA4, 1, X86InstInfo{"MOVSB",  TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SUPPORTS_REP,                                            0, nullptr}},
-    {0xA5, 1, X86InstInfo{"MOVS",   TYPE_INST, FLAGS_SUPPORTS_REP,                                                            0, nullptr}},
-    {0xA6, 1, X86InstInfo{"CMPSB",  TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SUPPORTS_REP,                                            0, nullptr}},
-    {0xA7, 1, X86InstInfo{"CMPS",   TYPE_INST, FLAGS_SUPPORTS_REP,                                                            0, nullptr}},
+    {0xA4, 1, X86InstInfo{"MOVSB",  TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_DEBUG_MEM_ACCESS  | FLAGS_SUPPORTS_REP,                                            0, nullptr}},
+    {0xA5, 1, X86InstInfo{"MOVS",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS | FLAGS_SUPPORTS_REP,                                                            0, nullptr}},
+    {0xA6, 1, X86InstInfo{"CMPSB",  TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_DEBUG_MEM_ACCESS  | FLAGS_SUPPORTS_REP,                                            0, nullptr}},
+    {0xA7, 1, X86InstInfo{"CMPS",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS | FLAGS_SUPPORTS_REP,                                                            0, nullptr}},
 
     {0xA8, 1, X86InstInfo{"TEST",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX ,                                             1, nullptr}},
     {0xA9, 1, X86InstInfo{"TEST",   TYPE_INST, FLAGS_SF_DST_RAX | FLAGS_SRC_SEXT | FLAGS_DISPLACE_SIZE_DIV_2,                4, nullptr}},
@@ -170,10 +169,9 @@ void InitializeBaseTables(Context::OperatingMode Mode) {
     {0xC9, 1, X86InstInfo{"LEAVE",  TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_DEBUG_MEM_ACCESS ,                                                0, nullptr}},
     {0xCA, 2, X86InstInfo{"RETF",   TYPE_PRIV, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_BLOCK_END,                                                              0, nullptr}},
     {0xCC, 1, X86InstInfo{"INT3",   TYPE_INST, FLAGS_DEBUG,                                                                                      0, nullptr}},
-    {0xCD, 1, X86InstInfo{"INT",    TYPE_INST, FLAGS_DEBUG ,                                                                  1, nullptr}},
+    {0xCD, 1, X86InstInfo{"INT",    TYPE_INST, DEFAULT_SYSCALL_FLAGS,                                                                  1, nullptr}},
     {0xCF, 1, X86InstInfo{"IRET",   TYPE_INST, FLAGS_SETS_RIP | FLAGS_BLOCK_END,                                                                                    0, nullptr}},
 
-    {0xD6, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                                    0, nullptr}},
     {0xD7, 1, X86InstInfo{"XLAT",   TYPE_INST, FLAGS_DEBUG_MEM_ACCESS,                                                                           0, nullptr}},
 
     {0xE0, 1, X86InstInfo{"LOOPNE", TYPE_INST, GenFlagsSameSize(SIZE_64BITDEF) | FLAGS_SETS_RIP | FLAGS_SRC_SEXT | FLAGS_SF_SRC_RCX,                             1, nullptr}},
@@ -255,6 +253,9 @@ void InitializeBaseTables(Context::OperatingMode Mode) {
     {0xA3, 1, X86InstInfo{"MOV",    TYPE_INST, FLAGS_SF_SRC_RAX | FLAGS_MEM_OFFSET, 8, nullptr}},
     {0xCE, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                                    0, nullptr}},
     {0xD4, 2, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                                    0, nullptr}},
+    // `L1OM` Larrabee instructions used this as an escape byte.
+    // FEX will never support this.
+    {0xD6, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                                    0, nullptr}},
     {0xEA, 1, X86InstInfo{"[INV]",  TYPE_INVALID, FLAGS_NONE,                                                                                                      0, nullptr}},
   };
 
@@ -285,6 +286,7 @@ void InitializeBaseTables(Context::OperatingMode Mode) {
     {0xCE, 1, X86InstInfo{"INTO",   TYPE_INST, FLAGS_NONE,                                                        0, nullptr}},
     {0xD4, 1, X86InstInfo{"AAM",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX,                    1, nullptr}},
     {0xD5, 1, X86InstInfo{"AAD",    TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX,                    1, nullptr}},
+    {0xD6, 1, X86InstInfo{"SALC",   TYPE_INST, GenFlagsSameSize(SIZE_8BIT) | FLAGS_SF_DST_RAX | FLAGS_SF_SRC_RAX, 0, nullptr}},
     {0xEA, 1, X86InstInfo{"JMPF",   TYPE_INST, FLAGS_NONE,                                                        0, nullptr}},
   };